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Diffstat (limited to 'OSCAD/Examples/sedra_smith')
430 files changed, 0 insertions, 31845 deletions
diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/analysis b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/analysis deleted file mode 100644 index ea22c29..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 1e-00 3e-00 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.bak b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.bak deleted file mode 100644 index c0bd60e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.bak +++ /dev/null @@ -1,145 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 07 May 2013 12:28:25 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.lib deleted file mode 100644 index dfad98c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.lib +++ /dev/null @@ -1,145 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 02:05:36 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.bak b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.bak deleted file mode 100644 index 025172a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.bak +++ /dev/null @@ -1,193 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 07 May 2013 12:28:25 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_12.8-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "7 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 8250 2800 8400 2800 -Connection ~ 7000 2750 -Wire Wire Line - 8600 2250 8600 2000 -Wire Wire Line - 8600 2000 7500 2000 -Wire Wire Line - 6900 3650 7900 3650 -Wire Wire Line - 7750 3650 7750 3300 -Wire Wire Line - 7500 2000 7500 2200 -Connection ~ 7200 2750 -Wire Wire Line - 7200 2750 6900 2750 -Wire Wire Line - 7750 2800 7750 2750 -Connection ~ 7500 2750 -Wire Wire Line - 7750 2750 7500 2750 -Wire Wire Line - 7500 2600 7500 2850 -Wire Wire Line - 7200 2400 7200 3050 -Connection ~ 7750 2750 -Wire Wire Line - 7500 3250 7500 3450 -Connection ~ 7750 3650 -Wire Wire Line - 7500 3450 8600 3450 -Wire Wire Line - 8600 3450 8600 3150 -Wire Wire Line - 7750 3300 8400 3300 -$Comp -L IPLOT U1 -U 1 1 5188A5F5 -P 8000 2800 -F 0 "U1" H 7850 2900 50 0000 C CNN -F 1 "IPLOT" H 8150 2900 50 0000 C CNN - 1 8000 2800 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 5188A185 -P 7750 2450 -F 0 "U2" H 7600 2550 50 0000 C CNN -F 1 "VPLOT8_1" H 7900 2550 50 0000 C CNN - 2 7750 2450 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 51889CD8 -P 7000 2450 -F 0 "U2" H 6850 2550 50 0000 C CNN -F 1 "VPLOT8_1" H 7150 2550 50 0000 C CNN - 1 7000 2450 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 518897EF -P 7200 2750 -F 0 "#FLG01" H 7200 3020 30 0001 C CNN -F 1 "PWR_FLAG" H 7200 2980 30 0000 C CNN - 1 7200 2750 - 1 0 0 -1 -$EndComp -$Comp -L SINE v1 -U 1 1 51889574 -P 6900 3200 -F 0 "v1" H 6700 3300 60 0000 C CNN -F 1 "SINE" H 6700 3150 60 0000 C CNN -F 2 "R1" H 6600 3200 60 0000 C CNN - 1 6900 3200 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 51889502 -P 7750 3650 -F 0 "#FLG02" H 7750 3920 30 0001 C CNN -F 1 "PWR_FLAG" H 7750 3880 30 0000 C CNN - 1 7750 3650 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 518894F5 -P 7900 3650 -F 0 "#PWR03" H 7900 3650 30 0001 C CNN -F 1 "GND" H 7900 3580 30 0001 C CNN - 1 7900 3650 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 518894AB -P 8600 2700 -F 0 "v2" H 8400 2800 60 0000 C CNN -F 1 "23" H 8400 2650 60 0000 C CNN -F 2 "R1" H 8300 2700 60 0000 C CNN - 1 8600 2700 - -1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5188943C -P 8400 3050 -F 0 "R1" V 8480 3050 50 0000 C CNN -F 1 "8" V 8400 3050 50 0000 C CNN - 1 8400 3050 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q2 -U 1 1 518893FC -P 7400 3050 -F 0 "Q2" H 7400 2900 60 0000 R CNN -F 1 "PNP" H 7400 3200 60 0000 R CNN - 1 7400 3050 - 1 0 0 1 -$EndComp -$Comp -L NPN Q1 -U 1 1 518893F7 -P 7400 2400 -F 0 "Q1" H 7400 2250 50 0000 R CNN -F 1 "NPN" H 7400 2550 50 0000 R CNN - 1 7400 2400 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir deleted file mode 100644 index 93fe4d6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir +++ /dev/null @@ -1,16 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 02:05:33 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v3 0 5 23 -U1 6 4 IPLOT -U2 2 6 VPLOT8_1 -v1 2 0 SINE -v2 1 0 23 -R1 4 0 8 -Q2 6 2 5 PNP -Q1 6 2 1 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.ckt deleted file mode 100644 index 903850c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.ckt +++ /dev/null @@ -1,15 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 02:05:33 pm ist - -v3 0 5 23 -V_u1 6 4 0 -* Plotting option vplot8_1 -v1 2 0 sine( 17.9 1000 ) -v2 1 0 23 -r1 4 0 8 -q2 5 2 6 pnp -q1 1 2 6 npn - -.tran 1e-00 3e-00 0e-00 -.plot i(V_u1) -.plot v(2) v(6) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.out deleted file mode 100644 index 061ce43..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 02:05:33 pm ist - -v3 0 5 23 -V_u1 6 4 0 -* Plotting option vplot8_1 -v1 2 0 sine( 17.9 1000 ) -v2 1 0 23 -r1 4 0 8 -q2 5 2 6 pnp -q1 1 2 6 npn - -.tran 1e-00 3e-00 0e-00 - -* Control Statements -.control -run -plot i(V_u1) -plot v(2) v(6) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.pro b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.pro deleted file mode 100644 index c84bea9..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 07 May 2013 11:10:57 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.proj b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.proj deleted file mode 100644 index fdaaf23..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_12.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.sch b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.sch deleted file mode 100644 index 15b79e2..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.sch +++ /dev/null @@ -1,221 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 02:05:36 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_12.8-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L GND #PWR01 -U 1 1 5190A5AD -P 9250 2600 -F 0 "#PWR01" H 9250 2600 30 0001 C CNN -F 1 "GND" H 9250 2530 30 0001 C CNN - 1 9250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 8950 2600 -Wire Wire Line - 8950 2600 9250 2600 -Wire Wire Line - 8950 3600 8600 3600 -Wire Wire Line - 8600 3600 8600 3450 -Wire Wire Line - 8250 2800 8400 2800 -Connection ~ 7000 2750 -Wire Wire Line - 7500 2000 8600 2000 -Wire Wire Line - 6900 3650 7900 3650 -Wire Wire Line - 7750 3650 7750 3300 -Wire Wire Line - 7500 2000 7500 2200 -Connection ~ 7200 2750 -Wire Wire Line - 7200 2750 6900 2750 -Wire Wire Line - 7750 2800 7750 2750 -Connection ~ 7500 2750 -Wire Wire Line - 7750 2750 7500 2750 -Wire Wire Line - 7500 2600 7500 2850 -Wire Wire Line - 7200 2400 7200 3050 -Connection ~ 7750 2750 -Wire Wire Line - 7500 3250 7500 3450 -Connection ~ 7750 3650 -Wire Wire Line - 7500 3450 8600 3450 -Wire Wire Line - 7750 3300 8400 3300 -Wire Wire Line - 8600 2000 8600 1600 -Wire Wire Line - 8600 1600 8950 1600 -Wire Wire Line - 8950 2500 8950 2700 -$Comp -L DC v3 -U 1 1 5190A59B -P 8950 3150 -F 0 "v3" H 8750 3250 60 0000 C CNN -F 1 "23" H 8750 3100 60 0000 C CNN -F 2 "R1" H 8650 3150 60 0000 C CNN - 1 8950 3150 - -1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 5188A5F5 -P 8000 2800 -F 0 "U1" H 7850 2900 50 0000 C CNN -F 1 "IPLOT" H 8150 2900 50 0000 C CNN - 1 8000 2800 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 5188A185 -P 7750 2450 -F 0 "U2" H 7600 2550 50 0000 C CNN -F 1 "VPLOT8_1" H 7900 2550 50 0000 C CNN - 2 7750 2450 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 51889CD8 -P 7000 2450 -F 0 "U2" H 6850 2550 50 0000 C CNN -F 1 "VPLOT8_1" H 7150 2550 50 0000 C CNN - 1 7000 2450 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 518897EF -P 7200 2750 -F 0 "#FLG02" H 7200 3020 30 0001 C CNN -F 1 "PWR_FLAG" H 7200 2980 30 0000 C CNN - 1 7200 2750 - 1 0 0 -1 -$EndComp -$Comp -L SINE v1 -U 1 1 51889574 -P 6900 3200 -F 0 "v1" H 6700 3300 60 0000 C CNN -F 1 "SINE" H 6700 3150 60 0000 C CNN -F 2 "R1" H 6600 3200 60 0000 C CNN - 1 6900 3200 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG03 -U 1 1 51889502 -P 7750 3650 -F 0 "#FLG03" H 7750 3920 30 0001 C CNN -F 1 "PWR_FLAG" H 7750 3880 30 0000 C CNN - 1 7750 3650 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR04 -U 1 1 518894F5 -P 7900 3650 -F 0 "#PWR04" H 7900 3650 30 0001 C CNN -F 1 "GND" H 7900 3580 30 0001 C CNN - 1 7900 3650 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 518894AB -P 8950 2050 -F 0 "v2" H 8750 2150 60 0000 C CNN -F 1 "23" H 8750 2000 60 0000 C CNN -F 2 "R1" H 8650 2050 60 0000 C CNN - 1 8950 2050 - -1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5188943C -P 8400 3050 -F 0 "R1" V 8480 3050 50 0000 C CNN -F 1 "8" V 8400 3050 50 0000 C CNN - 1 8400 3050 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q2 -U 1 1 518893FC -P 7400 3050 -F 0 "Q2" H 7400 2900 60 0000 R CNN -F 1 "PNP" H 7400 3200 60 0000 R CNN - 1 7400 3050 - 1 0 0 1 -$EndComp -$Comp -L NPN Q1 -U 1 1 518893F7 -P 7400 2400 -F 0 "Q1" H 7400 2250 50 0000 R CNN -F 1 "NPN" H 7400 2550 50 0000 R CNN - 1 7400 2400 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib deleted file mode 100644 index 89d421d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib +++ /dev/null @@ -1,2 +0,0 @@ -.model 1n4007 D( IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1E-11 -+VJ=0.7 M=0.5 FC=0.5 TT=1E-07 KF=0 AF=1 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis deleted file mode 100644 index 09ae223..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 1e-01 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak deleted file mode 100644 index a47b560..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak +++ /dev/null @@ -1,108 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 11:21:47 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib deleted file mode 100644 index 6d1cabe..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib +++ /dev/null @@ -1,108 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 11:52:16 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak deleted file mode 100644 index 3314c60..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak +++ /dev/null @@ -1,133 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 14 May 2013 11:21:47 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:example_2.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "14 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5750 5050 -Wire Wire Line - 5550 3150 5650 3150 -Wire Wire Line - 5050 4550 5050 5050 -Wire Wire Line - 6500 4900 6500 5050 -Wire Wire Line - 6050 3150 6500 3150 -Wire Wire Line - 5750 5050 5750 5800 -Connection ~ 5750 5550 -Connection ~ 6500 3150 -Wire Wire Line - 6500 3150 6500 3350 -Wire Wire Line - 6500 3850 6500 4000 -Wire Wire Line - 5050 3150 5050 3650 -Wire Wire Line - 6500 5050 5050 5050 -$Comp -L DC v2 -U 1 1 516BA020 -P 6500 4450 -F 0 "v2" H 6300 4550 60 0000 C CNN -F 1 "DC" H 6300 4400 60 0000 C CNN -F 2 "R1" H 6200 4450 60 0000 C CNN - 1 6500 4450 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5167CC3A -P 5750 5550 -F 0 "#FLG01" H 5750 5645 30 0001 C CNN -F 1 "PWR_FLAG" H 5750 5730 30 0000 C CNN - 1 5750 5550 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5167CC15 -P 5750 5800 -F 0 "#PWR02" H 5750 5800 30 0001 C CNN -F 1 "GND" H 5750 5730 30 0001 C CNN - 1 5750 5800 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 5166A34A -P 6500 3600 -F 0 "U1" H 6350 3700 50 0000 C CNN -F 1 "IPLOT" H 6650 3700 50 0000 C CNN - 1 6500 3600 - 0 1 1 0 -$EndComp -$Comp -L DIODE D1 -U 1 1 5166A210 -P 5850 3150 -F 0 "D1" H 5850 3250 40 0000 C CNN -F 1 "DIODE" H 5850 3050 40 0000 C CNN - 1 5850 3150 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166A1EB -P 5300 3150 -F 0 "R1" V 5380 3150 50 0000 C CNN -F 1 "100" V 5300 3150 50 0000 C CNN - 1 5300 3150 - 0 -1 -1 0 -$EndComp -$Comp -L SINE v1 -U 1 1 5166A1AC -P 5050 4100 -F 0 "v1" H 4850 4200 60 0000 C CNN -F 1 "SINE" H 4850 4050 60 0000 C CNN -F 2 "R1" H 4750 4100 60 0000 C CNN - 1 5050 4100 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd deleted file mode 100644 index bf4bd89..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd +++ /dev/null @@ -1,172 +0,0 @@ -PCBNEW-BOARD Version 1 date Friday 12 April 2013 02:43:29 PM IST - -# Created by Pcbnew(2012-apr-16-27)-stable - -$GENERAL -encoding utf-8 -LayerCount 2 -Ly 1FFF8001 -EnabledLayers 1FFF8001 -Links 0 -NoConn 0 -Di 40424 25540 76751 39450 -Ndraw 0 -Ntrack 0 -Nzone 0 -BoardThickness 630 -Nmodule 2 -Nnets 4 -$EndGENERAL - -$SHEETDESCR -Sheet A4 11700 8267 -Title "" -Date "12 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndSHEETDESCR - -$SETUP -InternalUnit 0.000100 INCH -Layers 2 -Layer[0] Back signal -Layer[15] Front signal -TrackWidth 80 -TrackClearence 100 -ZoneClearence 200 -TrackMinWidth 80 -DrawSegmWidth 150 -EdgeSegmWidth 150 -ViaSize 350 -ViaDrill 250 -ViaMinSize 350 -ViaMinDrill 200 -MicroViaSize 200 -MicroViaDrill 50 -MicroViasAllowed 0 -MicroViaMinSize 200 -MicroViaMinDrill 50 -TextPcbWidth 120 -TextPcbSize 600 800 -EdgeModWidth 150 -TextModSize 600 600 -TextModWidth 120 -PadSize 600 600 -PadDrill 320 -Pad2MaskClearance 100 -AuxiliaryAxisOrg 0 0 -PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) -$EndSETUP - -$EQUIPOT -Na 0 "" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 1 "GND" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 2 "N-000018" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 3 "N-000019" -St ~ -$EndEQUIPOT -$NCLASS -Name "Default" -Desc "This is the default net class." -Clearance 100 -TrackWidth 80 -ViaDia 350 -ViaDrill 250 -uViaDia 200 -uViaDrill 50 -AddNet "" -AddNet "GND" -AddNet "N-000018" -AddNet "N-000019" -$EndNCLASS -$MODULE 1pin -Po 41500 38000 0 15 00200000 5167CFD9 ~~ -Li 1pin -Cd module 1 pin (ou trou mecanique de percage) -Kw DEV -Sc 5167CFD9 -AR 1pin -Op 0 0 0 -T0 0 -1200 400 400 0 100 N V 21 N "1PIN" -T1 0 1100 400 400 0 100 N I 21 N "P***" -DC 0 0 0 -900 150 21 -$PAD -Sh "1" C 1600 1600 0 0 0 -Dr 1200 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 0 0 -$EndPAD -$EndMODULE 1pin -$MODULE 3PIN_6mm -Po 68000 29000 0 15 00200000 5167CFEC ~~ -Li 3PIN_6mm -Cd module 2 pin (trou 6 mm) -Kw DEV -Sc 5167CFEC -AR -Op 0 0 0 -T0 4000 -3000 600 600 0 120 N V 21 N "K1" -T1 -3000 -3000 600 600 0 120 N V 21 N "CONN_3" -DS -8500 -2500 8500 -2500 150 21 -DS 8500 -2500 8500 2500 150 21 -DS 8500 2500 -8500 2500 150 21 -DS -8500 2500 -8500 -2500 150 21 -$PAD -Sh "1" C 4000 4000 0 0 0 -Dr 2400 0 0 -At STD N 00E0FFFF -Ne 2 "N-000018" -Po -5900 0 -$EndPAD -$PAD -Sh "3" C 4000 4000 0 0 0 -Dr 2400 0 0 -At STD N 00E0FFFF -Ne 3 "N-000019" -Po 5900 0 -$EndPAD -$PAD -Sh "2" C 4000 4000 0 0 0 -Dr 2400 0 0 -At STD N 00E0FFFF -Ne 1 "GND" -Po 0 0 -$EndPAD -$SHAPE3D -Na "device/douille_4mm(black).wrl" -Sc 1.800000 1.800000 1.800000 -Of 0.000000 0.000000 0.000000 -Ro 0.000000 0.000000 0.000000 -$EndSHAPE3D -$SHAPE3D -Na "device/douille_4mm(red).wrl" -Sc 1.800000 1.800000 1.800000 -Of -0.590000 0.000000 0.000000 -Ro 0.000000 0.000000 0.000000 -$EndSHAPE3D -$SHAPE3D -Na "device/douille_4mm(green).wrl" -Sc 1.800000 1.800000 1.800000 -Of 0.590000 0.000000 0.000000 -Ro 0.000000 0.000000 0.000000 -$EndSHAPE3D -$EndMODULE 3PIN_6mm -$TRACK -$EndTRACK -$ZONE -$EndZONE -$EndBOARD diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir deleted file mode 100644 index 16861f7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir +++ /dev/null @@ -1,13 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 12:08:03 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v2 1 0 DC -U1 3 1 IPLOT -D1 5 3 DIODE -R1 2 5 100 -v1 2 0 SINE - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt deleted file mode 100644 index 6d02b34..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt +++ /dev/null @@ -1,11 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 12:08:03 pm ist - -v2 1 0 dc 12 -V_u1 3 1 0 -d1 5 3 diode -r1 2 5 100 -v1 2 0 sine(0 24 50 0 0) - -.tran 10e-03 1e-01 0e-00 -.plot i(V_u1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out deleted file mode 100644 index 52cc067..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out +++ /dev/null @@ -1,16 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 12:08:03 pm ist - -v2 1 0 dc 12 -V_u1 3 1 0 -d1 5 3 diode -r1 2 5 100 -v1 2 0 sine(0 24 50 0 0) - -.tran 10e-03 1e-01 0e-00 - -* Control Statements -.control -run -plot i(V_u1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp deleted file mode 100644 index 779ff51..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp +++ /dev/null @@ -1,38 +0,0 @@ -Cmp-Mod V01 Created by CvPcb (2012-apr-16-27)-stable date = Friday 12 April 2013 02:41:23 PM IST - -BeginCmp -TimeStamp = /5166A210; -Reference = D1; -ValeurCmp = DIODE; -IdModule = ; -EndCmp - -BeginCmp -TimeStamp = /5166A1EB; -Reference = R1; -ValeurCmp = 100; -IdModule = ; -EndCmp - -BeginCmp -TimeStamp = /5166A34A; -Reference = U1; -ValeurCmp = IPLOT; -IdModule = ; -EndCmp - -BeginCmp -TimeStamp = /5166A1AC; -Reference = v1; -ValeurCmp = SINE; -IdModule = R1; -EndCmp - -BeginCmp -TimeStamp = /5166A26E; -Reference = v2; -ValeurCmp = 12V; -IdModule = R1; -EndCmp - -EndListe diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net deleted file mode 100644 index eeea8db..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net +++ /dev/null @@ -1,44 +0,0 @@ -# EESchema Netlist Version 1.1 created Friday 12 April 2013 02:41:23 PM IST -( - ( /5166A210 $noname$ D1 DIODE - ( 1 N-000002 ) - ( 2 N-000004 ) - ) - ( /5166A1EB $noname$ R1 100 - ( 1 N-000001 ) - ( 2 N-000002 ) - ) - ( /5166A34A $noname$ U1 IPLOT - ( 1 N-000004 ) - ( 2 N-000003 ) - ) - ( /5166A1AC R1 v1 SINE - ( 1 N-000001 ) - ( 2 GND ) - ) - ( /5166A26E R1 v2 12V - ( 1 N-000003 ) - ( 2 GND ) - ) -) -* -{ Allowed footprints by component: -$component D1 - D? - S* -$endlist -$component R1 - R? - SM0603 - SM0805 - R?-* - SM1206 -$endlist -$component v1 - 1_pin -$endlist -$component v2 - 1_pin -$endlist -$endfootprintlist -} diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro deleted file mode 100644 index f5826c2..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Thursday 11 April 2013 05:12:20 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj deleted file mode 100644 index 3cb5076..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_2.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch deleted file mode 100644 index dfa5e1d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch +++ /dev/null @@ -1,133 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 14 May 2013 11:52:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:example_2.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "14 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5750 5050 -Wire Wire Line - 5550 3150 5650 3150 -Wire Wire Line - 5050 4550 5050 5050 -Wire Wire Line - 6500 4900 6500 5050 -Wire Wire Line - 6050 3150 6500 3150 -Wire Wire Line - 5750 5050 5750 5800 -Connection ~ 5750 5550 -Connection ~ 6500 3150 -Wire Wire Line - 6500 3150 6500 3350 -Wire Wire Line - 6500 3850 6500 4000 -Wire Wire Line - 5050 3150 5050 3650 -Wire Wire Line - 6500 5050 5050 5050 -$Comp -L DC v2 -U 1 1 516BA020 -P 6500 4450 -F 0 "v2" H 6300 4550 60 0000 C CNN -F 1 "DC" H 6300 4400 60 0000 C CNN -F 2 "R1" H 6200 4450 60 0000 C CNN - 1 6500 4450 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5167CC3A -P 5750 5550 -F 0 "#FLG01" H 5750 5645 30 0001 C CNN -F 1 "PWR_FLAG" H 5750 5730 30 0000 C CNN - 1 5750 5550 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5167CC15 -P 5750 5800 -F 0 "#PWR02" H 5750 5800 30 0001 C CNN -F 1 "GND" H 5750 5730 30 0001 C CNN - 1 5750 5800 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 5166A34A -P 6500 3600 -F 0 "U1" H 6350 3700 50 0000 C CNN -F 1 "IPLOT" H 6650 3700 50 0000 C CNN - 1 6500 3600 - 0 1 1 0 -$EndComp -$Comp -L DIODE D1 -U 1 1 5166A210 -P 5850 3150 -F 0 "D1" H 5850 3250 40 0000 C CNN -F 1 "DIODE" H 5850 3050 40 0000 C CNN - 1 5850 3150 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166A1EB -P 5300 3150 -F 0 "R1" V 5380 3150 50 0000 C CNN -F 1 "100" V 5300 3150 50 0000 C CNN - 1 5300 3150 - 0 -1 -1 0 -$EndComp -$Comp -L SINE v1 -U 1 1 5166A1AC -P 5050 4100 -F 0 "v1" H 4850 4200 60 0000 C CNN -F 1 "SINE" H 4850 4050 60 0000 C CNN -F 2 "R1" H 4750 4100 60 0000 C CNN - 1 5050 4100 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis deleted file mode 100644 index 403e10c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v2 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak deleted file mode 100644 index fc013c5..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak +++ /dev/null @@ -1,90 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Sunday 14 April 2013 04:43:15 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 95 30 H I C CNN -F1 "PWR_FLAG" 0 180 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* - SM1206 -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib deleted file mode 100644 index aea3592..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib +++ /dev/null @@ -1,108 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 12:54:28 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak deleted file mode 100644 index 6ce76aa..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak +++ /dev/null @@ -1,162 +0,0 @@ -EESchema Schematic File Version 2 date Sunday 14 April 2013 04:43:15 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_2.2-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "14 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PWR_FLAG #FLG01 -U 1 1 516A8F23 -P 4150 6650 -F 0 "#FLG01" H 4150 6745 30 0001 C CNN -F 1 "PWR_FLAG" H 4150 6830 30 0000 C CNN - 1 4150 6650 - 0 1 1 0 -$EndComp -Connection ~ 4150 6650 -Connection ~ 6350 4000 -Wire Wire Line - 6350 3350 6350 3150 -Connection ~ 4150 5200 -Wire Wire Line - 6350 5200 4150 5200 -Wire Wire Line - 4800 3150 4150 3150 -Wire Wire Line - 4150 5350 4150 4650 -Wire Wire Line - 6350 3150 5700 3150 -Wire Wire Line - 6350 4650 6350 4800 -Wire Wire Line - 4150 5750 4150 6000 -Wire Wire Line - 6350 3850 6350 4150 -Wire Wire Line - 4150 3150 4150 4150 -Wire Wire Line - 4150 6850 4150 6500 -$Comp -L GND #PWR02 -U 1 1 5167DAB9 -P 4150 6850 -F 0 "#PWR02" H 4150 6850 30 0001 C CNN -F 1 "GND" H 4150 6780 30 0001 C CNN - 1 4150 6850 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 5167DA8B -P 4150 6250 -F 0 "U1" H 4000 6350 50 0000 C CNN -F 1 "IPLOT" H 4300 6350 50 0000 C CNN - 1 4150 6250 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 5167D9D2 -P 6350 3600 -F 0 "U2" H 6200 3700 50 0000 C CNN -F 1 "IPLOT" H 6500 3700 50 0000 C CNN - 1 6350 3600 - 0 1 1 0 -$EndComp -$Comp -L DIODE D2 -U 1 1 5167D956 -P 6350 5000 -F 0 "D2" H 6350 5100 40 0000 C CNN -F 1 "DIODE" H 6350 4900 40 0000 C CNN - 1 6350 5000 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 5167D912 -P 5250 3150 -F 0 "v1" H 5050 3250 60 0000 C CNN -F 1 "10V" H 5050 3100 60 0000 C CNN -F 2 "R1" H 4950 3150 60 0000 C CNN - 1 5250 3150 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5167D8E5 -P 6350 4400 -F 0 "R2" V 6430 4400 50 0000 C CNN -F 1 "10k" V 6350 4400 50 0000 C CNN - 1 6350 4400 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5167D8B8 -P 4150 4400 -F 0 "R1" V 4230 4400 50 0000 C CNN -F 1 "5k" V 4150 4400 50 0000 C CNN - 1 4150 4400 - 1 0 0 -1 -$EndComp -$Comp -L DIODE D1 -U 1 1 5167D869 -P 4150 5550 -F 0 "D1" H 4150 5650 40 0000 C CNN -F 1 "DIODE" H 4150 5450 40 0000 C CNN - 1 4150 5550 - 0 -1 -1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir deleted file mode 100644 index a8ccf76..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir +++ /dev/null @@ -1,17 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 12:54:07 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U3 6 VPLOT8_1 -v2 1 0 10V -v1 0 4 10V -U1 5 0 IPLOT -U2 1 7 IPLOT -D2 6 3 DIODE -R2 7 6 5k -R1 4 3 10k -D1 5 3 DIODE - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt deleted file mode 100644 index ec3f080..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:54:07 pm ist - -* Plotting option vplot8_1 -v2 1 0 10v -v1 0 4 10v -V_u1 5 0 0 -V_u2 1 7 0 -d2 6 3 diode -r2 7 6 5k -r1 4 3 10k -d1 5 3 diode - -.dc v2 0e-00 10e-00 1e-00 -.plot v(6) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out deleted file mode 100644 index b89d0e8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:54:07 pm ist - -* Plotting option vplot8_1 -v2 1 0 10v -v1 0 4 10v -V_u1 5 0 0 -V_u2 1 7 0 -d2 6 3 diode -r2 7 6 5k -r1 4 3 10k -d1 5 3 diode - -.dc v2 0e-00 10e-00 1e-00 - -* Control Statements -.control -run -plot v(6) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro deleted file mode 100644 index 49fe832..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro +++ /dev/null @@ -1,84 +0,0 @@ -update=Monday 13 May 2013 12:52:59 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice -LibName41=/home/holy/OSCAD/library/analogSpice -LibName42=/home/holy/OSCAD/library/analogXSpice -LibName43=/home/holy/OSCAD/library/convergenceAidSpice -LibName44=/home/holy/OSCAD/library/converterSpice -LibName45=/home/holy/OSCAD/library/digitalSpice -LibName46=/home/holy/OSCAD/library/digitalXSpice -LibName47=/home/holy/OSCAD/library/linearSpice -LibName48=/home/holy/OSCAD/library/measurementSpice -LibName49=/home/holy/OSCAD/library/portSpice -LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj deleted file mode 100644 index 049873b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_2.2.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch deleted file mode 100644 index de929d7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch +++ /dev/null @@ -1,195 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 12:54:28 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_2.2-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 6650 4750 -$Comp -L VPLOT8_1 U3 -U 1 1 519094DB -P 6650 4450 -F 0 "U3" H 6500 4550 50 0000 C CNN -F 1 "VPLOT8_1" H 6800 4550 50 0000 C CNN - 1 6650 4450 - 1 0 0 -1 -$EndComp -Connection ~ 6350 4750 -Wire Wire Line - 6350 4750 6650 4750 -Wire Wire Line - 5050 3150 5450 3150 -Wire Wire Line - 4150 6850 4150 6500 -Wire Wire Line - 4150 3150 4150 4150 -Wire Wire Line - 6350 3850 6350 4150 -Wire Wire Line - 4150 5750 4150 6000 -Wire Wire Line - 6350 4650 6350 4800 -Wire Wire Line - 4150 5350 4150 4650 -Wire Wire Line - 6350 5200 4150 5200 -Connection ~ 4150 5200 -Wire Wire Line - 6350 3350 6350 3150 -Connection ~ 6350 4000 -Connection ~ 4150 6650 -Wire Wire Line - 5250 3150 5250 3300 -Connection ~ 5250 3150 -$Comp -L GND #PWR01 -U 1 1 51909464 -P 5250 3300 -F 0 "#PWR01" H 5250 3300 30 0001 C CNN -F 1 "GND" H 5250 3230 30 0001 C CNN - 1 5250 3300 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 51909454 -P 5900 3150 -F 0 "v2" H 5700 3250 60 0000 C CNN -F 1 "10V" H 5700 3100 60 0000 C CNN -F 2 "R1" H 5600 3150 60 0000 C CNN - 1 5900 3150 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 5167D912 -P 4600 3150 -F 0 "v1" H 4400 3250 60 0000 C CNN -F 1 "10V" H 4400 3100 60 0000 C CNN -F 2 "R1" H 4300 3150 60 0000 C CNN - 1 4600 3150 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516A8F23 -P 4150 6650 -F 0 "#FLG02" H 4150 6745 30 0001 C CNN -F 1 "PWR_FLAG" H 4150 6830 30 0000 C CNN - 1 4150 6650 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 5167DAB9 -P 4150 6850 -F 0 "#PWR03" H 4150 6850 30 0001 C CNN -F 1 "GND" H 4150 6780 30 0001 C CNN - 1 4150 6850 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 5167DA8B -P 4150 6250 -F 0 "U1" H 4000 6350 50 0000 C CNN -F 1 "IPLOT" H 4300 6350 50 0000 C CNN - 1 4150 6250 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 5167D9D2 -P 6350 3600 -F 0 "U2" H 6200 3700 50 0000 C CNN -F 1 "IPLOT" H 6500 3700 50 0000 C CNN - 1 6350 3600 - 0 1 1 0 -$EndComp -$Comp -L DIODE D2 -U 1 1 5167D956 -P 6350 5000 -F 0 "D2" H 6350 5100 40 0000 C CNN -F 1 "DIODE" H 6350 4900 40 0000 C CNN - 1 6350 5000 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5167D8E5 -P 6350 4400 -F 0 "R2" V 6430 4400 50 0000 C CNN -F 1 "5k" V 6350 4400 50 0000 C CNN - 1 6350 4400 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5167D8B8 -P 4150 4400 -F 0 "R1" V 4230 4400 50 0000 C CNN -F 1 "10k" V 4150 4400 50 0000 C CNN - 1 4150 4400 - 1 0 0 -1 -$EndComp -$Comp -L DIODE D1 -U 1 1 5167D869 -P 4150 5550 -F 0 "D1" H 4150 5650 40 0000 C CNN -F 1 "DIODE" H 4150 5450 40 0000 C CNN - 1 4150 5550 - 0 -1 -1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis deleted file mode 100644 index f481193..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 5e-00 50e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib deleted file mode 100644 index f4b7c8a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model diode D( Vj=.65 Nbvl=14.976 Cjo=175p Rs=.20 Isr=1.859n -+ Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u -+ Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m -+ Is=880.5E-18 Xti=3 Ibvl=1.9556m )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak deleted file mode 100644 index f7ad596..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak +++ /dev/null @@ -1,105 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Friday 12 April 2013 03:08:39 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* - SM1206 -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8 -# -DEF vplot8 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -300 0 200 R 40 40 1 1 O -X - 9 300 0 200 L 40 40 1 1 O -X + 2 -300 0 200 R 40 40 2 1 O -X - 10 300 0 200 L 40 40 2 1 O -X + 3 -300 0 200 R 40 40 3 1 O -X - 11 300 0 200 L 40 40 3 1 O -X + 4 -300 0 200 R 40 40 4 1 O -X - 12 300 0 200 L 40 40 4 1 O -X + 5 -300 0 200 R 40 40 5 1 O -X - 13 300 0 200 L 40 40 5 1 O -X + 6 -300 0 200 R 40 40 6 1 O -X - 14 300 0 200 L 40 40 6 1 O -X + 7 -300 0 200 R 40 40 7 1 O -X - 15 300 0 200 L 40 40 7 1 O -X + 8 -300 0 200 R 40 40 8 1 O -X - 16 300 0 200 L 40 40 8 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib deleted file mode 100644 index 1321f82..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib +++ /dev/null @@ -1,108 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 12:59:04 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak deleted file mode 100644 index 132334d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak +++ /dev/null @@ -1,133 +0,0 @@ -EESchema Schematic File Version 2 date Friday 12 April 2013 03:08:39 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_2.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "12 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5700 3600 5500 3600 -Wire Wire Line - 6100 3650 6100 4100 -Connection ~ 5500 4100 -Wire Wire Line - 6100 4100 4200 4100 -Wire Wire Line - 4650 2850 4200 2850 -Wire Wire Line - 4200 2850 4200 3200 -Wire Wire Line - 5700 3200 5700 2850 -Wire Wire Line - 5150 2850 6100 2850 -Connection ~ 5700 2850 -Wire Wire Line - 6100 2850 6100 3050 -Wire Wire Line - 5200 4100 5200 4650 -Connection ~ 5200 4100 -$Comp -L IPLOT U2 -U 1 1 5167D5E8 -P 5500 3850 -F 0 "U2" H 5350 3950 50 0000 C CNN -F 1 "IPLOT" H 5650 3950 50 0000 C CNN - 1 5500 3850 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR01 -U 1 1 5166ABF9 -P 5200 4650 -F 0 "#PWR01" H 5200 4650 30 0001 C CNN -F 1 "GND" H 5200 4580 30 0001 C CNN - 1 5200 4650 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8 U1 -U 1 1 5166A97D -P 6100 3350 -F 0 "U1" H 5950 3450 50 0000 C CNN -F 1 "VPLOT8" H 6250 3450 50 0000 C CNN - 1 6100 3350 - 0 1 1 0 -$EndComp -$Comp -L DIODE D1 -U 1 1 5166A924 -P 5700 3400 -F 0 "D1" H 5700 3500 40 0000 C CNN -F 1 "DIODE" H 5700 3300 40 0000 C CNN - 1 5700 3400 - 0 1 1 0 -$EndComp -$Comp -L R R1 -U 1 1 5166A8EF -P 4900 2850 -F 0 "R1" V 4980 2850 50 0000 C CNN -F 1 "1000" V 4900 2850 50 0000 C CNN - 1 4900 2850 - 0 -1 -1 0 -$EndComp -$Comp -L DC v1 -U 1 1 5166A8CD -P 4200 3650 -F 0 "v1" H 4000 3750 60 0000 C CNN -F 1 "5V" H 4000 3600 60 0000 C CNN -F 2 "R1" H 3900 3650 60 0000 C CNN - 1 4200 3650 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir deleted file mode 100644 index 3731a3e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir +++ /dev/null @@ -1,13 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 12:59:00 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 2 VPLOT8_1 -U2 3 0 IPLOT -D1 2 3 DIODE -R1 1 2 1000 -v1 1 0 5V - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt deleted file mode 100644 index 43a6aa9..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt +++ /dev/null @@ -1,13 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:59:00 pm ist -.include diode.lib - -* Plotting option vplot8_1 -V_u2 3 0 0 -d1 2 3 diode -r1 1 2 1000 -v1 1 0 5v - -.dc v1 0e-00 5e-00 50e-03 -.plot v(2) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out deleted file mode 100644 index 3ce4892..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:59:00 pm ist -.include diode.lib - -* Plotting option vplot8_1 -V_u2 3 0 0 -d1 2 3 diode -r1 1 2 1000 -v1 1 0 5v - -.dc v1 0e-00 5e-00 50e-03 - -* Control Statements -.control -run -plot v(2) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro deleted file mode 100644 index 9718ce6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro +++ /dev/null @@ -1,84 +0,0 @@ -update=Monday 13 May 2013 12:58:14 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice -LibName41=/home/holy/OSCAD/library/analogSpice -LibName42=/home/holy/OSCAD/library/analogXSpice -LibName43=/home/holy/OSCAD/library/convergenceAidSpice -LibName44=/home/holy/OSCAD/library/converterSpice -LibName45=/home/holy/OSCAD/library/digitalSpice -LibName46=/home/holy/OSCAD/library/digitalXSpice -LibName47=/home/holy/OSCAD/library/linearSpice -LibName48=/home/holy/OSCAD/library/measurementSpice -LibName49=/home/holy/OSCAD/library/portSpice -LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj deleted file mode 100644 index eb6337b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_2.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch deleted file mode 100644 index 7aac593..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch +++ /dev/null @@ -1,139 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 12:59:04 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_2.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PWR_FLAG #FLG01 -U 1 1 51909635 -P 5200 4200 -F 0 "#FLG01" H 5200 4470 30 0001 C CNN -F 1 "PWR_FLAG" H 5200 4430 30 0000 C CNN - 1 5200 4200 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5190961B -P 5700 2550 -F 0 "U1" H 5550 2650 50 0000 C CNN -F 1 "VPLOT8_1" H 5850 2650 50 0000 C CNN - 1 5700 2550 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5150 2850 5700 2850 -Wire Wire Line - 5700 3600 5700 3700 -Connection ~ 5200 4200 -Wire Wire Line - 5200 4200 5200 4750 -Connection ~ 5700 2850 -Wire Wire Line - 5700 2850 5700 3200 -Wire Wire Line - 4200 3200 4200 2850 -Wire Wire Line - 4200 2850 4650 2850 -Wire Wire Line - 4200 4100 4200 4200 -Wire Wire Line - 4200 4200 5700 4200 -$Comp -L IPLOT U2 -U 1 1 5167D5E8 -P 5700 3950 -F 0 "U2" H 5550 4050 50 0000 C CNN -F 1 "IPLOT" H 5850 4050 50 0000 C CNN - 1 5700 3950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5166ABF9 -P 5200 4750 -F 0 "#PWR02" H 5200 4750 30 0001 C CNN -F 1 "GND" H 5200 4680 30 0001 C CNN - 1 5200 4750 - 1 0 0 -1 -$EndComp -$Comp -L DIODE D1 -U 1 1 5166A924 -P 5700 3400 -F 0 "D1" H 5700 3500 40 0000 C CNN -F 1 "DIODE" H 5700 3300 40 0000 C CNN - 1 5700 3400 - 0 1 1 0 -$EndComp -$Comp -L R R1 -U 1 1 5166A8EF -P 4900 2850 -F 0 "R1" V 4980 2850 50 0000 C CNN -F 1 "1000" V 4900 2850 50 0000 C CNN - 1 4900 2850 - 0 -1 -1 0 -$EndComp -$Comp -L DC v1 -U 1 1 5166A8CD -P 4200 3650 -F 0 "v1" H 4000 3750 60 0000 C CNN -F 1 "5V" H 4000 3600 60 0000 C CNN -F 2 "R1" H 3900 3650 60 0000 C CNN - 1 4200 3650 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis deleted file mode 100644 index 0a70a74..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 5e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib deleted file mode 100644 index d5c42a7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model diode D( Is=880.5E-18 Nbvl=14.976 Cjo=175p Rs=20 Isr=1.859n -+ Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u -+ Bv=8.1 Fc=.5 Ikf=0 Xti=3 Nr=2 -+ Vj=.65 Ibv=20.245m Ibvl=1.9556m )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak deleted file mode 100644 index 4dd86fe..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak +++ /dev/null @@ -1,108 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 02:41:15 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib deleted file mode 100644 index 9adc092..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib +++ /dev/null @@ -1,108 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 21 May 2013 11:07:18 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak deleted file mode 100644 index 21d43d7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak +++ /dev/null @@ -1,164 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 14 May 2013 02:41:15 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_2.5-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "14 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L DC v1 -U 1 1 5191FF90 -P 5000 3850 -F 0 "v1" H 4800 3950 60 0000 C CNN -F 1 "DC" H 4800 3800 60 0000 C CNN -F 2 "R1" H 4700 3850 60 0000 C CNN - 1 5000 3850 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5190978A -P 6250 5300 -F 0 "#FLG01" H 6250 5570 30 0001 C CNN -F 1 "PWR_FLAG" H 6250 5530 30 0000 C CNN - 1 6250 5300 - 1 0 0 -1 -$EndComp -Connection ~ 6600 2100 -$Comp -L VPLOT8_1 U1 -U 1 1 51909775 -P 6600 1800 -F 0 "U1" H 6450 1900 50 0000 C CNN -F 1 "VPLOT8_1" H 6750 1900 50 0000 C CNN - 1 6600 1800 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6250 5300 5000 5300 -Wire Wire Line - 6250 3300 6250 3350 -Wire Wire Line - 6250 4850 6250 5500 -Wire Wire Line - 6250 2350 6250 2100 -Connection ~ 6250 5300 -Connection ~ 6250 2100 -Wire Wire Line - 5250 2100 5000 2100 -Wire Wire Line - 5750 2100 6600 2100 -Connection ~ 6250 5300 -Wire Wire Line - 6250 2750 6250 2800 -Wire Wire Line - 5000 2100 5000 3400 -Wire Wire Line - 6250 4250 6250 4350 -Wire Wire Line - 5000 5300 5000 4300 -$Comp -L IPLOT U2 -U 1 1 519096FE -P 6250 4600 -F 0 "U2" H 6100 4700 50 0000 C CNN -F 1 "IPLOT" H 6400 4700 50 0000 C CNN - 1 6250 4600 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 519096A6 -P 6250 3050 -F 0 "R2" V 6330 3050 50 0000 C CNN -F 1 "20m" V 6250 3050 50 0000 C CNN - 1 6250 3050 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5190969F -P 6250 3800 -F 0 "v2" H 6050 3900 60 0000 C CNN -F 1 "65m" H 6050 3750 60 0000 C CNN -F 2 "R1" H 5950 3800 60 0000 C CNN - 1 6250 3800 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516A928C -P 5500 2100 -F 0 "R1" V 5580 2100 50 0000 C CNN -F 1 "1000" V 5500 2100 50 0000 C CNN - 1 5500 2100 - 0 -1 -1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5166AFB9 -P 6250 5500 -F 0 "#PWR02" H 6250 5500 30 0001 C CNN -F 1 "GND" H 6250 5430 30 0001 C CNN - 1 6250 5500 - 1 0 0 -1 -$EndComp -$Comp -L DIODE D1 -U 1 1 5166AF28 -P 6250 2550 -F 0 "D1" H 6250 2650 40 0000 C CNN -F 1 "DIODE" H 6250 2450 40 0000 C CNN - 1 6250 2550 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir deleted file mode 100644 index ab9de69..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 14 May 2013 02:41:09 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v1 1 0 DC -U1 5 VPLOT8_1 -U2 4 0 IPLOT -R2 3 2 20m -v2 2 4 65m -R1 1 5 1000 -D1 5 3 DIODE - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt deleted file mode 100644 index eb19daf..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt +++ /dev/null @@ -1,15 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 14 may 2013 02:41:09 pm ist -.include diode.lib - -v1 1 0 dc 5 -* Plotting option vplot8_1 -V_u2 4 0 0 -r2 3 2 20m -v2 2 4 65m -r1 1 5 1000 -d1 5 3 diode - -.dc v1 0e-00 5e-00 1e-00 -.plot v(5) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out deleted file mode 100644 index a3bbe2c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 14 may 2013 02:41:09 pm ist -.include diode.lib - -v1 1 0 dc 5 -* Plotting option vplot8_1 -V_u2 4 0 0 -r2 3 2 20m -v2 2 4 65m -r1 1 5 1000 -d1 5 3 diode - -.dc v1 0e-00 5e-00 1e-00 - -* Control Statements -.control -run -plot v(5) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro deleted file mode 100644 index 8e9a0fd..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro +++ /dev/null @@ -1,84 +0,0 @@ -update=Monday 13 May 2013 01:04:04 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice -LibName41=/home/holy/OSCAD/library/analogSpice -LibName42=/home/holy/OSCAD/library/analogXSpice -LibName43=/home/holy/OSCAD/library/convergenceAidSpice -LibName44=/home/holy/OSCAD/library/converterSpice -LibName45=/home/holy/OSCAD/library/digitalSpice -LibName46=/home/holy/OSCAD/library/digitalXSpice -LibName47=/home/holy/OSCAD/library/linearSpice -LibName48=/home/holy/OSCAD/library/measurementSpice -LibName49=/home/holy/OSCAD/library/portSpice -LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj deleted file mode 100644 index 1148c23..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_2.5.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch deleted file mode 100644 index ff9da18..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch +++ /dev/null @@ -1,168 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 21 May 2013 11:07:18 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_2.5-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "21 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 6650 2050 0 90 Italic 18 -Vd -Text Notes 6450 3850 0 90 Italic 18 -Id -$Comp -L DC v1 -U 1 1 5191FF90 -P 5000 3850 -F 0 "v1" H 4800 3950 60 0000 C CNN -F 1 "DC" H 4800 3800 60 0000 C CNN -F 2 "R1" H 4700 3850 60 0000 C CNN - 1 5000 3850 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5190978A -P 6250 5300 -F 0 "#FLG01" H 6250 5570 30 0001 C CNN -F 1 "PWR_FLAG" H 6250 5530 30 0000 C CNN - 1 6250 5300 - 1 0 0 -1 -$EndComp -Connection ~ 6600 2100 -$Comp -L VPLOT8_1 U1 -U 1 1 51909775 -P 6600 1800 -F 0 "U1" H 6450 1900 50 0000 C CNN -F 1 "VPLOT8_1" H 6750 1900 50 0000 C CNN - 1 6600 1800 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6250 5300 5000 5300 -Wire Wire Line - 6250 3300 6250 3350 -Wire Wire Line - 6250 4850 6250 5500 -Wire Wire Line - 6250 2350 6250 2100 -Connection ~ 6250 5300 -Connection ~ 6250 2100 -Wire Wire Line - 5250 2100 5000 2100 -Wire Wire Line - 5750 2100 6600 2100 -Connection ~ 6250 5300 -Wire Wire Line - 6250 2750 6250 2800 -Wire Wire Line - 5000 2100 5000 3400 -Wire Wire Line - 6250 4250 6250 4350 -Wire Wire Line - 5000 5300 5000 4300 -$Comp -L IPLOT U2 -U 1 1 519096FE -P 6250 4600 -F 0 "U2" H 6100 4700 50 0000 C CNN -F 1 "IPLOT" H 6400 4700 50 0000 C CNN - 1 6250 4600 - 0 1 1 0 -$EndComp -$Comp -L R Rd -U 1 1 519096A6 -P 6250 3050 -F 0 "Rd" V 6330 3050 50 0000 C CNN -F 1 "20m" V 6250 3050 50 0000 C CNN - 1 6250 3050 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5190969F -P 6250 3800 -F 0 "v2" H 6050 3900 60 0000 C CNN -F 1 "65m" H 6050 3750 60 0000 C CNN -F 2 "R1" H 5950 3800 60 0000 C CNN - 1 6250 3800 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516A928C -P 5500 2100 -F 0 "R1" V 5580 2100 50 0000 C CNN -F 1 "1000" V 5500 2100 50 0000 C CNN - 1 5500 2100 - 0 -1 -1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5166AFB9 -P 6250 5500 -F 0 "#PWR02" H 6250 5500 30 0001 C CNN -F 1 "GND" H 6250 5430 30 0001 C CNN - 1 6250 5500 - 1 0 0 -1 -$EndComp -$Comp -L DIODE D1 -U 1 1 5166AF28 -P 6250 2550 -F 0 "D1" H 6250 2650 40 0000 C CNN -F 1 "DIODE" H 6250 2450 40 0000 C CNN - 1 6250 2550 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/analysis deleted file mode 100644 index 35318bb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.bak deleted file mode 100644 index c86efd4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.bak +++ /dev/null @@ -1,93 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 03:23:37 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8 -# -DEF vplot8 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -300 0 200 R 40 40 1 1 O -X - 9 300 0 200 L 40 40 1 1 O -X + 2 -300 0 200 R 40 40 2 1 O -X - 10 300 0 200 L 40 40 2 1 O -X + 3 -300 0 200 R 40 40 3 1 O -X - 11 300 0 200 L 40 40 3 1 O -X + 4 -300 0 200 R 40 40 4 1 O -X - 12 300 0 200 L 40 40 4 1 O -X + 5 -300 0 200 R 40 40 5 1 O -X - 13 300 0 200 L 40 40 5 1 O -X + 6 -300 0 200 R 40 40 6 1 O -X - 14 300 0 200 L 40 40 6 1 O -X + 7 -300 0 200 R 40 40 7 1 O -X - 15 300 0 200 L 40 40 7 1 O -X + 8 -300 0 200 R 40 40 8 1 O -X - 16 300 0 200 L 40 40 8 1 O -ENDDRAW -ENDDEF -# -# ZENER -# -DEF ZENER D 0 40 N N 1 F N -F0 "D" 0 100 50 H V C CNN -F1 "ZENER" 0 -100 40 H V C CNN -$FPLIST - D? - SO* - SM* -$ENDFPLIST -DRAW -P 5 0 1 0 50 0 -50 50 -50 -50 50 0 50 0 F -P 5 0 1 8 70 50 50 30 50 -30 30 -50 30 -50 N -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.lib deleted file mode 100644 index 68b8c20..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.lib +++ /dev/null @@ -1,93 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 03:25:17 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8 -# -DEF vplot8 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -300 0 200 R 40 40 1 1 O -X - 9 300 0 200 L 40 40 1 1 O -X + 2 -300 0 200 R 40 40 2 1 O -X - 10 300 0 200 L 40 40 2 1 O -X + 3 -300 0 200 R 40 40 3 1 O -X - 11 300 0 200 L 40 40 3 1 O -X + 4 -300 0 200 R 40 40 4 1 O -X - 12 300 0 200 L 40 40 4 1 O -X + 5 -300 0 200 R 40 40 5 1 O -X - 13 300 0 200 L 40 40 5 1 O -X + 6 -300 0 200 R 40 40 6 1 O -X - 14 300 0 200 L 40 40 6 1 O -X + 7 -300 0 200 R 40 40 7 1 O -X - 15 300 0 200 L 40 40 7 1 O -X + 8 -300 0 200 R 40 40 8 1 O -X - 16 300 0 200 L 40 40 8 1 O -ENDDRAW -ENDDEF -# -# ZENER -# -DEF ZENER D 0 40 N N 1 F N -F0 "D" 0 100 50 H V C CNN -F1 "ZENER" 0 -100 40 H V C CNN -$FPLIST - D? - SO* - SM* -$ENDFPLIST -DRAW -P 5 0 1 0 50 0 -50 50 -50 -50 50 0 50 0 F -P 5 0 1 8 70 50 50 30 50 -30 30 -50 30 -50 N -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.bak deleted file mode 100644 index 298b82a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.bak +++ /dev/null @@ -1,132 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 03:23:37 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 7200 2400 -Connection ~ 7200 1800 -Wire Wire Line - 6450 2400 7550 2400 -Wire Wire Line - 6450 2400 6450 2250 -Connection ~ 6850 2400 -Wire Wire Line - 7550 2400 7550 2300 -Wire Wire Line - 6850 2000 6850 1700 -Wire Wire Line - 6850 1200 6450 1200 -Wire Wire Line - 7550 1800 6850 1800 -Connection ~ 6850 1800 -Wire Wire Line - 6450 1200 6450 1350 -Wire Wire Line - 7100 2400 7100 2600 -Connection ~ 7100 2400 -$Comp -L GND #PWR01 -U 1 1 516BCDAC -P 7100 2600 -F 0 "#PWR01" H 7100 2600 30 0001 C CNN -F 1 "GND" H 7100 2530 30 0001 C CNN - 1 7100 2600 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 516BCD76 -P 6450 1800 -F 0 "v1" H 6250 1900 60 0000 C CNN -F 1 "DC" H 6250 1750 60 0000 C CNN -F 2 "R1" H 6150 1800 60 0000 C CNN - 1 6450 1800 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8 U1 -U 1 1 516BCD56 -P 7200 2100 -F 0 "U1" H 7050 2200 50 0000 C CNN -F 1 "VPLOT8" H 7350 2200 50 0000 C CNN - 1 7200 2100 - 0 -1 -1 0 -$EndComp -$Comp -L R R2 -U 1 1 516BCD26 -P 7550 2050 -F 0 "R2" V 7630 2050 50 0000 C CNN -F 1 "R" V 7550 2050 50 0000 C CNN - 1 7550 2050 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516BCCFA -P 6850 1450 -F 0 "R1" V 6930 1450 50 0000 C CNN -F 1 "R" V 6850 1450 50 0000 C CNN - 1 6850 1450 - 1 0 0 -1 -$EndComp -$Comp -L ZENER D1 -U 1 1 516BCCC7 -P 6850 2200 -F 0 "D1" H 6850 2300 50 0000 C CNN -F 1 "ZENER" H 6850 2100 40 0000 C CNN - 1 6850 2200 - 0 -1 -1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir deleted file mode 100644 index 69c2aea..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir +++ /dev/null @@ -1,13 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 03:25:12 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v1 3 0 DC -U1 0 1 VPLOT8 -R2 1 0 2000 -R1 3 1 500 -D1 0 1 ZENER - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.ckt deleted file mode 100644 index cd705cf..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.ckt +++ /dev/null @@ -1,10 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 03:25:12 pm ist - -v1 3 0 dc 10 -r2 1 0 2000 -r1 3 1 500 -d1 0 1 zener - -.dc v1 0e-00 10e-00 5e-03 -.plot -v(1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.out deleted file mode 100644 index 2cdd76d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.out +++ /dev/null @@ -1,15 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 03:25:12 pm ist - -v1 3 0 dc 10 -r2 1 0 2000 -r1 3 1 500 -d1 0 1 zener - -.dc v1 0e-00 10e-00 5e-03 - -* Control Statements -.control -run -plot -v(1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.proj deleted file mode 100644 index e0d6a2f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_2.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.sch deleted file mode 100644 index ddb3704..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.sch +++ /dev/null @@ -1,123 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 03:25:17 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:example_2.8-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 7200 2400 -Connection ~ 7200 1800 -Wire Wire Line - 6450 2400 7550 2400 -Wire Wire Line - 6450 2400 6450 2250 -Connection ~ 6850 2400 -Wire Wire Line - 7550 2400 7550 2300 -Wire Wire Line - 6850 2000 6850 1700 -Wire Wire Line - 6850 1200 6450 1200 -Wire Wire Line - 7550 1800 6850 1800 -Connection ~ 6850 1800 -Wire Wire Line - 6450 1200 6450 1350 -Wire Wire Line - 7100 2400 7100 2600 -Connection ~ 7100 2400 -$Comp -L GND #PWR01 -U 1 1 516BCDAC -P 7100 2600 -F 0 "#PWR01" H 7100 2600 30 0001 C CNN -F 1 "GND" H 7100 2530 30 0001 C CNN - 1 7100 2600 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 516BCD76 -P 6450 1800 -F 0 "v1" H 6250 1900 60 0000 C CNN -F 1 "DC" H 6250 1750 60 0000 C CNN -F 2 "R1" H 6150 1800 60 0000 C CNN - 1 6450 1800 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8 U1 -U 1 1 516BCD56 -P 7200 2100 -F 0 "U1" H 7050 2200 50 0000 C CNN -F 1 "VPLOT8" H 7350 2200 50 0000 C CNN - 1 7200 2100 - 0 -1 -1 0 -$EndComp -$Comp -L R R2 -U 1 1 516BCD26 -P 7550 2050 -F 0 "R2" V 7630 2050 50 0000 C CNN -F 1 "2000" V 7550 2050 50 0000 C CNN - 1 7550 2050 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516BCCFA -P 6850 1450 -F 0 "R1" V 6930 1450 50 0000 C CNN -F 1 "500" V 6850 1450 50 0000 C CNN - 1 6850 1450 - 1 0 0 -1 -$EndComp -$Comp -L ZENER D1 -U 1 1 516BCCC7 -P 6850 2200 -F 0 "D1" H 6850 2300 50 0000 C CNN -F 1 "ZENER" H 6850 2100 40 0000 C CNN - 1 6850 2200 - 0 -1 -1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis deleted file mode 100644 index 73c8f09..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 4e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak deleted file mode 100644 index 1d8b498..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 04:09:27 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib deleted file mode 100644 index f2704f3..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib +++ /dev/null @@ -1,131 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:42:22 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# pulse -# -DEF pulse v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "pulse" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -25 -450 501 928 871 0 1 0 N -50 50 0 50 -A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 -A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 -A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 -A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 -A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak deleted file mode 100644 index ca5b9de..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak +++ /dev/null @@ -1,167 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 04:02:35 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example3.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5900 2550 5900 1050 -Wire Wire Line - 4400 4300 4400 3050 -Wire Wire Line - 5000 3800 5000 3250 -Wire Wire Line - 5000 2050 5000 1550 -Connection ~ 5000 5450 -Wire Wire Line - 4400 5450 5900 5450 -Wire Wire Line - 5900 1050 5000 1050 -Wire Wire Line - 4400 3050 4700 3050 -Wire Wire Line - 4400 5450 4400 5200 -Wire Wire Line - 5000 4950 5000 5750 -Connection ~ 5000 5600 -Connection ~ 5000 3450 -Wire Wire Line - 5000 2550 5000 2850 -Wire Wire Line - 5000 4300 5000 4450 -Wire Wire Line - 5900 5450 5900 3450 -$Comp -L IPLOT U2 -U 1 1 516BD643 -P 5000 4050 -F 0 "U2" H 4850 4150 50 0000 C CNN -F 1 "IPLOT" H 5150 4150 50 0000 C CNN - 1 5000 4050 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516BD5F9 -P 5000 2300 -F 0 "U1" H 4850 2400 50 0000 C CNN -F 1 "IPLOT" H 5150 2400 50 0000 C CNN - 1 5000 2300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5166BF83 -P 5000 5600 -F 0 "#FLG01" H 5000 5695 30 0001 C CNN -F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN - 1 5000 5600 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5166BF64 -P 5000 5750 -F 0 "#PWR02" H 5000 5750 30 0001 C CNN -F 1 "GND" H 5000 5680 30 0001 C CNN - 1 5000 5750 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166BEE6 -P 4400 4750 -F 0 "v1" H 4200 4850 60 0000 C CNN -F 1 "4" H 4200 4700 60 0000 C CNN -F 2 "R1" H 4100 4750 60 0000 C CNN - 1 4400 4750 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5166BED7 -P 5900 3000 -F 0 "v2" H 5700 3100 60 0000 C CNN -F 1 "10V" H 5700 2950 60 0000 C CNN -F 2 "R1" H 5600 3000 60 0000 C CNN - 1 5900 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5166BE96 -P 5000 4700 -F 0 "R2" V 5080 4700 50 0000 C CNN -F 1 "3300" V 5000 4700 50 0000 C CNN - 1 5000 4700 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166BE8E -P 5000 1300 -F 0 "R1" V 5080 1300 50 0000 C CNN -F 1 "4700" V 5000 1300 50 0000 C CNN - 1 5000 1300 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166BE53 -P 4900 3050 -F 0 "Q1" H 4900 2900 50 0000 R CNN -F 1 "NPN" H 4900 3200 50 0000 R CNN - 1 4900 3050 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir deleted file mode 100644 index 87e5f07..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir +++ /dev/null @@ -1,16 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 04:09:24 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U3 6 7 VPLOT8_1 -U2 7 3 IPLOT -U1 5 6 IPLOT -v1 2 0 4 -v2 4 0 10V -R2 3 0 3300 -R1 4 5 4700 -Q1 7 2 6 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt deleted file mode 100644 index 21ea9e6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt +++ /dev/null @@ -1,16 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 04:09:24 pm ist - -* Plotting option vplot8_1 -V_u2 7 3 0 -V_u1 5 6 0 -v1 2 0 4 -v2 4 0 10v -r2 3 0 3300 -r1 4 5 4700 -q1 6 2 7 npn - -.dc v1 0e-00 4e-00 5e-03 -.plot v(6) v(7) -.plot i(V_u2) -.plot i(V_u1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out deleted file mode 100644 index b00fc82..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out +++ /dev/null @@ -1,21 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 04:09:24 pm ist - -* Plotting option vplot8_1 -V_u2 7 3 0 -V_u1 5 6 0 -v1 2 0 4 -v2 4 0 10v -r2 3 0 3300 -r1 4 5 4700 -q1 6 2 7 npn - -.dc v1 0e-00 4e-00 5e-03 - -* Control Statements -.control -run -plot v(6) v(7) -plot i(V_u2) -plot i(V_u1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro deleted file mode 100644 index a38bf27..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro +++ /dev/null @@ -1,84 +0,0 @@ -update=Monday 15 April 2013 04:08:24 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice -LibName41=/home/holy/OSCAD/library/analogSpice -LibName42=/home/holy/OSCAD/library/analogXSpice -LibName43=/home/holy/OSCAD/library/convergenceAidSpice -LibName44=/home/holy/OSCAD/library/converterSpice -LibName45=/home/holy/OSCAD/library/digitalSpice -LibName46=/home/holy/OSCAD/library/digitalXSpice -LibName47=/home/holy/OSCAD/library/linearSpice -LibName48=/home/holy/OSCAD/library/measurementSpice -LibName49=/home/holy/OSCAD/library/portSpice -LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj deleted file mode 100644 index 9978f31..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example3.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch deleted file mode 100644 index 4138df7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch +++ /dev/null @@ -1,186 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 04:09:27 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example3.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5000 2650 -$Comp -L VPLOT8_1 U3 -U 1 1 516BD8B9 -P 5300 2650 -F 0 "U3" H 5150 2750 50 0000 C CNN -F 1 "VPLOT8_1" H 5450 2750 50 0000 C CNN - 1 5300 2650 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 2 1 516BD8AC -P 5300 3450 -F 0 "U3" H 5150 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5450 3550 50 0000 C CNN - 2 5300 3450 - 0 1 1 0 -$EndComp -Wire Wire Line - 5900 2550 5900 1050 -Wire Wire Line - 4400 4300 4400 3050 -Wire Wire Line - 5000 3800 5000 3250 -Wire Wire Line - 5000 2050 5000 1550 -Connection ~ 5000 5450 -Wire Wire Line - 4400 5450 5900 5450 -Wire Wire Line - 5900 1050 5000 1050 -Wire Wire Line - 4400 3050 4700 3050 -Wire Wire Line - 4400 5450 4400 5200 -Wire Wire Line - 5000 4950 5000 5750 -Connection ~ 5000 5600 -Connection ~ 5000 3450 -Wire Wire Line - 5000 2550 5000 2850 -Wire Wire Line - 5000 4300 5000 4450 -Wire Wire Line - 5900 5450 5900 3450 -$Comp -L IPLOT U2 -U 1 1 516BD643 -P 5000 4050 -F 0 "U2" H 4850 4150 50 0000 C CNN -F 1 "IPLOT" H 5150 4150 50 0000 C CNN - 1 5000 4050 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516BD5F9 -P 5000 2300 -F 0 "U1" H 4850 2400 50 0000 C CNN -F 1 "IPLOT" H 5150 2400 50 0000 C CNN - 1 5000 2300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5166BF83 -P 5000 5600 -F 0 "#FLG01" H 5000 5695 30 0001 C CNN -F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN - 1 5000 5600 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5166BF64 -P 5000 5750 -F 0 "#PWR02" H 5000 5750 30 0001 C CNN -F 1 "GND" H 5000 5680 30 0001 C CNN - 1 5000 5750 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166BEE6 -P 4400 4750 -F 0 "v1" H 4200 4850 60 0000 C CNN -F 1 "4" H 4200 4700 60 0000 C CNN -F 2 "R1" H 4100 4750 60 0000 C CNN - 1 4400 4750 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5166BED7 -P 5900 3000 -F 0 "v2" H 5700 3100 60 0000 C CNN -F 1 "10V" H 5700 2950 60 0000 C CNN -F 2 "R1" H 5600 3000 60 0000 C CNN - 1 5900 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5166BE96 -P 5000 4700 -F 0 "R2" V 5080 4700 50 0000 C CNN -F 1 "3300" V 5000 4700 50 0000 C CNN - 1 5000 4700 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166BE8E -P 5000 1300 -F 0 "R1" V 5080 1300 50 0000 C CNN -F 1 "4700" V 5000 1300 50 0000 C CNN - 1 5000 1300 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166BE53 -P 4900 3050 -F 0 "Q1" H 4900 2900 50 0000 R CNN -F 1 "NPN" H 4900 3200 50 0000 R CNN - 1 4900 3050 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis deleted file mode 100644 index 395e205..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v2 0e-00 15e-00 15e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak deleted file mode 100644 index 3c23bc8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak +++ /dev/null @@ -1,97 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 06:57:20 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib deleted file mode 100644 index b1e32d7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 06:59:23 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak deleted file mode 100644 index 9b63b41..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak +++ /dev/null @@ -1,154 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:57:20 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5750 5350 5750 5950 -Connection ~ 4300 4400 -Connection ~ 5750 4100 -Wire Wire Line - 4300 4500 4300 4400 -Wire Wire Line - 4300 4400 5450 4400 -Connection ~ 4750 4400 -Wire Wire Line - 4750 4600 4750 4050 -Wire Wire Line - 4750 3150 4750 2750 -Wire Wire Line - 4750 2750 5750 2750 -Wire Wire Line - 5750 4600 5750 4850 -Wire Wire Line - 4750 5500 4750 5950 -Wire Wire Line - 4750 5950 5750 5950 -Wire Wire Line - 5750 4200 5750 3250 -$Comp -L DC v1 -U 1 1 517A27AF -P 4750 3600 -F 0 "v1" H 4550 3700 60 0000 C CNN -F 1 "DC" H 4550 3550 60 0000 C CNN -F 2 "R1" H 4450 3600 60 0000 C CNN - 1 4750 3600 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 517A278C -P 4750 5050 -F 0 "v2" H 4550 5150 60 0000 C CNN -F 1 "DC" H 4550 5000 60 0000 C CNN -F 2 "R1" H 4450 5050 60 0000 C CNN - 1 4750 5050 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5178C864 -P 6050 4100 -F 0 "U1" H 5900 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 6200 4200 50 0000 C CNN - 1 6050 4100 - 0 1 1 0 -$EndComp -$Comp -L NPN Q1 -U 1 1 5178C812 -P 5650 4400 -F 0 "Q1" H 5650 4250 50 0000 R CNN -F 1 "NPN" H 5650 4550 50 0000 R CNN - 1 5650 4400 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516BDAF0 -P 4300 4400 -F 0 "#FLG01" H 4300 4670 30 0001 C CNN -F 1 "PWR_FLAG" H 4300 4630 30 0000 C CNN - 1 4300 4400 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516BDAE0 -P 4300 4500 -F 0 "#PWR02" H 4300 4500 30 0001 C CNN -F 1 "GND" H 4300 4430 30 0001 C CNN - 1 4300 4500 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516BD9B5 -P 5750 3000 -F 0 "R1" V 5830 3000 50 0000 C CNN -F 1 "5k" V 5750 3000 50 0000 C CNN - 1 5750 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516BD9A9 -P 5750 5100 -F 0 "R2" V 5850 5100 50 0000 C CNN -F 1 "7.07k" V 5750 5100 50 0000 C CNN - 1 5750 5100 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir deleted file mode 100644 index bdacb65..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 06:59:18 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 4 3 IPLOT -v1 1 0 DC -v2 0 5 DC -U1 3 VPLOT8_1 -Q1 2 0 3 NPN -R1 1 4 5k -R2 2 5 7.07k - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt deleted file mode 100644 index 055c4d2..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt +++ /dev/null @@ -1,15 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 06:59:18 pm ist -.include npn.lib - -V_u2 4 3 0 -v1 1 0 dc 15 -v2 0 5 dc 15 -* Plotting option vplot8_1 -q1 3 0 2 npn -r1 1 4 5k -r2 2 5 7.07k - -.dc v2 0e-00 15e-00 15e-00 -.plot i(V_u2) -.plot v(3) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out deleted file mode 100644 index 17c61c2..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 06:59:18 pm ist -.include npn.lib - -V_u2 4 3 0 -v1 1 0 dc 15 -v2 0 5 dc 15 -* Plotting option vplot8_1 -q1 3 0 2 npn -r1 1 4 5k -r2 2 5 7.07k - -.dc v2 0e-00 15e-00 15e-00 - -* Control Statements -.control -run -plot i(V_u2) -plot v(3) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro deleted file mode 100644 index 5bf994d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 15 April 2013 04:46:53 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj deleted file mode 100644 index 3a2ba21..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch deleted file mode 100644 index 7873ea6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch +++ /dev/null @@ -1,165 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:59:23 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5750 4200 5750 3850 -Wire Wire Line - 5750 5350 5750 5950 -Connection ~ 4300 4400 -Connection ~ 5750 4100 -Wire Wire Line - 4300 4500 4300 4400 -Wire Wire Line - 4300 4400 5450 4400 -Connection ~ 4750 4400 -Wire Wire Line - 4750 4600 4750 4050 -Wire Wire Line - 4750 3150 4750 2750 -Wire Wire Line - 4750 2750 5750 2750 -Wire Wire Line - 5750 4600 5750 4850 -Wire Wire Line - 4750 5500 4750 5950 -Wire Wire Line - 4750 5950 5750 5950 -Wire Wire Line - 5750 3250 5750 3350 -$Comp -L IPLOT U2 -U 1 1 51938D87 -P 5750 3600 -F 0 "U2" H 5600 3700 50 0000 C CNN -F 1 "IPLOT" H 5900 3700 50 0000 C CNN - 1 5750 3600 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 517A27AF -P 4750 3600 -F 0 "v1" H 4550 3700 60 0000 C CNN -F 1 "DC" H 4550 3550 60 0000 C CNN -F 2 "R1" H 4450 3600 60 0000 C CNN - 1 4750 3600 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 517A278C -P 4750 5050 -F 0 "v2" H 4550 5150 60 0000 C CNN -F 1 "DC" H 4550 5000 60 0000 C CNN -F 2 "R1" H 4450 5050 60 0000 C CNN - 1 4750 5050 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5178C864 -P 6050 4100 -F 0 "U1" H 5900 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 6200 4200 50 0000 C CNN - 1 6050 4100 - 0 1 1 0 -$EndComp -$Comp -L NPN Q1 -U 1 1 5178C812 -P 5650 4400 -F 0 "Q1" H 5650 4250 50 0000 R CNN -F 1 "NPN" H 5650 4550 50 0000 R CNN - 1 5650 4400 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG1 -U 1 1 516BDAF0 -P 4300 4400 -F 0 "#FLG1" H 4300 4670 30 0001 C CNN -F 1 "PWR_FLAG" H 4300 4630 30 0000 C CNN - 1 4300 4400 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR1 -U 1 1 516BDAE0 -P 4300 4500 -F 0 "#PWR1" H 4300 4500 30 0001 C CNN -F 1 "GND" H 4300 4430 30 0001 C CNN - 1 4300 4500 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516BD9B5 -P 5750 3000 -F 0 "R1" V 5830 3000 50 0000 C CNN -F 1 "5k" V 5750 3000 50 0000 C CNN - 1 5750 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516BD9A9 -P 5750 5100 -F 0 "R2" V 5850 5100 50 0000 C CNN -F 1 "7.07k" V 5750 5100 50 0000 C CNN - 1 5750 5100 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib deleted file mode 100644 index 1ff6b05..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 -+ Cje=4.493p Isc=0 Xtb=1.5 Rb=10 Rc=1 -+ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 -+ Ise=6.734f Br=.7371 Ikf=66.78m Mje=.2593 Mjc=.3085 -+ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=2 Itf=.4 -+ Is=6.734f Eg=1.11 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/analysis deleted file mode 100644 index bd0d4e6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 15e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10-cache.lib deleted file mode 100644 index a66f15e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 10:01:35 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir deleted file mode 100644 index 6cc7243..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir +++ /dev/null @@ -1,17 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 10:01:31 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 1 3 7 VPLOT8_1 -R2 1 0 50000 -R1 5 1 100000 -R4 4 0 3000 -U4 7 4 IPLOT -v1 5 0 15V -U3 6 3 IPLOT -R3 5 6 5000 -Q1 7 1 3 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.ckt deleted file mode 100644 index 6b82c7f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:01:31 pm ist - -* Plotting option vplot8_1 -r2 1 0 50000 -r1 5 1 100000 -r4 4 0 3000 -V_u4 7 4 0 -v1 5 0 15v -V_u3 6 3 0 -r3 5 6 5000 -q1 3 1 7 npn - -.dc v1 0e-00 15e-00 5e-03 -.plot v(1) v(3) v(7) -.plot i(V_u4) -.plot i(V_u3) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.out deleted file mode 100644 index 0e51a81..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:01:31 pm ist - -* Plotting option vplot8_1 -r2 1 0 50000 -r1 5 1 100000 -r4 4 0 3000 -V_u4 7 4 0 -v1 5 0 15v -V_u3 6 3 0 -r3 5 6 5000 -q1 3 1 7 npn - -.dc v1 0e-00 15e-00 5e-03 - -* Control Statements -.control -run -plot v(1) v(3) v(7) -plot i(V_u4) -plot i(V_u3) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.pro deleted file mode 100644 index 78f9f3c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 15 April 2013 09:51:55 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.proj deleted file mode 100644 index 6fef01d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.10.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.sch deleted file mode 100644 index 54adb65..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.sch +++ /dev/null @@ -1,209 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 10:01:35 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5050 3350 4200 3350 -Wire Wire Line - 6850 2850 6850 1300 -Wire Wire Line - 6850 1300 4200 1300 -Wire Wire Line - 4200 1300 4200 2200 -Connection ~ 4200 3350 -Wire Wire Line - 4200 2700 4200 3800 -Wire Wire Line - 6850 3750 6850 5150 -Wire Wire Line - 5350 3550 5350 3750 -Wire Wire Line - 5350 2050 5350 2250 -Wire Wire Line - 5350 1550 5350 1300 -Wire Wire Line - 5350 2750 5350 3150 -Wire Wire Line - 5350 4250 5350 4400 -Wire Wire Line - 4200 4300 4200 5150 -Wire Wire Line - 4200 5150 6850 5150 -Connection ~ 5350 5150 -Connection ~ 5350 1300 -Wire Wire Line - 5350 5650 5350 4900 -Connection ~ 5350 5500 -Connection ~ 5350 3650 -Connection ~ 5350 2900 -Connection ~ 5000 3350 -$Comp -L VPLOT8_1 U2 -U 3 1 516C2B0C -P 5650 3650 -F 0 "U2" H 5500 3750 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3750 50 0000 C CNN - 3 5650 3650 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516C2B05 -P 5650 2900 -F 0 "U2" H 5500 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3000 50 0000 C CNN - 2 5650 2900 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516C2AFE -P 5000 3050 -F 0 "U2" H 4850 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN - 1 5000 3050 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C2AB7 -P 5350 5500 -F 0 "#FLG01" H 5350 5770 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN - 1 5350 5500 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C2AAB -P 5350 5650 -F 0 "#PWR02" H 5350 5650 30 0001 C CNN -F 1 "GND" H 5350 5580 30 0001 C CNN - 1 5350 5650 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516C2A3E -P 4200 4050 -F 0 "R2" V 4280 4050 50 0000 C CNN -F 1 "50000" V 4200 4050 50 0000 C CNN - 1 4200 4050 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516C2A13 -P 4200 2450 -F 0 "R1" V 4280 2450 50 0000 C CNN -F 1 "100000" V 4200 2450 50 0000 C CNN - 1 4200 2450 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 516C29D9 -P 5350 4650 -F 0 "R4" V 5430 4650 50 0000 C CNN -F 1 "3000" V 5350 4650 50 0000 C CNN - 1 5350 4650 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516C29CD -P 5350 4000 -F 0 "U4" H 5200 4100 50 0000 C CNN -F 1 "IPLOT" H 5500 4100 50 0000 C CNN - 1 5350 4000 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C296E -P 6850 3300 -F 0 "v1" H 6650 3400 60 0000 C CNN -F 1 "15V" H 6650 3250 60 0000 C CNN -F 2 "R1" H 6550 3300 60 0000 C CNN - 1 6850 3300 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516C2958 -P 5350 2500 -F 0 "U3" H 5200 2600 50 0000 C CNN -F 1 "IPLOT" H 5500 2600 50 0000 C CNN - 1 5350 2500 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 516C293A -P 5350 1800 -F 0 "R3" V 5430 1800 50 0000 C CNN -F 1 "5000" V 5350 1800 50 0000 C CNN - 1 5350 1800 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 516C2934 -P 5250 3350 -F 0 "Q1" H 5250 3200 50 0000 R CNN -F 1 "NPN" H 5250 3500 50 0000 R CNN - 1 5250 3350 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/analysis deleted file mode 100644 index bd0d4e6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 15e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11-cache.lib deleted file mode 100644 index c412639..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11-cache.lib +++ /dev/null @@ -1,127 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 10:18:23 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir deleted file mode 100644 index 72eb140..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir +++ /dev/null @@ -1,23 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 10:18:19 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U4 11 VPLOT8_1 -R1 7 11 100000 -U3 1 4 6 5 VPLOT8_1 -R5 7 3 2000 -U5 3 6 IPLOT -R6 2 0 2700 -U6 5 2 IPLOT -R4 10 0 3000 -U2 4 10 IPLOT -R3 7 9 5000 -U1 9 1 IPLOT -v1 7 0 DC -R2 11 0 50000 -Q2 6 1 5 PNP -Q1 4 11 1 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.ckt deleted file mode 100644 index 5e6583e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.ckt +++ /dev/null @@ -1,26 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:18:19 pm ist - -* Plotting option vplot8_1 -r1 7 11 100000 -* Plotting option vplot8_1 -r5 7 3 2000 -V_u5 3 6 0 -r6 2 0 2700 -V_u6 5 2 0 -r4 10 0 3000 -V_u2 4 10 0 -r3 7 9 5000 -V_u1 9 1 0 -v1 7 0 dc 15 -r2 11 0 50000 -q2 5 1 6 pnp -q1 1 11 4 npn - -.dc v1 0e-00 15e-00 5e-03 -.plot v(11) -.plot v(1) v(4) v(6) v(5) -.plot i(V_u5) -.plot i(V_u6) -.plot i(V_u2) -.plot i(V_u1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.out deleted file mode 100644 index 1a2f17d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.out +++ /dev/null @@ -1,31 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:18:19 pm ist - -* Plotting option vplot8_1 -r1 7 11 100000 -* Plotting option vplot8_1 -r5 7 3 2000 -V_u5 3 6 0 -r6 2 0 2700 -V_u6 5 2 0 -r4 10 0 3000 -V_u2 4 10 0 -r3 7 9 5000 -V_u1 9 1 0 -v1 7 0 dc 15 -r2 11 0 50000 -q2 5 1 6 pnp -q1 1 11 4 npn - -.dc v1 0e-00 15e-00 5e-03 - -* Control Statements -.control -run -plot v(11) -plot v(1) v(4) v(6) v(5) -plot i(V_u5) -plot i(V_u6) -plot i(V_u2) -plot i(V_u1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.pro deleted file mode 100644 index 9c11e90..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 15 April 2013 10:04:33 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.proj deleted file mode 100644 index 1bbfadb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.11.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.sch deleted file mode 100644 index 766b40d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.sch +++ /dev/null @@ -1,295 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 10:18:23 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5150 3800 -$Comp -L VPLOT8_1 U4 -U 1 1 516C2F31 -P 5150 4100 -F 0 "U4" H 5000 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 5300 4200 50 0000 C CNN - 1 5150 4100 - -1 0 0 1 -$EndComp -Wire Wire Line - 7350 3200 6700 3200 -Connection ~ 4600 1600 -Wire Wire Line - 3350 3150 3350 1600 -Wire Wire Line - 3350 1600 7650 1600 -Wire Wire Line - 4600 5600 4600 4950 -Connection ~ 5750 1600 -Wire Wire Line - 4600 1600 4600 2100 -Wire Wire Line - 5450 3800 4600 3800 -Connection ~ 5750 3400 -Wire Wire Line - 6700 3200 6700 3400 -Wire Wire Line - 6700 3400 5750 3400 -Wire Wire Line - 7650 2100 7650 2250 -Wire Wire Line - 7650 3400 7650 3700 -Wire Wire Line - 5750 4900 5750 5100 -Wire Wire Line - 5750 2750 5750 2600 -Wire Wire Line - 5750 3600 5750 3250 -Wire Wire Line - 5750 4000 5750 4400 -Wire Wire Line - 7650 4200 7650 4350 -Wire Wire Line - 7650 4850 7650 5600 -Connection ~ 7650 5600 -Wire Wire Line - 7650 3000 7650 2750 -Wire Wire Line - 5750 1600 5750 2100 -Wire Wire Line - 4600 4450 4600 2600 -Connection ~ 4600 3800 -Wire Wire Line - 6450 5600 6450 5900 -Connection ~ 6450 5600 -Wire Wire Line - 3350 4050 3350 5600 -Wire Wire Line - 3350 5600 7650 5600 -Connection ~ 4600 5600 -Connection ~ 6450 5750 -Connection ~ 5750 3500 -Connection ~ 5750 4250 -Connection ~ 7650 2900 -Connection ~ 7650 3550 -Connection ~ 5750 5600 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C2ECC -P 6450 5750 -F 0 "#FLG01" H 6450 6020 30 0001 C CNN -F 1 "PWR_FLAG" H 6450 5980 30 0000 C CNN - 1 6450 5750 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C2EBF -P 6450 5900 -F 0 "#PWR02" H 6450 5900 30 0001 C CNN -F 1 "GND" H 6450 5830 30 0001 C CNN - 1 6450 5900 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516C2DFD -P 4600 2350 -F 0 "R1" V 4680 2350 50 0000 C CNN -F 1 "100000" V 4600 2350 50 0000 C CNN - 1 4600 2350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 3 1 516C2DD6 -P 7950 2900 -F 0 "U3" H 7800 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 8100 3000 50 0000 C CNN - 3 7950 2900 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 4 1 516C2DD0 -P 7950 3550 -F 0 "U3" H 7800 3650 50 0000 C CNN -F 1 "VPLOT8_1" H 8100 3650 50 0000 C CNN - 4 7950 3550 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 2 1 516C2DCC -P 6050 4250 -F 0 "U3" H 5900 4350 50 0000 C CNN -F 1 "VPLOT8_1" H 6200 4350 50 0000 C CNN - 2 6050 4250 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516C2DC4 -P 6050 3500 -F 0 "U3" H 5900 3600 50 0000 C CNN -F 1 "VPLOT8_1" H 6200 3600 50 0000 C CNN - 1 6050 3500 - 0 1 1 0 -$EndComp -$Comp -L R R5 -U 1 1 516C2D81 -P 7650 1850 -F 0 "R5" V 7730 1850 50 0000 C CNN -F 1 "2000" V 7650 1850 50 0000 C CNN - 1 7650 1850 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U5 -U 1 1 516C2D75 -P 7650 2500 -F 0 "U5" H 7500 2600 50 0000 C CNN -F 1 "IPLOT" H 7800 2600 50 0000 C CNN - 1 7650 2500 - 0 1 1 0 -$EndComp -$Comp -L R R6 -U 1 1 516C2D45 -P 7650 4600 -F 0 "R6" V 7730 4600 50 0000 C CNN -F 1 "2700" V 7650 4600 50 0000 C CNN - 1 7650 4600 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U6 -U 1 1 516C2D2F -P 7650 3950 -F 0 "U6" H 7500 4050 50 0000 C CNN -F 1 "IPLOT" H 7800 4050 50 0000 C CNN - 1 7650 3950 - 0 1 1 0 -$EndComp -$Comp -L R R4 -U 1 1 516C2CD2 -P 5750 5350 -F 0 "R4" V 5830 5350 50 0000 C CNN -F 1 "3000" V 5750 5350 50 0000 C CNN - 1 5750 5350 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C2CC9 -P 5750 4650 -F 0 "U2" H 5600 4750 50 0000 C CNN -F 1 "IPLOT" H 5900 4750 50 0000 C CNN - 1 5750 4650 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 516C2CA0 -P 5750 2350 -F 0 "R3" V 5830 2350 50 0000 C CNN -F 1 "5000" V 5750 2350 50 0000 C CNN - 1 5750 2350 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516C2C8D -P 5750 3000 -F 0 "U1" H 5600 3100 50 0000 C CNN -F 1 "IPLOT" H 5900 3100 50 0000 C CNN - 1 5750 3000 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C2C6F -P 3350 3600 -F 0 "v1" H 3150 3700 60 0000 C CNN -F 1 "DC" H 3150 3550 60 0000 C CNN -F 2 "R1" H 3050 3600 60 0000 C CNN - 1 3350 3600 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516C2C49 -P 4600 4700 -F 0 "R2" V 4680 4700 50 0000 C CNN -F 1 "50000" V 4600 4700 50 0000 C CNN - 1 4600 4700 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q2 -U 1 1 516C2C3A -P 7550 3200 -F 0 "Q2" H 7550 3050 60 0000 R CNN -F 1 "PNP" H 7550 3350 60 0000 R CNN - 1 7550 3200 - 1 0 0 1 -$EndComp -$Comp -L NPN Q1 -U 1 1 516C2C30 -P 5650 3800 -F 0 "Q1" H 5650 3650 50 0000 R CNN -F 1 "NPN" H 5650 3950 50 0000 R CNN - 1 5650 3800 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/analysis deleted file mode 100644 index aa8d005..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v3 0e-00 5e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.bak deleted file mode 100644 index e34974d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.bak +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:09:27 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.lib deleted file mode 100644 index b975094..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:31:57 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.bak deleted file mode 100644 index 99334cc..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.bak +++ /dev/null @@ -1,207 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:09:27 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.12-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 4900 3850 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CE3EB -P 4900 3850 -F 0 "#FLG01" H 4900 3945 30 0001 C CNN -F 1 "PWR_FLAG" H 4900 4030 30 0000 C CNN - 1 4900 3850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3850 4950 3850 3850 -Wire Wire Line - 6650 4100 6650 5950 -Wire Wire Line - 5350 3400 5350 3450 -Wire Wire Line - 3850 5850 3850 5950 -Wire Wire Line - 3850 5950 6650 5950 -Connection ~ 5050 3850 -Wire Wire Line - 4700 3850 5050 3850 -Wire Wire Line - 5700 4100 5350 4100 -Connection ~ 5350 4100 -Connection ~ 6500 4100 -Wire Wire Line - 6500 2550 5350 2550 -Wire Wire Line - 5350 2550 5350 3000 -Wire Wire Line - 5350 4900 5350 4600 -Wire Wire Line - 5350 5300 5350 5850 -Wire Wire Line - 5350 5850 6500 5850 -Wire Wire Line - 6750 4100 6200 4100 -Connection ~ 6650 4100 -Wire Wire Line - 3850 3850 4200 3850 -Wire Wire Line - 5050 5100 5050 3200 -Wire Wire Line - 5350 4100 5350 3950 -Wire Wire Line - 6500 4950 6500 3450 -$Comp -L IPLOT U1 -U 1 1 516C3068 -P 5350 3700 -F 0 "U1" H 5200 3800 50 0000 C CNN -F 1 "IPLOT" H 5500 3800 50 0000 C CNN - 1 5350 3700 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C304B -P 5350 4350 -F 0 "U2" H 5200 4450 50 0000 C CNN -F 1 "IPLOT" H 5500 4450 50 0000 C CNN - 1 5350 4350 - 0 1 1 0 -$EndComp -$Comp -L DC v3 -U 1 1 5166EE0B -P 3850 5400 -F 0 "v3" H 3650 5500 60 0000 C CNN -F 1 "5V" H 3650 5350 60 0000 C CNN -F 2 "R1" H 3550 5400 60 0000 C CNN - 1 3850 5400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5166ED91 -P 4450 3850 -F 0 "R2" V 4530 3850 50 0000 C CNN -F 1 "10000" V 4450 3850 50 0000 C CNN - 1 4450 3850 - 0 -1 -1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 5166ED50 -P 6650 4100 -F 0 "#FLG02" H 6650 4195 30 0001 C CNN -F 1 "PWR_FLAG" H 6650 4280 30 0000 C CNN - 1 6650 4100 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 5166ED33 -P 6750 4100 -F 0 "#PWR03" H 6750 4100 30 0001 C CNN -F 1 "GND" H 6750 4030 30 0001 C CNN - 1 6750 4100 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166ED03 -P 5950 4100 -F 0 "R1" V 6030 4100 50 0000 C CNN -F 1 "1000" V 5950 4100 50 0000 C CNN - 1 5950 4100 - 0 -1 -1 0 -$EndComp -$Comp -L DC v2 -U 1 1 5166ECC4 -P 6500 5400 -F 0 "v2" H 6300 5500 60 0000 C CNN -F 1 "5V" H 6300 5350 60 0000 C CNN -F 2 "R1" H 6200 5400 60 0000 C CNN - 1 6500 5400 - -1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166EC91 -P 6500 3000 -F 0 "v1" H 6300 3100 60 0000 C CNN -F 1 "5V" H 6300 2950 60 0000 C CNN -F 2 "R1" H 6200 3000 60 0000 C CNN - 1 6500 3000 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q2 -U 1 1 5166EC64 -P 5250 5100 -F 0 "Q2" H 5250 4950 60 0000 R CNN -F 1 "PNP" H 5250 5250 60 0000 R CNN - 1 5250 5100 - 1 0 0 1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166EC56 -P 5250 3200 -F 0 "Q1" H 5250 3050 50 0000 R CNN -F 1 "NPN" H 5250 3350 50 0000 R CNN - 1 5250 3200 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir deleted file mode 100644 index 1961478..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir +++ /dev/null @@ -1,18 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:31:53 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U3 5 1 IPLOT -U1 3 8 IPLOT -U2 1 7 IPLOT -v3 4 0 5V -R2 4 2 10000 -R1 5 0 1000 -v2 0 6 5V -v1 3 0 5V -Q2 7 2 6 PNP -Q1 1 2 8 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.ckt deleted file mode 100644 index 2283488..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.ckt +++ /dev/null @@ -1,18 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:31:53 pm ist - -V_u3 5 1 0 -V_u1 3 8 0 -V_u2 1 7 0 -v3 4 0 5v -r2 4 2 10000 -r1 5 0 1000 -v2 0 6 5v -v1 3 0 5v -q2 6 2 7 pnp -q1 8 2 1 npn - -.dc v3 0e-00 5e-00 1e-00 -.plot i(V_u3) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.out deleted file mode 100644 index 61a3934..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.out +++ /dev/null @@ -1,23 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:31:53 pm ist - -V_u3 5 1 0 -V_u1 3 8 0 -V_u2 1 7 0 -v3 4 0 5v -r2 4 2 10000 -r1 5 0 1000 -v2 0 6 5v -v1 3 0 5v -q2 6 2 7 pnp -q1 8 2 1 npn - -.dc v3 0e-00 5e-00 1e-00 - -* Control Statements -.control -run -plot i(V_u3) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.pro deleted file mode 100644 index d4fedff..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.pro +++ /dev/null @@ -1,84 +0,0 @@ -update=Monday 15 April 2013 10:21:09 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice -LibName41=/home/holy/OSCAD/library/analogSpice -LibName42=/home/holy/OSCAD/library/analogXSpice -LibName43=/home/holy/OSCAD/library/convergenceAidSpice -LibName44=/home/holy/OSCAD/library/converterSpice -LibName45=/home/holy/OSCAD/library/digitalSpice -LibName46=/home/holy/OSCAD/library/digitalXSpice -LibName47=/home/holy/OSCAD/library/linearSpice -LibName48=/home/holy/OSCAD/library/measurementSpice -LibName49=/home/holy/OSCAD/library/portSpice -LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.proj deleted file mode 100644 index cf8b515..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.12.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.sch deleted file mode 100644 index a133513..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.sch +++ /dev/null @@ -1,222 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 01:31:57 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.12-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5350 4000 -Connection ~ 6300 4100 -Wire Wire Line - 6300 4350 6300 4100 -Wire Wire Line - 5350 3400 5350 4100 -Wire Wire Line - 4950 2500 4950 2550 -Wire Wire Line - 4950 2550 6500 2550 -Wire Wire Line - 6500 4950 6500 3450 -Wire Wire Line - 5050 5100 5050 3200 -Wire Wire Line - 4200 3850 3850 3850 -Connection ~ 6650 4100 -Wire Wire Line - 6750 4100 6200 4100 -Wire Wire Line - 6500 5850 5350 5850 -Wire Wire Line - 5350 5850 5350 5300 -Wire Wire Line - 5350 4900 5350 4600 -Connection ~ 6500 4100 -Connection ~ 5350 4100 -Wire Wire Line - 4700 3850 5050 3850 -Connection ~ 5050 3850 -Wire Wire Line - 3850 5950 6650 5950 -Wire Wire Line - 3850 5950 3850 5850 -Wire Wire Line - 6650 5950 6650 4100 -Wire Wire Line - 3850 3850 3850 4950 -Connection ~ 4900 3850 -Wire Wire Line - 4950 3000 5350 3000 -Wire Wire Line - 5850 4000 5850 4350 -Wire Wire Line - 5850 4350 5800 4350 -$Comp -L IPLOT U3 -U 1 1 51909DB6 -P 5600 4000 -F 0 "U3" H 5450 4100 50 0000 C CNN -F 1 "IPLOT" H 5750 4100 50 0000 C CNN - 1 5600 4000 - -1 0 0 1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CE3EB -P 4900 3850 -F 0 "#FLG01" H 4900 3945 30 0001 C CNN -F 1 "PWR_FLAG" H 4900 4030 30 0000 C CNN - 1 4900 3850 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516C3068 -P 4950 2750 -F 0 "U1" H 4800 2850 50 0000 C CNN -F 1 "IPLOT" H 5100 2850 50 0000 C CNN - 1 4950 2750 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C304B -P 5350 4350 -F 0 "U2" H 5200 4450 50 0000 C CNN -F 1 "IPLOT" H 5500 4450 50 0000 C CNN - 1 5350 4350 - 0 1 1 0 -$EndComp -$Comp -L DC v3 -U 1 1 5166EE0B -P 3850 5400 -F 0 "v3" H 3650 5500 60 0000 C CNN -F 1 "5V" H 3650 5350 60 0000 C CNN -F 2 "R1" H 3550 5400 60 0000 C CNN - 1 3850 5400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5166ED91 -P 4450 3850 -F 0 "R2" V 4530 3850 50 0000 C CNN -F 1 "10000" V 4450 3850 50 0000 C CNN - 1 4450 3850 - 0 -1 -1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 5166ED50 -P 6650 4100 -F 0 "#FLG02" H 6650 4195 30 0001 C CNN -F 1 "PWR_FLAG" H 6650 4280 30 0000 C CNN - 1 6650 4100 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 5166ED33 -P 6750 4100 -F 0 "#PWR03" H 6750 4100 30 0001 C CNN -F 1 "GND" H 6750 4030 30 0001 C CNN - 1 6750 4100 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166ED03 -P 6050 4350 -F 0 "R1" V 6130 4350 50 0000 C CNN -F 1 "1000" V 6050 4350 50 0000 C CNN - 1 6050 4350 - 0 -1 -1 0 -$EndComp -$Comp -L DC v2 -U 1 1 5166ECC4 -P 6500 5400 -F 0 "v2" H 6300 5500 60 0000 C CNN -F 1 "5V" H 6300 5350 60 0000 C CNN -F 2 "R1" H 6200 5400 60 0000 C CNN - 1 6500 5400 - -1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166EC91 -P 6500 3000 -F 0 "v1" H 6300 3100 60 0000 C CNN -F 1 "5V" H 6300 2950 60 0000 C CNN -F 2 "R1" H 6200 3000 60 0000 C CNN - 1 6500 3000 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q2 -U 1 1 5166EC64 -P 5250 5100 -F 0 "Q2" H 5250 4950 60 0000 R CNN -F 1 "PNP" H 5250 5250 60 0000 R CNN - 1 5250 5100 - 1 0 0 1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166EC56 -P 5250 3200 -F 0 "Q1" H 5250 3050 50 0000 R CNN -F 1 "NPN" H 5250 3350 50 0000 R CNN - 1 5250 3200 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis deleted file mode 100644 index 11459c7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 12e-00 12e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib deleted file mode 100644 index efa56af..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:31:21 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak deleted file mode 100644 index db1ff38..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak +++ /dev/null @@ -1,210 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:16:49 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.10-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5050 3350 4200 3350 -Wire Wire Line - 6850 2850 6850 1300 -Wire Wire Line - 6850 1300 4200 1300 -Wire Wire Line - 4200 1300 4200 2200 -Connection ~ 4200 3350 -Wire Wire Line - 4200 2700 4200 3800 -Wire Wire Line - 6850 3750 6850 5150 -Wire Wire Line - 5350 3550 5350 3750 -Wire Wire Line - 5350 2050 5350 2250 -Wire Wire Line - 5350 1550 5350 1300 -Wire Wire Line - 5350 2750 5350 3150 -Wire Wire Line - 5350 4250 5350 4400 -Wire Wire Line - 4200 4300 4200 5150 -Wire Wire Line - 4200 5150 6850 5150 -Connection ~ 5350 5150 -Connection ~ 5350 1300 -Wire Wire Line - 5350 5650 5350 4900 -Connection ~ 5350 5500 -Connection ~ 5350 3650 -Connection ~ 5350 2900 -Connection ~ 5000 3350 -$Comp -L VPLOT8_1 U2 -U 3 1 516C2B0C -P 5650 3650 -F 0 "U2" H 5500 3750 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3750 50 0000 C CNN - 3 5650 3650 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516C2B05 -P 5650 2900 -F 0 "U2" H 5500 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3000 50 0000 C CNN - 2 5650 2900 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516C2AFE -P 5000 3050 -F 0 "U2" H 4850 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN - 1 5000 3050 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C2AB7 -P 5350 5500 -F 0 "#FLG01" H 5350 5770 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN - 1 5350 5500 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C2AAB -P 5350 5650 -F 0 "#PWR02" H 5350 5650 30 0001 C CNN -F 1 "GND" H 5350 5580 30 0001 C CNN - 1 5350 5650 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516C2A3E -P 4200 4050 -F 0 "R2" V 4280 4050 50 0000 C CNN -F 1 "50000" V 4200 4050 50 0000 C CNN - 1 4200 4050 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516C2A13 -P 4200 2450 -F 0 "R1" V 4280 2450 50 0000 C CNN -F 1 "100000" V 4200 2450 50 0000 C CNN - 1 4200 2450 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 516C29D9 -P 5350 4650 -F 0 "R4" V 5430 4650 50 0000 C CNN -F 1 "3000" V 5350 4650 50 0000 C CNN - 1 5350 4650 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516C29CD -P 5350 4000 -F 0 "U4" H 5200 4100 50 0000 C CNN -F 1 "IPLOT" H 5500 4100 50 0000 C CNN - 1 5350 4000 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C296E -P 6850 3300 -F 0 "v1" H 6650 3400 60 0000 C CNN -F 1 "15V" H 6650 3250 60 0000 C CNN -F 2 "R1" H 6550 3300 60 0000 C CNN - 1 6850 3300 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516C2958 -P 5350 2500 -F 0 "U3" H 5200 2600 50 0000 C CNN -F 1 "IPLOT" H 5500 2600 50 0000 C CNN - 1 5350 2500 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 516C293A -P 5350 1800 -F 0 "R3" V 5430 1800 50 0000 C CNN -F 1 "5000" V 5350 1800 50 0000 C CNN - 1 5350 1800 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 516C2934 -P 5250 3350 -F 0 "Q1" H 5250 3200 50 0000 R CNN -F 1 "NPN" H 5250 3500 50 0000 R CNN - 1 5250 3350 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir deleted file mode 100644 index 2015439..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir +++ /dev/null @@ -1,17 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 11:31:17 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -R1 5 7 80000 -U2 7 2 1 VPLOT8_1 -R2 7 0 40000 -R4 4 0 3300 -U4 1 4 IPLOT -v1 5 0 12V -U3 6 2 IPLOT -R3 5 6 4000 -Q1 1 7 2 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt deleted file mode 100644 index cc4fac4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 11:31:17 am ist - -r1 5 7 80000 -* Plotting option vplot8_1 -r2 7 0 40000 -r4 4 0 3300 -V_u4 1 4 0 -v1 5 0 12v -V_u3 6 2 0 -r3 5 6 4000 -q1 2 7 1 npn - -.dc v1 0e-00 12e-00 12e-03 -.plot v(7) v(2) v(1) -.plot i(V_u4) -.plot i(V_u3) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out deleted file mode 100644 index d5ce68a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 11:31:17 am ist - -r1 5 7 80000 -* Plotting option vplot8_1 -r2 7 0 40000 -r4 4 0 3300 -V_u4 1 4 0 -v1 5 0 12v -V_u3 6 2 0 -r3 5 6 4000 -q1 2 7 1 npn - -.dc v1 0e-00 12e-00 12e-03 - -* Control Statements -.control -run -plot v(7) v(2) v(1) -plot i(V_u4) -plot i(V_u3) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro deleted file mode 100644 index 9ed7c71..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 11:12:52 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj deleted file mode 100644 index a04af44..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.13.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch deleted file mode 100644 index d0ef771..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch +++ /dev/null @@ -1,209 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:31:21 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L R R1 -U 1 1 516CE8DE -P 4200 2450 -F 0 "R1" V 4280 2450 50 0000 C CNN -F 1 "80000" V 4200 2450 50 0000 C CNN - 1 4200 2450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5050 3350 4200 3350 -Wire Wire Line - 6850 2850 6850 1300 -Wire Wire Line - 6850 1300 4200 1300 -Wire Wire Line - 4200 1300 4200 2200 -Connection ~ 4200 3350 -Wire Wire Line - 4200 2700 4200 3800 -Wire Wire Line - 6850 3750 6850 5150 -Wire Wire Line - 5350 3550 5350 3750 -Wire Wire Line - 5350 2050 5350 2250 -Wire Wire Line - 5350 1550 5350 1300 -Wire Wire Line - 5350 2750 5350 3150 -Wire Wire Line - 5350 4250 5350 4400 -Wire Wire Line - 4200 4300 4200 5150 -Wire Wire Line - 4200 5150 6850 5150 -Connection ~ 5350 5150 -Connection ~ 5350 1300 -Wire Wire Line - 5350 5650 5350 4900 -Connection ~ 5350 5500 -Connection ~ 5350 3650 -Connection ~ 5350 2900 -Connection ~ 5000 3350 -$Comp -L VPLOT8_1 U2 -U 3 1 516C2B0C -P 5650 3650 -F 0 "U2" H 5500 3750 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3750 50 0000 C CNN - 3 5650 3650 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516C2B05 -P 5650 2900 -F 0 "U2" H 5500 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3000 50 0000 C CNN - 2 5650 2900 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516C2AFE -P 5000 3050 -F 0 "U2" H 4850 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN - 1 5000 3050 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C2AB7 -P 5350 5500 -F 0 "#FLG01" H 5350 5770 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN - 1 5350 5500 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C2AAB -P 5350 5650 -F 0 "#PWR02" H 5350 5650 30 0001 C CNN -F 1 "GND" H 5350 5580 30 0001 C CNN - 1 5350 5650 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516C2A3E -P 4200 4050 -F 0 "R2" V 4280 4050 50 0000 C CNN -F 1 "40000" V 4200 4050 50 0000 C CNN - 1 4200 4050 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 516C29D9 -P 5350 4650 -F 0 "R4" V 5430 4650 50 0000 C CNN -F 1 "3300" V 5350 4650 50 0000 C CNN - 1 5350 4650 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516C29CD -P 5350 4000 -F 0 "U4" H 5200 4100 50 0000 C CNN -F 1 "IPLOT" H 5500 4100 50 0000 C CNN - 1 5350 4000 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C296E -P 6850 3300 -F 0 "v1" H 6650 3400 60 0000 C CNN -F 1 "12V" H 6650 3250 60 0000 C CNN -F 2 "R1" H 6550 3300 60 0000 C CNN - 1 6850 3300 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516C2958 -P 5350 2500 -F 0 "U3" H 5200 2600 50 0000 C CNN -F 1 "IPLOT" H 5500 2600 50 0000 C CNN - 1 5350 2500 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 516C293A -P 5350 1800 -F 0 "R3" V 5430 1800 50 0000 C CNN -F 1 "4000" V 5350 1800 50 0000 C CNN - 1 5350 1800 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 516C2934 -P 5250 3350 -F 0 "Q1" H 5250 3200 50 0000 R CNN -F 1 "NPN" H 5250 3500 50 0000 R CNN - 1 5250 3350 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/analysis deleted file mode 100644 index 6295799..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 5e-00 100e-00 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14-cache.lib deleted file mode 100644 index 4090ea9..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14-cache.lib +++ /dev/null @@ -1,131 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:35:55 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# pulse -# -DEF pulse v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "pulse" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -25 -450 501 928 871 0 1 0 N -50 50 0 50 -A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 -A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 -A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 -A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 -A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.bak deleted file mode 100644 index 850e6be..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.bak +++ /dev/null @@ -1,227 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:42:22 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example3.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5000 5750 5000 4300 -Connection ~ 4550 3050 -Connection ~ 4650 3050 -Wire Wire Line - 4300 3050 4700 3050 -Wire Wire Line - 3800 3050 3700 3050 -Connection ~ 5000 2650 -Wire Wire Line - 5900 2550 5900 1050 -Wire Wire Line - 5000 3800 5000 3250 -Wire Wire Line - 5000 2050 5000 1550 -Connection ~ 5000 5450 -Wire Wire Line - 5900 1050 5000 1050 -Wire Wire Line - 2900 3050 3200 3050 -Wire Wire Line - 2900 5200 2900 5450 -Connection ~ 5000 5600 -Connection ~ 5000 3450 -Wire Wire Line - 5000 2550 5000 2850 -Wire Wire Line - 5900 3450 5900 5450 -Wire Wire Line - 2900 3950 2900 4300 -Wire Wire Line - 5900 5450 2900 5450 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CEB5B -P 4550 3050 -F 0 "#FLG01" H 4550 3145 30 0001 C CNN -F 1 "PWR_FLAG" H 4550 3230 30 0000 C CNN - 1 4550 3050 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U5 -U 1 1 516CEB46 -P 4650 3350 -F 0 "U5" H 4500 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 4800 3450 50 0000 C CNN - 1 4650 3350 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CEB0E -P 4050 3050 -F 0 "U4" H 3900 3150 50 0000 C CNN -F 1 "IPLOT" H 4200 3150 50 0000 C CNN - 1 4050 3050 - -1 0 0 1 -$EndComp -$Comp -L R R2 -U 1 1 516CEAFA -P 3450 3050 -F 0 "R2" V 3530 3050 50 0000 C CNN -F 1 "100000" V 3450 3050 50 0000 C CNN - 1 3450 3050 - 0 1 1 0 -$EndComp -$Comp -L PULSE v3 -U 1 1 516CEAC5 -P 2900 3500 -F 0 "v3" H 2700 3600 60 0000 C CNN -F 1 "PULSE" H 2700 3450 60 0000 C CNN -F 2 "R1" H 2600 3500 60 0000 C CNN - 1 2900 3500 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516BD8B9 -P 5300 2650 -F 0 "U3" H 5150 2750 50 0000 C CNN -F 1 "VPLOT8_1" H 5450 2750 50 0000 C CNN - 1 5300 2650 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 2 1 516BD8AC -P 5300 3450 -F 0 "U3" H 5150 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5450 3550 50 0000 C CNN - 2 5300 3450 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516BD643 -P 5000 4050 -F 0 "U2" H 4850 4150 50 0000 C CNN -F 1 "IPLOT" H 5150 4150 50 0000 C CNN - 1 5000 4050 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516BD5F9 -P 5000 2300 -F 0 "U1" H 4850 2400 50 0000 C CNN -F 1 "IPLOT" H 5150 2400 50 0000 C CNN - 1 5000 2300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 5166BF83 -P 5000 5600 -F 0 "#FLG02" H 5000 5695 30 0001 C CNN -F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN - 1 5000 5600 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 5166BF64 -P 5000 5750 -F 0 "#PWR03" H 5000 5750 30 0001 C CNN -F 1 "GND" H 5000 5680 30 0001 C CNN - 1 5000 5750 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166BEE6 -P 2900 4750 -F 0 "v1" H 2700 4850 60 0000 C CNN -F 1 "3V" H 2700 4700 60 0000 C CNN -F 2 "R1" H 2600 4750 60 0000 C CNN - 1 2900 4750 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5166BED7 -P 5900 3000 -F 0 "v2" H 5700 3100 60 0000 C CNN -F 1 "10V" H 5700 2950 60 0000 C CNN -F 2 "R1" H 5600 3000 60 0000 C CNN - 1 5900 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166BE8E -P 5000 1300 -F 0 "R1" V 5080 1300 50 0000 C CNN -F 1 "3000" V 5000 1300 50 0000 C CNN - 1 5000 1300 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166BE53 -P 4900 3050 -F 0 "Q1" H 4900 2900 50 0000 R CNN -F 1 "NPN" H 4900 3200 50 0000 R CNN - 1 4900 3050 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir deleted file mode 100644 index e9d15ad..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir +++ /dev/null @@ -1,20 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:35:51 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U6 8 VPLOT8_1 -U5 9 VPLOT8_1 -U4 9 1 IPLOT -R2 1 8 100000 -v3 8 4 PULSE -U3 2 3 VPLOT8_1 -U2 3 0 IPLOT -U1 7 2 IPLOT -v1 4 0 3V -v2 6 0 10V -R1 6 7 3000 -Q1 3 9 2 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.ckt deleted file mode 100644 index b1e99c7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.ckt +++ /dev/null @@ -1,23 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:35:51 pm ist - -* Plotting option vplot8_1 -* Plotting option vplot8_1 -V_u4 9 1 0 -r2 1 8 100000 -v3 8 4 pulse(0 1 0 0 0 2 ) -* Plotting option vplot8_1 -V_u2 3 0 0 -V_u1 7 2 0 -v1 4 0 3v -v2 6 0 10v -r1 6 7 3000 -q1 2 9 3 npn - -.tran 5e-00 100e-00 0e-00 -.plot v(8) -.plot v(9) -.plot i(V_u4) -.plot v(2) v(3) -.plot i(V_u2) -.plot i(V_u1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.out deleted file mode 100644 index be85aa9..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.out +++ /dev/null @@ -1,28 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:35:51 pm ist - -* Plotting option vplot8_1 -* Plotting option vplot8_1 -V_u4 9 1 0 -r2 1 8 100000 -v3 8 4 pulse(0 1 0 0 0 2 ) -* Plotting option vplot8_1 -V_u2 3 0 0 -V_u1 7 2 0 -v1 4 0 3v -v2 6 0 10v -r1 6 7 3000 -q1 2 9 3 npn - -.tran 5e-00 100e-00 0e-00 - -* Control Statements -.control -run -plot v(8) -plot v(9) -plot i(V_u4) -plot v(2) v(3) -plot i(V_u2) -plot i(V_u1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.pro deleted file mode 100644 index b5f9bd7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 11:34:19 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.proj deleted file mode 100644 index 2c95037..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.14.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.sch deleted file mode 100644 index 4f4f51a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.sch +++ /dev/null @@ -1,236 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 01:35:55 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 3050 3050 -$Comp -L VPLOT8_1 U6 -U 1 1 51909ECA -P 3050 3350 -F 0 "U6" H 2900 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 3200 3450 50 0000 C CNN - 1 3050 3350 - -1 0 0 1 -$EndComp -Wire Wire Line - 5000 5750 5000 4300 -Connection ~ 4550 3050 -Connection ~ 4650 3050 -Wire Wire Line - 4300 3050 4700 3050 -Wire Wire Line - 3800 3050 3700 3050 -Connection ~ 5000 2650 -Wire Wire Line - 5900 2550 5900 1050 -Wire Wire Line - 5000 3800 5000 3250 -Wire Wire Line - 5000 2050 5000 1550 -Connection ~ 5000 5450 -Wire Wire Line - 5900 1050 5000 1050 -Wire Wire Line - 2900 3050 3200 3050 -Wire Wire Line - 2900 5200 2900 5450 -Connection ~ 5000 5600 -Connection ~ 5000 3450 -Wire Wire Line - 5000 2550 5000 2850 -Wire Wire Line - 5900 3450 5900 5450 -Wire Wire Line - 2900 3950 2900 4300 -Wire Wire Line - 5900 5450 2900 5450 -$Comp -L PWR_FLAG #FLG1 -U 1 1 516CEB5B -P 4550 3050 -F 0 "#FLG1" H 4550 3145 30 0001 C CNN -F 1 "PWR_FLAG" H 4550 3230 30 0000 C CNN - 1 4550 3050 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U5 -U 1 1 516CEB46 -P 4650 3350 -F 0 "U5" H 4500 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 4800 3450 50 0000 C CNN - 1 4650 3350 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CEB0E -P 4050 3050 -F 0 "U4" H 3900 3150 50 0000 C CNN -F 1 "IPLOT" H 4200 3150 50 0000 C CNN - 1 4050 3050 - -1 0 0 1 -$EndComp -$Comp -L R R2 -U 1 1 516CEAFA -P 3450 3050 -F 0 "R2" V 3530 3050 50 0000 C CNN -F 1 "100000" V 3450 3050 50 0000 C CNN - 1 3450 3050 - 0 1 1 0 -$EndComp -$Comp -L PULSE v3 -U 1 1 516CEAC5 -P 2900 3500 -F 0 "v3" H 2700 3600 60 0000 C CNN -F 1 "PULSE" H 2700 3450 60 0000 C CNN -F 2 "R1" H 2600 3500 60 0000 C CNN - 1 2900 3500 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516BD8B9 -P 5300 2650 -F 0 "U3" H 5150 2750 50 0000 C CNN -F 1 "VPLOT8_1" H 5450 2750 50 0000 C CNN - 1 5300 2650 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 2 1 516BD8AC -P 5300 3450 -F 0 "U3" H 5150 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5450 3550 50 0000 C CNN - 2 5300 3450 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516BD643 -P 5000 4050 -F 0 "U2" H 4850 4150 50 0000 C CNN -F 1 "IPLOT" H 5150 4150 50 0000 C CNN - 1 5000 4050 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516BD5F9 -P 5000 2300 -F 0 "U1" H 4850 2400 50 0000 C CNN -F 1 "IPLOT" H 5150 2400 50 0000 C CNN - 1 5000 2300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG2 -U 1 1 5166BF83 -P 5000 5600 -F 0 "#FLG2" H 5000 5695 30 0001 C CNN -F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN - 1 5000 5600 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR1 -U 1 1 5166BF64 -P 5000 5750 -F 0 "#PWR1" H 5000 5750 30 0001 C CNN -F 1 "GND" H 5000 5680 30 0001 C CNN - 1 5000 5750 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166BEE6 -P 2900 4750 -F 0 "v1" H 2700 4850 60 0000 C CNN -F 1 "3V" H 2700 4700 60 0000 C CNN -F 2 "R1" H 2600 4750 60 0000 C CNN - 1 2900 4750 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5166BED7 -P 5900 3000 -F 0 "v2" H 5700 3100 60 0000 C CNN -F 1 "10V" H 5700 2950 60 0000 C CNN -F 2 "R1" H 5600 3000 60 0000 C CNN - 1 5900 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166BE8E -P 5000 1300 -F 0 "R1" V 5080 1300 50 0000 C CNN -F 1 "3000" V 5000 1300 50 0000 C CNN - 1 5000 1300 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166BE53 -P 4900 3050 -F 0 "Q1" H 4900 2900 50 0000 R CNN -F 1 "NPN" H 4900 3200 50 0000 R CNN - 1 4900 3050 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/analysis deleted file mode 100644 index 05351e0..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 1e-00 10e-00 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16-cache.lib deleted file mode 100644 index e8eb963..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16-cache.lib +++ /dev/null @@ -1,131 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 12:27:16 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# pulse -# -DEF pulse v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "pulse" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -25 -450 501 928 871 0 1 0 N -50 50 0 50 -A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 -A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 -A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 -A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 -A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.bak deleted file mode 100644 index 8773c0d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.bak +++ /dev/null @@ -1,221 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 12:24:14 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.3-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5450 4850 5450 5350 -Connection ~ 4300 5050 -Wire Wire Line - 4300 5050 4300 3300 -Wire Wire Line - 6650 5050 3500 5050 -Connection ~ 5450 5050 -Wire Wire Line - 6650 5050 6650 4450 -Wire Wire Line - 3500 5050 3500 4450 -Wire Wire Line - 5450 3700 5450 3500 -Wire Wire Line - 5450 2950 5450 3100 -Wire Wire Line - 5450 2300 5450 2450 -Connection ~ 5450 3050 -Connection ~ 5450 3600 -Wire Wire Line - 5450 1800 6650 1800 -Wire Wire Line - 6650 1800 6650 3550 -Wire Wire Line - 4800 3300 5150 3300 -Connection ~ 5100 3300 -Connection ~ 6650 5050 -Connection ~ 4950 3300 -Connection ~ 5450 5200 -Wire Wire Line - 3500 3550 3500 3050 -Wire Wire Line - 3500 3050 5450 3050 -Wire Wire Line - 5450 4200 5450 4350 -$Comp -L R R1 -U 1 1 516CF523 -P 5450 4600 -F 0 "R1" V 5530 4600 50 0000 C CNN -F 1 "5000" V 5450 4600 50 0000 C CNN - 1 5450 4600 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CE235 -P 4950 3300 -F 0 "#FLG01" H 4950 3570 30 0001 C CNN -F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN - 1 4950 3300 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516CE22C -P 5450 5200 -F 0 "#FLG02" H 5450 5470 30 0001 C CNN -F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN - 1 5450 5200 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516CE20C -P 5450 5350 -F 0 "#PWR03" H 5450 5350 30 0001 C CNN -F 1 "GND" H 5450 5280 30 0001 C CNN - 1 5450 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516CE1D8 -P 5100 3000 -F 0 "U2" H 4950 3100 50 0000 C CNN -F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516CE177 -P 4550 3300 -F 0 "U1" H 4400 3400 50 0000 C CNN -F 1 "IPLOT" H 4700 3400 50 0000 C CNN - 1 4550 3300 - -1 0 0 1 -$EndComp -$Comp -L DC v1 -U 1 1 516CE159 -P 3500 4000 -F 0 "v1" H 3300 4100 60 0000 C CNN -F 1 "5V" H 3300 3950 60 0000 C CNN -F 2 "R1" H 3200 4000 60 0000 C CNN - 1 3500 4000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516CE102 -P 5750 3050 -F 0 "U2" H 5600 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN - 2 5750 3050 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516CE0C0 -P 5450 2050 -F 0 "R2" V 5530 2050 50 0000 C CNN -F 1 "10000" V 5450 2050 50 0000 C CNN - 1 5450 2050 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516CE0B6 -P 5450 2700 -F 0 "U3" H 5300 2800 50 0000 C CNN -F 1 "IPLOT" H 5600 2800 50 0000 C CNN - 1 5450 2700 - 0 1 1 0 -$EndComp -$Comp -L DC v2 -U 1 1 516CE08D -P 6650 4000 -F 0 "v2" H 6450 4100 60 0000 C CNN -F 1 "10V" H 6450 3950 60 0000 C CNN -F 2 "R1" H 6350 4000 60 0000 C CNN - 1 6650 4000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516CE083 -P 5750 3600 -F 0 "U2" H 5600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN - 3 5750 3600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CE07C -P 5450 3950 -F 0 "U4" H 5300 4050 50 0000 C CNN -F 1 "IPLOT" H 5600 4050 50 0000 C CNN - 1 5450 3950 - 0 1 1 0 -$EndComp -$Comp -L NPN Q1 -U 1 1 516CE055 -P 5350 3300 -F 0 "Q1" H 5350 3150 50 0000 R CNN -F 1 "NPN" H 5350 3450 50 0000 R CNN - 1 5350 3300 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir deleted file mode 100644 index e62088b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir +++ /dev/null @@ -1,17 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 12:27:13 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v1 7 0 PULSE -R1 1 0 5000 -U2 2 7 6 VPLOT8_1 -U1 2 0 IPLOT -R2 4 5 10000 -U3 5 7 IPLOT -v2 4 0 10V -U4 6 1 IPLOT -Q1 6 2 7 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.ckt deleted file mode 100644 index 3741239..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.ckt +++ /dev/null @@ -1,18 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 12:27:13 pm ist - -v1 7 0 pulse(0 5 0 0 0 1 2) -r1 1 0 5000 -* Plotting option vplot8_1 -V_u1 2 0 0 -r2 4 5 10000 -V_u3 5 7 0 -v2 4 0 10v -V_u4 6 1 0 -q1 7 2 6 npn - -.tran 1e-00 10e-00 0e-00 -.plot v(2) v(7) v(6) -.plot i(V_u1) -.plot i(V_u3) -.plot i(V_u4) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.out deleted file mode 100644 index 86e4303..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.out +++ /dev/null @@ -1,23 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 12:27:13 pm ist - -v1 7 0 pulse(0 5 0 0 0 1 2) -r1 1 0 5000 -* Plotting option vplot8_1 -V_u1 2 0 0 -r2 4 5 10000 -V_u3 5 7 0 -v2 4 0 10v -V_u4 6 1 0 -q1 7 2 6 npn - -.tran 1e-00 10e-00 0e-00 - -* Control Statements -.control -run -plot v(2) v(7) v(6) -plot i(V_u1) -plot i(V_u3) -plot i(V_u4) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.pro deleted file mode 100644 index ebd9c0e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 12:26:32 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.proj deleted file mode 100644 index 5af6371..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.16.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.sch deleted file mode 100644 index 95e37c9..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.sch +++ /dev/null @@ -1,220 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 12:27:16 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PULSE v1 -U 1 1 516CF62D -P 3500 4000 -F 0 "v1" H 3300 4100 60 0000 C CNN -F 1 "PULSE" H 3300 3950 60 0000 C CNN -F 2 "R1" H 3200 4000 60 0000 C CNN - 1 3500 4000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5450 4850 5450 5350 -Connection ~ 4300 5050 -Wire Wire Line - 4300 5050 4300 3300 -Wire Wire Line - 6650 5050 3500 5050 -Connection ~ 5450 5050 -Wire Wire Line - 6650 5050 6650 4450 -Wire Wire Line - 3500 5050 3500 4450 -Wire Wire Line - 5450 3700 5450 3500 -Wire Wire Line - 5450 2950 5450 3100 -Wire Wire Line - 5450 2300 5450 2450 -Connection ~ 5450 3050 -Connection ~ 5450 3600 -Wire Wire Line - 5450 1800 6650 1800 -Wire Wire Line - 6650 1800 6650 3550 -Wire Wire Line - 4800 3300 5150 3300 -Connection ~ 5100 3300 -Connection ~ 6650 5050 -Connection ~ 4950 3300 -Connection ~ 5450 5200 -Wire Wire Line - 3500 3550 3500 3050 -Wire Wire Line - 3500 3050 5450 3050 -Wire Wire Line - 5450 4200 5450 4350 -$Comp -L R R1 -U 1 1 516CF523 -P 5450 4600 -F 0 "R1" V 5530 4600 50 0000 C CNN -F 1 "5000" V 5450 4600 50 0000 C CNN - 1 5450 4600 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CE235 -P 4950 3300 -F 0 "#FLG01" H 4950 3570 30 0001 C CNN -F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN - 1 4950 3300 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516CE22C -P 5450 5200 -F 0 "#FLG02" H 5450 5470 30 0001 C CNN -F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN - 1 5450 5200 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516CE20C -P 5450 5350 -F 0 "#PWR03" H 5450 5350 30 0001 C CNN -F 1 "GND" H 5450 5280 30 0001 C CNN - 1 5450 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516CE1D8 -P 5100 3000 -F 0 "U2" H 4950 3100 50 0000 C CNN -F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516CE177 -P 4550 3300 -F 0 "U1" H 4400 3400 50 0000 C CNN -F 1 "IPLOT" H 4700 3400 50 0000 C CNN - 1 4550 3300 - -1 0 0 1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516CE102 -P 5750 3050 -F 0 "U2" H 5600 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN - 2 5750 3050 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516CE0C0 -P 5450 2050 -F 0 "R2" V 5530 2050 50 0000 C CNN -F 1 "10000" V 5450 2050 50 0000 C CNN - 1 5450 2050 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516CE0B6 -P 5450 2700 -F 0 "U3" H 5300 2800 50 0000 C CNN -F 1 "IPLOT" H 5600 2800 50 0000 C CNN - 1 5450 2700 - 0 1 1 0 -$EndComp -$Comp -L DC v2 -U 1 1 516CE08D -P 6650 4000 -F 0 "v2" H 6450 4100 60 0000 C CNN -F 1 "10V" H 6450 3950 60 0000 C CNN -F 2 "R1" H 6350 4000 60 0000 C CNN - 1 6650 4000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516CE083 -P 5750 3600 -F 0 "U2" H 5600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN - 3 5750 3600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CE07C -P 5450 3950 -F 0 "U4" H 5300 4050 50 0000 C CNN -F 1 "IPLOT" H 5600 4050 50 0000 C CNN - 1 5450 3950 - 0 1 1 0 -$EndComp -$Comp -L NPN Q1 -U 1 1 516CE055 -P 5350 3300 -F 0 "Q1" H 5350 3150 50 0000 R CNN -F 1 "NPN" H 5350 3450 50 0000 R CNN - 1 5350 3300 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/analysis deleted file mode 100644 index 31f2ad8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 2e-00 2e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.bak deleted file mode 100644 index 646744a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.bak +++ /dev/null @@ -1,107 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Friday 26 April 2013 04:00:58 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# Idc -# -DEF Idc i 0 40 Y Y 1 F N -F0 "i" -200 100 60 H V C CNN -F1 "Idc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.lib deleted file mode 100644 index b92ac3a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.lib +++ /dev/null @@ -1,107 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Friday 26 April 2013 04:23:31 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# Idc -# -DEF Idc i 0 40 Y Y 1 F N -F0 "i" -200 100 60 H V C CNN -F1 "Idc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.bak deleted file mode 100644 index 65ec82c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.bak +++ /dev/null @@ -1,188 +0,0 @@ -EESchema Schematic File Version 2 date Friday 26 April 2013 04:00:58 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.20-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "26 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 6350 3300 6350 2800 -Wire Wire Line - 6350 2800 5950 2800 -Wire Wire Line - 4750 4200 4950 4200 -Wire Wire Line - 5450 4200 5650 4200 -Wire Wire Line - 5950 3300 5950 3650 -Wire Wire Line - 5950 4200 5950 4050 -Connection ~ 5950 5350 -Connection ~ 5950 5450 -Connection ~ 5950 3450 -Connection ~ 5950 4100 -Wire Wire Line - 6350 4200 6350 5350 -Wire Wire Line - 5650 4200 5650 3850 -Connection ~ 5650 3850 -Connection ~ 5650 3950 -Wire Wire Line - 5950 5600 5950 4700 -Wire Wire Line - 6350 5350 5450 5350 -Wire Wire Line - 5450 5350 5450 5100 -Wire Wire Line - 5450 5100 4750 5100 -$Comp -L IDC i1 -U 1 1 517A17EC -P 4750 4650 -F 0 "i1" H 4550 4750 60 0000 C CNN -F 1 "IDC" H 4550 4600 60 0000 C CNN -F 2 "R1" H 4450 4650 60 0000 C CNN - 1 4750 4650 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 517A1753 -P 5950 5350 -F 0 "#FLG01" H 5950 5620 30 0001 C CNN -F 1 "PWR_FLAG" H 5950 5580 30 0000 C CNN - 1 5950 5350 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 517A174B -P 5650 3950 -F 0 "#FLG02" H 5650 4220 30 0001 C CNN -F 1 "PWR_FLAG" H 5650 4180 30 0000 C CNN - 1 5650 3950 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 517A172B -P 5950 4450 -F 0 "U4" H 5800 4550 50 0000 C CNN -F 1 "IPLOT" H 6100 4550 50 0000 C CNN - 1 5950 4450 - 0 -1 -1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 517A1709 -P 5200 4200 -F 0 "U2" H 5050 4300 50 0000 C CNN -F 1 "IPLOT" H 5350 4300 50 0000 C CNN - 1 5200 4200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 517A16C8 -P 5950 3050 -F 0 "U3" H 5800 3150 50 0000 C CNN -F 1 "IPLOT" H 6100 3150 50 0000 C CNN - 1 5950 3050 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 5166CA3C -P 5650 4100 -F 0 "U1" H 5500 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN - 2 5650 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5166C9F3 -P 5650 3450 -F 0 "U1" H 5500 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN - 1 5650 3450 - 0 -1 -1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 5166C87D -P 5950 5600 -F 0 "#PWR03" H 5950 5600 30 0001 C CNN -F 1 "GND" H 5950 5530 30 0001 C CNN - 1 5950 5600 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166C79C -P 6350 3750 -F 0 "v1" H 6150 3850 60 0000 C CNN -F 1 "2" H 6150 3700 60 0000 C CNN -F 2 "R1" H 6050 3750 60 0000 C CNN - 1 6350 3750 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166C72A -P 5850 3850 -F 0 "Q1" H 5850 3700 50 0000 R CNN -F 1 "NPN" H 5850 4000 50 0000 R CNN - 1 5850 3850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir deleted file mode 100644 index 419bc05..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Friday 26 April 2013 03:55:55 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -i1 5 0 IDC -U4 0 1 IPLOT -U2 3 5 IPLOT -U3 4 6 IPLOT -U1 6 1 VPLOT8_1 -v1 4 0 2 -Q1 1 3 6 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.ckt deleted file mode 100644 index a91b990..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: friday 26 april 2013 03:55:55 pm ist -.include npn.lib - -i1 5 0 idc -V_u4 0 1 0 -V_u2 3 5 0 -V_u3 4 6 0 -* Plotting option vplot8_1 -v1 4 0 2 -q1 6 3 1 npn - -.dc v1 0e-00 2e-00 2e-03 -.plot i(V_u4) -.plot i(V_u2) -.plot i(V_u3) -.plot v(6) v(1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.out deleted file mode 100644 index b2caa59..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: friday 26 april 2013 03:55:55 pm ist -.include npn.lib - -i1 5 0 idc -V_u4 0 1 0 -V_u2 3 5 0 -V_u3 4 6 0 -* Plotting option vplot8_1 -v1 4 0 2 -q1 6 3 1 npn - -.dc v1 0e-00 2e-00 2e-03 - -* Control Statements -.control -run -plot i(V_u4) -plot i(V_u2) -plot i(V_u3) -plot v(6) v(1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.pro deleted file mode 100644 index d4ac2ef..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 12:53:24 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.proj deleted file mode 100644 index 231747a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.20.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.sch deleted file mode 100644 index a694eb1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.sch +++ /dev/null @@ -1,183 +0,0 @@ -EESchema Schematic File Version 2 date Friday 26 April 2013 04:23:31 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.20-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "26 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 6350 4200 6350 5100 -Wire Wire Line - 6350 3300 6350 2800 -Wire Wire Line - 6350 2800 5950 2800 -Wire Wire Line - 4750 4200 4950 4200 -Wire Wire Line - 5450 4200 5650 4200 -Wire Wire Line - 5950 3300 5950 3650 -Wire Wire Line - 5950 4200 5950 4050 -Connection ~ 5950 5100 -Connection ~ 5950 3450 -Connection ~ 5950 4100 -Wire Wire Line - 5650 4200 5650 3850 -Connection ~ 5650 3850 -Connection ~ 5650 3950 -Wire Wire Line - 6350 5100 4750 5100 -Wire Wire Line - 5950 5200 5950 4700 -$Comp -L IDC i1 -U 1 1 517A17EC -P 4750 4650 -F 0 "i1" H 4550 4750 60 0000 C CNN -F 1 "IDC" H 4550 4600 60 0000 C CNN -F 2 "R1" H 4450 4650 60 0000 C CNN - 1 4750 4650 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 517A1753 -P 5950 5100 -F 0 "#FLG01" H 5950 5370 30 0001 C CNN -F 1 "PWR_FLAG" H 5950 5330 30 0000 C CNN - 1 5950 5100 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 517A174B -P 5650 3950 -F 0 "#FLG02" H 5650 4220 30 0001 C CNN -F 1 "PWR_FLAG" H 5650 4180 30 0000 C CNN - 1 5650 3950 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 517A172B -P 5950 4450 -F 0 "U4" H 5800 4550 50 0000 C CNN -F 1 "IPLOT" H 6100 4550 50 0000 C CNN - 1 5950 4450 - 0 -1 -1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 517A1709 -P 5200 4200 -F 0 "U2" H 5050 4300 50 0000 C CNN -F 1 "IPLOT" H 5350 4300 50 0000 C CNN - 1 5200 4200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 517A16C8 -P 5950 3050 -F 0 "U3" H 5800 3150 50 0000 C CNN -F 1 "IPLOT" H 6100 3150 50 0000 C CNN - 1 5950 3050 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 5166CA3C -P 5650 4100 -F 0 "U1" H 5500 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN - 2 5650 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5166C9F3 -P 5650 3450 -F 0 "U1" H 5500 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN - 1 5650 3450 - 0 -1 -1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 5166C87D -P 5950 5200 -F 0 "#PWR03" H 5950 5200 30 0001 C CNN -F 1 "GND" H 5950 5130 30 0001 C CNN - 1 5950 5200 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166C79C -P 6350 3750 -F 0 "v1" H 6150 3850 60 0000 C CNN -F 1 "2" H 6150 3700 60 0000 C CNN -F 2 "R1" H 6050 3750 60 0000 C CNN - 1 6350 3750 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166C72A -P 5850 3850 -F 0 "Q1" H 5850 3700 50 0000 R CNN -F 1 "NPN" H 5850 4000 50 0000 R CNN - 1 5850 3850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/npn.lib deleted file mode 100644 index 1ff6b05..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/npn.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 -+ Cje=4.493p Isc=0 Xtb=1.5 Rb=10 Rc=1 -+ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 -+ Ise=6.734f Br=.7371 Ikf=66.78m Mje=.2593 Mjc=.3085 -+ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=2 Itf=.4 -+ Is=6.734f Eg=1.11 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/analysis deleted file mode 100644 index 10c280a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 5e-00 5e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/bjt.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/bjt.lib deleted file mode 100644 index a8411e8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/bjt.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model bjt NPN( Vtf=1.7 Cjc=7.306p Nc=2 Tr=46.91n Ne=1.307 -+ Cje=22.01p Isc=0 Xtb=1.5 Rb=10 Rc=1 -+ Tf=411.1p Xti=3 Ikr=0 Bf=50 Fc=.5 -+ Ise=14.34f Br=6.092 Ikf=.2847 Mje=.377 Mjc=.3416 -+ Vaf=74.03 Vjc=.2 Vje=.75 Xtf=3 Itf=.6 -+ Is=14.34f Eg=1.11 )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.bak deleted file mode 100644 index dad7e0c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.bak +++ /dev/null @@ -1,218 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:57:15 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.3-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 4000 3300 -Wire Wire Line - 5450 4200 5450 5350 -Wire Wire Line - 6650 5050 3500 5050 -Connection ~ 5450 5050 -Wire Wire Line - 6650 5050 6650 4450 -Wire Wire Line - 3500 5050 3500 4450 -Wire Wire Line - 4300 3300 3500 3300 -Wire Wire Line - 5450 3700 5450 3500 -Wire Wire Line - 5450 2950 5450 3100 -Wire Wire Line - 5450 2300 5450 2450 -Connection ~ 5450 3050 -Connection ~ 5450 3600 -Wire Wire Line - 3500 3300 3500 3550 -Wire Wire Line - 5450 1800 6650 1800 -Wire Wire Line - 6650 1800 6650 3550 -Wire Wire Line - 4800 3300 5150 3300 -Connection ~ 5100 3300 -Connection ~ 6650 5050 -Connection ~ 4950 3300 -Connection ~ 5450 5200 -Connection ~ 5450 4400 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CE235 -P 4950 3300 -F 0 "#FLG01" H 4950 3570 30 0001 C CNN -F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN - 1 4950 3300 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516CE22C -P 5450 5200 -F 0 "#FLG02" H 5450 5470 30 0001 C CNN -F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN - 1 5450 5200 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516CE20C -P 5450 5350 -F 0 "#PWR03" H 5450 5350 30 0001 C CNN -F 1 "GND" H 5450 5280 30 0001 C CNN - 1 5450 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516CE1D8 -P 5100 3000 -F 0 "U2" H 4950 3100 50 0000 C CNN -F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516CE177 -P 4550 3300 -F 0 "U1" H 4400 3400 50 0000 C CNN -F 1 "IPLOT" H 4700 3400 50 0000 C CNN - 1 4550 3300 - -1 0 0 1 -$EndComp -$Comp -L DC v1 -U 1 1 516CE159 -P 3500 4000 -F 0 "v1" H 3300 4100 60 0000 C CNN -F 1 "5V" H 3300 3950 60 0000 C CNN -F 2 "R1" H 3200 4000 60 0000 C CNN - 1 3500 4000 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516CE13E -P 3750 3300 -F 0 "R1" V 3830 3300 50 0000 C CNN -F 1 "2200" V 3750 3300 50 0000 C CNN - 1 3750 3300 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516CE102 -P 5750 3050 -F 0 "U2" H 5600 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN - 2 5750 3050 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516CE0C0 -P 5450 2050 -F 0 "R2" V 5530 2050 50 0000 C CNN -F 1 "1000" V 5450 2050 50 0000 C CNN - 1 5450 2050 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516CE0B6 -P 5450 2700 -F 0 "U3" H 5300 2800 50 0000 C CNN -F 1 "IPLOT" H 5600 2800 50 0000 C CNN - 1 5450 2700 - 0 1 1 0 -$EndComp -$Comp -L DC v2 -U 1 1 516CE08D -P 6650 4000 -F 0 "v2" H 6450 4100 60 0000 C CNN -F 1 "10V" H 6450 3950 60 0000 C CNN -F 2 "R1" H 6350 4000 60 0000 C CNN - 1 6650 4000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516CE083 -P 5750 3600 -F 0 "U2" H 5600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN - 3 5750 3600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CE07C -P 5450 3950 -F 0 "U4" H 5300 4050 50 0000 C CNN -F 1 "IPLOT" H 5600 4050 50 0000 C CNN - 1 5450 3950 - 0 1 1 0 -$EndComp -$Comp -L NPN Q1 -U 1 1 516CE055 -P 5350 3300 -F 0 "Q1" H 5350 3150 50 0000 R CNN -F 1 "NPN" H 5350 3450 50 0000 R CNN - 1 5350 3300 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.cir deleted file mode 100644 index 2e072a8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.cir +++ /dev/null @@ -1,17 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 12:03:45 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -Q1 7 1 5 PNP -v1 7 0 PULSE -R1 6 0 5000 -U2 1 7 5 VPLOT8_1 -U1 1 0 IPLOT -R2 3 4 10000 -U3 4 7 IPLOT -v2 3 0 10V -U4 5 6 IPLOT - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.sch deleted file mode 100644 index e0eb696..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.sch +++ /dev/null @@ -1,235 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 12:03:50 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.3-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CF0A9 -P 4000 3050 -F 0 "#FLG01" H 4000 3320 30 0001 C CNN -F 1 "PWR_FLAG" H 4000 3280 30 0000 C CNN - 1 4000 3050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3500 4200 3500 5050 -Connection ~ 4300 5050 -Wire Wire Line - 4300 5050 4300 3300 -Connection ~ 3500 3300 -Wire Wire Line - 3500 3550 3500 3050 -Wire Wire Line - 5450 4200 5450 4350 -Connection ~ 4000 3050 -Wire Wire Line - 3500 5050 6650 5050 -Connection ~ 5450 5050 -Wire Wire Line - 6650 5050 6650 4450 -Wire Wire Line - 5450 3700 5450 3500 -Wire Wire Line - 5450 2950 5450 3100 -Wire Wire Line - 5450 2300 5450 2450 -Connection ~ 5450 3050 -Connection ~ 5450 3600 -Wire Wire Line - 5450 1800 6650 1800 -Wire Wire Line - 6650 1800 6650 3550 -Connection ~ 5100 3300 -Connection ~ 6650 5050 -Connection ~ 4950 3300 -Connection ~ 5450 5200 -Wire Wire Line - 5450 5350 5450 4850 -Wire Wire Line - 5150 3300 4800 3300 -Wire Wire Line - 3500 3050 5450 3050 -Wire Wire Line - 5450 3050 5450 3000 -Connection ~ 5450 3000 -$Comp -L PNP Q1 -U 1 1 516CEFD3 -P 5350 3300 -F 0 "Q1" H 5350 3150 60 0000 R CNN -F 1 "PNP" H 5350 3450 60 0000 R CNN - 1 5350 3300 - 1 0 0 1 -$EndComp -$Comp -L PULSE v1 -U 1 1 516CEF97 -P 3500 3750 -F 0 "v1" H 3300 3850 60 0000 C CNN -F 1 "PULSE" H 3300 3700 60 0000 C CNN -F 2 "R1" H 3200 3750 60 0000 C CNN - 1 3500 3750 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516CEF60 -P 5450 4600 -F 0 "R1" V 5530 4600 50 0000 C CNN -F 1 "5000" V 5450 4600 50 0000 C CNN - 1 5450 4600 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516CE235 -P 4950 3300 -F 0 "#FLG02" H 4950 3570 30 0001 C CNN -F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN - 1 4950 3300 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG03 -U 1 1 516CE22C -P 5450 5200 -F 0 "#FLG03" H 5450 5470 30 0001 C CNN -F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN - 1 5450 5200 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR04 -U 1 1 516CE20C -P 5450 5350 -F 0 "#PWR04" H 5450 5350 30 0001 C CNN -F 1 "GND" H 5450 5280 30 0001 C CNN - 1 5450 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516CE1D8 -P 5100 3000 -F 0 "U2" H 4950 3100 50 0000 C CNN -F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516CE177 -P 4550 3300 -F 0 "U1" H 4400 3400 50 0000 C CNN -F 1 "IPLOT" H 4700 3400 50 0000 C CNN - 1 4550 3300 - -1 0 0 1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516CE102 -P 5750 3050 -F 0 "U2" H 5600 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN - 2 5750 3050 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516CE0C0 -P 5450 2050 -F 0 "R2" V 5530 2050 50 0000 C CNN -F 1 "10000" V 5450 2050 50 0000 C CNN - 1 5450 2050 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516CE0B6 -P 5450 2700 -F 0 "U3" H 5300 2800 50 0000 C CNN -F 1 "IPLOT" H 5600 2800 50 0000 C CNN - 1 5450 2700 - 0 1 1 0 -$EndComp -$Comp -L DC v2 -U 1 1 516CE08D -P 6650 4000 -F 0 "v2" H 6450 4100 60 0000 C CNN -F 1 "10V" H 6450 3950 60 0000 C CNN -F 2 "R1" H 6350 4000 60 0000 C CNN - 1 6650 4000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516CE083 -P 5750 3600 -F 0 "U2" H 5600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN - 3 5750 3600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CE07C -P 5450 3950 -F 0 "U4" H 5300 4050 50 0000 C CNN -F 1 "IPLOT" H 5600 4050 50 0000 C CNN - 1 5450 3950 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.bak deleted file mode 100644 index f265808..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.bak +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 12:24:14 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.lib deleted file mode 100644 index 8652c69..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 25 April 2013 02:05:06 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.bak deleted file mode 100644 index 246ba5c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.bak +++ /dev/null @@ -1,217 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:04:07 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 4000 3300 -Wire Wire Line - 5450 4200 5450 5350 -Wire Wire Line - 6650 5050 3500 5050 -Connection ~ 5450 5050 -Wire Wire Line - 6650 5050 6650 4450 -Wire Wire Line - 3500 5050 3500 4450 -Wire Wire Line - 4300 3300 3500 3300 -Wire Wire Line - 5450 3700 5450 3500 -Wire Wire Line - 5450 2950 5450 3100 -Wire Wire Line - 5450 2300 5450 2450 -Connection ~ 5450 3050 -Connection ~ 5450 3600 -Wire Wire Line - 3500 3300 3500 3550 -Wire Wire Line - 5450 1800 6650 1800 -Wire Wire Line - 6650 1800 6650 3550 -Wire Wire Line - 4800 3300 5150 3300 -Connection ~ 5100 3300 -Connection ~ 6650 5050 -Connection ~ 4950 3300 -Connection ~ 5450 5200 -Connection ~ 5450 4400 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CE235 -P 4950 3300 -F 0 "#FLG01" H 4950 3570 30 0001 C CNN -F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN - 1 4950 3300 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516CE22C -P 5450 5200 -F 0 "#FLG02" H 5450 5470 30 0001 C CNN -F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN - 1 5450 5200 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516CE20C -P 5450 5350 -F 0 "#PWR03" H 5450 5350 30 0001 C CNN -F 1 "GND" H 5450 5280 30 0001 C CNN - 1 5450 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516CE1D8 -P 5100 3000 -F 0 "U2" H 4950 3100 50 0000 C CNN -F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516CE177 -P 4550 3300 -F 0 "U1" H 4400 3400 50 0000 C CNN -F 1 "IPLOT" H 4700 3400 50 0000 C CNN - 1 4550 3300 - -1 0 0 1 -$EndComp -$Comp -L DC v1 -U 1 1 516CE159 -P 3500 4000 -F 0 "v1" H 3300 4100 60 0000 C CNN -F 1 "5V" H 3300 3950 60 0000 C CNN -F 2 "R1" H 3200 4000 60 0000 C CNN - 1 3500 4000 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516CE13E -P 3750 3300 -F 0 "R1" V 3830 3300 50 0000 C CNN -F 1 "2200" V 3750 3300 50 0000 C CNN - 1 3750 3300 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516CE102 -P 5750 3050 -F 0 "U2" H 5600 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN - 2 5750 3050 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516CE0C0 -P 5450 2050 -F 0 "R2" V 5530 2050 50 0000 C CNN -F 1 "1000" V 5450 2050 50 0000 C CNN - 1 5450 2050 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516CE0B6 -P 5450 2700 -F 0 "U3" H 5300 2800 50 0000 C CNN -F 1 "IPLOT" H 5600 2800 50 0000 C CNN - 1 5450 2700 - 0 1 1 0 -$EndComp -$Comp -L DC v2 -U 1 1 516CE08D -P 6650 4000 -F 0 "v2" H 6450 4100 60 0000 C CNN -F 1 "10V" H 6450 3950 60 0000 C CNN -F 2 "R1" H 6350 4000 60 0000 C CNN - 1 6650 4000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516CE083 -P 5750 3600 -F 0 "U2" H 5600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN - 3 5750 3600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CE07C -P 5450 3950 -F 0 "U4" H 5300 4050 50 0000 C CNN -F 1 "IPLOT" H 5600 4050 50 0000 C CNN - 1 5450 3950 - 0 1 1 0 -$EndComp -$Comp -L NPN Q1 -U 1 1 516CE055 -P 5350 3300 -F 0 "Q1" H 5350 3150 50 0000 R CNN -F 1 "NPN" H 5350 3450 50 0000 R CNN - 1 5350 3300 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir deleted file mode 100644 index 97a0042..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir +++ /dev/null @@ -1,17 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 25 April 2013 02:05:01 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 7 2 5 VPLOT8_1 -U1 7 1 IPLOT -v1 1 0 5V -R1 1 1 2200 -R2 3 4 1k -U3 4 2 IPLOT -v2 3 0 10V -U4 5 0 IPLOT -Q1 5 7 2 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.ckt deleted file mode 100644 index 51d6e2f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.ckt +++ /dev/null @@ -1,19 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 02:05:01 pm ist -.include npn.lib - -* Plotting option vplot8_1 -V_u1 7 1 0 -v1 1 0 5v -r1 1 1 2200 -r2 3 4 1k -V_u3 4 2 0 -v2 3 0 10v -V_u4 5 0 0 -q1 2 7 5 npn - -.dc v1 0e-00 5e-00 5e-00 -.plot v(7) v(2) v(5) -.plot i(V_u1) -.plot i(V_u3) -.plot i(V_u4) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.out deleted file mode 100644 index 30154d7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 02:05:01 pm ist -.include npn.lib - -* Plotting option vplot8_1 -V_u1 7 1 0 -v1 1 0 5v -r1 1 1 2200 -r2 3 4 1k -V_u3 4 2 0 -v2 3 0 10v -V_u4 5 0 0 -q1 2 7 5 npn - -.dc v1 0e-00 5e-00 5e-00 - -* Control Statements -.control -run -plot v(7) v(2) v(5) -plot i(V_u1) -plot i(V_u3) -plot i(V_u4) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.pro deleted file mode 100644 index f37394e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 10:53:01 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.proj deleted file mode 100644 index 00153d6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.3.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.sch deleted file mode 100644 index 0bfa3f7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.sch +++ /dev/null @@ -1,218 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 25 April 2013 02:05:06 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.3-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "25 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 4000 3300 -Wire Wire Line - 5450 4200 5450 5350 -Wire Wire Line - 6650 5050 3500 5050 -Connection ~ 5450 5050 -Wire Wire Line - 6650 5050 6650 4450 -Wire Wire Line - 3500 5050 3500 4450 -Wire Wire Line - 4300 3300 3500 3300 -Wire Wire Line - 5450 3700 5450 3500 -Wire Wire Line - 5450 2950 5450 3100 -Wire Wire Line - 5450 2300 5450 2450 -Connection ~ 5450 3050 -Connection ~ 5450 3600 -Wire Wire Line - 3500 3300 3500 3550 -Wire Wire Line - 5450 1800 6650 1800 -Wire Wire Line - 6650 1800 6650 3550 -Wire Wire Line - 4800 3300 5150 3300 -Connection ~ 5100 3300 -Connection ~ 6650 5050 -Connection ~ 4950 3300 -Connection ~ 5450 5200 -Connection ~ 5450 4400 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CE235 -P 4950 3300 -F 0 "#FLG01" H 4950 3570 30 0001 C CNN -F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN - 1 4950 3300 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516CE22C -P 5450 5200 -F 0 "#FLG02" H 5450 5470 30 0001 C CNN -F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN - 1 5450 5200 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516CE20C -P 5450 5350 -F 0 "#PWR03" H 5450 5350 30 0001 C CNN -F 1 "GND" H 5450 5280 30 0001 C CNN - 1 5450 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516CE1D8 -P 5100 3000 -F 0 "U2" H 4950 3100 50 0000 C CNN -F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516CE177 -P 4550 3300 -F 0 "U1" H 4400 3400 50 0000 C CNN -F 1 "IPLOT" H 4700 3400 50 0000 C CNN - 1 4550 3300 - -1 0 0 1 -$EndComp -$Comp -L DC v1 -U 1 1 516CE159 -P 3500 4000 -F 0 "v1" H 3300 4100 60 0000 C CNN -F 1 "5V" H 3300 3950 60 0000 C CNN -F 2 "R1" H 3200 4000 60 0000 C CNN - 1 3500 4000 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516CE13E -P 3750 3300 -F 0 "R1" V 3830 3300 50 0000 C CNN -F 1 "2200" V 3750 3300 50 0000 C CNN - 1 3750 3300 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516CE102 -P 5750 3050 -F 0 "U2" H 5600 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN - 2 5750 3050 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516CE0C0 -P 5450 2050 -F 0 "R2" V 5530 2050 50 0000 C CNN -F 1 "1k" V 5450 2050 50 0000 C CNN - 1 5450 2050 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516CE0B6 -P 5450 2700 -F 0 "U3" H 5300 2800 50 0000 C CNN -F 1 "IPLOT" H 5600 2800 50 0000 C CNN - 1 5450 2700 - 0 1 1 0 -$EndComp -$Comp -L DC v2 -U 1 1 516CE08D -P 6650 4000 -F 0 "v2" H 6450 4100 60 0000 C CNN -F 1 "10V" H 6450 3950 60 0000 C CNN -F 2 "R1" H 6350 4000 60 0000 C CNN - 1 6650 4000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516CE083 -P 5750 3600 -F 0 "U2" H 5600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN - 3 5750 3600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516CE07C -P 5450 3950 -F 0 "U4" H 5300 4050 50 0000 C CNN -F 1 "IPLOT" H 5600 4050 50 0000 C CNN - 1 5450 3950 - 0 1 1 0 -$EndComp -$Comp -L NPN Q1 -U 1 1 516CE055 -P 5350 3300 -F 0 "Q1" H 5350 3150 50 0000 R CNN -F 1 "NPN" H 5350 3450 50 0000 R CNN - 1 5350 3300 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/npn.lib deleted file mode 100644 index 5aecc2e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/npn.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model npn NPN( Vtf= Cjc= Nc= Tr= Ne= -+ Cje= Vjc= Xtb= Rb= Rc= -+ Tf= Xti= Ikr= Bf=50 Fc= -+ Ikf= Br= Mje= Mjc= Vaf= -+ Isc= Ise= Xtf= Vje= Is= -+ Itf= Eg= )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/analysis deleted file mode 100644 index 35318bb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.bak deleted file mode 100644 index ea673cb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.bak +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 10:43:17 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.lib deleted file mode 100644 index ee59c22..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.lib +++ /dev/null @@ -1,108 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 12:52:43 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# VCCS -# -DEF VCCS G 0 40 Y Y 1 F N -F0 "G" -200 100 50 H V C CNN -F1 "VCCS" -200 -50 50 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.bak deleted file mode 100644 index 6e5ac9b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.bak +++ /dev/null @@ -1,172 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 07:53:26 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.6-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5650 3850 5650 5350 -Wire Wire Line - 5950 4700 5950 4850 -Wire Wire Line - 5950 2800 5950 2650 -Wire Wire Line - 5950 3300 5950 3650 -Wire Wire Line - 5950 2150 6350 2150 -Wire Wire Line - 5950 4200 5950 4050 -Wire Wire Line - 5650 5350 6350 5350 -Connection ~ 5950 5350 -Wire Wire Line - 5950 5350 5950 5600 -Connection ~ 5950 5450 -Connection ~ 5950 3450 -Connection ~ 5950 4100 -Wire Wire Line - 6350 2150 6350 3300 -Wire Wire Line - 6350 5350 6350 4200 -$Comp -L IPLOT U3 -U 1 1 516C0D28 -P 5950 4450 -F 0 "U3" H 5800 4550 50 0000 C CNN -F 1 "IPLOT" H 6100 4550 50 0000 C CNN - 1 5950 4450 - 0 -1 -1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C0CED -P 5950 3050 -F 0 "U2" H 5800 3150 50 0000 C CNN -F 1 "IPLOT" H 6100 3150 50 0000 C CNN - 1 5950 3050 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 5166CA3C -P 5650 4100 -F 0 "U1" H 5500 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN - 2 5650 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5166C9F3 -P 5650 3450 -F 0 "U1" H 5500 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN - 1 5650 3450 - 0 -1 -1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5166C8C4 -P 5950 5450 -F 0 "#FLG01" H 5950 5545 30 0001 C CNN -F 1 "PWR_FLAG" H 5950 5630 30 0000 C CNN - 1 5950 5450 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5166C87D -P 5950 5600 -F 0 "#PWR02" H 5950 5600 30 0001 C CNN -F 1 "GND" H 5950 5530 30 0001 C CNN - 1 5950 5600 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166C822 -P 5950 2400 -F 0 "R1" V 6030 2400 50 0000 C CNN -F 1 "4700" V 5950 2400 50 0000 C CNN - 1 5950 2400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5166C7EC -P 5950 5100 -F 0 "R2" V 6030 5100 50 0000 C CNN -F 1 "3300" V 5950 5100 50 0000 C CNN - 1 5950 5100 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166C79C -P 6350 3750 -F 0 "v1" H 6150 3850 60 0000 C CNN -F 1 "10V" H 6150 3700 60 0000 C CNN -F 2 "R1" H 6050 3750 60 0000 C CNN - 1 6350 3750 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166C72A -P 5850 3850 -F 0 "Q1" H 5850 3700 50 0000 R CNN -F 1 "NPN" H 5850 4000 50 0000 R CNN - 1 5850 3850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir deleted file mode 100644 index c9bc6a1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir +++ /dev/null @@ -1,16 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 10:43:13 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U4 0 7 IPLOT -U3 4 1 IPLOT -U2 2 3 IPLOT -U1 2 1 VPLOT8_1 -R1 5 3 4700 -R2 4 0 3300 -v1 5 0 10V -Q1 1 7 2 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.ckt deleted file mode 100644 index f76426b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.ckt +++ /dev/null @@ -1,18 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 10:43:13 am ist -.include npn.lib - -V_u4 0 7 0 -V_u3 4 1 0 -V_u2 2 3 0 -* Plotting option vplot8_1 -r1 5 3 4700 -r2 4 0 3300 -v1 5 0 10v -q1 2 7 1 npn - -.dc v1 0e-00 10e-00 5e-03 -.plot i(V_u4) -.plot i(V_u3) -.plot i(V_u2) -.plot v(2) v(1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.out deleted file mode 100644 index c87b0a7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.out +++ /dev/null @@ -1,23 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 10:43:13 am ist -.include npn.lib - -V_u4 0 7 0 -V_u3 4 1 0 -V_u2 2 3 0 -* Plotting option vplot8_1 -r1 5 3 4700 -r2 4 0 3300 -v1 5 0 10v -q1 2 7 1 npn - -.dc v1 0e-00 10e-00 5e-03 - -* Control Statements -.control -run -plot i(V_u4) -plot i(V_u3) -plot i(V_u2) -plot v(2) v(1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.pro deleted file mode 100644 index 36d0202..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.pro +++ /dev/null @@ -1,84 +0,0 @@ -update=Tuesday 16 April 2013 12:39:39 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice -LibName41=/home/holy/OSCAD/library/analogSpice -LibName42=/home/holy/OSCAD/library/analogXSpice -LibName43=/home/holy/OSCAD/library/convergenceAidSpice -LibName44=/home/holy/OSCAD/library/converterSpice -LibName45=/home/holy/OSCAD/library/digitalSpice -LibName46=/home/holy/OSCAD/library/digitalXSpice -LibName47=/home/holy/OSCAD/library/linearSpice -LibName48=/home/holy/OSCAD/library/measurementSpice -LibName49=/home/holy/OSCAD/library/portSpice -LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.proj deleted file mode 100644 index 3ace945..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.6.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.sch deleted file mode 100644 index d3d6988..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.sch +++ /dev/null @@ -1,195 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 10:43:17 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.6-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5650 3950 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516CDDBE -P 5650 3950 -F 0 "#FLG01" H 5650 4220 30 0001 C CNN -F 1 "PWR_FLAG" H 5650 4180 30 0000 C CNN - 1 5650 3950 - 0 -1 -1 0 -$EndComp -Connection ~ 5650 3850 -Connection ~ 5700 5350 -Wire Wire Line - 5650 4700 5650 5350 -Wire Wire Line - 5650 3850 5650 4200 -Wire Wire Line - 6350 4200 6350 5350 -Wire Wire Line - 6350 3300 6350 2150 -Connection ~ 5950 4100 -Connection ~ 5950 3450 -Connection ~ 5950 5450 -Wire Wire Line - 5950 5350 5950 5600 -Connection ~ 5950 5350 -Wire Wire Line - 6350 5350 5650 5350 -Wire Wire Line - 5950 4200 5950 4050 -Wire Wire Line - 6350 2150 5950 2150 -Wire Wire Line - 5950 3300 5950 3650 -Wire Wire Line - 5950 2800 5950 2650 -Wire Wire Line - 5950 4700 5950 4850 -$Comp -L IPLOT U4 -U 1 1 516CDCFB -P 5650 4450 -F 0 "U4" H 5500 4550 50 0000 C CNN -F 1 "IPLOT" H 5800 4550 50 0000 C CNN - 1 5650 4450 - 0 -1 -1 0 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516C0D28 -P 5950 4450 -F 0 "U3" H 5800 4550 50 0000 C CNN -F 1 "IPLOT" H 6100 4550 50 0000 C CNN - 1 5950 4450 - 0 -1 -1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C0CED -P 5950 3050 -F 0 "U2" H 5800 3150 50 0000 C CNN -F 1 "IPLOT" H 6100 3150 50 0000 C CNN - 1 5950 3050 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 5166CA3C -P 5650 4100 -F 0 "U1" H 5500 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN - 2 5650 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5166C9F3 -P 5650 3450 -F 0 "U1" H 5500 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN - 1 5650 3450 - 0 -1 -1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 5166C8C4 -P 5700 5350 -F 0 "#FLG02" H 5700 5445 30 0001 C CNN -F 1 "PWR_FLAG" H 5700 5530 30 0000 C CNN - 1 5700 5350 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 5166C87D -P 5950 5600 -F 0 "#PWR03" H 5950 5600 30 0001 C CNN -F 1 "GND" H 5950 5530 30 0001 C CNN - 1 5950 5600 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166C822 -P 5950 2400 -F 0 "R1" V 6030 2400 50 0000 C CNN -F 1 "4700" V 5950 2400 50 0000 C CNN - 1 5950 2400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5166C7EC -P 5950 5100 -F 0 "R2" V 6030 5100 50 0000 C CNN -F 1 "3300" V 5950 5100 50 0000 C CNN - 1 5950 5100 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5166C79C -P 6350 3750 -F 0 "v1" H 6150 3850 60 0000 C CNN -F 1 "10V" H 6150 3700 60 0000 C CNN -F 2 "R1" H 6050 3750 60 0000 C CNN - 1 6350 3750 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5166C72A -P 5850 3850 -F 0 "Q1" H 5850 3700 50 0000 R CNN -F 1 "NPN" H 5850 4000 50 0000 R CNN - 1 5850 3850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/npn.lib deleted file mode 100644 index f84808e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/npn.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model npn NPN( Vtf=1.7 Cjc=7.306p Nc=2 Tr=46.91n Ne=1.307 -+ Cje=22.01p Isc=0 Xtb=1.5 Rb=10 Rc=1 -+ Tf=411.1p Xti=3 Ikr=0 Bf=400 Fc=.5 -+ Ise=14.34f Br=6.092 Ikf=.2847 Mje=.377 Mjc=.3416 -+ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=3 Itf=.6 -+ Is=14.34f Eg=1.11 )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/analysis deleted file mode 100644 index 35318bb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.bak deleted file mode 100644 index 1c7c96a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.bak +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 08:09:14 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.lib deleted file mode 100644 index 0acf0b6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 08:10:59 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.bak deleted file mode 100644 index ca1bf82..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.bak +++ /dev/null @@ -1,172 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 08:09:14 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5050 4700 -Connection ~ 5050 3500 -Connection ~ 4500 5050 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C10CC -P 4500 5050 -F 0 "#FLG01" H 4500 5320 30 0001 C CNN -F 1 "PWR_FLAG" H 4500 5280 30 0000 C CNN - 1 4500 5050 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C10B9 -P 4450 5350 -F 0 "#PWR02" H 4450 5350 30 0001 C CNN -F 1 "GND" H 4450 5280 30 0001 C CNN - 1 4450 5350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4450 5350 4500 5350 -Wire Wire Line - 4500 5350 4500 3750 -Wire Wire Line - 4500 3750 4750 3750 -Wire Wire Line - 5050 4550 5050 4850 -Wire Wire Line - 5050 5350 5650 5350 -Wire Wire Line - 5050 3450 5050 3550 -Wire Wire Line - 5050 2850 5050 2950 -Wire Wire Line - 5050 3950 5050 4050 -Wire Wire Line - 5050 2350 5650 2350 -Wire Wire Line - 5650 2350 5650 3200 -Wire Wire Line - 5650 5350 5650 4100 -$Comp -L VPLOT8_1 U3 -U 2 1 516C107A -P 5350 4700 -F 0 "U3" H 5200 4800 50 0000 C CNN -F 1 "VPLOT8_1" H 5500 4800 50 0000 C CNN - 2 5350 4700 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C103D -P 5650 3650 -F 0 "v1" H 5450 3750 60 0000 C CNN -F 1 "DC" H 5450 3600 60 0000 C CNN -F 2 "R1" H 5350 3650 60 0000 C CNN - 1 5650 3650 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516C1001 -P 5350 3500 -F 0 "U3" H 5200 3600 50 0000 C CNN -F 1 "VPLOT8_1" H 5500 3600 50 0000 C CNN - 1 5350 3500 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516C0FB5 -P 5050 5100 -F 0 "R2" V 5130 5100 50 0000 C CNN -F 1 "R" V 5050 5100 50 0000 C CNN - 1 5050 5100 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C0FAB -P 5050 4300 -F 0 "U2" H 4900 4400 50 0000 C CNN -F 1 "IPLOT" H 5200 4400 50 0000 C CNN - 1 5050 4300 - 0 -1 -1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516C0F0F -P 5050 3200 -F 0 "U1" H 4900 3300 50 0000 C CNN -F 1 "IPLOT" H 5200 3300 50 0000 C CNN - 1 5050 3200 - 0 -1 -1 0 -$EndComp -$Comp -L R R1 -U 1 1 516C0F01 -P 5050 2600 -F 0 "R1" V 5130 2600 50 0000 C CNN -F 1 "R" V 5050 2600 50 0000 C CNN - 1 5050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q1 -U 1 1 516C0EEC -P 4950 3750 -F 0 "Q1" H 4950 3600 60 0000 R CNN -F 1 "PNP" H 4950 3900 60 0000 R CNN - 1 4950 3750 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir deleted file mode 100644 index 7d111e3..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 08:10:56 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U3 4 6 VPLOT8_1 -v1 3 5 10 -R2 6 3 2000 -U2 6 2 IPLOT -U1 4 1 IPLOT -R1 5 1 1000 -Q1 2 0 4 PNP - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.ckt deleted file mode 100644 index d569e7a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.ckt +++ /dev/null @@ -1,15 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:10:56 pm ist - -* Plotting option vplot8_1 -v1 3 5 10 -r2 6 3 2000 -V_u2 6 2 0 -V_u1 4 1 0 -r1 5 1 1000 -q1 4 0 2 pnp - -.dc v1 0e-00 10e-00 5e-03 -.plot v(4) v(6) -.plot i(V_u2) -.plot i(V_u1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.out deleted file mode 100644 index 946ba9b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:10:56 pm ist - -* Plotting option vplot8_1 -v1 3 5 10 -r2 6 3 2000 -V_u2 6 2 0 -V_u1 4 1 0 -r1 5 1 1000 -q1 4 0 2 pnp - -.dc v1 0e-00 10e-00 5e-03 - -* Control Statements -.control -run -plot v(4) v(6) -plot i(V_u2) -plot i(V_u1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.pro deleted file mode 100644 index 7b4f272..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 15 April 2013 07:58:37 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.proj deleted file mode 100644 index b07d448..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.7.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.sch deleted file mode 100644 index c9780ef..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.sch +++ /dev/null @@ -1,173 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 08:10:59 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.7-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5050 4700 -Connection ~ 5050 3500 -Connection ~ 4500 5050 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C10CC -P 4500 5050 -F 0 "#FLG01" H 4500 5320 30 0001 C CNN -F 1 "PWR_FLAG" H 4500 5280 30 0000 C CNN - 1 4500 5050 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C10B9 -P 4450 5350 -F 0 "#PWR02" H 4450 5350 30 0001 C CNN -F 1 "GND" H 4450 5280 30 0001 C CNN - 1 4450 5350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4450 5350 4500 5350 -Wire Wire Line - 4500 5350 4500 3750 -Wire Wire Line - 4500 3750 4750 3750 -Wire Wire Line - 5050 4550 5050 4850 -Wire Wire Line - 5050 5350 5650 5350 -Wire Wire Line - 5050 3450 5050 3550 -Wire Wire Line - 5050 2850 5050 2950 -Wire Wire Line - 5050 3950 5050 4050 -Wire Wire Line - 5050 2350 5650 2350 -Wire Wire Line - 5650 2350 5650 3200 -Wire Wire Line - 5650 5350 5650 4100 -$Comp -L VPLOT8_1 U3 -U 2 1 516C107A -P 5350 4700 -F 0 "U3" H 5200 4800 50 0000 C CNN -F 1 "VPLOT8_1" H 5500 4800 50 0000 C CNN - 2 5350 4700 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C103D -P 5650 3650 -F 0 "v1" H 5450 3750 60 0000 C CNN -F 1 "10" H 5450 3600 60 0000 C CNN -F 2 "R1" H 5350 3650 60 0000 C CNN - 1 5650 3650 - 1 0 0 1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516C1001 -P 5350 3500 -F 0 "U3" H 5200 3600 50 0000 C CNN -F 1 "VPLOT8_1" H 5500 3600 50 0000 C CNN - 1 5350 3500 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516C0FB5 -P 5050 5100 -F 0 "R2" V 5130 5100 50 0000 C CNN -F 1 "2000" V 5050 5100 50 0000 C CNN - 1 5050 5100 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C0FAB -P 5050 4300 -F 0 "U2" H 4900 4400 50 0000 C CNN -F 1 "IPLOT" H 5200 4400 50 0000 C CNN - 1 5050 4300 - 0 -1 -1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516C0F0F -P 5050 3200 -F 0 "U1" H 4900 3300 50 0000 C CNN -F 1 "IPLOT" H 5200 3300 50 0000 C CNN - 1 5050 3200 - 0 -1 -1 0 -$EndComp -$Comp -L R R1 -U 1 1 516C0F01 -P 5050 2600 -F 0 "R1" V 5130 2600 50 0000 C CNN -F 1 "1000" V 5050 2600 50 0000 C CNN - 1 5050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q1 -U 1 1 516C0EEC -P 4950 3750 -F 0 "Q1" H 4950 3600 60 0000 R CNN -F 1 "PNP" H 4950 3900 60 0000 R CNN - 1 4950 3750 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/analysis deleted file mode 100644 index 7946c35..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8-cache.lib deleted file mode 100644 index c582dbc..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 08:58:27 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir deleted file mode 100644 index 073dc21..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir +++ /dev/null @@ -1,16 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 08:58:23 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v1 3 0 5V -v2 2 0 10V -R1 6 3 100 -U3 1 4 VPLOT8_1 -U2 0 4 IPLOT -U1 1 5 IPLOT -R2 2 5 2000 -Q1 4 6 1 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.ckt deleted file mode 100644 index bf04d00..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.ckt +++ /dev/null @@ -1,16 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:58:23 pm ist - -v1 3 0 5v -v2 2 0 10v -r1 6 3 100 -* Plotting option vplot8_1 -V_u2 0 4 0 -V_u1 1 5 0 -r2 2 5 2000 -q1 1 6 4 npn - -.dc v1 0e-00 5e-00 5e-03 -.plot v(1) v(4) -.plot i(V_u2) -.plot i(V_u1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.out deleted file mode 100644 index 4fa87ff..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.out +++ /dev/null @@ -1,21 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:58:23 pm ist - -v1 3 0 5v -v2 2 0 10v -r1 6 3 100 -* Plotting option vplot8_1 -V_u2 0 4 0 -V_u1 1 5 0 -r2 2 5 2000 -q1 1 6 4 npn - -.dc v1 0e-00 5e-00 5e-03 - -* Control Statements -.control -run -plot v(1) v(4) -plot i(V_u2) -plot i(V_u1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.pro deleted file mode 100644 index 829ea15..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 15 April 2013 08:14:03 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.proj deleted file mode 100644 index 2797ff1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.sch deleted file mode 100644 index f8c5751..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.sch +++ /dev/null @@ -1,181 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 08:58:27 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5500 4450 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C1C70 -P 5500 4450 -F 0 "#FLG01" H 5500 4720 30 0001 C CNN -F 1 "PWR_FLAG" H 5500 4680 30 0000 C CNN - 1 5500 4450 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C1C57 -P 5500 4500 -F 0 "#PWR02" H 5500 4500 30 0001 C CNN -F 1 "GND" H 5500 4430 30 0001 C CNN - 1 5500 4500 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5500 4500 5500 4000 -Connection ~ 5500 4350 -Wire Wire Line - 4600 4350 6400 4350 -Wire Wire Line - 6400 2150 6400 1800 -Wire Wire Line - 6400 1800 5500 1800 -Connection ~ 5500 3450 -Connection ~ 5500 2950 -Wire Wire Line - 5500 2300 5500 2400 -Wire Wire Line - 5500 3000 5500 2900 -Wire Wire Line - 5500 3400 5500 3500 -Wire Wire Line - 5200 3200 5100 3200 -Wire Wire Line - 4600 4350 4600 4100 -Wire Wire Line - 6400 4350 6400 3050 -$Comp -L DC v1 -U 1 1 516C1BAA -P 4600 3650 -F 0 "v1" H 4400 3750 60 0000 C CNN -F 1 "5V" H 4400 3600 60 0000 C CNN -F 2 "R1" H 4300 3650 60 0000 C CNN - 1 4600 3650 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 516C1B93 -P 6400 2600 -F 0 "v2" H 6200 2700 60 0000 C CNN -F 1 "10V" H 6200 2550 60 0000 C CNN -F 2 "R1" H 6100 2600 60 0000 C CNN - 1 6400 2600 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516C130D -P 4850 3200 -F 0 "R1" V 4930 3200 50 0000 C CNN -F 1 "100" V 4850 3200 50 0000 C CNN - 1 4850 3200 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 2 1 516C12F0 -P 5800 3450 -F 0 "U3" H 5650 3550 50 0000 C CNN -F 1 "VPLOT8_1" H 5950 3550 50 0000 C CNN - 2 5800 3450 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516C12D2 -P 5500 3750 -F 0 "U2" H 5350 3850 50 0000 C CNN -F 1 "IPLOT" H 5650 3850 50 0000 C CNN - 1 5500 3750 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516C128C -P 5800 2950 -F 0 "U3" H 5650 3050 50 0000 C CNN -F 1 "VPLOT8_1" H 5950 3050 50 0000 C CNN - 1 5800 2950 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516C1282 -P 5500 2650 -F 0 "U1" H 5350 2750 50 0000 C CNN -F 1 "IPLOT" H 5650 2750 50 0000 C CNN - 1 5500 2650 - 0 -1 -1 0 -$EndComp -$Comp -L R R2 -U 1 1 516C125F -P 5500 2050 -F 0 "R2" V 5580 2050 50 0000 C CNN -F 1 "2000" V 5500 2050 50 0000 C CNN - 1 5500 2050 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 516C1252 -P 5400 3200 -F 0 "Q1" H 5400 3050 50 0000 R CNN -F 1 "NPN" H 5400 3350 50 0000 R CNN - 1 5400 3200 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis deleted file mode 100644 index 7946c35..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak deleted file mode 100644 index ab4ac6a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 09:47:58 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib deleted file mode 100644 index 19bc1ef..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:19:52 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PNP -# -DEF PNP Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 60 H V R CNN -F1 "PNP" 0 150 60 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 F -P 3 0 1 0 25 -25 0 0 0 0 N -P 3 0 1 0 100 -100 65 -65 65 -65 N -P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak deleted file mode 100644 index 9b2890f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak +++ /dev/null @@ -1,200 +0,0 @@ -EESchema Schematic File Version 2 date Monday 15 April 2013 09:47:58 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 4800 3600 4150 3600 -Wire Wire Line - 6500 2900 6500 2050 -Wire Wire Line - 6500 2050 5100 2050 -Wire Wire Line - 5100 5100 5100 5250 -Wire Wire Line - 5100 3800 5100 3950 -Wire Wire Line - 5100 3250 5100 3400 -Wire Wire Line - 5100 2650 5100 2750 -Wire Wire Line - 5100 4450 5100 4600 -Wire Wire Line - 5100 2050 5100 2150 -Connection ~ 5100 3350 -Connection ~ 5100 3900 -Wire Wire Line - 3650 3600 3650 5100 -Connection ~ 5100 2050 -Connection ~ 5100 2050 -Connection ~ 5100 2050 -Wire Wire Line - 6500 3800 6500 5250 -Wire Wire Line - 6500 5250 5100 5250 -Connection ~ 4750 3600 -Connection ~ 3650 3600 -Connection ~ 4150 3600 -Connection ~ 3950 3600 -Connection ~ 4800 3600 -Connection ~ 3650 4850 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516C1E89 -P 3650 4850 -F 0 "#FLG01" H 3650 5120 30 0001 C CNN -F 1 "PWR_FLAG" H 3650 5080 30 0000 C CNN - 1 3650 4850 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516C1EFD -P 4750 3300 -F 0 "U2" H 4600 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 4900 3400 50 0000 C CNN - 1 4750 3300 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516C1E7B -P 3650 5100 -F 0 "#PWR02" H 3650 5100 30 0001 C CNN -F 1 "GND" H 3650 5030 30 0001 C CNN - 1 3650 5100 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516C1E56 -P 3900 3600 -F 0 "R1" V 3980 3600 50 0000 C CNN -F 1 "10000" V 3900 3600 50 0000 C CNN - 1 3900 3600 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516C1E37 -P 5400 3900 -F 0 "U2" H 5250 4000 50 0000 C CNN -F 1 "VPLOT8_1" H 5550 4000 50 0000 C CNN - 3 5400 3900 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 516C1E04 -P 5100 4850 -F 0 "R3" V 5180 4850 50 0000 C CNN -F 1 "10000" V 5100 4850 50 0000 C CNN - 1 5100 4850 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516C1DF8 -P 5100 4200 -F 0 "U4" H 4950 4300 50 0000 C CNN -F 1 "IPLOT" H 5250 4300 50 0000 C CNN - 1 5100 4200 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516C1DCB -P 5400 3350 -F 0 "U2" H 5250 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 5550 3450 50 0000 C CNN - 2 5400 3350 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C1DBD -P 6500 3350 -F 0 "v1" H 6300 3450 60 0000 C CNN -F 1 "5" H 6300 3300 60 0000 C CNN -F 2 "R1" H 6200 3350 60 0000 C CNN - 1 6500 3350 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516C1DAD -P 5100 3000 -F 0 "U3" H 4950 3100 50 0000 C CNN -F 1 "IPLOT" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516C1D7F -P 5100 2400 -F 0 "R2" V 5180 2400 50 0000 C CNN -F 1 "1000" V 5100 2400 50 0000 C CNN - 1 5100 2400 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q1 -U 1 1 516C1D57 -P 5000 3600 -F 0 "Q1" H 5000 3450 60 0000 R CNN -F 1 "PNP" H 5000 3750 60 0000 R CNN - 1 5000 3600 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir deleted file mode 100644 index 484dfb8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir +++ /dev/null @@ -1,17 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:19:49 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v2 0 4 5 -U2 2 6 3 VPLOT8_1 -R1 2 0 10000 -R3 5 4 10000 -U4 3 5 IPLOT -v1 7 0 5 -U3 8 6 IPLOT -R2 7 8 1000 -Q1 3 2 6 PNP - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt deleted file mode 100644 index 3c4d3e8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:19:49 pm ist - -v2 0 4 5 -* Plotting option vplot8_1 -r1 2 0 10000 -r3 5 4 10000 -V_u4 3 5 0 -v1 7 0 5 -V_u3 8 6 0 -r2 7 8 1000 -q1 6 2 3 pnp - -.dc v1 0e-00 5e-00 5e-03 -.plot v(2) v(6) v(3) -.plot i(V_u4) -.plot i(V_u3) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out deleted file mode 100644 index 00c3815..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:19:49 pm ist - -v2 0 4 5 -* Plotting option vplot8_1 -r1 2 0 10000 -r3 5 4 10000 -V_u4 3 5 0 -v1 7 0 5 -V_u3 8 6 0 -r2 7 8 1000 -q1 6 2 3 pnp - -.dc v1 0e-00 5e-00 5e-03 - -* Control Statements -.control -run -plot v(2) v(6) v(3) -plot i(V_u4) -plot i(V_u3) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro deleted file mode 100644 index 50bea06..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 15 April 2013 09:01:17 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj deleted file mode 100644 index cf438f1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_3.9.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch deleted file mode 100644 index da988b4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch +++ /dev/null @@ -1,221 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 01:19:52 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_3.9-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L GND #PWR01 -U 1 1 51909AF0 -P 6700 3550 -F 0 "#PWR01" H 6700 3550 30 0001 C CNN -F 1 "GND" H 6700 3480 30 0001 C CNN - 1 6700 3550 - 1 0 0 -1 -$EndComp -Connection ~ 6500 3550 -Wire Wire Line - 6500 3550 6700 3550 -Wire Wire Line - 4800 3600 4150 3600 -Wire Wire Line - 6500 2050 5100 2050 -Wire Wire Line - 5100 5100 5100 5250 -Wire Wire Line - 5100 3800 5100 3950 -Wire Wire Line - 5100 3250 5100 3400 -Wire Wire Line - 5100 2650 5100 2750 -Wire Wire Line - 5100 4450 5100 4600 -Wire Wire Line - 5100 2050 5100 2150 -Connection ~ 5100 3350 -Connection ~ 5100 3900 -Wire Wire Line - 3650 3600 3650 5100 -Connection ~ 5100 2050 -Connection ~ 5100 2050 -Connection ~ 5100 2050 -Wire Wire Line - 5100 5250 6500 5250 -Connection ~ 4750 3600 -Connection ~ 3650 3600 -Connection ~ 4150 3600 -Connection ~ 3950 3600 -Connection ~ 4800 3600 -Connection ~ 3650 4850 -Wire Wire Line - 6500 2950 6500 4350 -$Comp -L DC v2 -U 1 1 51909ACB -P 6500 4800 -F 0 "v2" H 6300 4900 60 0000 C CNN -F 1 "5" H 6300 4750 60 0000 C CNN -F 2 "R1" H 6200 4800 60 0000 C CNN - 1 6500 4800 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516C1E89 -P 3650 4850 -F 0 "#FLG02" H 3650 5120 30 0001 C CNN -F 1 "PWR_FLAG" H 3650 5080 30 0000 C CNN - 1 3650 4850 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 516C1EFD -P 4750 3300 -F 0 "U2" H 4600 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 4900 3400 50 0000 C CNN - 1 4750 3300 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516C1E7B -P 3650 5100 -F 0 "#PWR03" H 3650 5100 30 0001 C CNN -F 1 "GND" H 3650 5030 30 0001 C CNN - 1 3650 5100 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516C1E56 -P 3900 3600 -F 0 "R1" V 3980 3600 50 0000 C CNN -F 1 "10000" V 3900 3600 50 0000 C CNN - 1 3900 3600 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 3 1 516C1E37 -P 5400 3900 -F 0 "U2" H 5250 4000 50 0000 C CNN -F 1 "VPLOT8_1" H 5550 4000 50 0000 C CNN - 3 5400 3900 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 516C1E04 -P 5100 4850 -F 0 "R3" V 5180 4850 50 0000 C CNN -F 1 "10000" V 5100 4850 50 0000 C CNN - 1 5100 4850 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516C1DF8 -P 5100 4200 -F 0 "U4" H 4950 4300 50 0000 C CNN -F 1 "IPLOT" H 5250 4300 50 0000 C CNN - 1 5100 4200 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 516C1DCB -P 5400 3350 -F 0 "U2" H 5250 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 5550 3450 50 0000 C CNN - 2 5400 3350 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516C1DBD -P 6500 2500 -F 0 "v1" H 6300 2600 60 0000 C CNN -F 1 "5" H 6300 2450 60 0000 C CNN -F 2 "R1" H 6200 2500 60 0000 C CNN - 1 6500 2500 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516C1DAD -P 5100 3000 -F 0 "U3" H 4950 3100 50 0000 C CNN -F 1 "IPLOT" H 5250 3100 50 0000 C CNN - 1 5100 3000 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 516C1D7F -P 5100 2400 -F 0 "R2" V 5180 2400 50 0000 C CNN -F 1 "1000" V 5100 2400 50 0000 C CNN - 1 5100 2400 - 1 0 0 -1 -$EndComp -$Comp -L PNP Q1 -U 1 1 516C1D57 -P 5000 3600 -F 0 "Q1" H 5000 3450 60 0000 R CNN -F 1 "PNP" H 5000 3750 60 0000 R CNN - 1 5000 3600 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/npn.lib deleted file mode 100644 index caa3cb7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_3/npn.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 -+ Cje=4.493p Isc=0 Xtb=1.5 Rb=10 Rc=1 -+ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 -+ Ise=6.734f Br=.7371 Ikf=66.78m Mje=.2593 Mjc=.3085 -+ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=2 Itf=.4 -+ Is=6.734 Eg=1.11 )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib deleted file mode 100644 index 89d421d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib +++ /dev/null @@ -1,2 +0,0 @@ -.model 1n4007 D( IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1E-11 -+VJ=0.7 M=0.5 FC=0.5 TT=1E-07 KF=0 AF=1 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis deleted file mode 100644 index f74e3c8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt deleted file mode 100644 index 0552575..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt +++ /dev/null @@ -1,22 +0,0 @@ -* CD4007 NMOS and PMOS transistor SPICE models - -* Typical - Typical Condition - -.model mos_n NMOS -+ Level=1 Gamma= 0 Xj=0 -+ Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=1.4 Lambda=0.01 -+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p -+ Cgdo=0.1p Is=16.64p N=1 - -*The default W and L is 30 and 10 um respectively and AD and AS -*should not be included. - - -.model mos_p PMOS -+ Level=1 Gamma= 0 Xj=0 -+ Tox=1200n Phi=.6 Rs=0 Kp=1u Vto=-1.2 Lambda=0.04 -+ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p -+ Cgdo=0.2p Is=16.64p N=1 - -*The default W and L is 60 and 10 um respectively and AD and AS -*should not be included. diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak deleted file mode 100644 index 5cb1eee..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak +++ /dev/null @@ -1,110 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 16 May 2013 11:39:19 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# MOS_N -# -DEF MOS_N M 0 0 N Y 1 F N -F0 "M" 10 170 60 H V R CNN -F1 "MOS_N" 10 -150 60 H V R CNN -ALIAS MOSFET_N -DRAW -P 2 0 1 8 -50 -100 -50 100 N -P 2 0 1 10 0 -150 0 150 N -P 2 0 1 0 100 -100 0 -100 N -P 2 0 1 0 100 100 0 100 N -P 3 0 1 8 100 -100 100 0 50 0 N -P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N -X D D 100 200 100 D 40 40 1 1 P -X G G -200 0 150 R 40 40 1 1 I -X S S 100 -200 100 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib deleted file mode 100644 index df97081..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib +++ /dev/null @@ -1,110 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 16 May 2013 11:43:16 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# MOS_N -# -DEF MOS_N M 0 0 N Y 1 F N -F0 "M" 10 170 60 H V R CNN -F1 "MOS_N" 10 -150 60 H V R CNN -ALIAS MOSFET_N -DRAW -P 2 0 1 8 -50 -100 -50 100 N -P 2 0 1 10 0 -150 0 150 N -P 2 0 1 0 100 -100 0 -100 N -P 2 0 1 0 100 100 0 100 N -P 3 0 1 8 100 -100 100 0 50 0 N -P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N -X D D 100 200 100 D 40 40 1 1 P -X G G -200 0 150 R 40 40 1 1 I -X S S 100 -200 100 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak deleted file mode 100644 index c4bf9b0..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak +++ /dev/null @@ -1,214 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 16 May 2013 11:39:19 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_4.5-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 6600 3650 -$Comp -L VPLOT8_1 U4 -U 2 1 519477A9 -P 6900 3650 -F 0 "U4" H 6750 3750 50 0000 C CNN -F 1 "VPLOT8_1" H 7050 3750 50 0000 C CNN - 2 6900 3650 - 0 1 1 0 -$EndComp -Wire Wire Line - 6600 4350 6600 4700 -Wire Wire Line - 5800 5500 5800 5550 -Wire Wire Line - 6600 2700 6600 3000 -Connection ~ 5800 5500 -Wire Wire Line - 5000 2850 5000 850 -Connection ~ 5700 850 -Wire Wire Line - 5000 850 6600 850 -Connection ~ 5700 3200 -Wire Wire Line - 5700 5500 5700 5200 -Wire Wire Line - 5700 1200 5700 850 -Wire Wire Line - 6600 850 6600 1200 -Wire Wire Line - 6600 5200 6600 5500 -Wire Wire Line - 6300 3200 5700 3200 -Connection ~ 5700 3200 -Connection ~ 6600 2850 -Connection ~ 6600 850 -Connection ~ 6600 5500 -Wire Wire Line - 5700 4700 5700 1700 -Wire Wire Line - 6600 5500 5000 5500 -Connection ~ 5700 5500 -Wire Wire Line - 5000 5500 5000 3750 -Wire Wire Line - 6600 1700 6600 2200 -Wire Wire Line - 6600 3400 6600 3800 -$Comp -L IPLOT U2 -U 1 1 51947793 -P 6600 4050 -F 0 "U2" H 6450 4150 50 0000 C CNN -F 1 "IPLOT" H 6750 4150 50 0000 C CNN - 1 6600 4050 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 518B75C0 -P 6600 2450 -F 0 "U1" H 6450 2550 50 0000 C CNN -F 1 "IPLOT" H 6750 2550 50 0000 C CNN - 1 6600 2450 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U4 -U 1 1 518B74B3 -P 6000 3200 -F 0 "U4" H 5850 3300 50 0000 C CNN -F 1 "VPLOT8_1" H 6150 3300 50 0000 C CNN - 1 6000 3200 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR01 -U 1 1 517A3B91 -P 5800 5550 -F 0 "#PWR01" H 5800 5550 30 0001 C CNN -F 1 "GND" H 5800 5480 30 0001 C CNN - 1 5800 5550 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 517A3B8C -P 5800 5500 -F 0 "#FLG02" H 5800 5770 30 0001 C CNN -F 1 "PWR_FLAG" H 5800 5730 30 0000 C CNN - 1 5800 5500 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 517A3ABD -P 5000 3300 -F 0 "v1" H 4800 3400 60 0000 C CNN -F 1 "10" H 4800 3250 60 0000 C CNN -F 2 "R1" H 4700 3300 60 0000 C CNN - 1 5000 3300 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516BA47D -P 6900 2850 -F 0 "U3" H 6750 2950 50 0000 C CNN -F 1 "VPLOT8_1" H 7050 2950 50 0000 C CNN - 1 6900 2850 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5166F1C0 -P 5700 4950 -F 0 "R2" V 5780 4950 50 0000 C CNN -F 1 "10M" V 5700 4950 50 0000 C CNN - 1 5700 4950 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166F1AE -P 5700 1450 -F 0 "R1" V 5780 1450 50 0000 C CNN -F 1 "10M" V 5700 1450 50 0000 C CNN - 1 5700 1450 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 5166F187 -P 6600 4950 -F 0 "R4" V 6680 4950 50 0000 C CNN -F 1 "6k" V 6600 4950 50 0000 C CNN - 1 6600 4950 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 5166F163 -P 6600 1450 -F 0 "R3" V 6680 1450 50 0000 C CNN -F 1 "6k" V 6600 1450 50 0000 C CNN - 1 6600 1450 - 1 0 0 -1 -$EndComp -$Comp -L MOS_N M1 -U 1 1 5166F12C -P 6500 3200 -F 0 "M1" H 6510 3370 60 0000 R CNN -F 1 "MOS_N" H 6510 3050 60 0000 R CNN - 1 6500 3200 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir deleted file mode 100644 index 4a904e0..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir +++ /dev/null @@ -1,18 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 16 May 2013 11:43:12 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U4 6 7 VPLOT8_1 -U2 7 4 IPLOT -U1 5 1 IPLOT -v1 3 0 10 -U3 1 VPLOT8_1 -R2 6 0 10M -R1 3 6 10M -R4 4 0 6k -R3 3 5 6k -M1 1 6 7 MOS_N - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt deleted file mode 100644 index 68ce4e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt +++ /dev/null @@ -1,19 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:43:12 am ist - -* Plotting option vplot8_1 -V_u2 7 4 0 -V_u1 5 1 0 -v1 3 0 10 -* Plotting option vplot8_1 -r2 6 0 10m -r1 3 6 10m -r4 4 0 6k -r3 3 5 6k -m1 1 6 7 mos_n - -.dc v1 0e-00 10e-00 1e-00 -.plot v(6) v(7) -.plot i(V_u2) -.plot i(V_u1) -.plot v(1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out deleted file mode 100644 index b363435..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:43:12 am ist - -* Plotting option vplot8_1 -V_u2 7 4 0 -V_u1 5 1 0 -v1 3 0 10 -* Plotting option vplot8_1 -r2 6 0 10m -r1 3 6 10m -r4 4 0 6k -r3 3 5 6k -m1 1 6 7 mos_n - -.dc v1 0e-00 10e-00 1e-00 - -* Control Statements -.control -run -plot v(6) v(7) -plot i(V_u2) -plot i(V_u1) -plot v(1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro deleted file mode 100644 index 2585a32..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro +++ /dev/null @@ -1,84 +0,0 @@ -update=Tuesday 07 May 2013 02:38:55 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/ambikeshwar/OSCAD/library/analogSpice -LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice -LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice -LibName34=/home/ambikeshwar/OSCAD/library/converterSpice -LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice -LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice -LibName37=/home/ambikeshwar/OSCAD/library/linearSpice -LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice -LibName39=/home/ambikeshwar/OSCAD/library/portSpice -LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice -LibName41=/home/holy/OSCAD/library/analogSpice -LibName42=/home/holy/OSCAD/library/analogXSpice -LibName43=/home/holy/OSCAD/library/convergenceAidSpice -LibName44=/home/holy/OSCAD/library/converterSpice -LibName45=/home/holy/OSCAD/library/digitalSpice -LibName46=/home/holy/OSCAD/library/digitalXSpice -LibName47=/home/holy/OSCAD/library/linearSpice -LibName48=/home/holy/OSCAD/library/measurementSpice -LibName49=/home/holy/OSCAD/library/portSpice -LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj deleted file mode 100644 index 2320ec1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_4.5.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch deleted file mode 100644 index a1406f4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch +++ /dev/null @@ -1,214 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 16 May 2013 11:43:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_4.5-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 6600 4300 6600 4700 -Wire Wire Line - 6600 3400 6600 3800 -Wire Wire Line - 6600 1700 6600 2200 -Wire Wire Line - 5000 3750 5000 5500 -Connection ~ 5700 5500 -Wire Wire Line - 5000 5500 6600 5500 -Wire Wire Line - 5700 4700 5700 1700 -Connection ~ 6600 5500 -Connection ~ 6600 850 -Connection ~ 6600 2850 -Connection ~ 5700 3200 -Wire Wire Line - 6300 3200 5700 3200 -Wire Wire Line - 6600 5500 6600 5200 -Wire Wire Line - 6600 1200 6600 850 -Wire Wire Line - 5700 1200 5700 850 -Wire Wire Line - 5700 5500 5700 5200 -Connection ~ 5700 3200 -Wire Wire Line - 6600 850 5000 850 -Connection ~ 5700 850 -Wire Wire Line - 5000 850 5000 2850 -Connection ~ 5800 5500 -Wire Wire Line - 6600 2700 6600 3000 -Wire Wire Line - 5800 5500 5800 5550 -Connection ~ 6600 3650 -$Comp -L VPLOT8_1 U4 -U 2 1 519477A9 -P 6900 3650 -F 0 "U4" H 6750 3750 50 0000 C CNN -F 1 "VPLOT8_1" H 7050 3750 50 0000 C CNN - 2 6900 3650 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 51947793 -P 6600 4050 -F 0 "U2" H 6450 4150 50 0000 C CNN -F 1 "IPLOT" H 6750 4150 50 0000 C CNN - 1 6600 4050 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 518B75C0 -P 6600 2450 -F 0 "U1" H 6450 2550 50 0000 C CNN -F 1 "IPLOT" H 6750 2550 50 0000 C CNN - 1 6600 2450 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U4 -U 1 1 518B74B3 -P 6000 3200 -F 0 "U4" H 5850 3300 50 0000 C CNN -F 1 "VPLOT8_1" H 6150 3300 50 0000 C CNN - 1 6000 3200 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR01 -U 1 1 517A3B91 -P 5800 5550 -F 0 "#PWR01" H 5800 5550 30 0001 C CNN -F 1 "GND" H 5800 5480 30 0001 C CNN - 1 5800 5550 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 517A3B8C -P 5800 5500 -F 0 "#FLG02" H 5800 5770 30 0001 C CNN -F 1 "PWR_FLAG" H 5800 5730 30 0000 C CNN - 1 5800 5500 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 517A3ABD -P 5000 3300 -F 0 "v1" H 4800 3400 60 0000 C CNN -F 1 "10" H 4800 3250 60 0000 C CNN -F 2 "R1" H 4700 3300 60 0000 C CNN - 1 5000 3300 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516BA47D -P 6900 2850 -F 0 "U3" H 6750 2950 50 0000 C CNN -F 1 "VPLOT8_1" H 7050 2950 50 0000 C CNN - 1 6900 2850 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5166F1C0 -P 5700 4950 -F 0 "R2" V 5780 4950 50 0000 C CNN -F 1 "10M" V 5700 4950 50 0000 C CNN - 1 5700 4950 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5166F1AE -P 5700 1450 -F 0 "R1" V 5780 1450 50 0000 C CNN -F 1 "10M" V 5700 1450 50 0000 C CNN - 1 5700 1450 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 5166F187 -P 6600 4950 -F 0 "R4" V 6680 4950 50 0000 C CNN -F 1 "6k" V 6600 4950 50 0000 C CNN - 1 6600 4950 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 5166F163 -P 6600 1450 -F 0 "R3" V 6680 1450 50 0000 C CNN -F 1 "6k" V 6600 1450 50 0000 C CNN - 1 6600 1450 - 1 0 0 -1 -$EndComp -$Comp -L MOS_N M1 -U 1 1 5166F12C -P 6500 3200 -F 0 "M1" H 6510 3370 60 0000 R CNN -F 1 "MOS_N" H 6510 3050 60 0000 R CNN - 1 6500 3200 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis deleted file mode 100644 index 1665db7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 100e-03 100e-06 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak deleted file mode 100644 index 7a3e4b4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak +++ /dev/null @@ -1,126 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 09 May 2013 05:04:50 PM IST -#encoding utf-8 -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# LM741 -# -DEF LM741 U 0 20 Y Y 1 F N -F0 "U" 150 150 60 H V C CNN -F1 "LM741" 150 250 60 H V C CNN -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X ~ 1 0 -400 300 U 40 40 1 1 I -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X V- 4 -100 -400 250 U 40 40 1 1 I -X ~ 5 100 -400 350 U 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -X V+ 7 -100 400 250 D 40 40 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib deleted file mode 100644 index 5b4c901..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 10:18:21 AM IST -#encoding utf-8 -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak deleted file mode 100644 index abf9a53..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak +++ /dev/null @@ -1,181 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 09 May 2013 05:04:50 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "9 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L LM741 U? -U 1 1 518B89AE -P 8800 3550 -F 0 "U?" H 8950 3700 60 0000 C CNN -F 1 "LM741" H 8950 3800 60 0000 C CNN - 1 8800 3550 - 1 0 0 -1 -$EndComp -$Comp -L UA741 X? -U 1 1 518B899E -P 9050 2450 -F 0 "X?" H 9200 2600 60 0000 C CNN -F 1 "UA741" H 9200 2700 60 0000 C CNN - 1 9050 2450 - 1 0 0 -1 -$EndComp -$Comp -L SINE v1 -U 1 1 516F84E1 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "SINE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7150 3300 6350 3300 -Wire Wire Line - 5300 2400 5300 3200 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 4200 5350 3400 -Connection ~ 5300 3200 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 6900 2400 7050 2400 -Wire Wire Line - 7050 2400 7050 3300 -Wire Wire Line - 6400 2400 5800 2400 -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7050 3600 -F 0 "U3" H 6900 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN - 1 7050 3600 - -1 0 0 1 -$EndComp -$Comp -L PWR_FLAG #FLG1 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG1" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2400 -F 0 "U2" H 5400 2500 50 0000 C CNN -F 1 "IPLOT" H 5700 2500 50 0000 C CNN - 1 5550 2400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6650 2400 -F 0 "R2" V 6730 2400 50 0000 C CNN -F 1 "10000" V 6650 2400 50 0000 C CNN - 1 6650 2400 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR1 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR1" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir deleted file mode 100644 index d11b7e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir +++ /dev/null @@ -1,24 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:42:46 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v1 4 0 PULSE -v2 11 0 10V -U3 8 3 VPLOT8_1 -R5 13 3 10000 -R4 0 13 10000 -R3 1 11 10000 -U5 8 2 IPLOT -Q2 1 1 2 NPN -X2 1 13 3 UA741 -U4 10 8 IPLOT -Q1 10 0 9 NPN -U1 6 7 IPLOT -U2 7 9 IPLOT -R2 8 5 10000 -R1 6 4 1000 -X1 7 0 5 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt deleted file mode 100644 index db0e45e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt +++ /dev/null @@ -1,16 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist -.include ua741.sub - -* Plotting option vplot8_1 -V_u1 6 5 0 -V_u2 5 4 0 -r2 1 4 100000 -v1 3 0 100m -r1 6 3 1000 -x1 5 0 1 ua741 - -.dc v1 0e-00 100e-03 100e-06 -.plot v(1) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out deleted file mode 100644 index d01be76..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out +++ /dev/null @@ -1,21 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist -.include ua741.sub - -* Plotting option vplot8_1 -V_u1 6 5 0 -V_u2 5 4 0 -r2 1 4 100000 -v1 3 0 100m -r1 6 3 1000 -x1 5 0 1 ua741 - -.dc v1 0e-00 100e-03 100e-06 - -* Control Statements -.control -run -plot v(1) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net deleted file mode 100644 index 6696e60..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net +++ /dev/null @@ -1,76 +0,0 @@ -# EESchema Netlist Version 1.1 created Thursday 18 April 2013 11:00:24 AM IST -( - ( /516F84E1 R1 v1 SINE {Lib=SINE} - ( 1 N-000005 ) - ( 2 GND ) - ) - ( /516D117B $noname U3 VPLOT8_1 {Lib=VPLOT8_1} - ( 1 N-000004 ) - ) - ( /516D1019 $noname U1 IPLOT {Lib=IPLOT} - ( 1 N-000002 ) - ( 2 N-000003 ) - ) - ( /516D0FEC $noname U2 IPLOT {Lib=IPLOT} - ( 1 N-000003 ) - ( 2 N-000001 ) - ) - ( /516D0FE2 $noname R2 10000 {Lib=R} - ( 1 N-000004 ) - ( 2 N-000001 ) - ) - ( /516D0F10 $noname R1 1000 {Lib=R} - ( 1 N-000002 ) - ( 2 N-000005 ) - ) - ( /516D0E60 $noname X1 UA741 {Lib=UA741} - ( 2 N-000003 ) - ( 3 GND ) - ( 6 N-000004 ) - ) -) -* -{ Allowed footprints by component: -$component v1 - 1_pin -$endlist -$component R2 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R1 - R? - SM0603 - SM0805 - R?-* -$endlist -$component X1 - DIP-8__300 -$endlist -$endfootprintlist -} -{ Pin List by Nets -Net 1 "" "" - R2 2 - U2 2 -Net 2 "" "" - R1 1 - U1 1 -Net 3 "" "" - X1 2 - U2 1 - U1 2 -Net 4 "" "" - U3 1 - R2 1 - X1 6 -Net 5 "" "" - v1 1 - R1 2 -Net 6 "GND" "GND" - X1 3 - v1 2 -} -#End diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro deleted file mode 100644 index 2d33bde..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 02:06:21 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj deleted file mode 100644 index fb6ad90..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch deleted file mode 100644 index 9267154..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch +++ /dev/null @@ -1,163 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 10:18:21 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L SINE v1 -U 1 1 516F84E1 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "SINE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7150 3300 6350 3300 -Wire Wire Line - 5300 2400 5300 3200 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 4200 5350 3400 -Connection ~ 5300 3200 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 6900 2400 7050 2400 -Wire Wire Line - 7050 2400 7050 3300 -Wire Wire Line - 6400 2400 5800 2400 -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7050 3600 -F 0 "U3" H 6900 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN - 1 7050 3600 - -1 0 0 1 -$EndComp -$Comp -L PWR_FLAG #FLG1 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG1" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2400 -F 0 "U2" H 5400 2500 50 0000 C CNN -F 1 "IPLOT" H 5700 2500 50 0000 C CNN - 1 5550 2400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6650 2400 -F 0 "R2" V 6730 2400 50 0000 C CNN -F 1 "10000" V 6650 2400 50 0000 C CNN - 1 6650 2400 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR1 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR1" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib deleted file mode 100644 index e9ec641..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 02:55:26 PM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro deleted file mode 100644 index 46bdf8d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Tuesday 16 April 2013 02:56:39 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice -LibName39=/home/holy/OSCAD/library/analogSpice -LibName40=/home/holy/OSCAD/library/analogXSpice -LibName41=/home/holy/OSCAD/library/convergenceAidSpice -LibName42=/home/holy/OSCAD/library/converterSpice -LibName43=/home/holy/OSCAD/library/digitalSpice -LibName44=/home/holy/OSCAD/library/digitalXSpice -LibName45=/home/holy/OSCAD/library/linearSpice -LibName46=/home/holy/OSCAD/library/measurementSpice -LibName47=/home/holy/OSCAD/library/portSpice -LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis deleted file mode 100644 index 63f4a40..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis +++ /dev/null @@ -1,8 +0,0 @@ - -.ac lin 20 1Hz 10Meg - - -.end -.control -run -.endc diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak deleted file mode 100644 index 3c7e9ce..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak +++ /dev/null @@ -1,97 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Sunday 12 May 2013 08:39:09 PM IST -#encoding utf-8 -# -# AC -# -DEF AC AC 0 40 Y Y 1 F N -F0 "AC" -200 100 60 H V C CNN -F1 "AC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib deleted file mode 100644 index 1541b6a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib +++ /dev/null @@ -1,97 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:50:16 PM IST -#encoding utf-8 -# -# AC -# -DEF AC AC 0 40 Y Y 1 F N -F0 "AC" -200 100 60 H V C CNN -F1 "AC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak deleted file mode 100644 index 7d24c57..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak +++ /dev/null @@ -1,143 +0,0 @@ -EESchema Schematic File Version 2 date Sunday 12 May 2013 08:39:09 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.10-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "12 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5200 3800 -$Comp -L VPLOT8_1 U1 -U 1 1 51877E04 -P 5200 4100 -F 0 "U1" H 5050 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 5350 4200 50 0000 C CNN - 1 5200 4100 - -1 0 0 1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 51877DFD -P 6500 3400 -F 0 "U1" H 6350 3500 50 0000 C CNN -F 1 "VPLOT8_1" H 6650 3500 50 0000 C CNN - 2 6500 3400 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 51877DEF -P 4850 4700 -F 0 "#FLG01" H 4850 4970 30 0001 C CNN -F 1 "PWR_FLAG" H 4850 4930 30 0000 C CNN - 1 4850 4700 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 51877DE4 -P 4850 4850 -F 0 "#PWR02" H 4850 4850 30 0001 C CNN -F 1 "GND" H 4850 4780 30 0001 C CNN - 1 4850 4850 - 1 0 0 -1 -$EndComp -Connection ~ 4850 4700 -Wire Wire Line - 4850 4700 4850 4850 -Connection ~ 6350 3700 -Wire Wire Line - 6500 3700 6250 3700 -Wire Wire Line - 5050 3800 5250 3800 -Wire Wire Line - 5250 3600 5050 3600 -Wire Wire Line - 5150 3600 5150 3200 -Connection ~ 5150 3600 -Wire Wire Line - 5150 3200 6350 3200 -Wire Wire Line - 6350 3200 6350 3700 -Wire Wire Line - 4550 3600 4550 4700 -Wire Wire Line - 4550 4700 5050 4700 -$Comp -L AC V1 -U 1 1 51877DB5 -P 5050 4250 -F 0 "V1" H 4850 4350 60 0000 C CNN -F 1 "AC" H 4850 4200 60 0000 C CNN -F 2 "R1" H 4750 4250 60 0000 C CNN - 1 5050 4250 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 51877DA4 -P 4800 3600 -F 0 "R1" V 4880 3600 50 0000 C CNN -F 1 "R" V 4800 3600 50 0000 C CNN - 1 4800 3600 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 51877D93 -P 5750 3700 -F 0 "X1" H 5900 3850 60 0000 C CNN -F 1 "UA741" H 5900 3950 60 0000 C CNN - 1 5750 3700 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir deleted file mode 100644 index 103691f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir +++ /dev/null @@ -1,13 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:50:12 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -R2 1 4 100k -U1 3 1 VPLOT8_1 -V1 3 0 AC -R1 4 0 1k -X1 3 4 1 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt deleted file mode 100644 index b3db0c4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt +++ /dev/null @@ -1,12 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:50:12 pm ist -.include ua741.sub - -r2 1 4 100k -* Plotting option vplot8_1 -v1 3 0 ac 1 -r1 4 0 1k -x1 3 4 1 ua741 - -.ac lin 10 1Hz 1Meg -.plot v(3) v(1) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out deleted file mode 100644 index 3554667..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:50:12 pm ist -.include ua741.sub - -r2 1 4 100k -* Plotting option vplot8_1 -v1 3 0 ac 1 -r1 4 0 1k -x1 3 4 1 ua741 - -.ac lin 10 1Hz 1Meg - -* Control Statements -.control -run -plot v(3) v(1) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro deleted file mode 100644 index 77913bc..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 06 May 2013 03:19:21 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.proj deleted file mode 100644 index 81a471e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.10.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.sch deleted file mode 100644 index 8601e68..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.sch +++ /dev/null @@ -1,154 +0,0 @@ -EESchema Schematic File Version 2 date Monday 13 May 2013 01:50:16 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.10-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "13 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 6000 3200 6350 3200 -Connection ~ 5200 3800 -Connection ~ 4850 4700 -Wire Wire Line - 4850 4700 4850 4850 -Connection ~ 6350 3700 -Wire Wire Line - 6500 3700 6250 3700 -Wire Wire Line - 5050 3800 5250 3800 -Wire Wire Line - 5250 3600 5050 3600 -Wire Wire Line - 5150 3600 5150 3200 -Connection ~ 5150 3600 -Wire Wire Line - 6350 3200 6350 3700 -Wire Wire Line - 4550 3600 4550 4700 -Wire Wire Line - 4550 4700 5050 4700 -Wire Wire Line - 5150 3200 5500 3200 -$Comp -L R R2 -U 1 1 5190A20F -P 5750 3200 -F 0 "R2" V 5830 3200 50 0000 C CNN -F 1 "100k" V 5750 3200 50 0000 C CNN - 1 5750 3200 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 51877E04 -P 5200 4100 -F 0 "U1" H 5050 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 5350 4200 50 0000 C CNN - 1 5200 4100 - -1 0 0 1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 51877DFD -P 6500 3400 -F 0 "U1" H 6350 3500 50 0000 C CNN -F 1 "VPLOT8_1" H 6650 3500 50 0000 C CNN - 2 6500 3400 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG1 -U 1 1 51877DEF -P 4850 4700 -F 0 "#FLG1" H 4850 4970 30 0001 C CNN -F 1 "PWR_FLAG" H 4850 4930 30 0000 C CNN - 1 4850 4700 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR1 -U 1 1 51877DE4 -P 4850 4850 -F 0 "#PWR1" H 4850 4850 30 0001 C CNN -F 1 "GND" H 4850 4780 30 0001 C CNN - 1 4850 4850 - 1 0 0 -1 -$EndComp -$Comp -L AC V1 -U 1 1 51877DB5 -P 5050 4250 -F 0 "V1" H 4850 4350 60 0000 C CNN -F 1 "AC" H 4850 4200 60 0000 C CNN -F 2 "R1" H 4750 4250 60 0000 C CNN - 1 5050 4250 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 51877DA4 -P 4800 3600 -F 0 "R1" V 4880 3600 50 0000 C CNN -F 1 "1k" V 4800 3600 50 0000 C CNN - 1 4800 3600 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 51877D93 -P 5750 3700 -F 0 "X1" H 5900 3850 60 0000 C CNN -F 1 "UA741" H 5900 3950 60 0000 C CNN - 1 5750 3700 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak deleted file mode 100644 index 696ddb5..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak +++ /dev/null @@ -1,116 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 07 May 2013 04:32:37 PM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 0 -50 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# VCCS -# -DEF VCCS G 0 40 Y Y 1 F N -F0 "G" -200 100 50 H V C CNN -F1 "VCCS" -200 -50 50 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib deleted file mode 100644 index 4ffd70b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib +++ /dev/null @@ -1,116 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 08 May 2013 02:27:06 PM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 0 -50 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# VCCS -# -DEF VCCS G 0 40 Y Y 1 F N -F0 "G" -200 100 50 H V C CNN -F1 "VCCS" -200 -50 50 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro deleted file mode 100644 index e55b2df..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Sunday 12 May 2013 08:34:27 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice -LibName39=/home/holy/OSCAD/library/analogSpice -LibName40=/home/holy/OSCAD/library/analogXSpice -LibName41=/home/holy/OSCAD/library/convergenceAidSpice -LibName42=/home/holy/OSCAD/library/converterSpice -LibName43=/home/holy/OSCAD/library/digitalSpice -LibName44=/home/holy/OSCAD/library/digitalXSpice -LibName45=/home/holy/OSCAD/library/linearSpice -LibName46=/home/holy/OSCAD/library/measurementSpice -LibName47=/home/holy/OSCAD/library/portSpice -LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis deleted file mode 100644 index 7946c35..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib deleted file mode 100644 index 40f51d7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib +++ /dev/null @@ -1,107 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 03:05:48 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak deleted file mode 100644 index 9eb4b13..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak +++ /dev/null @@ -1,171 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 02:59:48 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 6400 3350 6400 2950 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 4200 5350 3400 -Connection ~ 5300 3200 -Wire Wire Line - 5300 2950 5300 3200 -Wire Wire Line - 5350 3200 5250 3200 -Connection ~ 6400 3300 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Wire Wire Line - 6350 3300 6400 3300 -Connection ~ 6350 3300 -Connection ~ 6400 3350 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG01" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 6700 3350 -F 0 "U3" H 6550 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 6850 3450 50 0000 C CNN - 1 6700 3350 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG02" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "100000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516D0FD3 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "100m" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR03" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir deleted file mode 100644 index b0ee189..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir +++ /dev/null @@ -1,19 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 03:05:45 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U5 3 8 IPLOT -U4 2 VPLOT8_1 -R3 0 2 100000 -R4 3 2 100000 -U3 8 VPLOT8_1 -U1 6 4 IPLOT -U2 4 5 IPLOT -R2 2 5 100000 -v1 7 0 100m -R1 6 7 1000 -X1 4 0 8 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt deleted file mode 100644 index ea512f4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 03:05:45 pm ist -.include ua741.sub - -V_u5 3 8 0 -* Plotting option vplot8_1 -r3 0 2 100000 -r4 3 2 100000 -* Plotting option vplot8_1 -V_u1 6 4 0 -V_u2 4 5 0 -r2 2 5 100000 -v1 7 0 100m -r1 6 7 1000 -x1 4 0 8 ua741 - -.dc v1 0e-00 5e-00 5e-03 -.plot i(V_u5) -.plot v(2) -.plot v(8) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out deleted file mode 100644 index fdcc306..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out +++ /dev/null @@ -1,27 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 03:05:45 pm ist -.include ua741.sub - -V_u5 3 8 0 -* Plotting option vplot8_1 -r3 0 2 100000 -r4 3 2 100000 -* Plotting option vplot8_1 -V_u1 6 4 0 -V_u2 4 5 0 -r2 2 5 100000 -v1 7 0 100m -r1 6 7 1000 -x1 4 0 8 ua741 - -.dc v1 0e-00 5e-00 5e-03 - -* Control Statements -.control -run -plot i(V_u5) -plot v(2) -plot v(8) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro deleted file mode 100644 index 4197879..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 02:59:20 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj deleted file mode 100644 index e56c1d2..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.2.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch deleted file mode 100644 index 5dbaecc..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch +++ /dev/null @@ -1,224 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 16 April 2013 03:05:48 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 7000 3000 7000 3350 -Connection ~ 7000 2400 -Connection ~ 6450 2500 -Connection ~ 6450 2400 -Wire Wire Line - 6350 3300 7000 3300 -Wire Wire Line - 6450 2900 6450 3000 -Connection ~ 7000 3350 -Connection ~ 6350 3300 -Connection ~ 5350 4100 -Wire Wire Line - 4150 3200 4050 3200 -Wire Wire Line - 5900 2400 5800 2400 -Connection ~ 7000 3300 -Wire Wire Line - 5350 3200 5250 3200 -Connection ~ 5300 3200 -Wire Wire Line - 5350 4200 5350 3400 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 6400 2400 6500 2400 -Wire Wire Line - 5300 2400 5300 3200 -Wire Wire Line - 7000 2400 7000 2500 -$Comp -L IPLOT U5 -U 1 1 516D1AB3 -P 7000 2750 -F 0 "U5" H 6850 2850 50 0000 C CNN -F 1 "IPLOT" H 7150 2850 50 0000 C CNN - 1 7000 2750 - 0 1 1 0 -$EndComp -$Comp -L VPLOT8_1 U4 -U 1 1 516D1A8F -P 6450 2100 -F 0 "U4" H 6300 2200 50 0000 C CNN -F 1 "VPLOT8_1" H 6600 2200 50 0000 C CNN - 1 6450 2100 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR01 -U 1 1 516D1A5C -P 6450 3000 -F 0 "#PWR01" H 6450 3000 30 0001 C CNN -F 1 "GND" H 6450 2930 30 0001 C CNN - 1 6450 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 516D1A47 -P 6450 2650 -F 0 "R3" V 6530 2650 50 0000 C CNN -F 1 "100000" V 6450 2650 50 0000 C CNN - 1 6450 2650 - -1 0 0 1 -$EndComp -$Comp -L R R4 -U 1 1 516D1A3E -P 6750 2400 -F 0 "R4" V 6830 2400 50 0000 C CNN -F 1 "100000" V 6750 2400 50 0000 C CNN - 1 6750 2400 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG02" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7300 3350 -F 0 "U3" H 7150 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 7450 3450 50 0000 C CNN - 1 7300 3350 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG03 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG03" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2400 -F 0 "U2" H 5400 2500 50 0000 C CNN -F 1 "IPLOT" H 5700 2500 50 0000 C CNN - 1 5550 2400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2400 -F 0 "R2" V 6230 2400 50 0000 C CNN -F 1 "100000" V 6150 2400 50 0000 C CNN - 1 6150 2400 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516D0FD3 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "100m" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR04 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR04" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro deleted file mode 100644 index 34303c7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Tuesday 16 April 2013 03:06:44 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice -LibName39=/home/holy/OSCAD/library/analogSpice -LibName40=/home/holy/OSCAD/library/analogXSpice -LibName41=/home/holy/OSCAD/library/convergenceAidSpice -LibName42=/home/holy/OSCAD/library/converterSpice -LibName43=/home/holy/OSCAD/library/digitalSpice -LibName44=/home/holy/OSCAD/library/digitalXSpice -LibName45=/home/holy/OSCAD/library/linearSpice -LibName46=/home/holy/OSCAD/library/measurementSpice -LibName47=/home/holy/OSCAD/library/portSpice -LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis deleted file mode 100644 index 7946c35..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak deleted file mode 100644 index e6f6afe..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak +++ /dev/null @@ -1,107 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 09:35:11 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib deleted file mode 100644 index 4daeb80..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib +++ /dev/null @@ -1,107 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 21 May 2013 11:13:50 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak deleted file mode 100644 index d0ef6de..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak +++ /dev/null @@ -1,182 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 15 May 2013 09:35:11 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 7050 3300 7050 2950 -Wire Wire Line - 6450 3300 6350 3300 -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 3400 5350 4200 -Connection ~ 5300 3200 -Wire Wire Line - 5300 2950 5300 3200 -Wire Wire Line - 5250 3200 5350 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 7050 3300 6950 3300 -Wire Wire Line - 7050 2950 6400 2950 -$Comp -L R R3 -U 1 1 516D1D5E -P 6700 3300 -F 0 "R3" V 6780 3300 50 0000 C CNN -F 1 "100k" V 6700 3300 50 0000 C CNN - 1 6700 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG01" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7350 3300 -F 0 "U3" H 7200 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN - 1 7350 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG02" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "1000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516D0FD3 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "10" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR03" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "10" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir deleted file mode 100644 index 25f7e67..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir +++ /dev/null @@ -1,16 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 09:29:30 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -R3 1 7 100k -U3 1 VPLOT8_1 -U1 5 2 IPLOT -U2 2 3 IPLOT -R2 1 3 1000 -v1 6 0 10 -R1 5 6 10 -X1 2 0 7 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt deleted file mode 100644 index 5cc8d66..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 09:29:30 pm ist -.include ua741.sub - -r3 1 7 100k -* Plotting option vplot8_1 -V_u1 5 2 0 -V_u2 2 3 0 -r2 1 3 1000 -v1 6 0 10 -r1 5 6 10 -x1 2 0 7 ua741 - -.dc v1 0e-00 5e-00 5e-03 -.plot v(1) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out deleted file mode 100644 index 1d3b745..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 09:29:30 pm ist -.include ua741.sub - -r3 1 7 100k -* Plotting option vplot8_1 -V_u1 5 2 0 -V_u2 2 3 0 -r2 1 3 1000 -v1 6 0 10 -r1 5 6 10 -x1 2 0 7 ua741 - -.dc v1 0e-00 5e-00 5e-03 - -* Control Statements -.control -run -plot v(1) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro deleted file mode 100644 index 68ef472..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 03:20:48 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj deleted file mode 100644 index 36f23a8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.3.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch deleted file mode 100644 index a549a57..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch +++ /dev/null @@ -1,183 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 21 May 2013 11:13:50 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.3-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "21 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 7050 3300 7050 2950 -Wire Wire Line - 6450 3300 6350 3300 -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 3400 5350 4200 -Connection ~ 5300 3200 -Wire Wire Line - 5300 2950 5300 3200 -Wire Wire Line - 5250 3200 5350 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 7050 3300 6950 3300 -Wire Wire Line - 7050 2950 6400 2950 -$Comp -L R RL -U 1 1 516D1D5E -P 6700 3300 -F 0 "RL" V 6780 3300 50 0000 C CNN -F 1 "100k" V 6700 3300 50 0000 C CNN - 1 6700 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG01" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7350 3300 -F 0 "U3" H 7200 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN - 1 7350 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG02" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R Rf -U 1 1 516D0FE2 -P 6150 2950 -F 0 "Rf" V 6230 2950 50 0000 C CNN -F 1 "1000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 516D0FD3 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "10" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR03" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "10" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro deleted file mode 100644 index 1f35813..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Wednesday 15 May 2013 09:42:35 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice -LibName39=/home/holy/OSCAD/library/analogSpice -LibName40=/home/holy/OSCAD/library/analogXSpice -LibName41=/home/holy/OSCAD/library/convergenceAidSpice -LibName42=/home/holy/OSCAD/library/converterSpice -LibName43=/home/holy/OSCAD/library/digitalSpice -LibName44=/home/holy/OSCAD/library/digitalXSpice -LibName45=/home/holy/OSCAD/library/linearSpice -LibName46=/home/holy/OSCAD/library/measurementSpice -LibName47=/home/holy/OSCAD/library/portSpice -LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis deleted file mode 100644 index 35318bb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak deleted file mode 100644 index c4ca8fc..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak +++ /dev/null @@ -1,107 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:43:16 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib deleted file mode 100644 index 18a7cf4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib +++ /dev/null @@ -1,107 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:47:25 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak deleted file mode 100644 index f68a6c8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak +++ /dev/null @@ -1,345 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:43:16 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "17 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 1400 6300 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D2826 -P 1400 6300 -F 0 "#FLG01" H 1400 6570 30 0001 C CNN -F 1 "PWR_FLAG" H 1400 6530 30 0000 C CNN - 1 1400 6300 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516D27F8 -P 1400 6450 -F 0 "#PWR02" H 1400 6450 30 0001 C CNN -F 1 "GND" H 1400 6380 30 0001 C CNN - 1 1400 6450 - 1 0 0 -1 -$EndComp -Connection ~ 1400 6100 -Wire Wire Line - 1400 6100 1400 6450 -Connection ~ 2400 3250 -Connection ~ 4500 3450 -Connection ~ 4500 4400 -Connection ~ 6750 3900 -Wire Wire Line - 5100 4700 5100 4850 -Wire Wire Line - 1600 5200 1600 5000 -Wire Wire Line - 1600 5000 2400 5000 -Connection ~ 3650 4900 -Wire Wire Line - 3900 4400 3900 4900 -Wire Wire Line - 3900 4900 3400 4900 -Connection ~ 2400 4500 -Wire Wire Line - 2400 4500 2600 4500 -Wire Wire Line - 3650 3000 3650 3550 -Wire Wire Line - 3650 3550 3100 3550 -Wire Wire Line - 2400 4250 2400 4800 -Wire Wire Line - 6750 3900 6750 3950 -Wire Wire Line - 6750 3950 6150 3950 -Wire Wire Line - 5300 3350 5100 3350 -Connection ~ 5100 3850 -Wire Wire Line - 5100 3350 5100 3850 -Wire Wire Line - 4400 3450 4550 3450 -Wire Wire Line - 4550 3450 4550 3850 -Wire Wire Line - 5150 3850 5050 3850 -Wire Wire Line - 5150 4050 5050 4050 -Wire Wire Line - 4550 4050 4550 4400 -Wire Wire Line - 4550 4400 4400 4400 -Wire Wire Line - 5800 3350 5950 3350 -Wire Wire Line - 6450 3350 6450 3950 -Connection ~ 6450 3950 -Wire Wire Line - 2400 3750 2400 3100 -Wire Wire Line - 2400 3550 2600 3550 -Connection ~ 2400 3550 -Wire Wire Line - 3400 3000 3900 3000 -Wire Wire Line - 3900 3000 3900 3450 -Connection ~ 3650 3000 -Wire Wire Line - 3100 4500 3650 4500 -Wire Wire Line - 3650 4500 3650 4900 -Wire Wire Line - 2400 2900 1150 2900 -Wire Wire Line - 1150 2900 1150 3600 -Wire Wire Line - 5100 4050 5100 4200 -Connection ~ 5100 4050 -Wire Wire Line - 1150 4500 1150 6100 -Wire Wire Line - 1150 6100 1600 6100 -$Comp -L DC v2 -U 1 1 516D27D5 -P 1600 5650 -F 0 "v2" H 1400 5750 60 0000 C CNN -F 1 "DC" H 1400 5600 60 0000 C CNN -F 2 "R1" H 1300 5650 60 0000 C CNN - 1 1600 5650 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 516D27D0 -P 1150 4050 -F 0 "v1" H 950 4150 60 0000 C CNN -F 1 "DC" H 950 4000 60 0000 C CNN -F 2 "R1" H 850 4050 60 0000 C CNN - 1 1150 4050 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 516D27AE -P 2400 4200 -F 0 "U1" H 2250 4300 50 0000 C CNN -F 1 "VPLOT8_1" H 2550 4300 50 0000 C CNN - 2 2400 4200 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 516D27A5 -P 2400 3250 -F 0 "U1" H 2250 3350 50 0000 C CNN -F 1 "VPLOT8_1" H 2550 3350 50 0000 C CNN - 1 2400 3250 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 5 1 516D278E -P 6750 3600 -F 0 "U1" H 6600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 6900 3700 50 0000 C CNN - 5 6750 3600 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 4 1 516D2789 -P 4500 4100 -F 0 "U1" H 4350 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 4650 4200 50 0000 C CNN - 4 4500 4100 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 3 1 516D2785 -P 4500 3150 -F 0 "U1" H 4350 3250 50 0000 C CNN -F 1 "VPLOT8_1" H 4650 3250 50 0000 C CNN - 3 4500 3150 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D274C -P 5100 4850 -F 0 "#PWR03" H 5100 4850 30 0001 C CNN -F 1 "GND" H 5100 4780 30 0001 C CNN - 1 5100 4850 - 1 0 0 -1 -$EndComp -$Comp -L R R6 -U 1 1 516D2736 -P 5100 4450 -F 0 "R6" V 5180 4450 50 0000 C CNN -F 1 "R" V 5100 4450 50 0000 C CNN - 1 5100 4450 - -1 0 0 1 -$EndComp -$Comp -L R R3 -U 1 1 516D26F4 -P 2850 4500 -F 0 "R3" V 2930 4500 50 0000 C CNN -F 1 "R" V 2850 4500 50 0000 C CNN - 1 2850 4500 - 0 -1 -1 0 -$EndComp -$Comp -L R R2 -U 1 1 516D26CE -P 2850 3550 -F 0 "R2" V 2930 3550 50 0000 C CNN -F 1 "R" V 2850 3550 50 0000 C CNN - 1 2850 3550 - 0 -1 -1 0 -$EndComp -$Comp -L R R1 -U 1 1 516D26AE -P 2400 4000 -F 0 "R1" V 2480 4000 50 0000 C CNN -F 1 "R" V 2400 4000 50 0000 C CNN - 1 2400 4000 - -1 0 0 1 -$EndComp -$Comp -L R R7 -U 1 1 516D268C -P 6200 3350 -F 0 "R7" V 6280 3350 50 0000 C CNN -F 1 "R" V 6200 3350 50 0000 C CNN - 1 6200 3350 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516D267F -P 5550 3350 -F 0 "U4" H 5400 3450 50 0000 C CNN -F 1 "IPLOT" H 5700 3450 50 0000 C CNN - 1 5550 3350 - 1 0 0 -1 -$EndComp -$Comp -L UA741 X2 -U 1 1 516D2661 -P 2900 4900 -F 0 "X2" H 3050 5050 60 0000 C CNN -F 1 "UA741" H 3050 5150 60 0000 C CNN - 1 2900 4900 - 1 0 0 1 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D2656 -P 2900 3000 -F 0 "X1" H 3050 3150 60 0000 C CNN -F 1 "UA741" H 3050 3250 60 0000 C CNN - 1 2900 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516D264E -P 4150 4400 -F 0 "U3" H 4000 4500 50 0000 C CNN -F 1 "IPLOT" H 4300 4500 50 0000 C CNN - 1 4150 4400 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D2648 -P 4150 3450 -F 0 "U2" H 4000 3550 50 0000 C CNN -F 1 "IPLOT" H 4300 3550 50 0000 C CNN - 1 4150 3450 - 1 0 0 -1 -$EndComp -$Comp -L R R5 -U 1 1 516D2600 -P 4800 4050 -F 0 "R5" V 4880 4050 50 0000 C CNN -F 1 "R" V 4800 4050 50 0000 C CNN - 1 4800 4050 - 0 1 1 0 -$EndComp -$Comp -L R R4 -U 1 1 516D25EC -P 4800 3850 -F 0 "R4" V 4880 3850 50 0000 C CNN -F 1 "R" V 4800 3850 50 0000 C CNN - 1 4800 3850 - 0 1 1 0 -$EndComp -$Comp -L UA741 X3 -U 1 1 516D25CD -P 5650 3950 -F 0 "X3" H 5800 4100 60 0000 C CNN -F 1 "UA741" H 5800 4200 60 0000 C CNN - 1 5650 3950 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir deleted file mode 100644 index 4788ef3..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir +++ /dev/null @@ -1,24 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 17 April 2013 12:47:21 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v2 5 0 10V -v1 9 0 20V -U1 3 4 6 2 11 VPLOT8_1 -R6 0 7 R -R3 4 12 R -R2 3 8 R -R1 4 3 R -R7 11 10 R -U4 13 10 IPLOT -X2 4 5 12 UA741 -X1 3 9 8 UA741 -U3 12 2 IPLOT -U2 8 6 IPLOT -R5 7 2 R -R4 13 6 R -X3 13 7 11 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt deleted file mode 100644 index 2fc3967..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt +++ /dev/null @@ -1,26 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:47:21 pm ist -.include ua741.sub - -v2 5 0 10v -v1 9 0 20v -* Plotting option vplot8_1 -r6 0 7 r -r3 4 12 r -r2 3 8 r -r1 4 3 r -r7 11 10 r -V_u4 13 10 0 -x2 4 5 12 ua741 -x1 3 9 8 ua741 -V_u3 12 2 0 -V_u2 8 6 0 -r5 7 2 r -r4 13 6 r -x3 13 7 11 ua741 - -.dc v1 0e-00 10e-00 5e-03 -.plot v(3) v(4) v(6) v(2) v(11) -.plot i(V_u4) -.plot i(V_u3) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out deleted file mode 100644 index 98912a5..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out +++ /dev/null @@ -1,31 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:47:21 pm ist -.include ua741.sub - -v2 5 0 10v -v1 9 0 20v -* Plotting option vplot8_1 -r6 0 7 r -r3 4 12 r -r2 3 8 r -r1 4 3 r -r7 11 10 r -V_u4 13 10 0 -x2 4 5 12 ua741 -x1 3 9 8 ua741 -V_u3 12 2 0 -V_u2 8 6 0 -r5 7 2 r -r4 13 6 r -x3 13 7 11 ua741 - -.dc v1 0e-00 10e-00 5e-03 - -* Control Statements -.control -run -plot v(3) v(4) v(6) v(2) v(11) -plot i(V_u4) -plot i(V_u3) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro deleted file mode 100644 index ac34f0e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 16 April 2013 03:49:31 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj deleted file mode 100644 index 799253b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch deleted file mode 100644 index 8b83c0d..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch +++ /dev/null @@ -1,345 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:47:25 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "17 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 1400 6300 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D2826 -P 1400 6300 -F 0 "#FLG01" H 1400 6570 30 0001 C CNN -F 1 "PWR_FLAG" H 1400 6530 30 0000 C CNN - 1 1400 6300 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516D27F8 -P 1400 6450 -F 0 "#PWR02" H 1400 6450 30 0001 C CNN -F 1 "GND" H 1400 6380 30 0001 C CNN - 1 1400 6450 - 1 0 0 -1 -$EndComp -Connection ~ 1400 6100 -Wire Wire Line - 1400 6100 1400 6450 -Connection ~ 2400 3250 -Connection ~ 4500 3450 -Connection ~ 4500 4400 -Connection ~ 6750 3900 -Wire Wire Line - 5100 4700 5100 4850 -Wire Wire Line - 1600 5200 1600 5000 -Wire Wire Line - 1600 5000 2400 5000 -Connection ~ 3650 4900 -Wire Wire Line - 3900 4400 3900 4900 -Wire Wire Line - 3900 4900 3400 4900 -Connection ~ 2400 4500 -Wire Wire Line - 2400 4500 2600 4500 -Wire Wire Line - 3650 3000 3650 3550 -Wire Wire Line - 3650 3550 3100 3550 -Wire Wire Line - 2400 4250 2400 4800 -Wire Wire Line - 6750 3900 6750 3950 -Wire Wire Line - 6750 3950 6150 3950 -Wire Wire Line - 5300 3350 5100 3350 -Connection ~ 5100 3850 -Wire Wire Line - 5100 3350 5100 3850 -Wire Wire Line - 4400 3450 4550 3450 -Wire Wire Line - 4550 3450 4550 3850 -Wire Wire Line - 5150 3850 5050 3850 -Wire Wire Line - 5150 4050 5050 4050 -Wire Wire Line - 4550 4050 4550 4400 -Wire Wire Line - 4550 4400 4400 4400 -Wire Wire Line - 5800 3350 5950 3350 -Wire Wire Line - 6450 3350 6450 3950 -Connection ~ 6450 3950 -Wire Wire Line - 2400 3750 2400 3100 -Wire Wire Line - 2400 3550 2600 3550 -Connection ~ 2400 3550 -Wire Wire Line - 3400 3000 3900 3000 -Wire Wire Line - 3900 3000 3900 3450 -Connection ~ 3650 3000 -Wire Wire Line - 3100 4500 3650 4500 -Wire Wire Line - 3650 4500 3650 4900 -Wire Wire Line - 2400 2900 1150 2900 -Wire Wire Line - 1150 2900 1150 3600 -Wire Wire Line - 5100 4050 5100 4200 -Connection ~ 5100 4050 -Wire Wire Line - 1150 4500 1150 6100 -Wire Wire Line - 1150 6100 1600 6100 -$Comp -L DC v2 -U 1 1 516D27D5 -P 1600 5650 -F 0 "v2" H 1400 5750 60 0000 C CNN -F 1 "10V" H 1400 5600 60 0000 C CNN -F 2 "R1" H 1300 5650 60 0000 C CNN - 1 1600 5650 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 516D27D0 -P 1150 4050 -F 0 "v1" H 950 4150 60 0000 C CNN -F 1 "20V" H 950 4000 60 0000 C CNN -F 2 "R1" H 850 4050 60 0000 C CNN - 1 1150 4050 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 516D27AE -P 2400 4200 -F 0 "U1" H 2250 4300 50 0000 C CNN -F 1 "VPLOT8_1" H 2550 4300 50 0000 C CNN - 2 2400 4200 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 516D27A5 -P 2400 3250 -F 0 "U1" H 2250 3350 50 0000 C CNN -F 1 "VPLOT8_1" H 2550 3350 50 0000 C CNN - 1 2400 3250 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 5 1 516D278E -P 6750 3600 -F 0 "U1" H 6600 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 6900 3700 50 0000 C CNN - 5 6750 3600 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 4 1 516D2789 -P 4500 4100 -F 0 "U1" H 4350 4200 50 0000 C CNN -F 1 "VPLOT8_1" H 4650 4200 50 0000 C CNN - 4 4500 4100 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 3 1 516D2785 -P 4500 3150 -F 0 "U1" H 4350 3250 50 0000 C CNN -F 1 "VPLOT8_1" H 4650 3250 50 0000 C CNN - 3 4500 3150 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D274C -P 5100 4850 -F 0 "#PWR03" H 5100 4850 30 0001 C CNN -F 1 "GND" H 5100 4780 30 0001 C CNN - 1 5100 4850 - 1 0 0 -1 -$EndComp -$Comp -L R R6 -U 1 1 516D2736 -P 5100 4450 -F 0 "R6" V 5180 4450 50 0000 C CNN -F 1 "R" V 5100 4450 50 0000 C CNN - 1 5100 4450 - -1 0 0 1 -$EndComp -$Comp -L R R3 -U 1 1 516D26F4 -P 2850 4500 -F 0 "R3" V 2930 4500 50 0000 C CNN -F 1 "R" V 2850 4500 50 0000 C CNN - 1 2850 4500 - 0 -1 -1 0 -$EndComp -$Comp -L R R2 -U 1 1 516D26CE -P 2850 3550 -F 0 "R2" V 2930 3550 50 0000 C CNN -F 1 "R" V 2850 3550 50 0000 C CNN - 1 2850 3550 - 0 -1 -1 0 -$EndComp -$Comp -L R R1 -U 1 1 516D26AE -P 2400 4000 -F 0 "R1" V 2480 4000 50 0000 C CNN -F 1 "R" V 2400 4000 50 0000 C CNN - 1 2400 4000 - -1 0 0 1 -$EndComp -$Comp -L R R7 -U 1 1 516D268C -P 6200 3350 -F 0 "R7" V 6280 3350 50 0000 C CNN -F 1 "R" V 6200 3350 50 0000 C CNN - 1 6200 3350 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516D267F -P 5550 3350 -F 0 "U4" H 5400 3450 50 0000 C CNN -F 1 "IPLOT" H 5700 3450 50 0000 C CNN - 1 5550 3350 - 1 0 0 -1 -$EndComp -$Comp -L UA741 X2 -U 1 1 516D2661 -P 2900 4900 -F 0 "X2" H 3050 5050 60 0000 C CNN -F 1 "UA741" H 3050 5150 60 0000 C CNN - 1 2900 4900 - 1 0 0 1 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D2656 -P 2900 3000 -F 0 "X1" H 3050 3150 60 0000 C CNN -F 1 "UA741" H 3050 3250 60 0000 C CNN - 1 2900 3000 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U3 -U 1 1 516D264E -P 4150 4400 -F 0 "U3" H 4000 4500 50 0000 C CNN -F 1 "IPLOT" H 4300 4500 50 0000 C CNN - 1 4150 4400 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D2648 -P 4150 3450 -F 0 "U2" H 4000 3550 50 0000 C CNN -F 1 "IPLOT" H 4300 3550 50 0000 C CNN - 1 4150 3450 - 1 0 0 -1 -$EndComp -$Comp -L R R5 -U 1 1 516D2600 -P 4800 4050 -F 0 "R5" V 4880 4050 50 0000 C CNN -F 1 "R" V 4800 4050 50 0000 C CNN - 1 4800 4050 - 0 1 1 0 -$EndComp -$Comp -L R R4 -U 1 1 516D25EC -P 4800 3850 -F 0 "R4" V 4880 3850 50 0000 C CNN -F 1 "R" V 4800 3850 50 0000 C CNN - 1 4800 3850 - 0 1 1 0 -$EndComp -$Comp -L UA741 X3 -U 1 1 516D25CD -P 5650 3950 -F 0 "X3" H 5800 4100 60 0000 C CNN -F 1 "UA741" H 5800 4200 60 0000 C CNN - 1 5650 3950 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro deleted file mode 100644 index 0d94955..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Wednesday 17 April 2013 12:46:01 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice -LibName39=/home/holy/OSCAD/library/analogSpice -LibName40=/home/holy/OSCAD/library/analogXSpice -LibName41=/home/holy/OSCAD/library/convergenceAidSpice -LibName42=/home/holy/OSCAD/library/converterSpice -LibName43=/home/holy/OSCAD/library/digitalSpice -LibName44=/home/holy/OSCAD/library/digitalXSpice -LibName45=/home/holy/OSCAD/library/linearSpice -LibName46=/home/holy/OSCAD/library/measurementSpice -LibName47=/home/holy/OSCAD/library/portSpice -LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis deleted file mode 100644 index c9183fa..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak deleted file mode 100644 index 79f0251..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 11:57:44 AM IST -#encoding utf-8 -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib deleted file mode 100644 index 951b224..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib +++ /dev/null @@ -1,109 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:50:53 PM IST -#encoding utf-8 -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak deleted file mode 100644 index 9eaa078..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak +++ /dev/null @@ -1,171 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 17 April 2013 11:57:44 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "17 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L SINE v1 -U 1 1 516E3BC9 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "SINE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 6350 3300 7050 3300 -Wire Wire Line - 6400 2950 7050 2950 -Connection ~ 7050 3300 -Connection ~ 6350 3300 -Connection ~ 5350 4100 -Wire Wire Line - 4150 3200 4050 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 5300 2950 5300 3200 -Connection ~ 5300 3200 -Wire Wire Line - 5350 4200 5350 3400 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 7050 2950 7050 3300 -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG01" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7350 3300 -F 0 "U3" H 7200 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN - 1 7350 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG02" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "9000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR03" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir deleted file mode 100644 index cbcca2f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir +++ /dev/null @@ -1,16 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 17 April 2013 12:50:50 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -R3 6 0 1000 -v1 5 0 SINE -U3 6 VPLOT8_1 -U1 4 2 IPLOT -U2 2 3 IPLOT -R2 6 3 9000 -R1 4 5 1000 -X1 2 0 6 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt deleted file mode 100644 index 6843d47..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist -.include ua741.sub - -r3 6 0 1000 -v1 5 0 sine(0 5 50 0 0) -* Plotting option vplot8_1 -V_u1 4 2 0 -V_u2 2 3 0 -r2 6 3 9000 -r1 4 5 1000 -x1 2 0 6 ua741 - -.tran 10e-03 20e-03 0e-00 -.plot v(6) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out deleted file mode 100644 index 9e60789..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist -.include ua741.sub - -r3 6 0 1000 -v1 5 0 sine(0 5 50 0 0) -* Plotting option vplot8_1 -V_u1 4 2 0 -V_u2 2 3 0 -r2 6 3 9000 -r1 4 5 1000 -x1 2 0 6 ua741 - -.tran 10e-03 20e-03 0e-00 - -* Control Statements -.control -run -plot v(6) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro deleted file mode 100644 index ead436b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Wednesday 17 April 2013 11:37:31 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj deleted file mode 100644 index 8554126..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.6.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch deleted file mode 100644 index 73864f6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch +++ /dev/null @@ -1,183 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:50:53 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.6-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "17 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 4050 4100 7050 4100 -Wire Wire Line - 7050 4100 7050 4000 -Wire Wire Line - 7050 3300 6350 3300 -Wire Wire Line - 6400 2950 7050 2950 -Connection ~ 7050 3300 -Connection ~ 6350 3300 -Connection ~ 5350 4100 -Wire Wire Line - 4150 3200 4050 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 5300 2950 5300 3200 -Connection ~ 5300 3200 -Wire Wire Line - 5350 4200 5350 3400 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 7050 2950 7050 3500 -$Comp -L R R3 -U 1 1 516E4D07 -P 7050 3750 -F 0 "R3" V 7130 3750 50 0000 C CNN -F 1 "1000" V 7050 3750 50 0000 C CNN - 1 7050 3750 - 1 0 0 -1 -$EndComp -$Comp -L SINE v1 -U 1 1 516E3BC9 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "SINE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG01" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7350 3300 -F 0 "U3" H 7200 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN - 1 7350 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG02" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "9000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR03" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro deleted file mode 100644 index 1235eb1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Wednesday 17 April 2013 12:51:39 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice -LibName39=/home/holy/OSCAD/library/analogSpice -LibName40=/home/holy/OSCAD/library/analogXSpice -LibName41=/home/holy/OSCAD/library/convergenceAidSpice -LibName42=/home/holy/OSCAD/library/converterSpice -LibName43=/home/holy/OSCAD/library/digitalSpice -LibName44=/home/holy/OSCAD/library/digitalXSpice -LibName45=/home/holy/OSCAD/library/linearSpice -LibName46=/home/holy/OSCAD/library/measurementSpice -LibName47=/home/holy/OSCAD/library/portSpice -LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis deleted file mode 100644 index 234e759..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis +++ /dev/null @@ -1,8 +0,0 @@ - -.ac lin 10 1Hz 1Meg - - -.end -.control -run -.endc diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak deleted file mode 100644 index bef6862..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak +++ /dev/null @@ -1,127 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 10:40:53 PM IST -#encoding utf-8 -# -# AC -# -DEF AC AC 0 40 Y Y 1 F N -F0 "AC" -200 100 60 H V C CNN -F1 "AC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib deleted file mode 100644 index a99ee60..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib +++ /dev/null @@ -1,127 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 10:41:23 PM IST -#encoding utf-8 -# -# AC -# -DEF AC AC 0 40 Y Y 1 F N -F0 "AC" -200 100 60 H V C CNN -F1 "AC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak deleted file mode 100644 index 5b65555..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak +++ /dev/null @@ -1,210 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 15 May 2013 10:40:53 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.7-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L AC AC1 -U 1 1 5193C186 -P 4050 3650 -F 0 "AC1" H 3850 3750 60 0000 C CNN -F 1 "AC" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7050 3500 7050 2950 -Connection ~ 6500 2950 -Wire Wire Line - 6500 2950 6500 2550 -Wire Wire Line - 6500 2550 6300 2550 -Connection ~ 5300 2950 -Wire Wire Line - 5300 2550 5300 3200 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 4200 5350 3400 -Connection ~ 5300 3200 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 7050 2950 6400 2950 -Wire Wire Line - 6350 3300 7050 3300 -Wire Wire Line - 5800 2550 5900 2550 -Wire Wire Line - 4050 4100 7050 4100 -Wire Wire Line - 7050 4100 7050 4000 -Connection ~ 7050 3400 -$Comp -L R R3 -U 1 1 516E71B7 -P 7050 3750 -F 0 "R3" V 7130 3750 50 0000 C CNN -F 1 "R" V 7050 3750 50 0000 C CNN - 1 7050 3750 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG2 -U 1 1 516E6E61 -P 5350 4100 -F 0 "#FLG2" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - -1 0 0 1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516E6E43 -P 7350 3400 -F 0 "U3" H 7200 3500 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3500 50 0000 C CNN - 1 7350 3400 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG1 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG1" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L C C1 -U 1 1 516E6B62 -P 6100 2550 -F 0 "C1" H 6150 2650 50 0000 L CNN -F 1 "1.59n" H 6150 2450 50 0000 L CNN - 1 6100 2550 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516E6B56 -P 5550 2550 -F 0 "U4" H 5400 2650 50 0000 C CNN -F 1 "IPLOT" H 5700 2650 50 0000 C CNN - 1 5550 2550 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "10000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR1 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR1" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir deleted file mode 100644 index 944330f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir +++ /dev/null @@ -1,18 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 10:41:20 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v1 6 0 AC -R3 7 0 R -U3 7 VPLOT8_1 -C1 7 3 1.59n -U4 1 3 IPLOT -U1 5 1 IPLOT -U2 1 4 IPLOT -R2 7 4 10000 -R1 5 6 1000 -X1 1 0 7 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt deleted file mode 100644 index 28de072..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 10:41:20 pm ist -.include ua741.sub - -v1 6 0 ac 1 -r3 7 0 r -* Plotting option vplot8_1 -c1 7 3 1.59n -V_u4 1 3 0 -V_u1 5 1 0 -V_u2 1 4 0 -r2 7 4 10000 -r1 5 6 1000 -x1 1 0 7 ua741 - -.ac lin 10 1Hz 1Meg -.plot v(7) -.plot i(V_u4) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out deleted file mode 100644 index 9002bf8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out +++ /dev/null @@ -1,25 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 10:41:20 pm ist -.include ua741.sub - -v1 6 0 ac 1 -r3 7 0 r -* Plotting option vplot8_1 -c1 7 3 1.59n -V_u4 1 3 0 -V_u1 5 1 0 -V_u2 1 4 0 -r2 7 4 10000 -r1 5 6 1000 -x1 1 0 7 ua741 - -.ac lin 10 1Hz 1Meg - -* Control Statements -.control -run -plot v(7) -plot i(V_u4) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro deleted file mode 100644 index a2b4ce1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Wednesday 17 April 2013 12:56:50 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj deleted file mode 100644 index 304c734..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.7.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch deleted file mode 100644 index d7677e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch +++ /dev/null @@ -1,210 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 15 May 2013 10:41:23 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.7-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "15 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L AC v1 -U 1 1 5193C186 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "AC" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7050 3500 7050 2950 -Connection ~ 6500 2950 -Wire Wire Line - 6500 2950 6500 2550 -Wire Wire Line - 6500 2550 6300 2550 -Connection ~ 5300 2950 -Wire Wire Line - 5300 2550 5300 3200 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 4200 5350 3400 -Connection ~ 5300 3200 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 7050 2950 6400 2950 -Wire Wire Line - 6350 3300 7050 3300 -Wire Wire Line - 5800 2550 5900 2550 -Wire Wire Line - 4050 4100 7050 4100 -Wire Wire Line - 7050 4100 7050 4000 -Connection ~ 7050 3400 -$Comp -L R R3 -U 1 1 516E71B7 -P 7050 3750 -F 0 "R3" V 7130 3750 50 0000 C CNN -F 1 "R" V 7050 3750 50 0000 C CNN - 1 7050 3750 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516E6E61 -P 5350 4100 -F 0 "#FLG01" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - -1 0 0 1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516E6E43 -P 7350 3400 -F 0 "U3" H 7200 3500 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3500 50 0000 C CNN - 1 7350 3400 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG02" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L C C1 -U 1 1 516E6B62 -P 6100 2550 -F 0 "C1" H 6150 2650 50 0000 L CNN -F 1 "1.59n" H 6150 2450 50 0000 L CNN - 1 6100 2550 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516E6B56 -P 5550 2550 -F 0 "U4" H 5400 2650 50 0000 C CNN -F 1 "IPLOT" H 5700 2650 50 0000 C CNN - 1 5550 2550 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "10000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR03" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro deleted file mode 100644 index 9aa118e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro +++ /dev/null @@ -1,72 +0,0 @@ -update=Monday 17 December 2012 06:14:06 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis deleted file mode 100644 index 64c6d69..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 1e-03 2e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch deleted file mode 100644 index d6f19aa..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch +++ /dev/null @@ -1,172 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 17 April 2013 05:15:51 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "17 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 6350 3300 7050 3300 -Wire Wire Line - 6400 2950 7050 2950 -Connection ~ 7050 3300 -Connection ~ 6350 3300 -Connection ~ 5350 4100 -Wire Wire Line - 4150 3200 4050 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 5300 2950 5300 3200 -Connection ~ 5300 3200 -Wire Wire Line - 5350 4200 5350 3400 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 7050 2950 7050 3300 -$Comp -L SINE v1 -U 1 1 516E3AE9 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "SINE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG01" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7350 3300 -F 0 "U3" H 7200 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN - 1 7350 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG02" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "10000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR03 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR03" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak deleted file mode 100644 index 969d8ac..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak +++ /dev/null @@ -1,157 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 18 April 2013 09:19:41 AM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# pulse -# -DEF pulse v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "pulse" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -25 -450 501 928 871 0 1 0 N -50 50 0 50 -A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 -A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 -A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 -A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 -A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8 -# -DEF vplot8 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -300 0 200 R 40 40 1 1 O -X - 9 300 0 200 L 40 40 1 1 O -X + 2 -300 0 200 R 40 40 2 1 O -X - 10 300 0 200 L 40 40 2 1 O -X + 3 -300 0 200 R 40 40 3 1 O -X - 11 300 0 200 L 40 40 3 1 O -X + 4 -300 0 200 R 40 40 4 1 O -X - 12 300 0 200 L 40 40 4 1 O -X + 5 -300 0 200 R 40 40 5 1 O -X - 13 300 0 200 L 40 40 5 1 O -X + 6 -300 0 200 R 40 40 6 1 O -X - 14 300 0 200 L 40 40 6 1 O -X + 7 -300 0 200 R 40 40 7 1 O -X - 15 300 0 200 L 40 40 7 1 O -X + 8 -300 0 200 R 40 40 8 1 O -X - 16 300 0 200 L 40 40 8 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib deleted file mode 100644 index 32852ba..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib +++ /dev/null @@ -1,157 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 18 April 2013 10:25:50 AM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# iplot -# -DEF iplot U 0 20 Y Y 1 F N -F0 "U" -150 100 50 H V C CNN -F1 "iplot" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -250 0 150 R 30 30 1 1 I -X - 2 250 0 150 L 30 30 1 1 I -ENDDRAW -ENDDEF -# -# pulse -# -DEF pulse v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "pulse" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -25 -450 501 928 871 0 1 0 N -50 50 0 50 -A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 -A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 -A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 -A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 -A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# uA741 -# -DEF uA741 X 0 20 Y Y 1 F N -F0 "X" 150 150 60 H V C CNN -F1 "uA741" 150 250 60 H V C CNN -$FPLIST - DIP-8__300 -$ENDFPLIST -DRAW -P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N -X - 2 -500 -100 300 R 40 40 1 1 I -X + 3 -500 100 300 R 40 40 1 1 I -X ~ 6 500 0 300 L 40 40 1 1 O -ENDDRAW -ENDDEF -# -# vplot8 -# -DEF vplot8 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -300 0 200 R 40 40 1 1 O -X - 9 300 0 200 L 40 40 1 1 O -X + 2 -300 0 200 R 40 40 2 1 O -X - 10 300 0 200 L 40 40 2 1 O -X + 3 -300 0 200 R 40 40 3 1 O -X - 11 300 0 200 L 40 40 3 1 O -X + 4 -300 0 200 R 40 40 4 1 O -X - 12 300 0 200 L 40 40 4 1 O -X + 5 -300 0 200 R 40 40 5 1 O -X - 13 300 0 200 L 40 40 5 1 O -X + 6 -300 0 200 R 40 40 6 1 O -X - 14 300 0 200 L 40 40 6 1 O -X + 7 -300 0 200 R 40 40 7 1 O -X - 15 300 0 200 L 40 40 7 1 O -X + 8 -300 0 200 R 40 40 8 1 O -X - 16 300 0 200 L 40 40 8 1 O -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak deleted file mode 100644 index a102621..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 18 April 2013 09:19:41 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.8-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "18 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 3300 3700 3300 4300 -Wire Wire Line - 3300 3100 3300 2850 -Wire Wire Line - 3300 2850 4200 2850 -Wire Wire Line - 4200 2850 4200 3200 -Wire Wire Line - 5800 2600 5900 2600 -Wire Wire Line - 4050 4100 5350 4100 -Wire Wire Line - 6350 3300 7050 3300 -Wire Wire Line - 7050 2950 6400 2950 -Connection ~ 7050 3300 -Connection ~ 6350 3300 -Connection ~ 5350 4100 -Wire Wire Line - 4150 3200 4050 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 5250 3200 5350 3200 -Connection ~ 5300 3200 -Wire Wire Line - 5350 3400 5350 4200 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5300 3200 5300 2600 -Connection ~ 5300 2950 -Wire Wire Line - 6300 2600 7050 2600 -Wire Wire Line - 7050 2600 7050 3300 -Connection ~ 7050 2950 -Connection ~ 4100 3200 -Wire Wire Line - 4250 4100 4250 4300 -Connection ~ 4250 4100 -Wire Wire Line - 4250 4300 3300 4300 -$Comp -L VPLOT8 U5 -U 1 1 516F6D28 -P 3300 3400 -F 0 "U5" H 3150 3500 50 0000 C CNN -F 1 "VPLOT8" H 3450 3500 50 0000 C CNN - 1 3300 3400 - 0 1 1 0 -$EndComp -$Comp -L PULSE v1 -U 1 1 516E8CD4 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "PULSE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L C C1 -U 1 1 516E8BE7 -P 6100 2600 -F 0 "C1" H 6150 2700 50 0000 L CNN -F 1 "10n" H 6150 2500 50 0000 L CNN - 1 6100 2600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516E8BCF -P 5550 2600 -F 0 "U4" H 5400 2700 50 0000 C CNN -F 1 "IPLOT" H 5700 2700 50 0000 C CNN - 1 5550 2600 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG2 -U 1 1 516D11A2 -P 5350 4100 -F 0 "#FLG2" H 5350 4370 30 0001 C CNN -F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN - 1 5350 4100 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7350 3300 -F 0 "U3" H 7200 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN - 1 7350 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG1 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG1" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "1000000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR1 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR1" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "10000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir deleted file mode 100644 index b53502b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir +++ /dev/null @@ -1,18 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:25:46 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U5 5 0 VPLOT8 -v1 5 0 PULSE -C1 6 1 10n -U4 2 1 IPLOT -U3 6 VPLOT8_1 -U1 4 2 IPLOT -U2 2 3 IPLOT -R2 6 3 1000000 -R1 4 5 10000 -X1 2 0 6 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt deleted file mode 100644 index 63570ef..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:25:46 am ist -.include ua741.sub - -v1 5 0 pulse(1 0 0 0 0 0.001 0.002) -c1 6 1 10n -V_u4 2 1 0 -* Plotting option vplot8_1 -V_u1 4 2 0 -V_u2 2 3 0 -r2 6 3 1000000 -r1 4 5 10000 -x1 2 0 6 ua741 - -.tran 1e-03 2e-03 0e-00 -.plot v(5) -.plot i(V_u4) -.plot v(6) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out deleted file mode 100644 index ed95f2f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out +++ /dev/null @@ -1,25 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:25:46 am ist -.include ua741.sub - -v1 5 0 pulse(1 0 0 0 0 0.001 0.002) -c1 6 1 10n -V_u4 2 1 0 -* Plotting option vplot8_1 -V_u1 4 2 0 -V_u2 2 3 0 -r2 6 3 1000000 -r1 4 5 10000 -x1 2 0 6 ua741 - -.tran 1e-03 2e-03 0e-00 - -* Control Statements -.control -run -plot v(5) -plot i(V_u4) -plot v(6) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro deleted file mode 100644 index 62130f3..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Wednesday 17 April 2013 05:14:42 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj deleted file mode 100644 index a7ce942..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch deleted file mode 100644 index 976a836..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch +++ /dev/null @@ -1,214 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 18 April 2013 10:25:50 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.8-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "18 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 4100 3200 4100 2950 -Wire Wire Line - 4100 2950 4200 2950 -Wire Wire Line - 4200 2950 4200 2850 -Wire Wire Line - 4250 4300 3300 4300 -Connection ~ 4250 4100 -Wire Wire Line - 4250 4300 4250 4100 -Connection ~ 4100 3200 -Connection ~ 7050 2950 -Wire Wire Line - 7050 2600 7050 3300 -Wire Wire Line - 7050 2600 6300 2600 -Connection ~ 5300 2950 -Wire Wire Line - 5300 3200 5300 2600 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 3400 5350 4200 -Connection ~ 5300 3200 -Wire Wire Line - 5250 3200 5350 3200 -Wire Wire Line - 5900 2950 5800 2950 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 7050 2950 6400 2950 -Wire Wire Line - 7050 3300 6350 3300 -Wire Wire Line - 4050 4100 5350 4100 -Wire Wire Line - 5800 2600 5900 2600 -Wire Wire Line - 3300 4300 3300 3700 -Wire Wire Line - 3300 3100 3300 2850 -Wire Wire Line - 3300 2850 4200 2850 -$Comp -L VPLOT8 U5 -U 1 1 516F6D28 -P 3300 3400 -F 0 "U5" H 3150 3500 50 0000 C CNN -F 1 "VPLOT8" H 3450 3500 50 0000 C CNN - 1 3300 3400 - 0 1 1 0 -$EndComp -$Comp -L PULSE v1 -U 1 1 516E8CD4 -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "PULSE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L C C1 -U 1 1 516E8BE7 -P 6100 2600 -F 0 "C1" H 6150 2700 50 0000 L CNN -F 1 "10n" H 6150 2500 50 0000 L CNN - 1 6100 2600 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516E8BCF -P 5550 2600 -F 0 "U4" H 5400 2700 50 0000 C CNN -F 1 "IPLOT" H 5700 2700 50 0000 C CNN - 1 5550 2600 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7350 3300 -F 0 "U3" H 7200 3400 50 0000 C CNN -F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN - 1 7350 3300 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG01" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2950 -F 0 "U2" H 5400 3050 50 0000 C CNN -F 1 "IPLOT" H 5700 3050 50 0000 C CNN - 1 5550 2950 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6150 2950 -F 0 "R2" V 6230 2950 50 0000 C CNN -F 1 "1000000" V 6150 2950 50 0000 C CNN - 1 6150 2950 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR02" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "10000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro deleted file mode 100644 index 9aa118e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro +++ /dev/null @@ -1,72 +0,0 @@ -update=Monday 17 December 2012 06:14:06 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis deleted file mode 100644 index 48302a3..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 2e-03 4e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir deleted file mode 100644 index d30b232..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir +++ /dev/null @@ -1,24 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:53:39 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -v1 4 0 PULSE -v2 11 0 10V -U3 8 3 VPLOT8_1 -R5 13 3 10000 -R4 0 13 10000 -R3 1 11 10000 -U5 8 2 IPLOT -Q2 1 1 2 NPN -X2 1 13 3 UA741 -U4 10 8 IPLOT -Q1 10 0 9 NPN -U1 6 7 IPLOT -U2 7 9 IPLOT -R2 8 5 10000 -R1 6 4 1000 -X1 7 0 5 UA741 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt deleted file mode 100644 index 0decb7c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt +++ /dev/null @@ -1,27 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:53:39 am ist -.include ua741.sub - -v1 4 0 pulse(0 1 0.002 0.004) -v2 11 0 10v -* Plotting option vplot8_1 -r5 13 3 10000 -r4 0 13 10000 -r3 1 11 10000 -V_u5 8 2 0 -q2 2 1 1 npn -x2 1 13 3 ua741 -V_u4 10 8 0 -q1 10 0 9 npn -V_u1 6 7 0 -V_u2 7 9 0 -r2 8 5 10000 -r1 6 4 1000 -x1 7 0 5 ua741 - -.tran 2e-03 4e-03 0e-00 -.plot v(8) v(3) -.plot i(V_u5) -.plot i(V_u4) -.plot i(V_u1) -.plot i(V_u2) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out deleted file mode 100644 index f4b917f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out +++ /dev/null @@ -1,32 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:53:39 am ist -.include ua741.sub - -v1 4 0 pulse(0 1 0.002 0.004) -v2 11 0 10v -* Plotting option vplot8_1 -r5 13 3 10000 -r4 0 13 10000 -r3 1 11 10000 -V_u5 8 2 0 -q2 2 1 1 npn -x2 1 13 3 ua741 -V_u4 10 8 0 -q1 10 0 9 npn -V_u1 6 7 0 -V_u2 7 9 0 -r2 8 5 10000 -r1 6 4 1000 -x1 7 0 5 ua741 - -.tran 2e-03 4e-03 0e-00 - -* Control Statements -.control -run -plot v(8) v(3) -plot i(V_u5) -plot i(V_u4) -plot i(V_u1) -plot i(V_u2) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro deleted file mode 100644 index 6a09490..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Thursday 18 April 2013 10:31:10 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj deleted file mode 100644 index da8b8d1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_5.9.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch deleted file mode 100644 index 481506c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch +++ /dev/null @@ -1,324 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 18 April 2013 10:52:19 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_5.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "18 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L GND #PWR01 -U 1 1 516F8096 -P 6150 2850 -F 0 "#PWR01" H 6150 2850 30 0001 C CNN -F 1 "GND" H 6150 2780 30 0001 C CNN - 1 6150 2850 - 1 0 0 -1 -$EndComp -Connection ~ 6150 2750 -$Comp -L PWR_FLAG #FLG02 -U 1 1 516F807F -P 6150 2750 -F 0 "#FLG02" H 6150 3020 30 0001 C CNN -F 1 "PWR_FLAG" H 6150 2980 30 0000 C CNN - 1 6150 2750 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 6150 2700 6150 2850 -Wire Wire Line - 10200 3750 10200 5050 -Wire Wire Line - 10200 2850 10200 2400 -Wire Wire Line - 10200 2400 8100 2400 -Wire Wire Line - 9250 3700 9400 3700 -Wire Wire Line - 8250 3800 8250 4100 -Connection ~ 8100 3300 -Wire Wire Line - 8100 3050 8100 3600 -Wire Wire Line - 7900 3600 8250 3600 -Wire Wire Line - 7150 3300 6950 3300 -Wire Wire Line - 6350 2400 6400 2400 -Wire Wire Line - 5300 2400 5300 3200 -Wire Wire Line - 6350 3300 6450 3300 -Wire Wire Line - 4750 3200 4650 3200 -Wire Wire Line - 5350 4200 5350 3400 -Connection ~ 5300 3200 -Wire Wire Line - 5350 3200 5250 3200 -Wire Wire Line - 4150 3200 4050 3200 -Connection ~ 5350 4100 -Connection ~ 6350 3300 -Connection ~ 7050 3300 -Wire Wire Line - 5350 4100 4050 4100 -Wire Wire Line - 5800 2400 5950 2400 -Wire Wire Line - 6900 2400 7050 2400 -Wire Wire Line - 7050 2400 7050 3300 -Wire Wire Line - 7650 3300 7700 3300 -Connection ~ 8100 3600 -Wire Wire Line - 8100 2400 8100 2550 -Wire Wire Line - 8250 4000 8450 4000 -Connection ~ 8250 4000 -Wire Wire Line - 9300 3700 9300 4000 -Wire Wire Line - 9300 4000 8950 4000 -Connection ~ 9300 3700 -Connection ~ 9400 3700 -Connection ~ 8100 2400 -Wire Wire Line - 10200 5050 8250 5050 -Wire Wire Line - 8250 5250 8250 4600 -Connection ~ 8250 5050 -Connection ~ 8250 5150 -$Comp -L GND #PWR03 -U 1 1 516F8034 -P 8250 5250 -F 0 "#PWR03" H 8250 5250 30 0001 C CNN -F 1 "GND" H 8250 5180 30 0001 C CNN - 1 8250 5250 - 1 0 0 -1 -$EndComp -$Comp -L PULSE v1 -U 1 1 516F801F -P 4050 3650 -F 0 "v1" H 3850 3750 60 0000 C CNN -F 1 "PULSE" H 3850 3600 60 0000 C CNN -F 2 "R1" H 3750 3650 60 0000 C CNN - 1 4050 3650 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 516F7FED -P 10200 3300 -F 0 "v2" H 10000 3400 60 0000 C CNN -F 1 "10V" H 10000 3250 60 0000 C CNN -F 2 "R1" H 9900 3300 60 0000 C CNN - 1 10200 3300 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 2 1 516F7F85 -P 9400 4000 -F 0 "U3" H 9250 4100 50 0000 C CNN -F 1 "VPLOT8_1" H 9550 4100 50 0000 C CNN - 2 9400 4000 - -1 0 0 1 -$EndComp -$Comp -L R R5 -U 1 1 516F7F66 -P 8700 4000 -F 0 "R5" V 8780 4000 50 0000 C CNN -F 1 "10000" V 8700 4000 50 0000 C CNN - 1 8700 4000 - 0 -1 -1 0 -$EndComp -$Comp -L R R4 -U 1 1 516F7F56 -P 8250 4350 -F 0 "R4" V 8330 4350 50 0000 C CNN -F 1 "10000" V 8250 4350 50 0000 C CNN - 1 8250 4350 - -1 0 0 1 -$EndComp -$Comp -L R R3 -U 1 1 516F7F35 -P 8100 2800 -F 0 "R3" V 8180 2800 50 0000 C CNN -F 1 "10000" V 8100 2800 50 0000 C CNN - 1 8100 2800 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U5 -U 1 1 516F7EEB -P 7400 3300 -F 0 "U5" H 7250 3400 50 0000 C CNN -F 1 "IPLOT" H 7550 3400 50 0000 C CNN - 1 7400 3300 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q2 -U 1 1 516F7EDC -P 7900 3400 -F 0 "Q2" H 7900 3250 50 0000 R CNN -F 1 "NPN" H 7900 3550 50 0000 R CNN - 1 7900 3400 - 0 -1 -1 0 -$EndComp -$Comp -L UA741 X2 -U 1 1 516F7ED1 -P 8750 3700 -F 0 "X2" H 8900 3850 60 0000 C CNN -F 1 "UA741" H 8900 3950 60 0000 C CNN - 1 8750 3700 - 1 0 0 1 -$EndComp -$Comp -L IPLOT U4 -U 1 1 516F7EB1 -P 6650 2400 -F 0 "U4" H 6500 2500 50 0000 C CNN -F 1 "IPLOT" H 6800 2500 50 0000 C CNN - 1 6650 2400 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 516F7E9D -P 6150 2500 -F 0 "Q1" H 6150 2350 50 0000 R CNN -F 1 "NPN" H 6150 2650 50 0000 R CNN - 1 6150 2500 - 0 -1 -1 0 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 516D117B -P 7050 3600 -F 0 "U3" H 6900 3700 50 0000 C CNN -F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN - 1 7050 3600 - -1 0 0 1 -$EndComp -$Comp -L PWR_FLAG #FLG04 -U 1 1 516D1102 -P 5300 3200 -F 0 "#FLG04" H 5300 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN - 1 5300 3200 - -1 0 0 1 -$EndComp -$Comp -L IPLOT U1 -U 1 1 516D1019 -P 5000 3200 -F 0 "U1" H 4850 3300 50 0000 C CNN -F 1 "IPLOT" H 5150 3300 50 0000 C CNN - 1 5000 3200 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U2 -U 1 1 516D0FEC -P 5550 2400 -F 0 "U2" H 5400 2500 50 0000 C CNN -F 1 "IPLOT" H 5700 2500 50 0000 C CNN - 1 5550 2400 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 516D0FE2 -P 6700 3300 -F 0 "R2" V 6780 3300 50 0000 C CNN -F 1 "10000" V 6700 3300 50 0000 C CNN - 1 6700 3300 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR05 -U 1 1 516D0F6B -P 5350 4200 -F 0 "#PWR05" H 5350 4200 30 0001 C CNN -F 1 "GND" H 5350 4130 30 0001 C CNN - 1 5350 4200 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 516D0F10 -P 4400 3200 -F 0 "R1" V 4480 3200 50 0000 C CNN -F 1 "1000" V 4400 3200 50 0000 C CNN - 1 4400 3200 - 0 1 1 0 -$EndComp -$Comp -L UA741 X1 -U 1 1 516D0E60 -P 5850 3300 -F 0 "X1" H 6000 3450 60 0000 C CNN -F 1 "UA741" H 6000 3550 60 0000 C CNN - 1 5850 3300 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak deleted file mode 100644 index 6be9280..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak +++ /dev/null @@ -1,208 +0,0 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "20 oct 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U1 -U 3 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 3 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 1 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 2 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir deleted file mode 100644 index de79742..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out deleted file mode 100644 index 3661a9a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out +++ /dev/null @@ -1,9 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro deleted file mode 100644 index df98e42..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Thursday 18 April 2013 01:48:22 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/OSCAD/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice -LibName39=/home/holy/OSCAD/library/analogSpice -LibName40=/home/holy/OSCAD/library/analogXSpice -LibName41=/home/holy/OSCAD/library/convergenceAidSpice -LibName42=/home/holy/OSCAD/library/converterSpice -LibName43=/home/holy/OSCAD/library/digitalSpice -LibName44=/home/holy/OSCAD/library/digitalXSpice -LibName45=/home/holy/OSCAD/library/linearSpice -LibName46=/home/holy/OSCAD/library/measurementSpice -LibName47=/home/holy/OSCAD/library/portSpice -LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch deleted file mode 100644 index 7dfc5e1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub deleted file mode 100644 index 1edba9f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 - -.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis deleted file mode 100644 index 0e8f996..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak deleted file mode 100644 index 6284625..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak +++ /dev/null @@ -1,98 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 22 April 2013 12:05:40 PM IST -#encoding utf-8 -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# VCVS -# -DEF VCVS E 0 40 Y Y 1 F N -F0 "E" -200 100 50 H V C CNN -F1 "VCVS" -200 -50 50 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib deleted file mode 100644 index 388a263..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib +++ /dev/null @@ -1,98 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 22 April 2013 12:09:56 PM IST -#encoding utf-8 -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# VCVS -# -DEF VCVS E 0 40 Y Y 1 F N -F0 "E" -200 100 50 H V C CNN -F1 "VCVS" -200 -50 50 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak deleted file mode 100644 index cc13116..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak +++ /dev/null @@ -1,231 +0,0 @@ -EESchema Schematic File Version 2 date Monday 22 April 2013 12:05:40 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_7.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "22 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 1050 3250 -$Comp -L VPLOT8_1 U2 -U 1 1 5174D971 -P 1050 2950 -F 0 "U2" H 900 3050 50 0000 C CNN -F 1 "VPLOT8_1" H 1200 3050 50 0000 C CNN - 1 1050 2950 - 1 0 0 -1 -$EndComp -Connection ~ 2950 3200 -$Comp -L PWR_FLAG #FLG01 -U 1 1 5174D14C -P 2050 5350 -F 0 "#FLG01" H 2050 5620 30 0001 C CNN -F 1 "PWR_FLAG" H 2050 5580 30 0000 C CNN - 1 2050 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 5174D02B -P 2950 2900 -F 0 "U1" H 2800 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 3100 3000 50 0000 C CNN - 2 2950 2900 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5174D021 -P 2050 2900 -F 0 "U1" H 1900 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 2200 3000 50 0000 C CNN - 1 2050 2900 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 3 1 5174D010 -P 4050 2900 -F 0 "U1" H 3900 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 4200 3000 50 0000 C CNN - 3 4050 2900 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5174CFD9 -P 2050 5500 -F 0 "#PWR02" H 2050 5500 30 0001 C CNN -F 1 "GND" H 2050 5430 30 0001 C CNN - 1 2050 5500 - 1 0 0 -1 -$EndComp -Connection ~ 2750 5350 -Wire Wire Line - 2750 3950 2750 5350 -Connection ~ 2050 5350 -Wire Wire Line - 1050 4200 1050 5350 -Connection ~ 2050 4600 -Wire Wire Line - 2050 4800 2050 4000 -Wire Wire Line - 3650 4600 3800 4600 -Connection ~ 3800 3200 -Wire Wire Line - 3800 4600 3800 3200 -Connection ~ 4050 3200 -Wire Wire Line - 4050 3200 4050 3350 -Wire Wire Line - 2050 4200 2500 4200 -Connection ~ 2050 4200 -Wire Wire Line - 2500 4200 2500 3700 -Wire Wire Line - 1050 3200 1050 3300 -Wire Wire Line - 2050 3200 2050 3500 -Wire Wire Line - 1550 3200 2500 3200 -Wire Wire Line - 2500 3200 2500 3600 -Connection ~ 2050 3200 -Wire Wire Line - 2750 3350 2750 3200 -Wire Wire Line - 2750 3200 3100 3200 -Wire Wire Line - 3600 3200 4250 3200 -Wire Wire Line - 2050 4600 3150 4600 -Wire Wire Line - 2050 5300 2050 5500 -Wire Wire Line - 4050 3850 4050 5350 -Wire Wire Line - 4050 5350 1050 5350 -$Comp -L R R3 -U 1 1 5174CF9E -P 2050 5050 -F 0 "R3" V 2130 5050 50 0000 C CNN -F 1 "1000" V 2050 5050 50 0000 C CNN - 1 2050 5050 - -1 0 0 1 -$EndComp -$Comp -L R R5 -U 1 1 5174CF7E -P 3400 4600 -F 0 "R5" V 3480 4600 50 0000 C CNN -F 1 "100000" V 3400 4600 50 0000 C CNN - 1 3400 4600 - 0 1 1 0 -$EndComp -$Comp -L R R6 -U 1 1 5174CF4D -P 4050 3600 -F 0 "R6" V 4130 3600 50 0000 C CNN -F 1 "2000" V 4050 3600 50 0000 C CNN - 1 4050 3600 - -1 0 0 1 -$EndComp -$Comp -L R R4 -U 1 1 5174CF16 -P 3350 3200 -F 0 "R4" V 3430 3200 50 0000 C CNN -F 1 "1000" V 3350 3200 50 0000 C CNN - 1 3350 3200 - 0 1 1 0 -$EndComp -$Comp -L VCVS E1 -U 1 1 5174CEE8 -P 2700 3650 -F 0 "E1" H 2500 3750 50 0000 C CNN -F 1 "10000" H 2500 3600 50 0000 C CNN - 1 2700 3650 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5174CEC2 -P 2050 3750 -F 0 "R2" V 2130 3750 50 0000 C CNN -F 1 "100000" V 2050 3750 50 0000 C CNN - 1 2050 3750 - -1 0 0 1 -$EndComp -$Comp -L SINE v1 -U 1 1 5174CE88 -P 1050 3750 -F 0 "v1" H 850 3850 60 0000 C CNN -F 1 "SINE" H 850 3700 60 0000 C CNN -F 2 "R1" H 750 3750 60 0000 C CNN - 1 1050 3750 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5174CE5E -P 1300 3200 -F 0 "R1" V 1380 3200 50 0000 C CNN -F 1 "10000" V 1300 3200 50 0000 C CNN - 1 1300 3200 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir deleted file mode 100644 index c73ab3c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir +++ /dev/null @@ -1,18 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 22 April 2013 12:19:08 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -XU2 1 VPLOT8_1 -XU1 4 3 5 VPLOT8_1 -R3 0 6 1000 -R5 5 6 100000 -R6 0 5 2000 -R4 5 3 1000 -E1 3 0 4 6 2 -R2 6 4 100000 -v1 1 0 SINE -R1 4 1 10000 - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt deleted file mode 100644 index 9a79ca6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt +++ /dev/null @@ -1,17 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 12:09:21 pm ist - -* Plotting option vplot8_1 -* Plotting option vplot8_1 -r3 0 6 1000 -r5 5 6 100000 -r6 0 5 2000 -r4 5 3 1000 -e1 3 0 4 6 2 -r2 6 4 100000 -v1 1 0 sine(0 5 50 0 0) -r1 4 1 10000 - -.tran 2e-03 20e-03 0e-00 -.plot v(1) -.plot v(4) v(3) v(5) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out deleted file mode 100644 index 222f9bd..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 12:09:21 pm ist - -* Plotting option vplot8_1 -* Plotting option vplot8_1 -r3 0 6 1000 -r5 5 6 100000 -r6 0 5 2000 -r4 5 3 1000 -e1 3 0 4 6 2 -r2 6 4 100000 -v1 1 0 sine(0 5 50 0 0) -r1 4 1 10000 - -.tran 2e-03 20e-03 0e-00 - -* Control Statements -.control -run -plot v(1) -plot v(4) v(3) v(5) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro deleted file mode 100644 index 414c8ad..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 22 April 2013 11:14:03 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj deleted file mode 100644 index dafbe48..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_7.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch deleted file mode 100644 index 7980439..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch +++ /dev/null @@ -1,231 +0,0 @@ -EESchema Schematic File Version 2 date Monday 22 April 2013 12:09:56 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_7.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "22 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 1050 3250 -$Comp -L VPLOT8_1 U2 -U 1 1 5174D971 -P 1050 2950 -F 0 "U2" H 900 3050 50 0000 C CNN -F 1 "VPLOT8_1" H 1200 3050 50 0000 C CNN - 1 1050 2950 - 1 0 0 -1 -$EndComp -Connection ~ 2950 3200 -$Comp -L PWR_FLAG #FLG01 -U 1 1 5174D14C -P 2050 5350 -F 0 "#FLG01" H 2050 5620 30 0001 C CNN -F 1 "PWR_FLAG" H 2050 5580 30 0000 C CNN - 1 2050 5350 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 2 1 5174D02B -P 2950 2900 -F 0 "U1" H 2800 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 3100 3000 50 0000 C CNN - 2 2950 2900 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 1 1 5174D021 -P 2050 2900 -F 0 "U1" H 1900 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 2200 3000 50 0000 C CNN - 1 2050 2900 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U1 -U 3 1 5174D010 -P 4050 2900 -F 0 "U1" H 3900 3000 50 0000 C CNN -F 1 "VPLOT8_1" H 4200 3000 50 0000 C CNN - 3 4050 2900 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5174CFD9 -P 2050 5500 -F 0 "#PWR02" H 2050 5500 30 0001 C CNN -F 1 "GND" H 2050 5430 30 0001 C CNN - 1 2050 5500 - 1 0 0 -1 -$EndComp -Connection ~ 2750 5350 -Wire Wire Line - 2750 3950 2750 5350 -Connection ~ 2050 5350 -Wire Wire Line - 1050 4200 1050 5350 -Connection ~ 2050 4600 -Wire Wire Line - 2050 4800 2050 4000 -Wire Wire Line - 3650 4600 3800 4600 -Connection ~ 3800 3200 -Wire Wire Line - 3800 4600 3800 3200 -Connection ~ 4050 3200 -Wire Wire Line - 4050 3200 4050 3350 -Wire Wire Line - 2050 4200 2500 4200 -Connection ~ 2050 4200 -Wire Wire Line - 2500 4200 2500 3700 -Wire Wire Line - 1050 3200 1050 3300 -Wire Wire Line - 2050 3200 2050 3500 -Wire Wire Line - 1550 3200 2500 3200 -Wire Wire Line - 2500 3200 2500 3600 -Connection ~ 2050 3200 -Wire Wire Line - 2750 3350 2750 3200 -Wire Wire Line - 2750 3200 3100 3200 -Wire Wire Line - 3600 3200 4250 3200 -Wire Wire Line - 2050 4600 3150 4600 -Wire Wire Line - 2050 5300 2050 5500 -Wire Wire Line - 4050 3850 4050 5350 -Wire Wire Line - 4050 5350 1050 5350 -$Comp -L R R3 -U 1 1 5174CF9E -P 2050 5050 -F 0 "R3" V 2130 5050 50 0000 C CNN -F 1 "1000" V 2050 5050 50 0000 C CNN - 1 2050 5050 - -1 0 0 1 -$EndComp -$Comp -L R R5 -U 1 1 5174CF7E -P 3400 4600 -F 0 "R5" V 3480 4600 50 0000 C CNN -F 1 "100000" V 3400 4600 50 0000 C CNN - 1 3400 4600 - 0 1 1 0 -$EndComp -$Comp -L R R6 -U 1 1 5174CF4D -P 4050 3600 -F 0 "R6" V 4130 3600 50 0000 C CNN -F 1 "2000" V 4050 3600 50 0000 C CNN - 1 4050 3600 - -1 0 0 1 -$EndComp -$Comp -L R R4 -U 1 1 5174CF16 -P 3350 3200 -F 0 "R4" V 3430 3200 50 0000 C CNN -F 1 "1000" V 3350 3200 50 0000 C CNN - 1 3350 3200 - 0 1 1 0 -$EndComp -$Comp -L VCVS E1 -U 1 1 5174CEE8 -P 2700 3650 -F 0 "E1" H 2500 3750 50 0000 C CNN -F 1 "2" H 2500 3600 50 0000 C CNN - 1 2700 3650 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5174CEC2 -P 2050 3750 -F 0 "R2" V 2130 3750 50 0000 C CNN -F 1 "100000" V 2050 3750 50 0000 C CNN - 1 2050 3750 - -1 0 0 1 -$EndComp -$Comp -L SINE v1 -U 1 1 5174CE88 -P 1050 3750 -F 0 "v1" H 850 3850 60 0000 C CNN -F 1 "SINE" H 850 3700 60 0000 C CNN -F 2 "R1" H 750 3750 60 0000 C CNN - 1 1050 3750 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 5174CE5E -P 1300 3200 -F 0 "R1" V 1380 3200 50 0000 C CNN -F 1 "10000" V 1300 3200 50 0000 C CNN - 1 1300 3200 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis deleted file mode 100644 index 0e8f996..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib deleted file mode 100644 index 394db4b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib +++ /dev/null @@ -1,115 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 22 April 2013 02:21:52 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir deleted file mode 100644 index fc9aa74..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 22 April 2013 02:21:49 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 5 4 VPLOT8_1 -v2 2 0 12 -R2 4 3 47000 -R1 3 5 10000 -v1 5 0 SINE -R3 2 4 4700 -Q1 0 3 4 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt deleted file mode 100644 index 421fe94..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt +++ /dev/null @@ -1,13 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 02:21:49 pm ist - -* Plotting option vplot8_1 -v2 2 0 12 -r2 4 3 47000 -r1 3 5 10000 -v1 5 0 sine( 5 50 ) -r3 2 4 4700 -q1 4 3 0 npn - -.tran 2e-03 20e-03 0e-00 -.plot v(5) v(4) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out deleted file mode 100644 index db0fe26..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 02:21:49 pm ist - -* Plotting option vplot8_1 -v2 2 0 12 -r2 4 3 47000 -r1 3 5 10000 -v1 5 0 sine( 5 50 ) -r3 2 4 4700 -q1 4 3 0 npn - -.tran 2e-03 20e-03 0e-00 - -* Control Statements -.control -run -plot v(5) v(4) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro deleted file mode 100644 index 1618111..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 22 April 2013 02:17:45 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj deleted file mode 100644 index ff14336..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_7.3.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch deleted file mode 100644 index fddbc06..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch +++ /dev/null @@ -1,175 +0,0 @@ -EESchema Schematic File Version 2 date Monday 22 April 2013 02:21:52 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "22 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L VPLOT8_1 U1 -U 1 1 5174FA0E -P 3850 3350 -F 0 "U1" H 3700 3450 50 0000 C CNN -F 1 "VPLOT8_1" H 4000 3450 50 0000 C CNN - 1 3850 3350 - 1 0 0 -1 -$EndComp -Connection ~ 3850 3650 -Wire Wire Line - 3850 3650 3800 3650 -Connection ~ 4350 3650 -Connection ~ 5300 3350 -Wire Wire Line - 4950 4650 4950 3850 -Wire Wire Line - 5800 3200 5800 2800 -Wire Wire Line - 5800 2800 4950 2800 -Wire Wire Line - 4350 3350 4350 3650 -Wire Wire Line - 4350 3350 4450 3350 -Wire Wire Line - 4950 3450 4950 3300 -Wire Wire Line - 4350 3650 4650 3650 -Wire Wire Line - 4950 3350 5300 3350 -Connection ~ 4950 3350 -Wire Wire Line - 5800 4100 5800 4550 -Wire Wire Line - 5800 4550 3800 4550 -Connection ~ 4950 4550 -$Comp -L VPLOT8_1 U1 -U 2 1 5174F9F2 -P 5300 3050 -F 0 "U1" H 5150 3150 50 0000 C CNN -F 1 "VPLOT8_1" H 5450 3150 50 0000 C CNN - 2 5300 3050 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5174F9DF -P 4950 4550 -F 0 "#FLG01" H 4950 4820 30 0001 C CNN -F 1 "PWR_FLAG" H 4950 4780 30 0000 C CNN - 1 4950 4550 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5174F9D4 -P 4950 4650 -F 0 "#PWR02" H 4950 4650 30 0001 C CNN -F 1 "GND" H 4950 4580 30 0001 C CNN - 1 4950 4650 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5174F994 -P 5800 3650 -F 0 "v2" H 5600 3750 60 0000 C CNN -F 1 "12" H 5600 3600 60 0000 C CNN -F 2 "R1" H 5500 3650 60 0000 C CNN - 1 5800 3650 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5174F959 -P 4700 3350 -F 0 "R2" V 4780 3350 50 0000 C CNN -F 1 "47000" V 4700 3350 50 0000 C CNN - 1 4700 3350 - 0 1 1 0 -$EndComp -$Comp -L R R1 -U 1 1 5174F943 -P 4100 3650 -F 0 "R1" V 4180 3650 50 0000 C CNN -F 1 "10000" V 4100 3650 50 0000 C CNN - 1 4100 3650 - 0 1 1 0 -$EndComp -$Comp -L SINE v1 -U 1 1 5174F939 -P 3800 4100 -F 0 "v1" H 3600 4200 60 0000 C CNN -F 1 "SINE" H 3600 4050 60 0000 C CNN -F 2 "R1" H 3500 4100 60 0000 C CNN - 1 3800 4100 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 5174F90B -P 4950 3050 -F 0 "R3" V 5030 3050 50 0000 C CNN -F 1 "4700" V 4950 3050 50 0000 C CNN - 1 4950 3050 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 5174F8FA -P 4850 3650 -F 0 "Q1" H 4850 3500 50 0000 R CNN -F 1 "NPN" H 4850 3800 50 0000 R CNN - 1 4850 3650 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis deleted file mode 100644 index 0e8f996..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak deleted file mode 100644 index 61d077a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak +++ /dev/null @@ -1,133 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 23 April 2013 11:46:23 AM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib deleted file mode 100644 index b4c0e94..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib +++ /dev/null @@ -1,133 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Tuesday 23 April 2013 12:03:44 PM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak deleted file mode 100644 index 0eedc93..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak +++ /dev/null @@ -1,348 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 23 April 2013 11:46:23 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_7.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "23 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 6350 3000 -$Comp -L VPLOT8_1 U1 -U 1 1 517625EA -P 6350 2700 -F 0 "U1" H 6200 2800 50 0000 C CNN -F 1 "VPLOT8_1" H 6500 2800 50 0000 C CNN - 1 6350 2700 - 1 0 0 -1 -$EndComp -Connection ~ 7000 2450 -$Comp -L VPLOT8_1 U1 -U 2 1 517625DB -P 7000 2150 -F 0 "U1" H 6850 2250 50 0000 C CNN -F 1 "VPLOT8_1" H 7150 2250 50 0000 C CNN - 2 7000 2150 - 1 0 0 -1 -$EndComp -Connection ~ 5800 2700 -$Comp -L PWR_FLAG #FLG01 -U 1 1 517625B5 -P 5800 2700 -F 0 "#FLG01" H 5800 2970 30 0001 C CNN -F 1 "PWR_FLAG" H 5800 2930 30 0000 C CNN - 1 5800 2700 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 517625AE -P 4050 3100 -F 0 "#FLG02" H 4050 3370 30 0001 C CNN -F 1 "PWR_FLAG" H 4050 3330 30 0000 C CNN - 1 4050 3100 - 1 0 0 -1 -$EndComp -Connection ~ 3250 4150 -$Comp -L PWR_FLAG #FLG03 -U 1 1 5176256A -P 3250 4150 -F 0 "#FLG03" H 3250 4420 30 0001 C CNN -F 1 "PWR_FLAG" H 3250 4380 30 0000 C CNN - 1 3250 4150 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR04 -U 1 1 5176255C -P 3250 4300 -F 0 "#PWR04" H 3250 4300 30 0001 C CNN -F 1 "GND" H 3250 4230 30 0001 C CNN - 1 3250 4300 - 1 0 0 -1 -$EndComp -Connection ~ 3250 3950 -Wire Wire Line - 3250 3950 3250 4300 -Wire Wire Line - 2500 3100 2750 3100 -Connection ~ 6200 1700 -Wire Wire Line - 7500 2400 7500 1700 -Wire Wire Line - 7500 1700 4050 1700 -Wire Wire Line - 5200 4350 5000 4350 -Wire Wire Line - 6600 3000 6600 4350 -Connection ~ 6200 3000 -Wire Wire Line - 6600 3000 6200 3000 -Connection ~ 4050 3950 -Wire Wire Line - 3850 3100 4400 3100 -Connection ~ 4050 3100 -Wire Wire Line - 4050 3450 4050 2650 -Connection ~ 4700 1700 -Wire Wire Line - 4050 1700 4050 2150 -Connection ~ 6200 3950 -Wire Wire Line - 6200 3550 6200 3950 -Wire Wire Line - 6900 2450 7050 2450 -Wire Wire Line - 5200 3450 5200 3400 -Connection ~ 4700 3400 -Wire Wire Line - 5200 3400 4700 3400 -Wire Wire Line - 4700 3300 4700 3450 -Wire Wire Line - 6200 2500 6200 2350 -Wire Wire Line - 4700 2600 4700 2900 -Wire Wire Line - 5900 2700 4700 2700 -Connection ~ 4700 2700 -Wire Wire Line - 6200 2450 6500 2450 -Connection ~ 6200 2450 -Wire Wire Line - 6200 2900 6200 3050 -Wire Wire Line - 5200 3950 5200 3850 -Wire Wire Line - 7050 3950 7050 2950 -Connection ~ 5200 3950 -Wire Wire Line - 4700 1700 4700 2100 -Wire Wire Line - 6200 1700 6200 1850 -Connection ~ 4700 3950 -Wire Wire Line - 3450 3100 3250 3100 -Wire Wire Line - 6600 4350 5600 4350 -Wire Wire Line - 4500 4350 3950 4350 -Wire Wire Line - 3950 4350 3950 3100 -Connection ~ 3950 3100 -Wire Wire Line - 7500 3300 7500 3950 -Wire Wire Line - 7500 3950 2750 3950 -Connection ~ 7050 3950 -Wire Wire Line - 2750 3950 2750 4000 -Wire Wire Line - 2750 4000 2500 4000 -$Comp -L SINE v1 -U 1 1 5176244C -P 2500 3550 -F 0 "v1" H 2300 3650 60 0000 C CNN -F 1 "SINE" H 2300 3500 60 0000 C CNN -F 2 "R1" H 2200 3550 60 0000 C CNN - 1 2500 3550 - 1 0 0 -1 -$EndComp -$Comp -L R R6 -U 1 1 51761AB3 -P 4750 4350 -F 0 "R6" V 4830 4350 50 0000 C CNN -F 1 "10k" V 4750 4350 50 0000 C CNN - 1 4750 4350 - 0 1 1 0 -$EndComp -$Comp -L R R1 -U 1 1 51761A46 -P 3000 3100 -F 0 "R1" V 3080 3100 50 0000 C CNN -F 1 "10k" V 3000 3100 50 0000 C CNN - 1 3000 3100 - 0 1 1 0 -$EndComp -$Comp -L C C1 -U 1 1 51761A2D -P 3650 3100 -F 0 "C1" H 3700 3200 50 0000 L CNN -F 1 "1k" H 3700 3000 50 0000 L CNN - 1 3650 3100 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 51761A14 -P 4050 3700 -F 0 "R3" V 4130 3700 50 0000 C CNN -F 1 "15k" V 4050 3700 50 0000 C CNN - 1 4050 3700 - 1 0 0 -1 -$EndComp -$Comp -L R R9 -U 1 1 517619D2 -P 7050 2700 -F 0 "R9" V 7130 2700 50 0000 C CNN -F 1 "1k" V 7050 2700 50 0000 C CNN - 1 7050 2700 - 1 0 0 -1 -$EndComp -$Comp -L C C2 -U 1 1 517619B5 -P 5200 3650 -F 0 "C2" H 5250 3750 50 0000 L CNN -F 1 "1k" H 5250 3550 50 0000 L CNN - 1 5200 3650 - 1 0 0 -1 -$EndComp -$Comp -L R R7 -U 1 1 517619A1 -P 6200 2100 -F 0 "R7" V 6280 2100 50 0000 C CNN -F 1 "8k" V 6200 2100 50 0000 C CNN - 1 6200 2100 - 1 0 0 -1 -$EndComp -$Comp -L R R8 -U 1 1 5176198B -P 6200 3300 -F 0 "R8" V 6280 3300 50 0000 C CNN -F 1 "3.4k" V 6200 3300 50 0000 C CNN - 1 6200 3300 - 1 0 0 -1 -$EndComp -$Comp -L C C4 -U 1 1 5176197A -P 6700 2450 -F 0 "C4" H 6750 2550 50 0000 L CNN -F 1 "1k" H 6750 2350 50 0000 L CNN - 1 6700 2450 - 0 1 1 0 -$EndComp -$Comp -L R R5 -U 1 1 51761974 -P 4700 3700 -F 0 "R5" V 4780 3700 50 0000 C CNN -F 1 "870" V 4700 3700 50 0000 C CNN - 1 4700 3700 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 51761961 -P 4700 2350 -F 0 "R4" V 4780 2350 50 0000 C CNN -F 1 "10k" V 4700 2350 50 0000 C CNN - 1 4700 2350 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5176195A -P 7500 2850 -F 0 "v2" H 7300 2950 60 0000 C CNN -F 1 "12" H 7300 2800 60 0000 C CNN -F 2 "R1" H 7200 2850 60 0000 C CNN - 1 7500 2850 - 1 0 0 -1 -$EndComp -$Comp -L C C3 -U 1 1 51761951 -P 5400 4350 -F 0 "C3" H 5450 4450 50 0000 L CNN -F 1 "1k" H 5450 4250 50 0000 L CNN - 1 5400 4350 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5176194E -P 4050 2400 -F 0 "R2" V 4130 2400 50 0000 C CNN -F 1 "100k" V 4050 2400 50 0000 C CNN - 1 4050 2400 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q2 -U 1 1 5176191C -P 6100 2700 -F 0 "Q2" H 6100 2550 50 0000 R CNN -F 1 "NPN" H 6100 2850 50 0000 R CNN - 1 6100 2700 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 517618FE -P 4600 3100 -F 0 "Q1" H 4600 2950 50 0000 R CNN -F 1 "NPN" H 4600 3250 50 0000 R CNN - 1 4600 3100 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir deleted file mode 100644 index 66167e8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir +++ /dev/null @@ -1,26 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 23 April 2013 12:03:40 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 8 7 VPLOT8_1 -v1 2 0 SINE -R6 3 6 10k -R1 1 2 10k -C1 6 1 1m -R3 6 0 15k -R9 7 0 1k -C2 11 0 1m -R7 4 9 8k -R8 8 0 3.4k -C4 7 9 1m -R5 11 0 870 -R4 4 10 10k -v2 4 0 12 -C3 8 3 1m -R2 4 6 100k -Q2 8 10 9 NPN -Q1 11 6 10 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt deleted file mode 100644 index d627f6f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt +++ /dev/null @@ -1,24 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 23 april 2013 12:03:40 pm ist - -* Plotting option vplot8_1 -v1 2 0 sine(0 1 50 ) -r6 3 6 10k -r1 1 2 10k -c1 6 1 1m -r3 6 0 15k -r9 7 0 1k -c2 11 0 1m -r7 4 9 8k -r8 8 0 3.4k -c4 7 9 1m -r5 11 0 870 -r4 4 10 10k -v2 4 0 12 -c3 8 3 1m -r2 4 6 100k -q2 9 10 8 npn -q1 10 6 11 npn - -.tran 2e-03 20e-03 0e-00 -.plot v(8) v(7) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out deleted file mode 100644 index 669fcbb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out +++ /dev/null @@ -1,29 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: tuesday 23 april 2013 12:03:40 pm ist - -* Plotting option vplot8_1 -v1 2 0 sine(0 1 50 ) -r6 3 6 10k -r1 1 2 10k -c1 6 1 1m -r3 6 0 15k -r9 7 0 1k -c2 11 0 1m -r7 4 9 8k -r8 8 0 3.4k -c4 7 9 1m -r5 11 0 870 -r4 4 10 10k -v2 4 0 12 -c3 8 3 1m -r2 4 6 100k -q2 9 10 8 npn -q1 10 6 11 npn - -.tran 2e-03 20e-03 0e-00 - -* Control Statements -.control -run -plot v(8) v(7) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro deleted file mode 100644 index 29f504b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 23 April 2013 10:45:01 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj deleted file mode 100644 index a6cb330..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_7.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch deleted file mode 100644 index 1f165d6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch +++ /dev/null @@ -1,348 +0,0 @@ -EESchema Schematic File Version 2 date Tuesday 23 April 2013 12:03:44 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_7.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "23 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 6350 3000 -$Comp -L VPLOT8_1 U1 -U 1 1 517625EA -P 6350 2700 -F 0 "U1" H 6200 2800 50 0000 C CNN -F 1 "VPLOT8_1" H 6500 2800 50 0000 C CNN - 1 6350 2700 - 1 0 0 -1 -$EndComp -Connection ~ 7000 2450 -$Comp -L VPLOT8_1 U1 -U 2 1 517625DB -P 7000 2150 -F 0 "U1" H 6850 2250 50 0000 C CNN -F 1 "VPLOT8_1" H 7150 2250 50 0000 C CNN - 2 7000 2150 - 1 0 0 -1 -$EndComp -Connection ~ 5800 2700 -$Comp -L PWR_FLAG #FLG01 -U 1 1 517625B5 -P 5800 2700 -F 0 "#FLG01" H 5800 2970 30 0001 C CNN -F 1 "PWR_FLAG" H 5800 2930 30 0000 C CNN - 1 5800 2700 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 517625AE -P 4050 3100 -F 0 "#FLG02" H 4050 3370 30 0001 C CNN -F 1 "PWR_FLAG" H 4050 3330 30 0000 C CNN - 1 4050 3100 - 1 0 0 -1 -$EndComp -Connection ~ 3250 4150 -$Comp -L PWR_FLAG #FLG03 -U 1 1 5176256A -P 3250 4150 -F 0 "#FLG03" H 3250 4420 30 0001 C CNN -F 1 "PWR_FLAG" H 3250 4380 30 0000 C CNN - 1 3250 4150 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR04 -U 1 1 5176255C -P 3250 4300 -F 0 "#PWR04" H 3250 4300 30 0001 C CNN -F 1 "GND" H 3250 4230 30 0001 C CNN - 1 3250 4300 - 1 0 0 -1 -$EndComp -Connection ~ 3250 3950 -Wire Wire Line - 3250 3950 3250 4300 -Wire Wire Line - 2500 3100 2750 3100 -Connection ~ 6200 1700 -Wire Wire Line - 7500 2400 7500 1700 -Wire Wire Line - 7500 1700 4050 1700 -Wire Wire Line - 5200 4350 5000 4350 -Wire Wire Line - 6600 3000 6600 4350 -Connection ~ 6200 3000 -Wire Wire Line - 6600 3000 6200 3000 -Connection ~ 4050 3950 -Wire Wire Line - 3850 3100 4400 3100 -Connection ~ 4050 3100 -Wire Wire Line - 4050 3450 4050 2650 -Connection ~ 4700 1700 -Wire Wire Line - 4050 1700 4050 2150 -Connection ~ 6200 3950 -Wire Wire Line - 6200 3550 6200 3950 -Wire Wire Line - 6900 2450 7050 2450 -Wire Wire Line - 5200 3450 5200 3400 -Connection ~ 4700 3400 -Wire Wire Line - 5200 3400 4700 3400 -Wire Wire Line - 4700 3300 4700 3450 -Wire Wire Line - 6200 2500 6200 2350 -Wire Wire Line - 4700 2600 4700 2900 -Wire Wire Line - 5900 2700 4700 2700 -Connection ~ 4700 2700 -Wire Wire Line - 6200 2450 6500 2450 -Connection ~ 6200 2450 -Wire Wire Line - 6200 2900 6200 3050 -Wire Wire Line - 5200 3950 5200 3850 -Wire Wire Line - 7050 3950 7050 2950 -Connection ~ 5200 3950 -Wire Wire Line - 4700 1700 4700 2100 -Wire Wire Line - 6200 1700 6200 1850 -Connection ~ 4700 3950 -Wire Wire Line - 3450 3100 3250 3100 -Wire Wire Line - 6600 4350 5600 4350 -Wire Wire Line - 4500 4350 3950 4350 -Wire Wire Line - 3950 4350 3950 3100 -Connection ~ 3950 3100 -Wire Wire Line - 7500 3300 7500 3950 -Wire Wire Line - 7500 3950 2750 3950 -Connection ~ 7050 3950 -Wire Wire Line - 2750 3950 2750 4000 -Wire Wire Line - 2750 4000 2500 4000 -$Comp -L SINE v1 -U 1 1 5176244C -P 2500 3550 -F 0 "v1" H 2300 3650 60 0000 C CNN -F 1 "SINE" H 2300 3500 60 0000 C CNN -F 2 "R1" H 2200 3550 60 0000 C CNN - 1 2500 3550 - 1 0 0 -1 -$EndComp -$Comp -L R R6 -U 1 1 51761AB3 -P 4750 4350 -F 0 "R6" V 4830 4350 50 0000 C CNN -F 1 "10k" V 4750 4350 50 0000 C CNN - 1 4750 4350 - 0 1 1 0 -$EndComp -$Comp -L R R1 -U 1 1 51761A46 -P 3000 3100 -F 0 "R1" V 3080 3100 50 0000 C CNN -F 1 "10k" V 3000 3100 50 0000 C CNN - 1 3000 3100 - 0 1 1 0 -$EndComp -$Comp -L C C1 -U 1 1 51761A2D -P 3650 3100 -F 0 "C1" H 3700 3200 50 0000 L CNN -F 1 "1m" H 3700 3000 50 0000 L CNN - 1 3650 3100 - 0 1 1 0 -$EndComp -$Comp -L R R3 -U 1 1 51761A14 -P 4050 3700 -F 0 "R3" V 4130 3700 50 0000 C CNN -F 1 "15k" V 4050 3700 50 0000 C CNN - 1 4050 3700 - 1 0 0 -1 -$EndComp -$Comp -L R R9 -U 1 1 517619D2 -P 7050 2700 -F 0 "R9" V 7130 2700 50 0000 C CNN -F 1 "1k" V 7050 2700 50 0000 C CNN - 1 7050 2700 - 1 0 0 -1 -$EndComp -$Comp -L C C2 -U 1 1 517619B5 -P 5200 3650 -F 0 "C2" H 5250 3750 50 0000 L CNN -F 1 "1m" H 5250 3550 50 0000 L CNN - 1 5200 3650 - 1 0 0 -1 -$EndComp -$Comp -L R R7 -U 1 1 517619A1 -P 6200 2100 -F 0 "R7" V 6280 2100 50 0000 C CNN -F 1 "8k" V 6200 2100 50 0000 C CNN - 1 6200 2100 - 1 0 0 -1 -$EndComp -$Comp -L R R8 -U 1 1 5176198B -P 6200 3300 -F 0 "R8" V 6280 3300 50 0000 C CNN -F 1 "3.4k" V 6200 3300 50 0000 C CNN - 1 6200 3300 - 1 0 0 -1 -$EndComp -$Comp -L C C4 -U 1 1 5176197A -P 6700 2450 -F 0 "C4" H 6750 2550 50 0000 L CNN -F 1 "1m" H 6750 2350 50 0000 L CNN - 1 6700 2450 - 0 1 1 0 -$EndComp -$Comp -L R R5 -U 1 1 51761974 -P 4700 3700 -F 0 "R5" V 4780 3700 50 0000 C CNN -F 1 "870" V 4700 3700 50 0000 C CNN - 1 4700 3700 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 51761961 -P 4700 2350 -F 0 "R4" V 4780 2350 50 0000 C CNN -F 1 "10k" V 4700 2350 50 0000 C CNN - 1 4700 2350 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 5176195A -P 7500 2850 -F 0 "v2" H 7300 2950 60 0000 C CNN -F 1 "12" H 7300 2800 60 0000 C CNN -F 2 "R1" H 7200 2850 60 0000 C CNN - 1 7500 2850 - 1 0 0 -1 -$EndComp -$Comp -L C C3 -U 1 1 51761951 -P 5400 4350 -F 0 "C3" H 5450 4450 50 0000 L CNN -F 1 "1m" H 5450 4250 50 0000 L CNN - 1 5400 4350 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 5176194E -P 4050 2400 -F 0 "R2" V 4130 2400 50 0000 C CNN -F 1 "100k" V 4050 2400 50 0000 C CNN - 1 4050 2400 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q2 -U 1 1 5176191C -P 6100 2700 -F 0 "Q2" H 6100 2550 50 0000 R CNN -F 1 "NPN" H 6100 2850 50 0000 R CNN - 1 6100 2700 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 517618FE -P 4600 3100 -F 0 "Q1" H 4600 2950 50 0000 R CNN -F 1 "NPN" H 4600 3250 50 0000 R CNN - 1 4600 3100 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis deleted file mode 100644 index 0e8f996..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak deleted file mode 100644 index 6eed972..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak +++ /dev/null @@ -1,139 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 25 April 2013 11:20:04 AM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# Idc -# -DEF Idc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "Idc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# vplot8 -# -DEF vplot8 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -300 0 200 R 40 40 1 1 O -X - 9 300 0 200 L 40 40 1 1 O -X + 2 -300 0 200 R 40 40 2 1 O -X - 10 300 0 200 L 40 40 2 1 O -X + 3 -300 0 200 R 40 40 3 1 O -X - 11 300 0 200 L 40 40 3 1 O -X + 4 -300 0 200 R 40 40 4 1 O -X - 12 300 0 200 L 40 40 4 1 O -X + 5 -300 0 200 R 40 40 5 1 O -X - 13 300 0 200 L 40 40 5 1 O -X + 6 -300 0 200 R 40 40 6 1 O -X - 14 300 0 200 L 40 40 6 1 O -X + 7 -300 0 200 R 40 40 7 1 O -X - 15 300 0 200 L 40 40 7 1 O -X + 8 -300 0 200 R 40 40 8 1 O -X - 16 300 0 200 L 40 40 8 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib deleted file mode 100644 index 008a8d7..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib +++ /dev/null @@ -1,139 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Friday 26 April 2013 04:42:05 PM IST -#encoding utf-8 -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# Idc -# -DEF Idc i 0 40 Y Y 1 F N -F0 "i" -200 100 60 H V C CNN -F1 "Idc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# sine -# -DEF sine v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "sine" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 -A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 0 1 1 I -X - 2 0 -450 300 U 50 0 1 1 I -ENDDRAW -ENDDEF -# -# vplot8 -# -DEF vplot8 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 -300 0 200 R 40 40 1 1 O -X - 9 300 0 200 L 40 40 1 1 O -X + 2 -300 0 200 R 40 40 2 1 O -X - 10 300 0 200 L 40 40 2 1 O -X + 3 -300 0 200 R 40 40 3 1 O -X - 11 300 0 200 L 40 40 3 1 O -X + 4 -300 0 200 R 40 40 4 1 O -X - 12 300 0 200 L 40 40 4 1 O -X + 5 -300 0 200 R 40 40 5 1 O -X - 13 300 0 200 L 40 40 5 1 O -X + 6 -300 0 200 R 40 40 6 1 O -X - 14 300 0 200 L 40 40 6 1 O -X + 7 -300 0 200 R 40 40 7 1 O -X - 15 300 0 200 L 40 40 7 1 O -X + 8 -300 0 200 R 40 40 8 1 O -X - 16 300 0 200 L 40 40 8 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak deleted file mode 100644 index a480fc4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak +++ /dev/null @@ -1,245 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 25 April 2013 11:20:04 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_8-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "25 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 4700 4600 -$Comp -L PWR_FLAG #FLG01 -U 1 1 5178C3EF -P 4700 4600 -F 0 "#FLG01" H 4700 4870 30 0001 C CNN -F 1 "PWR_FLAG" H 4700 4830 30 0000 C CNN - 1 4700 4600 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5178C3E3 -P 4700 4700 -F 0 "#PWR02" H 4700 4700 30 0001 C CNN -F 1 "GND" H 4700 4630 30 0001 C CNN - 1 4700 4700 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4700 4500 4700 4700 -Connection ~ 5800 2350 -Wire Wire Line - 5600 2350 5800 2350 -Wire Wire Line - 3600 4250 3600 5000 -Wire Wire Line - 6100 2700 6100 5000 -Wire Wire Line - 6600 3750 6600 4750 -Wire Wire Line - 6600 4750 5300 4750 -Wire Wire Line - 4450 2700 4100 2700 -Wire Wire Line - 4750 1650 5800 1650 -Wire Wire Line - 5800 2900 5800 3200 -Wire Wire Line - 4750 2900 4750 3200 -Wire Wire Line - 4750 2150 4750 2500 -Wire Wire Line - 5800 2150 5800 2500 -Wire Wire Line - 5800 3700 4750 3700 -Wire Wire Line - 6100 5000 4100 5000 -Wire Wire Line - 5300 3700 5300 3850 -Connection ~ 5300 3700 -Wire Wire Line - 5750 1650 5750 1400 -Connection ~ 5750 1650 -Wire Wire Line - 5750 1400 6600 1400 -Wire Wire Line - 6600 1400 6600 2850 -Wire Wire Line - 3600 2700 3600 3350 -Wire Wire Line - 5000 2350 4750 2350 -Connection ~ 4750 2350 -Wire Wire Line - 5300 3800 4700 3800 -Connection ~ 5300 3800 -Wire Wire Line - 4700 3800 4700 4000 -$Comp -L R R7 -U 1 1 5178C3D2 -P 4700 4250 -F 0 "R7" V 4780 4250 50 0000 C CNN -F 1 "150" V 4700 4250 50 0000 C CNN - 1 4700 4250 - 1 0 0 -1 -$EndComp -$Comp -L SINE v1 -U 1 1 5178C33C -P 3600 3800 -F 0 "v1" H 3400 3900 60 0000 C CNN -F 1 "SINE" H 3400 3750 60 0000 C CNN -F 2 "R1" H 3300 3800 60 0000 C CNN - 1 3600 3800 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8 U1 -U 1 1 51779652 -P 5300 2350 -F 0 "U1" H 5150 2450 50 0000 C CNN -F 1 "VPLOT8" H 5450 2450 50 0000 C CNN - 1 5300 2350 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 517794FF -P 3850 2700 -F 0 "R1" V 3930 2700 50 0000 C CNN -F 1 "5k" V 3850 2700 50 0000 C CNN - 1 3850 2700 - 0 1 1 0 -$EndComp -$Comp -L R R6 -U 1 1 517794EA -P 5800 3450 -F 0 "R6" V 5880 3450 50 0000 C CNN -F 1 "150" V 5800 3450 50 0000 C CNN - 1 5800 3450 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 517794E3 -P 4750 3450 -F 0 "R4" V 4830 3450 50 0000 C CNN -F 1 "150" V 4750 3450 50 0000 C CNN - 1 4750 3450 - 1 0 0 -1 -$EndComp -$Comp -L R R5 -U 1 1 517794C9 -P 5800 1900 -F 0 "R5" V 5880 1900 50 0000 C CNN -F 1 "10k" V 5800 1900 50 0000 C CNN - 1 5800 1900 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 517794BE -P 4750 1900 -F 0 "R3" V 4830 1900 50 0000 C CNN -F 1 "10k" V 4750 1900 50 0000 C CNN - 1 4750 1900 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q2 -U 1 1 5177949E -P 5900 2700 -F 0 "Q2" H 5900 2550 50 0000 R CNN -F 1 "NPN" H 5900 2850 50 0000 R CNN - 1 5900 2700 - -1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 51779433 -P 3850 5000 -F 0 "R2" V 3930 5000 50 0000 C CNN -F 1 "R" V 3850 5000 50 0000 C CNN - 1 3850 5000 - 0 1 1 0 -$EndComp -$Comp -L DC v3 -U 1 1 51779424 -P 6600 3300 -F 0 "v3" H 6400 3400 60 0000 C CNN -F 1 "15" H 6400 3250 60 0000 C CNN -F 2 "R1" H 6300 3300 60 0000 C CNN - 1 6600 3300 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 51779415 -P 4650 2700 -F 0 "Q1" H 4650 2550 50 0000 R CNN -F 1 "NPN" H 4650 2850 50 0000 R CNN - 1 4650 2700 - 1 0 0 -1 -$EndComp -$Comp -L IDC v2 -U 1 1 5177940C -P 5300 4300 -F 0 "v2" H 5100 4400 60 0000 C CNN -F 1 "1m" H 5100 4250 60 0000 C CNN -F 2 "R1" H 5000 4300 60 0000 C CNN - 1 5300 4300 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir deleted file mode 100644 index b1cc053..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir +++ /dev/null @@ -1,21 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 25 April 2013 11:19:59 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -R7 9 0 150 -v1 2 5 SINE -U1 1 11 VPLOT8 -R1 8 2 5k -R6 3 9 150 -R4 7 9 150 -R5 12 11 10k -R3 12 1 10k -Q2 3 4 11 NPN -R2 4 5 R -v3 12 6 15 -Q1 7 8 1 NPN -v2 9 6 1m - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt deleted file mode 100644 index d42cb97..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt +++ /dev/null @@ -1,18 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 11:19:59 am ist - -r7 9 0 150 -v1 2 5 sine( 5 50 ) -r1 8 2 5k -r6 3 9 150 -r4 7 9 150 -r5 12 11 10k -r3 12 1 10k -q2 11 4 3 npn -r2 4 5 r -v3 12 6 15 -q1 1 8 7 npn -v2 9 6 1m - -.tran 2e-03 20e-03 0e-00 -.plot v(1)-v(11) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out deleted file mode 100644 index 95b8ceb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out +++ /dev/null @@ -1,23 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 11:19:59 am ist - -r7 9 0 150 -v1 2 5 sine( 5 50 ) -r1 8 2 5k -r6 3 9 150 -r4 7 9 150 -r5 12 11 10k -r3 12 1 10k -q2 11 4 3 npn -r2 4 5 r -v3 12 6 15 -q1 1 8 7 npn -v2 9 6 1m - -.tran 2e-03 20e-03 0e-00 - -* Control Statements -.control -run -plot v(1)-v(11) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro deleted file mode 100644 index 71bd9f1..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Thursday 18 April 2013 03:16:09 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj deleted file mode 100644 index fe0de23..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch deleted file mode 100644 index 06b9dfa..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch +++ /dev/null @@ -1,245 +0,0 @@ -EESchema Schematic File Version 2 date Friday 26 April 2013 04:42:05 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_8.1-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "26 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5450 5400 -$Comp -L PWR_FLAG #FLG01 -U 1 1 5178C3EF -P 5450 5400 -F 0 "#FLG01" H 5450 5670 30 0001 C CNN -F 1 "PWR_FLAG" H 5450 5630 30 0000 C CNN - 1 5450 5400 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5178C3E3 -P 5450 5500 -F 0 "#PWR02" H 5450 5500 30 0001 C CNN -F 1 "GND" H 5450 5430 30 0001 C CNN - 1 5450 5500 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5450 5300 5450 5500 -Connection ~ 6550 3150 -Wire Wire Line - 6350 3150 6550 3150 -Wire Wire Line - 4350 5050 4350 5800 -Wire Wire Line - 6850 3500 6850 5800 -Wire Wire Line - 7350 4550 7350 5550 -Wire Wire Line - 7350 5550 6050 5550 -Wire Wire Line - 5200 3500 4850 3500 -Wire Wire Line - 5500 2450 6550 2450 -Wire Wire Line - 6550 3700 6550 4000 -Wire Wire Line - 5500 3700 5500 4000 -Wire Wire Line - 5500 2950 5500 3300 -Wire Wire Line - 6550 2950 6550 3300 -Wire Wire Line - 6550 4500 5500 4500 -Wire Wire Line - 6850 5800 4850 5800 -Wire Wire Line - 6050 4500 6050 4650 -Connection ~ 6050 4500 -Wire Wire Line - 6500 2450 6500 2200 -Connection ~ 6500 2450 -Wire Wire Line - 6500 2200 7350 2200 -Wire Wire Line - 7350 2200 7350 3650 -Wire Wire Line - 4350 3500 4350 4150 -Wire Wire Line - 5750 3150 5500 3150 -Connection ~ 5500 3150 -Wire Wire Line - 6050 4600 5450 4600 -Connection ~ 6050 4600 -Wire Wire Line - 5450 4600 5450 4800 -$Comp -L R R7 -U 1 1 5178C3D2 -P 5450 5050 -F 0 "R7" V 5530 5050 50 0000 C CNN -F 1 "150" V 5450 5050 50 0000 C CNN - 1 5450 5050 - 1 0 0 -1 -$EndComp -$Comp -L SINE v1 -U 1 1 5178C33C -P 4350 4600 -F 0 "v1" H 4150 4700 60 0000 C CNN -F 1 "SINE" H 4150 4550 60 0000 C CNN -F 2 "R1" H 4050 4600 60 0000 C CNN - 1 4350 4600 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8 U1 -U 1 1 51779652 -P 6050 3150 -F 0 "U1" H 5900 3250 50 0000 C CNN -F 1 "VPLOT8" H 6200 3250 50 0000 C CNN - 1 6050 3150 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 517794FF -P 4600 3500 -F 0 "R1" V 4680 3500 50 0000 C CNN -F 1 "5k" V 4600 3500 50 0000 C CNN - 1 4600 3500 - 0 1 1 0 -$EndComp -$Comp -L R R6 -U 1 1 517794EA -P 6550 4250 -F 0 "R6" V 6630 4250 50 0000 C CNN -F 1 "150" V 6550 4250 50 0000 C CNN - 1 6550 4250 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 517794E3 -P 5500 4250 -F 0 "R4" V 5580 4250 50 0000 C CNN -F 1 "150" V 5500 4250 50 0000 C CNN - 1 5500 4250 - 1 0 0 -1 -$EndComp -$Comp -L R R5 -U 1 1 517794C9 -P 6550 2700 -F 0 "R5" V 6630 2700 50 0000 C CNN -F 1 "10k" V 6550 2700 50 0000 C CNN - 1 6550 2700 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 517794BE -P 5500 2700 -F 0 "R3" V 5580 2700 50 0000 C CNN -F 1 "10k" V 5500 2700 50 0000 C CNN - 1 5500 2700 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q2 -U 1 1 5177949E -P 6650 3500 -F 0 "Q2" H 6650 3350 50 0000 R CNN -F 1 "NPN" H 6650 3650 50 0000 R CNN - 1 6650 3500 - -1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 51779433 -P 4600 5800 -F 0 "R2" V 4680 5800 50 0000 C CNN -F 1 "R" V 4600 5800 50 0000 C CNN - 1 4600 5800 - 0 1 1 0 -$EndComp -$Comp -L DC v3 -U 1 1 51779424 -P 7350 4100 -F 0 "v3" H 7150 4200 60 0000 C CNN -F 1 "15" H 7150 4050 60 0000 C CNN -F 2 "R1" H 7050 4100 60 0000 C CNN - 1 7350 4100 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 51779415 -P 5400 3500 -F 0 "Q1" H 5400 3350 50 0000 R CNN -F 1 "NPN" H 5400 3650 50 0000 R CNN - 1 5400 3500 - 1 0 0 -1 -$EndComp -$Comp -L IDC v2 -U 1 1 5177940C -P 6050 5100 -F 0 "v2" H 5850 5200 60 0000 C CNN -F 1 "1m" H 5850 5050 60 0000 C CNN -F 2 "R1" H 5750 5100 60 0000 C CNN - 1 6050 5100 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis deleted file mode 100644 index 722124c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 15e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib Binary files differdeleted file mode 100644 index e93b428..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib +++ /dev/null diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir deleted file mode 100644 index 7f3611e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir +++ /dev/null @@ -1,41 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 29 April 2013 11:24:11 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U3 0 25 0 21 25 24 22 21 VPLOT8_1 -U13 23 VPLOT8_1 -v2 0 8 15 -U14 12 6 IPLOT -U11 5 18 IPLOT -R7 7 8 3k -U15 9 7 IPLOT -Q9 9 23 6 NPN -U12 23 1 IPLOT -R6 1 8 15.7k -U9 2 8 IPLOT -U6 11 8 IPLOT -U2 10 8 IPLOT -Q6 2 25 4 NPN -U8 3 4 IPLOT -R5 12 5 2.3k -U10 19 22 IPLOT -U7 13 21 IPLOT -U4 14 24 IPLOT -U5 15 16 IPLOT -U1 17 25 IPLOT -Q8 23 22 18 NPN -R4 12 19 3k -Q7 3 21 22 NPN -Q5 3 24 12 NPN -R1 0 17 28.6k -Q1 10 25 25 NPN -Q3 11 25 16 NPN -R3 12 13 20k -Q4 15 0 21 NPN -v1 12 0 15 -R2 12 14 20k -Q2 15 0 24 NPN - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt deleted file mode 100644 index 14076b8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt +++ /dev/null @@ -1,53 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 29 april 2013 11:24:11 am ist
-
-* Plotting option vplot8_1
-* Plotting option vplot8_1
-v2 0 8 15
-V_u14 12 6 0
-V_u11 5 18 0
-r7 7 8 3k
-V_u15 9 7 0
-q9 6 23 9 npn
-V_u12 23 1 0
-r6 1 8 15.7k
-V_u9 2 8 0
-V_u6 11 8 0
-V_u2 10 8 0
-q6 4 25 2 npn
-V_u8 3 4 0
-r5 12 5 2.3k
-V_u10 19 22 0
-V_u7 13 21 0
-V_u4 14 24 0
-V_u5 15 16 0
-V_u1 17 25 0
-q8 18 22 23 npn
-r4 12 19 3k
-q7 22 21 3 npn
-q5 12 24 3 npn
-r1 0 17 28.6k
-q1 25 25 10 npn
-q3 16 25 11 npn
-r3 12 13 20k
-q4 21 0 15 npn
-v1 12 0 15
-r2 12 14 20k
-q2 24 0 15 npn
-
-.dc v1 0e-00 15e-00 1e-00
-.plot v(0) v(25) v(0) v(21) v(25) v(24) v(22) v(21)
-.plot v(23)
-.plot i(V_u14)
-.plot i(V_u11)
-.plot i(V_u15)
-.plot i(V_u12)
-.plot i(V_u9)
-.plot i(V_u6)
-.plot i(V_u2)
-.plot i(V_u8)
-.plot i(V_u10)
-.plot i(V_u7)
-.plot i(V_u4)
-.plot i(V_u5)
-.plot i(V_u1)
-.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out deleted file mode 100644 index a08c832..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out +++ /dev/null @@ -1,58 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 29 april 2013 11:24:11 am ist
-
-* Plotting option vplot8_1
-* Plotting option vplot8_1
-v2 0 8 15
-V_u14 12 6 0
-V_u11 5 18 0
-r7 7 8 3k
-V_u15 9 7 0
-q9 6 23 9 npn
-V_u12 23 1 0
-r6 1 8 15.7k
-V_u9 2 8 0
-V_u6 11 8 0
-V_u2 10 8 0
-q6 4 25 2 npn
-V_u8 3 4 0
-r5 12 5 2.3k
-V_u10 19 22 0
-V_u7 13 21 0
-V_u4 14 24 0
-V_u5 15 16 0
-V_u1 17 25 0
-q8 18 22 23 npn
-r4 12 19 3k
-q7 22 21 3 npn
-q5 12 24 3 npn
-r1 0 17 28.6k
-q1 25 25 10 npn
-q3 16 25 11 npn
-r3 12 13 20k
-q4 21 0 15 npn
-v1 12 0 15
-r2 12 14 20k
-q2 24 0 15 npn
-
-.dc v1 0e-00 15e-00 1e-00
-
-* Control Statements
-.control
-run
-plot v(0) v(25) v(0) v(21) v(25) v(24) v(22) v(21)
-plot v(23)
-plot i(V_u14)
-plot i(V_u11)
-plot i(V_u15)
-plot i(V_u12)
-plot i(V_u9)
-plot i(V_u6)
-plot i(V_u2)
-plot i(V_u8)
-plot i(V_u10)
-plot i(V_u7)
-plot i(V_u4)
-plot i(V_u5)
-plot i(V_u1)
-.endc
-.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro deleted file mode 100644 index 767e17f..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Monday 29 April 2013 10:50:36 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.proj b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.proj deleted file mode 100644 index c332699..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_8.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch deleted file mode 100644 index cc68262..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch +++ /dev/null @@ -1,573 +0,0 @@ -EESchema Schematic File Version 2 date Monday 29 April 2013 11:24:17 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -EELAYER 43 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "29 apr 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 3450 1150 -Connection ~ 3300 5050 -Connection ~ 4900 2900 -$Comp -L VPLOT8_1 U3 -U 8 1 517E0976 -P 4900 2600 -F 0 "U3" H 4750 2700 50 0000 C CNN -F 1 "VPLOT8_1" H 5050 2700 50 0000 C CNN - 8 4900 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3750 3100 -Connection ~ 3900 2550 -Connection ~ 4000 3000 -Connection ~ 4750 2600 -Connection ~ 5500 2950 -Connection ~ 3900 4150 -$Comp -L VPLOT8_1 U3 -U 5 1 517E0908 -P 3900 3850 -F 0 "U3" H 3750 3950 50 0000 C CNN -F 1 "VPLOT8_1" H 4050 3950 50 0000 C CNN - 5 3900 3850 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 2 1 517E0903 -P 2950 3850 -F 0 "U3" H 2800 3950 50 0000 C CNN -F 1 "VPLOT8_1" H 3100 3950 50 0000 C CNN - 2 2950 3850 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 1 1 517E08FC -P 2750 2650 -F 0 "U3" H 2600 2750 50 0000 C CNN -F 1 "VPLOT8_1" H 2900 2750 50 0000 C CNN - 1 2750 2650 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 3 1 517E08F3 -P 3750 2800 -F 0 "U3" H 3600 2900 50 0000 C CNN -F 1 "VPLOT8_1" H 3900 2900 50 0000 C CNN - 3 3750 2800 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 6 1 517E08EB -P 4000 2700 -F 0 "U3" H 3850 2800 50 0000 C CNN -F 1 "VPLOT8_1" H 4150 2800 50 0000 C CNN - 6 4000 2700 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 4 1 517E08E7 -P 3900 2250 -F 0 "U3" H 3750 2350 50 0000 C CNN -F 1 "VPLOT8_1" H 4050 2350 50 0000 C CNN - 4 3900 2250 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U3 -U 7 1 517E08DA -P 4750 2300 -F 0 "U3" H 4600 2400 50 0000 C CNN -F 1 "VPLOT8_1" H 4900 2400 50 0000 C CNN - 7 4750 2300 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U13 -U 1 1 517E08D5 -P 5500 2650 -F 0 "U13" H 5350 2750 50 0000 C CNN -F 1 "VPLOT8_1" H 5650 2750 50 0000 C CNN - 1 5500 2650 - 1 0 0 -1 -$EndComp -Connection ~ 4000 5050 -Wire Wire Line - 4000 5050 4000 5550 -Wire Wire Line - 4000 5550 3350 5550 -Connection ~ 2350 2550 -Wire Wire Line - 2350 2550 2350 4150 -Wire Wire Line - 2350 4150 1900 4150 -Connection ~ 3100 1150 -Connection ~ 2400 2550 -Connection ~ 2650 2750 -Wire Wire Line - 2250 2550 2650 2550 -Wire Wire Line - 2650 2550 2650 2950 -Connection ~ 2750 2950 -Wire Wire Line - 2750 2950 2750 3300 -Wire Wire Line - 2750 3300 3750 3300 -Wire Wire Line - 3750 3300 3750 2950 -Wire Wire Line - 5250 2250 5250 2400 -Wire Wire Line - 5900 2750 5900 2450 -Wire Wire Line - 5900 3800 5900 4000 -Connection ~ 5250 2950 -Wire Wire Line - 5250 2950 5600 2950 -Wire Wire Line - 5250 3650 5250 4200 -Wire Wire Line - 4500 4350 4500 4550 -Wire Wire Line - 4500 3750 4500 3950 -Connection ~ 3450 2550 -Wire Wire Line - 3450 2550 4900 2550 -Wire Wire Line - 4900 2550 4900 3000 -Connection ~ 4350 1150 -Wire Wire Line - 3100 1650 3100 1950 -Wire Wire Line - 4600 1650 4600 1950 -Wire Wire Line - 2550 3250 2550 3350 -Wire Wire Line - 4350 3200 4600 3200 -Wire Wire Line - 3300 4550 3300 4350 -Wire Wire Line - 2550 4350 2550 4550 -Wire Wire Line - 2550 3850 2550 3950 -Connection ~ 3300 3150 -Wire Wire Line - 3300 3750 3300 3950 -Wire Wire Line - 3450 3150 3100 3150 -Wire Wire Line - 2650 2950 2800 2950 -Wire Wire Line - 3100 2750 3100 2450 -Wire Wire Line - 3450 2450 3450 2750 -Wire Wire Line - 3000 4150 2850 4150 -Wire Wire Line - 2550 3900 2950 3900 -Wire Wire Line - 2950 3900 2950 4150 -Connection ~ 2950 4150 -Connection ~ 2550 3900 -Wire Wire Line - 3100 2650 3950 2650 -Connection ~ 3100 2650 -Wire Wire Line - 3950 2650 3950 3000 -Wire Wire Line - 3950 3000 4050 3000 -Wire Wire Line - 4600 2800 4600 2450 -Wire Wire Line - 3300 3150 3300 3250 -Wire Wire Line - 3450 1650 3450 1950 -Wire Wire Line - 4350 1150 4350 2800 -Wire Wire Line - 4950 2600 4600 2600 -Connection ~ 4600 2600 -Connection ~ 4600 1150 -Wire Wire Line - 4500 3200 4500 3250 -Connection ~ 4500 3200 -Wire Wire Line - 2950 4150 4200 4150 -Wire Wire Line - 5250 2800 5250 3150 -Wire Wire Line - 5250 5050 5250 4700 -Connection ~ 4500 5050 -Wire Wire Line - 5900 3150 5900 3300 -Wire Wire Line - 5900 4500 5900 5050 -Wire Wire Line - 5900 5050 2550 5050 -Connection ~ 5250 5050 -Wire Wire Line - 5250 1650 5250 1750 -Wire Wire Line - 5900 1950 5900 1150 -Connection ~ 5250 1150 -Wire Wire Line - 2650 2750 2550 2750 -Wire Wire Line - 5900 1150 1900 1150 -Wire Wire Line - 1900 1150 1900 3250 -Wire Wire Line - 2450 2550 2450 5550 -Connection ~ 2450 2550 -$Comp -L DC v2 -U 1 1 517E089A -P 2900 5550 -F 0 "v2" H 2700 5650 60 0000 C CNN -F 1 "15" H 2700 5500 60 0000 C CNN -F 2 "R1" H 2600 5550 60 0000 C CNN - 1 2900 5550 - 0 -1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 517E07C2 -P 2400 2550 -F 0 "#FLG01" H 2400 2820 30 0001 C CNN -F 1 "PWR_FLAG" H 2400 2780 30 0000 C CNN - 1 2400 2550 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 517E07B3 -P 2250 2550 -F 0 "#PWR02" H 2250 2550 30 0001 C CNN -F 1 "GND" H 2250 2480 30 0001 C CNN - 1 2250 2550 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U14 -U 1 1 517E06CB -P 5900 2200 -F 0 "U14" H 5750 2300 50 0000 C CNN -F 1 "IPLOT" H 6050 2300 50 0000 C CNN - 1 5900 2200 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U11 -U 1 1 517E06B1 -P 5250 2000 -F 0 "U11" H 5100 2100 50 0000 C CNN -F 1 "IPLOT" H 5400 2100 50 0000 C CNN - 1 5250 2000 - 0 1 1 0 -$EndComp -$Comp -L R R7 -U 1 1 517E061A -P 5900 4250 -F 0 "R7" V 5980 4250 50 0000 C CNN -F 1 "3k" V 5900 4250 50 0000 C CNN - 1 5900 4250 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U15 -U 1 1 517E060D -P 5900 3550 -F 0 "U15" H 5750 3650 50 0000 C CNN -F 1 "IPLOT" H 6050 3650 50 0000 C CNN - 1 5900 3550 - 0 1 1 0 -$EndComp -$Comp -L NPN Q9 -U 1 1 517E05E2 -P 5800 2950 -F 0 "Q9" H 5800 2800 50 0000 R CNN -F 1 "NPN" H 5800 3100 50 0000 R CNN - 1 5800 2950 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U12 -U 1 1 517E05AE -P 5250 3400 -F 0 "U12" H 5100 3500 50 0000 C CNN -F 1 "IPLOT" H 5400 3500 50 0000 C CNN - 1 5250 3400 - 0 1 1 0 -$EndComp -$Comp -L R R6 -U 1 1 517E0593 -P 5250 4450 -F 0 "R6" V 5330 4450 50 0000 C CNN -F 1 "15.7k" V 5250 4450 50 0000 C CNN - 1 5250 4450 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U9 -U 1 1 517E0566 -P 4500 4800 -F 0 "U9" H 4350 4900 50 0000 C CNN -F 1 "IPLOT" H 4650 4900 50 0000 C CNN - 1 4500 4800 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U6 -U 1 1 517E0562 -P 3300 4800 -F 0 "U6" H 3150 4900 50 0000 C CNN -F 1 "IPLOT" H 3450 4900 50 0000 C CNN - 1 3300 4800 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U2 -U 1 1 517E055E -P 2550 4800 -F 0 "U2" H 2400 4900 50 0000 C CNN -F 1 "IPLOT" H 2700 4900 50 0000 C CNN - 1 2550 4800 - 0 1 1 0 -$EndComp -$Comp -L NPN Q6 -U 1 1 517E0538 -P 4400 4150 -F 0 "Q6" H 4400 4000 50 0000 R CNN -F 1 "NPN" H 4400 4300 50 0000 R CNN - 1 4400 4150 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U8 -U 1 1 517E0528 -P 4500 3500 -F 0 "U8" H 4350 3600 50 0000 C CNN -F 1 "IPLOT" H 4650 3600 50 0000 C CNN - 1 4500 3500 - 0 1 1 0 -$EndComp -$Comp -L R R5 -U 1 1 517E04FA -P 5250 1400 -F 0 "R5" V 5330 1400 50 0000 C CNN -F 1 "2.3k" V 5250 1400 50 0000 C CNN - 1 5250 1400 - 1 0 0 -1 -$EndComp -$Comp -L IPLOT U10 -U 1 1 517E04B8 -P 4600 2200 -F 0 "U10" H 4450 2300 50 0000 C CNN -F 1 "IPLOT" H 4750 2300 50 0000 C CNN - 1 4600 2200 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U7 -U 1 1 517E04B5 -P 3450 2200 -F 0 "U7" H 3300 2300 50 0000 C CNN -F 1 "IPLOT" H 3600 2300 50 0000 C CNN - 1 3450 2200 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U4 -U 1 1 517E04B0 -P 3100 2200 -F 0 "U4" H 2950 2300 50 0000 C CNN -F 1 "IPLOT" H 3250 2300 50 0000 C CNN - 1 3100 2200 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U5 -U 1 1 517E0481 -P 3300 3500 -F 0 "U5" H 3150 3600 50 0000 C CNN -F 1 "IPLOT" H 3450 3600 50 0000 C CNN - 1 3300 3500 - 0 1 1 0 -$EndComp -$Comp -L IPLOT U1 -U 1 1 517E0473 -P 2550 3600 -F 0 "U1" H 2400 3700 50 0000 C CNN -F 1 "IPLOT" H 2700 3700 50 0000 C CNN - 1 2550 3600 - 0 1 1 0 -$EndComp -$Comp -L NPN Q8 -U 1 1 517E0432 -P 5150 2600 -F 0 "Q8" H 5150 2450 50 0000 R CNN -F 1 "NPN" H 5150 2750 50 0000 R CNN - 1 5150 2600 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 517E0427 -P 4600 1400 -F 0 "R4" V 4680 1400 50 0000 C CNN -F 1 "3k" V 4600 1400 50 0000 C CNN - 1 4600 1400 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q7 -U 1 1 517E0411 -P 4700 3000 -F 0 "Q7" H 4700 2850 50 0000 R CNN -F 1 "NPN" H 4700 3150 50 0000 R CNN - 1 4700 3000 - -1 0 0 -1 -$EndComp -$Comp -L NPN Q5 -U 1 1 517E03F6 -P 4250 3000 -F 0 "Q5" H 4250 2850 50 0000 R CNN -F 1 "NPN" H 4250 3150 50 0000 R CNN - 1 4250 3000 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 517E03C0 -P 2550 3000 -F 0 "R1" V 2630 3000 50 0000 C CNN -F 1 "28.6k" V 2550 3000 50 0000 C CNN - 1 2550 3000 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q1 -U 1 1 517E03AD -P 2650 4150 -F 0 "Q1" H 2650 4000 50 0000 R CNN -F 1 "NPN" H 2650 4300 50 0000 R CNN - 1 2650 4150 - -1 0 0 -1 -$EndComp -$Comp -L NPN Q3 -U 1 1 517E03A2 -P 3200 4150 -F 0 "Q3" H 3200 4000 50 0000 R CNN -F 1 "NPN" H 3200 4300 50 0000 R CNN - 1 3200 4150 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 517E0387 -P 3450 1400 -F 0 "R3" V 3530 1400 50 0000 C CNN -F 1 "20k" V 3450 1400 50 0000 C CNN - 1 3450 1400 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q4 -U 1 1 517E0370 -P 3550 2950 -F 0 "Q4" H 3550 2800 50 0000 R CNN -F 1 "NPN" H 3550 3100 50 0000 R CNN - 1 3550 2950 - -1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 517E0351 -P 1900 3700 -F 0 "v1" H 1700 3800 60 0000 C CNN -F 1 "15" H 1700 3650 60 0000 C CNN -F 2 "R1" H 1600 3700 60 0000 C CNN - 1 1900 3700 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 517E0341 -P 3100 1400 -F 0 "R2" V 3180 1400 50 0000 C CNN -F 1 "20k" V 3100 1400 50 0000 C CNN - 1 3100 1400 - 1 0 0 -1 -$EndComp -$Comp -L NPN Q2 -U 1 1 517E0337 -P 3000 2950 -F 0 "Q2" H 3000 2800 50 0000 R CNN -F 1 "NPN" H 3000 3100 50 0000 R CNN - 1 3000 2950 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/analysis b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/analysis deleted file mode 100644 index f74e3c8..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/analysis +++ /dev/null @@ -1 +0,0 @@ -.dc v1 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt deleted file mode 100644 index cb5beb4..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt +++ /dev/null @@ -1,22 +0,0 @@ -* CD4007 NMOS and PMOS transistor SPICE models - -* Typical - Typical Condition - -.model MbreakND NMOS -+ Level=1 Gamma= 0 Xj=0 -+ Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=1.4 Lambda=0.01 -+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p -+ Cgdo=0.1p Is=16.64p N=1 - -*The default W and L is 30 and 10 um respectively and AD and AS -*should not be included. - - -.model MbreakPD PMOS -+ Level=1 Gamma= 0 Xj=0 -+ Tox=1200n Phi=.6 Rs=0 Kp=55u Vto=-1.2 Lambda=0.04 -+ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p -+ Cgdo=0.2p Is=16.64p N=1 - -*The default W and L is 60 and 10 um respectively and AD and AS -*should not be included. diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak deleted file mode 100644 index cc8bedb..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak +++ /dev/null @@ -1,118 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Friday 10 May 2013 04:54:25 PM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# MOS_N -# -DEF MOS_N M 0 0 N Y 1 F N -F0 "M" 10 170 60 H V R CNN -F1 "MOS_N" 10 -150 60 H V R CNN -ALIAS MOSFET_N -DRAW -P 2 0 1 8 -50 -100 -50 100 N -P 2 0 1 10 0 -150 0 150 N -P 2 0 1 0 100 -100 0 -100 N -P 2 0 1 0 100 100 0 100 N -P 3 0 1 8 100 -100 100 0 50 0 N -P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N -X D D 100 200 100 D 40 40 1 1 P -X G G -200 0 150 R 40 40 1 1 I -X S S 100 -200 100 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# MOS_P -# -DEF MOS_P M 0 40 Y N 1 F N -F0 "M" 0 190 60 H V R CNN -F1 "MOS_P" 0 -180 60 H V R CNN -ALIAS MOSFET_P -DRAW -P 2 0 1 8 -50 -100 -50 100 N -P 2 0 1 10 0 -150 0 150 N -P 2 0 1 8 30 0 0 0 N -P 2 0 1 0 100 -100 0 -100 N -P 2 0 1 0 100 100 0 100 N -P 3 0 1 0 80 0 100 0 100 -100 N -P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N -X D D 100 200 100 D 40 40 1 1 P -X G G -200 0 150 R 40 40 1 1 I -X S S 100 -200 100 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.lib deleted file mode 100644 index 5680002..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.lib +++ /dev/null @@ -1,118 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thursday 16 May 2013 11:24:57 AM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# dc -# -DEF dc v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# MOS_N -# -DEF MOS_N M 0 0 N Y 1 F N -F0 "M" 10 170 60 H V R CNN -F1 "MOS_N" 10 -150 60 H V R CNN -ALIAS MOSFET_N -DRAW -P 2 0 1 8 -50 -100 -50 100 N -P 2 0 1 10 0 -150 0 150 N -P 2 0 1 0 100 -100 0 -100 N -P 2 0 1 0 100 100 0 100 N -P 3 0 1 8 100 -100 100 0 50 0 N -P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N -X D D 100 200 100 D 40 40 1 1 P -X G G -200 0 150 R 40 40 1 1 I -X S S 100 -200 100 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# MOS_P -# -DEF MOS_P M 0 40 Y N 1 F N -F0 "M" 0 190 60 H V R CNN -F1 "MOS_P" 0 -180 60 H V R CNN -ALIAS MOSFET_P -DRAW -P 2 0 1 8 -50 -100 -50 100 N -P 2 0 1 10 0 -150 0 150 N -P 2 0 1 8 30 0 0 0 N -P 2 0 1 0 100 -100 0 -100 N -P 2 0 1 0 100 100 0 100 N -P 3 0 1 0 80 0 100 0 100 -100 N -P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N -X D D 100 200 100 D 40 40 1 1 P -X G G -200 0 150 R 40 40 1 1 I -X S S 100 -200 100 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# vplot8_1 -# -DEF vplot8_1 U 0 40 Y Y 8 F N -F0 "U" -150 100 50 H V C CNN -F1 "vplot8_1" 150 100 50 H V C CNN -DRAW -C 0 0 100 0 0 0 N -X + 1 0 -300 200 U 40 40 1 1 I -X + 2 0 -300 200 U 40 40 2 1 I -X + 3 0 -300 200 U 40 40 3 1 I -X + 4 0 -300 200 U 40 40 4 1 I -X + 5 0 -300 200 U 40 40 5 1 I -X + 6 0 -300 200 U 40 40 6 1 I -X + 7 0 -300 200 U 40 40 7 1 I -X + 8 0 -300 200 U 40 40 8 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak deleted file mode 100644 index e14fb9e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak +++ /dev/null @@ -1,194 +0,0 @@ -EESchema Schematic File Version 2 date Friday 10 May 2013 04:54:25 PM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_9.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "10 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5750 3600 -Wire Wire Line - 5750 3600 5300 3600 -Wire Wire Line - 5300 3600 5300 3850 -Connection ~ 5600 3450 -Wire Wire Line - 5600 3650 5600 3450 -Wire Wire Line - 6050 3450 6400 3450 -Connection ~ 6050 4300 -Wire Wire Line - 6050 4050 6050 4350 -Wire Wire Line - 6050 4350 5100 4350 -Wire Wire Line - 6650 3900 6650 4300 -Wire Wire Line - 6050 2850 6050 2700 -Wire Wire Line - 6050 3250 6050 3650 -Wire Wire Line - 5750 3050 5750 3850 -Connection ~ 6050 3450 -Wire Wire Line - 6400 3450 6400 3750 -Connection ~ 6400 4300 -Wire Wire Line - 6050 2700 6650 2700 -Wire Wire Line - 6650 2700 6650 3000 -Wire Wire Line - 5750 3450 5100 3450 -Connection ~ 5750 3450 -Wire Wire Line - 5100 3450 5100 3550 -Wire Wire Line - 6400 4400 6400 4150 -Connection ~ 5500 3450 -Wire Wire Line - 6650 4300 6050 4300 -Connection ~ 6200 3450 -Wire Wire Line - 5600 4050 5600 4350 -Connection ~ 5600 4350 -$Comp -L MOS_N M3 -U 1 1 518CD8BE -P 5500 3850 -F 0 "M3" H 5510 4020 60 0000 R CNN -F 1 "MOS_N" H 5510 3700 60 0000 R CNN - 1 5500 3850 - 1 0 0 -1 -$EndComp -$Comp -L MOS_P M1 -U 1 1 5188E486 -P 5950 3050 -F 0 "M1" H 5950 3240 60 0000 R CNN -F 1 "MOS_P" H 5950 2870 60 0000 R CNN - 1 5950 3050 - 1 0 0 1 -$EndComp -$Comp -L MOS_N M2 -U 1 1 5188E477 -P 5950 3850 -F 0 "M2" H 5960 4020 60 0000 R CNN -F 1 "MOS_N" H 5960 3700 60 0000 R CNN - 1 5950 3850 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 5188E0A2 -P 6200 3150 -F 0 "U2" H 6050 3250 50 0000 C CNN -F 1 "VPLOT8_1" H 6350 3250 50 0000 C CNN - 2 6200 3150 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5188E094 -P 6400 4300 -F 0 "#FLG01" H 6400 4570 30 0001 C CNN -F 1 "PWR_FLAG" H 6400 4530 30 0000 C CNN - 1 6400 4300 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 517F5425 -P 6650 3450 -F 0 "v2" H 6450 3550 60 0000 C CNN -F 1 "10" H 6450 3400 60 0000 C CNN -F 2 "R1" H 6350 3450 60 0000 C CNN - 1 6650 3450 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 517F5879 -P 5500 3150 -F 0 "U2" H 5350 3250 50 0000 C CNN -F 1 "VPLOT8_1" H 5650 3250 50 0000 C CNN - 1 5500 3150 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 517F5470 -P 6400 4400 -F 0 "#PWR02" H 6400 4400 30 0001 C CNN -F 1 "GND" H 6400 4330 30 0001 C CNN - 1 6400 4400 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 517F544C -P 5100 3900 -F 0 "v1" H 4900 4000 60 0000 C CNN -F 1 "DC" H 4900 3850 60 0000 C CNN -F 2 "R1" H 4800 3900 60 0000 C CNN - 1 5100 3900 - 1 0 0 -1 -$EndComp -$Comp -L C C1 -U 1 1 517F53E7 -P 6400 3950 -F 0 "C1" H 6450 4050 50 0000 L CNN -F 1 ".5p" H 6450 3850 50 0000 L CNN - 1 6400 3950 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir deleted file mode 100644 index f3aa33e..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir +++ /dev/null @@ -1,14 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 16 May 2013 11:24:53 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -M1 4 3 1 MOS_P -M2 4 3 0 MOS_N -U2 3 4 VPLOT8_1 -v2 1 0 10 -v1 3 0 DC -C1 4 0 .5p - -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt deleted file mode 100644 index 0699b0a..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt +++ /dev/null @@ -1,14 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:24:53 am ist -.include mos_p.lib -.include mos_n.lib - -m1 4 3 1 1 mos_p -m2 4 3 0 0 mos_n -* Plotting option vplot8_1 -v2 1 0 10 -v1 3 0 dc 10 -c1 4 0 .5p - -.dc v1 0e-00 10e-00 1e-00 -.plot v(3) v(4) -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out deleted file mode 100644 index 4fc3ec2..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out +++ /dev/null @@ -1,19 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:24:53 am ist -.include mos_p.lib -.include mos_n.lib - -m1 4 3 1 1 mos_p -m2 4 3 0 0 mos_n -* Plotting option vplot8_1 -v2 1 0 10 -v1 3 0 dc 10 -c1 4 0 .5p - -.dc v1 0e-00 10e-00 1e-00 - -* Control Statements -.control -run -plot v(3) v(4) -.endc -.end diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro deleted file mode 100644 index d4ca737..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Tuesday 30 April 2013 10:42:25 AM IST -last_client=eeschema -[eeschema] -version=1 -LibDir= -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/holy/OSCAD/library/analogSpice -LibName32=/home/holy/OSCAD/library/analogXSpice -LibName33=/home/holy/OSCAD/library/convergenceAidSpice -LibName34=/home/holy/OSCAD/library/converterSpice -LibName35=/home/holy/OSCAD/library/digitalSpice -LibName36=/home/holy/OSCAD/library/digitalXSpice -LibName37=/home/holy/OSCAD/library/linearSpice -LibName38=/home/holy/OSCAD/library/measurementSpice -LibName39=/home/holy/OSCAD/library/portSpice -LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj deleted file mode 100644 index 8fac45c..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile example_9.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch deleted file mode 100644 index de8111b..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch +++ /dev/null @@ -1,175 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 16 May 2013 11:24:57 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:convergenceAidSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:digitalXSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:example_9.4-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "16 may 2013" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5750 3600 -Wire Wire Line - 6050 3450 6400 3450 -Connection ~ 6050 4300 -Wire Wire Line - 6050 4050 6050 4350 -Wire Wire Line - 6050 4350 5100 4350 -Wire Wire Line - 6650 3900 6650 4300 -Wire Wire Line - 6050 2850 6050 2700 -Wire Wire Line - 6050 3250 6050 3650 -Wire Wire Line - 5750 3050 5750 3850 -Connection ~ 6050 3450 -Wire Wire Line - 6400 3450 6400 3750 -Connection ~ 6400 4300 -Wire Wire Line - 6050 2700 6650 2700 -Wire Wire Line - 6650 2700 6650 3000 -Wire Wire Line - 5750 3450 5100 3450 -Connection ~ 5750 3450 -Wire Wire Line - 5100 3450 5100 3550 -Wire Wire Line - 6400 4400 6400 4150 -Connection ~ 5500 3450 -Wire Wire Line - 6650 4300 6050 4300 -Connection ~ 6200 3450 -$Comp -L MOS_P M1 -U 1 1 5188E486 -P 5950 3050 -F 0 "M1" H 5950 3240 60 0000 R CNN -F 1 "MOS_P" H 5950 2870 60 0000 R CNN - 1 5950 3050 - 1 0 0 1 -$EndComp -$Comp -L MOS_N M2 -U 1 1 5188E477 -P 5950 3850 -F 0 "M2" H 5960 4020 60 0000 R CNN -F 1 "MOS_N" H 5960 3700 60 0000 R CNN - 1 5950 3850 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 2 1 5188E0A2 -P 6200 3150 -F 0 "U2" H 6050 3250 50 0000 C CNN -F 1 "VPLOT8_1" H 6350 3250 50 0000 C CNN - 2 6200 3150 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5188E094 -P 6400 4300 -F 0 "#FLG01" H 6400 4570 30 0001 C CNN -F 1 "PWR_FLAG" H 6400 4530 30 0000 C CNN - 1 6400 4300 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 517F5425 -P 6650 3450 -F 0 "v2" H 6450 3550 60 0000 C CNN -F 1 "10" H 6450 3400 60 0000 C CNN -F 2 "R1" H 6350 3450 60 0000 C CNN - 1 6650 3450 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 517F5879 -P 5500 3150 -F 0 "U2" H 5350 3250 50 0000 C CNN -F 1 "VPLOT8_1" H 5650 3250 50 0000 C CNN - 1 5500 3150 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 517F5470 -P 6400 4400 -F 0 "#PWR02" H 6400 4400 30 0001 C CNN -F 1 "GND" H 6400 4330 30 0001 C CNN - 1 6400 4400 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 517F544C -P 5100 3900 -F 0 "v1" H 4900 4000 60 0000 C CNN -F 1 "DC" H 4900 3850 60 0000 C CNN -F 2 "R1" H 4800 3900 60 0000 C CNN - 1 5100 3900 - 1 0 0 -1 -$EndComp -$Comp -L C C1 -U 1 1 517F53E7 -P 6400 3950 -F 0 "C1" H 6450 4050 50 0000 L CNN -F 1 ".5p" H 6450 3850 50 0000 L CNN - 1 6400 3950 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib deleted file mode 100644 index 23ac1f6..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model mos_n NMOS( Cgso=877.2p Tox=100n Rs=70.6m Tt=140n Vto=-3.67 -+ Pb=.8 Rg=.811 Theta=0 Phi=.6 Fc=.5 -+ Delta=0 Vmax=0 Kappa=0 Rds=444.4K Level=3 -+ L=2u Mj=.5 Uo=300 Eta=0 W=1.9 -+ Cgdo=369.3p Gamma=0 Xj=0 Rd=60.66m Cbd=2.141n -+ Is=52.23E-18 N=2 Kp=10.15u ) diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib deleted file mode 100644 index 2c58d87..0000000 --- a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib +++ /dev/null @@ -1,6 +0,0 @@ -.model mos_p PMOS( Cgso=877.2p Tox=100n Rs=70.6m Tt=140n Vto=-3.67 -+ Pb=.8 Rg=.811 Theta=0 Phi=.6 Fc=.5 -+ Delta=0 Vmax=0 Kappa=0 Rds=444.4K Level=3 -+ L=2u Mj=.5 Uo=300 Eta=0 W=1.9 -+ Cgdo=369.3p Gamma=0 Xj=0 Rd=60.66m Cbd=2.141n -+ Is=52.23E-18 N=2 Kp=10.15u )
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