index
:
FreeEDA/.git
master
Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad)
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
OSCAD
/
Examples
/
sedra_smith
/
chapter_3
/
example_3.11
/
analysis
blob: bd0d4e68c1b13d0a63203e7146d64ec4c77548eb (
plain
)
1
.dc v1 0e-00 15e-00 5e-03