| Mode | Name | Size | |
|---|---|---|---|
| d--------- | chapter_12 / example_12.8 | 39 | logplain |
| d--------- | chapter_2 | 190 | logplain |
| d--------- | chapter_3 | 573 | logplain |
| d--------- | chapter_4 / example_4.5 | 38 | logplain |
| d--------- | chapter_5 | 343 | logplain |
| d--------- | chapter_7 | 114 | logplain |
| d--------- | chapter_8 | 76 | logplain |
| d--------- | chapter_9 / example_9.4 | 38 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |