| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 25 | logplain |
| -rw-r--r-- | example_12.8-cache.bak | 2729 | logplain |
| -rw-r--r-- | example_12.8-cache.lib | 2728 | logplain |
| -rw-r--r-- | example_12.8.bak | 3430 | logplain |
| -rw-r--r-- | example_12.8.cir | 446 | logplain |
| -rw-r--r-- | example_12.8.cir.ckt | 282 | logplain |
| -rw-r--r-- | example_12.8.cir.out | 322 | logplain |
| -rw-r--r-- | example_12.8.pro | 1408 | logplain |
| -rw-r--r-- | example_12.8.proj | 31 | logplain |
| -rw-r--r-- | example_12.8.sch | 3961 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |