analysis « example_12.8 « chapter_12 « sedra_smith « Examples « OSCAD - FreeEDA/.git - Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad)

summary refs log tree commit diff

path: root/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/analysis

blob: ea22c2911a1ba2cf64c97d7c9cb6f1e1061eb9ef (plain)

1	`.tran 1e-00 3e-00 0e-00`