analysis « example_7.3 « chapter_7 « sedra_smith « Examples « OSCAD - FreeEDA/.git - Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad)

summary refs log tree commit diff

path: root/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis

blob: 0e8f99625da839d676bb093ff9deec401272dbb9 (plain)

1	`.tran 2e-03 20e-03 0e-00`