| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_7.3-cache.lib | 2127 | logplain |
| -rw-r--r-- | example_7.3.cir | 438 | logplain |
| -rw-r--r-- | example_7.3.cir.ckt | 262 | logplain |
| -rw-r--r-- | example_7.3.cir.out | 303 | logplain |
| -rw-r--r-- | example_7.3.pro | 1409 | logplain |
| -rw-r--r-- | example_7.3.proj | 30 | logplain |
| -rw-r--r-- | example_7.3.sch | 3084 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |