index
:
FreeEDA/.git
master
Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad)
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
OSCAD
/
Examples
/
sedra_smith
/
chapter_3
/
example_3.13
/
analysis
blob: 11459c7bc16db14a9e03398746ba56b87623d1f5 (
plain
)
1
.dc v1 0e-00 12e-00 12e-03
