| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 28 | logplain |
| -rw-r--r-- | example_3.13-cache.lib | 2004 | logplain |
| -rw-r--r-- | example_3.13.bak | 3727 | logplain |
| -rw-r--r-- | example_3.13.cir | 474 | logplain |
| -rw-r--r-- | example_3.13.cir.ckt | 312 | logplain |
| -rw-r--r-- | example_3.13.cir.out | 351 | logplain |
| -rw-r--r-- | example_3.13.pro | 1410 | logplain |
| -rw-r--r-- | example_3.13.proj | 31 | logplain |
| -rw-r--r-- | example_3.13.sch | 3702 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |