index
:
FreeEDA/.git
master
Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad)
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
OSCAD
/
Examples
/
sedra_smith
/
chapter_5
/
example_5.8
/
analysis
blob: 64c6d697e9d909f6d5bcd4a8d4a65bd3847e18e0 (
plain
)
1
.tran 1e-03 2e-03 0e-00