diff options
| author | Akshay NH | 2018-06-28 19:22:03 +0530 |
|---|---|---|
| committer | Akshay NH | 2018-06-28 19:22:03 +0530 |
| commit | d1edc2c0c9b8d823892b94482e01451e82c3eec1 (patch) | |
| tree | 9fb54dfd93a975be8b2a8cb29b21eb5639ac29ef | |
| download | eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.gz eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.bz2 eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.zip | |
adding kicad analog and digital circuits
318 files changed, 28544 insertions, 0 deletions
diff --git a/analog circuits/BJT_frequency_response/BJT_frequency_response-cache.lib b/analog circuits/BJT_frequency_response/BJT_frequency_response-cache.lib new file mode 100644 index 0000000..e2fbd07 --- /dev/null +++ b/analog circuits/BJT_frequency_response/BJT_frequency_response-cache.lib @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Transistor_BJT:BC547 +# +DEF Transistor_BJT:BC547 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "Transistor_BJT:BC547" 200 0 50 H V L CNN +F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC546 BC548 BC549 BC550 BC337 BC338 +$FPLIST + TO?92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 25 0 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 200 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/BJT_frequency_response/BJT_frequency_response.bak b/analog circuits/BJT_frequency_response/BJT_frequency_response.bak new file mode 100644 index 0000000..4c4473d --- /dev/null +++ b/analog circuits/BJT_frequency_response/BJT_frequency_response.bak @@ -0,0 +1,244 @@ +EESchema Schematic File Version 4
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diff --git a/analog circuits/BJT_frequency_response/BJT_frequency_response.cir b/analog circuits/BJT_frequency_response/BJT_frequency_response.cir new file mode 100644 index 0000000..3e9e3a6 --- /dev/null +++ b/analog circuits/BJT_frequency_response/BJT_frequency_response.cir @@ -0,0 +1,16 @@ +.title KiCad schematic +.include "/home/akshay/Desktop/analog circuits/libs/fzt1049a.lib" +R1 Net-_C1-Pad2_ Net-_R1-Pad2_ 50 +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 40u +R2 Net-_R2-Pad1_ Net-_R2-Pad2_ 200k +R3 GND Net-_R2-Pad1_ 50k +R5 Net-_C3-Pad2_ Net-_R2-Pad2_ 2k +C3 out Net-_C3-Pad2_ 10p +R4 GND Net-_C2-Pad2_ 1.5k +C2 GND Net-_C2-Pad2_ 100u +R6 GND out 1k +Q1 Net-_C3-Pad2_ Net-_C1-Pad1_ Net-_C2-Pad2_ FZT1049A +V1 Net-_R1-Pad2_ GND ac 500m +V2 Net-_R2-Pad2_ GND dc 10 +.ac dec 10 1 1000meg +.end diff --git a/analog circuits/BJT_frequency_response/BJT_frequency_response.kicad_pcb b/analog circuits/BJT_frequency_response/BJT_frequency_response.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/BJT_frequency_response/BJT_frequency_response.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/BJT_frequency_response/BJT_frequency_response.pro b/analog circuits/BJT_frequency_response/BJT_frequency_response.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/BJT_frequency_response/BJT_frequency_response.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 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0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6150 3300 50 0001 L CNN +F 4 "Q" H 6150 3300 50 0001 C CNN "Spice_Primitive" +F 5 "Y" H 6150 3300 50 0001 C CNN "Spice_Netlist_Enabled" +F 6 "FZT1049A" H 6150 3300 50 0001 C CNN "Spice_Model" +F 7 "/home/akshay/Desktop/analog circuits/libs/fzt1049a.lib" H 6150 3300 50 0001 C CNN "Spice_Lib_File" + 1 6150 3300 + 1 0 0 -1 +$EndComp +Connection ~ 8450 4700 +Wire Wire Line + 6800 4700 8450 4700 +$Comp +L power:GND #PWR0101 +U 1 1 5B23FDC0 +P 5850 4900 +F 0 "#PWR0101" H 5850 4650 50 0001 C CNN +F 1 "GND" H 5855 4727 50 0000 C CNN +F 2 "" H 5850 4900 50 0001 C CNN +F 3 "" H 5850 4900 50 0001 C CNN + 1 5850 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 4900 5850 4700 +Connection ~ 5850 4700 +Wire Wire Line + 5850 4700 6250 4700 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B242617 +P 3150 4000 +F 0 "V1" H 3378 4046 50 0000 L CNN +F 1 "VSOURCE" H 3378 3955 50 0000 L CNN +F 2 "" H 3150 4000 50 0001 C CNN +F 3 "" H 3150 4000 50 0001 C CNN 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+out +Wire Wire Line + 8100 2150 8350 2150 +Wire Wire Line + 8350 2150 8350 2700 +Connection ~ 8350 2700 +Wire Wire Line + 8350 2700 8450 2700 +$EndSCHEMATC diff --git a/analog circuits/Notch_filter/Notch_filter-cache.lib b/analog circuits/Notch_filter/Notch_filter-cache.lib new file mode 100644 index 0000000..ba5f3e4 --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter-cache.lib @@ -0,0 +1,144 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:CP1 +# +DEF Device:CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Notch_filter-rescue:GND-sallen_key_schlib +# +DEF Notch_filter-rescue:GND-sallen_key_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "Notch_filter-rescue:GND-sallen_key_schlib" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Notch_filter-rescue:Generic_Opamp-sallen_key_schlib +# +DEF Notch_filter-rescue:Generic_Opamp-sallen_key_schlib U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Notch_filter-rescue:Generic_Opamp-sallen_key_schlib" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Notch_filter-rescue:VDD-sallen_key_schlib +# +DEF Notch_filter-rescue:VDD-sallen_key_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "Notch_filter-rescue:VDD-sallen_key_schlib" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Notch_filter-rescue:VSOURCE-sallen_key_schlib +# +DEF ~Notch_filter-rescue:VSOURCE-sallen_key_schlib V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "Notch_filter-rescue:VSOURCE-sallen_key_schlib" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# Notch_filter-rescue:VSS-sallen_key_schlib +# +DEF Notch_filter-rescue:VSS-sallen_key_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "Notch_filter-rescue:VSS-sallen_key_schlib" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/Notch_filter/Notch_filter-rescue.dcm b/analog circuits/Notch_filter/Notch_filter-rescue.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/analog circuits/Notch_filter/Notch_filter-rescue.lib b/analog circuits/Notch_filter/Notch_filter-rescue.lib new file mode 100644 index 0000000..a365450 --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter-rescue.lib @@ -0,0 +1,81 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# GND-sallen_key_schlib +# +DEF GND-sallen_key_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND-sallen_key_schlib" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp-sallen_key_schlib +# +DEF Generic_Opamp-sallen_key_schlib U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp-sallen_key_schlib" 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0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS-sallen_key_schlib +# +DEF VSS-sallen_key_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS-sallen_key_schlib" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/Notch_filter/Notch_filter.bak b/analog circuits/Notch_filter/Notch_filter.bak new file mode 100644 index 0000000..691c36e --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter.bak @@ -0,0 +1,321 @@ +EESchema Schematic File Version 4
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diff --git a/analog circuits/Notch_filter/Notch_filter.cir b/analog circuits/Notch_filter/Notch_filter.cir new file mode 100644 index 0000000..c44d88d --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter.cir @@ -0,0 +1,15 @@ +.title KiCad schematic +.include "/home/akshay/Desktop/analog circuits/libs/ad8051.lib" +R1 Net-_C1-Pad2_ Net-_R1-Pad2_ 5.6k +R2 Net-_R2-Pad1_ Net-_R1-Pad2_ 5.6k +R3 Net-_R2-Pad1_ GND 5.6k +R4 out Net-_C1-Pad1_ 5.6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 0.1u +C2 out Net-_C1-Pad2_ 1000p +R5 out GND 5.6k +V1 Net-_R1-Pad2_ GND ac 1 +XU1 Net-_C1-Pad1_ Net-_R2-Pad1_ VDD VSS out AD8051 +V2 VDD GND DC 10 +V3 GND VSS DC 10 +.ac dec 10 1 1Meg +.end diff --git a/analog circuits/Notch_filter/Notch_filter.kicad_pcb b/analog circuits/Notch_filter/Notch_filter.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/Notch_filter/Notch_filter.pro b/analog circuits/Notch_filter/Notch_filter.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/Notch_filter/Notch_filter.sch b/analog circuits/Notch_filter/Notch_filter.sch new file mode 100644 index 0000000..25836bd --- /dev/null +++ b/analog circuits/Notch_filter/Notch_filter.sch @@ -0,0 +1,320 @@ +EESchema Schematic File Version 4 +LIBS:Notch_filter-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R1 +U 1 1 5B0F87D4 +P 4850 3500 +F 0 "R1" V 4643 3500 50 0000 C CNN +F 1 "5.6k" V 4734 3500 50 0000 C CNN +F 2 "" V 4780 3500 50 0001 C CNN +F 3 "~" H 4850 3500 50 0001 C CNN + 1 4850 3500 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0F881C +P 4850 3800 +F 0 "R2" V 4643 3800 50 0000 C CNN +F 1 "5.6k" V 4734 3800 50 0000 C CNN +F 2 "" V 4780 3800 50 0001 C CNN +F 3 "~" H 4850 3800 50 0001 C CNN + 1 4850 3800 + 0 1 1 0 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0F8AE7 +P 5900 4100 +F 0 "R3" H 5970 4146 50 0000 L CNN +F 1 "5.6k" H 5970 4055 50 0000 L CNN +F 2 "" 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Notch_filter-rescue:VSOURCE-sallen_key_schlib V1 +U 1 1 57336052 +P 3050 4450 +F 0 "V1" H 3178 4496 50 0000 L CNN +F 1 "AC 1" H 3178 4405 50 0000 L CNN +F 2 "" H 3050 4450 50 0000 C CNN +F 3 "" H 3050 4450 50 0000 C CNN +F 4 "V" H 3050 4450 50 0001 C CNN "Spice_Primitive" +F 5 "ac 1" H 3050 4450 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3050 4450 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3050 4450 + 1 0 0 -1 +$EndComp +Text Notes 7800 3450 0 60 ~ 0 +.ac dec 10 1 1Meg\n +$Comp +L Notch_filter-rescue:Generic_Opamp-sallen_key_schlib U1 +U 1 1 5788FF9F +P 6550 3600 +F 0 "U1" H 6650 3750 50 0000 L CNN +F 1 "AD8051" H 6600 3450 50 0000 L CNN +F 2 "" H 6450 3500 50 0000 C CNN +F 3 "" H 6550 3600 50 0000 C CNN +F 4 "X" H 6550 3600 60 0001 C CNN "Spice_Primitive" +F 5 "AD8051" H 6550 3600 60 0001 C CNN "Spice_Model" +F 6 "/home/akshay/Desktop/analog circuits/libs/ad8051.lib" H 6550 3600 60 0001 C CNN "Spice_Lib_File" +F 7 "Y" H 6550 3600 60 0001 C CNN "Spice_Netlist_Enabled" + 1 6550 3600 + 1 0 0 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+F 1 "GND" H 9405 1927 50 0000 C CNN +F 2 "" H 9400 2100 50 0000 C CNN +F 3 "" H 9400 2100 50 0000 C CNN + 1 9400 2100 + 1 0 0 -1 +$EndComp +$Comp +L Notch_filter-rescue:VDD-sallen_key_schlib #PWR05 +U 1 1 578903C0 +P 9650 1600 +F 0 "#PWR05" H 9650 1450 50 0001 C CNN +F 1 "VDD" H 9667 1773 50 0000 C CNN +F 2 "" H 9650 1600 50 0000 C CNN +F 3 "" H 9650 1600 50 0000 C CNN + 1 9650 1600 + 1 0 0 -1 +$EndComp +$Comp +L Notch_filter-rescue:VSS-sallen_key_schlib #PWR06 +U 1 1 578903E2 +P 9650 2600 +F 0 "#PWR06" H 9650 2450 50 0001 C CNN +F 1 "VSS" H 9668 2773 50 0000 C CNN +F 2 "" H 9650 2600 50 0000 C CNN +F 3 "" H 9650 2600 50 0000 C CNN + 1 9650 2600 + -1 0 0 1 +$EndComp +$Comp +L Notch_filter-rescue:VDD-sallen_key_schlib #PWR02 +U 1 1 57890425 +P 6450 3300 +F 0 "#PWR02" H 6450 3150 50 0001 C CNN +F 1 "VDD" H 6467 3473 50 0000 C CNN +F 2 "" H 6450 3300 50 0000 C CNN +F 3 "" H 6450 3300 50 0000 C CNN + 1 6450 3300 + 1 0 0 -1 +$EndComp +$Comp +L Notch_filter-rescue:VSS-sallen_key_schlib #PWR03 +U 1 1 57890453 +P 6450 3900 +F 0 "#PWR03" H 6450 3750 50 0001 C CNN +F 1 "VSS" H 6468 4073 50 0000 C CNN +F 2 "" H 6450 3900 50 0000 C CNN +F 3 "" H 6450 3900 50 0000 C CNN + 1 6450 3900 + -1 0 0 1 +$EndComp +Wire Wire Line + 9650 2100 9400 2100 +Wire Wire Line + 9650 2600 9650 2550 +Wire Wire Line + 9650 1600 9650 1650 +Wire Wire Line + 9650 2050 9650 2100 +Connection ~ 9650 2100 +Wire Wire Line + 9650 2100 9650 2150 +Wire Wire Line + 3050 3650 3050 4250 +Wire Wire Line + 3050 4650 3050 5150 +$EndSCHEMATC diff --git a/analog circuits/Notch_filter/sym-lib-table b/analog circuits/Notch_filter/sym-lib-table new file mode 100644 index 0000000..47a29ff --- /dev/null +++ b/analog circuits/Notch_filter/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name Notch_filter-rescue)(type Legacy)(uri ${KIPRJMOD}/Notch_filter-rescue.lib)(options "")(descr "")) +) diff --git a/analog circuits/R-2R DAC/R-2R DAC-cache.lib b/analog circuits/R-2R DAC/R-2R DAC-cache.lib new file mode 100644 index 0000000..f84b4bf --- /dev/null +++ b/analog circuits/R-2R DAC/R-2R DAC-cache.lib @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Amplifier_Operational:AD8620 +# +DEF Amplifier_Operational:AD8620 U 0 20 Y Y 3 L N +F0 "U" 0 200 50 H V L CNN +F1 "Amplifier_Operational:AD8620" 0 -200 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS LM358 AD8620 LMC6062 LMC6082 TL062 TL072 TL082 NE5532 SA5532 RC4558 RC4560 RC4580 LMV358 TS912 TSV912IDT TSV912IST TLC272 TLC277 MCP602 OPA2134 OPA2340 OPA2376xxD OPA2376xxDGK MC33078 MC33178 LM4562 OP249 OP275 ADA4075-2 MCP6002-xP MCP6002-xSN MCP6002-xMS LM7332 OPA2333xxD OPA2333xxDGK LMC6482 LT1492 LTC6081xMS8 LM6172 MCP6L92 NJM2043 NJM2114 NJM4556A NJM4558 NJM4559 NJM4560 NJM4580 NJM5532 ADA4807-2ARM OPA2691 LT6233 OPA2356xxD OPA2356xxDGK +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* + TO*99* + OnSemi*Micro8* + TSSOP*3x3mm*P0.65mm* + TSSOP*4.4x3mm*P0.65mm* + MSOP*3x3mm*P0.65mm* + SSOP*3.9x4.9mm*P0.635mm* + LFCSP*2x2mm*P0.5mm* + *SIP* + SOIC*5.3x6.2mm*P1.27mm* +$ENDFPLIST +DRAW +P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f +P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f +X ~ 1 300 0 100 L 50 50 1 1 O +X - 2 -300 -100 100 R 50 50 1 1 I +X + 3 -300 100 100 R 50 50 1 1 I +X + 5 -300 100 100 R 50 50 2 1 I +X - 6 -300 -100 100 R 50 50 2 1 I +X ~ 7 300 0 100 L 50 50 2 1 O +X V- 4 -100 -300 150 U 50 50 3 1 W +X V+ 8 -100 300 150 D 50 50 3 1 W +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VSS +# +DEF power:VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VSS" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/R-2R DAC/R-2R DAC.bak b/analog circuits/R-2R DAC/R-2R DAC.bak new file mode 100644 index 0000000..df042fc --- /dev/null +++ b/analog circuits/R-2R DAC/R-2R DAC.bak @@ -0,0 +1,500 @@ +EESchema Schematic File Version 4 +LIBS:R-2R DAC-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R2 +U 1 1 5B0A220F +P 3800 4050 +F 0 "R2" H 3870 4096 50 0000 L CNN +F 1 "2k" H 3870 4005 50 0000 L CNN +F 2 "" V 3730 4050 50 0001 C CNN +F 3 "~" H 3800 4050 50 0001 C CNN + 1 3800 4050 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0A2246 +P 3500 4050 +F 0 "R1" H 3570 4096 50 0000 L CNN +F 1 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4850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3800 4850 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3800 4850 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0A2607 +P 4350 4900 +F 0 "V2" H 4578 4946 50 0000 L CNN +F 1 "VSOURCE" H 4578 4855 50 0000 L CNN +F 2 "" H 4350 4900 50 0001 C CNN +F 3 "" H 4350 4900 50 0001 C CNN +F 4 "V" H 4350 4900 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 4350 4900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4350 4900 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4350 4900 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0A2655 +P 4950 4900 +F 0 "V3" H 5178 4946 50 0000 L CNN +F 1 "VSOURCE" H 5178 4855 50 0000 L CNN +F 2 "" H 4950 4900 50 0001 C CNN +F 3 "" H 4950 4900 50 0001 C CNN +F 4 "V" H 4950 4900 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 4950 4900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4950 4900 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4950 4900 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V4 +U 1 1 5B0A26A3 +P 5550 4900 +F 0 "V4" H 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CNN "Spice_Netlist_Enabled" + 1 8300 3100 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V6 +U 1 1 5B0C8F5F +P 8300 4100 +F 0 "V6" H 8528 4146 50 0000 L CNN +F 1 "VSOURCE" H 8528 4055 50 0000 L CNN +F 2 "" H 8300 4100 50 0001 C CNN +F 3 "" H 8300 4100 50 0001 C CNN +F 4 "V" H 8300 4100 50 0001 C CNN "Spice_Primitive" +F 5 "dc 10" H 8300 4100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8300 4100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8300 4100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR06 +U 1 1 5B0C9017 +P 8300 2600 +F 0 "#PWR06" H 8300 2450 50 0001 C CNN +F 1 "VDD" H 8317 2773 50 0000 C CNN +F 2 "" H 8300 2600 50 0001 C CNN +F 3 "" H 8300 2600 50 0001 C CNN + 1 8300 2600 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR07 +U 1 1 5B0C90B6 +P 8450 4800 +F 0 "#PWR07" H 8450 4650 50 0001 C CNN +F 1 "VSS" H 8467 4973 50 0000 C CNN +F 2 "" H 8450 4800 50 0001 C CNN +F 3 "" H 8450 4800 50 0001 C CNN + 1 8450 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8450 4800 8300 4800 +Wire Wire Line + 8300 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Line + 5800 3400 6200 3400 +Connection ~ 5800 3600 +Connection ~ 6200 3400 +$Comp +L power:GND #PWR0101 +U 1 1 5B0D2212 +P 6200 3800 +F 0 "#PWR0101" H 6200 3550 50 0001 C CNN +F 1 "GND" H 6205 3627 50 0000 C CNN +F 2 "" H 6200 3800 50 0001 C CNN +F 3 "" H 6200 3800 50 0001 C CNN + 1 6200 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 3800 6200 3600 +Wire Wire Line + 6200 3600 6450 3600 +Text Notes 7050 5450 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/R-2R DAC/R-2R DAC.cir b/analog circuits/R-2R DAC/R-2R DAC.cir new file mode 100644 index 0000000..bb15d6b --- /dev/null +++ b/analog circuits/R-2R DAC/R-2R DAC.cir @@ -0,0 +1,20 @@ +.title KiCad schematic +R2 Net-_R1-Pad1_ Net-_R2-Pad2_ 2k +R1 Net-_R1-Pad1_ GND 2k +R4 Net-_R3-Pad1_ Net-_R4-Pad2_ 2k +R6 Net-_R5-Pad1_ Net-_R6-Pad2_ 2k +R8 Net-_R10-Pad2_ Net-_R8-Pad2_ 2k +R9 Net-_R10-Pad2_ GND 2k +R3 Net-_R3-Pad1_ Net-_R1-Pad1_ 1k +R5 Net-_R5-Pad1_ Net-_R3-Pad1_ 1k +R7 Net-_R10-Pad2_ Net-_R5-Pad1_ 1k +V1 Net-_R2-Pad2_ GND dc 0 +V2 Net-_R4-Pad2_ GND dc 0 +V3 Net-_R6-Pad2_ GND dc 0 +V4 Net-_R8-Pad2_ GND dc 5 +U1 out Net-_R10-Pad2_ GND AD8620 +V5 VDD GND dc 10 +V6 GND VSS dc 10 +R10 out Net-_R10-Pad2_ 2k +.tran .25m 30m +.end diff --git a/analog circuits/R-2R DAC/R-2R DAC.kicad_pcb b/analog circuits/R-2R DAC/R-2R DAC.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/R-2R DAC/R-2R DAC.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/R-2R DAC/R-2R DAC.pro b/analog circuits/R-2R DAC/R-2R DAC.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/R-2R DAC/R-2R DAC.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/R-2R DAC/R-2R DAC.sch b/analog circuits/R-2R DAC/R-2R DAC.sch new file mode 100644 index 0000000..c3a9d36 --- /dev/null +++ b/analog circuits/R-2R DAC/R-2R DAC.sch @@ -0,0 +1,428 @@ +EESchema Schematic File Version 4 +LIBS:R-2R DAC-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R2 +U 1 1 5B0A220F +P 3800 4050 +F 0 "R2" H 3870 4096 50 0000 L CNN +F 1 "2k" H 3870 4005 50 0000 L CNN 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-1 +$EndComp +$Comp +L Device:R R9 +U 1 1 5B0A236E +P 5800 4050 +F 0 "R9" H 5870 4096 50 0000 L CNN +F 1 "2k" H 5870 4005 50 0000 L CNN +F 2 "" V 5730 4050 50 0001 C CNN +F 3 "~" H 5800 4050 50 0001 C CNN + 1 5800 4050 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0A23C4 +P 4100 3600 +F 0 "R3" V 3893 3600 50 0000 C CNN +F 1 "1k" V 3984 3600 50 0000 C CNN +F 2 "" V 4030 3600 50 0001 C CNN +F 3 "~" H 4100 3600 50 0001 C CNN + 1 4100 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:R R5 +U 1 1 5B0A24D0 +P 4650 3600 +F 0 "R5" V 4443 3600 50 0000 C CNN +F 1 "1k" V 4534 3600 50 0000 C CNN +F 2 "" V 4580 3600 50 0001 C CNN +F 3 "~" H 4650 3600 50 0001 C CNN + 1 4650 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:R R7 +U 1 1 5B0A2532 +P 5250 3600 +F 0 "R7" V 5043 3600 50 0000 C CNN +F 1 "1k" V 5134 3600 50 0000 C CNN +F 2 "" V 5180 3600 50 0001 C CNN +F 3 "~" H 5250 3600 50 0001 C CNN + 1 5250 3600 + 0 1 1 0 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0A25BF +P 3800 4850 +F 0 "V1" H 4028 4896 50 0000 L CNN +F 1 "VSOURCE" H 4028 4805 50 0000 L CNN +F 2 "" H 3800 4850 50 0001 C CNN +F 3 "" H 3800 4850 50 0001 C CNN +F 4 "V" H 3800 4850 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0" H 3800 4850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3800 4850 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3800 4850 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0A2607 +P 4350 4900 +F 0 "V2" H 4578 4946 50 0000 L CNN +F 1 "VSOURCE" H 4578 4855 50 0000 L CNN +F 2 "" H 4350 4900 50 0001 C CNN +F 3 "" H 4350 4900 50 0001 C CNN +F 4 "V" H 4350 4900 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0" H 4350 4900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4350 4900 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4350 4900 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0A2655 +P 4950 4900 +F 0 "V3" H 5178 4946 50 0000 L CNN +F 1 "VSOURCE" H 5178 4855 50 0000 L CNN +F 2 "" H 4950 4900 50 0001 C CNN +F 3 "" H 4950 4900 50 0001 C CNN +F 4 "V" H 4950 4900 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0" H 4950 4900 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Line + 4350 3600 4350 3900 +Wire Wire Line + 4350 3600 4500 3600 +Connection ~ 4350 3600 +Wire Wire Line + 4800 3600 4950 3600 +Wire Wire Line + 4950 3900 4950 3600 +Connection ~ 4950 3600 +Wire Wire Line + 4950 3600 5100 3600 +Wire Wire Line + 4350 4600 4350 4200 +Wire Wire Line + 4950 4600 4950 4200 +Wire Wire Line + 5550 4600 5550 4200 +Wire Wire Line + 5550 3900 5550 3600 +Wire Wire Line + 5550 3600 5400 3600 +$Comp +L Amplifier_Operational:AD8620 U1 +U 1 1 5B0A3185 +P 6750 3500 +F 0 "U1" H 6750 3022 50 0000 C CNN +F 1 "AD8620" H 6750 3113 50 0000 C CNN +F 2 "" H 6750 3500 50 0001 C CNN +F 3 "http://www.analog.com/media/en/technical-documentation/data-sheets/AD8610_8620.pdf" H 6750 3500 50 0001 C CNN + 1 6750 3500 + 1 0 0 1 +$EndComp +$Comp +L power:GND #PWR02 +U 1 1 5B0A33C5 +P 4700 5650 +F 0 "#PWR02" H 4700 5400 50 0001 C CNN +F 1 "GND" H 4705 5477 50 0000 C CNN +F 2 "" H 4700 5650 50 0001 C CNN +F 3 "" H 4700 5650 50 0001 C CNN + 1 4700 5650 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B0A3401 +P 3100 4300 +F 0 "#PWR01" H 3100 4050 50 0001 C CNN +F 1 "GND" H 3105 4127 50 0000 C CNN +F 2 "" H 3100 4300 50 0001 C CNN +F 3 "" H 3100 4300 50 0001 C CNN + 1 3100 4300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B0A3436 +P 5800 4300 +F 0 "#PWR03" H 5800 4050 50 0001 C CNN +F 1 "GND" H 5805 4127 50 0000 C CNN +F 2 "" H 5800 4300 50 0001 C CNN +F 3 "" H 5800 4300 50 0001 C CNN + 1 5800 4300 + 1 0 0 -1 +$EndComp +Connection ~ 5550 3600 +Wire Wire Line + 3800 3600 3500 3600 +Wire Wire Line + 3500 3600 3500 3900 +Connection ~ 3800 3600 +Wire Wire Line + 3500 4200 3100 4200 +Wire Wire Line + 3100 4200 3100 4300 +Wire Wire Line + 5800 4300 5800 4200 +Wire Wire Line + 5800 3900 5800 3600 +Wire Wire Line + 5800 3600 5550 3600 +Wire Wire Line + 6450 3400 6200 3400 +Wire Wire Line + 6200 3400 6200 2900 +Wire Wire Line + 7250 2900 7250 3200 +Wire Wire Line + 7250 3500 7050 3500 +Wire Wire Line + 4700 5650 4700 5400 +Connection ~ 4700 5400 +Wire Wire Line + 4700 5400 4950 5400 +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 5B0A5E2D +P 6150 4300 +F 0 "#FLG0101" H 6150 4375 50 0001 C CNN +F 1 "PWR_FLAG" H 6150 4474 50 0000 C CNN +F 2 "" H 6150 4300 50 0001 C CNN +F 3 "~" H 6150 4300 50 0001 C CNN + 1 6150 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 4300 5800 4300 +Connection ~ 5800 4300 +$Comp +L pspice:VSOURCE V5 +U 1 1 5B0C8ED6 +P 8300 3100 +F 0 "V5" H 8528 3146 50 0000 L CNN +F 1 "VSOURCE" H 8528 3055 50 0000 L CNN +F 2 "" H 8300 3100 50 0001 C CNN +F 3 "" H 8300 3100 50 0001 C CNN +F 4 "V" H 8300 3100 50 0001 C CNN "Spice_Primitive" +F 5 "dc 10" H 8300 3100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8300 3100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8300 3100 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V6 +U 1 1 5B0C8F5F +P 8300 4100 +F 0 "V6" H 8528 4146 50 0000 L CNN +F 1 "VSOURCE" H 8528 4055 50 0000 L CNN +F 2 "" H 8300 4100 50 0001 C CNN +F 3 "" H 8300 4100 50 0001 C CNN +F 4 "V" H 8300 4100 50 0001 C CNN "Spice_Primitive" +F 5 "dc 10" H 8300 4100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8300 4100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8300 4100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR06 +U 1 1 5B0C9017 +P 8300 2600 +F 0 "#PWR06" H 8300 2450 50 0001 C CNN +F 1 "VDD" H 8317 2773 50 0000 C CNN +F 2 "" H 8300 2600 50 0001 C CNN +F 3 "" H 8300 2600 50 0001 C CNN + 1 8300 2600 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR07 +U 1 1 5B0C90B6 +P 8450 4800 +F 0 "#PWR07" H 8450 4650 50 0001 C CNN +F 1 "VSS" H 8467 4973 50 0000 C CNN +F 2 "" H 8450 4800 50 0001 C CNN +F 3 "" H 8450 4800 50 0001 C CNN + 1 8450 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8450 4800 8300 4800 +Wire Wire Line + 8300 4800 8300 4400 +Wire Wire Line + 8300 3800 8300 3650 +Wire Wire Line + 8300 2800 8300 2600 +$Comp +L power:GND #PWR08 +U 1 1 5B0CADF6 +P 8800 3750 +F 0 "#PWR08" H 8800 3500 50 0001 C CNN +F 1 "GND" H 8805 3577 50 0000 C CNN +F 2 "" H 8800 3750 50 0001 C CNN +F 3 "" H 8800 3750 50 0001 C CNN + 1 8800 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 3750 8800 3650 +Wire Wire Line + 8800 3650 8300 3650 +Connection ~ 8300 3650 +Wire Wire Line + 8300 3650 8300 3400 +Text GLabel 7750 3350 0 50 Input ~ 0 +out +Wire Wire Line + 7750 3350 7750 3200 +Wire Wire Line + 7750 3200 7250 3200 +Connection ~ 7250 3200 +Wire Wire Line + 7250 3200 7250 3500 +$Comp +L Device:R R10 +U 1 1 5B0CDF7D +P 6650 2900 +F 0 "R10" V 6443 2900 50 0000 C CNN +F 1 "2k" V 6534 2900 50 0000 C CNN +F 2 "" V 6580 2900 50 0001 C CNN +F 3 "~" H 6650 2900 50 0001 C CNN + 1 6650 2900 + 0 1 1 0 +$EndComp +Wire Wire Line + 6800 2900 7250 2900 +Wire Wire Line + 6500 2900 6200 2900 +Wire Wire Line + 5800 3600 5800 3400 +Wire Wire Line + 5800 3400 6200 3400 +Connection ~ 5800 3600 +Connection ~ 6200 3400 +$Comp +L power:GND #PWR0101 +U 1 1 5B0D2212 +P 6200 3800 +F 0 "#PWR0101" H 6200 3550 50 0001 C CNN +F 1 "GND" H 6205 3627 50 0000 C CNN +F 2 "" H 6200 3800 50 0001 C CNN +F 3 "" H 6200 3800 50 0001 C CNN + 1 6200 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 3800 6200 3600 +Wire Wire Line + 6200 3600 6450 3600 +Text Notes 7050 5450 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/R-2R DAC/sym-lib-table b/analog circuits/R-2R DAC/sym-lib-table new file mode 100644 index 0000000..9e1a465 --- /dev/null +++ b/analog circuits/R-2R DAC/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sallen_key_schlib)(type Legacy)(uri "/home/akshay/kicad_examples/R-2R DAC/sallen_key_schlib.lib")(options "")(descr "")) +) diff --git a/analog circuits/RC/RC-cache.lib b/analog circuits/RC/RC-cache.lib new file mode 100644 index 0000000..6884347 --- /dev/null +++ b/analog circuits/RC/RC-cache.lib @@ -0,0 +1,69 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/RC/RC.bak b/analog circuits/RC/RC.bak new file mode 100644 index 0000000..8b6bea6 --- /dev/null +++ b/analog circuits/RC/RC.bak @@ -0,0 +1,83 @@ +EESchema Schematic File Version 4
+LIBS:RC-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B07B93A
+P 3600 3850
+F 0 "V1" H 3828 3896 50 0000 L CNN
+F 1 "VSOURCE" H 3828 3805 50 0000 L CNN
+F 2 "" H 3600 3850 50 0001 C CNN
+F 3 "" H 3600 3850 50 0001 C CNN
+F 4 "V" H 3600 3850 50 0001 C CNN "Spice_Primitive"
+F 5 "Y" H 3600 3850 50 0001 C CNN "Spice_Netlist_Enabled"
+F 6 "pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3600 3850 50 0001 C CNN "Spice_Model"
+ 1 3600 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B07B9AD
+P 4750 3100
+F 0 "R1" V 4543 3100 50 0000 C CNN
+F 1 "1k" V 4634 3100 50 0000 C CNN
+F 2 "" V 4680 3100 50 0001 C CNN
+F 3 "~" H 4750 3100 50 0001 C CNN
+ 1 4750 3100
+ 0 1 1 0
+$EndComp
+$Comp
+L Device:C C1
+U 1 1 5B07BB2F
+P 5650 3800
+F 0 "C1" H 5765 3846 50 0000 L CNN
+F 1 "10u" H 5765 3755 50 0000 L CNN
+F 2 "" H 5688 3650 50 0001 C CNN
+F 3 "~" H 5650 3800 50 0001 C CNN
+ 1 5650 3800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3600 4150 3600 4350
+Wire Wire Line
+ 3600 4350 4550 4350
+Wire Wire Line
+ 5650 4350 5650 3950
+$Comp
+L power:GND #PWR01
+U 1 1 5B07BC3B
+P 4550 4600
+F 0 "#PWR01" H 4550 4350 50 0001 C CNN
+F 1 "GND" H 4555 4427 50 0000 C CNN
+F 2 "" H 4550 4600 50 0001 C CNN
+F 3 "" H 4550 4600 50 0001 C CNN
+ 1 4550 4600
+ 1 0 0 -1
+$EndComp
+Connection ~ 4550 4350
+Wire Wire Line
+ 4550 4350 5650 4350
+Wire Wire Line
+ 4550 4350 4550 4600
+Wire Wire Line
+ 4900 3100 5650 3100
+Wire Wire Line
+ 5650 3100 5650 3650
+Wire Wire Line
+ 3600 3550 3600 3100
+Wire Wire Line
+ 3600 3100 4600 3100
+$EndSCHEMATC
diff --git a/analog circuits/RC/RC.cir b/analog circuits/RC/RC.cir new file mode 100644 index 0000000..5a513c7 --- /dev/null +++ b/analog circuits/RC/RC.cir @@ -0,0 +1,6 @@ +.title KiCad schematic +V1 ip GND pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0) +R1 out ip 1k +C1 out GND 10u +.tran 5m 100m +.end diff --git a/analog circuits/RC/RC.kicad_pcb b/analog circuits/RC/RC.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/RC/RC.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/RC/RC.pro b/analog circuits/RC/RC.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/RC/RC.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/RC/RC.sch b/analog circuits/RC/RC.sch new file mode 100644 index 0000000..ab0da2e --- /dev/null +++ b/analog circuits/RC/RC.sch @@ -0,0 +1,103 @@ +EESchema Schematic File Version 4 +LIBS:RC-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B07B93A +P 3600 3850 +F 0 "V1" H 3828 3896 50 0000 L CNN +F 1 "VSOURCE" H 3828 3805 50 0000 L CNN +F 2 "" H 3600 3850 50 0001 C CNN +F 3 "" H 3600 3850 50 0001 C CNN +F 4 "V" H 3600 3850 50 0001 C CNN "Spice_Primitive" +F 5 "Y" H 3600 3850 50 0001 C CNN "Spice_Netlist_Enabled" +F 6 "pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3600 3850 50 0001 C CNN "Spice_Model" + 1 3600 3850 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B07B9AD +P 4750 3100 +F 0 "R1" V 4543 3100 50 0000 C CNN +F 1 "1k" V 4634 3100 50 0000 C CNN +F 2 "" V 4680 3100 50 0001 C CNN +F 3 "~" H 4750 3100 50 0001 C CNN + 1 4750 3100 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B07BB2F +P 5650 3800 +F 0 "C1" H 5765 3846 50 0000 L CNN +F 1 "10u" H 5765 3755 50 0000 L CNN +F 2 "" H 5688 3650 50 0001 C CNN +F 3 "~" H 5650 3800 50 0001 C CNN + 1 5650 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4150 3600 4350 +Wire Wire Line + 3600 4350 4550 4350 +Wire Wire Line + 5650 4350 5650 3950 +$Comp +L power:GND #PWR01 +U 1 1 5B07BC3B +P 4550 4600 +F 0 "#PWR01" H 4550 4350 50 0001 C CNN +F 1 "GND" H 4555 4427 50 0000 C CNN +F 2 "" H 4550 4600 50 0001 C CNN +F 3 "" H 4550 4600 50 0001 C CNN + 1 4550 4600 + 1 0 0 -1 +$EndComp +Connection ~ 4550 4350 +Wire Wire Line + 4550 4350 5650 4350 +Wire Wire Line + 4550 4350 4550 4600 +Wire Wire Line + 4900 3100 5550 3100 +Wire Wire Line + 5650 3100 5650 3650 +Wire Wire Line + 3600 3550 3600 3100 +Wire Wire Line + 3600 3100 3700 3100 +Text GLabel 3450 2750 0 50 Input ~ 0 +ip +Wire Wire Line + 3450 2750 3700 2750 +Wire Wire Line + 3700 2750 3700 3100 +Connection ~ 3700 3100 +Wire Wire Line + 3700 3100 4600 3100 +Text GLabel 5350 2800 0 50 Output ~ 0 +out +Wire Wire Line + 5350 2800 5550 2800 +Wire Wire Line + 5550 2800 5550 3100 +Connection ~ 5550 3100 +Wire Wire Line + 5550 3100 5650 3100 +Text Notes 7400 5800 0 50 ~ 0 +.tran 5m 100m +$EndSCHEMATC diff --git a/analog circuits/README.md b/analog circuits/README.md new file mode 100644 index 0000000..ffa4773 --- /dev/null +++ b/analog circuits/README.md @@ -0,0 +1,2 @@ +# kicad-simulation-examples +Example projects for spice simulation(analog circuits) in KiCad diff --git a/analog circuits/RL/RL-cache.lib b/analog circuits/RL/RL-cache.lib new file mode 100644 index 0000000..73507d9 --- /dev/null +++ b/analog circuits/RL/RL-cache.lib @@ -0,0 +1,74 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:L +# +DEF Device:L L 0 40 N N 1 F N +F0 "L" -50 0 50 V V C CNN +F1 "Device:L" 75 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Choke_* + *Coil* + Inductor_* + L_* +$ENDFPLIST +DRAW +A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 +A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 +A 0 25 25 -899 899 0 1 0 N 0 0 0 50 +A 0 75 25 -899 899 0 1 0 N 0 50 0 100 +X 1 1 0 150 50 D 50 50 1 1 P +X 2 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/RL/RL.bak b/analog circuits/RL/RL.bak new file mode 100644 index 0000000..c5f3ec9 --- /dev/null +++ b/analog circuits/RL/RL.bak @@ -0,0 +1,83 @@ +EESchema Schematic File Version 4
+LIBS:RL-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B08233B
+P 3550 3700
+F 0 "V1" H 3778 3746 50 0000 L CNN
+F 1 "VSOURCE" H 3778 3655 50 0000 L CNN
+F 2 "" H 3550 3700 50 0001 C CNN
+F 3 "" H 3550 3700 50 0001 C CNN
+F 4 "V" H 3550 3700 50 0001 C CNN "Spice_Primitive"
+F 5 "pwl(0 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3550 3700 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 3550 3700 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 3550 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B082392
+P 5150 2800
+F 0 "R1" V 4943 2800 50 0000 C CNN
+F 1 "10" V 5034 2800 50 0000 C CNN
+F 2 "" V 5080 2800 50 0001 C CNN
+F 3 "~" H 5150 2800 50 0001 C CNN
+ 1 5150 2800
+ 0 1 1 0
+$EndComp
+$Comp
+L Device:L L1
+U 1 1 5B0824D0
+P 6500 3700
+F 0 "L1" H 6553 3746 50 0000 L CNN
+F 1 "100m" H 6553 3655 50 0000 L CNN
+F 2 "" H 6500 3700 50 0001 C CNN
+F 3 "~" H 6500 3700 50 0001 C CNN
+ 1 6500 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #PWR01
+U 1 1 5B08256D
+P 5100 5050
+F 0 "#PWR01" H 5100 4800 50 0001 C CNN
+F 1 "GND" H 5105 4877 50 0000 C CNN
+F 2 "" H 5100 5050 50 0001 C CNN
+F 3 "" H 5100 5050 50 0001 C CNN
+ 1 5100 5050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3550 3400 3550 2800
+Wire Wire Line
+ 3550 2800 5000 2800
+Wire Wire Line
+ 5300 2800 6500 2800
+Wire Wire Line
+ 6500 2800 6500 3550
+Wire Wire Line
+ 3550 4000 3550 4700
+Wire Wire Line
+ 6500 3850 6500 4700
+Wire Wire Line
+ 3550 4700 5100 4700
+Connection ~ 5100 4700
+Wire Wire Line
+ 5100 4700 6500 4700
+Wire Wire Line
+ 5100 4700 5100 5050
+$EndSCHEMATC
diff --git a/analog circuits/RL/RL.cir b/analog circuits/RL/RL.cir new file mode 100644 index 0000000..13c893d --- /dev/null +++ b/analog circuits/RL/RL.cir @@ -0,0 +1,6 @@ +.title KiCad schematic +V1 ip GND pwl(0 0 0.5m 5 50m 5 50.5m 0 100m 0) +R1 out ip 10 +L1 out GND 100m +.tran 5m 100m +.end diff --git a/analog circuits/RL/RL.kicad_pcb b/analog circuits/RL/RL.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/RL/RL.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/RL/RL.pro b/analog circuits/RL/RL.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/RL/RL.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/RL/RL.sch b/analog circuits/RL/RL.sch new file mode 100644 index 0000000..ca3751b --- /dev/null +++ b/analog circuits/RL/RL.sch @@ -0,0 +1,103 @@ +EESchema Schematic File Version 4 +LIBS:RL-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B08233B +P 3550 3700 +F 0 "V1" H 3778 3746 50 0000 L CNN +F 1 "VSOURCE" H 3778 3655 50 0000 L CNN +F 2 "" H 3550 3700 50 0001 C CNN +F 3 "" H 3550 3700 50 0001 C CNN +F 4 "V" H 3550 3700 50 0001 C CNN "Spice_Primitive" +F 5 "pwl(0 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3550 3700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3550 3700 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3550 3700 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B082392 +P 5150 2800 +F 0 "R1" V 4943 2800 50 0000 C CNN +F 1 "10" V 5034 2800 50 0000 C CNN +F 2 "" V 5080 2800 50 0001 C CNN +F 3 "~" H 5150 2800 50 0001 C CNN + 1 5150 2800 + 0 1 1 0 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0824D0 +P 6500 3700 +F 0 "L1" H 6553 3746 50 0000 L CNN +F 1 "100m" H 6553 3655 50 0000 L CNN +F 2 "" H 6500 3700 50 0001 C CNN +F 3 "~" H 6500 3700 50 0001 C CNN + 1 6500 3700 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B08256D +P 5100 5050 +F 0 "#PWR01" H 5100 4800 50 0001 C CNN +F 1 "GND" H 5105 4877 50 0000 C CNN +F 2 "" H 5100 5050 50 0001 C CNN +F 3 "" H 5100 5050 50 0001 C CNN + 1 5100 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3550 3400 3550 2800 +Wire Wire Line + 3550 2800 3750 2800 +Wire Wire Line + 5300 2800 6250 2800 +Wire Wire Line + 6500 2800 6500 3550 +Wire Wire Line + 3550 4000 3550 4700 +Wire Wire Line + 6500 3850 6500 4700 +Wire Wire Line + 3550 4700 5100 4700 +Connection ~ 5100 4700 +Wire Wire Line + 5100 4700 6500 4700 +Wire Wire Line + 5100 4700 5100 5050 +Text GLabel 3400 2250 0 50 Input ~ 0 +ip +Wire Wire Line + 3400 2250 3750 2250 +Wire Wire Line + 3750 2250 3750 2800 +Connection ~ 3750 2800 +Wire Wire Line + 3750 2800 5000 2800 +Text GLabel 5750 2100 0 50 Output ~ 0 +out +Wire Wire Line + 5750 2100 6250 2100 +Wire Wire Line + 6250 2100 6250 2800 +Connection ~ 6250 2800 +Wire Wire Line + 6250 2800 6500 2800 +Text Notes 8250 4750 0 50 ~ 0 +.tran 5m 100m +$EndSCHEMATC diff --git a/analog circuits/RLC-Series/RLC-Series-cache.lib b/analog circuits/RLC-Series/RLC-Series-cache.lib new file mode 100644 index 0000000..603b5a7 --- /dev/null +++ b/analog circuits/RLC-Series/RLC-Series-cache.lib @@ -0,0 +1,105 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:L +# +DEF Device:L L 0 40 N N 1 F N +F0 "L" -50 0 50 V V C CNN +F1 "Device:L" 75 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Choke_* + *Coil* + Inductor_* + L_* +$ENDFPLIST +DRAW +A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 +A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 +A 0 25 25 -899 899 0 1 0 N 0 0 0 50 +A 0 75 25 -899 899 0 1 0 N 0 50 0 100 +X 1 1 0 150 50 D 50 50 1 1 P +X 2 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/RLC-Series/RLC-Series.bak b/analog circuits/RLC-Series/RLC-Series.bak new file mode 100644 index 0000000..874a6c7 --- /dev/null +++ b/analog circuits/RLC-Series/RLC-Series.bak @@ -0,0 +1,111 @@ +EESchema Schematic File Version 4
+EELAYER 26 0
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diff --git a/analog circuits/RLC-Series/RLC-Series.cir b/analog circuits/RLC-Series/RLC-Series.cir new file mode 100644 index 0000000..81947fa --- /dev/null +++ b/analog circuits/RLC-Series/RLC-Series.cir @@ -0,0 +1,7 @@ +.title KiCad schematic +V1 Net-_R1-Pad2_ GND ac 10 0 +R1 Net-_L1-Pad1_ Net-_R1-Pad2_ 1k +L1 Net-_L1-Pad1_ Net-_C1-Pad1_ 100m +C1 Net-_C1-Pad1_ GND 0.01u +.ac dec 10 1 1meg +.end diff --git a/analog circuits/RLC-Series/RLC-Series.kicad_pcb b/analog circuits/RLC-Series/RLC-Series.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/RLC-Series/RLC-Series.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/RLC-Series/RLC-Series.pro b/analog circuits/RLC-Series/RLC-Series.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/RLC-Series/RLC-Series.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/RLC-Series/RLC-Series.sch b/analog circuits/RLC-Series/RLC-Series.sch new file mode 100644 index 0000000..41790a8 --- /dev/null +++ b/analog circuits/RLC-Series/RLC-Series.sch @@ -0,0 +1,114 @@ +EESchema Schematic File Version 4 +LIBS:RLC-Series-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0E7BD2 +P 4050 3400 +F 0 "V1" H 4278 3446 50 0000 L CNN +F 1 "VSOURCE" H 4278 3355 50 0000 L CNN +F 2 "" H 4050 3400 50 0001 C CNN +F 3 "" H 4050 3400 50 0001 C CNN +F 4 "V" H 4050 3400 50 0001 C CNN "Spice_Primitive" +F 5 "ac 10 0" H 4050 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4050 3400 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4050 3400 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0E7C21 +P 5150 2800 +F 0 "R1" V 4943 2800 50 0000 C CNN +F 1 "1k" V 5034 2800 50 0000 C CNN +F 2 "" V 5080 2800 50 0001 C CNN +F 3 "~" H 5150 2800 50 0001 C CNN + 1 5150 2800 + 0 1 1 0 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0E7CAD +P 6050 2800 +F 0 "L1" V 6240 2800 50 0000 C CNN +F 1 "100m" V 6149 2800 50 0000 C CNN +F 2 "" H 6050 2800 50 0001 C CNN +F 3 "~" H 6050 2800 50 0001 C CNN + 1 6050 2800 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0E7D3E +P 7400 2800 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+F3 "" 0 0 50 H I C CNN +$FPLIST + Choke_* + *Coil* + Inductor_* + L_* +$ENDFPLIST +DRAW +A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 +A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 +A 0 25 25 -899 899 0 1 0 N 0 0 0 50 +A 0 75 25 -899 899 0 1 0 N 0 50 0 100 +X 1 1 0 150 50 D 50 50 1 1 P +X 2 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/RLC-parallel/RLC-parallel.bak b/analog circuits/RLC-parallel/RLC-parallel.bak new file mode 100644 index 0000000..30d8b63 --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.bak @@ -0,0 +1,120 @@ +EESchema Schematic File Version 4
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+EELAYER END
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diff --git a/analog circuits/RLC-parallel/RLC-parallel.cir b/analog circuits/RLC-parallel/RLC-parallel.cir new file mode 100644 index 0000000..ff1b87d --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.cir @@ -0,0 +1,7 @@ +.title KiCad schematic +V1 ip GND ac 5 0 +R1 ip Net-_L1-Pad1_ 1k +L1 Net-_L1-Pad1_ GND 100m +C1 ip GND 0.1u +.ac dec 10 1 1meg +.end diff --git a/analog circuits/RLC-parallel/RLC-parallel.kicad_pcb b/analog circuits/RLC-parallel/RLC-parallel.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/RLC-parallel/RLC-parallel.pro b/analog circuits/RLC-parallel/RLC-parallel.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/RLC-parallel/RLC-parallel.sch b/analog circuits/RLC-parallel/RLC-parallel.sch new file mode 100644 index 0000000..e12bb77 --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.sch @@ -0,0 +1,136 @@ +EESchema Schematic File Version 4 +LIBS:RLC-parallel-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B090E79 +P 4200 3550 +F 0 "V1" H 4428 3596 50 0000 L CNN +F 1 "VSOURCE" H 4428 3505 50 0000 L CNN +F 2 "" H 4200 3550 50 0001 C CNN +F 3 "" H 4200 3550 50 0001 C CNN +F 4 "V" H 4200 3550 50 0001 C CNN "Spice_Primitive" +F 5 "ac 5 0" H 4200 3550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4200 3550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4200 3550 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B090F12 +P 6300 3000 +F 0 "R1" H 6370 3046 50 0000 L CNN +F 1 "1k" H 6370 2955 50 0000 L CNN +F 2 "" V 6230 3000 50 0001 C CNN +F 3 "~" H 6300 3000 50 0001 C CNN + 1 6300 3000 + 1 0 0 -1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B090F9F +P 6300 3850 +F 0 "L1" H 6353 3896 50 0000 L CNN +F 1 "100m" H 6353 3805 50 0000 L CNN +F 2 "" H 6300 3850 50 0001 C CNN +F 3 "~" H 6300 3850 50 0001 C CNN + 1 6300 3850 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B091068 +P 7100 3350 +F 0 "C1" H 7215 3396 50 0000 L CNN +F 1 "0.1u" H 7215 3305 50 0000 L CNN +F 2 "" H 7138 3200 50 0001 C CNN +F 3 "~" H 7100 3350 50 0001 C CNN + 1 7100 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 3250 4200 2600 +Wire Wire Line + 4200 2600 6300 2600 +Wire Wire Line + 6300 2600 6300 2850 +Wire Wire Line + 6300 3150 6300 3700 +Wire Wire Line + 7100 3200 7100 2600 +Wire Wire Line + 7100 2600 6300 2600 +Connection ~ 6300 2600 +Wire Wire Line + 4200 3850 4200 4200 +Wire Wire Line + 4200 4200 5650 4200 +Wire Wire Line + 6300 4200 6300 4000 +Wire Wire Line + 7100 3500 7100 4200 +Wire Wire Line + 7100 4200 6300 4200 +Connection ~ 6300 4200 +$Comp +L power:GND #PWR0101 +U 1 1 5B09125A +P 5650 4450 +F 0 "#PWR0101" H 5650 4200 50 0001 C CNN +F 1 "GND" H 5655 4277 50 0000 C CNN +F 2 "" H 5650 4450 50 0001 C CNN +F 3 "" H 5650 4450 50 0001 C CNN + 1 5650 4450 + 1 0 0 -1 +$EndComp +Connection ~ 5650 4200 +Wire Wire Line + 5650 4200 6300 4200 +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 5B09135C +P 5100 4400 +F 0 "#FLG0101" H 5100 4475 50 0001 C CNN +F 1 "PWR_FLAG" H 5100 4574 50 0000 C CNN +F 2 "" H 5100 4400 50 0001 C CNN +F 3 "~" H 5100 4400 50 0001 C CNN + 1 5100 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4400 5650 4400 +Wire Wire Line + 5650 4200 5650 4400 +Connection ~ 5650 4400 +Wire Wire Line + 5650 4400 5650 4450 +Text GLabel 4100 2300 0 50 Input ~ 0 +ip +Wire Wire Line + 4100 2300 4200 2300 +Wire Wire Line + 4200 2300 4200 2600 +Connection ~ 4200 2600 +Text GLabel 6750 2150 0 50 Output ~ 0 +out +Wire Wire Line + 6750 2150 7100 2150 +Wire Wire Line + 7100 2150 7100 2600 +Connection ~ 7100 2600 +Text Notes 8700 5000 0 50 ~ 0 +.ac dec 10 1 1meg +$EndSCHEMATC diff --git a/analog circuits/ac to dc converter/ZenerD1N750.lib b/analog circuits/ac to dc converter/ZenerD1N750.lib new file mode 100755 index 0000000..890c37f --- /dev/null +++ b/analog circuits/ac to dc converter/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/analog circuits/ac to dc converter/ac to dc converter-cache.lib b/analog circuits/ac to dc converter/ac to dc converter-cache.lib new file mode 100644 index 0000000..44a8ec5 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:D_Zener +# +DEF Device:D_Zener D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device:D_Zener" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 0 50 0 -50 0 N +P 3 0 1 8 -50 -50 -50 50 -30 50 N +P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# rectifier_schlib:D +# +DEF rectifier_schlib:D D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "rectifier_schlib:D" 0 -100 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + Diode_* + D-Pak_TO252AA + *SingleDiode + *_Diode_* + *SingleDiode* +$ENDFPLIST +DRAW +P 2 0 1 6 -50 50 -50 -50 N +P 3 0 1 0 50 50 -50 0 50 -50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/ac to dc converter/ac to dc converter.bak b/analog circuits/ac to dc converter/ac to dc converter.bak new file mode 100644 index 0000000..99fa2e0 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.bak @@ -0,0 +1,267 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0CF0CE +P 2750 4550 +F 0 "V1" H 2978 4596 50 0000 L CNN +F 1 "VSOURCE" H 2978 4505 50 0000 L CNN +F 2 "" H 2750 4550 50 0001 C CNN +F 3 "" H 2750 4550 50 0001 C CNN +F 4 "V" H 2750 4550 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 200)" H 2750 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2750 4550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2750 4550 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0CF1A2 +P 3950 3600 +F 0 "R1" V 3743 3600 50 0000 C CNN +F 1 "470k" V 3834 3600 50 0000 C CNN +F 2 "" V 3880 3600 50 0001 C CNN +F 3 "~" H 3950 3600 50 0001 C CNN + 1 3950 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0CF208 +P 3950 3950 +F 0 "C1" V 3698 3950 50 0000 C CNN +F 1 "22u" V 3789 3950 50 0000 C CNN +F 2 "" H 3988 3800 50 0001 C CNN +F 3 "~" H 3950 3950 50 0001 C CNN + 1 3950 3950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0CF246 +P 4350 5250 +F 0 "R2" V 4143 5250 50 0000 C CNN +F 1 "100" V 4234 5250 50 0000 C CNN +F 2 "" V 4280 5250 50 0001 C CNN +F 3 "~" H 4350 5250 50 0001 C CNN + 1 4350 5250 + 0 1 1 0 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0CF2C8 +P 5500 4300 +F 0 "D1" H 5500 4516 50 0000 C CNN +F 1 "D_ALT" H 5500 4425 50 0000 C CNN +F 2 "" H 5500 4300 50 0001 C CNN +F 3 "~" H 5500 4300 50 0001 C CNN + 1 5500 4300 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D3 +U 1 1 5B0CF325 +P 6300 4300 +F 0 "D3" H 6300 4516 50 0000 C CNN +F 1 "D_ALT" H 6300 4425 50 0000 C CNN +F 2 "" H 6300 4300 50 0001 C CNN +F 3 "~" H 6300 4300 50 0001 C CNN + 1 6300 4300 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D4 +U 1 1 5B0CF37B +P 6300 4700 +F 0 "D4" H 6300 4916 50 0000 C CNN +F 1 "D_ALT" H 6300 4825 50 0000 C CNN +F 2 "" H 6300 4700 50 0001 C CNN +F 3 "~" H 6300 4700 50 0001 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D2 +U 1 1 5B0CF3C2 +P 5500 4700 +F 0 "D2" H 5500 4916 50 0000 C CNN +F 1 "D_ALT" H 5500 4825 50 0000 C CNN +F 2 "" H 5500 4700 50 0001 C CNN +F 3 "~" H 5500 4700 50 0001 C CNN + 1 5500 4700 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0CF442 +P 7150 4650 +F 0 "C2" H 7035 4604 50 0000 R CNN +F 1 "470u" H 7035 4695 50 0000 R CNN +F 2 "" H 7188 4500 50 0001 C CNN +F 3 "~" H 7150 4650 50 0001 C CNN + 1 7150 4650 + -1 0 0 1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0CF524 +P 8050 4400 +F 0 "R3" V 7843 4400 50 0000 C CNN +F 1 "100" V 7934 4400 50 0000 C CNN +F 2 "" V 7980 4400 50 0001 C CNN +F 3 "~" H 8050 4400 50 0001 C CNN + 1 8050 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 6150 4300 5900 4300 +Wire Wire Line + 5350 4300 5300 4300 +Wire Wire Line + 5300 4300 5300 4500 +Wire Wire Line + 5300 4700 5350 4700 +Wire Wire Line + 5650 4700 5900 4700 +Wire Wire Line + 6450 4700 6450 4550 +Wire Wire Line + 6450 4550 6750 4550 +Wire Wire Line + 6750 4550 6750 4400 +Wire Wire Line + 6750 4400 7150 4400 +Connection ~ 6450 4550 +Wire Wire Line + 6450 4550 6450 4300 +Wire Wire Line + 8200 4400 8400 4400 +Wire Wire Line + 8400 4400 8400 5000 +Wire Wire Line + 8400 5300 7450 5300 +Wire Wire Line + 4950 5300 4950 4500 +Wire Wire Line + 4950 4500 5300 4500 +Connection ~ 5300 4500 +Wire Wire Line + 5300 4500 5300 4700 +Wire Wire Line + 7150 4500 7150 4400 +Connection ~ 7150 4400 +Wire Wire Line + 7150 4400 7900 4400 +Wire Wire Line + 7150 4800 7150 5300 +Connection ~ 7150 5300 +Wire Wire Line + 7150 5300 4950 5300 +Wire Wire Line + 2750 4250 2750 3600 +Wire Wire Line + 2750 3600 3500 3600 +Wire Wire Line + 4100 3600 4250 3600 +Wire Wire Line + 5900 3600 5900 4300 +Connection ~ 5900 4300 +Wire Wire Line + 5900 4300 5650 4300 +Wire Wire Line + 3500 3600 3500 3950 +Wire Wire Line + 3500 3950 3800 3950 +Connection ~ 3500 3600 +Wire Wire Line + 3500 3600 3800 3600 +Wire Wire Line + 4100 3950 4250 3950 +Wire Wire Line + 4250 3950 4250 3600 +Connection ~ 4250 3600 +Wire Wire Line + 4250 3600 5900 3600 +Wire Wire Line + 2750 4850 2750 5250 +Wire Wire Line + 2750 5250 4200 5250 +Wire Wire Line + 4500 5250 4500 5650 +Wire Wire Line + 4500 5650 5900 5650 +Wire Wire Line + 5900 5650 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5900 4700 6150 4700 +Text GLabel 9050 4300 0 50 Output ~ 0 +out +Wire Wire Line + 9050 4300 9800 4300 +Wire Wire Line + 9800 4300 9800 4150 +Wire Wire Line + 9800 4150 8400 4150 +Wire Wire Line + 8400 4150 8400 4400 +Connection ~ 8400 4400 +Text GLabel 2500 3350 0 50 Input ~ 0 +ip +Wire Wire Line + 2500 3350 2750 3350 +Wire Wire Line + 2750 3350 2750 3600 +Connection ~ 2750 3600 +$Comp +L power:GND #PWR0101 +U 1 1 5B0D3840 +P 7450 5550 +F 0 "#PWR0101" H 7450 5300 50 0001 C CNN +F 1 "GND" H 7455 5377 50 0000 C CNN +F 2 "" H 7450 5550 50 0001 C CNN +F 3 "" H 7450 5550 50 0001 C CNN + 1 7450 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 5550 7450 5300 +Connection ~ 7450 5300 +Wire Wire Line + 7450 5300 7150 5300 +$Comp +L Device:D_Zener D5 +U 1 1 5B0D4B1F +P 8400 5150 +F 0 "D5" V 8354 5229 50 0000 L CNN +F 1 "D_Zener" V 8445 5229 50 0000 L CNN +F 2 "" H 8400 5150 50 0001 C CNN +F 3 "~" H 8400 5150 50 0001 C CNN + 1 8400 5150 + 0 1 1 0 +$EndComp +Text GLabel 7050 4050 0 50 Output ~ 0 +vd +Wire Wire Line + 7050 4050 7550 4050 +Wire Wire Line + 7550 4050 7550 3850 +Wire Wire Line + 7550 3850 6750 3850 +Wire Wire Line + 6750 3850 6750 4400 +Connection ~ 6750 4400 +$EndSCHEMATC diff --git a/analog circuits/ac to dc converter/ac to dc converter.cir b/analog circuits/ac to dc converter/ac to dc converter.cir new file mode 100644 index 0000000..0c7dca8 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.cir @@ -0,0 +1,15 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" +V1 ip Net-_R2-Pad2_ sin(0 250) +R1 Net-_C1-Pad1_ ip 470k +C1 Net-_C1-Pad1_ ip 22u +R2 Net-_D2-Pad2_ Net-_R2-Pad2_ 100 +C2 GND vd 470u +R3 out vd 100 +D5 out GND D1N750 +D1 Net-_C1-Pad1_ GND D +D3 vd Net-_C1-Pad1_ D +D4 vd Net-_D2-Pad2_ D +D2 Net-_D2-Pad2_ GND D +.tran .25m 30m +.end diff --git a/analog circuits/ac to dc converter/ac to dc converter.kicad_pcb b/analog circuits/ac to dc converter/ac to dc converter.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/ac to dc converter/ac to dc converter.pro b/analog circuits/ac to dc converter/ac to dc converter.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/ac to dc converter/ac to dc converter.sch b/analog circuits/ac to dc converter/ac to dc converter.sch new file mode 100644 index 0000000..85840c3 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.sch @@ -0,0 +1,290 @@ +EESchema Schematic File Version 4 +LIBS:ac to dc converter-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0CF0CE +P 2750 4550 +F 0 "V1" H 2978 4596 50 0000 L CNN +F 1 "VSOURCE" H 2978 4505 50 0000 L CNN +F 2 "" H 2750 4550 50 0001 C CNN +F 3 "" H 2750 4550 50 0001 C CNN +F 4 "V" H 2750 4550 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 250)" H 2750 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2750 4550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2750 4550 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0CF1A2 +P 3950 3600 +F 0 "R1" V 3743 3600 50 0000 C CNN +F 1 "470k" V 3834 3600 50 0000 C CNN +F 2 "" V 3880 3600 50 0001 C CNN +F 3 "~" H 3950 3600 50 0001 C CNN + 1 3950 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0CF208 +P 3950 3950 +F 0 "C1" V 3698 3950 50 0000 C CNN +F 1 "22u" V 3789 3950 50 0000 C CNN +F 2 "" H 3988 3800 50 0001 C CNN +F 3 "~" H 3950 3950 50 0001 C CNN + 1 3950 3950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0CF246 +P 4350 5250 +F 0 "R2" V 4143 5250 50 0000 C CNN +F 1 "100" V 4234 5250 50 0000 C CNN +F 2 "" V 4280 5250 50 0001 C CNN +F 3 "~" H 4350 5250 50 0001 C CNN + 1 4350 5250 + 0 1 1 0 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0CF442 +P 7150 4650 +F 0 "C2" H 7035 4604 50 0000 R CNN +F 1 "470u" H 7035 4695 50 0000 R CNN +F 2 "" H 7188 4500 50 0001 C CNN +F 3 "~" H 7150 4650 50 0001 C CNN + 1 7150 4650 + -1 0 0 1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0CF524 +P 8050 4400 +F 0 "R3" V 7843 4400 50 0000 C CNN +F 1 "100" V 7934 4400 50 0000 C CNN +F 2 "" V 7980 4400 50 0001 C CNN +F 3 "~" H 8050 4400 50 0001 C CNN + 1 8050 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 6150 4300 5900 4300 +Wire Wire Line + 5350 4300 5300 4300 +Wire Wire Line + 5300 4300 5300 4500 +Wire Wire Line + 5300 4700 5350 4700 +Wire Wire Line + 5650 4700 5900 4700 +Wire Wire Line + 6450 4550 6750 4550 +Wire Wire Line + 6750 4550 6750 4400 +Wire Wire Line + 6750 4400 7150 4400 +Connection ~ 6450 4550 +Wire Wire Line + 6450 4550 6450 4300 +Wire Wire Line + 8200 4400 8400 4400 +Wire Wire Line + 8400 4400 8400 5000 +Wire Wire Line + 8400 5300 7450 5300 +Wire Wire Line + 4950 5300 4950 4500 +Wire Wire Line + 4950 4500 5300 4500 +Connection ~ 5300 4500 +Wire Wire Line + 5300 4500 5300 4700 +Wire Wire Line + 7150 4500 7150 4400 +Connection ~ 7150 4400 +Wire Wire Line + 7150 4400 7900 4400 +Wire Wire Line + 7150 4800 7150 5300 +Connection ~ 7150 5300 +Wire Wire Line + 7150 5300 4950 5300 +Wire Wire Line + 2750 4250 2750 3600 +Wire Wire Line + 2750 3600 3500 3600 +Wire Wire Line + 4100 3600 4250 3600 +Wire Wire Line + 5900 3600 5900 4300 +Connection ~ 5900 4300 +Wire Wire Line + 5900 4300 5650 4300 +Wire Wire Line + 3500 3600 3500 3950 +Wire Wire Line + 3500 3950 3800 3950 +Connection ~ 3500 3600 +Wire Wire Line + 3500 3600 3800 3600 +Wire Wire Line + 4100 3950 4250 3950 +Wire Wire Line + 4250 3950 4250 3600 +Connection ~ 4250 3600 +Wire Wire Line + 4250 3600 5900 3600 +Wire Wire Line + 2750 4850 2750 5250 +Wire Wire Line + 2750 5250 4200 5250 +Wire Wire Line + 4500 5250 4500 5650 +Wire Wire Line + 4500 5650 5900 5650 +Wire Wire Line + 5900 5650 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5900 4700 6150 4700 +Text GLabel 9050 4300 0 50 Output ~ 0 +out +Wire Wire Line + 9050 4300 9800 4300 +Wire Wire Line + 9800 4300 9800 4150 +Wire Wire Line + 9800 4150 8400 4150 +Wire Wire Line + 8400 4150 8400 4400 +Connection ~ 8400 4400 +Text GLabel 2500 3350 0 50 Input ~ 0 +ip +Wire Wire Line + 2500 3350 2750 3350 +Wire Wire Line + 2750 3350 2750 3600 +Connection ~ 2750 3600 +$Comp +L power:GND #PWR0101 +U 1 1 5B0D3840 +P 7450 5550 +F 0 "#PWR0101" H 7450 5300 50 0001 C CNN +F 1 "GND" H 7455 5377 50 0000 C CNN +F 2 "" H 7450 5550 50 0001 C CNN +F 3 "" H 7450 5550 50 0001 C CNN + 1 7450 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 5550 7450 5300 +Connection ~ 7450 5300 +Wire Wire Line + 7450 5300 7150 5300 +$Comp +L Device:D_Zener D5 +U 1 1 5B0D4B1F +P 8400 5150 +F 0 "D5" V 8354 5229 50 0000 L CNN +F 1 "D_Zener" V 8445 5229 50 0000 L CNN +F 2 "" H 8400 5150 50 0001 C CNN +F 3 "~" H 8400 5150 50 0001 C CNN +F 4 "D" H 8400 5150 50 0001 C CNN "Spice_Primitive" +F 5 "D1N750" H 8400 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8400 5150 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" H 8400 5150 50 0001 C CNN "Spice_Lib_File" + 1 8400 5150 + 0 1 1 0 +$EndComp +Text GLabel 7050 4050 0 50 Output ~ 0 +vd +Wire Wire Line + 7050 4050 7550 4050 +Wire Wire Line + 7550 4050 7550 3850 +Wire Wire Line + 7550 3850 6750 3850 +Wire Wire Line + 6750 3850 6750 4400 +Connection ~ 6750 4400 +Wire Wire Line + 6450 4550 6450 4700 +$Comp +L rectifier_schlib:D D1 +U 1 1 5B30D294 +P 5500 4300 +F 0 "D1" H 5500 4515 50 0000 C CNN +F 1 "D" H 5500 4424 50 0000 C CNN +F 2 "" H 5500 4300 50 0000 C CNN +F 3 "" H 5500 4300 50 0000 C CNN +F 4 "D" H 5500 4300 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 5500 4300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 4300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5500 4300 50 0001 C CNN "Spice_Node_Sequence" + 1 5500 4300 + 1 0 0 -1 +$EndComp +$Comp +L rectifier_schlib:D D3 +U 1 1 5B30D899 +P 6300 4300 +F 0 "D3" H 6300 4515 50 0000 C CNN +F 1 "D" H 6300 4424 50 0000 C CNN +F 2 "" H 6300 4300 50 0000 C CNN +F 3 "" H 6300 4300 50 0000 C CNN +F 4 "D" H 6300 4300 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 6300 4300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6300 4300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 6300 4300 50 0001 C CNN "Spice_Node_Sequence" + 1 6300 4300 + 1 0 0 -1 +$EndComp +$Comp +L rectifier_schlib:D D4 +U 1 1 5B30D908 +P 6300 4700 +F 0 "D4" H 6300 4915 50 0000 C CNN +F 1 "D" H 6300 4824 50 0000 C CNN +F 2 "" H 6300 4700 50 0000 C CNN +F 3 "" H 6300 4700 50 0000 C CNN +F 4 "D" H 6300 4700 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 6300 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6300 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 6300 4700 50 0001 C CNN "Spice_Node_Sequence" + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L rectifier_schlib:D D2 +U 1 1 5B30D95C +P 5500 4700 +F 0 "D2" H 5500 4915 50 0000 C CNN +F 1 "D" H 5500 4824 50 0000 C CNN +F 2 "" H 5500 4700 50 0000 C CNN +F 3 "" H 5500 4700 50 0000 C CNN +F 4 "D" H 5500 4700 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 5500 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5500 4700 50 0001 C CNN "Spice_Node_Sequence" + 1 5500 4700 + 1 0 0 -1 +$EndComp +Text Notes 8450 5800 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/ac to dc converter/sym-lib-table b/analog circuits/ac to dc converter/sym-lib-table new file mode 100644 index 0000000..efed22d --- /dev/null +++ b/analog circuits/ac to dc converter/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name rectifier_schlib)(type Legacy)(uri /home/akshay/kicad-source-mirror-master/demos/simulation/rectifier/rectifier_schlib.lib)(options "")(descr "")) +) diff --git a/analog circuits/class B push pull amplifier/NPN.lib b/analog circuits/class B push pull amplifier/NPN.lib new file mode 100644 index 0000000..6509fe7 --- /dev/null +++ b/analog circuits/class B push pull amplifier/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/analog circuits/class B push pull amplifier/class B push pull amplifier-cache.lib b/analog circuits/class B push pull amplifier/class B push pull amplifier-cache.lib new file mode 100644 index 0000000..96616f0 --- /dev/null +++ b/analog circuits/class B push pull amplifier/class B push pull amplifier-cache.lib @@ -0,0 +1,138 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:D_ALT +# +DEF Device:D_ALT D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device:D_ALT" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 50 -50 -50 N +P 2 0 1 0 50 0 -50 0 N +P 4 0 1 8 50 50 50 -50 -50 0 50 50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Transistor_BJT:BC548 +# +DEF Transistor_BJT:BC548 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "Transistor_BJT:BC548" 200 0 50 H V L CNN +F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC546 BC548 BC549 BC550 BC337 BC338 +$FPLIST + TO?92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 25 0 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 200 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Transistor_BJT:BC556 +# +DEF Transistor_BJT:BC556 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "Transistor_BJT:BC556" 200 0 50 H V L CNN +F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC556 BC558 BC559 BC560 BC327 BC328 +$FPLIST + TO?92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/class B push pull amplifier/class B push pull amplifier.bak b/analog circuits/class B push pull amplifier/class B push pull amplifier.bak new file mode 100644 index 0000000..d4d08a4 --- /dev/null +++ b/analog circuits/class B push pull amplifier/class B push pull amplifier.bak @@ -0,0 +1,372 @@ +EESchema Schematic File Version 4 +LIBS:class B push pull amplifier-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0D1F5B +P 2650 4750 +F 0 "V1" H 2878 4796 50 0000 L CNN +F 1 "VSOURCE" H 2878 4705 50 0000 L CNN +F 2 "" H 2650 4750 50 0001 C CNN +F 3 "" H 2650 4750 50 0001 C CNN +F 4 "V" H 2650 4750 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 20 1000)" H 2650 4750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2650 4750 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2650 4750 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0D1FC5 +P 3900 3700 +F 0 "C2" V 3648 3700 50 0000 C CNN +F 1 "100u" V 3739 3700 50 0000 C CNN +F 2 "" H 3938 3550 50 0001 C CNN +F 3 "~" H 3900 3700 50 0001 C CNN + 1 3900 3700 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0D2000 +P 3850 5150 +F 0 "C1" V 3598 5150 50 0000 C CNN +F 1 "100u" V 3689 5150 50 0000 C CNN +F 2 "" H 3888 5000 50 0001 C CNN +F 3 "~" H 3850 5150 50 0001 C CNN + 1 3850 5150 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0D207E +P 4950 2600 +F 0 "R1" H 5020 2646 50 0000 L CNN +F 1 "68" H 5020 2555 50 0000 L CNN +F 2 "" V 4880 2600 50 0001 C CNN +F 3 "~" H 4950 2600 50 0001 C CNN + 1 4950 2600 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0D20F1 +P 5000 3750 +F 0 "D1" V 5046 3671 50 0000 R CNN +F 1 "D_ALT" V 4955 3671 50 0000 R CNN +F 2 "" H 5000 3750 50 0001 C CNN +F 3 "~" H 5000 3750 50 0001 C CNN + 1 5000 3750 + 0 -1 -1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0D216D +P 5000 4850 +F 0 "R2" H 5070 4896 50 0000 L CNN +F 1 "1" H 5070 4805 50 0000 L CNN +F 2 "" V 4930 4850 50 0001 C CNN +F 3 "~" H 5000 4850 50 0001 C CNN + 1 5000 4850 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0D21B3 +P 5000 5950 +F 0 "R3" H 5070 5996 50 0000 L CNN +F 1 "68" H 5070 5905 50 0000 L CNN +F 2 "" V 4930 5950 50 0001 C CNN +F 3 "~" H 5000 5950 50 0001 C CNN + 1 5000 5950 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R5 +U 1 1 5B0D2210 +P 6300 2550 +F 0 "R5" H 6370 2596 50 0000 L CNN +F 1 "1" H 6370 2505 50 0000 L CNN +F 2 "" V 6230 2550 50 0001 C CNN +F 3 "~" H 6300 2550 50 0001 C CNN + 1 6300 2550 + 1 0 0 -1 +$EndComp +$Comp +L Transistor_BJT:BC556 Q1 +U 1 1 5B0D23D7 +P 5950 5200 +F 0 "Q1" H 6140 5154 50 0000 L CNN +F 1 "BC556" H 6140 5245 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6150 5125 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC557.pdf" H 5950 5200 50 0001 L CNN + 1 5950 5200 + 1 0 0 1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0D2500 +P 7900 5900 +F 0 "V3" V 7397 5900 50 0000 C CNN +F 1 "VSOURCE" V 7488 5900 50 0000 C CNN +F 2 "" H 7900 5900 50 0001 C CNN +F 3 "" H 7900 5900 50 0001 C CNN +F 4 "V" H 7900 5900 50 0001 C CNN "Spice_Primitive" +F 5 "dc 12" H 7900 5900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7900 5900 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7900 5900 + 0 1 1 0 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0D25B9 +P 7850 2600 +F 0 "V2" V 7347 2600 50 0000 C CNN +F 1 "VSOURCE" V 7438 2600 50 0000 C CNN +F 2 "" H 7850 2600 50 0001 C CNN +F 3 "" H 7850 2600 50 0001 C CNN +F 4 "V" H 7850 2600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 12" H 7850 2600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7850 2600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7850 2600 + 0 -1 1 0 +$EndComp +Wire Wire Line + 2650 4450 2650 3700 +Wire Wire Line + 2650 3700 3050 3700 +Wire Wire Line + 4050 3700 4050 3350 +Wire Wire Line + 4050 3350 6000 3350 +Wire Wire Line + 2650 5050 2650 5150 +Wire Wire Line + 4000 5150 4000 5500 +Wire Wire Line + 6300 2400 4950 2400 +Wire Wire Line + 4950 2400 4950 2450 +Wire Wire Line + 4950 2750 4950 3600 +Wire Wire Line + 4950 3600 5000 3600 +Wire Wire Line + 5000 3900 5000 4700 +Wire Wire Line + 5000 5000 5000 5800 +Wire Wire Line + 5000 6100 5000 6400 +Wire Wire Line + 6050 3550 6300 3550 +Wire Wire Line + 6300 3150 6300 2700 +Wire Wire Line + 7600 6400 7600 5900 +Wire Wire Line + 6300 2400 6650 2400 +Wire Wire Line + 7550 2400 7550 2600 +Connection ~ 6300 2400 +$Comp +L power:GND #PWR01 +U 1 1 5B0D39AA +P 2600 6100 +F 0 "#PWR01" H 2600 5850 50 0001 C CNN +F 1 "GND" H 2605 5927 50 0000 C CNN +F 2 "" H 2600 6100 50 0001 C CNN +F 3 "" H 2600 6100 50 0001 C CNN + 1 2600 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 6100 2600 5150 +Wire Wire Line + 2600 5150 2650 5150 +$Comp +L power:GND #PWR04 +U 1 1 5B0D3D93 +P 8850 2850 +F 0 "#PWR04" H 8850 2600 50 0001 C CNN +F 1 "GND" H 8855 2677 50 0000 C CNN +F 2 "" H 8850 2850 50 0001 C CNN +F 3 "" H 8850 2850 50 0001 C CNN + 1 8850 2850 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B0D3DC8 +P 8700 6000 +F 0 "#PWR03" H 8700 5750 50 0001 C CNN +F 1 "GND" H 8705 5827 50 0000 C CNN +F 2 "" H 8700 6000 50 0001 C CNN +F 3 "" H 8700 6000 50 0001 C CNN + 1 8700 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 5900 8700 5900 +Wire Wire Line + 8700 5900 8700 6000 +Wire Wire Line + 8150 2600 8850 2600 +Wire Wire Line + 8850 2600 8850 2850 +Wire Wire Line + 3700 5150 3500 5150 +Wire Wire Line + 3500 5150 3500 3700 +Connection ~ 3500 3700 +Wire Wire Line + 3500 3700 3750 3700 +Text GLabel 2700 3400 0 50 Input ~ 0 +ip +Wire Wire Line + 2700 3400 3050 3400 +Wire Wire Line + 3050 3400 3050 3700 +Connection ~ 3050 3700 +Wire Wire Line + 3050 3700 3500 3700 +$Comp +L Transistor_BJT:BC548 Q2 +U 1 1 5B0FA052 +P 6200 3350 +F 0 "Q2" H 6391 3396 50 0000 L CNN +F 1 "BC548" H 6391 3305 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6400 3275 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6200 3350 50 0001 L CNN + 1 6200 3350 + 1 0 0 -1 +$EndComp +$Comp +L Transistor_BJT:BC548 Q3 +U 1 1 5B0FDC04 +P 6550 4050 +F 0 "Q3" H 6741 4096 50 0000 L CNN +F 1 "BC548" H 6741 4005 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6750 3975 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6550 4050 50 0001 L CNN + 1 6550 4050 + 1 0 0 -1 +$EndComp +$Comp +L Transistor_BJT:BC548 Q4 +U 1 1 5B0FDC52 +P 6650 5500 +F 0 "Q4" H 6841 5546 50 0000 L CNN +F 1 "BC548" H 6841 5455 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6850 5425 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6650 5500 50 0001 L CNN + 1 6650 5500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 3850 6650 2400 +Connection ~ 6650 2400 +Wire Wire Line + 6650 2400 7550 2400 +Wire Wire Line + 6050 3550 6050 4050 +Wire Wire Line + 6050 4050 6350 4050 +Wire Wire Line + 6650 4250 6650 4600 +Wire Wire Line + 6650 5000 6650 5300 +Wire Wire Line + 6650 5300 6750 5300 +Connection ~ 6650 5000 +Wire Wire Line + 6050 5000 6650 5000 +Wire Wire Line + 5750 5200 4450 5200 +Wire Wire Line + 4450 5200 4450 5500 +Wire Wire Line + 4450 5500 4000 5500 +Wire Wire Line + 6050 5400 6050 5500 +Wire Wire Line + 6050 5500 6450 5500 +Wire Wire Line + 5000 6400 6050 6400 +Wire Wire Line + 6750 5700 6750 6400 +Connection ~ 6750 6400 +Wire Wire Line + 6750 6400 7600 6400 +Wire Wire Line + 6050 5500 6050 6400 +Connection ~ 6050 5500 +Connection ~ 6050 6400 +Wire Wire Line + 6050 6400 6750 6400 +$Comp +L Device:C C3 +U 1 1 5B103F89 +P 7050 4600 +F 0 "C3" V 6798 4600 50 0000 C CNN +F 1 "100u" V 6889 4600 50 0000 C CNN +F 2 "" H 7088 4450 50 0001 C CNN +F 3 "~" H 7050 4600 50 0001 C CNN + 1 7050 4600 + 0 1 1 0 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B1048CE +P 7650 4750 +F 0 "R4" H 7720 4796 50 0000 L CNN +F 1 "4" H 7720 4705 50 0000 L CNN +F 2 "" V 7580 4750 50 0001 C CNN +F 3 "~" H 7650 4750 50 0001 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 5B10497D +P 7650 4900 +F 0 "#PWR0101" H 7650 4650 50 0001 C CNN +F 1 "GND" H 7655 4727 50 0000 C CNN +F 2 "" H 7650 4900 50 0001 C CNN +F 3 "" H 7650 4900 50 0001 C CNN + 1 7650 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7200 4600 7650 4600 +Wire Wire Line + 6900 4600 6850 4600 +Connection ~ 6650 4600 +Wire Wire Line + 6650 4600 6650 5000 +Text GLabel 7800 4250 0 50 Output ~ 0 +out +Wire Wire Line + 7800 4250 7850 4250 +Wire Wire Line + 7850 4250 7850 4100 +Wire Wire Line + 7850 4100 6850 4100 +Wire Wire Line + 6850 4100 6850 4600 +Connection ~ 6850 4600 +Wire Wire Line + 6850 4600 6650 4600 +$EndSCHEMATC diff --git a/analog circuits/class B push pull amplifier/class B push pull amplifier.cir b/analog circuits/class B push pull amplifier/class B push pull amplifier.cir new file mode 100644 index 0000000..a762456 --- /dev/null +++ b/analog circuits/class B push pull amplifier/class B push pull amplifier.cir @@ -0,0 +1,21 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/PNP.lib" +.include "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" +V1 ip GND sin(0 20 1000) +C2 Net-_C2-Pad1_ ip 100u +C1 Net-_C1-Pad1_ ip 100u +R1 Net-_Q3-Pad1_ Net-_D1-Pad2_ 68 +D1 Net-_D1-Pad2_ Net-_D1-Pad1_ D_ALT +R2 Net-_D1-Pad1_ Net-_R2-Pad2_ 1 +R3 Net-_R2-Pad2_ Net-_Q1-Pad1_ 68 +R5 Net-_Q3-Pad1_ Net-_Q2-Pad1_ 1 +V3 GND Net-_Q1-Pad1_ dc 12 +V2 Net-_Q3-Pad1_ GND dc 12 +Q2 Net-_Q2-Pad1_ Net-_C2-Pad1_ Net-_Q2-Pad3_ Q2N2222 +C3 Net-_C3-Pad1_ out 100u +R4 Net-_C3-Pad1_ GND 4 +Q1 Net-_Q1-Pad1_ Net-_C1-Pad1_ out Q2N2907A +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad3_ out Q2N2222 +Q4 out Net-_Q1-Pad1_ Net-_Q1-Pad1_ Q2N2222 +.tran .25m 30m +.end diff --git a/analog circuits/class B push pull amplifier/class B push pull amplifier.kicad_pcb b/analog circuits/class B push pull amplifier/class B push pull amplifier.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/class B push pull amplifier/class B push pull amplifier.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/class B push pull amplifier/class B push pull amplifier.pro b/analog circuits/class B push pull amplifier/class B push pull amplifier.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/class B push pull amplifier/class B push pull amplifier.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/class B push pull amplifier/class B push pull amplifier.sch b/analog circuits/class B push pull amplifier/class B push pull amplifier.sch new file mode 100644 index 0000000..a42e87a --- /dev/null +++ b/analog circuits/class B push pull amplifier/class B push pull amplifier.sch @@ -0,0 +1,394 @@ +EESchema Schematic File Version 4 +LIBS:class B push pull amplifier-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0D1F5B +P 2650 4750 +F 0 "V1" H 2878 4796 50 0000 L CNN +F 1 "VSOURCE" H 2878 4705 50 0000 L CNN +F 2 "" H 2650 4750 50 0001 C CNN +F 3 "" H 2650 4750 50 0001 C CNN +F 4 "V" H 2650 4750 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 20 1000)" H 2650 4750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2650 4750 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2650 4750 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0D1FC5 +P 3900 3700 +F 0 "C2" V 3648 3700 50 0000 C CNN +F 1 "100u" V 3739 3700 50 0000 C CNN +F 2 "" H 3938 3550 50 0001 C CNN +F 3 "~" H 3900 3700 50 0001 C CNN + 1 3900 3700 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0D2000 +P 3850 5150 +F 0 "C1" V 3598 5150 50 0000 C CNN +F 1 "100u" V 3689 5150 50 0000 C CNN +F 2 "" H 3888 5000 50 0001 C CNN +F 3 "~" H 3850 5150 50 0001 C CNN + 1 3850 5150 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0D207E +P 4950 2600 +F 0 "R1" H 5020 2646 50 0000 L CNN +F 1 "68" H 5020 2555 50 0000 L CNN +F 2 "" V 4880 2600 50 0001 C CNN +F 3 "~" H 4950 2600 50 0001 C CNN + 1 4950 2600 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0D20F1 +P 5000 3750 +F 0 "D1" V 5046 3671 50 0000 R CNN +F 1 "D_ALT" V 4955 3671 50 0000 R CNN +F 2 "" H 5000 3750 50 0001 C CNN +F 3 "~" H 5000 3750 50 0001 C CNN +F 4 "D" H 5000 3750 50 0001 C CNN "Spice_Primitive" +F 5 "D_ALT" H 5000 3750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5000 3750 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5000 3750 50 0001 C CNN "Spice_Node_Sequence" + 1 5000 3750 + 0 -1 -1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0D216D +P 5000 4850 +F 0 "R2" H 5070 4896 50 0000 L CNN +F 1 "1" H 5070 4805 50 0000 L CNN +F 2 "" V 4930 4850 50 0001 C CNN +F 3 "~" H 5000 4850 50 0001 C CNN + 1 5000 4850 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0D21B3 +P 5000 5950 +F 0 "R3" H 5070 5996 50 0000 L CNN +F 1 "68" H 5070 5905 50 0000 L CNN +F 2 "" V 4930 5950 50 0001 C CNN +F 3 "~" H 5000 5950 50 0001 C CNN + 1 5000 5950 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R5 +U 1 1 5B0D2210 +P 6300 2550 +F 0 "R5" H 6370 2596 50 0000 L CNN +F 1 "1" H 6370 2505 50 0000 L CNN +F 2 "" V 6230 2550 50 0001 C CNN +F 3 "~" H 6300 2550 50 0001 C CNN + 1 6300 2550 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0D2500 +P 7900 5900 +F 0 "V3" V 7397 5900 50 0000 C CNN +F 1 "VSOURCE" V 7488 5900 50 0000 C CNN +F 2 "" H 7900 5900 50 0001 C CNN +F 3 "" H 7900 5900 50 0001 C CNN +F 4 "V" H 7900 5900 50 0001 C CNN "Spice_Primitive" +F 5 "dc 12" H 7900 5900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7900 5900 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7900 5900 + 0 1 1 0 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0D25B9 +P 7850 2600 +F 0 "V2" V 7347 2600 50 0000 C CNN +F 1 "VSOURCE" V 7438 2600 50 0000 C CNN +F 2 "" H 7850 2600 50 0001 C CNN +F 3 "" H 7850 2600 50 0001 C CNN +F 4 "V" H 7850 2600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 12" H 7850 2600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7850 2600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7850 2600 + 0 -1 1 0 +$EndComp +Wire Wire Line + 2650 4450 2650 3700 +Wire Wire Line + 2650 3700 3050 3700 +Wire Wire Line + 4050 3700 4050 3350 +Wire Wire Line + 4050 3350 6000 3350 +Wire Wire Line + 2650 5050 2650 5150 +Wire Wire Line + 4000 5150 4000 5500 +Wire Wire Line + 6300 2400 4950 2400 +Wire Wire Line + 4950 2400 4950 2450 +Wire Wire Line + 4950 2750 4950 3600 +Wire Wire Line + 4950 3600 5000 3600 +Wire Wire Line + 5000 3900 5000 4700 +Wire Wire Line + 5000 5000 5000 5800 +Wire Wire Line + 5000 6100 5000 6400 +Wire Wire Line + 6050 3550 6300 3550 +Wire Wire Line + 6300 3150 6300 2700 +Wire Wire Line + 7600 6400 7600 5900 +Wire Wire Line + 6300 2400 6650 2400 +Wire Wire Line + 7550 2400 7550 2600 +Connection ~ 6300 2400 +$Comp +L power:GND #PWR01 +U 1 1 5B0D39AA +P 2600 6100 +F 0 "#PWR01" H 2600 5850 50 0001 C CNN +F 1 "GND" H 2605 5927 50 0000 C CNN +F 2 "" H 2600 6100 50 0001 C CNN +F 3 "" H 2600 6100 50 0001 C CNN + 1 2600 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 6100 2600 5150 +Wire Wire Line + 2600 5150 2650 5150 +$Comp +L power:GND #PWR04 +U 1 1 5B0D3D93 +P 8850 2850 +F 0 "#PWR04" H 8850 2600 50 0001 C CNN +F 1 "GND" H 8855 2677 50 0000 C CNN +F 2 "" H 8850 2850 50 0001 C CNN +F 3 "" H 8850 2850 50 0001 C CNN + 1 8850 2850 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B0D3DC8 +P 8700 6000 +F 0 "#PWR03" H 8700 5750 50 0001 C CNN +F 1 "GND" H 8705 5827 50 0000 C CNN +F 2 "" H 8700 6000 50 0001 C CNN +F 3 "" H 8700 6000 50 0001 C CNN + 1 8700 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 5900 8700 5900 +Wire Wire Line + 8700 5900 8700 6000 +Wire Wire Line + 8150 2600 8850 2600 +Wire Wire Line + 8850 2600 8850 2850 +Wire Wire Line + 3700 5150 3500 5150 +Wire Wire Line + 3500 5150 3500 3700 +Connection ~ 3500 3700 +Wire Wire Line + 3500 3700 3750 3700 +Text GLabel 2700 3400 0 50 Input ~ 0 +ip +Wire Wire Line + 2700 3400 3050 3400 +Wire Wire Line + 3050 3400 3050 3700 +Connection ~ 3050 3700 +Wire Wire Line + 3050 3700 3500 3700 +$Comp +L Transistor_BJT:BC548 Q2 +U 1 1 5B0FA052 +P 6200 3350 +F 0 "Q2" H 6391 3396 50 0000 L CNN +F 1 "BC548" H 6391 3305 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6400 3275 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6200 3350 50 0001 L CNN +F 4 "Q" H 6200 3350 50 0001 C CNN "Spice_Primitive" +F 5 "Q2N2222" H 6200 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" H 6200 3350 50 0001 C CNN "Spice_Lib_File" + 1 6200 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 3850 6650 2400 +Connection ~ 6650 2400 +Wire Wire Line + 6650 2400 7550 2400 +Wire Wire Line + 6050 3550 6050 4050 +Wire Wire Line + 6050 4050 6350 4050 +Wire Wire Line + 6650 4250 6650 4600 +Wire Wire Line + 6650 5000 6650 5300 +Wire Wire Line + 6650 5300 6750 5300 +Connection ~ 6650 5000 +Wire Wire Line + 6050 5000 6650 5000 +Wire Wire Line + 5750 5200 4450 5200 +Wire Wire Line + 4450 5200 4450 5500 +Wire Wire Line + 4450 5500 4000 5500 +Wire Wire Line + 6050 5400 6050 5500 +Wire Wire Line + 6050 5500 6450 5500 +Wire Wire Line + 5000 6400 6050 6400 +Wire Wire Line + 6750 5700 6750 6400 +Connection ~ 6750 6400 +Wire Wire Line + 6750 6400 7600 6400 +Wire Wire Line + 6050 5500 6050 6400 +Connection ~ 6050 5500 +Connection ~ 6050 6400 +Wire Wire Line + 6050 6400 6750 6400 +$Comp +L Device:C C3 +U 1 1 5B103F89 +P 7050 4600 +F 0 "C3" V 6798 4600 50 0000 C CNN +F 1 "100u" V 6889 4600 50 0000 C CNN +F 2 "" H 7088 4450 50 0001 C CNN +F 3 "~" H 7050 4600 50 0001 C CNN + 1 7050 4600 + 0 1 1 0 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B1048CE +P 7650 4750 +F 0 "R4" H 7720 4796 50 0000 L CNN +F 1 "4" H 7720 4705 50 0000 L CNN +F 2 "" V 7580 4750 50 0001 C CNN +F 3 "~" H 7650 4750 50 0001 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 5B10497D +P 7650 4900 +F 0 "#PWR0101" H 7650 4650 50 0001 C CNN +F 1 "GND" H 7655 4727 50 0000 C CNN +F 2 "" H 7650 4900 50 0001 C CNN +F 3 "" H 7650 4900 50 0001 C CNN + 1 7650 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7200 4600 7650 4600 +Wire Wire Line + 6900 4600 6850 4600 +Connection ~ 6650 4600 +Wire Wire Line + 6650 4600 6650 5000 +Text GLabel 7800 4250 0 50 Output ~ 0 +out +Wire Wire Line + 7800 4250 7850 4250 +Wire Wire Line + 7850 4250 7850 4100 +Wire Wire Line + 7850 4100 6850 4100 +Wire Wire Line + 6850 4100 6850 4600 +Connection ~ 6850 4600 +Wire Wire Line + 6850 4600 6650 4600 +$Comp +L Transistor_BJT:BC556 Q1 +U 1 1 5B0D23D7 +P 5950 5200 +F 0 "Q1" H 6140 5154 50 0000 L CNN +F 1 "BC556" H 6140 5245 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6150 5125 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC557.pdf" H 5950 5200 50 0001 L CNN +F 4 "Q" H 5950 5200 50 0001 C CNN "Spice_Primitive" +F 5 "Q2N2907A" H 5950 5200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5950 5200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/PNP.lib" H 5950 5200 50 0001 C CNN "Spice_Lib_File" + 1 5950 5200 + 1 0 0 1 +$EndComp +$Comp +L Transistor_BJT:BC548 Q3 +U 1 1 5B30F9B3 +P 6550 4050 +F 0 "Q3" H 6741 4096 50 0000 L CNN +F 1 "BC548" H 6741 4005 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6750 3975 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6550 4050 50 0001 L CNN +F 4 "Q" H 6550 4050 50 0001 C CNN "Spice_Primitive" +F 5 "Q2N2222" H 6550 4050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6550 4050 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" H 6550 4050 50 0001 C CNN "Spice_Lib_File" + 1 6550 4050 + 1 0 0 -1 +$EndComp +$Comp +L Transistor_BJT:BC548 Q4 +U 1 1 5B30FA33 +P 6650 5500 +F 0 "Q4" H 6841 5546 50 0000 L CNN +F 1 "BC548" H 6841 5455 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6850 5425 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6650 5500 50 0001 L CNN +F 4 "Q" H 6650 5500 50 0001 C CNN "Spice_Primitive" +F 5 "Q2N2222" H 6650 5500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6650 5500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" H 6650 5500 50 0001 C CNN "Spice_Lib_File" + 1 6650 5500 + 1 0 0 -1 +$EndComp +Text Notes 9050 5200 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/clipper circuit/clipper circuit-cache.lib b/analog circuits/clipper circuit/clipper circuit-cache.lib new file mode 100644 index 0000000..eb61469 --- /dev/null +++ b/analog circuits/clipper circuit/clipper circuit-cache.lib @@ -0,0 +1,73 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:D_ALT +# +DEF Device:D_ALT D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device:D_ALT" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 50 -50 -50 N +P 2 0 1 0 50 0 -50 0 N +P 4 0 1 8 50 50 50 -50 -50 0 50 50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/clipper circuit/clipper circuit.bak b/analog circuits/clipper circuit/clipper circuit.bak new file mode 100644 index 0000000..30fb589 --- /dev/null +++ b/analog circuits/clipper circuit/clipper circuit.bak @@ -0,0 +1,104 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0DADA3 +P 3750 4350 +F 0 "V1" H 3978 4396 50 0000 L CNN +F 1 "VSOURCE" H 3978 4305 50 0000 L CNN +F 2 "" H 3750 4350 50 0001 C CNN +F 3 "" H 3750 4350 50 0001 C CNN +F 4 "V" H 3750 4350 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 5)" H 3750 4350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3750 4350 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3750 4350 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0DAE19 +P 5150 4000 +F 0 "D1" H 5150 4216 50 0000 C CNN +F 1 "D_ALT" H 5150 4125 50 0000 C CNN +F 2 "" H 5150 4000 50 0001 C CNN +F 3 "~" H 5150 4000 50 0001 C CNN + 1 5150 4000 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0DAE60 +P 5950 4300 +F 0 "R1" H 6020 4346 50 0000 L CNN +F 1 "1k" H 6020 4255 50 0000 L CNN +F 2 "" V 5880 4300 50 0001 C CNN +F 3 "~" H 5950 4300 50 0001 C CNN + 1 5950 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4050 3750 4000 +Wire Wire Line + 3750 4000 4150 4000 +Wire Wire Line + 5300 4000 5850 4000 +Wire Wire Line + 5950 4000 5950 4150 +Wire Wire Line + 5950 4450 5950 4800 +Wire Wire Line + 5950 4800 4850 4800 +Wire Wire Line + 3750 4800 3750 4650 +$Comp +L power:GND #PWR01 +U 1 1 5B0DAEDB +P 4850 5100 +F 0 "#PWR01" H 4850 4850 50 0001 C CNN +F 1 "GND" H 4855 4927 50 0000 C CNN +F 2 "" H 4850 5100 50 0001 C CNN +F 3 "" H 4850 5100 50 0001 C CNN + 1 4850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 5100 4850 4800 +Connection ~ 4850 4800 +Wire Wire Line + 4850 4800 3750 4800 +Text GLabel 3600 3800 0 50 Input ~ 0 +ip +Wire Wire Line + 3600 3800 4150 3800 +Wire Wire Line + 4150 3800 4150 4000 +Connection ~ 4150 4000 +Wire Wire Line + 4150 4000 5000 4000 +Text GLabel 6600 3850 0 50 Output ~ 0 +out +Wire Wire Line + 6600 3850 6850 3850 +Wire Wire Line + 6850 3850 6850 3650 +Wire Wire Line + 6850 3650 5850 3650 +Wire Wire Line + 5850 3650 5850 4000 +Connection ~ 5850 4000 +Wire Wire Line + 5850 4000 5950 4000 +$EndSCHEMATC diff --git a/analog circuits/clipper circuit/clipper circuit.cir b/analog circuits/clipper circuit/clipper circuit.cir new file mode 100644 index 0000000..68338d1 --- /dev/null +++ b/analog circuits/clipper circuit/clipper circuit.cir @@ -0,0 +1,6 @@ +.title KiCad schematic +V1 ip GND sin(0 5) +D1 out ip D_ALT +R1 out GND 1k +.tran .25m 30m +.end diff --git a/analog circuits/clipper circuit/clipper circuit.kicad_pcb b/analog circuits/clipper circuit/clipper circuit.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/clipper circuit/clipper circuit.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/clipper circuit/clipper circuit.pro b/analog circuits/clipper circuit/clipper circuit.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/clipper circuit/clipper circuit.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/clipper circuit/clipper circuit.sch b/analog circuits/clipper circuit/clipper circuit.sch new file mode 100644 index 0000000..c06a66e --- /dev/null +++ b/analog circuits/clipper circuit/clipper circuit.sch @@ -0,0 +1,111 @@ +EESchema Schematic File Version 4 +LIBS:clipper circuit-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0DADA3 +P 3750 4350 +F 0 "V1" H 3978 4396 50 0000 L CNN +F 1 "VSOURCE" H 3978 4305 50 0000 L CNN +F 2 "" H 3750 4350 50 0001 C CNN +F 3 "" H 3750 4350 50 0001 C CNN +F 4 "V" H 3750 4350 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 5)" H 3750 4350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3750 4350 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3750 4350 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0DAE19 +P 5150 4000 +F 0 "D1" H 5150 4216 50 0000 C CNN +F 1 "D_ALT" H 5150 4125 50 0000 C CNN +F 2 "" H 5150 4000 50 0001 C CNN +F 3 "~" H 5150 4000 50 0001 C CNN +F 4 "D" H 5150 4000 50 0001 C CNN "Spice_Primitive" +F 5 "D_ALT" H 5150 4000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5150 4000 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5150 4000 50 0001 C CNN "Spice_Node_Sequence" + 1 5150 4000 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0DAE60 +P 5950 4300 +F 0 "R1" H 6020 4346 50 0000 L CNN +F 1 "1k" H 6020 4255 50 0000 L CNN +F 2 "" V 5880 4300 50 0001 C CNN +F 3 "~" H 5950 4300 50 0001 C CNN + 1 5950 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4050 3750 4000 +Wire Wire Line + 3750 4000 4150 4000 +Wire Wire Line + 5300 4000 5850 4000 +Wire Wire Line + 5950 4000 5950 4150 +Wire Wire Line + 5950 4450 5950 4800 +Wire Wire Line + 5950 4800 4850 4800 +Wire Wire Line + 3750 4800 3750 4650 +$Comp +L power:GND #PWR01 +U 1 1 5B0DAEDB +P 4850 5100 +F 0 "#PWR01" H 4850 4850 50 0001 C CNN +F 1 "GND" H 4855 4927 50 0000 C CNN +F 2 "" H 4850 5100 50 0001 C CNN +F 3 "" H 4850 5100 50 0001 C CNN + 1 4850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 5100 4850 4800 +Connection ~ 4850 4800 +Wire Wire Line + 4850 4800 3750 4800 +Text GLabel 3600 3800 0 50 Input ~ 0 +ip +Wire Wire Line + 3600 3800 4150 3800 +Wire Wire Line + 4150 3800 4150 4000 +Connection ~ 4150 4000 +Wire Wire Line + 4150 4000 5000 4000 +Text GLabel 6600 3850 0 50 Output ~ 0 +out +Wire Wire Line + 6600 3850 6850 3850 +Wire Wire Line + 6850 3850 6850 3650 +Wire Wire Line + 6850 3650 5850 3650 +Wire Wire Line + 5850 3650 5850 4000 +Connection ~ 5850 4000 +Wire Wire Line + 5850 4000 5950 4000 +Text Notes 7700 5250 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/colpitt oscillator/NPN.lib b/analog circuits/colpitt oscillator/NPN.lib new file mode 100644 index 0000000..6509fe7 --- /dev/null +++ b/analog circuits/colpitt oscillator/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/analog circuits/colpitt oscillator/colpitt oscillator-cache.lib b/analog circuits/colpitt oscillator/colpitt oscillator-cache.lib new file mode 100644 index 0000000..4235a61 --- /dev/null +++ b/analog circuits/colpitt oscillator/colpitt oscillator-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:L +# +DEF Device:L L 0 40 N N 1 F N +F0 "L" -50 0 50 V V C CNN +F1 "Device:L" 75 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Choke_* + *Coil* + Inductor_* + L_* +$ENDFPLIST +DRAW +A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 +A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 +A 0 25 25 -899 899 0 1 0 N 0 0 0 50 +A 0 75 25 -899 899 0 1 0 N 0 50 0 100 +X 1 1 0 150 50 D 50 50 1 1 P +X 2 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Transistor_BJT:BC548 +# +DEF Transistor_BJT:BC548 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "Transistor_BJT:BC548" 200 0 50 H V L CNN +F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC546 BC548 BC549 BC550 BC337 BC338 +$FPLIST + TO?92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 25 0 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 200 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/colpitt oscillator/colpitt oscillator.bak b/analog circuits/colpitt oscillator/colpitt oscillator.bak new file mode 100644 index 0000000..9d3be17 --- /dev/null +++ b/analog circuits/colpitt oscillator/colpitt oscillator.bak @@ -0,0 +1,268 @@ +EESchema Schematic File Version 4 +LIBS:colpitt oscillator-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:C C1 +U 1 1 5B0DB14E +P 3000 3850 +F 0 "C1" V 2748 3850 50 0000 C CNN +F 1 "0.1u" V 2839 3850 50 0000 C CNN +F 2 "" H 3038 3700 50 0001 C CNN +F 3 "~" H 3000 3850 50 0001 C CNN + 1 3000 3850 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0DB24B +P 3650 2800 +F 0 "R2" H 3720 2846 50 0000 L CNN +F 1 "190k" H 3720 2755 50 0000 L CNN +F 2 "" V 3580 2800 50 0001 C CNN +F 3 "~" H 3650 2800 50 0001 C CNN + 1 3650 2800 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0DB27E +P 3600 4350 +F 0 "R1" H 3670 4396 50 0000 L CNN +F 1 "36k" H 3670 4305 50 0000 L CNN +F 2 "" V 3530 4350 50 0001 C CNN +F 3 "~" H 3600 4350 50 0001 C CNN + 1 3600 4350 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B0DB2BC +P 5000 2800 +F 0 "R4" H 5070 2846 50 0000 L CNN +F 1 "4.8k" H 5070 2755 50 0000 L CNN +F 2 "" V 4930 2800 50 0001 C CNN +F 3 "~" H 5000 2800 50 0001 C CNN + 1 5000 2800 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0DB347 +P 4950 4350 +F 0 "R3" H 5020 4396 50 0000 L CNN +F 1 "1.2k" H 5020 4305 50 0000 L CNN +F 2 "" V 4880 4350 50 0001 C CNN +F 3 "~" H 4950 4350 50 0001 C CNN + 1 4950 4350 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0DB393 +P 5650 4350 +F 0 "C2" H 5535 4304 50 0000 R CNN +F 1 "0.1u" H 5535 4395 50 0000 R CNN +F 2 "" H 5688 4200 50 0001 C CNN +F 3 "~" H 5650 4350 50 0001 C CNN + 1 5650 4350 + -1 0 0 1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0DB486 +P 6250 3550 +F 0 "V1" H 6478 3596 50 0000 L CNN +F 1 "VSOURCE" H 6478 3505 50 0000 L CNN +F 2 "" H 6250 3550 50 0001 C CNN +F 3 "" H 6250 3550 50 0001 C CNN +F 4 "V" H 6250 3550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 6250 3550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6250 3550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 6250 3550 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C3 +U 1 1 5B0DB4CA +P 7400 3550 +F 0 "C3" H 7285 3504 50 0000 R CNN +F 1 "20n" H 7285 3595 50 0000 R CNN +F 2 "" H 7438 3400 50 0001 C CNN +F 3 "~" H 7400 3550 50 0001 C CNN + 1 7400 3550 + -1 0 0 1 +$EndComp +$Comp +L Device:C C4 +U 1 1 5B0DB53B +P 7400 4400 +F 0 "C4" H 7285 4354 50 0000 R CNN +F 1 "5n" H 7285 4445 50 0000 R CNN +F 2 "" H 7438 4250 50 0001 C CNN +F 3 "~" H 7400 4400 50 0001 C CNN + 1 7400 4400 + -1 0 0 1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0DB5B6 +P 8250 3800 +F 0 "L1" H 8303 3846 50 0000 L CNN +F 1 "50m" H 8303 3755 50 0000 L CNN +F 2 "" H 8250 3800 50 0001 C CNN +F 3 "~" H 8250 3800 50 0001 C CNN + 1 8250 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 3850 3150 3600 +Wire Wire Line + 3150 3600 3600 3600 +Wire Wire Line + 3600 4200 3600 3600 +Connection ~ 3600 3600 +Wire Wire Line + 3600 3600 4200 3600 +Wire Wire Line + 3600 3600 3600 2950 +Wire Wire Line + 3600 2950 3650 2950 +Wire Wire Line + 3650 2650 3650 2050 +Wire Wire Line + 3650 2050 5000 2050 +Wire Wire Line + 5000 2050 5000 2650 +Wire Wire Line + 3600 4500 3600 5250 +Wire Wire Line + 3600 5250 4950 5250 +Wire Wire Line + 4500 3800 4950 3800 +Wire Wire Line + 4950 3800 4950 4050 +Wire Wire Line + 4500 3400 5000 3400 +Wire Wire Line + 5000 3400 5000 3100 +Wire Wire Line + 5650 4200 5650 4050 +Wire Wire Line + 5650 4050 4950 4050 +Connection ~ 4950 4050 +Wire Wire Line + 4950 4050 4950 4200 +Wire Wire Line + 4950 5250 5300 5250 +Wire Wire Line + 6250 5250 6250 3850 +Connection ~ 4950 5250 +Wire Wire Line + 4950 4500 4950 5250 +Wire Wire Line + 5650 4500 5650 5250 +Connection ~ 5650 5250 +Wire Wire Line + 5650 5250 6250 5250 +Wire Wire Line + 6250 3250 6250 2050 +Wire Wire Line + 6250 2050 5000 2050 +Connection ~ 5000 2050 +Wire Wire Line + 2850 3850 2850 5950 +Wire Wire Line + 2850 5950 7400 5950 +Wire Wire Line + 7400 5950 7400 4550 +Wire Wire Line + 7400 4250 7400 3950 +Wire Wire Line + 7400 3400 7400 3100 +Wire Wire Line + 7400 3100 5000 3100 +Connection ~ 5000 3100 +Wire Wire Line + 5000 3100 5000 2950 +Wire Wire Line + 7400 5950 8250 5950 +Wire Wire Line + 8250 5950 8250 3950 +Connection ~ 7400 5950 +Wire Wire Line + 8250 3650 8250 3100 +Wire Wire Line + 8250 3100 7400 3100 +Connection ~ 7400 3100 +$Comp +L power:GND #PWR01 +U 1 1 5B0DE237 +P 5300 5550 +F 0 "#PWR01" H 5300 5300 50 0001 C CNN +F 1 "GND" H 5305 5377 50 0000 C CNN +F 2 "" H 5300 5550 50 0001 C CNN +F 3 "" H 5300 5550 50 0001 C CNN + 1 5300 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 5550 5300 5250 +Connection ~ 5300 5250 +Wire Wire Line + 5300 5250 5650 5250 +$Comp +L power:GND #PWR02 +U 1 1 5B0DE71B +P 7850 4100 +F 0 "#PWR02" H 7850 3850 50 0001 C CNN +F 1 "GND" H 7855 3927 50 0000 C CNN +F 2 "" H 7850 4100 50 0001 C CNN +F 3 "" H 7850 4100 50 0001 C CNN + 1 7850 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7850 4100 7850 3950 +Wire Wire Line + 7850 3950 7400 3950 +Connection ~ 7400 3950 +Wire Wire Line + 7400 3950 7400 3700 +Text GLabel 8650 2550 0 50 Output ~ 0 +out +Wire Wire Line + 8650 2550 8800 2550 +Wire Wire Line + 8800 2550 8800 2100 +Wire Wire Line + 8800 2100 8250 2100 +Wire Wire Line + 8250 2100 8250 3100 +Connection ~ 8250 3100 +$Comp +L Transistor_BJT:BC548 Q1 +U 1 1 5B0E8A8C +P 4400 3600 +F 0 "Q1" H 4591 3646 50 0000 L CNN +F 1 "BC548" H 4591 3555 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 4600 3525 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 4400 3600 50 0001 L CNN + 1 4400 3600 + 1 0 0 -1 +$EndComp +Text Notes 9050 5350 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/colpitt oscillator/colpitt oscillator.cir b/analog circuits/colpitt oscillator/colpitt oscillator.cir new file mode 100644 index 0000000..0ae75ec --- /dev/null +++ b/analog circuits/colpitt oscillator/colpitt oscillator.cir @@ -0,0 +1,15 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 0.1u +R2 Net-_R2-Pad1_ Net-_C1-Pad1_ 190k +R1 Net-_C1-Pad1_ GND 36k +R4 Net-_R2-Pad1_ out 4.8k +R3 Net-_C2-Pad2_ GND 1.2k +C2 GND Net-_C2-Pad2_ 0.1u +V1 Net-_R2-Pad1_ GND dc 5 +C3 GND out 20n +C4 Net-_C1-Pad2_ GND 5n +L1 out Net-_C1-Pad2_ 50m +Q1 out Net-_C1-Pad1_ Net-_C2-Pad2_ BC548 +.tran .25m 30m +.end diff --git a/analog circuits/colpitt oscillator/colpitt oscillator.kicad_pcb b/analog circuits/colpitt oscillator/colpitt oscillator.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/colpitt oscillator/colpitt oscillator.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/colpitt oscillator/colpitt oscillator.pro b/analog circuits/colpitt oscillator/colpitt oscillator.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/colpitt oscillator/colpitt oscillator.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/colpitt oscillator/colpitt oscillator.sch b/analog circuits/colpitt oscillator/colpitt oscillator.sch new file mode 100644 index 0000000..1889122 --- /dev/null +++ b/analog circuits/colpitt oscillator/colpitt oscillator.sch @@ -0,0 +1,272 @@ +EESchema Schematic File Version 4 +LIBS:colpitt oscillator-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:C C1 +U 1 1 5B0DB14E +P 3000 3850 +F 0 "C1" V 2748 3850 50 0000 C CNN +F 1 "0.1u" V 2839 3850 50 0000 C CNN +F 2 "" H 3038 3700 50 0001 C CNN +F 3 "~" H 3000 3850 50 0001 C CNN + 1 3000 3850 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0DB24B +P 3650 2800 +F 0 "R2" H 3720 2846 50 0000 L CNN +F 1 "190k" H 3720 2755 50 0000 L CNN +F 2 "" V 3580 2800 50 0001 C CNN +F 3 "~" H 3650 2800 50 0001 C CNN + 1 3650 2800 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0DB27E +P 3600 4350 +F 0 "R1" H 3670 4396 50 0000 L CNN +F 1 "36k" H 3670 4305 50 0000 L CNN +F 2 "" V 3530 4350 50 0001 C CNN +F 3 "~" H 3600 4350 50 0001 C CNN + 1 3600 4350 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B0DB2BC +P 5000 2800 +F 0 "R4" H 5070 2846 50 0000 L CNN +F 1 "4.8k" H 5070 2755 50 0000 L CNN +F 2 "" V 4930 2800 50 0001 C CNN +F 3 "~" H 5000 2800 50 0001 C CNN + 1 5000 2800 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0DB347 +P 4950 4350 +F 0 "R3" H 5020 4396 50 0000 L CNN +F 1 "1.2k" H 5020 4305 50 0000 L CNN +F 2 "" V 4880 4350 50 0001 C CNN +F 3 "~" H 4950 4350 50 0001 C CNN + 1 4950 4350 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0DB393 +P 5650 4350 +F 0 "C2" H 5535 4304 50 0000 R CNN +F 1 "0.1u" H 5535 4395 50 0000 R CNN +F 2 "" H 5688 4200 50 0001 C CNN +F 3 "~" H 5650 4350 50 0001 C CNN + 1 5650 4350 + -1 0 0 1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0DB486 +P 6250 3550 +F 0 "V1" H 6478 3596 50 0000 L CNN +F 1 "VSOURCE" H 6478 3505 50 0000 L CNN +F 2 "" H 6250 3550 50 0001 C CNN +F 3 "" H 6250 3550 50 0001 C CNN +F 4 "V" H 6250 3550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 6250 3550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6250 3550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 6250 3550 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C3 +U 1 1 5B0DB4CA +P 7400 3550 +F 0 "C3" H 7285 3504 50 0000 R CNN +F 1 "20n" H 7285 3595 50 0000 R CNN +F 2 "" H 7438 3400 50 0001 C CNN +F 3 "~" H 7400 3550 50 0001 C CNN + 1 7400 3550 + -1 0 0 1 +$EndComp +$Comp +L Device:C C4 +U 1 1 5B0DB53B +P 7400 4400 +F 0 "C4" H 7285 4354 50 0000 R CNN +F 1 "5n" H 7285 4445 50 0000 R CNN +F 2 "" H 7438 4250 50 0001 C CNN +F 3 "~" H 7400 4400 50 0001 C CNN + 1 7400 4400 + -1 0 0 1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0DB5B6 +P 8250 3800 +F 0 "L1" H 8303 3846 50 0000 L CNN +F 1 "50m" H 8303 3755 50 0000 L CNN +F 2 "" H 8250 3800 50 0001 C CNN +F 3 "~" H 8250 3800 50 0001 C CNN + 1 8250 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 3850 3150 3600 +Wire Wire Line + 3150 3600 3600 3600 +Wire Wire Line + 3600 4200 3600 3600 +Connection ~ 3600 3600 +Wire Wire Line + 3600 3600 4200 3600 +Wire Wire Line + 3600 3600 3600 2950 +Wire Wire Line + 3600 2950 3650 2950 +Wire Wire Line + 3650 2650 3650 2050 +Wire Wire Line + 3650 2050 5000 2050 +Wire Wire Line + 5000 2050 5000 2650 +Wire Wire Line + 3600 4500 3600 5250 +Wire Wire Line + 3600 5250 4950 5250 +Wire Wire Line + 4500 3800 4950 3800 +Wire Wire Line + 4950 3800 4950 4050 +Wire Wire Line + 4500 3400 5000 3400 +Wire Wire Line + 5000 3400 5000 3100 +Wire Wire Line + 5650 4200 5650 4050 +Wire Wire Line + 5650 4050 4950 4050 +Connection ~ 4950 4050 +Wire Wire Line + 4950 4050 4950 4200 +Wire Wire Line + 4950 5250 5300 5250 +Wire Wire Line + 6250 5250 6250 3850 +Connection ~ 4950 5250 +Wire Wire Line + 4950 4500 4950 5250 +Wire Wire Line + 5650 4500 5650 5250 +Connection ~ 5650 5250 +Wire Wire Line + 5650 5250 6250 5250 +Wire Wire Line + 6250 3250 6250 2050 +Wire Wire Line + 6250 2050 5000 2050 +Connection ~ 5000 2050 +Wire Wire Line + 2850 3850 2850 5950 +Wire Wire Line + 2850 5950 7400 5950 +Wire Wire Line + 7400 5950 7400 4550 +Wire Wire Line + 7400 4250 7400 3950 +Wire Wire Line + 7400 3400 7400 3100 +Wire Wire Line + 7400 3100 5000 3100 +Connection ~ 5000 3100 +Wire Wire Line + 5000 3100 5000 2950 +Wire Wire Line + 7400 5950 8250 5950 +Wire Wire Line + 8250 5950 8250 3950 +Connection ~ 7400 5950 +Wire Wire Line + 8250 3650 8250 3100 +Wire Wire Line + 8250 3100 7400 3100 +Connection ~ 7400 3100 +$Comp +L power:GND #PWR01 +U 1 1 5B0DE237 +P 5300 5550 +F 0 "#PWR01" H 5300 5300 50 0001 C CNN +F 1 "GND" H 5305 5377 50 0000 C CNN +F 2 "" H 5300 5550 50 0001 C CNN +F 3 "" H 5300 5550 50 0001 C CNN + 1 5300 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 5550 5300 5250 +Connection ~ 5300 5250 +Wire Wire Line + 5300 5250 5650 5250 +$Comp +L power:GND #PWR02 +U 1 1 5B0DE71B +P 7850 4100 +F 0 "#PWR02" H 7850 3850 50 0001 C CNN +F 1 "GND" H 7855 3927 50 0000 C CNN +F 2 "" H 7850 4100 50 0001 C CNN +F 3 "" H 7850 4100 50 0001 C CNN + 1 7850 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7850 4100 7850 3950 +Wire Wire Line + 7850 3950 7400 3950 +Connection ~ 7400 3950 +Wire Wire Line + 7400 3950 7400 3700 +Text GLabel 8650 2550 0 50 Output ~ 0 +out +Wire Wire Line + 8650 2550 8800 2550 +Wire Wire Line + 8800 2550 8800 2100 +Wire Wire Line + 8800 2100 8250 2100 +Wire Wire Line + 8250 2100 8250 3100 +Connection ~ 8250 3100 +$Comp +L Transistor_BJT:BC548 Q1 +U 1 1 5B0E8A8C +P 4400 3600 +F 0 "Q1" H 4591 3646 50 0000 L CNN +F 1 "BC548" H 4591 3555 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 4600 3525 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 4400 3600 50 0001 L CNN +F 4 "Q" H 4400 3600 50 0001 C CNN "Spice_Primitive" +F 5 "BC548" H 4400 3600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4400 3600 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" H 4400 3600 50 0001 C CNN "Spice_Lib_File" + 1 4400 3600 + 1 0 0 -1 +$EndComp +Text Notes 9050 5350 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/differential amplifier using op amp/differential amplifier using op amp-cache.lib b/analog circuits/differential amplifier using op amp/differential amplifier using op amp-cache.lib new file mode 100644 index 0000000..e5ac7f8 --- /dev/null +++ b/analog circuits/differential amplifier using op amp/differential amplifier using op amp-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:Opamp_Dual_Generic +# +DEF Device:Opamp_Dual_Generic U 0 20 Y Y 3 F N +F0 "U" 0 200 50 H V L CNN +F1 "Device:Opamp_Dual_Generic" 0 -200 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* + MSOP*3x3mm*P0.65mm* + SSOP*2.95x2.8mm*P0.65mm* + TSSOP*3x3mm*P0.65mm* + VSSOP*P0.5mm* + TO?99* +$ENDFPLIST +DRAW +P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f +P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f +X ~ 1 300 0 100 L 50 50 1 1 O +X - 2 -300 -100 100 R 50 50 1 1 I +X + 3 -300 100 100 R 50 50 1 1 I +X + 5 -300 100 100 R 50 50 2 1 I +X - 6 -300 -100 100 R 50 50 2 1 I +X ~ 7 300 0 100 L 50 50 2 1 O +X V- 4 -100 -300 150 U 50 50 3 1 W +X V+ 8 -100 300 150 D 50 50 3 1 W +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VSS +# +DEF power:VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VSS" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/differential amplifier using op amp/differential amplifier using op amp.bak b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.bak new file mode 100644 index 0000000..7fe40ca --- /dev/null +++ b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.bak @@ -0,0 +1,288 @@ +EESchema Schematic File Version 4 +LIBS:differential amplifier using op amp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R3 +U 1 1 5B0A7E4C +P 4700 3300 +F 0 "R3" V 4493 3300 50 0000 C CNN +F 1 "100k" V 4584 3300 50 0000 C CNN +F 2 "" V 4630 3300 50 0001 C CNN +F 3 "~" H 4700 3300 50 0001 C CNN + 1 4700 3300 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0A7E89 +P 4550 3650 +F 0 "R1" V 4343 3650 50 0000 C CNN +F 1 "100k" V 4434 3650 50 0000 C CNN +F 2 "" V 4480 3650 50 0001 C CNN +F 3 "~" H 4550 3650 50 0001 C CNN + 1 4550 3650 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0A7EBE +P 4550 3950 +F 0 "R2" V 4343 3950 50 0000 C CNN +F 1 "100k" V 4434 3950 50 0000 C CNN +F 2 "" V 4480 3950 50 0001 C CNN +F 3 "~" H 4550 3950 50 0001 C CNN + 1 4550 3950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B0A7F12 +P 5950 4400 +F 0 "R4" V 5743 4400 50 0000 C CNN +F 1 "100k" V 5834 4400 50 0000 C CNN +F 2 "" V 5880 4400 50 0001 C CNN +F 3 "~" H 5950 4400 50 0001 C CNN + 1 5950 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 4700 3650 5200 3650 +Wire Wire Line + 4700 3950 5300 3950 +Wire Wire Line + 5700 3950 5700 3850 +Wire Wire Line + 5300 3950 5300 4400 +Wire Wire Line + 5300 4400 5800 4400 +Connection ~ 5300 3950 +Wire Wire Line + 5300 3950 5700 3950 +Wire Wire Line + 6100 4400 6800 4400 +Wire Wire Line + 6800 4400 6800 3750 +Wire Wire Line + 6800 3750 6600 3750 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0A7FEF +P 3850 4300 +F 0 "V1" H 4078 4346 50 0000 L CNN +F 1 "VSOURCE" H 4078 4255 50 0000 L CNN +F 2 "" H 3850 4300 50 0001 C CNN +F 3 "" H 3850 4300 50 0001 C CNN +F 4 "V" H 3850 4300 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 9)" H 3850 4300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3850 4300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3850 4300 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0A802D +P 4400 4700 +F 0 "V2" H 4628 4746 50 0000 L CNN +F 1 "VSOURCE" H 4628 4655 50 0000 L CNN +F 2 "" H 4400 4700 50 0001 C CNN +F 3 "" H 4400 4700 50 0001 C CNN +F 4 "V" H 4400 4700 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 4)" H 4400 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4400 4700 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4400 4700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4400 4400 4100 +Wire Wire Line + 3850 4000 3850 3650 +Wire Wire Line + 3850 3650 4200 3650 +Wire Wire Line + 3850 4600 3850 5200 +Wire Wire Line + 3850 5200 4150 5200 +Wire Wire Line + 4400 5200 4400 5000 +Wire Wire Line + 4850 3300 5200 3300 +Wire Wire Line + 5200 3300 5200 3650 +Connection ~ 5200 3650 +Wire Wire Line + 5200 3650 5700 3650 +Wire Wire Line + 4550 3300 3250 3300 +Wire Wire Line + 3250 3300 3250 5550 +Wire Wire Line + 3250 5550 3900 5550 +Wire Wire Line + 4150 5550 4150 5200 +Connection ~ 4150 5200 +Wire Wire Line + 4150 5200 4400 5200 +$Comp +L power:GND #PWR01 +U 1 1 5B0A911C +P 3900 5650 +F 0 "#PWR01" H 3900 5400 50 0001 C CNN +F 1 "GND" H 3905 5477 50 0000 C CNN +F 2 "" H 3900 5650 50 0001 C CNN +F 3 "" H 3900 5650 50 0001 C CNN + 1 3900 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 5650 3900 5600 +Connection ~ 3900 5550 +Wire Wire Line + 3900 5550 4150 5550 +$Comp +L power:PWR_FLAG #FLG01 +U 1 1 5B0AA282 +P 4400 5600 +F 0 "#FLG01" H 4400 5675 50 0001 C CNN +F 1 "PWR_FLAG" H 4400 5774 50 0000 C CNN +F 2 "" H 4400 5600 50 0001 C CNN +F 3 "~" H 4400 5600 50 0001 C CNN + 1 4400 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 5600 3900 5600 +Connection ~ 3900 5600 +Wire Wire Line + 3900 5600 3900 5550 +$Comp +L pspice:VSOURCE V4 +U 1 1 5B0FBDCF +P 7650 4050 +F 0 "V4" H 7878 4096 50 0000 L CNN +F 1 "VSOURCE" H 7878 4005 50 0000 L CNN +F 2 "" H 7650 4050 50 0001 C CNN +F 3 "" H 7650 4050 50 0001 C CNN +F 4 "V" H 7650 4050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 10" H 7650 4050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7650 4050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7650 4050 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0FBE45 +P 7650 3300 +F 0 "V3" H 7878 3346 50 0000 L CNN +F 1 "VSOURCE" H 7878 3255 50 0000 L CNN +F 2 "" H 7650 3300 50 0001 C CNN +F 3 "" H 7650 3300 50 0001 C CNN +F 4 "V" H 7650 3300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 10" H 7650 3300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7650 3300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7650 3300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR06 +U 1 1 5B0FBEF4 +P 7950 3700 +F 0 "#PWR06" H 7950 3450 50 0001 C CNN +F 1 "GND" H 7955 3527 50 0000 C CNN +F 2 "" H 7950 3700 50 0001 C CNN +F 3 "" H 7950 3700 50 0001 C CNN + 1 7950 3700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B0FBF47 +P 7650 3000 +F 0 "#PWR04" H 7650 2850 50 0001 C CNN +F 1 "VDD" H 7667 3173 50 0000 C CNN +F 2 "" H 7650 3000 50 0001 C CNN +F 3 "" H 7650 3000 50 0001 C CNN + 1 7650 3000 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR05 +U 1 1 5B0FBF6D +P 7850 4500 +F 0 "#PWR05" H 7850 4350 50 0001 C CNN +F 1 "VSS" H 7867 4673 50 0000 C CNN +F 2 "" H 7850 4500 50 0001 C CNN +F 3 "" H 7850 4500 50 0001 C CNN + 1 7850 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7650 4350 7650 4500 +Wire Wire Line + 7650 4500 7850 4500 +Wire Wire Line + 7650 3750 7650 3700 +Wire Wire Line + 7950 3700 7650 3700 +Connection ~ 7650 3700 +Wire Wire Line + 7650 3700 7650 3600 +Text GLabel 4150 3450 0 50 Input ~ 0 +i1 +Wire Wire Line + 4150 3450 4200 3450 +Wire Wire Line + 4200 3450 4200 3650 +Connection ~ 4200 3650 +Wire Wire Line + 4200 3650 4400 3650 +Text GLabel 4200 4000 0 50 Input ~ 0 +i2 +Wire Wire Line + 4200 4000 4200 4100 +Wire Wire Line + 4200 4100 4400 4100 +Connection ~ 4400 4100 +Wire Wire Line + 4400 4100 4400 3950 +Text GLabel 6850 3550 0 50 Output ~ 0 +out +Wire Wire Line + 6850 3550 7200 3550 +Wire Wire Line + 7200 3550 7200 3300 +Wire Wire Line + 7200 3300 6600 3300 +Wire Wire Line + 6600 3300 6600 3750 +Connection ~ 6600 3750 +Wire Wire Line + 6600 3750 6300 3750 +$Comp +L Device:Opamp_Dual_Generic U1 +U 1 1 5B20D0B6 +P 6000 3750 +F 0 "U1" H 6000 4117 50 0000 C CNN +F 1 "Opamp_Dual_Generic" H 6000 4026 50 0000 C CNN +F 2 "" H 6000 3750 50 0001 C CNN +F 3 "~" H 6000 3750 50 0001 C CNN +F 4 "X" H 6000 3750 50 0001 C CNN "Spice_Primitive" +F 5 "OPAMP1" H 6000 3750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6000 3750 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/newopamp.cir" H 6000 3750 50 0001 C CNN "Spice_Lib_File" + 1 6000 3750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/analog circuits/differential amplifier using op amp/differential amplifier using op amp.cir b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.cir new file mode 100644 index 0000000..c8d6342 --- /dev/null +++ b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.cir @@ -0,0 +1,12 @@ +.title KiCad schematic +.include "/home/akshay/newopamp.cir" +R3 Net-_R1-Pad1_ GND 100k +R1 Net-_R1-Pad1_ i1 100k +R2 Net-_R2-Pad1_ i2 100k +R4 out Net-_R2-Pad1_ 100k +V1 i1 GND dc 10 +V2 i2 GND dc 3 +V4 GND VSS dc 10 +V3 VDD GND dc 10 +XU1 out Net-_R2-Pad1_ Net-_R1-Pad1_ OPAMP1 +.end diff --git a/analog circuits/differential amplifier using op amp/differential amplifier using op amp.kicad_pcb b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/differential amplifier using op amp/differential amplifier using op amp.pro b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/differential amplifier using op amp/differential amplifier using op amp.sch b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.sch new file mode 100644 index 0000000..480280d --- /dev/null +++ b/analog circuits/differential amplifier using op amp/differential amplifier using op amp.sch @@ -0,0 +1,290 @@ +EESchema Schematic File Version 4 +LIBS:differential amplifier using op amp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R3 +U 1 1 5B0A7E4C +P 4700 3300 +F 0 "R3" V 4493 3300 50 0000 C CNN +F 1 "100k" V 4584 3300 50 0000 C CNN +F 2 "" V 4630 3300 50 0001 C CNN +F 3 "~" H 4700 3300 50 0001 C CNN + 1 4700 3300 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0A7E89 +P 4550 3650 +F 0 "R1" V 4343 3650 50 0000 C CNN +F 1 "100k" V 4434 3650 50 0000 C CNN +F 2 "" V 4480 3650 50 0001 C CNN +F 3 "~" H 4550 3650 50 0001 C CNN + 1 4550 3650 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0A7EBE +P 4550 3950 +F 0 "R2" V 4343 3950 50 0000 C CNN +F 1 "100k" V 4434 3950 50 0000 C CNN +F 2 "" V 4480 3950 50 0001 C CNN +F 3 "~" H 4550 3950 50 0001 C CNN + 1 4550 3950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B0A7F12 +P 5950 4400 +F 0 "R4" V 5743 4400 50 0000 C CNN +F 1 "100k" V 5834 4400 50 0000 C CNN +F 2 "" V 5880 4400 50 0001 C CNN +F 3 "~" H 5950 4400 50 0001 C CNN + 1 5950 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 4700 3650 5200 3650 +Wire Wire Line + 4700 3950 5300 3950 +Wire Wire Line + 5700 3950 5700 3850 +Wire Wire Line + 5300 3950 5300 4400 +Wire Wire Line + 5300 4400 5800 4400 +Connection ~ 5300 3950 +Wire Wire Line + 5300 3950 5700 3950 +Wire Wire Line + 6100 4400 6800 4400 +Wire Wire Line + 6800 4400 6800 3750 +Wire Wire Line + 6800 3750 6600 3750 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0A7FEF +P 3850 4300 +F 0 "V1" H 4078 4346 50 0000 L CNN +F 1 "VSOURCE" H 4078 4255 50 0000 L CNN +F 2 "" H 3850 4300 50 0001 C CNN +F 3 "" H 3850 4300 50 0001 C CNN +F 4 "V" H 3850 4300 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 9)" H 3850 4300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3850 4300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3850 4300 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0A802D +P 4400 4700 +F 0 "V2" H 4628 4746 50 0000 L CNN +F 1 "VSOURCE" H 4628 4655 50 0000 L CNN +F 2 "" H 4400 4700 50 0001 C CNN +F 3 "" H 4400 4700 50 0001 C CNN +F 4 "V" H 4400 4700 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 4)" H 4400 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4400 4700 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4400 4700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4400 4400 4100 +Wire Wire Line + 3850 4000 3850 3650 +Wire Wire Line + 3850 3650 4200 3650 +Wire Wire Line + 3850 4600 3850 5200 +Wire Wire Line + 3850 5200 4150 5200 +Wire Wire Line + 4400 5200 4400 5000 +Wire Wire Line + 4850 3300 5200 3300 +Wire Wire Line + 5200 3300 5200 3650 +Connection ~ 5200 3650 +Wire Wire Line + 5200 3650 5700 3650 +Wire Wire Line + 4550 3300 3250 3300 +Wire Wire Line + 3250 3300 3250 5550 +Wire Wire Line + 3250 5550 3900 5550 +Wire Wire Line + 4150 5550 4150 5200 +Connection ~ 4150 5200 +Wire Wire Line + 4150 5200 4400 5200 +$Comp +L power:GND #PWR01 +U 1 1 5B0A911C +P 3900 5650 +F 0 "#PWR01" H 3900 5400 50 0001 C CNN +F 1 "GND" H 3905 5477 50 0000 C CNN +F 2 "" H 3900 5650 50 0001 C CNN +F 3 "" H 3900 5650 50 0001 C CNN + 1 3900 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 5650 3900 5600 +Connection ~ 3900 5550 +Wire Wire Line + 3900 5550 4150 5550 +$Comp +L power:PWR_FLAG #FLG01 +U 1 1 5B0AA282 +P 4400 5600 +F 0 "#FLG01" H 4400 5675 50 0001 C CNN +F 1 "PWR_FLAG" H 4400 5774 50 0000 C CNN +F 2 "" H 4400 5600 50 0001 C CNN +F 3 "~" H 4400 5600 50 0001 C CNN + 1 4400 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 5600 3900 5600 +Connection ~ 3900 5600 +Wire Wire Line + 3900 5600 3900 5550 +$Comp +L pspice:VSOURCE V4 +U 1 1 5B0FBDCF +P 7650 4050 +F 0 "V4" H 7878 4096 50 0000 L CNN +F 1 "VSOURCE" H 7878 4005 50 0000 L CNN +F 2 "" H 7650 4050 50 0001 C CNN +F 3 "" H 7650 4050 50 0001 C CNN +F 4 "V" H 7650 4050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 10" H 7650 4050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7650 4050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7650 4050 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0FBE45 +P 7650 3300 +F 0 "V3" H 7878 3346 50 0000 L CNN +F 1 "VSOURCE" H 7878 3255 50 0000 L CNN +F 2 "" H 7650 3300 50 0001 C CNN +F 3 "" H 7650 3300 50 0001 C CNN +F 4 "V" H 7650 3300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 10" H 7650 3300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7650 3300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7650 3300 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR06 +U 1 1 5B0FBEF4 +P 7950 3700 +F 0 "#PWR06" H 7950 3450 50 0001 C CNN +F 1 "GND" H 7955 3527 50 0000 C CNN +F 2 "" H 7950 3700 50 0001 C CNN +F 3 "" H 7950 3700 50 0001 C CNN + 1 7950 3700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B0FBF47 +P 7650 3000 +F 0 "#PWR04" H 7650 2850 50 0001 C CNN +F 1 "VDD" H 7667 3173 50 0000 C CNN +F 2 "" H 7650 3000 50 0001 C CNN +F 3 "" H 7650 3000 50 0001 C CNN + 1 7650 3000 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR05 +U 1 1 5B0FBF6D +P 7850 4500 +F 0 "#PWR05" H 7850 4350 50 0001 C CNN +F 1 "VSS" H 7867 4673 50 0000 C CNN +F 2 "" H 7850 4500 50 0001 C CNN +F 3 "" H 7850 4500 50 0001 C CNN + 1 7850 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7650 4350 7650 4500 +Wire Wire Line + 7650 4500 7850 4500 +Wire Wire Line + 7650 3750 7650 3700 +Wire Wire Line + 7950 3700 7650 3700 +Connection ~ 7650 3700 +Wire Wire Line + 7650 3700 7650 3600 +Text GLabel 4150 3450 0 50 Input ~ 0 +i1 +Wire Wire Line + 4150 3450 4200 3450 +Wire Wire Line + 4200 3450 4200 3650 +Connection ~ 4200 3650 +Wire Wire Line + 4200 3650 4400 3650 +Text GLabel 4200 4000 0 50 Input ~ 0 +i2 +Wire Wire Line + 4200 4000 4200 4100 +Wire Wire Line + 4200 4100 4400 4100 +Connection ~ 4400 4100 +Wire Wire Line + 4400 4100 4400 3950 +Text GLabel 6850 3550 0 50 Output ~ 0 +out +Wire Wire Line + 6850 3550 7200 3550 +Wire Wire Line + 7200 3550 7200 3300 +Wire Wire Line + 7200 3300 6600 3300 +Wire Wire Line + 6600 3300 6600 3750 +Connection ~ 6600 3750 +Wire Wire Line + 6600 3750 6300 3750 +$Comp +L Device:Opamp_Dual_Generic U1 +U 1 1 5B20D0B6 +P 6000 3750 +F 0 "U1" H 6000 4117 50 0000 C CNN +F 1 "Opamp_Dual_Generic" H 6000 4026 50 0000 C CNN +F 2 "" H 6000 3750 50 0001 C CNN +F 3 "~" H 6000 3750 50 0001 C CNN +F 4 "X" H 6000 3750 50 0001 C CNN "Spice_Primitive" +F 5 "OPAMP1" H 6000 3750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6000 3750 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/newopamp.cir" H 6000 3750 50 0001 C CNN "Spice_Lib_File" + 1 6000 3750 + 1 0 0 -1 +$EndComp +Text Notes 6600 5450 0 50 ~ 0 +.tran .25 30m +$EndSCHEMATC diff --git a/analog circuits/differential amplifier using op amp/newopamp.cir b/analog circuits/differential amplifier using op amp/newopamp.cir new file mode 100644 index 0000000..425ef47 --- /dev/null +++ b/analog circuits/differential amplifier using op amp/newopamp.cir @@ -0,0 +1,5 @@ +.SUBCKT OPAMP1 3 2 1 +RIN 1 2 10MEG +EGAIN 3 0 1 2 100K +.ENDS + diff --git a/analog circuits/hartley oscillator/NPN.lib b/analog circuits/hartley oscillator/NPN.lib new file mode 100644 index 0000000..6509fe7 --- /dev/null +++ b/analog circuits/hartley oscillator/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/analog circuits/hartley oscillator/hartley oscillator-cache.lib b/analog circuits/hartley oscillator/hartley oscillator-cache.lib new file mode 100644 index 0000000..4235a61 --- /dev/null +++ b/analog circuits/hartley oscillator/hartley oscillator-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:L +# +DEF Device:L L 0 40 N N 1 F N +F0 "L" -50 0 50 V V C CNN +F1 "Device:L" 75 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Choke_* + *Coil* + Inductor_* + L_* +$ENDFPLIST +DRAW +A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 +A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 +A 0 25 25 -899 899 0 1 0 N 0 0 0 50 +A 0 75 25 -899 899 0 1 0 N 0 50 0 100 +X 1 1 0 150 50 D 50 50 1 1 P +X 2 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Transistor_BJT:BC548 +# +DEF Transistor_BJT:BC548 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "Transistor_BJT:BC548" 200 0 50 H V L CNN +F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC546 BC548 BC549 BC550 BC337 BC338 +$FPLIST + TO?92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 25 0 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 200 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/hartley oscillator/hartley oscillator.bak b/analog circuits/hartley oscillator/hartley oscillator.bak new file mode 100644 index 0000000..30ee76e --- /dev/null +++ b/analog circuits/hartley oscillator/hartley oscillator.bak @@ -0,0 +1,276 @@ +EESchema Schematic File Version 4 +LIBS:hartley oscillator-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:C C1 +U 1 1 5B0E41FC +P 2900 3250 +F 0 "C1" V 2648 3250 50 0000 C CNN +F 1 "0.1u" V 2739 3250 50 0000 C CNN +F 2 "" H 2938 3100 50 0001 C CNN +F 3 "~" H 2900 3250 50 0001 C CNN + 1 2900 3250 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0E431E +P 4150 2400 +F 0 "R1" H 4220 2446 50 0000 L CNN +F 1 "380k" H 4220 2355 50 0000 L CNN +F 2 "" V 4080 2400 50 0001 C CNN +F 3 "~" H 4150 2400 50 0001 C CNN + 1 4150 2400 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0E4345 +P 5200 2450 +F 0 "R3" H 5270 2496 50 0000 L CNN +F 1 "4.8k" H 5270 2405 50 0000 L CNN +F 2 "" V 5130 2450 50 0001 C CNN +F 3 "~" H 5200 2450 50 0001 C CNN + 1 5200 2450 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0E43D1 +P 4150 4100 +F 0 "R2" H 4220 4146 50 0000 L CNN +F 1 "72k" H 4220 4055 50 0000 L CNN +F 2 "" V 4080 4100 50 0001 C CNN +F 3 "~" H 4150 4100 50 0001 C CNN + 1 4150 4100 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B0E4426 +P 5200 4050 +F 0 "R4" H 5270 4096 50 0000 L CNN +F 1 "1.2k" H 5270 4005 50 0000 L CNN +F 2 "" V 5130 4050 50 0001 C CNN +F 3 "~" H 5200 4050 50 0001 C CNN + 1 5200 4050 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C3 +U 1 1 5B0E44A6 +P 6000 4050 +F 0 "C3" H 5885 4004 50 0000 R CNN +F 1 "0.1u" H 5885 4095 50 0000 R CNN +F 2 "" H 6038 3900 50 0001 C CNN +F 3 "~" H 6000 4050 50 0001 C CNN + 1 6000 4050 + -1 0 0 1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0E460A +P 4300 4800 +F 0 "L1" V 4490 4800 50 0000 C CNN +F 1 "12.66m" V 4399 4800 50 0000 C CNN +F 2 "" H 4300 4800 50 0001 C CNN +F 3 "~" H 4300 4800 50 0001 C CNN + 1 4300 4800 + 0 -1 -1 0 +$EndComp +$Comp +L Device:L L2 +U 1 1 5B0E46B5 +P 4950 4800 +F 0 "L2" V 5140 4800 50 0000 C CNN +F 1 "12.66m" V 5049 4800 50 0000 C CNN +F 2 "" H 4950 4800 50 0001 C CNN +F 3 "~" H 4950 4800 50 0001 C CNN + 1 4950 4800 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C4 +U 1 1 5B0E472E +P 6150 2550 +F 0 "C4" V 5898 2550 50 0000 C CNN +F 1 "0.1u" V 5989 2550 50 0000 C CNN +F 2 "" H 6188 2400 50 0001 C CNN +F 3 "~" H 6150 2550 50 0001 C CNN + 1 6150 2550 + 0 1 1 0 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0E479A +P 4650 5150 +F 0 "C2" V 4398 5150 50 0000 C CNN +F 1 "0.01u" V 4489 5150 50 0000 C CNN +F 2 "" H 4688 5000 50 0001 C CNN +F 3 "~" H 4650 5150 50 0001 C CNN + 1 4650 5150 + 0 1 1 0 +$EndComp +Wire Wire Line + 3050 3250 3050 3200 +Wire Wire Line + 3050 3200 4900 3200 +Wire Wire Line + 4150 2550 4150 3950 +Wire Wire Line + 4150 2250 4150 2200 +Wire Wire Line + 4150 2200 4650 2200 +Wire Wire Line + 5200 2200 5200 2300 +Wire Wire Line + 5200 3000 5200 2650 +Wire Wire Line + 5200 3400 5200 3900 +Wire Wire Line + 5200 4200 5200 4400 +Wire Wire Line + 5200 4400 4700 4400 +Wire Wire Line + 4150 4400 4150 4250 +Wire Wire Line + 2750 3250 2750 4800 +Wire Wire Line + 2750 4800 4150 4800 +Wire Wire Line + 4450 4800 4750 4800 +Wire Wire Line + 6300 4800 6300 2550 +Wire Wire Line + 5100 4800 6300 4800 +Wire Wire Line + 6000 2550 5350 2550 +Wire Wire Line + 5350 2550 5350 2650 +Wire Wire Line + 5350 2650 5200 2650 +Connection ~ 5200 2650 +Wire Wire Line + 5200 2650 5200 2600 +Wire Wire Line + 6000 4200 6000 4400 +Wire Wire Line + 6000 4400 5200 4400 +Connection ~ 5200 4400 +Wire Wire Line + 6000 3900 5200 3900 +Connection ~ 5200 3900 +Wire Wire Line + 2750 4800 2750 5150 +Wire Wire Line + 2750 5150 4500 5150 +Connection ~ 2750 4800 +Wire Wire Line + 4800 5150 6300 5150 +Wire Wire Line + 6300 5150 6300 4800 +Connection ~ 6300 4800 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0E58AC +P 5200 1600 +F 0 "V1" V 5565 1600 50 0000 C CNN +F 1 "VSOURCE" V 5474 1600 50 0000 C CNN +F 2 "" H 5200 1600 50 0001 C CNN +F 3 "" H 5200 1600 50 0001 C CNN +F 4 "V" H 5200 1600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 5200 1600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5200 1600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5200 1600 + 0 -1 -1 0 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B0E5C5B +P 5750 1750 +F 0 "#PWR03" H 5750 1500 50 0001 C CNN +F 1 "GND" H 5755 1577 50 0000 C CNN +F 2 "" H 5750 1750 50 0001 C CNN +F 3 "" H 5750 1750 50 0001 C CNN + 1 5750 1750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 1600 4650 1600 +Wire Wire Line + 4650 1600 4650 2200 +Connection ~ 4650 2200 +Wire Wire Line + 4650 2200 5200 2200 +Wire Wire Line + 5500 1600 5750 1600 +Wire Wire Line + 5750 1600 5750 1750 +$Comp +L power:GND #PWR01 +U 1 1 5B0E6585 +P 4700 4450 +F 0 "#PWR01" H 4700 4200 50 0001 C CNN +F 1 "GND" H 4705 4277 50 0000 C CNN +F 2 "" H 4700 4450 50 0001 C CNN +F 3 "" H 4700 4450 50 0001 C CNN + 1 4700 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 4450 4700 4400 +Connection ~ 4700 4400 +Wire Wire Line + 4700 4400 4150 4400 +$Comp +L power:GND #PWR02 +U 1 1 5B0E6DFB +P 4750 4850 +F 0 "#PWR02" H 4750 4600 50 0001 C CNN +F 1 "GND" H 4755 4677 50 0000 C CNN +F 2 "" H 4750 4850 50 0001 C CNN +F 3 "" H 4750 4850 50 0001 C CNN + 1 4750 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 4850 4750 4800 +Connection ~ 4750 4800 +Wire Wire Line + 4750 4800 4800 4800 +Text GLabel 6750 2400 0 50 Output ~ 0 +out +Wire Wire Line + 6750 2400 6900 2400 +Wire Wire Line + 6900 2400 6900 2200 +Wire Wire Line + 6900 2200 6300 2200 +Wire Wire Line + 6300 2200 6300 2550 +Connection ~ 6300 2550 +$Comp +L Transistor_BJT:BC548 Q1 +U 1 1 5B0FCDD5 +P 5100 3200 +F 0 "Q1" H 5291 3246 50 0000 L CNN +F 1 "BC548" H 5291 3155 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 5300 3125 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 5100 3200 50 0001 L CNN + 1 5100 3200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/analog circuits/hartley oscillator/hartley oscillator.cir b/analog circuits/hartley oscillator/hartley oscillator.cir new file mode 100644 index 0000000..0d059b2 --- /dev/null +++ b/analog circuits/hartley oscillator/hartley oscillator.cir @@ -0,0 +1,16 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 0.1u +R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 380k +R3 Net-_R1-Pad1_ Net-_C4-Pad2_ 4.8k +R2 Net-_R1-Pad2_ GND 72k +R4 Net-_C3-Pad2_ GND 1.2k +C3 GND Net-_C3-Pad2_ 0.1u +L1 Net-_C1-Pad2_ GND 12.66m +L2 GND out 12.66m +C4 out Net-_C4-Pad2_ 0.1u +C2 out Net-_C1-Pad2_ 0.01u +V1 Net-_R1-Pad1_ GND dc 5 +Q1 Net-_C4-Pad2_ Net-_C1-Pad1_ Net-_C3-Pad2_ Q2N2222 +.tran .25m 30m +.end diff --git a/analog circuits/hartley oscillator/hartley oscillator.kicad_pcb b/analog circuits/hartley oscillator/hartley oscillator.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/hartley oscillator/hartley oscillator.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/hartley oscillator/hartley oscillator.pro b/analog circuits/hartley oscillator/hartley oscillator.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/hartley oscillator/hartley oscillator.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/hartley oscillator/hartley oscillator.sch b/analog circuits/hartley oscillator/hartley oscillator.sch new file mode 100644 index 0000000..6839da2 --- /dev/null +++ b/analog circuits/hartley oscillator/hartley oscillator.sch @@ -0,0 +1,282 @@ +EESchema Schematic File Version 4 +LIBS:hartley oscillator-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:C C1 +U 1 1 5B0E41FC +P 2900 3250 +F 0 "C1" V 2648 3250 50 0000 C CNN +F 1 "0.1u" V 2739 3250 50 0000 C CNN +F 2 "" H 2938 3100 50 0001 C CNN +F 3 "~" H 2900 3250 50 0001 C CNN + 1 2900 3250 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0E431E +P 4150 2400 +F 0 "R1" H 4220 2446 50 0000 L CNN +F 1 "380k" H 4220 2355 50 0000 L CNN +F 2 "" V 4080 2400 50 0001 C CNN +F 3 "~" H 4150 2400 50 0001 C CNN + 1 4150 2400 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0E4345 +P 5200 2450 +F 0 "R3" H 5270 2496 50 0000 L CNN +F 1 "4.8k" H 5270 2405 50 0000 L CNN +F 2 "" V 5130 2450 50 0001 C CNN +F 3 "~" H 5200 2450 50 0001 C CNN + 1 5200 2450 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0E43D1 +P 4150 4100 +F 0 "R2" H 4220 4146 50 0000 L CNN +F 1 "72k" H 4220 4055 50 0000 L CNN +F 2 "" V 4080 4100 50 0001 C CNN +F 3 "~" H 4150 4100 50 0001 C CNN + 1 4150 4100 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B0E4426 +P 5200 4050 +F 0 "R4" H 5270 4096 50 0000 L CNN +F 1 "1.2k" H 5270 4005 50 0000 L CNN +F 2 "" V 5130 4050 50 0001 C CNN +F 3 "~" H 5200 4050 50 0001 C CNN + 1 5200 4050 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C3 +U 1 1 5B0E44A6 +P 6000 4050 +F 0 "C3" H 5885 4004 50 0000 R CNN +F 1 "0.1u" H 5885 4095 50 0000 R CNN +F 2 "" H 6038 3900 50 0001 C CNN +F 3 "~" H 6000 4050 50 0001 C CNN + 1 6000 4050 + -1 0 0 1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0E460A +P 4300 4800 +F 0 "L1" V 4490 4800 50 0000 C CNN +F 1 "12.66m" V 4399 4800 50 0000 C CNN +F 2 "" H 4300 4800 50 0001 C CNN +F 3 "~" H 4300 4800 50 0001 C CNN + 1 4300 4800 + 0 -1 -1 0 +$EndComp +$Comp +L Device:L L2 +U 1 1 5B0E46B5 +P 4950 4800 +F 0 "L2" V 5140 4800 50 0000 C CNN +F 1 "12.66m" V 5049 4800 50 0000 C CNN +F 2 "" H 4950 4800 50 0001 C CNN +F 3 "~" H 4950 4800 50 0001 C CNN + 1 4950 4800 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C4 +U 1 1 5B0E472E +P 6150 2550 +F 0 "C4" V 5898 2550 50 0000 C CNN +F 1 "0.1u" V 5989 2550 50 0000 C CNN +F 2 "" H 6188 2400 50 0001 C CNN +F 3 "~" H 6150 2550 50 0001 C CNN + 1 6150 2550 + 0 1 1 0 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0E479A +P 4650 5150 +F 0 "C2" V 4398 5150 50 0000 C CNN +F 1 "0.01u" V 4489 5150 50 0000 C CNN +F 2 "" H 4688 5000 50 0001 C CNN +F 3 "~" H 4650 5150 50 0001 C CNN + 1 4650 5150 + 0 1 1 0 +$EndComp +Wire Wire Line + 3050 3250 3050 3200 +Wire Wire Line + 3050 3200 4900 3200 +Wire Wire Line + 4150 2550 4150 3950 +Wire Wire Line + 4150 2250 4150 2200 +Wire Wire Line + 4150 2200 4650 2200 +Wire Wire Line + 5200 2200 5200 2300 +Wire Wire Line + 5200 3000 5200 2650 +Wire Wire Line + 5200 3400 5200 3900 +Wire Wire Line + 5200 4200 5200 4400 +Wire Wire Line + 5200 4400 4700 4400 +Wire Wire Line + 4150 4400 4150 4250 +Wire Wire Line + 2750 3250 2750 4800 +Wire Wire Line + 2750 4800 4150 4800 +Wire Wire Line + 4450 4800 4750 4800 +Wire Wire Line + 6300 4800 6300 2550 +Wire Wire Line + 5100 4800 6300 4800 +Wire Wire Line + 6000 2550 5350 2550 +Wire Wire Line + 5350 2550 5350 2650 +Wire Wire Line + 5350 2650 5200 2650 +Connection ~ 5200 2650 +Wire Wire Line + 5200 2650 5200 2600 +Wire Wire Line + 6000 4200 6000 4400 +Wire Wire Line + 6000 4400 5200 4400 +Connection ~ 5200 4400 +Wire Wire Line + 6000 3900 5200 3900 +Connection ~ 5200 3900 +Wire Wire Line + 2750 4800 2750 5150 +Wire Wire Line + 2750 5150 4500 5150 +Connection ~ 2750 4800 +Wire Wire Line + 4800 5150 6300 5150 +Wire Wire Line + 6300 5150 6300 4800 +Connection ~ 6300 4800 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0E58AC +P 5200 1600 +F 0 "V1" V 5565 1600 50 0000 C CNN +F 1 "VSOURCE" V 5474 1600 50 0000 C CNN +F 2 "" H 5200 1600 50 0001 C CNN +F 3 "" H 5200 1600 50 0001 C CNN +F 4 "V" H 5200 1600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 5200 1600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5200 1600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5200 1600 + 0 -1 -1 0 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B0E5C5B +P 5750 1750 +F 0 "#PWR03" H 5750 1500 50 0001 C CNN +F 1 "GND" H 5755 1577 50 0000 C CNN +F 2 "" H 5750 1750 50 0001 C CNN +F 3 "" H 5750 1750 50 0001 C CNN + 1 5750 1750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 1600 4650 1600 +Wire Wire Line + 4650 1600 4650 2200 +Connection ~ 4650 2200 +Wire Wire Line + 4650 2200 5200 2200 +Wire Wire Line + 5500 1600 5750 1600 +Wire Wire Line + 5750 1600 5750 1750 +$Comp +L power:GND #PWR01 +U 1 1 5B0E6585 +P 4700 4450 +F 0 "#PWR01" H 4700 4200 50 0001 C CNN +F 1 "GND" H 4705 4277 50 0000 C CNN +F 2 "" H 4700 4450 50 0001 C CNN +F 3 "" H 4700 4450 50 0001 C CNN + 1 4700 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 4450 4700 4400 +Connection ~ 4700 4400 +Wire Wire Line + 4700 4400 4150 4400 +$Comp +L power:GND #PWR02 +U 1 1 5B0E6DFB +P 4750 4850 +F 0 "#PWR02" H 4750 4600 50 0001 C CNN +F 1 "GND" H 4755 4677 50 0000 C CNN +F 2 "" H 4750 4850 50 0001 C CNN +F 3 "" H 4750 4850 50 0001 C CNN + 1 4750 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 4850 4750 4800 +Connection ~ 4750 4800 +Wire Wire Line + 4750 4800 4800 4800 +Text GLabel 6750 2400 0 50 Output ~ 0 +out +Wire Wire Line + 6750 2400 6900 2400 +Wire Wire Line + 6900 2400 6900 2200 +Wire Wire Line + 6900 2200 6300 2200 +Wire Wire Line + 6300 2200 6300 2550 +Connection ~ 6300 2550 +$Comp +L Transistor_BJT:BC548 Q1 +U 1 1 5B0FCDD5 +P 5100 3200 +F 0 "Q1" H 5291 3246 50 0000 L CNN +F 1 "BC548" H 5291 3155 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 5300 3125 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 5100 3200 50 0001 L CNN +F 4 "Q" H 5100 3200 50 0001 C CNN "Spice_Primitive" +F 5 "Q2N2222" H 5100 3200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5100 3200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Rc_Phase_Shift_Oscillator_By_Ms_Rohini.n,_Parkavi.k/NPN.lib" H 5100 3200 50 0001 C CNN "Spice_Lib_File" + 1 5100 3200 + 1 0 0 -1 +$EndComp +Text Notes 6900 3900 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/high pass filter with opamp/ad8051.lib b/analog circuits/high pass filter with opamp/ad8051.lib new file mode 100644 index 0000000..20ac791 --- /dev/null +++ b/analog circuits/high pass filter with opamp/ad8051.lib @@ -0,0 +1,112 @@ +* AD8051 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Single 110 MHz rail-to-rail op amp - 3V +* Developed by: JCH / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (09/1998) +* Copyright 1998, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* CMRR IS NOT MODELED +* +* Parameters modeled include: +* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) +* +* END Notes +* +* Node assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8051 1 2 99 50 45 +* +* INPUT STAGE +* +Q1 4 3 5 QPI +Q2 6 2 7 QPI +RC1 50 4 20.5k +RC2 50 6 20.5k +RE1 5 8 5k +RE2 7 8 5k +EOS 3 1 POLY(1) 53 98 1.7E-3 1 +IOS 1 2 0.1u +FNOI1 1 0 VMEAS2 1E-4 +FNOI2 2 0 VMEAS2 1E-4 + +CPAR1 3 50 1.7p +CPAR2 2 50 1.7p +VCMH1 99 9 1 +VCMH2 99 10 1 +D1 5 9 DX +D2 7 10 DX +IBIAS 99 8 73u +* +* INTERNAL VOLTAGE REFERENCE +* +EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 +EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 +GREF2 97 0 97 0 1E-6 +* +*VOLTAGE NOISE STAGE +* +DN1 51 52 DNOI1 +VN1 51 98 0.61 +VMEAS 52 98 0 +RNOI1 52 98 6.5E-3 + +H1 53 98 VMEAS 1 +RNOI2 53 98 1 +* +*CURRENT NOISE STAGE +* +DN2 61 62 DNOI2 +VN2 61 98 0.545 +VMEAS2 62 98 0 +RNOI3 62 98 2E-4 +* +* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz +* +G1 98 20 4 6 1E-3 +RP1 98 20 550 +CP1 98 20 3p +* +* GAIN STAGE WITH DOMINANT POLE +* +G4 98 30 20 98 2.6E-3 +RG1 30 98 155k +CF1 30 45 13.5p +D5 31 99 DX +D6 50 32 DX +V1 31 30 0.6 +V2 30 32 0.6 +* +* OUTPUT STAGE +* +Q3 45 42 99 QPOX +Q4 45 44 50 QNOX +EO3 99 42 POLY(1) 98 30 0.7175 0.5 +EO4 44 50 POLY(1) 30 98 0.7355 0.5 +* +* MODELS +* +.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) +.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) +.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) +.MODEL DX D(IS=1E-16) +.MODEL DZ D(IS=1E-14,BV=6.6) +.MODEL DNOI1 D(KF=9E-10) +.MODEL DNOI2 D(KF=1E-8) +.ENDS AD8051 + + + + diff --git a/analog circuits/high pass filter with opamp/high pass filter with opamp-cache.lib b/analog circuits/high pass filter with opamp/high pass filter with opamp-cache.lib new file mode 100644 index 0000000..a6e6634 --- /dev/null +++ b/analog circuits/high pass filter with opamp/high pass filter with opamp-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VSS +# +DEF power:VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VSS" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sallen_key_schlib:Generic_Opamp +# +DEF sallen_key_schlib:Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "sallen_key_schlib:Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/high pass filter with opamp/high pass filter with opamp.bak b/analog circuits/high pass filter with opamp/high pass filter with opamp.bak new file mode 100644 index 0000000..31941ee --- /dev/null +++ b/analog circuits/high pass filter with opamp/high pass filter with opamp.bak @@ -0,0 +1,270 @@ +EESchema Schematic File Version 4 +LIBS:high pass filter with opamp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0C3012 +P 3050 4100 +F 0 "V1" H 3278 4146 50 0000 L CNN +F 1 "VSOURCE" H 3278 4055 50 0000 L CNN +F 2 "" H 3050 4100 50 0001 C CNN +F 3 "" H 3050 4100 50 0001 C CNN +F 4 "V" H 3050 4100 50 0001 C CNN "Spice_Primitive" +F 5 "ac 5 0" H 3050 4100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3050 4100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3050 4100 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0C32D3 +P 3700 3700 +F 0 "C1" V 3448 3700 50 0000 C CNN +F 1 "10n" V 3539 3700 50 0000 C CNN +F 2 "" H 3738 3550 50 0001 C CNN +F 3 "~" H 3700 3700 50 0001 C CNN + 1 3700 3700 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0C3340 +P 4000 4100 +F 0 "R1" H 4070 4146 50 0000 L CNN +F 1 "1k" H 4070 4055 50 0000 L CNN +F 2 "" V 3930 4100 50 0001 C CNN +F 3 "~" H 4000 4100 50 0001 C CNN + 1 4000 4100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR02 +U 1 1 5B0C33C3 +P 4000 4650 +F 0 "#PWR02" H 4000 4400 50 0001 C CNN +F 1 "GND" H 4005 4477 50 0000 C CNN +F 2 "" H 4000 4650 50 0001 C CNN +F 3 "" H 4000 4650 50 0001 C CNN + 1 4000 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 3800 3050 3700 +Wire Wire Line + 3050 3700 3550 3700 +Wire Wire Line + 3850 3700 4000 3700 +Wire Wire Line + 4000 3950 4000 3700 +Connection ~ 4000 3700 +Wire Wire Line + 4000 3700 5250 3700 +Wire Wire Line + 4000 4650 4000 4250 +$Comp +L power:GND #PWR01 +U 1 1 5B0C3470 +P 3050 4750 +F 0 "#PWR01" H 3050 4500 50 0001 C CNN +F 1 "GND" H 3055 4577 50 0000 C CNN +F 2 "" H 3050 4750 50 0001 C CNN +F 3 "" H 3050 4750 50 0001 C CNN + 1 3050 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 4750 3050 4400 +$Comp +L Device:R R3 +U 1 1 5B0C34C9 +P 6200 2950 +F 0 "R3" V 5993 2950 50 0000 C CNN +F 1 "9k" V 6084 2950 50 0000 C CNN +F 2 "" V 6130 2950 50 0001 C CNN +F 3 "~" H 6200 2950 50 0001 C CNN + 1 6200 2950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0C352B +P 4600 3100 +F 0 "R2" V 4393 3100 50 0000 C CNN +F 1 "3k" V 4484 3100 50 0000 C CNN +F 2 "" V 4530 3100 50 0001 C CNN +F 3 "~" H 4600 3100 50 0001 C CNN + 1 4600 3100 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B0C35A7 +P 4400 3300 +F 0 "#PWR03" H 4400 3050 50 0001 C CNN +F 1 "GND" H 4405 3127 50 0000 C CNN +F 2 "" H 4400 3300 50 0001 C CNN +F 3 "" H 4400 3300 50 0001 C CNN + 1 4400 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 3600 6550 3600 +Wire Wire Line + 6550 3600 6550 2950 +Wire Wire Line + 6550 2950 6350 2950 +Wire Wire Line + 6050 2950 5100 2950 +Wire Wire Line + 5100 2950 5100 3100 +Wire Wire Line + 5100 3500 5250 3500 +Wire Wire Line + 4750 3100 5100 3100 +Connection ~ 5100 3100 +Wire Wire Line + 5100 3100 5100 3500 +Wire Wire Line + 4450 3100 4400 3100 +Wire Wire Line + 4400 3100 4400 3300 +$Comp +L power:VSS #PWR05 +U 1 1 5B0C38A4 +P 6000 3250 +F 0 "#PWR05" H 6000 3100 50 0001 C CNN +F 1 "VSS" H 6017 3423 50 0000 C CNN +F 2 "" H 6000 3250 50 0001 C CNN +F 3 "" H 6000 3250 50 0001 C CNN + 1 6000 3250 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B0C3925 +P 5850 4000 +F 0 "#PWR04" H 5850 3850 50 0001 C CNN +F 1 "VDD" H 5867 4173 50 0000 C CNN +F 2 "" H 5850 4000 50 0001 C CNN +F 3 "" H 5850 4000 50 0001 C CNN + 1 5850 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6000 3300 6000 3250 +Wire Wire Line + 5450 4000 5450 3900 +Wire Wire Line + 6000 3300 5450 3300 +Wire Wire Line + 5450 4000 5850 4000 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0C4695 +P 8500 3000 +F 0 "V2" H 8728 3046 50 0000 L CNN +F 1 "VSOURCE" H 8728 2955 50 0000 L CNN +F 2 "" H 8500 3000 50 0001 C CNN +F 3 "" H 8500 3000 50 0001 C CNN +F 4 "V" H 8500 3000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 8500 3000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8500 3000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8500 3000 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0C46DE +P 8500 3950 +F 0 "V3" H 8728 3996 50 0000 L CNN +F 1 "VSOURCE" H 8728 3905 50 0000 L CNN +F 2 "" H 8500 3950 50 0001 C CNN +F 3 "" H 8500 3950 50 0001 C CNN +F 4 "V" H 8500 3950 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 8500 3950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8500 3950 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8500 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 3650 8500 3450 +$Comp +L power:GND #PWR06 +U 1 1 5B0C4942 +P 7700 3550 +F 0 "#PWR06" H 7700 3300 50 0001 C CNN +F 1 "GND" H 7705 3377 50 0000 C CNN +F 2 "" H 7700 3550 50 0001 C CNN +F 3 "" H 7700 3550 50 0001 C CNN + 1 7700 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 3550 7700 3450 +Wire Wire Line + 7700 3450 8500 3450 +Connection ~ 8500 3450 +Wire Wire Line + 8500 3450 8500 3300 +$Comp +L power:VDD #PWR07 +U 1 1 5B0C4BE8 +P 8500 2550 +F 0 "#PWR07" H 8500 2400 50 0001 C CNN +F 1 "VDD" H 8517 2723 50 0000 C CNN +F 2 "" H 8500 2550 50 0001 C CNN +F 3 "" H 8500 2550 50 0001 C CNN + 1 8500 2550 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR08 +U 1 1 5B0C4C77 +P 8700 4550 +F 0 "#PWR08" H 8700 4400 50 0001 C CNN +F 1 "VSS" H 8717 4723 50 0000 C CNN +F 2 "" H 8700 4550 50 0001 C CNN +F 3 "" H 8700 4550 50 0001 C CNN + 1 8700 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 2700 8500 2550 +Wire Wire Line + 8500 4250 8500 4550 +Wire Wire Line + 8500 4550 8700 4550 +$Comp +L Amplifier_Operational:AD8620 U1 +U 1 1 5B0C5383 +P 5550 3600 +F 0 "U1" H 5891 3646 50 0000 L CNN +F 1 "AD8620" H 5891 3555 50 0000 L CNN +F 2 "" H 5550 3600 50 0001 C CNN +F 3 "http://www.analog.com/media/en/technical-documentation/data-sheets/AD8610_8620.pdf" H 5550 3600 50 0001 C CNN + 1 5550 3600 + 1 0 0 -1 +$EndComp +Text GLabel 6850 3850 0 50 Output ~ 0 +out +Wire Wire Line + 6850 3850 6950 3850 +Wire Wire Line + 6950 3850 6950 3600 +Wire Wire Line + 6950 3600 6550 3600 +Connection ~ 6550 3600 +$EndSCHEMATC diff --git a/analog circuits/high pass filter with opamp/high pass filter with opamp.cir b/analog circuits/high pass filter with opamp/high pass filter with opamp.cir new file mode 100644 index 0000000..cd8f5ab --- /dev/null +++ b/analog circuits/high pass filter with opamp/high pass filter with opamp.cir @@ -0,0 +1,12 @@ +.title KiCad schematic +.include "/home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/ad8051.lib" +V1 Net-_C1-Pad2_ GND ac 5 0 +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10n +R1 Net-_C1-Pad1_ GND 1k +R3 out Net-_R2-Pad1_ 9k +R2 Net-_R2-Pad1_ GND 3k +V2 VDD GND dc 15 +V3 GND VSS dc 15 +XU1 Net-_C1-Pad1_ Net-_R2-Pad1_ VDD VSS out AD8051 +.ac dec 10 1 1meg +.end diff --git a/analog circuits/high pass filter with opamp/high pass filter with opamp.kicad_pcb b/analog circuits/high pass filter with opamp/high pass filter with opamp.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/high pass filter with opamp/high pass filter with opamp.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/high pass filter with opamp/high pass filter with opamp.pro b/analog circuits/high pass filter with opamp/high pass filter with opamp.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/high pass filter with opamp/high pass filter with opamp.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/high pass filter with opamp/high pass filter with opamp.sch b/analog circuits/high pass filter with opamp/high pass filter with opamp.sch new file mode 100644 index 0000000..7b4de44 --- /dev/null +++ b/analog circuits/high pass filter with opamp/high pass filter with opamp.sch @@ -0,0 +1,276 @@ +EESchema Schematic File Version 4 +LIBS:high pass filter with opamp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0C3012 +P 3050 4100 +F 0 "V1" H 3278 4146 50 0000 L CNN +F 1 "VSOURCE" H 3278 4055 50 0000 L CNN +F 2 "" H 3050 4100 50 0001 C CNN +F 3 "" H 3050 4100 50 0001 C CNN +F 4 "V" H 3050 4100 50 0001 C CNN "Spice_Primitive" +F 5 "ac 5 0" H 3050 4100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3050 4100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3050 4100 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0C32D3 +P 3700 3700 +F 0 "C1" V 3448 3700 50 0000 C CNN +F 1 "10n" V 3539 3700 50 0000 C CNN +F 2 "" H 3738 3550 50 0001 C CNN +F 3 "~" H 3700 3700 50 0001 C CNN + 1 3700 3700 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0C3340 +P 4000 4100 +F 0 "R1" H 4070 4146 50 0000 L CNN +F 1 "1k" H 4070 4055 50 0000 L CNN +F 2 "" V 3930 4100 50 0001 C CNN +F 3 "~" H 4000 4100 50 0001 C CNN + 1 4000 4100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR02 +U 1 1 5B0C33C3 +P 4000 4650 +F 0 "#PWR02" H 4000 4400 50 0001 C CNN +F 1 "GND" H 4005 4477 50 0000 C CNN +F 2 "" H 4000 4650 50 0001 C CNN +F 3 "" H 4000 4650 50 0001 C CNN + 1 4000 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 3800 3050 3700 +Wire Wire Line + 3050 3700 3550 3700 +Wire Wire Line + 3850 3700 4000 3700 +Wire Wire Line + 4000 3950 4000 3700 +Connection ~ 4000 3700 +Wire Wire Line + 4000 3700 5250 3700 +Wire Wire Line + 4000 4650 4000 4250 +$Comp +L power:GND #PWR01 +U 1 1 5B0C3470 +P 3050 4750 +F 0 "#PWR01" H 3050 4500 50 0001 C CNN +F 1 "GND" H 3055 4577 50 0000 C CNN +F 2 "" H 3050 4750 50 0001 C CNN +F 3 "" H 3050 4750 50 0001 C CNN + 1 3050 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 4750 3050 4400 +$Comp +L Device:R R3 +U 1 1 5B0C34C9 +P 6200 2950 +F 0 "R3" V 5993 2950 50 0000 C CNN +F 1 "9k" V 6084 2950 50 0000 C CNN +F 2 "" V 6130 2950 50 0001 C CNN +F 3 "~" H 6200 2950 50 0001 C CNN + 1 6200 2950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0C352B +P 4600 3100 +F 0 "R2" V 4393 3100 50 0000 C CNN +F 1 "3k" V 4484 3100 50 0000 C CNN +F 2 "" V 4530 3100 50 0001 C CNN +F 3 "~" H 4600 3100 50 0001 C CNN + 1 4600 3100 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B0C35A7 +P 4400 3300 +F 0 "#PWR03" H 4400 3050 50 0001 C CNN +F 1 "GND" H 4405 3127 50 0000 C CNN +F 2 "" H 4400 3300 50 0001 C CNN +F 3 "" H 4400 3300 50 0001 C CNN + 1 4400 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 3600 6550 3600 +Wire Wire Line + 6550 3600 6550 2950 +Wire Wire Line + 6550 2950 6350 2950 +Wire Wire Line + 6050 2950 5100 2950 +Wire Wire Line + 5100 2950 5100 3100 +Wire Wire Line + 5100 3500 5250 3500 +Wire Wire Line + 4750 3100 5100 3100 +Connection ~ 5100 3100 +Wire Wire Line + 5100 3100 5100 3500 +Wire Wire Line + 4450 3100 4400 3100 +Wire Wire Line + 4400 3100 4400 3300 +$Comp +L power:VSS #PWR05 +U 1 1 5B0C38A4 +P 6000 3250 +F 0 "#PWR05" H 6000 3100 50 0001 C CNN +F 1 "VSS" H 6017 3423 50 0000 C CNN +F 2 "" H 6000 3250 50 0001 C CNN +F 3 "" H 6000 3250 50 0001 C CNN + 1 6000 3250 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B0C3925 +P 5850 4000 +F 0 "#PWR04" H 5850 3850 50 0001 C CNN +F 1 "VDD" H 5867 4173 50 0000 C CNN +F 2 "" H 5850 4000 50 0001 C CNN +F 3 "" H 5850 4000 50 0001 C CNN + 1 5850 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6000 3300 6000 3250 +Wire Wire Line + 5450 4000 5450 3900 +Wire Wire Line + 6000 3300 5450 3300 +Wire Wire Line + 5450 4000 5850 4000 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B0C4695 +P 8500 3000 +F 0 "V2" H 8728 3046 50 0000 L CNN +F 1 "VSOURCE" H 8728 2955 50 0000 L CNN +F 2 "" H 8500 3000 50 0001 C CNN +F 3 "" H 8500 3000 50 0001 C CNN +F 4 "V" H 8500 3000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 8500 3000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8500 3000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8500 3000 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B0C46DE +P 8500 3950 +F 0 "V3" H 8728 3996 50 0000 L CNN +F 1 "VSOURCE" H 8728 3905 50 0000 L CNN +F 2 "" H 8500 3950 50 0001 C CNN +F 3 "" H 8500 3950 50 0001 C CNN +F 4 "V" H 8500 3950 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 8500 3950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8500 3950 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8500 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 3650 8500 3450 +$Comp +L power:GND #PWR06 +U 1 1 5B0C4942 +P 7700 3550 +F 0 "#PWR06" H 7700 3300 50 0001 C CNN +F 1 "GND" H 7705 3377 50 0000 C CNN +F 2 "" H 7700 3550 50 0001 C CNN +F 3 "" H 7700 3550 50 0001 C CNN + 1 7700 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 3550 7700 3450 +Wire Wire Line + 7700 3450 8500 3450 +Connection ~ 8500 3450 +Wire Wire Line + 8500 3450 8500 3300 +$Comp +L power:VDD #PWR07 +U 1 1 5B0C4BE8 +P 8500 2550 +F 0 "#PWR07" H 8500 2400 50 0001 C CNN +F 1 "VDD" H 8517 2723 50 0000 C CNN +F 2 "" H 8500 2550 50 0001 C CNN +F 3 "" H 8500 2550 50 0001 C CNN + 1 8500 2550 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR08 +U 1 1 5B0C4C77 +P 8700 4550 +F 0 "#PWR08" H 8700 4400 50 0001 C CNN +F 1 "VSS" H 8717 4723 50 0000 C CNN +F 2 "" H 8700 4550 50 0001 C CNN +F 3 "" H 8700 4550 50 0001 C CNN + 1 8700 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 2700 8500 2550 +Wire Wire Line + 8500 4250 8500 4550 +Wire Wire Line + 8500 4550 8700 4550 +Text GLabel 6850 3850 0 50 Output ~ 0 +out +Wire Wire Line + 6850 3850 6950 3850 +Wire Wire Line + 6950 3850 6950 3600 +Wire Wire Line + 6950 3600 6550 3600 +Connection ~ 6550 3600 +$Comp +L sallen_key_schlib:Generic_Opamp U1 +U 1 1 5B31CA71 +P 5550 3600 +F 0 "U1" H 5550 3122 50 0000 C CNN +F 1 "Generic_Opamp" H 5550 3213 50 0000 C CNN +F 2 "" H 5450 3500 50 0000 C CNN +F 3 "" H 5550 3600 50 0000 C CNN +F 4 "X" H 5550 3600 50 0001 C CNN "Spice_Primitive" +F 5 "AD8051" H 5550 3600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 3600 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/ad8051.lib" H 5550 3600 50 0001 C CNN "Spice_Lib_File" + 1 5550 3600 + 1 0 0 1 +$EndComp +Text Notes 6150 5050 0 50 ~ 0 +.ac dec 10 1 1meg +$EndSCHEMATC diff --git a/analog circuits/high pass filter with opamp/sallen_key_schlib.lib b/analog circuits/high pass filter with opamp/sallen_key_schlib.lib new file mode 100644 index 0000000..dc98765 --- /dev/null +++ b/analog circuits/high pass filter with opamp/sallen_key_schlib.lib @@ -0,0 +1,121 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp +# +DEF Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VDD +# +DEF VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS +# +DEF VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/high pass filter with opamp/sym-lib-table b/analog circuits/high pass filter with opamp/sym-lib-table new file mode 100644 index 0000000..fc4d1f2 --- /dev/null +++ b/analog circuits/high pass filter with opamp/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sallen_key_schlib)(type Legacy)(uri /home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/sallen_key_schlib.lib)(options "")(descr "")) +) diff --git a/analog circuits/libs/NPN.lib b/analog circuits/libs/NPN.lib new file mode 100644 index 0000000..6509fe7 --- /dev/null +++ b/analog circuits/libs/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/analog circuits/libs/ZenerD1N750.lib b/analog circuits/libs/ZenerD1N750.lib new file mode 100755 index 0000000..890c37f --- /dev/null +++ b/analog circuits/libs/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/analog circuits/libs/ad8051.lib b/analog circuits/libs/ad8051.lib new file mode 100644 index 0000000..20ac791 --- /dev/null +++ b/analog circuits/libs/ad8051.lib @@ -0,0 +1,112 @@ +* AD8051 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Single 110 MHz rail-to-rail op amp - 3V +* Developed by: JCH / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (09/1998) +* Copyright 1998, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* CMRR IS NOT MODELED +* +* Parameters modeled include: +* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) +* +* END Notes +* +* Node assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8051 1 2 99 50 45 +* +* INPUT STAGE +* +Q1 4 3 5 QPI +Q2 6 2 7 QPI +RC1 50 4 20.5k +RC2 50 6 20.5k +RE1 5 8 5k +RE2 7 8 5k +EOS 3 1 POLY(1) 53 98 1.7E-3 1 +IOS 1 2 0.1u +FNOI1 1 0 VMEAS2 1E-4 +FNOI2 2 0 VMEAS2 1E-4 + +CPAR1 3 50 1.7p +CPAR2 2 50 1.7p +VCMH1 99 9 1 +VCMH2 99 10 1 +D1 5 9 DX +D2 7 10 DX +IBIAS 99 8 73u +* +* INTERNAL VOLTAGE REFERENCE +* +EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 +EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 +GREF2 97 0 97 0 1E-6 +* +*VOLTAGE NOISE STAGE +* +DN1 51 52 DNOI1 +VN1 51 98 0.61 +VMEAS 52 98 0 +RNOI1 52 98 6.5E-3 + +H1 53 98 VMEAS 1 +RNOI2 53 98 1 +* +*CURRENT NOISE STAGE +* +DN2 61 62 DNOI2 +VN2 61 98 0.545 +VMEAS2 62 98 0 +RNOI3 62 98 2E-4 +* +* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz +* +G1 98 20 4 6 1E-3 +RP1 98 20 550 +CP1 98 20 3p +* +* GAIN STAGE WITH DOMINANT POLE +* +G4 98 30 20 98 2.6E-3 +RG1 30 98 155k +CF1 30 45 13.5p +D5 31 99 DX +D6 50 32 DX +V1 31 30 0.6 +V2 30 32 0.6 +* +* OUTPUT STAGE +* +Q3 45 42 99 QPOX +Q4 45 44 50 QNOX +EO3 99 42 POLY(1) 98 30 0.7175 0.5 +EO4 44 50 POLY(1) 30 98 0.7355 0.5 +* +* MODELS +* +.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) +.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) +.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) +.MODEL DX D(IS=1E-16) +.MODEL DZ D(IS=1E-14,BV=6.6) +.MODEL DNOI1 D(KF=9E-10) +.MODEL DNOI2 D(KF=1E-8) +.ENDS AD8051 + + + + diff --git a/analog circuits/libs/fzt1049a.lib b/analog circuits/libs/fzt1049a.lib new file mode 100644 index 0000000..9aed971 --- /dev/null +++ b/analog circuits/libs/fzt1049a.lib @@ -0,0 +1 @@ +.model FZT1049A NPN IS=1.5E-12 NF=1.0 BF=600 IKF=7.5 VAF=100 ISE=0.9E-13 NE=1.25 NR=1.0 BR=150 IKR=3 VAR=15 ISC=5.0E-13 NC=1.76 RB=0.1 RE=0.018 RC=0.007 CJC=136E-12 CJE=550E-12 MJC=0.352 MJE=0.36 VJC=0.554 VJE=0.726 TF=400E-12 TR=6.9E-9
\ No newline at end of file diff --git a/analog circuits/libs/laser_driver_schlib.lib b/analog circuits/libs/laser_driver_schlib.lib new file mode 100644 index 0000000..f44ec29 --- /dev/null +++ b/analog circuits/libs/laser_driver_schlib.lib @@ -0,0 +1,166 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp +# +DEF Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# LED +# +DEF LED D 0 40 Y N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "LED" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + LED-3MM + LED-5MM + LED-10MM + LED-0603 + LED-0805 + LED-1206 + LEDV +$ENDFPLIST +DRAW +P 2 0 1 0 -50 50 -50 -50 N +P 3 0 1 0 -80 -25 -125 -65 -120 -40 N +P 3 0 1 0 -65 -40 -110 -80 -105 -55 N +P 3 0 1 0 50 50 -50 0 50 -50 F +X K 1 -200 0 150 R 40 40 1 1 P +X A 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# Q_NPN_CBE +# +DEF Q_NPN_CBE Q 0 0 Y N 1 F N +F0 "Q" 300 50 50 H V R CNN +F1 "Q_NPN_CBE" 600 -50 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VDD +# +DEF VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS +# +DEF VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/libs/newopamp.cir b/analog circuits/libs/newopamp.cir new file mode 100644 index 0000000..425ef47 --- /dev/null +++ b/analog circuits/libs/newopamp.cir @@ -0,0 +1,5 @@ +.SUBCKT OPAMP1 3 2 1 +RIN 1 2 10MEG +EGAIN 3 0 1 2 100K +.ENDS + diff --git a/analog circuits/libs/sallen_key_schlib.lib b/analog circuits/libs/sallen_key_schlib.lib new file mode 100644 index 0000000..dc98765 --- /dev/null +++ b/analog circuits/libs/sallen_key_schlib.lib @@ -0,0 +1,121 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp +# +DEF Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VDD +# +DEF VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS +# +DEF VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/monostable/monostable-cache.lib b/analog circuits/monostable/monostable-cache.lib new file mode 100644 index 0000000..3cf7927 --- /dev/null +++ b/analog circuits/monostable/monostable-cache.lib @@ -0,0 +1,167 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Amplifier_Operational:AD8620 +# +DEF Amplifier_Operational:AD8620 U 0 20 Y Y 3 L N +F0 "U" 0 200 50 H V L CNN +F1 "Amplifier_Operational:AD8620" 0 -200 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS LM358 AD8620 LMC6062 LMC6082 TL062 TL072 TL082 NE5532 SA5532 RC4558 RC4560 RC4580 LMV358 TS912 TSV912IDT TSV912IST TLC272 TLC277 MCP602 OPA2134 OPA2340 OPA2376xxD OPA2376xxDGK MC33078 MC33178 LM4562 OP249 OP275 ADA4075-2 MCP6002-xP MCP6002-xSN MCP6002-xMS LM7332 OPA2333xxD OPA2333xxDGK LMC6482 LT1492 LTC6081xMS8 LM6172 MCP6L92 NJM2043 NJM2114 NJM4556A NJM4558 NJM4559 NJM4560 NJM4580 NJM5532 ADA4807-2ARM OPA2691 LT6233 OPA2356xxD OPA2356xxDGK +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* + TO*99* + OnSemi*Micro8* + TSSOP*3x3mm*P0.65mm* + TSSOP*4.4x3mm*P0.65mm* + MSOP*3x3mm*P0.65mm* + SSOP*3.9x4.9mm*P0.635mm* + LFCSP*2x2mm*P0.5mm* + *SIP* + SOIC*5.3x6.2mm*P1.27mm* +$ENDFPLIST +DRAW +P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f +P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f +X ~ 1 300 0 100 L 50 50 1 1 O +X - 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diff --git a/analog circuits/monostable/monostable.cir b/analog circuits/monostable/monostable.cir new file mode 100644 index 0000000..4633076 --- /dev/null +++ b/analog circuits/monostable/monostable.cir @@ -0,0 +1,14 @@ +.title KiCad schematic +R2 Net-_C2-Pad2_ GND 10k +R1 Net-_R1-Pad1_ Net-_C2-Pad2_ 240k +R3 Net-_C1-Pad1_ GND 150k +C2 out Net-_C2-Pad2_ 0.03u +C1 Net-_C1-Pad1_ in 0.0001u +V2 in GND pulse(0 3 100n 1n 1n 20n 100n) +D1 GND Net-_C1-Pad1_ D +V1 GND Net-_R1-Pad1_ dc 12 +V3 VDD GND dc 15 +V4 GND VSS dc 15 +U1 out Net-_C1-Pad1_ Net-_C2-Pad2_ AD8620 +.tran 15p 300n +.end diff --git a/analog circuits/monostable/monostable.kicad_pcb b/analog circuits/monostable/monostable.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/monostable/monostable.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/monostable/monostable.pro b/analog circuits/monostable/monostable.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/monostable/monostable.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/monostable/monostable.sch b/analog circuits/monostable/monostable.sch new file mode 100644 index 0000000..6b12617 --- /dev/null +++ b/analog circuits/monostable/monostable.sch @@ -0,0 +1,332 @@ +EESchema Schematic File Version 4 +LIBS:monostable-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R2 +U 1 1 5B08D693 +P 3150 2900 +F 0 "R2" H 3220 2946 50 0000 L CNN +F 1 "10k" H 3220 2855 50 0000 L CNN +F 2 "" V 3080 2900 50 0001 C CNN +F 3 "~" H 3150 2900 50 0001 C CNN + 1 3150 2900 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B08D758 +P 3150 2050 +F 0 "R1" H 3220 2096 50 0000 L CNN +F 1 "240k" H 3220 2005 50 0000 L CNN +F 2 "" V 3080 2050 50 0001 C CNN +F 3 "~" H 3150 2050 50 0001 C CNN + 1 3150 2050 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B08D786 +P 5350 3100 +F 0 "R3" H 5420 3146 50 0000 L CNN +F 1 "150k" H 5420 3055 50 0000 L CNN +F 2 "" V 5280 3100 50 0001 C CNN +F 3 "~" H 5350 3100 50 0001 C CNN + 1 5350 3100 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B08D7C8 +P 6700 1850 +F 0 "C2" V 6448 1850 50 0000 C CNN +F 1 "0.03u" V 6539 1850 50 0000 C CNN +F 2 "" H 6738 1700 50 0001 C CNN +F 3 "~" H 6700 1850 50 0001 C CNN + 1 6700 1850 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B08D834 +P 5100 2550 +F 0 "C1" V 5250 2400 50 0000 C CNN +F 1 "0.0001u" V 5350 2450 50 0000 C CNN +F 2 "" H 5138 2400 50 0001 C CNN +F 3 "~" H 5100 2550 50 0001 C CNN + 1 5100 2550 + 0 1 1 0 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B08DAC0 +P 4400 3400 +F 0 "V2" H 4628 3446 50 0000 L CNN +F 1 "VSOURCE" H 4628 3355 50 0000 L CNN +F 2 "" H 4400 3400 50 0001 C CNN +F 3 "" H 4400 3400 50 0001 C CNN +F 4 "V" H 4400 3400 50 0001 C CNN "Spice_Primitive" +F 5 "pulse(0 3 100n 1n 1n 20n 100n)" H 4400 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4400 3400 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4400 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 2550 5350 2550 +$Comp +L power:GND #PWR01 +U 1 1 5B08DC9A +P 3150 3800 +F 0 "#PWR01" H 3150 3550 50 0001 C CNN +F 1 "GND" H 3155 3627 50 0000 C CNN +F 2 "" H 3150 3800 50 0001 C CNN +F 3 "" H 3150 3800 50 0001 C CNN + 1 3150 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG01 +U 1 1 5B08DCDA +P 3800 4000 +F 0 "#FLG01" H 3800 4075 50 0001 C CNN +F 1 "PWR_FLAG" H 3800 4174 50 0000 C CNN +F 2 "" H 3800 4000 50 0001 C CNN +F 3 "~" H 3800 4000 50 0001 C CNN + 1 3800 4000 + 1 0 0 -1 +$EndComp +$Comp +L Device:D D1 +U 1 1 5B08DD83 +P 5650 3100 +F 0 "D1" V 5604 3179 50 0000 L CNN +F 1 "D" V 5695 3179 50 0000 L CNN +F 2 "" H 5650 3100 50 0001 C CNN +F 3 "~" H 5650 3100 50 0001 C CNN +F 4 "D" H 5650 3100 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 5650 3100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5650 3100 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5650 3100 50 0001 C CNN "Spice_Node_Sequence" + 1 5650 3100 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 2950 5650 2550 +Connection ~ 5650 2550 +Wire Wire Line + 5650 2550 5750 2550 +Wire Wire Line + 5350 2950 5350 2550 +Connection ~ 5350 2550 +Wire Wire Line + 5350 2550 5650 2550 +Wire Wire Line + 4400 3700 4400 4000 +Wire Wire Line + 5350 3250 5350 3450 +Wire Wire Line + 5650 3250 5650 3450 +Wire Wire Line + 5650 3450 5350 3450 +Connection ~ 5350 3450 +Wire Wire Line + 5350 3450 5350 4000 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B08E08C +P 3150 1100 +F 0 "V1" H 3378 1146 50 0000 L CNN +F 1 "VSOURCE" H 3378 1055 50 0000 L CNN +F 2 "" H 3150 1100 50 0001 C CNN +F 3 "" H 3150 1100 50 0001 C CNN +F 4 "V" H 3150 1100 50 0001 C CNN "Spice_Primitive" +F 5 "dc 12" H 3150 1100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3150 1100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3150 1100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 4000 4400 4000 +Connection ~ 4400 4000 +Wire Wire Line + 3150 1900 3150 1400 +Wire Wire Line + 3150 2200 3150 2400 +Wire Wire Line + 4400 4000 5350 4000 +Wire Wire Line + 3150 3050 3150 3800 +Connection ~ 3150 2400 +Wire Wire Line + 3150 2400 3150 2750 +Wire Wire Line + 4400 2550 4400 3100 +$Comp +L power:GND #PWR02 +U 1 1 5B08EB5B +P 4000 800 +F 0 "#PWR02" H 4000 550 50 0001 C CNN +F 1 "GND" H 4005 627 50 0000 C CNN +F 2 "" H 4000 800 50 0001 C CNN +F 3 "" H 4000 800 50 0001 C CNN + 1 4000 800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 800 4000 800 +Wire Wire Line + 5750 1850 6550 1850 +Wire Wire Line + 6850 1850 7800 1850 +Wire Wire Line + 7800 1850 7800 2200 +Wire Wire Line + 7800 2450 6350 2450 +$Comp +L power:GND #PWR03 +U 1 1 5B08F52C +P 4400 4300 +F 0 "#PWR03" H 4400 4050 50 0001 C CNN +F 1 "GND" H 4405 4127 50 0000 C CNN +F 2 "" H 4400 4300 50 0001 C CNN +F 3 "" H 4400 4300 50 0001 C CNN + 1 4400 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4300 4400 4000 +Wire Wire Line + 3150 2400 5750 2400 +Text GLabel 8450 1850 0 50 Output ~ 0 +out +Wire Wire Line + 8450 1850 8450 2200 +Wire Wire Line + 8450 2200 7800 2200 +Connection ~ 7800 2200 +Wire Wire Line + 7800 2200 7800 2450 +Text GLabel 4450 2100 0 50 Input ~ 0 +in +Wire Wire Line + 4450 2100 4450 2550 +Wire Wire Line + 4400 2550 4450 2550 +Connection ~ 4450 2550 +Wire Wire Line + 4450 2550 4950 2550 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B331B7A +P 9400 1700 +F 0 "V3" H 9628 1746 50 0000 L CNN +F 1 "VSOURCE" H 9628 1655 50 0000 L CNN +F 2 "" H 9400 1700 50 0001 C CNN +F 3 "" H 9400 1700 50 0001 C CNN +F 4 "V" H 9400 1700 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 9400 1700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 9400 1700 50 0001 C CNN "Spice_Netlist_Enabled" + 1 9400 1700 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V4 +U 1 1 5B331BBD +P 9400 2600 +F 0 "V4" H 9628 2646 50 0000 L CNN +F 1 "VSOURCE" H 9628 2555 50 0000 L CNN +F 2 "" H 9400 2600 50 0001 C CNN +F 3 "" H 9400 2600 50 0001 C CNN +F 4 "V" H 9400 2600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 9400 2600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 9400 2600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 9400 2600 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0101 +U 1 1 5B331C64 +P 9400 1400 +F 0 "#PWR0101" H 9400 1250 50 0001 C CNN +F 1 "VDD" H 9417 1573 50 0000 C CNN +F 2 "" H 9400 1400 50 0001 C CNN +F 3 "" H 9400 1400 50 0001 C CNN + 1 9400 1400 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR0102 +U 1 1 5B331D28 +P 9750 3100 +F 0 "#PWR0102" H 9750 2950 50 0001 C CNN +F 1 "VSS" H 9767 3273 50 0000 C CNN +F 2 "" H 9750 3100 50 0001 C CNN +F 3 "" H 9750 3100 50 0001 C CNN + 1 9750 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 2900 9400 3100 +Wire Wire Line + 9400 3100 9750 3100 +$Comp +L power:GND #PWR0103 +U 1 1 5B332236 +P 9850 2250 +F 0 "#PWR0103" H 9850 2000 50 0001 C CNN +F 1 "GND" H 9855 2077 50 0000 C CNN +F 2 "" H 9850 2250 50 0001 C CNN +F 3 "" H 9850 2250 50 0001 C CNN + 1 9850 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 2300 9400 2250 +Wire Wire Line + 9850 2250 9400 2250 +Connection ~ 9400 2250 +Wire Wire Line + 9400 2250 9400 2000 +Wire Wire Line + 5750 1850 5750 2400 +Wire Wire Line + 6350 2450 6350 2600 +Wire Wire Line + 6350 2600 6500 2600 +Wire Wire Line + 6500 2600 6500 2850 +Wire Wire Line + 5900 2750 5900 2400 +Wire Wire Line + 5900 2400 5750 2400 +Connection ~ 5750 2400 +Wire Wire Line + 5750 2550 5750 2950 +Wire Wire Line + 5750 2950 5900 2950 +Text Notes 7750 4200 0 50 ~ 0 +.tran 15p 300n +$Comp +L Amplifier_Operational:AD8620 U1 +U 1 1 5B334902 +P 6200 2850 +F 0 "U1" H 6200 3217 50 0000 C CNN +F 1 "AD8620" H 6200 3126 50 0000 C CNN +F 2 "" H 6200 2850 50 0001 C CNN +F 3 "http://www.analog.com/media/en/technical-documentation/data-sheets/AD8610_8620.pdf" H 6200 2850 50 0001 C CNN + 1 6200 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/analog circuits/monostable/sym-lib-table b/analog circuits/monostable/sym-lib-table new file mode 100644 index 0000000..0bbcf1e --- /dev/null +++ b/analog circuits/monostable/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sallen_key_schlib)(type Legacy)(uri "/home/akshay/Desktop/analog circuits/libs/sallen_key_schlib.lib")(options "")(descr "")) +) diff --git a/analog circuits/peltz oscillator/fzt1049a.lib b/analog circuits/peltz oscillator/fzt1049a.lib new file mode 100644 index 0000000..9aed971 --- /dev/null +++ b/analog circuits/peltz oscillator/fzt1049a.lib @@ -0,0 +1 @@ +.model FZT1049A NPN IS=1.5E-12 NF=1.0 BF=600 IKF=7.5 VAF=100 ISE=0.9E-13 NE=1.25 NR=1.0 BR=150 IKR=3 VAR=15 ISC=5.0E-13 NC=1.76 RB=0.1 RE=0.018 RC=0.007 CJC=136E-12 CJE=550E-12 MJC=0.352 MJE=0.36 VJC=0.554 VJE=0.726 TF=400E-12 TR=6.9E-9
\ No newline at end of file diff --git a/analog circuits/peltz oscillator/laser_driver_schlib.lib b/analog circuits/peltz oscillator/laser_driver_schlib.lib new file mode 100644 index 0000000..f44ec29 --- /dev/null +++ b/analog circuits/peltz oscillator/laser_driver_schlib.lib @@ -0,0 +1,166 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp +# +DEF Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# LED +# +DEF LED D 0 40 Y N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "LED" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + LED-3MM + LED-5MM + LED-10MM + LED-0603 + LED-0805 + LED-1206 + LEDV +$ENDFPLIST +DRAW +P 2 0 1 0 -50 50 -50 -50 N +P 3 0 1 0 -80 -25 -125 -65 -120 -40 N +P 3 0 1 0 -65 -40 -110 -80 -105 -55 N +P 3 0 1 0 50 50 -50 0 50 -50 F +X K 1 -200 0 150 R 40 40 1 1 P +X A 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# Q_NPN_CBE +# +DEF Q_NPN_CBE Q 0 0 Y N 1 F N +F0 "Q" 300 50 50 H V R CNN +F1 "Q_NPN_CBE" 600 -50 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VDD +# +DEF VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS +# +DEF VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/peltz oscillator/peltz oscillator-cache.lib b/analog circuits/peltz oscillator/peltz oscillator-cache.lib new file mode 100644 index 0000000..d05309d --- /dev/null +++ b/analog circuits/peltz oscillator/peltz oscillator-cache.lib @@ -0,0 +1,111 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:L +# +DEF Device:L L 0 40 N N 1 F N +F0 "L" -50 0 50 V V C CNN +F1 "Device:L" 75 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Choke_* + *Coil* + Inductor_* + L_* +$ENDFPLIST +DRAW +A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 +A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 +A 0 25 25 -899 899 0 1 0 N 0 0 0 50 +A 0 75 25 -899 899 0 1 0 N 0 50 0 100 +X 1 1 0 150 50 D 50 50 1 1 P +X 2 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# laser_driver_schlib:Q_NPN_CBE +# +DEF laser_driver_schlib:Q_NPN_CBE Q 0 0 Y N 1 F N +F0 "Q" 300 50 50 H V R CNN +F1 "laser_driver_schlib:Q_NPN_CBE" 600 -50 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/peltz oscillator/peltz oscillator.bak b/analog circuits/peltz oscillator/peltz oscillator.bak new file mode 100644 index 0000000..63e3dea --- /dev/null +++ b/analog circuits/peltz oscillator/peltz oscillator.bak @@ -0,0 +1,176 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Transistor_BJT:BC548 Q1 +U 1 1 5B0EB9A9 +P 4500 4550 +F 0 "Q1" H 4690 4596 50 0000 L CNN +F 1 "BC548" H 4690 4505 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 4700 4475 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 4500 4550 50 0001 L CNN + 1 4500 4550 + -1 0 0 -1 +$EndComp +$Comp +L Transistor_BJT:BC548 Q2 +U 1 1 5B0EBA4B +P 6500 4550 +F 0 "Q2" H 6690 4596 50 0000 L CNN +F 1 "BC548" H 6690 4505 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6700 4475 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 6500 4550 50 0001 L CNN + 1 6500 4550 + -1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0EBB46 +P 3150 4500 +F 0 "V1" H 3378 4546 50 0000 L CNN +F 1 "VSOURCE" H 3378 4455 50 0000 L CNN +F 2 "" H 3150 4500 50 0001 C CNN +F 3 "" H 3150 4500 50 0001 C CNN + 1 3150 4500 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0EBB9C +P 4550 3650 +F 0 "R1" H 4620 3696 50 0000 L CNN +F 1 "200k" H 4620 3605 50 0000 L CNN +F 2 "" V 4480 3650 50 0001 C CNN +F 3 "~" H 4550 3650 50 0001 C CNN + 1 4550 3650 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0EBBE1 +P 5600 3650 +F 0 "C1" H 5715 3696 50 0000 L CNN +F 1 "10n" H 5715 3605 50 0000 L CNN +F 2 "" H 5638 3500 50 0001 C CNN +F 3 "~" H 5600 3650 50 0001 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0EBC51 +P 5100 3650 +F 0 "L1" H 5153 3696 50 0000 L CNN +F 1 "0.5m" H 5153 3605 50 0000 L CNN +F 2 "" H 5100 3650 50 0001 C CNN +F 3 "~" H 5100 3650 50 0001 C CNN + 1 5100 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 4200 3150 2900 +Wire Wire Line + 3150 2900 4400 2900 +Wire Wire Line + 4550 2900 4550 3500 +Wire Wire Line + 4400 4350 4400 2900 +Connection ~ 4400 2900 +Wire Wire Line + 4400 2900 4550 2900 +Wire Wire Line + 4550 2900 5100 2900 +Wire Wire Line + 5100 2900 5100 3500 +Connection ~ 4550 2900 +Wire Wire Line + 5100 2900 5600 2900 +Wire Wire Line + 5600 2900 5600 3500 +Connection ~ 5100 2900 +Wire Wire Line + 6700 4550 7000 4550 +Wire Wire Line + 7000 4550 7000 2900 +Wire Wire Line + 7000 2900 5600 2900 +Connection ~ 5600 2900 +Wire Wire Line + 4700 4550 4700 4150 +Wire Wire Line + 4700 4150 4550 4150 +Wire Wire Line + 4550 4150 4550 3800 +Wire Wire Line + 4550 3800 5100 3800 +Connection ~ 4550 3800 +Wire Wire Line + 5100 3800 5600 3800 +Connection ~ 5100 3800 +Wire Wire Line + 5600 3800 6400 3800 +Wire Wire Line + 6400 3800 6400 3950 +Connection ~ 5600 3800 +Wire Wire Line + 4400 4750 5400 4750 +$Comp +L Device:R R2 +U 1 1 5B0EC27B +P 5400 5100 +F 0 "R2" H 5470 5146 50 0000 L CNN +F 1 "50k" H 5470 5055 50 0000 L CNN +F 2 "" V 5330 5100 50 0001 C CNN +F 3 "~" H 5400 5100 50 0001 C CNN + 1 5400 5100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B0EC333 +P 5400 5450 +F 0 "#PWR01" H 5400 5200 50 0001 C CNN +F 1 "GND" H 5405 5277 50 0000 C CNN +F 2 "" H 5400 5450 50 0001 C CNN +F 3 "" H 5400 5450 50 0001 C CNN + 1 5400 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 4950 5400 4750 +Connection ~ 5400 4750 +Wire Wire Line + 5400 4750 6400 4750 +Wire Wire Line + 5400 5450 5400 5350 +Wire Wire Line + 5400 5350 3150 5350 +Wire Wire Line + 3150 5350 3150 4800 +Connection ~ 5400 5350 +Wire Wire Line + 5400 5350 5400 5250 +Text GLabel 7700 4050 0 50 Output ~ 0 +out +Wire Wire Line + 7700 4050 7800 4050 +Wire Wire Line + 7800 4050 7800 3950 +Wire Wire Line + 7800 3950 6400 3950 +Connection ~ 6400 3950 +Wire Wire Line + 6400 3950 6400 4350 +$EndSCHEMATC diff --git a/analog circuits/peltz oscillator/peltz oscillator.cir b/analog circuits/peltz oscillator/peltz oscillator.cir new file mode 100644 index 0000000..722eaee --- /dev/null +++ b/analog circuits/peltz oscillator/peltz oscillator.cir @@ -0,0 +1,11 @@ +.title KiCad schematic +.include "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" +V1 Net-_C1-Pad1_ GND dc 5 +R1 Net-_C1-Pad1_ out 200k +C1 Net-_C1-Pad1_ out 10n +L1 Net-_C1-Pad1_ out 0.5m +R2 Net-_Q1-Pad3_ GND 50k +Q1 Net-_C1-Pad1_ out Net-_Q1-Pad3_ FZT1049A +Q2 out Net-_C1-Pad1_ Net-_Q1-Pad3_ FZT1049A +.tran .25m 30m +.end diff --git a/analog circuits/peltz oscillator/peltz oscillator.kicad_pcb b/analog circuits/peltz oscillator/peltz oscillator.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/peltz oscillator/peltz oscillator.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/peltz oscillator/peltz oscillator.pro b/analog circuits/peltz oscillator/peltz oscillator.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/peltz oscillator/peltz oscillator.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/peltz oscillator/peltz oscillator.sch b/analog circuits/peltz oscillator/peltz oscillator.sch new file mode 100644 index 0000000..4786011 --- /dev/null +++ b/analog circuits/peltz oscillator/peltz oscillator.sch @@ -0,0 +1,190 @@ +EESchema Schematic File Version 4 +LIBS:peltz oscillator-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0EBB46 +P 3150 4500 +F 0 "V1" H 3378 4546 50 0000 L CNN +F 1 "VSOURCE" H 3378 4455 50 0000 L CNN +F 2 "" H 3150 4500 50 0001 C CNN +F 3 "" H 3150 4500 50 0001 C CNN +F 4 "V" H 3150 4500 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 3150 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3150 4500 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3150 4500 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0EBB9C +P 4550 3650 +F 0 "R1" H 4620 3696 50 0000 L CNN +F 1 "200k" H 4620 3605 50 0000 L CNN +F 2 "" V 4480 3650 50 0001 C CNN +F 3 "~" H 4550 3650 50 0001 C CNN + 1 4550 3650 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0EBBE1 +P 5600 3650 +F 0 "C1" H 5715 3696 50 0000 L CNN +F 1 "10n" H 5715 3605 50 0000 L CNN +F 2 "" H 5638 3500 50 0001 C CNN +F 3 "~" H 5600 3650 50 0001 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B0EBC51 +P 5100 3650 +F 0 "L1" H 5153 3696 50 0000 L CNN +F 1 "0.5m" H 5153 3605 50 0000 L CNN +F 2 "" H 5100 3650 50 0001 C CNN +F 3 "~" H 5100 3650 50 0001 C CNN + 1 5100 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 4200 3150 2900 +Wire Wire Line + 3150 2900 4400 2900 +Wire Wire Line + 4550 2900 4550 3500 +Wire Wire Line + 4400 4350 4400 2900 +Connection ~ 4400 2900 +Wire Wire Line + 4400 2900 4550 2900 +Wire Wire Line + 4550 2900 5100 2900 +Wire Wire Line + 5100 2900 5100 3500 +Connection ~ 4550 2900 +Wire Wire Line + 5100 2900 5600 2900 +Wire Wire Line + 5600 2900 5600 3500 +Connection ~ 5100 2900 +Wire Wire Line + 6700 4550 7000 4550 +Wire Wire Line + 7000 4550 7000 2900 +Wire Wire Line + 7000 2900 5600 2900 +Connection ~ 5600 2900 +Wire Wire Line + 4700 4550 4700 4150 +Wire Wire Line + 4700 4150 4550 4150 +Wire Wire Line + 4550 4150 4550 3800 +Wire Wire Line + 4550 3800 5100 3800 +Connection ~ 4550 3800 +Wire Wire Line + 5100 3800 5600 3800 +Connection ~ 5100 3800 +Wire Wire Line + 5600 3800 6400 3800 +Wire Wire Line + 6400 3800 6400 3950 +Connection ~ 5600 3800 +Wire Wire Line + 4400 4750 5400 4750 +$Comp +L Device:R R2 +U 1 1 5B0EC27B +P 5400 5100 +F 0 "R2" H 5470 5146 50 0000 L CNN +F 1 "50k" H 5470 5055 50 0000 L CNN +F 2 "" V 5330 5100 50 0001 C CNN +F 3 "~" H 5400 5100 50 0001 C CNN + 1 5400 5100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B0EC333 +P 5400 5450 +F 0 "#PWR01" H 5400 5200 50 0001 C CNN +F 1 "GND" H 5405 5277 50 0000 C CNN +F 2 "" H 5400 5450 50 0001 C CNN +F 3 "" H 5400 5450 50 0001 C CNN + 1 5400 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 4950 5400 4750 +Connection ~ 5400 4750 +Wire Wire Line + 5400 4750 6400 4750 +Wire Wire Line + 5400 5450 5400 5350 +Wire Wire Line + 5400 5350 3150 5350 +Wire Wire Line + 3150 5350 3150 4800 +Connection ~ 5400 5350 +Wire Wire Line + 5400 5350 5400 5250 +Text GLabel 7700 4050 0 50 Output ~ 0 +out +Wire Wire Line + 7700 4050 7800 4050 +Wire Wire Line + 7800 4050 7800 3950 +Wire Wire Line + 7800 3950 6400 3950 +Connection ~ 6400 3950 +Wire Wire Line + 6400 3950 6400 4350 +Text Notes 7750 5400 0 50 ~ 0 +.tran .25m 30m +$Comp +L laser_driver_schlib:Q_NPN_CBE Q1 +U 1 1 5B30BE28 +P 4500 4550 +F 0 "Q1" H 4690 4596 50 0000 L CNN +F 1 "Q_NPN_CBE" H 4690 4505 50 0000 L CNN +F 2 "" H 4700 4650 29 0000 C CNN +F 3 "" H 4500 4550 60 0000 C CNN +F 4 "Q" H 4500 4550 50 0001 C CNN "Spice_Primitive" +F 5 "FZT1049A" H 4500 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4500 4550 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" H 4500 4550 50 0001 C CNN "Spice_Lib_File" + 1 4500 4550 + -1 0 0 -1 +$EndComp +$Comp +L laser_driver_schlib:Q_NPN_CBE Q2 +U 1 1 5B30C950 +P 6500 4550 +F 0 "Q2" H 6690 4596 50 0000 L CNN +F 1 "Q_NPN_CBE" H 6690 4505 50 0000 L CNN +F 2 "" H 6700 4650 29 0000 C CNN +F 3 "" H 6500 4550 60 0000 C CNN +F 4 "Q" H 6500 4550 50 0001 C CNN "Spice_Primitive" +F 5 "FZT1049A" H 6500 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6500 4550 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" H 6500 4550 50 0001 C CNN "Spice_Lib_File" + 1 6500 4550 + -1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/analog circuits/peltz oscillator/sym-lib-table b/analog circuits/peltz oscillator/sym-lib-table new file mode 100644 index 0000000..272ef44 --- /dev/null +++ b/analog circuits/peltz oscillator/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name laser_driver_schlib)(type Legacy)(uri /home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/laser_driver_schlib.lib)(options "")(descr "")) +) diff --git a/analog circuits/rc coupled amplifier/fzt1049a.lib b/analog circuits/rc coupled amplifier/fzt1049a.lib new file mode 100644 index 0000000..9aed971 --- /dev/null +++ b/analog circuits/rc coupled amplifier/fzt1049a.lib @@ -0,0 +1 @@ +.model FZT1049A NPN IS=1.5E-12 NF=1.0 BF=600 IKF=7.5 VAF=100 ISE=0.9E-13 NE=1.25 NR=1.0 BR=150 IKR=3 VAR=15 ISC=5.0E-13 NC=1.76 RB=0.1 RE=0.018 RC=0.007 CJC=136E-12 CJE=550E-12 MJC=0.352 MJE=0.36 VJC=0.554 VJE=0.726 TF=400E-12 TR=6.9E-9
\ No newline at end of file diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier-cache.lib b/analog circuits/rc coupled amplifier/rc coupled amplifier-cache.lib new file mode 100644 index 0000000..eb2b450 --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Transistor_BJT:BC547 +# +DEF Transistor_BJT:BC547 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "Transistor_BJT:BC547" 200 0 50 H V L CNN +F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC546 BC548 BC549 BC550 BC337 BC338 +$FPLIST + TO?92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 25 0 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 200 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# rc-coupled-amplifier-rescue:GND-sallen_key_schlib +# +DEF rc-coupled-amplifier-rescue:GND-sallen_key_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "rc-coupled-amplifier-rescue:GND-sallen_key_schlib" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# rc-coupled-amplifier-rescue:VDD-laser_driver_schlib +# +DEF rc-coupled-amplifier-rescue:VDD-laser_driver_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "rc-coupled-amplifier-rescue:VDD-laser_driver_schlib" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier-rescue.dcm b/analog circuits/rc coupled amplifier/rc coupled amplifier-rescue.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier-rescue.lib b/analog circuits/rc coupled amplifier/rc coupled amplifier-rescue.lib new file mode 100644 index 0000000..d915334 --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier-rescue.lib @@ -0,0 +1,69 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# GND-sallen_key_schlib +# +DEF GND-sallen_key_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND-sallen_key_schlib" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Q_NPN_CBE-laser_driver_schlib +# +DEF Q_NPN_CBE-laser_driver_schlib Q 0 0 Y N 1 F N +F0 "Q" 300 50 50 H V R CNN +F1 "Q_NPN_CBE-laser_driver_schlib" 600 -50 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# VDD-laser_driver_schlib +# +DEF VDD-laser_driver_schlib #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD-laser_driver_schlib" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE-laser_driver_schlib +# +DEF ~VSOURCE-laser_driver_schlib V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE-laser_driver_schlib" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier.bak b/analog circuits/rc coupled amplifier/rc coupled amplifier.bak new file mode 100644 index 0000000..06d08d4 --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier.bak @@ -0,0 +1,449 @@ +EESchema Schematic File Version 4 +LIBS:rc coupled amplifier-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:C C1 +U 1 1 5B0E94FC +P 4200 4100 +F 0 "C1" V 3948 4100 50 0000 C CNN +F 1 "10u" V 4039 4100 50 0000 C CNN +F 2 "" H 4238 3950 50 0001 C CNN +F 3 "~" H 4200 4100 50 0001 C CNN + 1 4200 4100 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0E9636 +P 5050 3200 +F 0 "R1" H 5120 3246 50 0000 L CNN +F 1 "33k" H 5120 3155 50 0000 L CNN +F 2 "" V 4980 3200 50 0001 C CNN +F 3 "~" H 5050 3200 50 0001 C CNN + 1 5050 3200 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0E9698 +P 5050 5050 +F 0 "R2" H 5120 5096 50 0000 L CNN +F 1 "3.3k" H 5120 5005 50 0000 L CNN +F 2 "" V 4980 5050 50 0001 C CNN +F 3 "~" H 5050 5050 50 0001 C CNN + 1 5050 5050 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0E96EF +P 6000 3200 +F 0 "R3" H 6070 3246 50 0000 L CNN +F 1 "1k" H 6070 3155 50 0000 L CNN +F 2 "" V 5930 3200 50 0001 C CNN +F 3 "~" H 6000 3200 50 0001 C CNN + 1 6000 3200 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B0E9773 +P 6000 5000 +F 0 "R4" H 6070 5046 50 0000 L CNN +F 1 "330" H 6070 4955 50 0000 L CNN +F 2 "" V 5930 5000 50 0001 C CNN +F 3 "~" H 6000 5000 50 0001 C CNN + 1 6000 5000 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0E97EC +P 6750 5000 +F 0 "C2" H 6635 4954 50 0000 R CNN +F 1 "100u" H 6635 5045 50 0000 R CNN +F 2 "" H 6788 4850 50 0001 C CNN +F 3 "~" H 6750 5000 50 0001 C CNN + 1 6750 5000 + -1 0 0 1 +$EndComp +$Comp +L Device:C C3 +U 1 1 5B0E985D +P 7250 3750 +F 0 "C3" V 6998 3750 50 0000 C CNN +F 1 "10u" V 7089 3750 50 0000 C CNN +F 2 "" H 7288 3600 50 0001 C CNN +F 3 "~" H 7250 3750 50 0001 C CNN + 1 7250 3750 + 0 1 1 0 +$EndComp +$Comp +L Device:R R5 +U 1 1 5B0E9940 +P 7800 3250 +F 0 "R5" H 7870 3296 50 0000 L CNN +F 1 "33k" H 7870 3205 50 0000 L CNN +F 2 "" V 7730 3250 50 0001 C CNN +F 3 "~" H 7800 3250 50 0001 C CNN + 1 7800 3250 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R6 +U 1 1 5B0E99CA +P 7850 4850 +F 0 "R6" H 7920 4896 50 0000 L CNN +F 1 "3.3k" H 7920 4805 50 0000 L CNN +F 2 "" V 7780 4850 50 0001 C CNN +F 3 "~" H 7850 4850 50 0001 C CNN + 1 7850 4850 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R7 +U 1 1 5B0E9A36 +P 8300 3250 +F 0 "R7" H 8370 3296 50 0000 L CNN +F 1 "1k" H 8370 3205 50 0000 L CNN +F 2 "" V 8230 3250 50 0001 C CNN +F 3 "~" H 8300 3250 50 0001 C CNN + 1 8300 3250 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R8 +U 1 1 5B0E9AB9 +P 8400 4850 +F 0 "R8" H 8470 4896 50 0000 L CNN +F 1 "330" H 8470 4805 50 0000 L CNN +F 2 "" V 8330 4850 50 0001 C CNN +F 3 "~" H 8400 4850 50 0001 C CNN + 1 8400 4850 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C4 +U 1 1 5B0E9B21 +P 8900 4800 +F 0 "C4" H 8785 4754 50 0000 R CNN +F 1 "100u" H 8785 4845 50 0000 R CNN +F 2 "" H 8938 4650 50 0001 C CNN +F 3 "~" H 8900 4800 50 0001 C CNN + 1 8900 4800 + -1 0 0 1 +$EndComp +$Comp +L Device:C C5 +U 1 1 5B0E9BB0 +P 9300 3650 +F 0 "C5" V 9048 3650 50 0000 C CNN +F 1 "10u" V 9139 3650 50 0000 C CNN +F 2 "" H 9338 3500 50 0001 C CNN +F 3 "~" H 9300 3650 50 0001 C CNN + 1 9300 3650 + 0 1 1 0 +$EndComp +Wire Wire Line + 3100 4450 3100 4100 +Wire Wire Line + 3100 4100 4050 4100 +Wire Wire Line + 4350 4100 5050 4100 +Wire Wire Line + 5050 4900 5050 4100 +Connection ~ 5050 4100 +Wire Wire Line + 5050 4100 5700 4100 +Wire Wire Line + 5050 4100 5050 3350 +Wire Wire Line + 5050 3050 6000 3050 +Wire Wire Line + 6000 5150 6000 5450 +Wire Wire Line + 6000 5450 5050 5450 +Wire Wire Line + 5050 5450 5050 5200 +Wire Wire Line + 6000 4700 6750 4700 +Wire Wire Line + 6750 4700 6750 4850 +Connection ~ 6000 4700 +Wire Wire Line + 6000 4700 6000 4850 +Wire Wire Line + 6750 5150 6750 5450 +Wire Wire Line + 6750 5450 6000 5450 +Connection ~ 6000 5450 +Wire Wire Line + 7400 3750 7400 4050 +Wire Wire Line + 7400 4050 7850 4050 +Wire Wire Line + 7800 3400 7850 3400 +Wire Wire Line + 7850 3400 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CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 5900 4100 50 0001 L CNN +F 4 "V" H 5900 4100 50 0001 C CNN "Spice_Primitive" +F 5 "Y" H 5900 4100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5900 4100 + 1 0 0 -1 +$EndComp +$Comp +L Transistor_BJT:BC547 Q2 +U 1 1 5B11E104 +P 8250 4050 +F 0 "Q2" H 8441 4096 50 0000 L CNN +F 1 "BC547" H 8441 4005 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 8450 3975 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 8250 4050 50 0001 L CNN +F 4 "V" H 8250 4050 50 0001 C CNN "Spice_Primitive" +F 5 "Y" H 8250 4050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8250 4050 + 1 0 0 -1 +$EndComp +Text Notes 4750 6450 0 50 ~ 0 +.ac dec 10 1 1meg +$EndSCHEMATC diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier.cir b/analog circuits/rc coupled amplifier/rc coupled amplifier.cir new file mode 100644 index 0000000..a4200e6 --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier.cir @@ -0,0 +1,22 @@ +.title KiCad schematic +.include "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" +C1 Net-_C1-Pad1_ ip 10u +R1 VDD Net-_C1-Pad1_ 33k +R2 Net-_C1-Pad1_ GND 3.3k +R3 VDD Net-_C3-Pad2_ 1k +R4 Net-_C2-Pad2_ GND 330 +C2 GND Net-_C2-Pad2_ 100u +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10u +R5 VDD Net-_C3-Pad1_ 33k +R6 Net-_C3-Pad1_ GND 3.3k +R7 VDD Net-_C5-Pad2_ 1k +R8 Net-_C4-Pad2_ GND 330 +C4 GND Net-_C4-Pad2_ 100u +C5 out Net-_C5-Pad2_ 10u +R9 out GND 4.7k +V1 ip GND ac 20 0 +V2 VDD GND dc 25 +Q1 Net-_C3-Pad2_ Net-_C1-Pad1_ Net-_C2-Pad2_ FZT1049A +Q2 Net-_C5-Pad2_ Net-_C3-Pad1_ Net-_C4-Pad2_ FZT1049A +.ac dec 10 1 1meg +.end diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier.kicad_pcb b/analog circuits/rc coupled amplifier/rc coupled amplifier.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier.pro b/analog circuits/rc coupled amplifier/rc coupled amplifier.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/rc coupled amplifier/rc coupled amplifier.sch b/analog circuits/rc coupled amplifier/rc coupled amplifier.sch new file mode 100644 index 0000000..2bdaf6c --- /dev/null +++ b/analog circuits/rc coupled amplifier/rc coupled amplifier.sch @@ -0,0 +1,453 @@ +EESchema Schematic File Version 4 +LIBS:rc coupled amplifier-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:C C1 +U 1 1 5B0E94FC +P 4200 4100 +F 0 "C1" V 3948 4100 50 0000 C CNN +F 1 "10u" V 4039 4100 50 0000 C CNN +F 2 "" H 4238 3950 50 0001 C CNN +F 3 "~" H 4200 4100 50 0001 C CNN + 1 4200 4100 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0E9636 +P 5050 3200 +F 0 "R1" H 5120 3246 50 0000 L CNN +F 1 "33k" H 5120 3155 50 0000 L CNN +F 2 "" V 4980 3200 50 0001 C CNN +F 3 "~" H 5050 3200 50 0001 C CNN + 1 5050 3200 + 1 0 0 -1 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CNN +F 1 "VSOURCE" H 3328 4705 50 0000 L CNN +F 2 "" H 3100 4750 50 0001 C CNN +F 3 "" H 3100 4750 50 0001 C CNN +F 4 "V" H 3100 4750 50 0001 C CNN "Spice_Primitive" +F 5 "ac 20 0" H 3100 4750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3100 4750 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3100 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 5400 3100 5050 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B110487 +P 9050 1750 +F 0 "V2" H 9278 1796 50 0000 L CNN +F 1 "VSOURCE" H 9278 1705 50 0000 L CNN +F 2 "" H 9050 1750 50 0001 C CNN +F 3 "" H 9050 1750 50 0001 C CNN +F 4 "V" H 9050 1750 50 0001 C CNN "Spice_Primitive" +F 5 "dc 25" H 9050 1750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 9050 1750 50 0001 C CNN "Spice_Netlist_Enabled" + 1 9050 1750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 2050 9650 2050 +Wire Wire Line + 9050 1450 9400 1450 +Wire Wire Line + 9400 1450 9400 1650 +Wire Wire Line + 9400 1650 9650 1650 +Wire Wire Line + 6800 2300 6800 1600 +Wire Wire Line + 6800 1600 8100 1600 +Wire Wire Line + 8100 1600 8100 3100 +Connection ~ 6800 2300 +Connection ~ 8100 3100 +Wire Wire Line + 8100 3100 7800 3100 +$Comp +L Transistor_BJT:BC547 Q1 +U 1 1 5B11CD51 +P 5900 4100 +F 0 "Q1" H 6091 4146 50 0000 L CNN +F 1 "BC547" H 6091 4055 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 6100 4025 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 5900 4100 50 0001 L CNN +F 4 "Q" H 5900 4100 50 0001 C CNN "Spice_Primitive" +F 5 "Y" H 5900 4100 50 0001 C CNN "Spice_Netlist_Enabled" +F 6 "FZT1049A" H 5900 4100 50 0001 C CNN "Spice_Model" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" H 5900 4100 50 0001 C CNN "Spice_Lib_File" + 1 5900 4100 + 1 0 0 -1 +$EndComp +Text Notes 4750 6450 0 50 ~ 0 +.ac dec 10 1 1meg +$Comp +L Transistor_BJT:BC547 Q2 +U 1 1 5B30C7DB +P 8250 4050 +F 0 "Q2" H 8441 4096 50 0000 L CNN +F 1 "BC547" H 8441 4005 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 8450 3975 50 0001 L CIN +F 3 "http://www.fairchildsemi.com/ds/BC/BC547.pdf" H 8250 4050 50 0001 L CNN +F 4 "Q" H 8250 4050 50 0001 C CNN "Spice_Primitive" +F 5 "Y" H 8250 4050 50 0001 C CNN "Spice_Netlist_Enabled" +F 6 "FZT1049A" H 8250 4050 50 0001 C CNN "Spice_Model" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" H 8250 4050 50 0001 C CNN "Spice_Lib_File" + 1 8250 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/analog circuits/rc coupled amplifier/sym-lib-table b/analog circuits/rc coupled amplifier/sym-lib-table new file mode 100644 index 0000000..9fbdeee --- /dev/null +++ b/analog circuits/rc coupled amplifier/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name rc-coupled-amplifier-rescue)(type Legacy)(uri "${KIPRJMOD}/rc coupled amplifier-rescue.lib")(options "")(descr "")) +) diff --git a/analog circuits/second order low pass filter using op amp/ad8051.lib b/analog circuits/second order low pass filter using op amp/ad8051.lib new file mode 100644 index 0000000..20ac791 --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/ad8051.lib @@ -0,0 +1,112 @@ +* AD8051 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Single 110 MHz rail-to-rail op amp - 3V +* Developed by: JCH / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (09/1998) +* Copyright 1998, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* CMRR IS NOT MODELED +* +* Parameters modeled include: +* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) +* +* END Notes +* +* Node assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8051 1 2 99 50 45 +* +* INPUT STAGE +* +Q1 4 3 5 QPI +Q2 6 2 7 QPI +RC1 50 4 20.5k +RC2 50 6 20.5k +RE1 5 8 5k +RE2 7 8 5k +EOS 3 1 POLY(1) 53 98 1.7E-3 1 +IOS 1 2 0.1u +FNOI1 1 0 VMEAS2 1E-4 +FNOI2 2 0 VMEAS2 1E-4 + +CPAR1 3 50 1.7p +CPAR2 2 50 1.7p +VCMH1 99 9 1 +VCMH2 99 10 1 +D1 5 9 DX +D2 7 10 DX +IBIAS 99 8 73u +* +* INTERNAL VOLTAGE REFERENCE +* +EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 +EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 +GREF2 97 0 97 0 1E-6 +* +*VOLTAGE NOISE STAGE +* +DN1 51 52 DNOI1 +VN1 51 98 0.61 +VMEAS 52 98 0 +RNOI1 52 98 6.5E-3 + +H1 53 98 VMEAS 1 +RNOI2 53 98 1 +* +*CURRENT NOISE STAGE +* +DN2 61 62 DNOI2 +VN2 61 98 0.545 +VMEAS2 62 98 0 +RNOI3 62 98 2E-4 +* +* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz +* +G1 98 20 4 6 1E-3 +RP1 98 20 550 +CP1 98 20 3p +* +* GAIN STAGE WITH DOMINANT POLE +* +G4 98 30 20 98 2.6E-3 +RG1 30 98 155k +CF1 30 45 13.5p +D5 31 99 DX +D6 50 32 DX +V1 31 30 0.6 +V2 30 32 0.6 +* +* OUTPUT STAGE +* +Q3 45 42 99 QPOX +Q4 45 44 50 QNOX +EO3 99 42 POLY(1) 98 30 0.7175 0.5 +EO4 44 50 POLY(1) 30 98 0.7355 0.5 +* +* MODELS +* +.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) +.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) +.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) +.MODEL DX D(IS=1E-16) +.MODEL DZ D(IS=1E-14,BV=6.6) +.MODEL DNOI1 D(KF=9E-10) +.MODEL DNOI2 D(KF=1E-8) +.ENDS AD8051 + + + + diff --git a/analog circuits/second order low pass filter using op amp/sallen_key_schlib.lib b/analog circuits/second order low pass filter using op amp/sallen_key_schlib.lib new file mode 100644 index 0000000..dc98765 --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/sallen_key_schlib.lib @@ -0,0 +1,121 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp +# +DEF Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VDD +# +DEF VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS +# +DEF VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp-cache.lib b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp-cache.lib new file mode 100644 index 0000000..89a1d55 --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp-cache.lib @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VSS +# +DEF power:VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VSS" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sallen_key_schlib:Generic_Opamp +# +DEF sallen_key_schlib:Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "sallen_key_schlib:Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.bak b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.bak new file mode 100644 index 0000000..8c2e069 --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.bak @@ -0,0 +1,551 @@ +EESchema Schematic File Version 4 +LIBS:second order low pass filter using op amp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R3 +U 1 1 5B099DBF +P 2400 3450 +F 0 "R3" V 2193 3450 50 0000 C CNN +F 1 "1k" V 2284 3450 50 0000 C CNN +F 2 "" V 2330 3450 50 0001 C CNN +F 3 "~" H 2400 3450 50 0001 C CNN + 1 2400 3450 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B099F16 +P 1650 3450 +F 0 "R1" V 1443 3450 50 0000 C CNN +F 1 "1k" V 1534 3450 50 0000 C CNN +F 2 "" V 1580 3450 50 0001 C CNN +F 3 "~" H 1650 3450 50 0001 C CNN + 1 1650 3450 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B099F7E +P 2050 3200 +F 0 "R2" V 1843 3200 50 0000 C CNN +F 1 "1k" V 1934 3200 50 0000 C CNN +F 2 "" V 1980 3200 50 0001 C CNN +F 3 "~" H 2050 3200 50 0001 C CNN + 1 2050 3200 + 0 1 1 0 +$EndComp +$Comp +L Device:R R4 +U 1 1 5B09A00F +P 2850 2800 +F 0 "R4" V 2643 2800 50 0000 C CNN +F 1 "1k" V 2734 2800 50 0000 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1150 3450 +Wire Wire Line + 1150 3450 1500 3450 +Wire Wire Line + 1800 3450 2000 3450 +Wire Wire Line + 2550 3450 2850 3450 +Wire Wire Line + 2000 4250 2000 3900 +Wire Wire Line + 2000 3600 2000 3450 +Connection ~ 2000 3450 +Wire Wire Line + 2000 3450 2250 3450 +Wire Wire Line + 2200 3200 2550 3200 +Wire Wire Line + 3250 3200 3250 3250 +Wire Wire Line + 2550 3200 2550 2800 +Wire Wire Line + 2550 2800 2700 2800 +Connection ~ 2550 3200 +Wire Wire Line + 2550 3200 3250 3200 +Wire Wire Line + 3000 2800 3850 2800 +Wire Wire Line + 3850 2800 3850 3350 +$Comp +L power:GND #PWR02 +U 1 1 5B09ADE3 +P 1350 3200 +F 0 "#PWR02" H 1350 2950 50 0001 C CNN +F 1 "GND" H 1355 3027 50 0000 C CNN +F 2 "" H 1350 3200 50 0001 C CNN +F 3 "" H 1350 3200 50 0001 C CNN + 1 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR03 +U 1 1 5B09AE10 +P 3050 3900 +F 0 "#PWR03" H 3050 3650 50 0001 C CNN +F 1 "GND" H 3055 3727 50 0000 C CNN +F 2 "" H 3050 3900 50 0001 C CNN +F 3 "" H 3050 3900 50 0001 C CNN + 1 3050 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2 "" H 8150 2100 50 0001 C CNN +F 3 "" H 8150 2100 50 0001 C CNN + 1 8150 2100 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR011 +U 1 1 5B0C85F4 +P 8300 4350 +F 0 "#PWR011" H 8300 4200 50 0001 C CNN +F 1 "VSS" H 8317 4523 50 0000 C CNN +F 2 "" H 8300 4350 50 0001 C CNN +F 3 "" H 8300 4350 50 0001 C CNN + 1 8300 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 2250 8150 2100 +Wire Wire Line + 8150 3850 8150 4350 +Wire Wire Line + 8150 4350 8300 4350 +Wire Wire Line + 8150 2850 8150 3100 +$Comp +L power:GND #PWR012 +U 1 1 5B0CB840 +P 8650 3150 +F 0 "#PWR012" H 8650 2900 50 0001 C CNN +F 1 "GND" H 8655 2977 50 0000 C CNN +F 2 "" H 8650 3150 50 0001 C CNN +F 3 "" H 8650 3150 50 0001 C CNN + 1 8650 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8650 3150 8650 3100 +Wire Wire Line + 8650 3100 8150 3100 +Connection ~ 8150 3100 +Wire Wire Line + 8150 3100 8150 3250 +Text GLabel 1000 3300 0 50 Input ~ 0 +ip +Wire Wire Line + 1000 3300 1150 3300 +Wire Wire Line + 1150 3300 1150 3450 +Connection ~ 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sallen_key_schlib:Generic_Opamp U1 +U 1 1 5B2BA360 +P 3550 3350 +F 0 "U1" H 3891 3396 50 0000 L CNN +F 1 "Generic_Opamp" H 3891 3305 50 0000 L CNN +F 2 "" H 3450 3250 50 0000 C CNN +F 3 "" H 3550 3350 50 0000 C CNN +F 4 "X" H 3550 3350 50 0001 C CNN "Spice_Primitive" +F 5 "AD8051" H 3550 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3550 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/ad8051.lib" H 3550 3350 50 0001 C CNN "Spice_Lib_File" + 1 3550 3350 + 1 0 0 -1 +$EndComp +$Comp +L sallen_key_schlib:Generic_Opamp U2 +U 1 1 5B2BA47E +P 6150 3350 +F 0 "U2" H 6491 3396 50 0000 L CNN +F 1 "Generic_Opamp" H 6491 3305 50 0000 L CNN +F 2 "" H 6050 3250 50 0000 C CNN +F 3 "" H 6150 3350 50 0000 C CNN +F 4 "X" H 6150 3350 50 0001 C CNN "Spice_Primitive" +F 5 "AD8051" H 6150 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6150 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/ad8051.lib" H 6150 3350 50 0001 C CNN "Spice_Lib_File" + 1 6150 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.cir b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.cir new file mode 100644 index 0000000..d4b2606 --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.cir @@ -0,0 +1,21 @@ +.title KiCad schematic +.include "/home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/ad8051.lib" +R3 Net-_C2-Pad1_ Net-_C1-Pad1_ 1k +R1 Net-_C1-Pad1_ ip 1k +R2 Net-_R2-Pad1_ GND 1k +R4 Net-_C1-Pad2_ Net-_R2-Pad1_ 1k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 0.1u +C2 Net-_C2-Pad1_ GND 0.1u +V1 ip GND ac 1 0 +R6 Net-_C3-Pad1_ Net-_C1-Pad2_ 1k +R7 Net-_C4-Pad1_ Net-_C3-Pad1_ 1k +C3 Net-_C3-Pad1_ out 0.1u +C4 Net-_C4-Pad1_ GND 0.1u +R5 Net-_R5-Pad1_ GND 1k +R8 out Net-_R5-Pad1_ 1k +V2 VDD GND dc 15 +V3 GND VSS dc 15 +XU1 Net-_R2-Pad1_ Net-_C2-Pad1_ VDD VSS Net-_C1-Pad2_ AD8051 +XU2 Net-_R5-Pad1_ Net-_C4-Pad1_ VDD VSS out AD8051 +.ac dec 10 1 1meg +.end diff --git a/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.kicad_pcb b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.pro b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.sch b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.sch new file mode 100644 index 0000000..8292770 --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/second order low pass filter using op amp.sch @@ -0,0 +1,553 @@ +EESchema Schematic File Version 4 +LIBS:second order low pass filter using op amp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R3 +U 1 1 5B099DBF +P 2400 3450 +F 0 "R3" V 2193 3450 50 0000 C CNN +F 1 "1k" V 2284 3450 50 0000 C CNN +F 2 "" V 2330 3450 50 0001 C CNN +F 3 "~" H 2400 3450 50 0001 C CNN + 1 2400 3450 + 0 1 1 0 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B099F16 +P 1650 3450 +F 0 "R1" V 1443 3450 50 0000 C CNN +F 1 "1k" V 1534 3450 50 0000 C CNN +F 2 "" V 1580 3450 50 0001 C CNN +F 3 "~" H 1650 3450 50 0001 C CNN + 1 1650 3450 + 0 1 1 0 +$EndComp +$Comp +L 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8150 3550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 8150 3550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8150 3550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8150 3550 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR010 +U 1 1 5B0C8552 +P 8150 2100 +F 0 "#PWR010" H 8150 1950 50 0001 C CNN +F 1 "VDD" H 8167 2273 50 0000 C CNN +F 2 "" H 8150 2100 50 0001 C CNN +F 3 "" H 8150 2100 50 0001 C CNN + 1 8150 2100 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR011 +U 1 1 5B0C85F4 +P 8300 4350 +F 0 "#PWR011" H 8300 4200 50 0001 C CNN +F 1 "VSS" H 8317 4523 50 0000 C CNN +F 2 "" H 8300 4350 50 0001 C CNN +F 3 "" H 8300 4350 50 0001 C CNN + 1 8300 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 2250 8150 2100 +Wire Wire Line + 8150 3850 8150 4350 +Wire Wire Line + 8150 4350 8300 4350 +Wire Wire Line + 8150 2850 8150 3100 +$Comp +L power:GND #PWR012 +U 1 1 5B0CB840 +P 8650 3150 +F 0 "#PWR012" H 8650 2900 50 0001 C CNN +F 1 "GND" H 8655 2977 50 0000 C CNN +F 2 "" H 8650 3150 50 0001 C CNN +F 3 "" H 8650 3150 50 0001 C CNN + 1 8650 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8650 3150 8650 3100 +Wire Wire Line + 8650 3100 8150 3100 +Connection ~ 8150 3100 +Wire Wire Line + 8150 3100 8150 3250 +Text GLabel 1000 3300 0 50 Input ~ 0 +ip +Wire Wire Line + 1000 3300 1150 3300 +Wire Wire Line + 1150 3300 1150 3450 +Connection ~ 1150 3450 +$Comp +L power:VDD #PWR0101 +U 1 1 5B0FD915 +P 3100 3000 +F 0 "#PWR0101" H 3100 2850 50 0001 C CNN +F 1 "VDD" H 3117 3173 50 0000 C CNN +F 2 "" H 3100 3000 50 0001 C CNN +F 3 "" H 3100 3000 50 0001 C CNN + 1 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR0102 +U 1 1 5B0FD9B7 +P 3300 3900 +F 0 "#PWR0102" H 3300 3750 50 0001 C CNN +F 1 "VSS" H 3317 4073 50 0000 C CNN +F 2 "" H 3300 3900 50 0001 C CNN +F 3 "" H 3300 3900 50 0001 C CNN + 1 3300 3900 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0103 +U 1 1 5B0FD9FC +P 5500 3100 +F 0 "#PWR0103" H 5500 2950 50 0001 C CNN +F 1 "VDD" H 5517 3273 50 0000 C CNN +F 2 "" H 5500 3100 50 0001 C CNN +F 3 "" H 5500 3100 50 0001 C CNN + 1 5500 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR0104 +U 1 1 5B0FDA3A +P 6200 3900 +F 0 "#PWR0104" H 6200 3750 50 0001 C CNN +F 1 "VSS" H 6217 4073 50 0000 C CNN +F 2 "" H 6200 3900 50 0001 C CNN +F 3 "" H 6200 3900 50 0001 C CNN + 1 6200 3900 + 1 0 0 -1 +$EndComp +$Comp +L sallen_key_schlib:Generic_Opamp U1 +U 1 1 5B2BA360 +P 3550 3350 +F 0 "U1" H 3891 3396 50 0000 L CNN +F 1 "Generic_Opamp" H 3891 3305 50 0000 L CNN +F 2 "" H 3450 3250 50 0000 C CNN +F 3 "" H 3550 3350 50 0000 C CNN +F 4 "X" H 3550 3350 50 0001 C CNN "Spice_Primitive" +F 5 "AD8051" H 3550 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3550 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/ad8051.lib" H 3550 3350 50 0001 C CNN "Spice_Lib_File" + 1 3550 3350 + 1 0 0 -1 +$EndComp +$Comp +L sallen_key_schlib:Generic_Opamp U2 +U 1 1 5B2BA47E +P 6150 3350 +F 0 "U2" H 6491 3396 50 0000 L CNN +F 1 "Generic_Opamp" H 6491 3305 50 0000 L CNN +F 2 "" H 6050 3250 50 0000 C CNN +F 3 "" H 6150 3350 50 0000 C CNN +F 4 "X" H 6150 3350 50 0001 C CNN "Spice_Primitive" +F 5 "AD8051" H 6150 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6150 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/ad8051.lib" H 6150 3350 50 0001 C CNN "Spice_Lib_File" + 1 6150 3350 + 1 0 0 -1 +$EndComp +Text Notes 4000 5650 0 50 ~ 0 +.ac dec 10 1 1meg +$EndSCHEMATC diff --git a/analog circuits/second order low pass filter using op amp/sym-lib-table b/analog circuits/second order low pass filter using op amp/sym-lib-table new file mode 100644 index 0000000..fc4d1f2 --- /dev/null +++ b/analog circuits/second order low pass filter using op amp/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sallen_key_schlib)(type Legacy)(uri /home/akshay/kicad-source-mirror-master/demos/simulation/sallen_key/sallen_key_schlib.lib)(options "")(descr "")) +) diff --git a/analog circuits/voltage doubler/voltage doubler-cache.lib b/analog circuits/voltage doubler/voltage doubler-cache.lib new file mode 100644 index 0000000..452a2d2 --- /dev/null +++ b/analog circuits/voltage doubler/voltage doubler-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:D_ALT +# +DEF Device:D_ALT D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device:D_ALT" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 50 -50 -50 N +P 2 0 1 0 50 0 -50 0 N +P 4 0 1 8 50 50 50 -50 -50 0 50 50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/voltage doubler/voltage doubler.bak b/analog circuits/voltage doubler/voltage doubler.bak new file mode 100644 index 0000000..c036c76 --- /dev/null +++ b/analog circuits/voltage doubler/voltage doubler.bak @@ -0,0 +1,155 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0E3691 +P 3100 4150 +F 0 "V1" H 3328 4196 50 0000 L CNN +F 1 "VSOURCE" H 3328 4105 50 0000 L CNN +F 2 "" H 3100 4150 50 0001 C CNN +F 3 "" H 3100 4150 50 0001 C CNN +F 4 "V" H 3100 4150 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 20 1000)" H 3100 4150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3100 4150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3100 4150 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0E3707 +P 4100 3600 +F 0 "C1" V 3848 3600 50 0000 C CNN +F 1 "100u" V 3939 3600 50 0000 C CNN +F 2 "" H 4138 3450 50 0001 C CNN +F 3 "~" H 4100 3600 50 0001 C CNN + 1 4100 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0E37E5 +P 4800 4250 +F 0 "D1" V 4754 4329 50 0000 L CNN +F 1 "D_ALT" V 4845 4329 50 0000 L CNN +F 2 "" H 4800 4250 50 0001 C CNN +F 3 "~" H 4800 4250 50 0001 C CNN + 1 4800 4250 + 0 1 1 0 +$EndComp +$Comp +L Device:D_ALT D2 +U 1 1 5B0E3825 +P 5400 3600 +F 0 "D2" H 5400 3384 50 0000 C CNN +F 1 "D_ALT" H 5400 3475 50 0000 C CNN +F 2 "" H 5400 3600 50 0001 C CNN +F 3 "~" H 5400 3600 50 0001 C CNN + 1 5400 3600 + -1 0 0 1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0E3882 +P 6200 4000 +F 0 "C2" H 6085 3954 50 0000 R CNN +F 1 "100u" H 6085 4045 50 0000 R CNN +F 2 "" H 6238 3850 50 0001 C CNN +F 3 "~" H 6200 4000 50 0001 C CNN + 1 6200 4000 + -1 0 0 1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0E392D +P 7050 4000 +F 0 "R1" H 7120 4046 50 0000 L CNN +F 1 "20k" H 7120 3955 50 0000 L CNN +F 2 "" V 6980 4000 50 0001 C CNN +F 3 "~" H 7050 4000 50 0001 C CNN + 1 7050 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 3850 3100 3600 +Wire Wire Line + 3100 3600 3950 3600 +Wire Wire Line + 4250 3600 4800 3600 +Wire Wire Line + 4800 3600 4800 4100 +Wire Wire Line + 4800 3600 5250 3600 +Connection ~ 4800 3600 +Wire Wire Line + 5550 3600 6200 3600 +Wire Wire Line + 6200 3600 6200 3850 +Wire Wire Line + 6200 3600 7050 3600 +Wire Wire Line + 7050 3600 7050 3850 +Connection ~ 6200 3600 +Wire Wire Line + 3100 4450 3100 4750 +Wire Wire Line + 3100 4750 4800 4750 +Wire Wire Line + 4800 4750 4800 4400 +Wire Wire Line + 4800 4750 5600 4750 +Wire Wire Line + 6200 4750 6200 4150 +Connection ~ 4800 4750 +Wire Wire Line + 6200 4750 7050 4750 +Wire Wire Line + 7050 4750 7050 4150 +Connection ~ 6200 4750 +$Comp +L power:GND #PWR01 +U 1 1 5B0E3C1D +P 5600 5000 +F 0 "#PWR01" H 5600 4750 50 0001 C CNN +F 1 "GND" H 5605 4827 50 0000 C CNN +F 2 "" H 5600 5000 50 0001 C CNN +F 3 "" H 5600 5000 50 0001 C CNN + 1 5600 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 5000 5600 4750 +Connection ~ 5600 4750 +Wire Wire Line + 5600 4750 6200 4750 +Text GLabel 7600 3400 0 50 Output ~ 0 +out +Wire Wire Line + 7600 3400 7750 3400 +Wire Wire Line + 7750 3400 7750 3000 +Wire Wire Line + 7750 3000 7050 3000 +Wire Wire Line + 7050 3000 7050 3600 +Connection ~ 7050 3600 +Text GLabel 2650 3300 0 50 Input ~ 0 +ip +Wire Wire Line + 2650 3300 3100 3300 +Wire Wire Line + 3100 3300 3100 3600 +Connection ~ 3100 3600 +$EndSCHEMATC diff --git a/analog circuits/voltage doubler/voltage doubler.cir b/analog circuits/voltage doubler/voltage doubler.cir new file mode 100644 index 0000000..294b44c --- /dev/null +++ b/analog circuits/voltage doubler/voltage doubler.cir @@ -0,0 +1,8 @@ +.title KiCad schematic +V1 ip GND sin(0 20 1000) +C1 Net-_C1-Pad1_ ip 100u +D1 GND Net-_C1-Pad1_ D_ALT +D2 Net-_C1-Pad1_ out D_ALT +C2 GND out 100u +R1 out GND 20k +.end diff --git a/analog circuits/voltage doubler/voltage doubler.kicad_pcb b/analog circuits/voltage doubler/voltage doubler.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/voltage doubler/voltage doubler.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/voltage doubler/voltage doubler.pro b/analog circuits/voltage doubler/voltage doubler.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/voltage doubler/voltage doubler.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/voltage doubler/voltage doubler.sch b/analog circuits/voltage doubler/voltage doubler.sch new file mode 100644 index 0000000..a9e8f9b --- /dev/null +++ b/analog circuits/voltage doubler/voltage doubler.sch @@ -0,0 +1,166 @@ +EESchema Schematic File Version 4 +LIBS:voltage doubler-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0E3691 +P 3100 4150 +F 0 "V1" H 3328 4196 50 0000 L CNN +F 1 "VSOURCE" H 3328 4105 50 0000 L CNN +F 2 "" H 3100 4150 50 0001 C CNN +F 3 "" H 3100 4150 50 0001 C CNN +F 4 "V" H 3100 4150 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 20 1000)" H 3100 4150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3100 4150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3100 4150 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0E3707 +P 4100 3600 +F 0 "C1" V 3848 3600 50 0000 C CNN +F 1 "100u" V 3939 3600 50 0000 C CNN +F 2 "" H 4138 3450 50 0001 C CNN +F 3 "~" H 4100 3600 50 0001 C CNN + 1 4100 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0E37E5 +P 4800 4250 +F 0 "D1" V 4754 4329 50 0000 L CNN +F 1 "D_ALT" V 4845 4329 50 0000 L CNN +F 2 "" H 4800 4250 50 0001 C CNN +F 3 "~" H 4800 4250 50 0001 C CNN +F 4 "D" H 4800 4250 50 0001 C CNN "Spice_Primitive" +F 5 "D_ALT" H 4800 4250 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4800 4250 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 4800 4250 50 0001 C CNN "Spice_Node_Sequence" + 1 4800 4250 + 0 1 1 0 +$EndComp +$Comp +L Device:D_ALT D2 +U 1 1 5B0E3825 +P 5400 3600 +F 0 "D2" H 5400 3384 50 0000 C CNN +F 1 "D_ALT" H 5400 3475 50 0000 C CNN +F 2 "" H 5400 3600 50 0001 C CNN +F 3 "~" H 5400 3600 50 0001 C CNN +F 4 "D" H 5400 3600 50 0001 C CNN "Spice_Primitive" +F 5 "D_ALT" H 5400 3600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5400 3600 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5400 3600 50 0001 C CNN "Spice_Node_Sequence" + 1 5400 3600 + -1 0 0 1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0E3882 +P 6200 4000 +F 0 "C2" H 6085 3954 50 0000 R CNN +F 1 "100u" H 6085 4045 50 0000 R CNN +F 2 "" H 6238 3850 50 0001 C CNN +F 3 "~" H 6200 4000 50 0001 C CNN + 1 6200 4000 + -1 0 0 1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0E392D +P 7050 4000 +F 0 "R1" H 7120 4046 50 0000 L CNN +F 1 "20k" H 7120 3955 50 0000 L CNN +F 2 "" V 6980 4000 50 0001 C CNN +F 3 "~" H 7050 4000 50 0001 C CNN + 1 7050 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 3850 3100 3600 +Wire Wire Line + 3100 3600 3950 3600 +Wire Wire Line + 4250 3600 4800 3600 +Wire Wire Line + 4800 3600 4800 4100 +Wire Wire Line + 4800 3600 5250 3600 +Connection ~ 4800 3600 +Wire Wire Line + 5550 3600 6200 3600 +Wire Wire Line + 6200 3600 6200 3850 +Wire Wire Line + 6200 3600 7050 3600 +Wire Wire Line + 7050 3600 7050 3850 +Connection ~ 6200 3600 +Wire Wire Line + 3100 4450 3100 4750 +Wire Wire Line + 3100 4750 4800 4750 +Wire Wire Line + 4800 4750 4800 4400 +Wire Wire Line + 4800 4750 5600 4750 +Wire Wire Line + 6200 4750 6200 4150 +Connection ~ 4800 4750 +Wire Wire Line + 6200 4750 7050 4750 +Wire Wire Line + 7050 4750 7050 4150 +Connection ~ 6200 4750 +$Comp +L power:GND #PWR01 +U 1 1 5B0E3C1D +P 5600 5000 +F 0 "#PWR01" H 5600 4750 50 0001 C CNN +F 1 "GND" H 5605 4827 50 0000 C CNN +F 2 "" H 5600 5000 50 0001 C CNN +F 3 "" H 5600 5000 50 0001 C CNN + 1 5600 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 5000 5600 4750 +Connection ~ 5600 4750 +Wire Wire Line + 5600 4750 6200 4750 +Text GLabel 7600 3400 0 50 Output ~ 0 +out +Wire Wire Line + 7600 3400 7750 3400 +Wire Wire Line + 7750 3400 7750 3000 +Wire Wire Line + 7750 3000 7050 3000 +Wire Wire Line + 7050 3000 7050 3600 +Connection ~ 7050 3600 +Text GLabel 2650 3300 0 50 Input ~ 0 +ip +Wire Wire Line + 2650 3300 3100 3300 +Wire Wire Line + 3100 3300 3100 3600 +Connection ~ 3100 3600 +Text Notes 7350 5850 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/voltage regulator/ZenerD1N750.lib b/analog circuits/voltage regulator/ZenerD1N750.lib new file mode 100755 index 0000000..890c37f --- /dev/null +++ b/analog circuits/voltage regulator/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/analog circuits/voltage regulator/fzt1049a.lib b/analog circuits/voltage regulator/fzt1049a.lib new file mode 100644 index 0000000..9aed971 --- /dev/null +++ b/analog circuits/voltage regulator/fzt1049a.lib @@ -0,0 +1 @@ +.model FZT1049A NPN IS=1.5E-12 NF=1.0 BF=600 IKF=7.5 VAF=100 ISE=0.9E-13 NE=1.25 NR=1.0 BR=150 IKR=3 VAR=15 ISC=5.0E-13 NC=1.76 RB=0.1 RE=0.018 RC=0.007 CJC=136E-12 CJE=550E-12 MJC=0.352 MJE=0.36 VJC=0.554 VJE=0.726 TF=400E-12 TR=6.9E-9
\ No newline at end of file diff --git a/analog circuits/voltage regulator/laser_driver_schlib.lib b/analog circuits/voltage regulator/laser_driver_schlib.lib new file mode 100644 index 0000000..f44ec29 --- /dev/null +++ b/analog circuits/voltage regulator/laser_driver_schlib.lib @@ -0,0 +1,166 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp +# +DEF Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# LED +# +DEF LED D 0 40 Y N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "LED" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + LED-3MM + LED-5MM + LED-10MM + LED-0603 + LED-0805 + LED-1206 + LEDV +$ENDFPLIST +DRAW +P 2 0 1 0 -50 50 -50 -50 N +P 3 0 1 0 -80 -25 -125 -65 -120 -40 N +P 3 0 1 0 -65 -40 -110 -80 -105 -55 N +P 3 0 1 0 50 50 -50 0 50 -50 F +X K 1 -200 0 150 R 40 40 1 1 P +X A 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# Q_NPN_CBE +# +DEF Q_NPN_CBE Q 0 0 Y N 1 F N +F0 "Q" 300 50 50 H V R CNN +F1 "Q_NPN_CBE" 600 -50 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VDD +# +DEF VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS +# +DEF VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS" 0 150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/voltage regulator/sym-lib-table b/analog circuits/voltage regulator/sym-lib-table new file mode 100644 index 0000000..272ef44 --- /dev/null +++ b/analog circuits/voltage regulator/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name laser_driver_schlib)(type Legacy)(uri /home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/laser_driver_schlib.lib)(options "")(descr "")) +) diff --git a/analog circuits/voltage regulator/voltage regulator-cache.lib b/analog circuits/voltage regulator/voltage regulator-cache.lib new file mode 100644 index 0000000..5a05271 --- /dev/null +++ b/analog circuits/voltage regulator/voltage regulator-cache.lib @@ -0,0 +1,92 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:D_Zener +# +DEF Device:D_Zener D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device:D_Zener" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 0 50 0 -50 0 N +P 3 0 1 8 -50 -50 -50 50 -30 50 N +P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# laser_driver_schlib:Q_NPN_CBE +# +DEF laser_driver_schlib:Q_NPN_CBE Q 0 0 Y N 1 F N +F0 "Q" 300 50 50 H V R CNN +F1 "laser_driver_schlib:Q_NPN_CBE" 600 -50 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/voltage regulator/voltage regulator.bak b/analog circuits/voltage regulator/voltage regulator.bak new file mode 100644 index 0000000..68f15b9 --- /dev/null +++ b/analog circuits/voltage regulator/voltage regulator.bak @@ -0,0 +1,139 @@ +EESchema Schematic File Version 4 +LIBS:voltage regulator-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0D7E62 +P 3700 4150 +F 0 "V1" H 3928 4196 50 0000 L CNN +F 1 "VSOURCE" H 3928 4105 50 0000 L CNN +F 2 "" H 3700 4150 50 0001 C CNN +F 3 "" H 3700 4150 50 0001 C CNN + 1 3700 4150 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0D7EEC +P 4750 3600 +F 0 "R1" H 4820 3646 50 0000 L CNN +F 1 "1.5k" H 4820 3555 50 0000 L CNN +F 2 "" V 4680 3600 50 0001 C CNN +F 3 "~" H 4750 3600 50 0001 C CNN + 1 4750 3600 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0D8729 +P 6450 3800 +F 0 "R2" H 6520 3846 50 0000 L CNN +F 1 "1k" H 6520 3755 50 0000 L CNN +F 2 "" V 6380 3800 50 0001 C CNN +F 3 "~" H 6450 3800 50 0001 C CNN + 1 6450 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 3850 3700 3450 +Wire Wire Line + 3700 3450 4750 3450 +Wire Wire Line + 5400 3450 5400 3400 +Connection ~ 4750 3450 +Wire Wire Line + 5800 3400 6250 3400 +Wire Wire Line + 6450 3400 6450 3650 +Wire Wire Line + 3700 4450 3700 4600 +Wire Wire Line + 3700 4600 4800 4600 +Wire Wire Line + 6450 4600 6450 3950 +Wire Wire Line + 5550 3700 5600 3700 +Wire Wire Line + 4750 3750 4750 4050 +Wire Wire Line + 4750 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 3700 +$Comp +L power:GND #PWR0101 +U 1 1 5B0CEEB6 +P 4800 5000 +F 0 "#PWR0101" H 4800 4750 50 0001 C CNN +F 1 "GND" H 4805 4827 50 0000 C CNN +F 2 "" H 4800 5000 50 0001 C CNN +F 3 "" H 4800 5000 50 0001 C CNN + 1 4800 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 5000 4800 4600 +Wire Wire Line + 4800 4600 5550 4600 +Connection ~ 4800 4600 +Wire Wire Line + 5550 4200 5550 4050 +Connection ~ 5550 4050 +Wire Wire Line + 5550 4500 5550 4600 +Connection ~ 5550 4600 +Wire Wire Line + 5550 4600 6450 4600 +Wire Wire Line + 4750 3450 5400 3450 +$Comp +L laser_driver_schlib:Q_NPN_CBE Q1 +U 1 1 5B30C110 +P 5600 3500 +F 0 "Q1" V 5928 3500 50 0000 C CNN +F 1 "Q_NPN_CBE" V 5837 3500 50 0000 C CNN +F 2 "" H 5800 3600 29 0000 C CNN +F 3 "" H 5600 3500 60 0000 C CNN +F 4 "Q" H 5600 3500 50 0001 C CNN "Spice_Primitive" +F 5 "FZT1049A" H 5600 3500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5600 3500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" H 5600 3500 50 0001 C CNN "Spice_Lib_File" + 1 5600 3500 + 0 -1 -1 0 +$EndComp +Text GLabel 6250 2950 0 50 Output ~ 0 +vout +Wire Wire Line + 6250 2950 6250 3400 +Connection ~ 6250 3400 +Wire Wire Line + 6250 3400 6450 3400 +$Comp +L Device:D_Zener D1 +U 1 1 5B30C56C +P 5550 4350 +F 0 "D1" V 5504 4429 50 0000 L CNN +F 1 "D_Zener" V 5595 4429 50 0000 L CNN +F 2 "" H 5550 4350 50 0001 C CNN +F 3 "~" H 5550 4350 50 0001 C CNN +F 4 "D" H 5550 4350 50 0001 C CNN "Spice_Primitive" +F 5 "D1N750" H 5550 4350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 4350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5550 4350 50 0001 C CNN "Spice_Node_Sequence" +F 8 "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" H 5550 4350 50 0001 C CNN "Spice_Lib_File" + 1 5550 4350 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/analog circuits/voltage regulator/voltage regulator.cir b/analog circuits/voltage regulator/voltage regulator.cir new file mode 100644 index 0000000..bda5c6f --- /dev/null +++ b/analog circuits/voltage regulator/voltage regulator.cir @@ -0,0 +1,10 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" +.include "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" +V1 Net-_Q1-Pad1_ GND VSOURCE +R1 Net-_Q1-Pad1_ Net-_D1-Pad1_ 1.5k +R2 vout GND 1k +Q1 Net-_Q1-Pad1_ Net-_D1-Pad1_ vout FZT1049A +D1 GND Net-_D1-Pad1_ D1N750 +.dc V1 1 16 1 +.end diff --git a/analog circuits/voltage regulator/voltage regulator.kicad_pcb b/analog circuits/voltage regulator/voltage regulator.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/voltage regulator/voltage regulator.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/voltage regulator/voltage regulator.pro b/analog circuits/voltage regulator/voltage regulator.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/voltage regulator/voltage regulator.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/voltage regulator/voltage regulator.sch b/analog circuits/voltage regulator/voltage regulator.sch new file mode 100644 index 0000000..b72047f --- /dev/null +++ b/analog circuits/voltage regulator/voltage regulator.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 4 +LIBS:voltage regulator-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0D7E62 +P 3700 4150 +F 0 "V1" H 3928 4196 50 0000 L CNN +F 1 "VSOURCE" H 3928 4105 50 0000 L CNN +F 2 "" H 3700 4150 50 0001 C CNN +F 3 "" H 3700 4150 50 0001 C CNN + 1 3700 4150 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0D7EEC +P 4750 3600 +F 0 "R1" H 4820 3646 50 0000 L CNN +F 1 "1.5k" H 4820 3555 50 0000 L CNN +F 2 "" V 4680 3600 50 0001 C CNN +F 3 "~" H 4750 3600 50 0001 C CNN + 1 4750 3600 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0D8729 +P 6450 3800 +F 0 "R2" H 6520 3846 50 0000 L CNN +F 1 "1k" H 6520 3755 50 0000 L CNN +F 2 "" V 6380 3800 50 0001 C CNN +F 3 "~" H 6450 3800 50 0001 C CNN + 1 6450 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 3850 3700 3450 +Wire Wire Line + 3700 3450 3950 3450 +Wire Wire Line + 5400 3450 5400 3400 +Connection ~ 4750 3450 +Wire Wire Line + 5800 3400 6250 3400 +Wire Wire Line + 6450 3400 6450 3650 +Wire Wire Line + 3700 4450 3700 4600 +Wire Wire Line + 3700 4600 4800 4600 +Wire Wire Line + 6450 4600 6450 3950 +Wire Wire Line + 5550 3700 5600 3700 +Wire Wire Line + 4750 3750 4750 4050 +Wire Wire Line + 4750 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 3700 +$Comp +L power:GND #PWR0101 +U 1 1 5B0CEEB6 +P 4800 5000 +F 0 "#PWR0101" H 4800 4750 50 0001 C CNN +F 1 "GND" H 4805 4827 50 0000 C CNN +F 2 "" H 4800 5000 50 0001 C CNN +F 3 "" H 4800 5000 50 0001 C CNN + 1 4800 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 5000 4800 4600 +Wire Wire Line + 4800 4600 5550 4600 +Connection ~ 4800 4600 +Wire Wire Line + 5550 4200 5550 4050 +Connection ~ 5550 4050 +Wire Wire Line + 5550 4500 5550 4600 +Connection ~ 5550 4600 +Wire Wire Line + 5550 4600 6450 4600 +Wire Wire Line + 4750 3450 5400 3450 +$Comp +L laser_driver_schlib:Q_NPN_CBE Q1 +U 1 1 5B30C110 +P 5600 3500 +F 0 "Q1" V 5928 3500 50 0000 C CNN +F 1 "Q_NPN_CBE" V 5837 3500 50 0000 C CNN +F 2 "" H 5800 3600 29 0000 C CNN +F 3 "" H 5600 3500 60 0000 C CNN +F 4 "Q" H 5600 3500 50 0001 C CNN "Spice_Primitive" +F 5 "FZT1049A" H 5600 3500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5600 3500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad-source-mirror-master/demos/simulation/laser_driver/fzt1049a.lib" H 5600 3500 50 0001 C CNN "Spice_Lib_File" + 1 5600 3500 + 0 -1 -1 0 +$EndComp +Text GLabel 6250 2950 0 50 Output ~ 0 +vout +Wire Wire Line + 6250 2950 6250 3400 +Connection ~ 6250 3400 +Wire Wire Line + 6250 3400 6450 3400 +$Comp +L Device:D_Zener D1 +U 1 1 5B30C56C +P 5550 4350 +F 0 "D1" V 5504 4429 50 0000 L CNN +F 1 "D_Zener" V 5595 4429 50 0000 L CNN +F 2 "" H 5550 4350 50 0001 C CNN +F 3 "~" H 5550 4350 50 0001 C CNN +F 4 "D" H 5550 4350 50 0001 C CNN "Spice_Primitive" +F 5 "D1N750" H 5550 4350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 4350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5550 4350 50 0001 C CNN "Spice_Node_Sequence" +F 8 "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" H 5550 4350 50 0001 C CNN "Spice_Lib_File" + 1 5550 4350 + 0 1 1 0 +$EndComp +Text Notes 6400 5100 0 50 ~ 0 +.dc V1 1 16 1 +Text GLabel 3650 3000 0 50 Input ~ 0 +ip +Wire Wire Line + 3650 3000 3950 3000 +Wire Wire Line + 3950 3000 3950 3450 +Connection ~ 3950 3450 +Wire Wire Line + 3950 3450 4750 3450 +$EndSCHEMATC diff --git a/analog circuits/voltage tripler/_saved_voltage tripler-cache.lib b/analog circuits/voltage tripler/_saved_voltage tripler-cache.lib new file mode 100644 index 0000000..9d768a4 --- /dev/null +++ b/analog circuits/voltage tripler/_saved_voltage tripler-cache.lib @@ -0,0 +1,104 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:D_ALT +# +DEF Device:D_ALT D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device:D_ALT" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 50 -50 -50 N +P 2 0 1 0 50 0 -50 0 N +P 4 0 1 8 50 50 50 -50 -50 0 50 50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/voltage tripler/_saved_voltage tripler.bak b/analog circuits/voltage tripler/_saved_voltage tripler.bak new file mode 100644 index 0000000..e3dc1f5 --- /dev/null +++ b/analog circuits/voltage tripler/_saved_voltage tripler.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 4 +LIBS:voltage tripler-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0A1122 +P 3150 4200 +F 0 "V1" H 3378 4246 50 0000 L CNN +F 1 "VSOURCE" H 3378 4155 50 0000 L CNN +F 2 "" H 3150 4200 50 0001 C CNN +F 3 "" H 3150 4200 50 0001 C CNN +F 4 "V" H 3150 4200 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 15 1000)" H 3150 4200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3150 4200 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3150 4200 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D2 +U 1 1 5B0A119A +P 4300 4050 +F 0 "D2" H 4300 3834 50 0000 C CNN +F 1 "D_ALT" H 4300 3925 50 0000 C CNN +F 2 "" H 4300 4050 50 0001 C CNN +F 3 "~" H 4300 4050 50 0001 C CNN + 1 4300 4050 + -1 0 0 1 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0A1225 +P 4100 3550 +F 0 "D1" V 4146 3471 50 0000 R CNN +F 1 "D_ALT" V 4055 3471 50 0000 R CNN +F 2 "" H 4100 3550 50 0001 C CNN +F 3 "~" H 4100 3550 50 0001 C CNN + 1 4100 3550 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0A12C0 +P 4800 3600 +F 0 "C2" V 4548 3600 50 0000 C CNN +F 1 "100u" V 4639 3600 50 0000 C CNN +F 2 "" H 4838 3450 50 0001 C CNN +F 3 "~" H 4800 3600 50 0001 C CNN + 1 4800 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0A1393 +P 4050 4750 +F 0 "C1" H 3935 4704 50 0000 R CNN +F 1 "100u" H 3935 4795 50 0000 R CNN +F 2 "" H 4088 4600 50 0001 C CNN +F 3 "~" H 4050 4750 50 0001 C CNN + 1 4050 4750 + -1 0 0 1 +$EndComp +$Comp +L Device:D_ALT D3 +U 1 1 5B0A142D +P 5650 3600 +F 0 "D3" H 5650 3384 50 0000 C CNN +F 1 "D_ALT" H 5650 3475 50 0000 C CNN +F 2 "" H 5650 3600 50 0001 C CNN +F 3 "~" H 5650 3600 50 0001 C CNN + 1 5650 3600 + -1 0 0 1 +$EndComp +$Comp +L Device:C C3 +U 1 1 5B0A14A1 +P 5850 4100 +F 0 "C3" H 5735 4054 50 0000 R CNN +F 1 "100u" H 5735 4145 50 0000 R CNN +F 2 "" H 5888 3950 50 0001 C CNN +F 3 "~" H 5850 4100 50 0001 C CNN + 1 5850 4100 + -1 0 0 1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0A1525 +P 6250 4100 +F 0 "R1" H 6320 4146 50 0000 L CNN +F 1 "40k" H 6320 4055 50 0000 L CNN +F 2 "" V 6180 4100 50 0001 C CNN +F 3 "~" H 6250 4100 50 0001 C CNN + 1 6250 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 3900 3150 3400 +Wire Wire Line + 3150 3400 4100 3400 +Wire Wire Line + 4100 3400 4450 3400 +Wire Wire Line + 4650 3400 4650 3600 +Connection ~ 4100 3400 +Wire Wire Line + 4100 3700 4100 4050 +Wire Wire Line + 4100 4050 4150 4050 +Wire Wire Line + 4450 4050 4450 3400 +Connection ~ 4450 3400 +Wire Wire Line + 4450 3400 4650 3400 +Wire Wire Line + 4100 4050 4100 4600 +Wire Wire Line + 4100 4600 4050 4600 +Connection ~ 4100 4050 +Wire Wire Line + 4950 3600 5500 3600 +Wire Wire Line + 5800 3600 5850 3600 +Wire Wire Line + 5850 3600 5850 3950 +Wire Wire Line + 5850 3600 6250 3600 +Wire Wire Line + 6250 3600 6250 3950 +Connection ~ 5850 3600 +Wire Wire Line + 3150 4500 3150 4900 +Wire Wire Line + 3150 4900 4050 4900 +Wire Wire Line + 4050 4900 4800 4900 +Wire Wire Line + 6250 4900 6250 4250 +Connection ~ 4050 4900 +Wire Wire Line + 5850 4250 5850 4900 +Connection ~ 5850 4900 +Wire Wire Line + 5850 4900 6250 4900 +$Comp +L power:GND #PWR01 +U 1 1 5B0A1C04 +P 4800 5200 +F 0 "#PWR01" H 4800 4950 50 0001 C CNN +F 1 "GND" H 4805 5027 50 0000 C CNN +F 2 "" H 4800 5200 50 0001 C CNN +F 3 "" H 4800 5200 50 0001 C CNN + 1 4800 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 5200 4800 5150 +Connection ~ 4800 4900 +Wire Wire Line + 4800 4900 5850 4900 +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 5B0A1F21 +P 5150 5150 +F 0 "#FLG0101" H 5150 5225 50 0001 C CNN +F 1 "PWR_FLAG" H 5150 5324 50 0000 C CNN +F 2 "" H 5150 5150 50 0001 C CNN +F 3 "~" H 5150 5150 50 0001 C CNN + 1 5150 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 5150 4800 5150 +Connection ~ 4800 5150 +Wire Wire Line + 4800 5150 4800 4900 +Text GLabel 6700 3400 0 50 Output ~ 0 +out +Wire Wire Line + 6700 3400 7100 3400 +Wire Wire Line + 7100 3400 7100 2950 +Wire Wire Line + 7100 2950 6250 2950 +Wire Wire Line + 6250 2950 6250 3600 +Connection ~ 6250 3600 +Text GLabel 2300 3100 0 50 Input ~ 0 +ip +Wire Wire Line + 2300 3100 3150 3100 +Wire Wire Line + 3150 3100 3150 3400 +Connection ~ 3150 3400 +Text Notes 7650 5350 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/voltage tripler/_saved_voltage tripler.cir b/analog circuits/voltage tripler/_saved_voltage tripler.cir new file mode 100644 index 0000000..4494393 --- /dev/null +++ b/analog circuits/voltage tripler/_saved_voltage tripler.cir @@ -0,0 +1,11 @@ +.title KiCad schematic +V1 ip GND sin(0 15 120) +D2 ip Net-_C1-Pad2_ D_ALT +D1 Net-_C1-Pad2_ ip D_ALT +C2 Net-_C2-Pad1_ ip 100u +C1 GND Net-_C1-Pad2_ 100u +D3 out Net-_C2-Pad1_ D_ALT +C3 GND out 100u +R1 out GND 40k +.tran 1m 1 +.end diff --git a/analog circuits/voltage tripler/_saved_voltage tripler.pro b/analog circuits/voltage tripler/_saved_voltage tripler.pro new file mode 100644 index 0000000..148e9ed --- /dev/null +++ b/analog circuits/voltage tripler/_saved_voltage tripler.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice + diff --git a/analog circuits/voltage tripler/ad8051.lib b/analog circuits/voltage tripler/ad8051.lib new file mode 100644 index 0000000..20ac791 --- /dev/null +++ b/analog circuits/voltage tripler/ad8051.lib @@ -0,0 +1,112 @@ +* AD8051 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Single 110 MHz rail-to-rail op amp - 3V +* Developed by: JCH / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (09/1998) +* Copyright 1998, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* CMRR IS NOT MODELED +* +* Parameters modeled include: +* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) +* +* END Notes +* +* Node assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8051 1 2 99 50 45 +* +* INPUT STAGE +* +Q1 4 3 5 QPI +Q2 6 2 7 QPI +RC1 50 4 20.5k +RC2 50 6 20.5k +RE1 5 8 5k +RE2 7 8 5k +EOS 3 1 POLY(1) 53 98 1.7E-3 1 +IOS 1 2 0.1u +FNOI1 1 0 VMEAS2 1E-4 +FNOI2 2 0 VMEAS2 1E-4 + +CPAR1 3 50 1.7p +CPAR2 2 50 1.7p +VCMH1 99 9 1 +VCMH2 99 10 1 +D1 5 9 DX +D2 7 10 DX +IBIAS 99 8 73u +* +* INTERNAL VOLTAGE REFERENCE +* +EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 +EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 +GREF2 97 0 97 0 1E-6 +* +*VOLTAGE NOISE STAGE +* +DN1 51 52 DNOI1 +VN1 51 98 0.61 +VMEAS 52 98 0 +RNOI1 52 98 6.5E-3 + +H1 53 98 VMEAS 1 +RNOI2 53 98 1 +* +*CURRENT NOISE STAGE +* +DN2 61 62 DNOI2 +VN2 61 98 0.545 +VMEAS2 62 98 0 +RNOI3 62 98 2E-4 +* +* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz +* +G1 98 20 4 6 1E-3 +RP1 98 20 550 +CP1 98 20 3p +* +* GAIN STAGE WITH DOMINANT POLE +* +G4 98 30 20 98 2.6E-3 +RG1 30 98 155k +CF1 30 45 13.5p +D5 31 99 DX +D6 50 32 DX +V1 31 30 0.6 +V2 30 32 0.6 +* +* OUTPUT STAGE +* +Q3 45 42 99 QPOX +Q4 45 44 50 QNOX +EO3 99 42 POLY(1) 98 30 0.7175 0.5 +EO4 44 50 POLY(1) 30 98 0.7355 0.5 +* +* MODELS +* +.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) +.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) +.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) +.MODEL DX D(IS=1E-16) +.MODEL DZ D(IS=1E-14,BV=6.6) +.MODEL DNOI1 D(KF=9E-10) +.MODEL DNOI2 D(KF=1E-8) +.ENDS AD8051 + + + + diff --git a/analog circuits/voltage tripler/sym-lib-table b/analog circuits/voltage tripler/sym-lib-table new file mode 100644 index 0000000..10decd0 --- /dev/null +++ b/analog circuits/voltage tripler/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (lib (name basic_gates)(type Legacy)(uri /home/akshay/kicad_examples/and_sub/basic_gates.lib)(options "")(descr "")) + (lib (name rectifier_schlib)(type Legacy)(uri /home/akshay/kicad-source-mirror-master/demos/simulation/rectifier/rectifier_schlib.lib)(options "")(descr "")) +) diff --git a/analog circuits/voltage tripler/voltage tripler-cache.lib b/analog circuits/voltage tripler/voltage tripler-cache.lib new file mode 100644 index 0000000..57083b4 --- /dev/null +++ b/analog circuits/voltage tripler/voltage tripler-cache.lib @@ -0,0 +1,102 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Diode:1N4001 +# +DEF Diode:1N4001 D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Diode:1N4001" 0 -100 50 H V C CNN +F2 "Diode_THT:D_DO-41_SOD81_P10.16mm_Horizontal" 0 -175 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS 1N4002 1N4003 1N4004 1N4005 1N4006 1N4007 BA157 BA158 BA159 +$FPLIST + D*DO?41* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 50 -50 -50 N +P 2 0 1 0 50 0 -50 0 N +P 4 0 1 8 50 50 50 -50 -50 0 50 50 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/voltage tripler/voltage tripler.bak b/analog circuits/voltage tripler/voltage tripler.bak new file mode 100644 index 0000000..5d97c66 --- /dev/null +++ b/analog circuits/voltage tripler/voltage tripler.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 4 +LIBS:voltage tripler-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0A1122 +P 3150 4200 +F 0 "V1" H 3378 4246 50 0000 L CNN +F 1 "VSOURCE" H 3378 4155 50 0000 L CNN +F 2 "" H 3150 4200 50 0001 C CNN +F 3 "" H 3150 4200 50 0001 C CNN +F 4 "V" H 3150 4200 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 15 10k)" H 3150 4200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3150 4200 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3150 4200 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D2 +U 1 1 5B0A119A +P 4300 4050 +F 0 "D2" H 4300 3834 50 0000 C CNN +F 1 "D_ALT" H 4300 3925 50 0000 C CNN +F 2 "" H 4300 4050 50 0001 C CNN +F 3 "~" H 4300 4050 50 0001 C CNN + 1 4300 4050 + -1 0 0 1 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0A1225 +P 4100 3550 +F 0 "D1" V 4146 3471 50 0000 R CNN +F 1 "D_ALT" V 4055 3471 50 0000 R CNN +F 2 "" H 4100 3550 50 0001 C CNN +F 3 "~" H 4100 3550 50 0001 C CNN + 1 4100 3550 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0A12C0 +P 4800 3600 +F 0 "C2" V 4548 3600 50 0000 C CNN +F 1 "100u" V 4639 3600 50 0000 C CNN +F 2 "" H 4838 3450 50 0001 C CNN +F 3 "~" H 4800 3600 50 0001 C CNN + 1 4800 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0A1393 +P 4050 4750 +F 0 "C1" H 3935 4704 50 0000 R CNN +F 1 "100u" H 3935 4795 50 0000 R CNN +F 2 "" H 4088 4600 50 0001 C CNN +F 3 "~" H 4050 4750 50 0001 C CNN + 1 4050 4750 + -1 0 0 1 +$EndComp +$Comp +L Device:D_ALT D3 +U 1 1 5B0A142D +P 5650 3600 +F 0 "D3" H 5650 3384 50 0000 C CNN +F 1 "D_ALT" H 5650 3475 50 0000 C CNN +F 2 "" H 5650 3600 50 0001 C CNN +F 3 "~" H 5650 3600 50 0001 C CNN + 1 5650 3600 + -1 0 0 1 +$EndComp +$Comp +L Device:C C3 +U 1 1 5B0A14A1 +P 5850 4100 +F 0 "C3" H 5735 4054 50 0000 R CNN +F 1 "100u" H 5735 4145 50 0000 R CNN +F 2 "" H 5888 3950 50 0001 C CNN +F 3 "~" H 5850 4100 50 0001 C CNN + 1 5850 4100 + -1 0 0 1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0A1525 +P 6250 4100 +F 0 "R1" H 6320 4146 50 0000 L CNN +F 1 "40k" H 6320 4055 50 0000 L CNN +F 2 "" V 6180 4100 50 0001 C CNN +F 3 "~" H 6250 4100 50 0001 C CNN + 1 6250 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 3900 3150 3400 +Wire Wire Line + 3150 3400 4100 3400 +Wire Wire Line + 4100 3400 4450 3400 +Wire Wire Line + 4650 3400 4650 3600 +Connection ~ 4100 3400 +Wire Wire Line + 4100 3700 4100 4050 +Wire Wire Line + 4100 4050 4150 4050 +Wire Wire Line + 4450 4050 4450 3400 +Connection ~ 4450 3400 +Wire Wire Line + 4450 3400 4650 3400 +Wire Wire Line + 4100 4050 4100 4600 +Wire Wire Line + 4100 4600 4050 4600 +Connection ~ 4100 4050 +Wire Wire Line + 4950 3600 5500 3600 +Wire Wire Line + 5800 3600 5850 3600 +Wire Wire Line + 5850 3600 5850 3950 +Wire Wire Line + 5850 3600 6250 3600 +Wire Wire Line + 6250 3600 6250 3950 +Connection ~ 5850 3600 +Wire Wire Line + 3150 4500 3150 4900 +Wire Wire Line + 3150 4900 4050 4900 +Wire Wire Line + 4050 4900 4800 4900 +Wire Wire Line + 6250 4900 6250 4250 +Connection ~ 4050 4900 +Wire Wire Line + 5850 4250 5850 4900 +Connection ~ 5850 4900 +Wire Wire Line + 5850 4900 6250 4900 +$Comp +L power:GND #PWR01 +U 1 1 5B0A1C04 +P 4800 5200 +F 0 "#PWR01" H 4800 4950 50 0001 C CNN +F 1 "GND" H 4805 5027 50 0000 C CNN +F 2 "" H 4800 5200 50 0001 C CNN +F 3 "" H 4800 5200 50 0001 C CNN + 1 4800 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 5200 4800 5150 +Connection ~ 4800 4900 +Wire Wire Line + 4800 4900 5850 4900 +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 5B0A1F21 +P 5150 5150 +F 0 "#FLG0101" H 5150 5225 50 0001 C CNN +F 1 "PWR_FLAG" H 5150 5324 50 0000 C CNN +F 2 "" H 5150 5150 50 0001 C CNN +F 3 "~" H 5150 5150 50 0001 C CNN + 1 5150 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 5150 4800 5150 +Connection ~ 4800 5150 +Wire Wire Line + 4800 5150 4800 4900 +Text GLabel 6700 3400 0 50 Output ~ 0 +out +Wire Wire Line + 6700 3400 7100 3400 +Wire Wire Line + 7100 3400 7100 2950 +Wire Wire Line + 7100 2950 6250 2950 +Wire Wire Line + 6250 2950 6250 3600 +Connection ~ 6250 3600 +Text GLabel 2300 3100 0 50 Input ~ 0 +ip +Wire Wire Line + 2300 3100 3150 3100 +Wire Wire Line + 3150 3100 3150 3400 +Connection ~ 3150 3400 +Text Notes 7650 5350 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/voltage tripler/voltage tripler.cir b/analog circuits/voltage tripler/voltage tripler.cir new file mode 100644 index 0000000..e8980ac --- /dev/null +++ b/analog circuits/voltage tripler/voltage tripler.cir @@ -0,0 +1,11 @@ +.title KiCad schematic +V1 ip GND sin(0 10 1k) +C1 GND Net-_C1-Pad2_ 100u +C3 GND out 100u +D3 Net-_C2-Pad2_ out 1N4001 +D2 Net-_C1-Pad2_ Net-_C2-Pad2_ 1N4001 +D1 ip Net-_C1-Pad2_ 1N4001 +R1 out GND 40k +C2 ip Net-_C2-Pad2_ 100u +.tran .25m 30m +.end diff --git a/analog circuits/voltage tripler/voltage tripler.kicad_pcb b/analog circuits/voltage tripler/voltage tripler.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/voltage tripler/voltage tripler.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/voltage tripler/voltage tripler.pro b/analog circuits/voltage tripler/voltage tripler.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/voltage tripler/voltage tripler.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/voltage tripler/voltage tripler.sch b/analog circuits/voltage tripler/voltage tripler.sch new file mode 100644 index 0000000..48fd16c --- /dev/null +++ b/analog circuits/voltage tripler/voltage tripler.sch @@ -0,0 +1,226 @@ +EESchema Schematic File Version 4 +LIBS:voltage tripler-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0A1122 +P 3150 4200 +F 0 "V1" H 3378 4246 50 0000 L CNN +F 1 "VSOURCE" H 3378 4155 50 0000 L CNN +F 2 "" H 3150 4200 50 0001 C CNN +F 3 "" H 3150 4200 50 0001 C CNN +F 4 "V" H 3150 4200 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 5 1000)" H 3150 4200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3150 4200 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3150 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diff --git a/digital ciruits/FA/FA.cir b/digital ciruits/FA/FA.cir new file mode 100644 index 0000000..76afcd6 --- /dev/null +++ b/digital ciruits/FA/FA.cir @@ -0,0 +1,15 @@ +.title KiCad schematic +.include "C:\Users\Mind\Downloads\Kicad\new_file\libs\spice_models.lib" +V1 a GND dc 0 +R2 GND carry 10meg +R1 GND sum 10meg +X5 Net-_X3-Pad3_ Net-_X4-Pad3_ carry VDD OR +X1 a b Net-_X1-Pad3_ VDD XOR +X2 Net-_X1-Pad3_ c sum VDD XOR +X3 c Net-_X1-Pad3_ Net-_X3-Pad3_ VDD AND +X4 b a Net-_X4-Pad3_ VDD AND +V2 b GND dc 5 +V3 c GND dc 5 +V4 VDD GND dc 5 +.tran .25m 30m +.end diff --git a/digital ciruits/FA/FA.kicad_pcb b/digital ciruits/FA/FA.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/FA/FA.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/FA/FA.pro b/digital ciruits/FA/FA.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/FA/FA.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/FA/FA.sch b/digital ciruits/FA/FA.sch new file mode 100644 index 0000000..62185eb --- /dev/null +++ b/digital ciruits/FA/FA.sch @@ -0,0 +1,425 @@ +EESchema Schematic File Version 4 +LIBS:FA-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 7700 3650 7700 3050 +Wire Wire Line + 7700 3050 7950 3050 +Wire Wire Line + 5350 2300 5350 3550 +Wire Wire Line + 5350 3550 6850 3550 +Wire Wire Line + 5350 2100 5200 2100 +Wire Wire Line + 5150 2100 5150 3750 +Wire Wire Line + 5150 3750 6850 3750 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B04F8C7 +P 2350 2450 +F 0 "V1" H 2578 2496 50 0000 L CNN +F 1 "VSOURCE" H 2578 2405 50 0000 L CNN +F 2 "" H 2350 2450 50 0001 C CNN +F 3 "" H 2350 2450 50 0001 C CNN +F 4 "V" H 2350 2450 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0" H 2350 2450 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 2450 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 2450 + 1 0 0 -1 +$EndComp +Connection ~ 5200 2100 +Wire Wire Line + 5200 2100 5150 2100 +Wire Wire Line + 5000 2100 5000 2300 +Wire Wire Line + 5000 2300 5350 2300 +$Comp +L power:GND #PWR01 +U 1 1 5B050305 +P 2800 4050 +F 0 "#PWR01" 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Wire Line + 6050 2950 6850 2950 +Wire Wire Line + 6050 2350 6050 2950 +Wire Wire Line + 6800 2500 6800 2750 +Wire Wire Line + 6800 2750 6850 2750 +$Comp +L FA-rescue:and-and_sub X3 +U 1 1 5B321D1B +P 7100 2800 +F 0 "X3" H 7150 2528 50 0000 C CNN +F 1 "and" H 7150 2600 50 0000 C CNN +F 2 "" H 7100 2800 50 0001 C CNN +F 3 "" H 7100 2800 50 0001 C CNN +F 4 "X" H 7100 2800 50 0001 C CNN "Spice_Primitive" +F 5 "AND" H 7100 2800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7100 2800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "C:\\Users\\Mind\\Downloads\\Kicad\\new_file\\libs\\spice_models.lib" H 7100 2800 50 0001 C CNN "Spice_Lib_File" + 1 7100 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7350 2850 7950 2850 +$Comp +L power:VDD #PWR06 +U 1 1 5B332956 +P 6050 2100 +F 0 "#PWR06" H 6050 1950 50 0001 C CNN +F 1 "VDD" H 6067 2273 50 0000 C CNN +F 2 "" H 6050 2100 50 0001 C CNN +F 3 "" H 6050 2100 50 0001 C CNN + 1 6050 2100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR07 +U 1 1 5B3329A9 +P 7050 2100 +F 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10417 2173 50 0000 C CNN +F 2 "" H 10400 2000 50 0001 C CNN +F 3 "" H 10400 2000 50 0001 C CNN + 1 10400 2000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR012 +U 1 1 5B332D48 +P 10400 3050 +F 0 "#PWR012" H 10400 2800 50 0001 C CNN +F 1 "GND" H 10405 2877 50 0000 C CNN +F 2 "" H 10400 3050 50 0001 C CNN +F 3 "" H 10400 3050 50 0001 C CNN + 1 10400 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10400 2300 10400 2000 +Wire Wire Line + 10400 3050 10400 2900 +$Comp +L FA-rescue:and-and_sub X4 +U 1 1 5B334BB6 +P 7100 3600 +F 0 "X4" H 7150 3328 50 0000 C CNN +F 1 "and" H 7150 3400 50 0000 C CNN +F 2 "" H 7100 3600 50 0001 C CNN +F 3 "" H 7100 3600 50 0001 C CNN +F 4 "X" H 7100 3600 50 0001 C CNN "Spice_Primitive" +F 5 "AND" H 7100 3600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7100 3600 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "C:\\Users\\Mind\\Downloads\\Kicad\\new_file\\libs\\spice_models.lib" H 7100 3600 50 0001 C CNN "Spice_Lib_File" + 1 7100 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 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1 0 0 -1 +$EndComp +Text Notes 7900 5450 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/digital ciruits/FA/sym-lib-table b/digital ciruits/FA/sym-lib-table new file mode 100644 index 0000000..548b02d --- /dev/null +++ b/digital ciruits/FA/sym-lib-table @@ -0,0 +1,6 @@ +(sym_lib_table
+ (lib (name and_sub)(type Legacy)(uri H:/and_sub/and_sub.lib)(options "")(descr ""))
+ (lib (name or_sub)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/or_sub/or_sub.lib)(options "")(descr ""))
+ (lib (name xor_sub)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/xor_sub/xor_sub.lib)(options "")(descr ""))
+ (lib (name FA-rescue)(type Legacy)(uri ${KIPRJMOD}/FA-rescue.lib)(options "")(descr ""))
+)
diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB-cache.lib b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB-cache.lib new file mode 100644 index 0000000..49fc6b3 --- /dev/null +++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB-cache.lib @@ -0,0 +1,69 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# basic_gates:jkff +# +DEF basic_gates:jkff X 0 40 Y Y 1 F N +F0 "X" 0 -350 50 H V C CNN +F1 "basic_gates:jkff" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -350 250 350 -300 0 1 0 N +X J 1 -450 200 100 R 50 50 1 1 I +X clk 2 -450 0 100 R 50 50 1 1 I +X k 3 -450 -200 100 R 50 50 1 1 I +X vdd 4 0 350 100 D 50 50 1 1 O +X q 5 450 150 100 L 50 50 1 1 O +X nq 6 450 -200 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.bak b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.bak new file mode 100644 index 0000000..0db1d6a --- /dev/null +++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.bak @@ -0,0 +1,268 @@ +EESchema Schematic File Version 4 +LIBS:JK_FLL_SUB-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L basic_gates:jkff X1 +U 1 1 5B2A00A5 +P 5500 3950 +F 0 "X1" H 5500 3578 50 0000 C CNN +F 1 "jkff" H 5500 3487 50 0000 C CNN +F 2 "" H 5500 3950 50 0001 C CNN +F 3 "" H 5500 3950 50 0001 C CNN +F 4 "X" H 5500 3950 50 0001 C CNN "Spice_Primitive" +F 5 "JKFLIPFLOP" H 5500 3950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 3950 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad_examples/masterslave_jkff/masterslave_jkff.sub" H 5500 3950 50 0001 C CNN "Spice_Lib_File" + 1 5500 3950 + 1 0 0 -1 +$EndComp +Text GLabel 4450 3750 0 50 Input ~ 0 +j +Text GLabel 3700 3400 0 50 Input ~ 0 +clk +Text GLabel 4450 4150 0 50 Input ~ 0 +k +Text GLabel 5400 3250 0 50 Input ~ 0 +vdd +Wire Wire Line + 5500 3600 5500 3250 +Wire Wire Line + 5500 3250 5400 3250 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B2A08D7 +P 2950 3800 +F 0 "V1" H 3178 3846 50 0000 L CNN +F 1 "VSOURCE" H 3178 3755 50 0000 L CNN +F 2 "" H 2950 3800 50 0001 C CNN +F 3 "" H 2950 3800 50 0001 C CNN +F 4 "V" H 2950 3800 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 2950 3800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2950 3800 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2950 3800 + 1 0 0 -1 +$EndComp +Text GLabel 2900 3200 0 50 Input ~ 0 +j +$Comp +L power:GND #PWR01 +U 1 1 5B2A093F +P 2950 4250 +F 0 "#PWR01" H 2950 4000 50 0001 C CNN +F 1 "GND" H 2955 4077 50 0000 C CNN +F 2 "" H 2950 4250 50 0001 C CNN +F 3 "" H 2950 4250 50 0001 C CNN + 1 2950 4250 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B2A0956 +P 3700 5100 +F 0 "V2" H 3928 5146 50 0000 L CNN +F 1 "VSOURCE" H 3928 5055 50 0000 L CNN +F 2 "" H 3700 5100 50 0001 C CNN +F 3 "" H 3700 5100 50 0001 C CNN +F 4 "V" H 3700 5100 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3)" H 3700 5100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3700 5100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3700 5100 + 1 0 0 -1 +$EndComp +Text GLabel 3650 4500 0 50 Input ~ 0 +clk +$Comp +L power:GND #PWR02 +U 1 1 5B2A09B2 +P 3700 5550 +F 0 "#PWR02" H 3700 5300 50 0001 C CNN +F 1 "GND" H 3705 5377 50 0000 C CNN +F 2 "" H 3700 5550 50 0001 C CNN +F 3 "" H 3700 5550 50 0001 C CNN + 1 3700 5550 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B2A09CC +P 5600 5200 +F 0 "V3" H 5828 5246 50 0000 L CNN +F 1 "VSOURCE" H 5828 5155 50 0000 L CNN +F 2 "" H 5600 5200 50 0001 C CNN +F 3 "" H 5600 5200 50 0001 C CNN +F 4 "V" H 5600 5200 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 5600 5200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5600 5200 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5600 5200 + 1 0 0 -1 +$EndComp +Text GLabel 5600 4650 0 50 Input ~ 0 +k +$Comp +L power:GND #PWR03 +U 1 1 5B2A0A2A +P 5600 5650 +F 0 "#PWR03" H 5600 5400 50 0001 C CNN +F 1 "GND" H 5605 5477 50 0000 C CNN +F 2 "" H 5600 5650 50 0001 C CNN +F 3 "" H 5600 5650 50 0001 C CNN + 1 5600 5650 + 1 0 0 -1 +$EndComp +Text GLabel 6850 4650 0 50 Input ~ 0 +vdd +$Comp +L pspice:VSOURCE V4 +U 1 1 5B2A0A5B +P 6900 5150 +F 0 "V4" H 7128 5196 50 0000 L CNN +F 1 "VSOURCE" H 7128 5105 50 0000 L CNN +F 2 "" H 6900 5150 50 0001 C CNN +F 3 "" H 6900 5150 50 0001 C CNN +F 4 "V" H 6900 5150 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 6900 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6900 5150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 6900 5150 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B2A0AB6 +P 6900 5600 +F 0 "#PWR04" H 6900 5350 50 0001 C CNN +F 1 "GND" H 6905 5427 50 0000 C CNN +F 2 "" H 6900 5600 50 0001 C CNN +F 3 "" H 6900 5600 50 0001 C CNN + 1 6900 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 4650 6900 4650 +Wire Wire Line + 6900 4650 6900 4850 +Wire Wire Line + 6900 5450 6900 5600 +Wire Wire Line + 5600 5500 5600 5650 +Wire Wire Line + 5600 4900 5600 4650 +Wire Wire Line + 3650 4500 3700 4500 +Wire Wire Line + 3700 4500 3700 4800 +Wire Wire Line + 3700 5400 3700 5550 +Wire Wire Line + 2950 4100 2950 4250 +Wire Wire Line + 2950 3500 2950 3200 +Wire Wire Line + 2950 3200 2900 3200 +Text Notes 7900 4750 0 50 ~ 0 +.tran 1m 400m +$Comp +L Device:R R1 +U 1 1 5B2D9D54 +P 7150 3200 +F 0 "R1" V 6943 3200 50 0000 C CNN +F 1 "10meg" V 7034 3200 50 0000 C CNN +F 2 "" V 7080 3200 50 0001 C CNN +F 3 "~" H 7150 3200 50 0001 C CNN + 1 7150 3200 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR05 +U 1 1 5B2D9F98 +P 7500 3200 +F 0 "#PWR05" H 7500 2950 50 0001 C CNN +F 1 "GND" H 7505 3027 50 0000 C CNN +F 2 "" H 7500 3200 50 0001 C CNN +F 3 "" H 7500 3200 50 0001 C CNN + 1 7500 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 3200 7300 3200 +Text GLabel 6700 3300 0 50 Output ~ 0 +q0 +Wire Wire Line + 6700 3300 6950 3300 +Wire Wire Line + 7000 3300 7000 3200 +Wire Wire Line + 4450 3750 5050 3750 +Wire Wire Line + 4450 4150 5050 4150 +Wire Wire Line + 6950 3800 6950 3300 +Wire Wire Line + 5950 3800 6950 3800 +Connection ~ 6950 3300 +Wire Wire Line + 6950 3300 7000 3300 +Wire Wire Line + 3700 3400 3900 3400 +Wire Wire Line + 3900 3400 3900 3100 +Wire Wire Line + 4700 3100 4700 3650 +Wire Wire Line + 4700 3650 3900 3650 +Wire Wire Line + 3900 3650 3900 3950 +Wire Wire Line + 3900 3950 5050 3950 +Wire Wire Line + 3900 3100 4700 3100 +$Comp +L Device:R R2 +U 1 1 5B2B6E7D +P 7250 4200 +F 0 "R2" V 7043 4200 50 0000 C CNN +F 1 "10meg" V 7134 4200 50 0000 C CNN +F 2 "" V 7180 4200 50 0001 C CNN +F 3 "~" H 7250 4200 50 0001 C CNN + 1 7250 4200 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 5B2B6EB2 +P 7550 4200 +F 0 "#PWR0101" H 7550 3950 50 0001 C CNN +F 1 "GND" H 7555 4027 50 0000 C CNN +F 2 "" H 7550 4200 50 0001 C CNN +F 3 "" H 7550 4200 50 0001 C CNN + 1 7550 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7550 4200 7400 4200 +Wire Wire Line + 7100 4200 6950 4200 +Wire Wire Line + 5950 4200 5950 4150 +Text GLabel 6800 4050 0 50 Output ~ 0 +q1 +Wire Wire Line + 6800 4050 6950 4050 +Wire Wire Line + 6950 4050 6950 4200 +Connection ~ 6950 4200 +Wire Wire Line + 6950 4200 5950 4200 +$EndSCHEMATC diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.cir b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.cir new file mode 100644 index 0000000..031d2b3 --- /dev/null +++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.cir @@ -0,0 +1,11 @@ +.title KiCad schematic +.include "/home/akshay/kicad_examples/masterslave_jkff/masterslave_jkff.sub" +X1 j clk k vdd q0 q1 JKFLIPFLOP +V1 j GND dc 3.3 +V2 clk GND dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3) +V3 k GND dc 3.3 +V4 vdd GND dc 3.3 +R1 GND q0 10meg +R2 GND q1 10meg +.tran .25m 30m +.end diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.kicad_pcb b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.pro b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.sch b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.sch new file mode 100644 index 0000000..9a87a0b --- /dev/null +++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.sch @@ -0,0 +1,268 @@ +EESchema Schematic File Version 4 +LIBS:JK_FLL_SUB-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L basic_gates:jkff X1 +U 1 1 5B2A00A5 +P 5500 3950 +F 0 "X1" H 5500 3578 50 0000 C CNN +F 1 "jkff" H 5500 3487 50 0000 C CNN +F 2 "" H 5500 3950 50 0001 C CNN +F 3 "" H 5500 3950 50 0001 C CNN +F 4 "X" H 5500 3950 50 0001 C CNN "Spice_Primitive" +F 5 "JKFLIPFLOP" H 5500 3950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 3950 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/kicad_examples/masterslave_jkff/masterslave_jkff.sub" H 5500 3950 50 0001 C CNN "Spice_Lib_File" + 1 5500 3950 + 1 0 0 -1 +$EndComp +Text GLabel 4450 3750 0 50 Input ~ 0 +j +Text GLabel 3700 3400 0 50 Input ~ 0 +clk +Text GLabel 4450 4150 0 50 Input ~ 0 +k +Text GLabel 5400 3250 0 50 Input ~ 0 +vdd +Wire Wire Line + 5500 3600 5500 3250 +Wire Wire Line + 5500 3250 5400 3250 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B2A08D7 +P 2950 3800 +F 0 "V1" H 3178 3846 50 0000 L CNN +F 1 "VSOURCE" H 3178 3755 50 0000 L CNN +F 2 "" H 2950 3800 50 0001 C CNN +F 3 "" H 2950 3800 50 0001 C CNN +F 4 "V" H 2950 3800 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 2950 3800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2950 3800 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2950 3800 + 1 0 0 -1 +$EndComp +Text GLabel 2900 3200 0 50 Input ~ 0 +j +$Comp +L power:GND #PWR01 +U 1 1 5B2A093F +P 2950 4250 +F 0 "#PWR01" H 2950 4000 50 0001 C CNN +F 1 "GND" H 2955 4077 50 0000 C CNN +F 2 "" H 2950 4250 50 0001 C CNN +F 3 "" H 2950 4250 50 0001 C CNN + 1 2950 4250 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B2A0956 +P 3700 5100 +F 0 "V2" H 3928 5146 50 0000 L CNN +F 1 "VSOURCE" H 3928 5055 50 0000 L CNN +F 2 "" H 3700 5100 50 0001 C CNN +F 3 "" H 3700 5100 50 0001 C CNN +F 4 "V" H 3700 5100 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3)" H 3700 5100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3700 5100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3700 5100 + 1 0 0 -1 +$EndComp +Text GLabel 3650 4500 0 50 Input ~ 0 +clk +$Comp +L power:GND #PWR02 +U 1 1 5B2A09B2 +P 3700 5550 +F 0 "#PWR02" H 3700 5300 50 0001 C CNN +F 1 "GND" H 3705 5377 50 0000 C CNN +F 2 "" H 3700 5550 50 0001 C CNN +F 3 "" H 3700 5550 50 0001 C CNN + 1 3700 5550 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B2A09CC +P 5600 5200 +F 0 "V3" H 5828 5246 50 0000 L CNN +F 1 "VSOURCE" H 5828 5155 50 0000 L CNN +F 2 "" H 5600 5200 50 0001 C CNN +F 3 "" H 5600 5200 50 0001 C CNN +F 4 "V" H 5600 5200 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 5600 5200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5600 5200 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5600 5200 + 1 0 0 -1 +$EndComp +Text GLabel 5600 4650 0 50 Input ~ 0 +k +$Comp +L power:GND #PWR03 +U 1 1 5B2A0A2A +P 5600 5650 +F 0 "#PWR03" H 5600 5400 50 0001 C CNN +F 1 "GND" H 5605 5477 50 0000 C CNN +F 2 "" H 5600 5650 50 0001 C CNN +F 3 "" H 5600 5650 50 0001 C CNN + 1 5600 5650 + 1 0 0 -1 +$EndComp +Text GLabel 6850 4650 0 50 Input ~ 0 +vdd +$Comp +L pspice:VSOURCE V4 +U 1 1 5B2A0A5B +P 6900 5150 +F 0 "V4" H 7128 5196 50 0000 L CNN +F 1 "VSOURCE" H 7128 5105 50 0000 L CNN +F 2 "" H 6900 5150 50 0001 C CNN +F 3 "" H 6900 5150 50 0001 C CNN +F 4 "V" H 6900 5150 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 6900 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6900 5150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 6900 5150 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B2A0AB6 +P 6900 5600 +F 0 "#PWR04" H 6900 5350 50 0001 C CNN +F 1 "GND" H 6905 5427 50 0000 C CNN +F 2 "" H 6900 5600 50 0001 C CNN +F 3 "" H 6900 5600 50 0001 C CNN + 1 6900 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 4650 6900 4650 +Wire Wire Line + 6900 4650 6900 4850 +Wire Wire Line + 6900 5450 6900 5600 +Wire Wire Line + 5600 5500 5600 5650 +Wire Wire Line + 5600 4900 5600 4650 +Wire Wire Line + 3650 4500 3700 4500 +Wire Wire Line + 3700 4500 3700 4800 +Wire Wire Line + 3700 5400 3700 5550 +Wire Wire Line + 2950 4100 2950 4250 +Wire Wire Line + 2950 3500 2950 3200 +Wire Wire Line + 2950 3200 2900 3200 +Text Notes 7900 4750 0 50 ~ 0 +.tran .25m 30m +$Comp +L Device:R R1 +U 1 1 5B2D9D54 +P 7150 3200 +F 0 "R1" V 6943 3200 50 0000 C CNN +F 1 "10meg" V 7034 3200 50 0000 C CNN +F 2 "" V 7080 3200 50 0001 C CNN +F 3 "~" H 7150 3200 50 0001 C CNN + 1 7150 3200 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR05 +U 1 1 5B2D9F98 +P 7500 3200 +F 0 "#PWR05" H 7500 2950 50 0001 C CNN +F 1 "GND" H 7505 3027 50 0000 C CNN +F 2 "" H 7500 3200 50 0001 C CNN +F 3 "" H 7500 3200 50 0001 C CNN + 1 7500 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 3200 7300 3200 +Text GLabel 6700 3300 0 50 Output ~ 0 +q0 +Wire Wire Line + 6700 3300 6950 3300 +Wire Wire Line + 7000 3300 7000 3200 +Wire Wire Line + 4450 3750 5050 3750 +Wire Wire Line + 4450 4150 5050 4150 +Wire Wire Line + 6950 3800 6950 3300 +Wire Wire Line + 5950 3800 6950 3800 +Connection ~ 6950 3300 +Wire Wire Line + 6950 3300 7000 3300 +Wire Wire Line + 3700 3400 3900 3400 +Wire Wire Line + 3900 3400 3900 3100 +Wire Wire Line + 4700 3100 4700 3650 +Wire Wire Line + 4700 3650 3900 3650 +Wire Wire Line + 3900 3650 3900 3950 +Wire Wire Line + 3900 3950 5050 3950 +Wire Wire Line + 3900 3100 4700 3100 +$Comp +L Device:R R2 +U 1 1 5B2B6E7D +P 7250 4200 +F 0 "R2" V 7043 4200 50 0000 C CNN +F 1 "10meg" V 7134 4200 50 0000 C CNN +F 2 "" V 7180 4200 50 0001 C CNN +F 3 "~" H 7250 4200 50 0001 C CNN + 1 7250 4200 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 5B2B6EB2 +P 7550 4200 +F 0 "#PWR0101" H 7550 3950 50 0001 C CNN +F 1 "GND" H 7555 4027 50 0000 C CNN +F 2 "" H 7550 4200 50 0001 C CNN +F 3 "" H 7550 4200 50 0001 C CNN + 1 7550 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7550 4200 7400 4200 +Wire Wire Line + 7100 4200 6950 4200 +Wire Wire Line + 5950 4200 5950 4150 +Text GLabel 6800 4050 0 50 Output ~ 0 +q1 +Wire Wire Line + 6800 4050 6950 4050 +Wire Wire Line + 6950 4050 6950 4200 +Connection ~ 6950 4200 +Wire Wire Line + 6950 4200 5950 4200 +$EndSCHEMATC diff --git a/digital ciruits/JK_FLL_SUB/sym-lib-table b/digital ciruits/JK_FLL_SUB/sym-lib-table new file mode 100644 index 0000000..c79a55b --- /dev/null +++ b/digital ciruits/JK_FLL_SUB/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (lib (name basic_gates)(type Legacy)(uri /home/akshay/kicad_examples/and_sub/basic_gates.lib)(options "")(descr "")) + (lib (name sim_logic)(type Legacy)(uri /home/akshay/Downloads/kicad-simulation-examples-master/libs/sim_logic.lib)(options "")(descr "")) +) diff --git a/digital ciruits/README.md b/digital ciruits/README.md new file mode 100644 index 0000000..55646d2 --- /dev/null +++ b/digital ciruits/README.md @@ -0,0 +1,2 @@ +# kicad-simulation-examples +Example projects for spice simulation(digital circuits) in KiCad diff --git a/digital ciruits/and gate/and gate-cache.lib b/digital ciruits/and gate/and gate-cache.lib new file mode 100644 index 0000000..28aadfe --- /dev/null +++ b/digital ciruits/and gate/and gate-cache.lib @@ -0,0 +1,68 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/and gate/and gate.bak b/digital ciruits/and gate/and gate.bak new file mode 100644 index 0000000..7a004bd --- /dev/null +++ b/digital ciruits/and gate/and gate.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B28B068 +P 4150 3850 +F 0 "X1" H 4350 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 4350 3487 50 0000 C CNN +F 2 "" H 4150 3850 50 0001 C CNN +F 3 "" H 4150 3850 50 0001 C CNN +F 4 "X" H 4150 3850 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4150 3850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4150 3850 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 4150 3850 50 0001 C CNN "Spice_Lib_File" + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B28B0D0 +P 5900 3850 +F 0 "X2" H 6100 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 6100 3487 50 0000 C CNN +F 2 "" H 5900 3850 50 0001 C CNN +F 3 "" H 5900 3850 50 0001 C CNN + 1 5900 3850 + 1 0 0 -1 +$EndComp +Text GLabel 2850 3750 0 50 Input ~ 0 +1 +Wire Wire Line + 2850 3750 3950 3750 +Text GLabel 2850 3950 0 50 Input ~ 0 +2 +Wire Wire Line + 2850 3950 3950 3950 +Text GLabel 7250 3150 0 50 Output ~ 0 +3 +$Comp +L Device:R R1 +U 1 1 5B28B182 +P 7650 3850 +F 0 "R1" V 7443 3850 50 0000 C CNN +F 1 "10meg" V 7534 3850 50 0000 C CNN +F 2 "" V 7580 3850 50 0001 C CNN +F 3 "~" H 7650 3850 50 0001 C CNN + 1 7650 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28B214 +P 8150 4050 +F 0 "#PWR04" H 8150 3800 50 0001 C CNN +F 1 "GND" H 8155 3877 50 0000 C CNN +F 2 "" H 8150 4050 50 0001 C CNN +F 3 "" H 8150 4050 50 0001 C CNN + 1 8150 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 4050 8150 3850 +Wire Wire Line + 8150 3850 7800 3850 +Wire Wire Line + 7500 3850 7350 3850 +Wire Wire Line + 7250 3150 7350 3150 +Wire Wire Line + 7350 3150 7350 3850 +Connection ~ 7350 3850 +Wire Wire Line + 7350 3850 6500 3850 +Wire Wire Line + 4750 3850 4750 3750 +Wire Wire Line + 4750 3750 5700 3750 +Wire Wire Line + 4750 3850 4750 3950 +Wire Wire Line + 4750 3950 5700 3950 +Connection ~ 4750 3850 +Text GLabel 3850 2900 0 50 Input ~ 0 +4 +Wire Wire Line + 3850 2900 4350 2900 +Wire Wire Line + 6100 2900 6100 3450 +Wire Wire Line + 4350 3450 4350 2900 +Connection ~ 4350 2900 +Wire Wire Line + 4350 2900 6100 2900 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28B632 +P 1800 3400 +F 0 "V1" H 2028 3446 50 0000 L CNN +F 1 "VSOURCE" H 2028 3355 50 0000 L CNN +F 2 "" H 1800 3400 50 0001 C CNN +F 3 "" H 1800 3400 50 0001 C CNN +F 4 "V" H 1800 3400 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1800 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1800 3400 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1800 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B28B678 +P 1800 3950 +F 0 "#PWR01" H 1800 3700 50 0001 C CNN +F 1 "GND" H 1805 3777 50 0000 C CNN +F 2 "" H 1800 3950 50 0001 C CNN +F 3 "" H 1800 3950 50 0001 C CNN + 1 1800 3950 + 1 0 0 -1 +$EndComp +Text GLabel 1700 2750 0 50 Input ~ 0 +1 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28B69D +P 2050 5600 +F 0 "V2" H 2278 5646 50 0000 L CNN +F 1 "VSOURCE" H 2278 5555 50 0000 L CNN +F 2 "" H 2050 5600 50 0001 C CNN +F 3 "" H 2050 5600 50 0001 C CNN +F 4 "V" H 2050 5600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2050 5600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2050 5600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2050 5600 + 1 0 0 -1 +$EndComp +Text GLabel 1900 4950 0 50 Input ~ 0 +2 +$Comp +L power:GND #PWR02 +U 1 1 5B28B717 +P 2050 6100 +F 0 "#PWR02" H 2050 5850 50 0001 C CNN +F 1 "GND" H 2055 5927 50 0000 C CNN +F 2 "" H 2050 6100 50 0001 C CNN +F 3 "" H 2050 6100 50 0001 C CNN + 1 2050 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 6100 2050 5900 +Wire Wire Line + 2050 5300 2050 4950 +Wire Wire Line + 2050 4950 1900 4950 +Wire Wire Line + 1800 3100 1800 2750 +Wire Wire Line + 1800 2750 1700 2750 +Wire Wire Line + 1800 3950 1800 3700 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28BEA7 +P 7600 5550 +F 0 "V3" H 7828 5596 50 0000 L CNN +F 1 "VSOURCE" H 7828 5505 50 0000 L CNN +F 2 "" H 7600 5550 50 0001 C CNN +F 3 "" H 7600 5550 50 0001 C CNN +F 4 "V" H 7600 5550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 7600 5550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7600 5550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7600 5550 + 1 0 0 -1 +$EndComp +Text GLabel 7050 4800 0 50 Input ~ 0 +4 +Wire Wire Line + 7050 4800 7600 4800 +Wire Wire Line + 7600 4800 7600 5250 +$Comp +L power:GND #PWR03 +U 1 1 5B28C1DA +P 7600 6000 +F 0 "#PWR03" H 7600 5750 50 0001 C CNN +F 1 "GND" H 7605 5827 50 0000 C CNN +F 2 "" H 7600 6000 50 0001 C CNN +F 3 "" H 7600 6000 50 0001 C CNN + 1 7600 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 6000 7600 5850 +Text Notes 8750 5600 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and gate/and gate.cir b/digital ciruits/and gate/and gate.cir new file mode 100644 index 0000000..c69b756 --- /dev/null +++ b/digital ciruits/and gate/and gate.cir @@ -0,0 +1,10 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" +X1 1 2 Net-_X1-PadOut_ 4 NAND +X2 Net-_X1-PadOut_ Net-_X1-PadOut_ 3 4 NAND +R1 GND 3 10meg +V1 1 GND dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 2 GND dc 0 pulse(0 3.3 50m 0 0 50m 100m) +V3 4 GND dc 3.3 +.tran 1m 400m +.end diff --git a/digital ciruits/and gate/and gate.kicad_pcb b/digital ciruits/and gate/and gate.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/and gate/and gate.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/and gate/and gate.pro b/digital ciruits/and gate/and gate.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/and gate/and gate.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/and gate/and gate.sch b/digital ciruits/and gate/and gate.sch new file mode 100644 index 0000000..912ac63 --- /dev/null +++ b/digital ciruits/and gate/and gate.sch @@ -0,0 +1,212 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B28B068 +P 4150 3850 +F 0 "X1" H 4350 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 4350 3487 50 0000 C CNN +F 2 "" H 4150 3850 50 0001 C CNN +F 3 "" H 4150 3850 50 0001 C CNN +F 4 "X" H 4150 3850 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4150 3850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4150 3850 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 4150 3850 50 0001 C CNN "Spice_Lib_File" + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B28B0D0 +P 5900 3850 +F 0 "X2" H 6100 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 6100 3487 50 0000 C CNN +F 2 "" H 5900 3850 50 0001 C CNN +F 3 "" H 5900 3850 50 0001 C CNN +F 4 "X" H 5900 3850 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5900 3850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5900 3850 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5900 3850 50 0001 C CNN "Spice_Lib_File" + 1 5900 3850 + 1 0 0 -1 +$EndComp +Text GLabel 2850 3750 0 50 Input ~ 0 +1 +Wire Wire Line + 2850 3750 3950 3750 +Text GLabel 2850 3950 0 50 Input ~ 0 +2 +Wire Wire Line + 2850 3950 3950 3950 +Text GLabel 7250 3150 0 50 Output ~ 0 +3 +$Comp +L Device:R R1 +U 1 1 5B28B182 +P 7650 3850 +F 0 "R1" V 7443 3850 50 0000 C CNN +F 1 "10meg" V 7534 3850 50 0000 C CNN +F 2 "" V 7580 3850 50 0001 C CNN +F 3 "~" H 7650 3850 50 0001 C CNN + 1 7650 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28B214 +P 8150 4050 +F 0 "#PWR04" H 8150 3800 50 0001 C CNN +F 1 "GND" H 8155 3877 50 0000 C CNN +F 2 "" H 8150 4050 50 0001 C CNN +F 3 "" H 8150 4050 50 0001 C CNN + 1 8150 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 4050 8150 3850 +Wire Wire Line + 8150 3850 7800 3850 +Wire Wire Line + 7500 3850 7350 3850 +Wire Wire Line + 7250 3150 7350 3150 +Wire Wire Line + 7350 3150 7350 3850 +Connection ~ 7350 3850 +Wire Wire Line + 7350 3850 6500 3850 +Wire Wire Line + 4750 3850 4750 3750 +Wire Wire Line + 4750 3750 5700 3750 +Wire Wire Line + 4750 3850 4750 3950 +Wire Wire Line + 4750 3950 5700 3950 +Connection ~ 4750 3850 +Text GLabel 3850 2900 0 50 Input ~ 0 +4 +Wire Wire Line + 3850 2900 4350 2900 +Wire Wire Line + 6100 2900 6100 3450 +Wire Wire Line + 4350 3450 4350 2900 +Connection ~ 4350 2900 +Wire Wire Line + 4350 2900 6100 2900 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28B632 +P 1800 3400 +F 0 "V1" H 2028 3446 50 0000 L CNN +F 1 "VSOURCE" H 2028 3355 50 0000 L CNN +F 2 "" H 1800 3400 50 0001 C CNN +F 3 "" H 1800 3400 50 0001 C CNN +F 4 "V" H 1800 3400 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1800 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1800 3400 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1800 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B28B678 +P 1800 3950 +F 0 "#PWR01" H 1800 3700 50 0001 C CNN +F 1 "GND" H 1805 3777 50 0000 C CNN +F 2 "" H 1800 3950 50 0001 C CNN +F 3 "" H 1800 3950 50 0001 C CNN + 1 1800 3950 + 1 0 0 -1 +$EndComp +Text GLabel 1700 2750 0 50 Input ~ 0 +1 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28B69D +P 2050 5600 +F 0 "V2" H 2278 5646 50 0000 L CNN +F 1 "VSOURCE" H 2278 5555 50 0000 L CNN +F 2 "" H 2050 5600 50 0001 C CNN +F 3 "" H 2050 5600 50 0001 C CNN +F 4 "V" H 2050 5600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2050 5600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2050 5600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2050 5600 + 1 0 0 -1 +$EndComp +Text GLabel 1900 4950 0 50 Input ~ 0 +2 +$Comp +L power:GND #PWR02 +U 1 1 5B28B717 +P 2050 6100 +F 0 "#PWR02" H 2050 5850 50 0001 C CNN +F 1 "GND" H 2055 5927 50 0000 C CNN +F 2 "" H 2050 6100 50 0001 C CNN +F 3 "" H 2050 6100 50 0001 C CNN + 1 2050 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 6100 2050 5900 +Wire Wire Line + 2050 5300 2050 4950 +Wire Wire Line + 2050 4950 1900 4950 +Wire Wire Line + 1800 3100 1800 2750 +Wire Wire Line + 1800 2750 1700 2750 +Wire Wire Line + 1800 3950 1800 3700 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28BEA7 +P 7600 5550 +F 0 "V3" H 7828 5596 50 0000 L CNN +F 1 "VSOURCE" H 7828 5505 50 0000 L CNN +F 2 "" H 7600 5550 50 0001 C CNN +F 3 "" H 7600 5550 50 0001 C CNN +F 4 "V" H 7600 5550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 7600 5550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7600 5550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7600 5550 + 1 0 0 -1 +$EndComp +Text GLabel 7050 4800 0 50 Input ~ 0 +4 +Wire Wire Line + 7050 4800 7600 4800 +Wire Wire Line + 7600 4800 7600 5250 +$Comp +L power:GND #PWR03 +U 1 1 5B28C1DA +P 7600 6000 +F 0 "#PWR03" H 7600 5750 50 0001 C CNN +F 1 "GND" H 7605 5827 50 0000 C CNN +F 2 "" H 7600 6000 50 0001 C CNN +F 3 "" H 7600 6000 50 0001 C CNN + 1 7600 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 6000 7600 5850 +Text Notes 8750 5600 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and gate/sym-lib-table b/digital ciruits/and gate/sym-lib-table new file mode 100644 index 0000000..81cad09 --- /dev/null +++ b/digital ciruits/and gate/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (lib (name spice_models)(type Legacy)(uri /home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib)(options "")(descr "")) + (lib (name sim_logic)(type Legacy)(uri /home/akshay/Downloads/kicad-simulation-examples-master/libs/sim_logic.lib)(options "")(descr "")) +) diff --git a/digital ciruits/and_sub/and_sub-cache.lib b/digital ciruits/and_sub/and_sub-cache.lib new file mode 100644 index 0000000..7e993b2 --- /dev/null +++ b/digital ciruits/and_sub/and_sub-cache.lib @@ -0,0 +1,70 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# basic_gates:and +# +DEF basic_gates:and X 0 40 Y Y 1 F N +F0 "X" 0 250 50 H V C CNN +F1 "basic_gates:and" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 250 0 206 760 -760 0 1 0 N 300 200 300 -200 +P 2 0 1 0 -350 -200 300 -200 N +P 2 0 1 0 -350 200 -350 -200 N +P 2 0 1 0 -350 200 300 200 N +X A 1 -450 100 100 R 50 50 1 1 I +X B 2 -450 -100 100 R 50 50 1 1 I +X Out 3 550 0 100 L 50 50 1 1 O +X VDD 4 150 300 100 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/and_sub/and_sub.bak b/digital ciruits/and_sub/and_sub.bak new file mode 100644 index 0000000..e3fb14a --- /dev/null +++ b/digital ciruits/and_sub/and_sub.bak @@ -0,0 +1,185 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L basic_gates:and X1 +U 1 1 5B28C859 +P 5550 3900 +F 0 "X1" H 5600 3628 50 0000 C CNN +F 1 "and" H 5600 3537 50 0000 C CNN +F 2 "" H 5550 3900 50 0001 C CNN +F 3 "" H 5550 3900 50 0001 C CNN +F 4 "X" H 5550 3900 50 0001 C CNN "Spice_Primitive" +F 5 "AND" H 5550 3900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 3900 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5550 3900 50 0001 C CNN "Spice_Lib_File" + 1 5550 3900 + 1 0 0 -1 +$EndComp +Text GLabel 4200 3800 0 50 Input ~ 0 +a +Wire Wire Line + 4200 3800 5100 3800 +Text GLabel 4200 4000 0 50 Input ~ 0 +b +Wire Wire Line + 4200 4000 5100 4000 +$Comp +L Device:R R1 +U 1 1 5B28C8FD +P 7400 3850 +F 0 "R1" V 7193 3850 50 0000 C CNN +F 1 "10meg" V 7284 3850 50 0000 C CNN +F 2 "" V 7330 3850 50 0001 C CNN +F 3 "~" H 7400 3850 50 0001 C CNN + 1 7400 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28C98E +P 7700 4150 +F 0 "#PWR04" H 7700 3900 50 0001 C CNN +F 1 "GND" H 7705 3977 50 0000 C CNN +F 2 "" H 7700 4150 50 0001 C CNN +F 3 "" H 7700 4150 50 0001 C CNN + 1 7700 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 4150 7700 3850 +Wire Wire Line + 7700 3850 7550 3850 +Wire Wire Line + 7250 3850 7000 3850 +Wire Wire Line + 6100 3850 6100 3900 +Text GLabel 6750 3350 0 50 Output ~ 0 +out +Wire Wire Line + 6750 3350 7000 3350 +Wire Wire Line + 7000 3350 7000 3850 +Connection ~ 7000 3850 +Wire Wire Line + 7000 3850 6100 3850 +Text GLabel 5400 3050 0 50 Input ~ 0 +vdd +Wire Wire Line + 5400 3050 5700 3050 +Wire Wire Line + 5700 3050 5700 3600 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28CB23 +P 2350 3650 +F 0 "V1" H 2578 3696 50 0000 L CNN +F 1 "VSOURCE" H 2578 3605 50 0000 L CNN +F 2 "" H 2350 3650 50 0001 C CNN +F 3 "" H 2350 3650 50 0001 C CNN +F 4 "V" H 2350 3650 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 2350 3650 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 3650 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 3650 + 1 0 0 -1 +$EndComp +Text GLabel 2150 3050 0 50 Input ~ 0 +a +$Comp +L power:GND #PWR01 +U 1 1 5B28CB63 +P 2350 4150 +F 0 "#PWR01" H 2350 3900 50 0001 C CNN +F 1 "GND" H 2355 3977 50 0000 C CNN +F 2 "" H 2350 4150 50 0001 C CNN +F 3 "" H 2350 4150 50 0001 C CNN + 1 2350 4150 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28CB77 +P 2350 5050 +F 0 "V2" H 2578 5096 50 0000 L CNN +F 1 "VSOURCE" H 2578 5005 50 0000 L CNN +F 2 "" H 2350 5050 50 0001 C CNN +F 3 "" H 2350 5050 50 0001 C CNN +F 4 "V" H 2350 5050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2350 5050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 5050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 5050 + 1 0 0 -1 +$EndComp +Text GLabel 2250 4600 0 50 Input ~ 0 +b +$Comp +L power:GND #PWR02 +U 1 1 5B28CBDF +P 2350 5550 +F 0 "#PWR02" H 2350 5300 50 0001 C CNN +F 1 "GND" H 2355 5377 50 0000 C CNN +F 2 "" H 2350 5550 50 0001 C CNN +F 3 "" H 2350 5550 50 0001 C CNN + 1 2350 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2150 3050 2350 3050 +Wire Wire Line + 2350 3050 2350 3350 +Wire Wire Line + 2350 4150 2350 3950 +Wire Wire Line + 2250 4600 2350 4600 +Wire Wire Line + 2350 4600 2350 4750 +Wire Wire Line + 2350 5350 2350 5550 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28D002 +P 5300 5300 +F 0 "V3" H 5528 5346 50 0000 L CNN +F 1 "VSOURCE" H 5528 5255 50 0000 L CNN +F 2 "" H 5300 5300 50 0001 C CNN +F 3 "" H 5300 5300 50 0001 C CNN +F 4 "V" H 5300 5300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 5300 5300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5300 5300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5300 5300 + 1 0 0 -1 +$EndComp +Text GLabel 5100 4700 0 50 Input ~ 0 +vdd +$Comp +L power:GND #PWR03 +U 1 1 5B28D086 +P 5300 5800 +F 0 "#PWR03" H 5300 5550 50 0001 C CNN +F 1 "GND" H 5305 5627 50 0000 C CNN +F 2 "" H 5300 5800 50 0001 C CNN +F 3 "" H 5300 5800 50 0001 C CNN + 1 5300 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4700 5300 4700 +Wire Wire Line + 5300 4700 5300 5000 +Wire Wire Line + 5300 5600 5300 5800 +Text Notes 7500 5550 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and_sub/and_sub.cir b/digital ciruits/and_sub/and_sub.cir new file mode 100644 index 0000000..2e3875e --- /dev/null +++ b/digital ciruits/and_sub/and_sub.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" +X1 a b out vdd AND +R1 GND out 10meg +V1 a GND dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 b GND dc 0 pulse(0 3.3 50m 0 0 50m 100m) +V3 vdd GND dc 3.3 +.tran 1m 400m +.end diff --git a/digital ciruits/and_sub/and_sub.kicad_pcb b/digital ciruits/and_sub/and_sub.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/and_sub/and_sub.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/and_sub/and_sub.pro b/digital ciruits/and_sub/and_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/and_sub/and_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/and_sub/and_sub.sch b/digital ciruits/and_sub/and_sub.sch new file mode 100644 index 0000000..bebf8ba --- /dev/null +++ b/digital ciruits/and_sub/and_sub.sch @@ -0,0 +1,186 @@ +EESchema Schematic File Version 4 +LIBS:and_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L basic_gates:and X1 +U 1 1 5B28C859 +P 5550 3900 +F 0 "X1" H 5600 3628 50 0000 C CNN +F 1 "and" H 5600 3537 50 0000 C CNN +F 2 "" H 5550 3900 50 0001 C CNN +F 3 "" H 5550 3900 50 0001 C CNN +F 4 "X" H 5550 3900 50 0001 C CNN "Spice_Primitive" +F 5 "AND" H 5550 3900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 3900 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5550 3900 50 0001 C CNN "Spice_Lib_File" + 1 5550 3900 + 1 0 0 -1 +$EndComp +Text GLabel 4200 3800 0 50 Input ~ 0 +a +Wire Wire Line + 4200 3800 5100 3800 +Text GLabel 4200 4000 0 50 Input ~ 0 +b +Wire Wire Line + 4200 4000 5100 4000 +$Comp +L Device:R R1 +U 1 1 5B28C8FD +P 7400 3850 +F 0 "R1" V 7193 3850 50 0000 C CNN +F 1 "10meg" V 7284 3850 50 0000 C CNN +F 2 "" V 7330 3850 50 0001 C CNN +F 3 "~" H 7400 3850 50 0001 C CNN + 1 7400 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28C98E +P 7700 4150 +F 0 "#PWR04" H 7700 3900 50 0001 C CNN +F 1 "GND" H 7705 3977 50 0000 C CNN +F 2 "" H 7700 4150 50 0001 C CNN +F 3 "" H 7700 4150 50 0001 C CNN + 1 7700 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 4150 7700 3850 +Wire Wire Line + 7700 3850 7550 3850 +Wire Wire Line + 7250 3850 7000 3850 +Wire Wire Line + 6100 3850 6100 3900 +Text GLabel 6750 3350 0 50 Output ~ 0 +out +Wire Wire Line + 6750 3350 7000 3350 +Wire Wire Line + 7000 3350 7000 3850 +Connection ~ 7000 3850 +Wire Wire Line + 7000 3850 6100 3850 +Text GLabel 5400 3050 0 50 Input ~ 0 +vdd +Wire Wire Line + 5400 3050 5700 3050 +Wire Wire Line + 5700 3050 5700 3600 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28CB23 +P 2350 3650 +F 0 "V1" H 2578 3696 50 0000 L CNN +F 1 "VSOURCE" H 2578 3605 50 0000 L CNN +F 2 "" H 2350 3650 50 0001 C CNN +F 3 "" H 2350 3650 50 0001 C CNN +F 4 "V" H 2350 3650 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 2350 3650 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 3650 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 3650 + 1 0 0 -1 +$EndComp +Text GLabel 2150 3050 0 50 Input ~ 0 +a +$Comp +L power:GND #PWR01 +U 1 1 5B28CB63 +P 2350 4150 +F 0 "#PWR01" H 2350 3900 50 0001 C CNN +F 1 "GND" H 2355 3977 50 0000 C CNN +F 2 "" H 2350 4150 50 0001 C CNN +F 3 "" H 2350 4150 50 0001 C CNN + 1 2350 4150 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28CB77 +P 2350 5050 +F 0 "V2" H 2578 5096 50 0000 L CNN +F 1 "VSOURCE" H 2578 5005 50 0000 L CNN +F 2 "" H 2350 5050 50 0001 C CNN +F 3 "" H 2350 5050 50 0001 C CNN +F 4 "V" H 2350 5050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2350 5050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 5050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 5050 + 1 0 0 -1 +$EndComp +Text GLabel 2250 4600 0 50 Input ~ 0 +b +$Comp +L power:GND #PWR02 +U 1 1 5B28CBDF +P 2350 5550 +F 0 "#PWR02" H 2350 5300 50 0001 C CNN +F 1 "GND" H 2355 5377 50 0000 C CNN +F 2 "" H 2350 5550 50 0001 C CNN +F 3 "" H 2350 5550 50 0001 C CNN + 1 2350 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2150 3050 2350 3050 +Wire Wire Line + 2350 3050 2350 3350 +Wire Wire Line + 2350 4150 2350 3950 +Wire Wire Line + 2250 4600 2350 4600 +Wire Wire Line + 2350 4600 2350 4750 +Wire Wire Line + 2350 5350 2350 5550 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28D002 +P 5300 5300 +F 0 "V3" H 5528 5346 50 0000 L CNN +F 1 "VSOURCE" H 5528 5255 50 0000 L CNN +F 2 "" H 5300 5300 50 0001 C CNN +F 3 "" H 5300 5300 50 0001 C CNN +F 4 "V" H 5300 5300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 5300 5300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5300 5300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5300 5300 + 1 0 0 -1 +$EndComp +Text GLabel 5100 4700 0 50 Input ~ 0 +vdd +$Comp +L power:GND #PWR03 +U 1 1 5B28D086 +P 5300 5800 +F 0 "#PWR03" H 5300 5550 50 0001 C CNN +F 1 "GND" H 5305 5627 50 0000 C CNN +F 2 "" H 5300 5800 50 0001 C CNN +F 3 "" H 5300 5800 50 0001 C CNN + 1 5300 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4700 5300 4700 +Wire Wire Line + 5300 4700 5300 5000 +Wire Wire Line + 5300 5600 5300 5800 +Text Notes 7500 5550 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and_sub/b3v33check.log b/digital ciruits/and_sub/b3v33check.log new file mode 100644 index 0000000..6e015ea --- /dev/null +++ b/digital ciruits/and_sub/b3v33check.log @@ -0,0 +1,4 @@ +BSIM3v3.3.0 Parameter Checking. +Model = mpmos +Warning: Pd = 0 is less than W. +Warning: Ps = 0 is less than W. diff --git a/digital ciruits/and_sub/basic_gates.bck b/digital ciruits/and_sub/basic_gates.bck new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/and_sub/basic_gates.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/and_sub/basic_gates.dcm b/digital ciruits/and_sub/basic_gates.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/and_sub/basic_gates.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/and_sub/basic_gates.lib b/digital ciruits/and_sub/basic_gates.lib new file mode 100644 index 0000000..a4829ad --- /dev/null +++ b/digital ciruits/and_sub/basic_gates.lib @@ -0,0 +1,56 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# UA741 +# +DEF UA741 X 0 40 Y Y 1 F N +F0 "X" 0 -250 50 H V C CNN +F1 "UA741" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -200 200 -200 -200 300 0 -200 200 N +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X ~ 3 400 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# and +# +DEF and X 0 40 Y Y 1 F N +F0 "X" 0 250 50 H V C CNN +F1 "and" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 250 0 206 760 -760 0 1 0 N 300 200 300 -200 +P 2 0 1 0 -350 -200 300 -200 N +P 2 0 1 0 -350 200 -350 -200 N +P 2 0 1 0 -350 200 300 200 N +X A 1 -450 100 100 R 50 50 1 1 I +X B 2 -450 -100 100 R 50 50 1 1 I +X Out 3 550 0 100 L 50 50 1 1 O +X VDD 4 150 300 100 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# jkff +# +DEF jkff X 0 40 Y Y 1 F N +F0 "X" 0 -350 50 H V C CNN +F1 "jkff" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -350 250 350 -300 0 1 0 N +X J 1 -450 200 100 R 50 50 1 1 I +X clk 2 -450 0 100 R 50 50 1 1 I +X k 3 -450 -200 100 R 50 50 1 1 I +X vdd 4 0 350 100 D 50 50 1 1 O +X q 5 450 150 100 L 50 50 1 1 O +X nq 6 450 -200 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/and_sub/sym-lib-table b/digital ciruits/and_sub/sym-lib-table new file mode 100644 index 0000000..e843b54 --- /dev/null +++ b/digital ciruits/and_sub/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name basic_gates)(type Legacy)(uri /home/akshay/kicad_examples/and_sub/basic_gates.lib)(options "")(descr "")) +) diff --git a/digital ciruits/cmos_nand/cmos_nand-cache.lib b/digital ciruits/cmos_nand/cmos_nand-cache.lib new file mode 100644 index 0000000..6dd4c50 --- /dev/null +++ b/digital ciruits/cmos_nand/cmos_nand-cache.lib @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:MNMOS +# +DEF pspice:MNMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "pspice:MNMOS" 300 -50 50 H V L CNN +F2 "" -25 0 50 H I C CNN +F3 "" -25 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 -100 -50 100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 -25 0 50 25 50 -25 -25 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 -200 100 U 50 50 1 1 P +X B 4 200 -200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pspice:MPMOS +# +DEF pspice:MPMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "pspice:MPMOS" 300 -50 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 100 -50 -100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 200 0 125 25 125 -25 200 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 -200 100 U 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 200 100 D 50 50 1 1 P +X B 4 200 200 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand/cmos_nand.bak b/digital ciruits/cmos_nand/cmos_nand.bak new file mode 100644 index 0000000..23bc2a2 --- /dev/null +++ b/digital ciruits/cmos_nand/cmos_nand.bak @@ -0,0 +1,283 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 3800 1400 3750 +Text GLabel 4550 2700 0 50 Input ~ 0 +A +Text GLabel 7250 3100 2 50 Output ~ 0 +Out +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5000 2250 +F 0 "#PWR02" H 5000 2100 50 0001 C CNN +F 1 "VDD" H 5017 2423 50 0000 C CNN +F 2 "" H 5000 2250 50 0001 C CNN +F 3 "" H 5000 2250 50 0001 C CNN + 1 5000 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3700 5000 3850 +Wire Wire Line + 4700 3500 4550 3500 +Wire Wire Line + 5000 2500 5000 2450 +Wire Notes Line + 4650 2400 4650 5150 +Wire Notes Line + 7100 5150 7100 2400 +Wire Notes Line + 7100 2400 4650 2400 +Wire Notes Line + 4650 5150 7100 5150 +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Wire Wire Line + 4700 2700 4550 2700 +Wire Wire Line + 1400 2250 1400 2350 +Text Notes 4950 6000 0 50 ~ 0 +.tran 1m 400m +Text Notes 4950 5750 0 50 ~ 0 +.model mnmos nmos level=8 version=3.3.0\n.model mpmos pmos level=8 version=3.3.0\n +$Comp +L pspice:MPMOS M1 +U 1 1 5B2448E1 +P 4900 2700 +F 0 "M1" H 5187 2746 50 0000 L CNN +F 1 "MPMOS" H 5187 2655 50 0000 L CNN +F 2 "" H 4900 2700 50 0001 C CNN +F 3 "" H 4900 2700 50 0001 C CNN + 1 4900 2700 + 1 0 0 -1 +$EndComp +$Comp +L pspice:MNMOS M2 +U 1 1 5B244930 +P 4900 3500 +F 0 "M2" H 5188 3546 50 0000 L CNN +F 1 "MNMOS" H 5188 3455 50 0000 L CNN +F 2 "" H 4875 3500 50 0001 C CNN +F 3 "" H 4875 3500 50 0001 C CNN + 1 4900 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 2500 5100 2450 +Wire Wire Line + 5100 2450 5000 2450 +Connection ~ 5000 2450 +Wire Wire Line + 5000 2450 5000 2250 +Wire Wire Line + 5100 3700 5100 3850 +Wire Wire Line + 5100 3850 5000 3850 +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 2-input NAND gate using PMOS/NMOS\n2. Run the simulation and plot V(A), V(B) and V(out) +$Comp +L pspice:MPMOS M4 +U 1 1 5B249F5D +P 6350 2700 +F 0 "M4" H 6637 2746 50 0000 L CNN +F 1 "MPMOS" H 6637 2655 50 0000 L CNN +F 2 "" H 6350 2700 50 0001 C CNN +F 3 "" H 6350 2700 50 0001 C CNN + 1 6350 2700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR03 +U 1 1 5B249FBF +P 6450 2250 +F 0 "#PWR03" H 6450 2100 50 0001 C CNN +F 1 "VDD" H 6467 2423 50 0000 C CNN +F 2 "" H 6450 2250 50 0001 C CNN +F 3 "" H 6450 2250 50 0001 C CNN + 1 6450 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 2500 6450 2450 +Wire Wire Line + 6450 2450 6550 2450 +Wire Wire Line + 6550 2450 6550 2500 +Connection ~ 6450 2450 +Wire Wire Line + 6450 2450 6450 2250 +Text GLabel 5950 2700 0 50 Input ~ 0 +B +Wire Wire Line + 5950 2700 6150 2700 +Wire Wire Line + 5000 2900 5000 3100 +Wire Wire Line + 5000 4650 5000 4800 +Wire Wire Line + 4700 4450 4550 4450 +$Comp +L pspice:MNMOS M3 +U 1 1 5B24A6A3 +P 4900 4450 +F 0 "M3" H 5188 4496 50 0000 L CNN +F 1 "MNMOS" H 5188 4405 50 0000 L CNN +F 2 "" H 4875 4450 50 0001 C CNN +F 3 "" H 4875 4450 50 0001 C CNN + 1 4900 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4650 5100 4800 +Wire Wire Line + 5100 4800 5000 4800 +Wire Wire Line + 5000 3850 5000 4250 +Text GLabel 1500 2250 2 50 Output ~ 0 +A +Text GLabel 1500 4200 2 50 Output ~ 0 +B +Wire Wire Line + 5000 3100 6450 3100 +Wire Wire Line + 6450 3100 6450 2900 +Connection ~ 5000 3100 +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 7250 3100 6450 3100 +Connection ~ 6450 3100 +Connection ~ 5000 3850 +Text GLabel 4550 3500 0 50 Input ~ 0 +A +Text GLabel 4550 4450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B24C547 +P 5000 5300 +F 0 "#GND03" H 5000 5200 50 0001 C CNN +F 1 "0" H 5000 5387 50 0000 C CNN +F 2 "" H 5000 5300 50 0001 C CNN +F 3 "" H 5000 5300 50 0001 C CNN + 1 5000 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 4800 5000 5300 +Connection ~ 5000 4800 +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 5750 1400 5700 +Wire Wire Line + 1400 4200 1400 4300 +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 4950 6550 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(out)\n.endc +Text GLabel 5000 4100 0 50 BiDi ~ 0 +1 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand/cmos_nand.cir b/digital ciruits/cmos_nand/cmos_nand.cir new file mode 100644 index 0000000..b426375 --- /dev/null +++ b/digital ciruits/cmos_nand/cmos_nand.cir @@ -0,0 +1,16 @@ +.title KiCad schematic +V1 A 0 dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 VDD 0 3.3 +M1 Out A VDD VDD MPMOS +M2 Out A 1 1 MNMOS +M4 Out B VDD VDD MPMOS +M3 1 B 0 0 MNMOS +V3 B 0 dc 0 pulse(0 3.3 0 0 0 50m 100m) +.tran 1m 400m +.model mnmos nmos level=8 version=3.3.0 +.model mpmos pmos level=8 version=3.3.0 +.control +run +plot v(a)+5 v(b)+10 v(out) +.endc +.end diff --git a/digital ciruits/cmos_nand/cmos_nand.pro b/digital ciruits/cmos_nand/cmos_nand.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/cmos_nand/cmos_nand.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/cmos_nand/cmos_nand.sch b/digital ciruits/cmos_nand/cmos_nand.sch new file mode 100644 index 0000000..d8cdc4c --- /dev/null +++ b/digital ciruits/cmos_nand/cmos_nand.sch @@ -0,0 +1,287 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Text GLabel 4550 2700 0 50 Input ~ 0 +A +Text GLabel 7250 3100 2 50 Output ~ 0 +Out +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5000 2250 +F 0 "#PWR02" H 5000 2100 50 0001 C CNN +F 1 "VDD" H 5017 2423 50 0000 C CNN +F 2 "" H 5000 2250 50 0001 C CNN +F 3 "" H 5000 2250 50 0001 C CNN + 1 5000 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3700 5000 3850 +Wire Wire Line + 4700 3500 4550 3500 +Wire Wire Line + 5000 2500 5000 2450 +Wire Notes Line + 4650 2400 4650 5150 +Wire Notes Line + 7100 5150 7100 2400 +Wire Notes Line + 7100 2400 4650 2400 +Wire Notes Line + 4650 5150 7100 5150 +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Wire Wire Line + 4700 2700 4550 2700 +Text Notes 4950 6000 0 50 ~ 0 +.tran 1m 400m +Text Notes 4950 5750 0 50 ~ 0 +.model mnmos nmos level=8 version=3.3.0\n.model mpmos pmos level=8 version=3.3.0\n +$Comp +L pspice:MPMOS M1 +U 1 1 5B2448E1 +P 4900 2700 +F 0 "M1" H 5187 2746 50 0000 L CNN +F 1 "MPMOS" H 5187 2655 50 0000 L CNN +F 2 "" H 4900 2700 50 0001 C CNN +F 3 "" H 4900 2700 50 0001 C CNN + 1 4900 2700 + 1 0 0 -1 +$EndComp +$Comp +L pspice:MNMOS M2 +U 1 1 5B244930 +P 4900 3500 +F 0 "M2" H 5188 3546 50 0000 L CNN +F 1 "MNMOS" H 5188 3455 50 0000 L CNN +F 2 "" H 4875 3500 50 0001 C CNN +F 3 "" H 4875 3500 50 0001 C CNN + 1 4900 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 2500 5100 2450 +Wire Wire Line + 5100 2450 5000 2450 +Connection ~ 5000 2450 +Wire Wire Line + 5000 2450 5000 2250 +Wire Wire Line + 5100 3700 5100 3850 +Wire Wire Line + 5100 3850 5000 3850 +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 2-input NAND gate using PMOS/NMOS\n2. Run the simulation and plot V(A), V(B) and V(out) +$Comp +L pspice:MPMOS M4 +U 1 1 5B249F5D +P 6350 2700 +F 0 "M4" H 6637 2746 50 0000 L CNN +F 1 "MPMOS" H 6637 2655 50 0000 L CNN +F 2 "" H 6350 2700 50 0001 C CNN +F 3 "" H 6350 2700 50 0001 C CNN + 1 6350 2700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR03 +U 1 1 5B249FBF +P 6450 2250 +F 0 "#PWR03" H 6450 2100 50 0001 C CNN +F 1 "VDD" H 6467 2423 50 0000 C CNN +F 2 "" H 6450 2250 50 0001 C CNN +F 3 "" H 6450 2250 50 0001 C CNN + 1 6450 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 2500 6450 2450 +Wire Wire Line + 6450 2450 6550 2450 +Wire Wire Line + 6550 2450 6550 2500 +Connection ~ 6450 2450 +Wire Wire Line + 6450 2450 6450 2250 +Text GLabel 5950 2700 0 50 Input ~ 0 +B +Wire Wire Line + 5950 2700 6150 2700 +Wire Wire Line + 5000 2900 5000 3100 +Wire Wire Line + 5000 4650 5000 4800 +Wire Wire Line + 4700 4450 4550 4450 +$Comp +L pspice:MNMOS M3 +U 1 1 5B24A6A3 +P 4900 4450 +F 0 "M3" H 5188 4496 50 0000 L CNN +F 1 "MNMOS" H 5188 4405 50 0000 L CNN +F 2 "" H 4875 4450 50 0001 C CNN +F 3 "" H 4875 4450 50 0001 C CNN + 1 4900 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4650 5100 4800 +Wire Wire Line + 5100 4800 5000 4800 +Wire Wire Line + 5000 3850 5000 4250 +Text GLabel 1500 2250 2 50 Output ~ 0 +A +Text GLabel 1500 4200 2 50 Output ~ 0 +B +Wire Wire Line + 5000 3100 6450 3100 +Wire Wire Line + 6450 3100 6450 2900 +Connection ~ 5000 3100 +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 7250 3100 6450 3100 +Connection ~ 6450 3100 +Connection ~ 5000 3850 +Text GLabel 4550 3500 0 50 Input ~ 0 +A +Text GLabel 4550 4450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B24C547 +P 5000 5300 +F 0 "#GND03" H 5000 5200 50 0001 C CNN +F 1 "0" H 5000 5387 50 0000 C CNN +F 2 "" H 5000 5300 50 0001 C CNN +F 3 "" H 5000 5300 50 0001 C CNN + 1 5000 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 4800 5000 5300 +Connection ~ 5000 4800 +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 4950 6550 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(out)\n.endc +Text GLabel 5000 4100 0 50 BiDi ~ 0 +1 +Wire Wire Line + 1400 2250 1400 2750 +Wire Wire Line + 1400 3350 1400 3800 +Wire Wire Line + 1400 4200 1400 4700 +Wire Wire Line + 1400 5300 1400 5750 +Wire Wire Line + 10200 3500 10200 3100 +Wire Wire Line + 10200 4100 10200 4500 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/AKS.bck b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.bck new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/AKS.dcm b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/AKS.lib b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.lib new file mode 100644 index 0000000..58a69aa --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# dflipflop +# +DEF dflipflop X 0 40 Y Y 1 F N +F0 "X" 0 -250 50 H V C CNN +F1 "dflipflop" 0 -50 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -250 150 250 -200 0 1 0 N +X CLK B -350 100 100 R 50 50 1 1 I +X D B -350 -150 100 R 50 50 1 1 I +X nq Out 350 -150 100 L 50 50 1 1 O +X q Out 350 100 100 L 50 50 1 1 O +X VDD VDD 0 250 100 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.kicad_pcb b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.pro b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.sch b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.sch new file mode 100644 index 0000000..fff8c68 --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.sch @@ -0,0 +1,4 @@ +EESchema Schematic File Version 2 +EELAYER 25 0 +EELAYER END +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/pspice.dcm b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.dcm new file mode 100644 index 0000000..0c3c718 --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.dcm @@ -0,0 +1,18 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP MNMOS +D N-channel MOSFET +K mosfet nmos +$ENDCMP +# +$CMP MPMOS +D P-channel MOSFET +K mosfet pmos +$ENDCMP +# +$CMP R +D Resistance +K R DEV +$ENDCMP +# +#End Doc Library diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/pspice.lib b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.lib new file mode 100644 index 0000000..e95d245 --- /dev/null +++ b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.lib @@ -0,0 +1,213 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# 0 +# +DEF 0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# CAP +# +DEF CAP C 0 10 Y Y 1 F N +F0 "C" 100 150 50 V V C CNN +F1 "CAP" 100 -150 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS C +DRAW +P 2 0 1 0 -150 -50 150 -50 N +P 2 0 1 0 -150 50 150 50 N +X ~ 1 0 250 200 D 40 40 1 1 P +X ~ 2 0 -250 200 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 Y N 1 F N +F0 "D" 0 150 50 H V C CNN +F1 "DIODE" 0 -175 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 75 100 75 -100 N +P 3 0 1 0 -75 100 -75 -100 75 0 F +X K 1 -200 0 150 R 50 50 1 1 I +X A 2 200 0 150 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# INDUCTOR +# +DEF INDUCTOR L 0 0 N Y 1 F N +F0 "L" 0 100 50 H V C CNN +F1 "INDUCTOR" 0 -50 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A -150 0 50 1 1799 0 1 0 N -100 0 -200 0 +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 1 1799 0 1 0 N 100 0 0 0 +A 150 0 50 1 1799 0 1 0 N 200 0 100 0 +X 1 1 -250 0 50 R 30 30 1 1 I +X 2 2 250 0 50 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# ISOURCE +# +DEF ISOURCE I 0 40 Y Y 1 F N +F0 "I" -300 350 50 H V C CNN +F1 "ISOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 -100 200 0 1 0 N +C 0 100 202 0 1 0 N +T 0 -270 -10 50 0 0 1 I Normal 0 C C +P 2 0 1 0 -300 -200 -300 200 F +P 3 0 1 0 -350 200 -300 300 -250 200 F +X E1 1 0 400 100 D 50 50 1 1 I +X E2 2 0 -400 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# MNMOS +# +DEF MNMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "MNMOS" 300 -50 50 H V L CNN +F2 "" -25 0 50 H I C CNN +F3 "" -25 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 -100 -50 100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 -25 0 50 25 50 -25 -25 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 -200 100 U 50 50 1 1 P +X B 4 200 -200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# MPMOS +# +DEF MPMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "MPMOS" 300 -50 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 100 -50 -100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 200 0 125 25 125 -25 200 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 -200 100 U 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 200 100 D 50 50 1 1 P +X B 4 200 200 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# QNPN +# +DEF QNPN Q 0 0 Y Y 1 F N +F0 "Q" -100 300 50 H V C CNN +F1 "QNPN" -100 200 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 0 0 0 0 150 -150 N +P 4 0 0 0 150 -150 150 -50 50 -150 150 -150 F +P 2 0 1 0 0 -150 0 150 N +P 2 0 1 0 0 0 150 150 N +P 4 0 1 0 -100 -150 0 -150 0 -150 0 -150 N +X C 1 150 350 200 D 40 40 1 1 P +X B 2 -300 0 300 R 40 40 1 1 I +X E 3 150 -350 200 U 40 40 1 1 P +X Substrat 4 -100 -350 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# QPNP +# +DEF QPNP Q 0 0 Y Y 1 F N +F0 "Q" -100 300 50 H V C CNN +F1 "QPNP" -100 200 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 0 -150 0 150 N +P 2 0 1 0 0 0 150 -150 N +P 2 0 1 0 0 0 150 150 N +P 3 0 1 0 -100 -150 0 -150 0 -150 N +P 4 0 1 0 120 -180 180 -120 85 -85 120 -180 F +X C 1 150 350 200 D 40 40 1 1 C +X B 2 -300 0 300 R 40 40 1 1 I +X E 3 150 -350 200 U 40 40 1 1 E +X Substrat 4 -100 -350 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -40 150 40 -150 0 1 0 N +X ~ 1 0 250 100 D 50 50 1 1 P +X ~ 2 0 -250 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# dflip +# +DEF dflip X 0 40 Y Y 1 F N +F0 "X" 0 -150 50 H V C CNN +F1 "dflip" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -150 100 150 -100 0 1 0 N +X CLK B -250 50 100 R 50 50 1 1 I +X D B -250 -50 100 R 50 50 1 1 I +X nq Out 250 -50 100 L 50 50 1 1 O +X q Out 250 50 100 L 50 50 1 1 O +X VDD VDD 0 200 100 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand/sym-lib-table b/digital ciruits/cmos_nand/sym-lib-table new file mode 100644 index 0000000..a9aa174 --- /dev/null +++ b/digital ciruits/cmos_nand/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (lib (name basic_gates)(type Legacy)(uri /home/akshay/kicad_examples/and_sub/basic_gates.lib)(options "")(descr "")) + (lib (name sim_logic)(type Legacy)(uri "/home/akshay/Desktop/digital ciruits/libs/sim_logic.lib")(options "")(descr "")) +) diff --git a/digital ciruits/cmos_nand3/cmos_nand3-cache.lib b/digital ciruits/cmos_nand3/cmos_nand3-cache.lib new file mode 100644 index 0000000..6dd4c50 --- /dev/null +++ b/digital ciruits/cmos_nand3/cmos_nand3-cache.lib @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:MNMOS +# +DEF pspice:MNMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "pspice:MNMOS" 300 -50 50 H V L CNN +F2 "" -25 0 50 H I C CNN +F3 "" -25 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 -100 -50 100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 -25 0 50 25 50 -25 -25 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 -200 100 U 50 50 1 1 P +X B 4 200 -200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pspice:MPMOS +# +DEF pspice:MPMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "pspice:MPMOS" 300 -50 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 100 -50 -100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 200 0 125 25 125 -25 200 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 -200 100 U 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 200 100 D 50 50 1 1 P +X B 4 200 200 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand3/cmos_nand3.bak b/digital ciruits/cmos_nand3/cmos_nand3.bak new file mode 100644 index 0000000..3c74c4f --- /dev/null +++ b/digital ciruits/cmos_nand3/cmos_nand3.bak @@ -0,0 +1,382 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand3-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 5800 +F 0 "#GND01" H 1400 5700 50 0001 C CNN +F 1 "0" H 1400 5887 50 0000 C CNN +F 2 "" H 1400 5800 50 0001 C CNN +F 3 "" H 1400 5800 50 0001 C CNN + 1 1400 5800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 5050 +F 0 "V1" H 1828 5096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 5005 50 0000 L CNN +F 2 "" H 1400 5050 50 0001 C CNN +F 3 "" H 1400 5050 50 0001 C CNN +F 4 "V" H 1400 5050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 5050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 5800 1400 5750 +Text GLabel 4550 2700 0 50 Input ~ 0 +A +Text GLabel 8700 3100 2 50 Output ~ 0 +Out +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5000 2250 +F 0 "#PWR02" H 5000 2100 50 0001 C CNN +F 1 "VDD" H 5017 2423 50 0000 C CNN +F 2 "" H 5000 2250 50 0001 C CNN +F 3 "" H 5000 2250 50 0001 C CNN + 1 5000 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3700 5000 3850 +Wire Wire Line + 4700 3500 4550 3500 +Wire Wire Line + 5000 2500 5000 2450 +Wire Notes Line + 4650 2400 4650 6150 +Wire Notes Line + 8400 6150 8400 2400 +Wire Notes Line + 8400 2400 4650 2400 +Wire Notes Line + 4650 6150 8400 6150 +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Wire Wire Line + 4700 2700 4550 2700 +Wire Wire Line + 1400 4250 1400 4350 +Text Notes 9150 1400 0 50 ~ 0 +.tran 1m 400m +Text Notes 9150 1150 0 50 ~ 0 +.model mnmos nmos level=8 version=3.3.0\n.model mpmos pmos level=8 version=3.3.0\n +$Comp +L pspice:MPMOS M1 +U 1 1 5B2448E1 +P 4900 2700 +F 0 "M1" H 5187 2746 50 0000 L CNN +F 1 "MPMOS" H 5187 2655 50 0000 L CNN +F 2 "" H 4900 2700 50 0001 C CNN +F 3 "" H 4900 2700 50 0001 C CNN + 1 4900 2700 + 1 0 0 -1 +$EndComp +$Comp +L pspice:MNMOS M2 +U 1 1 5B244930 +P 4900 3500 +F 0 "M2" H 5188 3546 50 0000 L CNN +F 1 "MNMOS" H 5188 3455 50 0000 L CNN +F 2 "" H 4875 3500 50 0001 C CNN +F 3 "" H 4875 3500 50 0001 C CNN + 1 4900 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 2500 5100 2450 +Wire Wire Line + 5100 2450 5000 2450 +Connection ~ 5000 2450 +Wire Wire Line + 5000 2450 5000 2250 +Wire Wire Line + 5100 3700 5100 3850 +Wire Wire Line + 5100 3850 5000 3850 +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 3-input NAND gate PMOS/NMOS\n2. Run the simulation and plot V(A), V(B), V(C), V(out) +$Comp +L pspice:MPMOS M4 +U 1 1 5B249F5D +P 6350 2700 +F 0 "M4" H 6637 2746 50 0000 L CNN +F 1 "MPMOS" H 6637 2655 50 0000 L CNN +F 2 "" H 6350 2700 50 0001 C CNN +F 3 "" H 6350 2700 50 0001 C CNN + 1 6350 2700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR03 +U 1 1 5B249FBF +P 6450 2250 +F 0 "#PWR03" H 6450 2100 50 0001 C CNN +F 1 "VDD" H 6467 2423 50 0000 C CNN +F 2 "" H 6450 2250 50 0001 C CNN +F 3 "" H 6450 2250 50 0001 C CNN + 1 6450 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 2500 6450 2450 +Wire Wire Line + 6450 2450 6550 2450 +Wire Wire Line + 6550 2450 6550 2500 +Connection ~ 6450 2450 +Wire Wire Line + 6450 2450 6450 2250 +Text GLabel 5950 2700 0 50 Input ~ 0 +B +Wire Wire Line + 5950 2700 6150 2700 +Wire Wire Line + 5000 2900 5000 3100 +Wire Wire Line + 5000 4650 5000 4800 +Wire Wire Line + 4700 4450 4550 4450 +$Comp +L pspice:MNMOS M3 +U 1 1 5B24A6A3 +P 4900 4450 +F 0 "M3" H 5188 4496 50 0000 L CNN +F 1 "MNMOS" H 5188 4405 50 0000 L CNN +F 2 "" H 4875 4450 50 0001 C CNN +F 3 "" H 4875 4450 50 0001 C CNN + 1 4900 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4650 5100 4800 +Wire Wire Line + 5100 4800 5000 4800 +Wire Wire Line + 5000 3850 5000 4250 +Text GLabel 1500 4250 2 50 Output ~ 0 +B +Text GLabel 1500 2500 2 50 Output ~ 0 +A +Wire Wire Line + 5000 3100 6450 3100 +Wire Wire Line + 6450 3100 6450 2900 +Connection ~ 5000 3100 +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 8700 3100 7750 3100 +Connection ~ 6450 3100 +Connection ~ 5000 3850 +Text GLabel 4550 3500 0 50 Input ~ 0 +A +Text GLabel 4550 4450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B24C547 +P 5000 6350 +F 0 "#GND03" H 5000 6250 50 0001 C CNN +F 1 "0" H 5000 6437 50 0000 C CNN +F 2 "" H 5000 6350 50 0001 C CNN +F 3 "" H 5000 6350 50 0001 C CNN + 1 5000 6350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 4800 5000 5300 +Connection ~ 5000 4800 +Wire Wire Line + 1400 4250 1500 4250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 4050 +F 0 "#GND02" H 1400 3950 50 0001 C CNN +F 1 "0" H 1400 4137 50 0000 C CNN +F 2 "" H 1400 4050 50 0001 C CNN +F 3 "" H 1400 4050 50 0001 C CNN + 1 1400 4050 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 3300 +F 0 "V3" H 1828 3346 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 3255 50 0000 L CNN +F 2 "" H 1400 3300 50 0001 C CNN +F 3 "" H 1400 3300 50 0001 C CNN +F 4 "V" H 1400 3300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 3300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 4050 1400 4000 +Wire Wire Line + 1400 2500 1400 2600 +Wire Wire Line + 1400 2500 1500 2500 +Text Notes 1050 2100 0 50 ~ 0 +Test input signals +Text Notes 9150 1950 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(c)+15 v(out)\n.endc +Text GLabel 5000 4100 0 50 UnSpc ~ 0 +1 +$Comp +L pspice:MPMOS M6 +U 1 1 5B25ABD4 +P 7650 2700 +F 0 "M6" H 7937 2746 50 0000 L CNN +F 1 "MPMOS" H 7937 2655 50 0000 L CNN +F 2 "" H 7650 2700 50 0001 C CNN +F 3 "" H 7650 2700 50 0001 C CNN + 1 7650 2700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B25ABDB +P 7750 2250 +F 0 "#PWR04" H 7750 2100 50 0001 C CNN +F 1 "VDD" H 7767 2423 50 0000 C CNN +F 2 "" H 7750 2250 50 0001 C CNN +F 3 "" H 7750 2250 50 0001 C CNN + 1 7750 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 2500 7750 2450 +Wire Wire Line + 7750 2450 7850 2450 +Wire Wire Line + 7850 2450 7850 2500 +Connection ~ 7750 2450 +Wire Wire Line + 7750 2450 7750 2250 +Text GLabel 7250 2700 0 50 Input ~ 0 +C +Wire Wire Line + 7250 2700 7450 2700 +Wire Wire Line + 7750 3100 7750 2900 +Connection ~ 7750 3100 +Wire Wire Line + 7750 3100 6450 3100 +Wire Wire Line + 5000 5700 5000 5850 +$Comp +L pspice:MNMOS M5 +U 1 1 5B25C8DC +P 4900 5500 +F 0 "M5" H 5188 5546 50 0000 L CNN +F 1 "MNMOS" H 5188 5455 50 0000 L CNN +F 2 "" H 4875 5500 50 0001 C CNN +F 3 "" H 4875 5500 50 0001 C CNN + 1 4900 5500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 5700 5100 5850 +Wire Wire Line + 5100 5850 5000 5850 +Wire Wire Line + 5000 5850 5000 6350 +Connection ~ 5000 5850 +Wire Wire Line + 4700 5500 4550 5500 +Text GLabel 4550 5500 0 50 Input ~ 0 +C +Text GLabel 5000 5050 0 50 UnSpc ~ 0 +2 +$Comp +L pspice:0 #GND05 +U 1 1 5B25F78D +P 1400 7550 +F 0 "#GND05" H 1400 7450 50 0001 C CNN +F 1 "0" H 1400 7637 50 0000 C CNN +F 2 "" H 1400 7550 50 0001 C CNN +F 3 "" H 1400 7550 50 0001 C CNN + 1 1400 7550 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V4 +U 1 1 5B25F796 +P 1400 6800 +F 0 "V4" H 1828 6846 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 200m 400m)" H 1828 6755 50 0000 L CNN +F 2 "" H 1400 6800 50 0001 C CNN +F 3 "" H 1400 6800 50 0001 C CNN +F 4 "V" H 1400 6800 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 200m 400m)" H 1400 6800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 6800 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 6800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 7550 1400 7500 +Wire Wire Line + 1400 6000 1400 6100 +Text GLabel 1500 6000 2 50 Output ~ 0 +C +Wire Wire Line + 1400 6000 1500 6000 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand3/cmos_nand3.cir b/digital ciruits/cmos_nand3/cmos_nand3.cir new file mode 100644 index 0000000..d14d3d6 --- /dev/null +++ b/digital ciruits/cmos_nand3/cmos_nand3.cir @@ -0,0 +1,19 @@ +.title KiCad schematic +V1 B 0 dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 VDD 0 3.3 +M1 Out A VDD VDD MPMOS +M2 Out A 1 1 MNMOS +M4 Out B VDD VDD MPMOS +M3 1 B 2 2 MNMOS +V3 A 0 dc 0 pulse(0 3.3 0 0 0 50m 100m) +M6 Out C VDD VDD MPMOS +M5 2 C 0 0 MNMOS +V4 C 0 dc 0 pulse(0 3.3 0 0 0 200m 400m) +.tran 1m 400m +.model mnmos nmos level=8 version=3.3.0 +.model mpmos pmos level=8 version=3.3.0 +.control +run +plot v(a)+5 v(b)+10 v(c)+15 v(out) +.endc +.end diff --git a/digital ciruits/cmos_nand3/cmos_nand3.pro b/digital ciruits/cmos_nand3/cmos_nand3.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/cmos_nand3/cmos_nand3.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/cmos_nand3/cmos_nand3.sch b/digital ciruits/cmos_nand3/cmos_nand3.sch new file mode 100644 index 0000000..a30dc17 --- /dev/null +++ b/digital ciruits/cmos_nand3/cmos_nand3.sch @@ -0,0 +1,386 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand3-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 5800 +F 0 "#GND01" H 1400 5700 50 0001 C CNN +F 1 "0" H 1400 5887 50 0000 C CNN +F 2 "" H 1400 5800 50 0001 C CNN +F 3 "" H 1400 5800 50 0001 C CNN + 1 1400 5800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 5050 +F 0 "V1" H 1828 5096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 5005 50 0000 L CNN +F 2 "" H 1400 5050 50 0001 C CNN +F 3 "" H 1400 5050 50 0001 C CNN +F 4 "V" H 1400 5050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 5050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5050 + 1 0 0 -1 +$EndComp +Text GLabel 4550 2700 0 50 Input ~ 0 +A +Text GLabel 8700 3100 2 50 Output ~ 0 +Out +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5000 2250 +F 0 "#PWR02" H 5000 2100 50 0001 C CNN +F 1 "VDD" H 5017 2423 50 0000 C CNN +F 2 "" H 5000 2250 50 0001 C CNN +F 3 "" H 5000 2250 50 0001 C CNN + 1 5000 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3700 5000 3850 +Wire Wire Line + 4700 3500 4550 3500 +Wire Wire Line + 5000 2500 5000 2450 +Wire Notes Line + 4650 2400 4650 6150 +Wire Notes Line + 8400 6150 8400 2400 +Wire Notes Line + 8400 2400 4650 2400 +Wire Notes Line + 4650 6150 8400 6150 +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Wire Wire Line + 4700 2700 4550 2700 +Text Notes 9150 1400 0 50 ~ 0 +.tran 1m 400m +Text Notes 9150 1150 0 50 ~ 0 +.model mnmos nmos level=8 version=3.3.0\n.model mpmos pmos level=8 version=3.3.0\n +$Comp +L pspice:MPMOS M1 +U 1 1 5B2448E1 +P 4900 2700 +F 0 "M1" H 5187 2746 50 0000 L CNN +F 1 "MPMOS" H 5187 2655 50 0000 L CNN +F 2 "" H 4900 2700 50 0001 C CNN +F 3 "" H 4900 2700 50 0001 C CNN + 1 4900 2700 + 1 0 0 -1 +$EndComp +$Comp +L pspice:MNMOS M2 +U 1 1 5B244930 +P 4900 3500 +F 0 "M2" H 5188 3546 50 0000 L CNN +F 1 "MNMOS" H 5188 3455 50 0000 L CNN +F 2 "" H 4875 3500 50 0001 C CNN +F 3 "" H 4875 3500 50 0001 C CNN + 1 4900 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 2500 5100 2450 +Wire Wire Line + 5100 2450 5000 2450 +Connection ~ 5000 2450 +Wire Wire Line + 5000 2450 5000 2250 +Wire Wire Line + 5100 3700 5100 3850 +Wire Wire Line + 5100 3850 5000 3850 +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 3-input NAND gate PMOS/NMOS\n2. Run the simulation and plot V(A), V(B), V(C), V(out) +$Comp +L pspice:MPMOS M4 +U 1 1 5B249F5D +P 6350 2700 +F 0 "M4" H 6637 2746 50 0000 L CNN +F 1 "MPMOS" H 6637 2655 50 0000 L CNN +F 2 "" H 6350 2700 50 0001 C CNN +F 3 "" H 6350 2700 50 0001 C CNN + 1 6350 2700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR03 +U 1 1 5B249FBF +P 6450 2250 +F 0 "#PWR03" H 6450 2100 50 0001 C CNN +F 1 "VDD" H 6467 2423 50 0000 C CNN +F 2 "" H 6450 2250 50 0001 C CNN +F 3 "" H 6450 2250 50 0001 C CNN + 1 6450 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 2500 6450 2450 +Wire Wire Line + 6450 2450 6550 2450 +Wire Wire Line + 6550 2450 6550 2500 +Connection ~ 6450 2450 +Wire Wire Line + 6450 2450 6450 2250 +Text GLabel 5950 2700 0 50 Input ~ 0 +B +Wire Wire Line + 5950 2700 6150 2700 +Wire Wire Line + 5000 2900 5000 3100 +Wire Wire Line + 5000 4650 5000 4800 +Wire Wire Line + 4700 4450 4550 4450 +$Comp +L pspice:MNMOS M3 +U 1 1 5B24A6A3 +P 4900 4450 +F 0 "M3" H 5188 4496 50 0000 L CNN +F 1 "MNMOS" H 5188 4405 50 0000 L CNN +F 2 "" H 4875 4450 50 0001 C CNN +F 3 "" H 4875 4450 50 0001 C CNN + 1 4900 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4650 5100 4800 +Wire Wire Line + 5100 4800 5000 4800 +Wire Wire Line + 5000 3850 5000 4250 +Text GLabel 1500 4250 2 50 Output ~ 0 +B +Text GLabel 1500 2500 2 50 Output ~ 0 +A +Wire Wire Line + 5000 3100 6450 3100 +Wire Wire Line + 6450 3100 6450 2900 +Connection ~ 5000 3100 +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 8700 3100 7750 3100 +Connection ~ 6450 3100 +Connection ~ 5000 3850 +Text GLabel 4550 3500 0 50 Input ~ 0 +A +Text GLabel 4550 4450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B24C547 +P 5000 6350 +F 0 "#GND03" H 5000 6250 50 0001 C CNN +F 1 "0" H 5000 6437 50 0000 C CNN +F 2 "" H 5000 6350 50 0001 C CNN +F 3 "" H 5000 6350 50 0001 C CNN + 1 5000 6350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 4800 5000 5300 +Connection ~ 5000 4800 +Wire Wire Line + 1400 4250 1500 4250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 4050 +F 0 "#GND02" H 1400 3950 50 0001 C CNN +F 1 "0" H 1400 4137 50 0000 C CNN +F 2 "" H 1400 4050 50 0001 C CNN +F 3 "" H 1400 4050 50 0001 C CNN + 1 1400 4050 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 3300 +F 0 "V3" H 1828 3346 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 3255 50 0000 L CNN +F 2 "" H 1400 3300 50 0001 C CNN +F 3 "" H 1400 3300 50 0001 C CNN +F 4 "V" H 1400 3300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 3300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2500 1500 2500 +Text Notes 1050 2100 0 50 ~ 0 +Test input signals +Text Notes 9150 1950 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(c)+15 v(out)\n.endc +Text GLabel 5000 4100 0 50 UnSpc ~ 0 +1 +$Comp +L pspice:MPMOS M6 +U 1 1 5B25ABD4 +P 7650 2700 +F 0 "M6" H 7937 2746 50 0000 L CNN +F 1 "MPMOS" H 7937 2655 50 0000 L CNN +F 2 "" H 7650 2700 50 0001 C CNN +F 3 "" H 7650 2700 50 0001 C CNN + 1 7650 2700 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B25ABDB +P 7750 2250 +F 0 "#PWR04" H 7750 2100 50 0001 C CNN +F 1 "VDD" H 7767 2423 50 0000 C CNN +F 2 "" H 7750 2250 50 0001 C CNN +F 3 "" H 7750 2250 50 0001 C CNN + 1 7750 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 2500 7750 2450 +Wire Wire Line + 7750 2450 7850 2450 +Wire Wire Line + 7850 2450 7850 2500 +Connection ~ 7750 2450 +Wire Wire Line + 7750 2450 7750 2250 +Text GLabel 7250 2700 0 50 Input ~ 0 +C +Wire Wire Line + 7250 2700 7450 2700 +Wire Wire Line + 7750 3100 7750 2900 +Connection ~ 7750 3100 +Wire Wire Line + 7750 3100 6450 3100 +Wire Wire Line + 5000 5700 5000 5850 +$Comp +L pspice:MNMOS M5 +U 1 1 5B25C8DC +P 4900 5500 +F 0 "M5" H 5188 5546 50 0000 L CNN +F 1 "MNMOS" H 5188 5455 50 0000 L CNN +F 2 "" H 4875 5500 50 0001 C CNN +F 3 "" H 4875 5500 50 0001 C CNN + 1 4900 5500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 5700 5100 5850 +Wire Wire Line + 5100 5850 5000 5850 +Wire Wire Line + 5000 5850 5000 6350 +Connection ~ 5000 5850 +Wire Wire Line + 4700 5500 4550 5500 +Text GLabel 4550 5500 0 50 Input ~ 0 +C +Text GLabel 5000 5050 0 50 UnSpc ~ 0 +2 +$Comp +L pspice:0 #GND05 +U 1 1 5B25F78D +P 1400 7550 +F 0 "#GND05" H 1400 7450 50 0001 C CNN +F 1 "0" H 1400 7637 50 0000 C CNN +F 2 "" H 1400 7550 50 0001 C CNN +F 3 "" H 1400 7550 50 0001 C CNN + 1 1400 7550 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V4 +U 1 1 5B25F796 +P 1400 6800 +F 0 "V4" H 1828 6846 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 200m 400m)" H 1828 6755 50 0000 L CNN +F 2 "" H 1400 6800 50 0001 C CNN +F 3 "" H 1400 6800 50 0001 C CNN +F 4 "V" H 1400 6800 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 200m 400m)" H 1400 6800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 6800 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 6800 + 1 0 0 -1 +$EndComp +Text GLabel 1500 6000 2 50 Output ~ 0 +C +Wire Wire Line + 1400 6000 1500 6000 +Wire Wire Line + 1400 2500 1400 3000 +Wire Wire Line + 1400 3600 1400 4050 +Wire Wire Line + 1400 4250 1400 4750 +Wire Wire Line + 1400 5350 1400 5800 +Wire Wire Line + 1400 6000 1400 6500 +Wire Wire Line + 1400 7100 1400 7550 +Wire Wire Line + 10200 3500 10200 3100 +Wire Wire Line + 10200 4100 10200 4500 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib new file mode 100644 index 0000000..a3cd44b --- /dev/null +++ b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND3 +# +DEF sim_logic:CMOS_NAND3 X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND3" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 0 200 R 50 50 1 1 I +X C C -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.bak b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.bak new file mode 100644 index 0000000..a348c75 --- /dev/null +++ b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.bak @@ -0,0 +1,456 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_dflip-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 3800 1400 3750 +Text GLabel 4200 6100 0 50 Input ~ 0 +D +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 6400 3100 +F 0 "#PWR02" H 6400 2950 50 0001 C CNN +F 1 "VDD" H 6417 3273 50 0000 C CNN +F 2 "" H 6400 3100 50 0001 C CNN +F 3 "" H 6400 3100 50 0001 C CNN + 1 6400 3100 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A positive edge triggered D-type Flip-flop\n\nfrom https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Classical_positive-edge-triggered_D_flip-flop +Wire Wire Line + 1400 2250 1400 2350 +Text Notes 8950 1400 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a D-type flip-flop\n2. Run the simulation and plot V(D), V(CLK), V(Q), V(nQ)\n3. You can also export a SPICE netlist and run in ngspice +Text GLabel 1500 2250 2 50 Output ~ 0 +D +Text GLabel 1500 4200 2 50 Output ~ 0 +CLK +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 5750 1400 5700 +Wire Wire Line + 1400 4200 1400 4300 +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 8950 1950 0 50 ~ 0 +.control\nrun\nplot v(D)+15 v(CLK)+10 v(Q)+5 v(nQ)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 6200 3500 +F 0 "X1" H 6400 3228 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 3137 50 0000 C CNN +F 2 "" H 6200 3500 50 0001 C CNN +F 3 "" H 6200 3500 50 0001 C CNN +F 4 "X" H 6200 3500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 3500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 3500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 3500 50 0001 C CNN "Spice_Lib_File" + 1 6200 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3500 6950 3500 +Text GLabel 7350 3500 2 50 Output ~ 0 +Q +$Comp +L device:R R1 +U 1 1 5B2526A7 +P 7750 3650 +F 0 "R1" H 7820 3696 50 0000 L CNN +F 1 "10meg" H 7820 3605 50 0000 L CNN +F 2 "" V 7680 3650 50 0001 C CNN +F 3 "" H 7750 3650 50 0001 C CNN + 1 7750 3650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 7750 3950 +F 0 "#GND03" H 7750 3850 50 0001 C CNN +F 1 "0" H 7750 4037 50 0000 C CNN +F 2 "" H 7750 3950 50 0001 C CNN +F 3 "" H 7750 3950 50 0001 C CNN + 1 7750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3800 7750 3950 +$Comp +L power:VDD #PWR03 +U 1 1 5B253303 +P 5100 3000 +F 0 "#PWR03" H 5100 2850 50 0001 C CNN +F 1 "VDD" H 5117 3173 50 0000 C CNN +F 2 "" H 5100 3000 50 0001 C CNN +F 3 "" H 5100 3000 50 0001 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B25330D +P 4900 3400 +F 0 "X2" H 5100 3128 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 3037 50 0000 C CNN +F 2 "" H 4900 3400 50 0001 C CNN +F 3 "" H 4900 3400 50 0001 C CNN +F 4 "X" H 4900 3400 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 3400 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 3400 50 0001 C CNN "Spice_Lib_File" + 1 4900 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B2533AE +P 5100 4400 +F 0 "#PWR04" H 5100 4250 50 0001 C CNN +F 1 "VDD" H 5117 4573 50 0000 C CNN +F 2 "" H 5100 4400 50 0001 C CNN +F 3 "" H 5100 4400 50 0001 C CNN + 1 5100 4400 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X3 +U 1 1 5B2533B8 +P 4900 4800 +F 0 "X3" H 5100 4528 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 4437 50 0000 C CNN +F 2 "" H 4900 4800 50 0001 C CNN +F 3 "" H 4900 4800 50 0001 C CNN +F 4 "X" H 4900 4800 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 4900 4800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 4800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 4800 50 0001 C CNN "Spice_Lib_File" + 1 4900 4800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR05 +U 1 1 5B25340B +P 6400 4300 +F 0 "#PWR05" H 6400 4150 50 0001 C CNN +F 1 "VDD" H 6417 4473 50 0000 C CNN +F 2 "" H 6400 4300 50 0001 C CNN +F 3 "" H 6400 4300 50 0001 C CNN + 1 6400 4300 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X4 +U 1 1 5B253415 +P 6200 4700 +F 0 "X4" H 6400 4428 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 4337 50 0000 C CNN +F 2 "" H 6200 4700 50 0001 C CNN +F 3 "" H 6200 4700 50 0001 C CNN +F 4 "X" H 6200 4700 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 4700 50 0001 C CNN "Spice_Lib_File" + 1 6200 4700 + 1 0 0 -1 +$EndComp +Text GLabel 4200 4250 0 50 Input ~ 0 +CLK +Wire Wire Line + 4200 6100 4700 6100 +Wire Wire Line + 4700 3500 4400 3500 +Wire Wire Line + 4400 3500 4400 4250 +Wire Wire Line + 6000 3400 5600 3400 +Wire Wire Line + 6000 4800 5600 4800 +Wire Wire Line + 6000 3600 5900 3600 +Wire Wire Line + 5900 3600 5900 3900 +Wire Wire Line + 5900 3900 6950 4200 +Wire Wire Line + 6950 4200 6950 4700 +Wire Wire Line + 6950 4700 6800 4700 +Wire Wire Line + 6800 3500 6950 3500 +Wire Wire Line + 6950 3500 6950 3900 +Wire Wire Line + 6950 3900 5900 4200 +Wire Wire Line + 5900 4200 5900 4600 +Wire Wire Line + 5900 4600 6000 4600 +Wire Wire Line + 4700 4700 4600 4700 +Wire Wire Line + 4600 4700 4600 4200 +Wire Wire Line + 5500 3400 5600 3400 +Connection ~ 5600 3400 +Wire Wire Line + 5600 3400 5600 3900 +Wire Wire Line + 4600 4200 5600 3900 +Connection ~ 6950 3500 +Wire Wire Line + 7750 4700 6950 4700 +Text GLabel 7350 4700 2 50 Output ~ 0 +nQ +$Comp +L device:R R2 +U 1 1 5B254999 +P 7750 4850 +F 0 "R2" H 7820 4896 50 0000 L CNN +F 1 "10meg" H 7820 4805 50 0000 L CNN +F 2 "" V 7680 4850 50 0001 C CNN +F 3 "" H 7750 4850 50 0001 C CNN + 1 7750 4850 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND05 +U 1 1 5B2549A0 +P 7750 5150 +F 0 "#GND05" H 7750 5050 50 0001 C CNN +F 1 "0" H 7750 5237 50 0000 C CNN +F 2 "" H 7750 5150 50 0001 C CNN +F 3 "" H 7750 5150 50 0001 C CNN + 1 7750 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 5000 7750 5150 +Wire Notes Line + 4300 6450 7200 6450 +Wire Notes Line + 7200 6450 7200 1500 +Wire Notes Line + 7200 1500 4300 1500 +Wire Notes Line + 4300 1500 4300 6450 +Connection ~ 6950 4700 +Text GLabel 5800 3400 0 50 UnSpc ~ 0 +1 +Text GLabel 5750 4800 0 50 UnSpc ~ 0 +2 +$Comp +L sim_logic:CMOS_NAND X5 +U 1 1 5B269CCD +P 4900 2200 +F 0 "X5" H 5100 1928 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 1837 50 0000 C CNN +F 2 "" H 4900 2200 50 0001 C CNN +F 3 "" H 4900 2200 50 0001 C CNN +F 4 "X" H 4900 2200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 2200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 2200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 2200 50 0001 C CNN "Spice_Lib_File" + 1 4900 2200 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR06 +U 1 1 5B269D15 +P 5100 1800 +F 0 "#PWR06" H 5100 1650 50 0001 C CNN +F 1 "VDD" H 5117 1973 50 0000 C CNN +F 2 "" H 5100 1800 50 0001 C CNN +F 3 "" H 5100 1800 50 0001 C CNN + 1 5100 1800 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X6 +U 1 1 5B269DBA +P 4900 6000 +F 0 "X6" H 5100 5728 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 5637 50 0000 C CNN +F 2 "" H 4900 6000 50 0001 C CNN +F 3 "" H 4900 6000 50 0001 C CNN +F 4 "X" H 4900 6000 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 6000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 6000 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 6000 50 0001 C CNN "Spice_Lib_File" + 1 4900 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 4250 4400 4250 +Connection ~ 4400 4250 +Wire Wire Line + 4400 4250 4400 4800 +$Comp +L power:VDD #PWR07 +U 1 1 5B26A720 +P 5100 5600 +F 0 "#PWR07" H 5100 5450 50 0001 C CNN +F 1 "VDD" H 5117 5773 50 0000 C CNN +F 2 "" H 5100 5600 50 0001 C CNN +F 3 "" H 5100 5600 50 0001 C CNN + 1 5100 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4800 4700 4800 +Wire Wire Line + 4500 2100 4500 4900 +Wire Wire Line + 4500 4900 4600 4900 +Wire Wire Line + 5600 4800 5600 5300 +Wire Wire Line + 5600 5300 4600 5600 +Wire Wire Line + 4600 5600 4600 5900 +Wire Wire Line + 4600 5900 4700 5900 +Connection ~ 5600 4800 +Wire Wire Line + 5600 4800 5500 4800 +Wire Wire Line + 4600 4900 4600 5250 +Wire Wire Line + 4600 5250 5600 5550 +Wire Wire Line + 5600 5550 5600 6000 +Wire Wire Line + 5600 6000 5500 6000 +Connection ~ 4600 4900 +Wire Wire Line + 4600 4900 4700 4900 +Wire Wire Line + 4500 2100 4700 2100 +Wire Wire Line + 4700 2300 4600 2300 +Wire Wire Line + 4600 2300 4600 2500 +Wire Wire Line + 4600 2500 5600 2850 +Wire Wire Line + 5600 2850 5600 3400 +Wire Wire Line + 5500 2200 5600 2200 +Wire Wire Line + 5600 2200 5600 2500 +Wire Wire Line + 5600 2500 4600 2850 +Wire Wire Line + 4600 2850 4600 3300 +Wire Wire Line + 4600 3300 4700 3300 +Text GLabel 5600 5700 0 50 UnSpc ~ 0 +3 +Text GLabel 5600 2400 0 50 UnSpc ~ 0 +4 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.cir b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.cir new file mode 100644 index 0000000..27d60ce --- /dev/null +++ b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.cir @@ -0,0 +1,19 @@ +.title KiCad schematic +.include "../libs/spice_models.lib" +V1 D 0 dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 VDD GND 3.3 +V3 CLK 0 dc 0 pulse(0 3.3 25m 0 0 50m 100m) +X1 Net-_X1-PadA_ nq q VDD NAND +X2 Net-_X2-PadA_ CLK Net-_X1-PadA_ VDD NAND +X3 Net-_X1-PadA_ CLK Net-_X3-PadC_ Net-_X3-PadOut_ VDD NAND3 +X4 q Net-_X3-PadOut_ nq VDD NAND +X5 Net-_X3-PadC_ Net-_X1-PadA_ Net-_X2-PadA_ VDD NAND +X6 Net-_X3-PadOut_ D Net-_X3-PadC_ VDD NAND +R2 0 q 10meg +R1 0 nq 10meg +.tran 1m 400m +.control +run +plot v(D)+15 v(CLK)+10 v(Q)+5 v(nQ) +.endc +.end diff --git a/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.pro b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.sch b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.sch new file mode 100644 index 0000000..6b5df42 --- /dev/null +++ b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip.sch @@ -0,0 +1,474 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_dflip-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Text GLabel 4200 6100 0 50 Input ~ 0 +D +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 6400 3100 +F 0 "#PWR02" H 6400 2950 50 0001 C CNN +F 1 "VDD" H 6417 3273 50 0000 C CNN +F 2 "" H 6400 3100 50 0001 C CNN +F 3 "" H 6400 3100 50 0001 C CNN + 1 6400 3100 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A positive edge triggered D-type Flip-flop\n\nfrom https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Classical_positive-edge-triggered_D_flip-flop +Text Notes 8950 1400 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a D-type flip-flop\n2. Run the simulation and plot V(D), V(CLK), V(Q), V(nQ)\n3. You can also export a SPICE netlist and run in ngspice +Text GLabel 1500 2250 2 50 Output ~ 0 +D +Text GLabel 1500 4200 2 50 Output ~ 0 +CLK +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 8950 1950 0 50 ~ 0 +.control\nrun\nplot v(D)+15 v(CLK)+10 v(Q)+5 v(nQ)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 6200 3500 +F 0 "X1" H 6400 3228 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 3137 50 0000 C CNN +F 2 "" H 6200 3500 50 0001 C CNN +F 3 "" H 6200 3500 50 0001 C CNN +F 4 "X" H 6200 3500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 3500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 3500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 3500 50 0001 C CNN "Spice_Lib_File" + 1 6200 3500 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 7750 3950 +F 0 "#GND03" H 7750 3850 50 0001 C CNN +F 1 "0" H 7750 4037 50 0000 C CNN +F 2 "" H 7750 3950 50 0001 C CNN +F 3 "" H 7750 3950 50 0001 C CNN + 1 7750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3800 7750 3950 +$Comp +L power:VDD #PWR03 +U 1 1 5B253303 +P 5100 3000 +F 0 "#PWR03" H 5100 2850 50 0001 C CNN +F 1 "VDD" H 5117 3173 50 0000 C CNN +F 2 "" H 5100 3000 50 0001 C CNN +F 3 "" H 5100 3000 50 0001 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B25330D +P 4900 3400 +F 0 "X2" H 5100 3128 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 3037 50 0000 C CNN +F 2 "" H 4900 3400 50 0001 C CNN +F 3 "" H 4900 3400 50 0001 C CNN +F 4 "X" H 4900 3400 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 3400 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 3400 50 0001 C CNN "Spice_Lib_File" + 1 4900 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B2533AE +P 5100 4400 +F 0 "#PWR04" H 5100 4250 50 0001 C CNN +F 1 "VDD" H 5117 4573 50 0000 C CNN +F 2 "" H 5100 4400 50 0001 C CNN +F 3 "" H 5100 4400 50 0001 C CNN + 1 5100 4400 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X3 +U 1 1 5B2533B8 +P 4900 4800 +F 0 "X3" H 5100 4528 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 4437 50 0000 C CNN +F 2 "" H 4900 4800 50 0001 C CNN +F 3 "" H 4900 4800 50 0001 C CNN +F 4 "X" H 4900 4800 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 4900 4800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 4800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 4800 50 0001 C CNN "Spice_Lib_File" + 1 4900 4800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR05 +U 1 1 5B25340B +P 6400 4300 +F 0 "#PWR05" H 6400 4150 50 0001 C CNN +F 1 "VDD" H 6417 4473 50 0000 C CNN +F 2 "" H 6400 4300 50 0001 C CNN +F 3 "" H 6400 4300 50 0001 C CNN + 1 6400 4300 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X4 +U 1 1 5B253415 +P 6200 4700 +F 0 "X4" H 6400 4428 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 4337 50 0000 C CNN +F 2 "" H 6200 4700 50 0001 C CNN +F 3 "" H 6200 4700 50 0001 C CNN +F 4 "X" H 6200 4700 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 4700 50 0001 C CNN "Spice_Lib_File" + 1 6200 4700 + 1 0 0 -1 +$EndComp +Text GLabel 4200 4250 0 50 Input ~ 0 +CLK +Wire Wire Line + 4200 6100 4700 6100 +Wire Wire Line + 4700 3500 4400 3500 +Wire Wire Line + 4400 3500 4400 4250 +Wire Wire Line + 6000 3400 5600 3400 +Wire Wire Line + 6000 4800 5600 4800 +Wire Wire Line + 6000 3600 5900 3600 +Wire Wire Line + 5900 3600 5900 3900 +Wire Wire Line + 5900 3900 6950 4200 +Wire Wire Line + 6950 4200 6950 4700 +Wire Wire Line + 6950 4700 6800 4700 +Wire Wire Line + 6800 3500 6950 3500 +Wire Wire Line + 6950 3500 6950 3900 +Wire Wire Line + 6950 3900 5900 4200 +Wire Wire Line + 5900 4200 5900 4600 +Wire Wire Line + 5900 4600 6000 4600 +Wire Wire Line + 4700 4700 4600 4700 +Wire Wire Line + 4600 4700 4600 4200 +Wire Wire Line + 5500 3400 5600 3400 +Connection ~ 5600 3400 +Wire Wire Line + 5600 3400 5600 3900 +Wire Wire Line + 4600 4200 5600 3900 +Connection ~ 6950 3500 +$Comp +L pspice:0 #GND05 +U 1 1 5B2549A0 +P 7750 5150 +F 0 "#GND05" H 7750 5050 50 0001 C CNN +F 1 "0" H 7750 5237 50 0000 C CNN +F 2 "" H 7750 5150 50 0001 C CNN +F 3 "" H 7750 5150 50 0001 C CNN + 1 7750 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 5000 7750 5150 +Wire Notes Line + 4300 6450 7200 6450 +Wire Notes Line + 7200 6450 7200 1500 +Wire Notes Line + 7200 1500 4300 1500 +Wire Notes Line + 4300 1500 4300 6450 +Connection ~ 6950 4700 +$Comp +L sim_logic:CMOS_NAND X5 +U 1 1 5B269CCD +P 4900 2200 +F 0 "X5" H 5100 1928 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 1837 50 0000 C CNN +F 2 "" H 4900 2200 50 0001 C CNN +F 3 "" H 4900 2200 50 0001 C CNN +F 4 "X" H 4900 2200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 2200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 2200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 2200 50 0001 C CNN "Spice_Lib_File" + 1 4900 2200 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR06 +U 1 1 5B269D15 +P 5100 1800 +F 0 "#PWR06" H 5100 1650 50 0001 C CNN +F 1 "VDD" H 5117 1973 50 0000 C CNN +F 2 "" H 5100 1800 50 0001 C CNN +F 3 "" H 5100 1800 50 0001 C CNN + 1 5100 1800 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X6 +U 1 1 5B269DBA +P 4900 6000 +F 0 "X6" H 5100 5728 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 5637 50 0000 C CNN +F 2 "" H 4900 6000 50 0001 C CNN +F 3 "" H 4900 6000 50 0001 C CNN +F 4 "X" H 4900 6000 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 6000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 6000 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 6000 50 0001 C CNN "Spice_Lib_File" + 1 4900 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 4250 4400 4250 +Connection ~ 4400 4250 +Wire Wire Line + 4400 4250 4400 4800 +$Comp +L power:VDD #PWR07 +U 1 1 5B26A720 +P 5100 5600 +F 0 "#PWR07" H 5100 5450 50 0001 C CNN +F 1 "VDD" H 5117 5773 50 0000 C CNN +F 2 "" H 5100 5600 50 0001 C CNN +F 3 "" H 5100 5600 50 0001 C CNN + 1 5100 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4800 4700 4800 +Wire Wire Line + 4500 2100 4500 4900 +Wire Wire Line + 4500 4900 4600 4900 +Wire Wire Line + 5600 4800 5600 5300 +Wire Wire Line + 5600 5300 4600 5600 +Wire Wire Line + 4600 5600 4600 5900 +Wire Wire Line + 4600 5900 4700 5900 +Connection ~ 5600 4800 +Wire Wire Line + 5600 4800 5500 4800 +Wire Wire Line + 4600 4900 4600 5250 +Wire Wire Line + 4600 5250 5600 5550 +Wire Wire Line + 5600 5550 5600 6000 +Wire Wire Line + 5600 6000 5500 6000 +Connection ~ 4600 4900 +Wire Wire Line + 4600 4900 4700 4900 +Wire Wire Line + 4500 2100 4700 2100 +Wire Wire Line + 4700 2300 4600 2300 +Wire Wire Line + 4600 2300 4600 2500 +Wire Wire Line + 4600 2500 5600 2850 +Wire Wire Line + 5600 2850 5600 3400 +Wire Wire Line + 5500 2200 5600 2200 +Wire Wire Line + 5600 2200 5600 2500 +Wire Wire Line + 5600 2500 4600 2850 +Wire Wire Line + 4600 2850 4600 3300 +Wire Wire Line + 4600 3300 4700 3300 +Wire Wire Line + 1400 4200 1400 4700 +Wire Wire Line + 1400 5300 1400 5750 +Wire Wire Line + 1400 3350 1400 3800 +Wire Wire Line + 1400 2250 1400 2750 +$Comp +L Device:R R2 +U 1 1 5B2779BB +P 8200 3500 +F 0 "R2" V 7993 3500 50 0000 C CNN +F 1 "10meg" V 8084 3500 50 0000 C CNN +F 2 "" V 8130 3500 50 0001 C CNN +F 3 "~" H 8200 3500 50 0001 C CNN + 1 8200 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 6950 3500 7750 3500 +Wire Wire Line + 8350 3500 8350 3800 +Wire Wire Line + 8350 3800 7750 3800 +$Comp +L Device:R R1 +U 1 1 5B279A93 +P 8150 4700 +F 0 "R1" V 7943 4700 50 0000 C CNN +F 1 "10meg" V 8034 4700 50 0000 C CNN +F 2 "" V 8080 4700 50 0001 C CNN +F 3 "~" H 8150 4700 50 0001 C CNN + 1 8150 4700 + 0 1 1 0 +$EndComp +Wire Wire Line + 6950 4700 7900 4700 +Wire Wire Line + 8300 4700 8300 5000 +Wire Wire Line + 8300 5000 7750 5000 +Wire Wire Line + 10200 3500 10200 3100 +$Comp +L power:GND #PWR08 +U 1 1 5B27CBF5 +P 10200 4550 +F 0 "#PWR08" H 10200 4300 50 0001 C CNN +F 1 "GND" H 10205 4377 50 0000 C CNN +F 2 "" H 10200 4550 50 0001 C CNN +F 3 "" H 10200 4550 50 0001 C CNN + 1 10200 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10200 4550 10200 4100 +Text GLabel 7600 3050 0 50 Output ~ 0 +q +Wire Wire Line + 7600 3050 7750 3050 +Wire Wire Line + 7750 3050 7750 3500 +Connection ~ 7750 3500 +Wire Wire Line + 7750 3500 8050 3500 +Text GLabel 7750 4350 0 50 Output ~ 0 +nq +Wire Wire Line + 7750 4350 7900 4350 +Wire Wire Line + 7900 4350 7900 4700 +Connection ~ 7900 4700 +Wire Wire Line + 7900 4700 8000 4700 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_dflip/sym-lib-table b/digital ciruits/cmos_nand_dflip/sym-lib-table new file mode 100644 index 0000000..63105ad --- /dev/null +++ b/digital ciruits/cmos_nand_dflip/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sim_logic)(type Legacy)(uri ${KIPRJMOD}/../libs/sim_logic.lib)(options "")(descr "")) +) diff --git a/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch-cache.lib b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch-cache.lib new file mode 100644 index 0000000..d0e6eb2 --- /dev/null +++ b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.bak b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.bak new file mode 100644 index 0000000..8f57d2b --- /dev/null +++ b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.bak @@ -0,0 +1,352 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_dlatch-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 3800 1400 3750 +Text GLabel 4200 3300 0 50 Input ~ 0 +D +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 6400 3100 +F 0 "#PWR02" H 6400 2950 50 0001 C CNN +F 1 "VDD" H 6417 3273 50 0000 C CNN +F 2 "" H 6400 3100 50 0001 C CNN +F 3 "" H 6400 3100 50 0001 C CNN + 1 6400 3100 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A Gated D Latch\n\nfrom https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch +Wire Wire Line + 1400 2250 1400 2350 +Text Notes 6550 1450 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a D-latch\n2. Run the simulation and plot V(D), V(E), V(Q), V(nQ)\n3. You can also export a SPICE netlist and run in ngspice +Text GLabel 1500 2250 2 50 Output ~ 0 +D +Text GLabel 1500 4200 2 50 Output ~ 0 +E +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 5750 1400 5700 +Wire Wire Line + 1400 4200 1400 4300 +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 6550 2000 0 50 ~ 0 +.control\nrun\nplot v(D)+15 v(E)+10 v(Q)+5 v(nQ)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 6200 3500 +F 0 "X1" H 6400 3228 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 3137 50 0000 C CNN +F 2 "" H 6200 3500 50 0001 C CNN +F 3 "" H 6200 3500 50 0001 C CNN +F 4 "X" H 6200 3500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 3500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 3500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 3500 50 0001 C CNN "Spice_Lib_File" + 1 6200 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3500 6950 3500 +Text GLabel 7400 3500 0 50 BiDi ~ 0 +Q +$Comp +L device:R R1 +U 1 1 5B2526A7 +P 7750 3650 +F 0 "R1" H 7820 3696 50 0000 L CNN +F 1 "10meg" H 7820 3605 50 0000 L CNN +F 2 "" V 7680 3650 50 0001 C CNN +F 3 "" H 7750 3650 50 0001 C CNN + 1 7750 3650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 7750 3950 +F 0 "#GND03" H 7750 3850 50 0001 C CNN +F 1 "0" H 7750 4037 50 0000 C CNN +F 2 "" H 7750 3950 50 0001 C CNN +F 3 "" H 7750 3950 50 0001 C CNN + 1 7750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3800 7750 3950 +$Comp +L power:VDD #PWR03 +U 1 1 5B253303 +P 5100 3000 +F 0 "#PWR03" H 5100 2850 50 0001 C CNN +F 1 "VDD" H 5117 3173 50 0000 C CNN +F 2 "" H 5100 3000 50 0001 C CNN +F 3 "" H 5100 3000 50 0001 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B25330D +P 4900 3400 +F 0 "X2" H 5100 3128 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 3037 50 0000 C CNN +F 2 "" H 4900 3400 50 0001 C CNN +F 3 "" H 4900 3400 50 0001 C CNN +F 4 "X" H 4900 3400 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 3400 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 3400 50 0001 C CNN "Spice_Lib_File" + 1 4900 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B2533AE +P 5100 4400 +F 0 "#PWR04" H 5100 4250 50 0001 C CNN +F 1 "VDD" H 5117 4573 50 0000 C CNN +F 2 "" H 5100 4400 50 0001 C CNN +F 3 "" H 5100 4400 50 0001 C CNN + 1 5100 4400 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X3 +U 1 1 5B2533B8 +P 4900 4800 +F 0 "X3" H 5100 4528 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 4437 50 0000 C CNN +F 2 "" H 4900 4800 50 0001 C CNN +F 3 "" H 4900 4800 50 0001 C CNN +F 4 "X" H 4900 4800 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 4800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 4800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 4800 50 0001 C CNN "Spice_Lib_File" + 1 4900 4800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR05 +U 1 1 5B25340B +P 6400 4300 +F 0 "#PWR05" H 6400 4150 50 0001 C CNN +F 1 "VDD" H 6417 4473 50 0000 C CNN +F 2 "" H 6400 4300 50 0001 C CNN +F 3 "" H 6400 4300 50 0001 C CNN + 1 6400 4300 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X4 +U 1 1 5B253415 +P 6200 4700 +F 0 "X4" H 6400 4428 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 4337 50 0000 C CNN +F 2 "" H 6200 4700 50 0001 C CNN +F 3 "" H 6200 4700 50 0001 C CNN +F 4 "X" H 6200 4700 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 4700 50 0001 C CNN "Spice_Lib_File" + 1 6200 4700 + 1 0 0 -1 +$EndComp +Text GLabel 4250 4900 0 50 Input ~ 0 +E +Wire Wire Line + 4200 3300 4700 3300 +Wire Wire Line + 4700 3500 4400 3500 +Wire Wire Line + 4400 3500 4400 4900 +Wire Wire Line + 4400 4900 4700 4900 +Wire Wire Line + 6000 3400 5550 3400 +Wire Wire Line + 6000 4800 5500 4800 +Wire Wire Line + 6000 3600 5900 3600 +Wire Wire Line + 5900 3600 5900 3900 +Wire Wire Line + 5900 3900 6950 4150 +Wire Wire Line + 6950 4150 6950 4700 +Wire Wire Line + 6950 4700 6800 4700 +Wire Wire Line + 6800 3500 6950 3500 +Wire Wire Line + 6950 3500 6950 3900 +Wire Wire Line + 6950 3900 5900 4150 +Wire Wire Line + 5900 4150 5900 4600 +Wire Wire Line + 5900 4600 6000 4600 +Wire Wire Line + 4700 4700 4600 4700 +Wire Wire Line + 4600 4700 4600 4150 +Wire Wire Line + 5500 3400 5550 3400 +Connection ~ 5550 3400 +Wire Wire Line + 5550 3400 5550 3900 +Wire Wire Line + 4600 4150 5550 3900 +Connection ~ 6950 3500 +Wire Wire Line + 7750 4700 6950 4700 +Text GLabel 7450 4700 0 50 BiDi ~ 0 +nQ +$Comp +L device:R R2 +U 1 1 5B254999 +P 7750 4850 +F 0 "R2" H 7820 4896 50 0000 L CNN +F 1 "10meg" H 7820 4805 50 0000 L CNN +F 2 "" V 7680 4850 50 0001 C CNN +F 3 "" H 7750 4850 50 0001 C CNN + 1 7750 4850 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND05 +U 1 1 5B2549A0 +P 7750 5150 +F 0 "#GND05" H 7750 5050 50 0001 C CNN +F 1 "0" H 7750 5237 50 0000 C CNN +F 2 "" H 7750 5150 50 0001 C CNN +F 3 "" H 7750 5150 50 0001 C CNN + 1 7750 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 5000 7750 5150 +Wire Notes Line + 4300 5250 7200 5250 +Wire Notes Line + 7200 5250 7200 2700 +Wire Notes Line + 7200 2700 4300 2700 +Wire Notes Line + 4300 2700 4300 5250 +Connection ~ 6950 4700 +Connection ~ 4400 4900 +Wire Wire Line + 4400 4900 4250 4900 +Text GLabel 5800 3400 0 50 UnSpc ~ 0 +1 +Text GLabel 5750 4800 0 50 UnSpc ~ 0 +2 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.cir b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.cir new file mode 100644 index 0000000..e7ca311 --- /dev/null +++ b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.cir @@ -0,0 +1,17 @@ +.title KiCad schematic +.include "../libs/spice_models.lib" +V1 D 0 dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 VDD 0 3.3 +V3 E 0 dc 0 pulse(0 3.3 25m 0 0 50m 100m) +X1 1 nQ Q VDD NAND +X2 D E 1 VDD NAND +X3 1 E 2 VDD NAND +X4 Q 2 nQ VDD NAND +R2 0 Q 10meg +R1 0 nQ 10meg +.tran 1m 400m +.control +run +plot v(D)+15 v(E)+10 v(Q)+5 v(nQ) +.endc +.end diff --git a/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.pro b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.sch b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.sch new file mode 100644 index 0000000..4c25a38 --- /dev/null +++ b/digital ciruits/cmos_nand_dlatch/cmos_nand_dlatch.sch @@ -0,0 +1,360 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_dlatch-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Text GLabel 4200 3300 0 50 Input ~ 0 +D +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 6400 3100 +F 0 "#PWR02" H 6400 2950 50 0001 C CNN +F 1 "VDD" H 6417 3273 50 0000 C CNN +F 2 "" H 6400 3100 50 0001 C CNN +F 3 "" H 6400 3100 50 0001 C CNN + 1 6400 3100 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A Gated D Latch\n\nfrom https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch +Text Notes 6550 1450 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a D-latch\n2. Run the simulation and plot V(D), V(E), V(Q), V(nQ)\n3. You can also export a SPICE netlist and run in ngspice +Text GLabel 1500 2250 2 50 Output ~ 0 +D +Text GLabel 1500 4200 2 50 Output ~ 0 +E +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 25m 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 6550 2000 0 50 ~ 0 +.control\nrun\nplot v(D)+15 v(E)+10 v(Q)+5 v(nQ)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 6200 3500 +F 0 "X1" H 6400 3228 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 3137 50 0000 C CNN +F 2 "" H 6200 3500 50 0001 C CNN +F 3 "" H 6200 3500 50 0001 C CNN +F 4 "X" H 6200 3500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 3500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 3500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 3500 50 0001 C CNN "Spice_Lib_File" + 1 6200 3500 + 1 0 0 -1 +$EndComp +Text GLabel 7400 3500 0 50 BiDi ~ 0 +Q +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 7750 3950 +F 0 "#GND03" H 7750 3850 50 0001 C CNN +F 1 "0" H 7750 4037 50 0000 C CNN +F 2 "" H 7750 3950 50 0001 C CNN +F 3 "" H 7750 3950 50 0001 C CNN + 1 7750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3800 7750 3950 +$Comp +L power:VDD #PWR03 +U 1 1 5B253303 +P 5100 3000 +F 0 "#PWR03" H 5100 2850 50 0001 C CNN +F 1 "VDD" H 5117 3173 50 0000 C CNN +F 2 "" H 5100 3000 50 0001 C CNN +F 3 "" H 5100 3000 50 0001 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B25330D +P 4900 3400 +F 0 "X2" H 5100 3128 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 3037 50 0000 C CNN +F 2 "" H 4900 3400 50 0001 C CNN +F 3 "" H 4900 3400 50 0001 C CNN +F 4 "X" H 4900 3400 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 3400 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 3400 50 0001 C CNN "Spice_Lib_File" + 1 4900 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR04 +U 1 1 5B2533AE +P 5100 4400 +F 0 "#PWR04" H 5100 4250 50 0001 C CNN +F 1 "VDD" H 5117 4573 50 0000 C CNN +F 2 "" H 5100 4400 50 0001 C CNN +F 3 "" H 5100 4400 50 0001 C CNN + 1 5100 4400 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X3 +U 1 1 5B2533B8 +P 4900 4800 +F 0 "X3" H 5100 4528 50 0000 C CNN +F 1 "CMOS_NAND" H 5100 4437 50 0000 C CNN +F 2 "" H 4900 4800 50 0001 C CNN +F 3 "" H 4900 4800 50 0001 C CNN +F 4 "X" H 4900 4800 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4900 4800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4900 4800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 4900 4800 50 0001 C CNN "Spice_Lib_File" + 1 4900 4800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR05 +U 1 1 5B25340B +P 6400 4300 +F 0 "#PWR05" H 6400 4150 50 0001 C CNN +F 1 "VDD" H 6417 4473 50 0000 C CNN +F 2 "" H 6400 4300 50 0001 C CNN +F 3 "" H 6400 4300 50 0001 C CNN + 1 6400 4300 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X4 +U 1 1 5B253415 +P 6200 4700 +F 0 "X4" H 6400 4428 50 0000 C CNN +F 1 "CMOS_NAND" H 6400 4337 50 0000 C CNN +F 2 "" H 6200 4700 50 0001 C CNN +F 3 "" H 6200 4700 50 0001 C CNN +F 4 "X" H 6200 4700 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 6200 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6200 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 6200 4700 50 0001 C CNN "Spice_Lib_File" + 1 6200 4700 + 1 0 0 -1 +$EndComp +Text GLabel 4250 4900 0 50 Input ~ 0 +E +Wire Wire Line + 4200 3300 4700 3300 +Wire Wire Line + 4700 3500 4400 3500 +Wire Wire Line + 4400 3500 4400 4900 +Wire Wire Line + 4400 4900 4700 4900 +Wire Wire Line + 6000 3400 5550 3400 +Wire Wire Line + 6000 4800 5500 4800 +Wire Wire Line + 6000 3600 5900 3600 +Wire Wire Line + 5900 3600 5900 3900 +Wire Wire Line + 5900 3900 6950 4150 +Wire Wire Line + 6950 4150 6950 4700 +Wire Wire Line + 6950 4700 6800 4700 +Wire Wire Line + 6800 3500 6950 3500 +Wire Wire Line + 6950 3500 6950 3900 +Wire Wire Line + 6950 3900 5900 4150 +Wire Wire Line + 5900 4150 5900 4600 +Wire Wire Line + 5900 4600 6000 4600 +Wire Wire Line + 4700 4700 4600 4700 +Wire Wire Line + 4600 4700 4600 4150 +Wire Wire Line + 5500 3400 5550 3400 +Connection ~ 5550 3400 +Wire Wire Line + 5550 3400 5550 3900 +Wire Wire Line + 4600 4150 5550 3900 +Connection ~ 6950 3500 +Wire Wire Line + 7750 4700 6950 4700 +Text GLabel 7450 4700 0 50 BiDi ~ 0 +nQ +$Comp +L pspice:0 #GND05 +U 1 1 5B2549A0 +P 7750 5150 +F 0 "#GND05" H 7750 5050 50 0001 C CNN +F 1 "0" H 7750 5237 50 0000 C CNN +F 2 "" H 7750 5150 50 0001 C CNN +F 3 "" H 7750 5150 50 0001 C CNN + 1 7750 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 5000 7750 5150 +Wire Notes Line + 4300 5250 7200 5250 +Wire Notes Line + 7200 5250 7200 2700 +Wire Notes Line + 7200 2700 4300 2700 +Wire Notes Line + 4300 2700 4300 5250 +Connection ~ 6950 4700 +Connection ~ 4400 4900 +Wire Wire Line + 4400 4900 4250 4900 +Text GLabel 5800 3400 0 50 UnSpc ~ 0 +1 +Text GLabel 5750 4800 0 50 UnSpc ~ 0 +2 +Wire Wire Line + 1400 2250 1400 2750 +Wire Wire Line + 1400 3350 1400 3800 +Wire Wire Line + 1400 4200 1400 4700 +Wire Wire Line + 1400 5300 1400 5750 +Wire Wire Line + 10200 3500 10200 3100 +Wire Wire Line + 10200 4100 10200 4500 +$Comp +L Device:R R2 +U 1 1 5B326075 +P 8100 3500 +F 0 "R2" V 7893 3500 50 0000 C CNN +F 1 "10meg" V 7984 3500 50 0000 C CNN +F 2 "" V 8030 3500 50 0001 C CNN +F 3 "~" H 8100 3500 50 0001 C CNN + 1 8100 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 6950 3500 7950 3500 +Wire Wire Line + 8250 3500 8250 3800 +Wire Wire Line + 8250 3800 7750 3800 +$Comp +L Device:R R1 +U 1 1 5B326C92 +P 7750 4850 +F 0 "R1" H 7680 4804 50 0000 R CNN +F 1 "10meg" H 7680 4895 50 0000 R CNN +F 2 "" V 7680 4850 50 0001 C CNN +F 3 "~" H 7750 4850 50 0001 C CNN + 1 7750 4850 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_dlatch/sym-lib-table b/digital ciruits/cmos_nand_dlatch/sym-lib-table new file mode 100644 index 0000000..63105ad --- /dev/null +++ b/digital ciruits/cmos_nand_dlatch/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sim_logic)(type Legacy)(uri ${KIPRJMOD}/../libs/sim_logic.lib)(options "")(descr "")) +) diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub-cache.lib b/digital ciruits/cmos_nand_sub/cmos_nand_sub-cache.lib new file mode 100644 index 0000000..d0e6eb2 --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.bak b/digital ciruits/cmos_nand_sub/cmos_nand_sub.bak new file mode 100644 index 0000000..3be2dcc --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.bak @@ -0,0 +1,186 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 3800 1400 3750 +Text GLabel 5300 3250 0 50 Input ~ 0 +A +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5700 2950 +F 0 "#PWR02" H 5700 2800 50 0001 C CNN +F 1 "VDD" H 5717 3123 50 0000 C CNN +F 2 "" H 5700 2950 50 0001 C CNN +F 3 "" H 5700 2950 50 0001 C CNN + 1 5700 2950 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Wire Wire Line + 1400 2250 1400 2350 +Text Notes 5350 4700 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 2-input NAND gate using PMOS/NMOS pair\n2. In ngspice it is implemented as a subcircuit\n3. Run the simulation and plot V(A), V(B) and V(out) +Text GLabel 1500 2250 2 50 Output ~ 0 +A +Text GLabel 1500 4200 2 50 Output ~ 0 +B +Text GLabel 5300 3450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 5750 1400 5700 +Wire Wire Line + 1400 4200 1400 4300 +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 5350 5250 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(out)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 5500 3350 +F 0 "X1" H 5700 3078 50 0000 C CNN +F 1 "CMOS_NAND" H 5700 2987 50 0000 C CNN +F 2 "" H 5500 3350 50 0001 C CNN +F 3 "" H 5500 3350 50 0001 C CNN +F 4 "X" H 5500 3350 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5500 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 5500 3350 50 0001 C CNN "Spice_Lib_File" + 1 5500 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3350 6100 3350 +Text GLabel 6500 3350 0 50 BiDi ~ 0 +Out +$Comp +L device:R R1 +U 1 1 5B2526A7 +P 6750 3500 +F 0 "R1" H 6820 3546 50 0000 L CNN +F 1 "10meg" H 6820 3455 50 0000 L CNN +F 2 "" V 6680 3500 50 0001 C CNN +F 3 "" H 6750 3500 50 0001 C CNN + 1 6750 3500 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 6750 3800 +F 0 "#GND03" H 6750 3700 50 0001 C CNN +F 1 "0" H 6750 3887 50 0000 C CNN +F 2 "" H 6750 3800 50 0001 C CNN +F 3 "" H 6750 3800 50 0001 C CNN + 1 6750 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3650 6750 3800 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.cir b/digital ciruits/cmos_nand_sub/cmos_nand_sub.cir new file mode 100644 index 0000000..de057ba --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.cir @@ -0,0 +1,13 @@ +.title KiCad schematic +.include "../libs/spice_models.lib" +V1 A 0 dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 VDD 0 3.3 +V3 B 0 dc 0 pulse(0 3.3 0 0 0 50m 100m) +X1 A B Out VDD NAND +R1 0 Out 10meg +.tran 1m 400m +.control +run +plot v(a)+5 v(b)+10 v(out) +.endc +.end diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.pro b/digital ciruits/cmos_nand_sub/cmos_nand_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.sch b/digital ciruits/cmos_nand_sub/cmos_nand_sub.sch new file mode 100644 index 0000000..50cb360 --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.sch @@ -0,0 +1,203 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Text GLabel 5300 3250 0 50 Input ~ 0 +A +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5700 2950 +F 0 "#PWR02" H 5700 2800 50 0001 C CNN +F 1 "VDD" H 5717 3123 50 0000 C CNN +F 2 "" H 5700 2950 50 0001 C CNN +F 3 "" H 5700 2950 50 0001 C CNN + 1 5700 2950 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Text Notes 5350 4700 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 2-input NAND gate using PMOS/NMOS pair\n2. In ngspice it is implemented as a subcircuit\n3. Run the simulation and plot V(A), V(B) and V(out) +Text GLabel 1500 2250 2 50 Output ~ 0 +A +Text GLabel 1500 4200 2 50 Output ~ 0 +B +Text GLabel 5300 3450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 5350 5250 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(out)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 5500 3350 +F 0 "X1" H 5700 3078 50 0000 C CNN +F 1 "CMOS_NAND" H 5700 2987 50 0000 C CNN +F 2 "" H 5500 3350 50 0001 C CNN +F 3 "" H 5500 3350 50 0001 C CNN +F 4 "X" H 5500 3350 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5500 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 5500 3350 50 0001 C CNN "Spice_Lib_File" + 1 5500 3350 + 1 0 0 -1 +$EndComp +Text GLabel 6300 2850 0 50 BiDi ~ 0 +Out +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 6750 3800 +F 0 "#GND03" H 6750 3700 50 0001 C CNN +F 1 "0" H 6750 3887 50 0000 C CNN +F 2 "" H 6750 3800 50 0001 C CNN +F 3 "" H 6750 3800 50 0001 C CNN + 1 6750 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3650 6750 3800 +Wire Wire Line + 1400 2250 1400 2750 +Wire Wire Line + 1400 3350 1400 3800 +Wire Wire Line + 1400 4200 1400 4700 +Wire Wire Line + 1400 5300 1400 5750 +Wire Wire Line + 10200 3500 10200 3100 +Wire Wire Line + 10200 4100 10200 4500 +$Comp +L Device:R R1 +U 1 1 5B324889 +P 7300 3400 +F 0 "R1" V 7093 3400 50 0000 C CNN +F 1 "10meg" V 7184 3400 50 0000 C CNN +F 2 "" V 7230 3400 50 0001 C CNN +F 3 "~" H 7300 3400 50 0001 C CNN + 1 7300 3400 + 0 1 1 0 +$EndComp +Wire Wire Line + 7150 3350 7150 3400 +Wire Wire Line + 6100 3350 6700 3350 +Wire Wire Line + 7450 3400 7450 3650 +Wire Wire Line + 7450 3650 6750 3650 +Wire Wire Line + 6300 2850 6700 2850 +Wire Wire Line + 6700 2850 6700 3350 +Connection ~ 6700 3350 +Wire Wire Line + 6700 3350 7150 3350 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_sub/sym-lib-table b/digital ciruits/cmos_nand_sub/sym-lib-table new file mode 100644 index 0000000..63105ad --- /dev/null +++ b/digital ciruits/cmos_nand_sub/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sim_logic)(type Legacy)(uri ${KIPRJMOD}/../libs/sim_logic.lib)(options "")(descr "")) +) diff --git a/digital ciruits/ex1_trans_amp/ex1.wbk b/digital ciruits/ex1_trans_amp/ex1.wbk new file mode 100644 index 0000000..aadfc0a --- /dev/null +++ b/digital ciruits/ex1_trans_amp/ex1.wbk @@ -0,0 +1,10 @@ +1 +9 +.tran 10u 2m +2 +1 +base +V +1 +v1 +V diff --git a/digital ciruits/ex1_trans_amp/ex1_trans_amp-cache.lib b/digital ciruits/ex1_trans_amp/ex1_trans_amp-cache.lib new file mode 100644 index 0000000..5279693 --- /dev/null +++ b/digital ciruits/ex1_trans_amp/ex1_trans_amp-cache.lib @@ -0,0 +1,84 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:C +# +DEF pspice:C C 0 10 Y Y 1 F N +F0 "C" 100 150 50 V V C CNN +F1 "pspice:C" 100 -150 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS C +DRAW +P 2 0 1 0 -150 -50 150 -50 N +P 2 0 1 0 -150 50 150 50 N +X ~ 1 0 250 200 D 40 40 1 1 P +X ~ 2 0 -250 200 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# pspice:QNPN +# +DEF pspice:QNPN Q 0 0 Y Y 1 F N +F0 "Q" -100 300 50 H V C CNN +F1 "pspice:QNPN" -100 200 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 0 0 0 0 150 -150 N +P 4 0 0 0 150 -150 150 -50 50 -150 150 -150 F +P 2 0 1 0 0 -150 0 150 N +P 2 0 1 0 0 0 150 150 N +P 4 0 1 0 -100 -150 0 -150 0 -150 0 -150 N +X C 1 150 350 200 D 40 40 1 1 P +X B 2 -300 0 300 R 40 40 1 1 I +X E 3 150 -350 200 U 40 40 1 1 P +X Substrat 4 -100 -350 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# pspice:R +# +DEF pspice:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "pspice:R" 0 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -40 150 40 -150 0 1 0 N +X ~ 1 0 250 100 D 50 50 1 1 P +X ~ 2 0 -250 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/ex1_trans_amp/ex1_trans_amp.bak b/digital ciruits/ex1_trans_amp/ex1_trans_amp.bak new file mode 100644 index 0000000..4fef936 --- /dev/null +++ b/digital ciruits/ex1_trans_amp/ex1_trans_amp.bak @@ -0,0 +1,210 @@ +EESchema Schematic File Version 4 +LIBS:ex1_trans_amp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B215C64 +P 2300 2650 +F 0 "V1" H 2728 2696 50 0000 L CNN +F 1 "12" H 2728 2605 50 0000 L CNN +F 2 "" H 2300 2650 50 0001 C CNN +F 3 "" H 2300 2650 50 0001 C CNN + 1 2300 2650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R1 +U 1 1 5B215CDC +P 3700 2650 +F 0 "R1" H 3768 2696 50 0000 L CNN +F 1 "100k" H 3768 2605 50 0000 L CNN +F 2 "" H 3700 2650 50 0001 C CNN +F 3 "" H 3700 2650 50 0001 C CNN + 1 3700 2650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R3 +U 1 1 5B215D10 +P 4800 2650 +F 0 "R3" H 4868 2696 50 0000 L CNN +F 1 "3.9k" H 4868 2605 50 0000 L CNN +F 2 "" H 4800 2650 50 0001 C CNN +F 3 "" H 4800 2650 50 0001 C CNN + 1 4800 2650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R2 +U 1 1 5B215D5B +P 4100 4600 +F 0 "R2" H 4168 4646 50 0000 L CNN +F 1 "24k" H 4168 4555 50 0000 L CNN +F 2 "" H 4100 4600 50 0001 C CNN +F 3 "" H 4100 4600 50 0001 C CNN + 1 4100 4600 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R4 +U 1 1 5B215DB1 +P 4800 4600 +F 0 "R4" H 4868 4646 50 0000 L CNN +F 1 "1k" H 4868 4555 50 0000 L CNN +F 2 "" H 4800 4600 50 0001 C CNN +F 3 "" H 4800 4600 50 0001 C CNN + 1 4800 4600 + 1 0 0 -1 +$EndComp +$Comp +L pspice:C C1 +U 1 1 5B215E29 +P 3200 3800 +F 0 "C1" V 2885 3800 50 0000 C CNN +F 1 "10u" V 2976 3800 50 0000 C CNN +F 2 "" H 3200 3800 50 0001 C CNN +F 3 "" H 3200 3800 50 0001 C CNN + 1 3200 3800 + 0 1 1 0 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B215E9D +P 2300 4650 +F 0 "V2" H 2728 4696 50 0000 L CNN +F 1 "0 ac 1.0 sin(0 1 1k)" H 2728 4605 50 0000 L CNN +F 2 "" H 2300 4650 50 0001 C CNN +F 3 "" H 2300 4650 50 0001 C CNN + 1 2300 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2950 3800 2300 3800 +Wire Wire Line + 3700 2400 3700 1950 +Wire Wire Line + 3700 1950 2300 1950 +Wire Wire Line + 3700 1950 4800 1950 +Wire Wire Line + 4800 1950 4800 2400 +Connection ~ 3700 1950 +Wire Wire Line + 3700 2900 3700 3800 +Wire Wire Line + 3700 3800 3450 3800 +Connection ~ 3700 3800 +Wire Wire Line + 4800 3450 4800 2900 +$Comp +L pspice:0 #GND01 +U 1 1 5B216243 +P 2300 3350 +F 0 "#GND01" H 2300 3250 50 0001 C CNN +F 1 "0" H 2300 3437 50 0000 C CNN +F 2 "" H 2300 3350 50 0001 C CNN +F 3 "" H 2300 3350 50 0001 C CNN + 1 2300 3350 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND02 +U 1 1 5B21627D +P 2300 5350 +F 0 "#GND02" H 2300 5250 50 0001 C CNN +F 1 "0" H 2300 5437 50 0000 C CNN +F 2 "" H 2300 5350 50 0001 C CNN +F 3 "" H 2300 5350 50 0001 C CNN + 1 2300 5350 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B2162D0 +P 4100 5300 +F 0 "#GND03" H 4100 5200 50 0001 C CNN +F 1 "0" H 4100 5387 50 0000 C CNN +F 2 "" H 4100 5300 50 0001 C CNN +F 3 "" H 4100 5300 50 0001 C CNN + 1 4100 5300 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND04 +U 1 1 5B216303 +P 4800 5300 +F 0 "#GND04" H 4800 5200 50 0001 C CNN +F 1 "0" H 4800 5387 50 0000 C CNN +F 2 "" H 4800 5300 50 0001 C CNN +F 3 "" H 4800 5300 50 0001 C CNN + 1 4800 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4100 4850 4100 5300 +Wire Wire Line + 4800 4850 4800 5300 +Text GLabel 2050 3800 0 50 BiDi ~ 0 +v1 +Wire Wire Line + 2050 3800 2300 3800 +Connection ~ 2300 3800 +Text Notes 2250 6100 0 50 ~ 0 +.tran 1e-5 2e-3 +Text Notes 2250 5800 0 50 ~ 0 +.model qnpn npn +Text Notes 1500 1600 0 50 ~ 0 +1. Start the Simulator (Tools->Simulator)\n2. Click "Run/Stop Simulation".\n3. Click "Add signals"\n4. Add V(base) and V(v1), click OK. +Text Notes 1500 1000 0 80 ~ 0 +Example based on Chapter 21.1 AC coupler transistor amplifier, from\nhttp://ngspice.sourceforge.net/docs/ngspice-manual.pdf\n +Text Notes 2250 6600 0 50 ~ 0 +.control\nrun\nplot v(base) v(v1)\n.endc +Wire Wire Line + 4800 4150 4800 4250 +Wire Wire Line + 2300 3800 2300 4350 +Wire Wire Line + 2300 4950 2300 5350 +Wire Wire Line + 2300 3350 2300 2950 +Wire Wire Line + 2300 2350 2300 1950 +Wire Wire Line + 4350 3800 4100 3800 +Wire Wire Line + 3700 3800 4100 3800 +Connection ~ 4100 3800 +Wire Wire Line + 4100 3800 4100 4350 +$Comp +L pspice:QNPN Q1 +U 1 1 5B2E41F0 +P 4650 3800 +F 0 "Q1" H 4877 3846 50 0000 L CNN +F 1 "QNPN" H 4877 3755 50 0000 L CNN +F 2 "" H 4650 3800 50 0001 C CNN +F 3 "" H 4650 3800 50 0001 C CNN + 1 4650 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 4150 4550 4250 +Wire Wire Line + 4550 4250 4800 4250 +Connection ~ 4800 4250 +Wire Wire Line + 4800 4250 4800 4350 +$EndSCHEMATC diff --git a/digital ciruits/ex1_trans_amp/ex1_trans_amp.cir b/digital ciruits/ex1_trans_amp/ex1_trans_amp.cir new file mode 100644 index 0000000..83ed548 --- /dev/null +++ b/digital ciruits/ex1_trans_amp/ex1_trans_amp.cir @@ -0,0 +1,16 @@ +.title KiCad schematic +V1 Net-_R1-Pad1_ 0 12 +R1 Net-_R1-Pad1_ Net-_C1-Pad1_ 100k +R3 Net-_R1-Pad1_ out 3.9k +R2 Net-_C1-Pad1_ 0 24k +R4 Net-_Q1-Pad3_ 0 1k +C1 Net-_C1-Pad1_ v1 10u +V2 v1 0 0 ac 1.0 sin(0 1 1k) +Q1 out Net-_C1-Pad1_ Net-_Q1-Pad3_ Net-_Q1-Pad3_ QNPN +.tran 1e-5 2e-3 +.model qnpn npn +.control +run +plot v(base) v(v1) +.endc +.end diff --git a/digital ciruits/ex1_trans_amp/ex1_trans_amp.kicad_pcb b/digital ciruits/ex1_trans_amp/ex1_trans_amp.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/ex1_trans_amp/ex1_trans_amp.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/ex1_trans_amp/ex1_trans_amp.pro b/digital ciruits/ex1_trans_amp/ex1_trans_amp.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/ex1_trans_amp/ex1_trans_amp.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/ex1_trans_amp/ex1_trans_amp.sch b/digital ciruits/ex1_trans_amp/ex1_trans_amp.sch new file mode 100644 index 0000000..3f2a5de --- /dev/null +++ b/digital ciruits/ex1_trans_amp/ex1_trans_amp.sch @@ -0,0 +1,221 @@ +EESchema Schematic File Version 4 +LIBS:ex1_trans_amp-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B215C64 +P 2300 2650 +F 0 "V1" H 2728 2696 50 0000 L CNN +F 1 "12" H 2728 2605 50 0000 L CNN +F 2 "" H 2300 2650 50 0001 C CNN +F 3 "" H 2300 2650 50 0001 C CNN + 1 2300 2650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R1 +U 1 1 5B215CDC +P 3700 2650 +F 0 "R1" H 3768 2696 50 0000 L CNN +F 1 "100k" H 3768 2605 50 0000 L CNN +F 2 "" H 3700 2650 50 0001 C CNN +F 3 "" H 3700 2650 50 0001 C CNN + 1 3700 2650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R3 +U 1 1 5B215D10 +P 4800 2650 +F 0 "R3" H 4868 2696 50 0000 L CNN +F 1 "3.9k" H 4868 2605 50 0000 L CNN +F 2 "" H 4800 2650 50 0001 C CNN +F 3 "" H 4800 2650 50 0001 C CNN + 1 4800 2650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R2 +U 1 1 5B215D5B +P 4100 4600 +F 0 "R2" H 4168 4646 50 0000 L CNN +F 1 "24k" H 4168 4555 50 0000 L CNN +F 2 "" H 4100 4600 50 0001 C CNN +F 3 "" H 4100 4600 50 0001 C CNN + 1 4100 4600 + 1 0 0 -1 +$EndComp +$Comp +L pspice:R R4 +U 1 1 5B215DB1 +P 4800 4600 +F 0 "R4" H 4868 4646 50 0000 L CNN +F 1 "1k" H 4868 4555 50 0000 L CNN +F 2 "" H 4800 4600 50 0001 C CNN +F 3 "" H 4800 4600 50 0001 C CNN + 1 4800 4600 + 1 0 0 -1 +$EndComp +$Comp +L pspice:C C1 +U 1 1 5B215E29 +P 3200 3800 +F 0 "C1" V 2885 3800 50 0000 C CNN +F 1 "10u" V 2976 3800 50 0000 C CNN +F 2 "" H 3200 3800 50 0001 C CNN +F 3 "" H 3200 3800 50 0001 C CNN + 1 3200 3800 + 0 1 1 0 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B215E9D +P 2300 4650 +F 0 "V2" H 2728 4696 50 0000 L CNN +F 1 "0 ac 1.0 sin(0 1 1k)" H 2728 4605 50 0000 L CNN +F 2 "" H 2300 4650 50 0001 C CNN +F 3 "" H 2300 4650 50 0001 C CNN + 1 2300 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2950 3800 2300 3800 +Wire Wire Line + 3700 2400 3700 1950 +Wire Wire Line + 3700 1950 2300 1950 +Wire Wire Line + 3700 1950 4800 1950 +Wire Wire Line + 4800 1950 4800 2400 +Connection ~ 3700 1950 +Wire Wire Line + 3700 2900 3700 3800 +Wire Wire Line + 3700 3800 3450 3800 +Connection ~ 3700 3800 +Wire Wire Line + 4800 3450 4800 3300 +$Comp +L pspice:0 #GND01 +U 1 1 5B216243 +P 2300 3350 +F 0 "#GND01" H 2300 3250 50 0001 C CNN +F 1 "0" H 2300 3437 50 0000 C CNN +F 2 "" H 2300 3350 50 0001 C CNN +F 3 "" H 2300 3350 50 0001 C CNN + 1 2300 3350 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND02 +U 1 1 5B21627D +P 2300 5350 +F 0 "#GND02" H 2300 5250 50 0001 C CNN +F 1 "0" H 2300 5437 50 0000 C CNN +F 2 "" H 2300 5350 50 0001 C CNN +F 3 "" H 2300 5350 50 0001 C CNN + 1 2300 5350 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B2162D0 +P 4100 5300 +F 0 "#GND03" H 4100 5200 50 0001 C CNN +F 1 "0" H 4100 5387 50 0000 C CNN +F 2 "" H 4100 5300 50 0001 C CNN +F 3 "" H 4100 5300 50 0001 C CNN + 1 4100 5300 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND04 +U 1 1 5B216303 +P 4800 5300 +F 0 "#GND04" H 4800 5200 50 0001 C CNN +F 1 "0" H 4800 5387 50 0000 C CNN +F 2 "" H 4800 5300 50 0001 C CNN +F 3 "" H 4800 5300 50 0001 C CNN + 1 4800 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4100 4850 4100 5300 +Wire Wire Line + 4800 4850 4800 5300 +Text GLabel 2050 3800 0 50 BiDi ~ 0 +v1 +Wire Wire Line + 2050 3800 2300 3800 +Connection ~ 2300 3800 +Text Notes 2250 6100 0 50 ~ 0 +.tran 1e-5 2e-3 +Text Notes 2250 5800 0 50 ~ 0 +.model qnpn npn +Text Notes 1500 1600 0 50 ~ 0 +1. Start the Simulator (Tools->Simulator)\n2. Click "Run/Stop Simulation".\n3. Click "Add signals"\n4. Add V(base) and V(v1), click OK. +Text Notes 1500 1000 0 80 ~ 0 +Example based on Chapter 21.1 AC coupler transistor amplifier, from\nhttp://ngspice.sourceforge.net/docs/ngspice-manual.pdf\n +Text Notes 2250 6600 0 50 ~ 0 +.control\nrun\nplot v(base) v(v1)\n.endc +Wire Wire Line + 4800 4150 4800 4250 +Wire Wire Line + 2300 3800 2300 4350 +Wire Wire Line + 2300 4950 2300 5350 +Wire Wire Line + 2300 3350 2300 2950 +Wire Wire Line + 2300 2350 2300 1950 +Wire Wire Line + 4350 3800 4100 3800 +Wire Wire Line + 3700 3800 4100 3800 +Connection ~ 4100 3800 +Wire Wire Line + 4100 3800 4100 4350 +$Comp +L pspice:QNPN Q1 +U 1 1 5B2E41F0 +P 4650 3800 +F 0 "Q1" H 4877 3846 50 0000 L CNN +F 1 "QNPN" H 4877 3755 50 0000 L CNN +F 2 "" H 4650 3800 50 0001 C CNN +F 3 "" H 4650 3800 50 0001 C CNN + 1 4650 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 4150 4550 4250 +Wire Wire Line + 4550 4250 4800 4250 +Connection ~ 4800 4250 +Wire Wire Line + 4800 4250 4800 4350 +Text GLabel 5600 3100 0 50 Output ~ 0 +out +Wire Wire Line + 5600 3100 5950 3100 +Wire Wire Line + 5950 3100 5950 3300 +Wire Wire Line + 5950 3300 4800 3300 +Connection ~ 4800 3300 +Wire Wire Line + 4800 3300 4800 2900 +$EndSCHEMATC diff --git a/digital ciruits/inverter_mosfet/inverter_mosfet-cache.lib b/digital ciruits/inverter_mosfet/inverter_mosfet-cache.lib new file mode 100644 index 0000000..6dd4c50 --- /dev/null +++ b/digital ciruits/inverter_mosfet/inverter_mosfet-cache.lib @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:MNMOS +# +DEF pspice:MNMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "pspice:MNMOS" 300 -50 50 H V L CNN +F2 "" -25 0 50 H I C CNN +F3 "" -25 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 -100 -50 100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 -25 0 50 25 50 -25 -25 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 -200 100 U 50 50 1 1 P +X B 4 200 -200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pspice:MPMOS +# +DEF pspice:MPMOS M 0 0 Y Y 1 F N +F0 "M" 300 50 50 H V L CNN +F1 "pspice:MPMOS" 300 -50 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -50 100 -50 -100 N +P 2 0 1 0 -25 -100 100 -100 N +P 2 0 1 0 100 100 -25 100 N +P 2 0 1 0 200 0 -25 0 N +P 4 0 1 0 200 0 125 25 125 -25 200 0 F +P 2 1 1 0 -25 -100 -25 100 N +X D 1 100 -200 100 U 50 50 1 1 P +X G 2 -200 0 150 R 50 50 1 1 I +X S 3 100 200 100 D 50 50 1 1 P +X B 4 200 200 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/inverter_mosfet/inverter_mosfet.bak b/digital ciruits/inverter_mosfet/inverter_mosfet.bak new file mode 100644 index 0000000..e736808 --- /dev/null +++ b/digital ciruits/inverter_mosfet/inverter_mosfet.bak @@ -0,0 +1,171 @@ +EESchema Schematic File Version 4 +LIBS:inverter_mosfet-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 4750 4750 +F 0 "#GND01" H 4750 4650 50 0001 C CNN +F 1 "0" H 4750 4837 50 0000 C CNN +F 2 "" H 4750 4750 50 0001 C CNN +F 3 "" H 4750 4750 50 0001 C CNN + 1 4750 4750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 4100 3800 +F 0 "V1" H 4528 3846 50 0000 L CNN +F 1 "pulse(0 3.3 0 0 0 100m 200m)" H 4528 3755 50 0000 L CNN +F 2 "" H 4100 3800 50 0001 C CNN +F 3 "" H 4100 3800 50 0001 C CNN +F 4 "V" H 4100 3800 50 0001 C CNN "Spice_Primitive" +F 5 "pulse(0 3.3 0 0 0 100m 200m)" H 4100 3800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4100 3800 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4100 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 4750 4750 4500 +Wire Wire Line + 4100 4500 4750 4500 +Connection ~ 4750 4500 +Text GLabel 4750 2700 0 50 Input ~ 0 +vin +Text GLabel 7200 2700 2 50 Output ~ 0 +vout +Wire Wire Line + 6100 2900 6100 2700 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 2750 3800 +F 0 "V2" H 3178 3846 50 0000 L CNN +F 1 "3.3" H 3178 3755 50 0000 L CNN +F 2 "" H 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+F 0 "#PWR0106" H 8650 3300 50 0001 C CNN
+F 1 "VDD" H 8667 3623 50 0000 C CNN
+F 2 "" H 8650 3450 50 0001 C CNN
+F 3 "" H 8650 3450 50 0001 C CNN
+ 1 8650 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #PWR0107
+U 1 1 5B317D91
+P 8650 4250
+F 0 "#PWR0107" H 8650 4000 50 0001 C CNN
+F 1 "GND" H 8655 4077 50 0000 C CNN
+F 2 "" H 8650 4250 50 0001 C CNN
+F 3 "" H 8650 4250 50 0001 C CNN
+ 1 8650 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8650 4250 8650 4050
+Text GLabel 4100 2000 0 50 Output ~ 0
+q0
+Text GLabel 5500 2000 0 50 Output ~ 0
+q1
+Text GLabel 6900 2000 0 50 Output ~ 0
+q2
+Text GLabel 8050 2000 0 50 Output ~ 0
+q3
+Wire Wire Line
+ 8150 2350 8050 2350
+Wire Wire Line
+ 6900 2000 6900 2350
+Connection ~ 6900 2350
+Wire Wire Line
+ 6900 2350 7200 2350
+Wire Wire Line
+ 5500 2000 5500 2350
+Connection ~ 5500 2350
+Wire Wire Line
+ 5500 2350 5800 2350
+Wire Wire Line
+ 4100 2000 4100 2350
+Connection ~ 4100 2350
+Wire Wire Line
+ 4100 2350 4450 2350
+$Comp
+L power:GND #PWR0108
+U 1 1 5B318EAA
+P 8650 2350
+F 0 "#PWR0108" H 8650 2100 50 0001 C CNN
+F 1 "GND" H 8655 2177 50 0000 C CNN
+F 2 "" H 8650 2350 50 0001 C CNN
+F 3 "" H 8650 2350 50 0001 C CNN
+ 1 8650 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B318EFC
+P 8300 2350
+F 0 "R1" V 8093 2350 50 0000 C CNN
+F 1 "10meg" V 8184 2350 50 0000 C CNN
+F 2 "" V 8230 2350 50 0001 C CNN
+F 3 "~" H 8300 2350 50 0001 C CNN
+ 1 8300 2350
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 8450 2350 8650 2350
+Wire Wire Line
+ 8050 2000 8050 2350
+Connection ~ 8050 2350
+Wire Wire Line
+ 8050 2350 8000 2350
+Text GLabel 2150 3150 0 50 Output ~ 0
+clk
+Wire Wire Line
+ 2150 3150 2650 3150
+Connection ~ 2650 3150
+Wire Wire Line
+ 2650 3150 2650 2550
+$EndSCHEMATC
diff --git a/digital ciruits/johnson_counter/johnson_counter.cir b/digital ciruits/johnson_counter/johnson_counter.cir new file mode 100644 index 0000000..1670e64 --- /dev/null +++ b/digital ciruits/johnson_counter/johnson_counter.cir @@ -0,0 +1,11 @@ +.title KiCad schematic +.include "/home/akshay/Music/kicad-simulation-examples-master/libs/spice_models.lib" +X1 Net-_X1-Pad1_ clk q0 NC_01 VDD DFLIPFLOP +V2 VDD GND dc 5 +R1 GND q3 10meg +X2 q0 clk q1 NC_02 VDD DFLIPFLOP +X3 q1 clk q2 NC_03 VDD DFLIPFLOP +X4 q2 clk q3 Net-_X1-Pad1_ VDD DFLIPFLOP +V1 clk GND dc 0 pwl(0 0 5m 0 5.005m 5 10m 5 10.005m 0 15m 0 15.005m 5 20m 5) +.tran .25m 20m +.end diff --git a/digital ciruits/johnson_counter/johnson_counter.kicad_pcb b/digital ciruits/johnson_counter/johnson_counter.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/johnson_counter/johnson_counter.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/johnson_counter/johnson_counter.pro b/digital ciruits/johnson_counter/johnson_counter.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/johnson_counter/johnson_counter.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/johnson_counter/johnson_counter.sch b/digital ciruits/johnson_counter/johnson_counter.sch new file mode 100644 index 0000000..a3351d8 --- /dev/null +++ b/digital ciruits/johnson_counter/johnson_counter.sch @@ -0,0 +1,294 @@ +EESchema Schematic File Version 4 +LIBS:johnson_counter-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L johnson_counter-rescue:D_FLIPFLOP-sim_logic X1 +U 1 1 5B3146B6 +P 3250 2450 +F 0 "X1" H 3450 2178 50 0000 C CNN +F 1 "D_FLIPFLOP" H 3450 2087 50 0000 C CNN +F 2 "" H 3250 2450 50 0001 C CNN +F 3 "" H 3250 2450 50 0001 C CNN +F 4 "X" H 3250 2450 50 0001 C CNN "Spice_Primitive" +F 5 "DFLIPFLOP" H 3250 2450 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3250 2450 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Music/kicad-simulation-examples-master/libs/spice_models.lib" H 3250 2450 50 0001 C CNN "Spice_Lib_File" + 1 3250 2450 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 5B314A9F +P 2650 4350 +F 0 "#PWR0101" H 2650 4100 50 0001 C CNN +F 1 "GND" H 2655 4177 50 0000 C CNN +F 2 "" H 2650 4350 50 0001 C CNN +F 3 "" H 2650 4350 50 0001 C CNN + 1 2650 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 4350 2650 4200 +Wire Wire Line + 8500 800 2850 800 +Wire Wire Line + 2850 800 2850 2350 +Wire Wire Line + 2850 2350 3050 2350 +Wire Wire Line + 2650 3600 2650 3150 +Wire Wire Line + 2650 2550 2950 2550 +Wire Wire Line + 2950 2550 2950 3050 +Connection ~ 2950 2550 +Wire Wire Line + 2950 2550 3050 2550 +Wire Wire Line + 3850 2350 4100 2350 +Wire Wire Line + 2950 3050 4300 3050 +Wire Wire Line + 5250 2350 5500 2350 +Wire Wire Line + 6600 2350 6900 2350 +Wire Wire Line + 7050 3050 7050 2550 +Wire Wire Line + 7050 2550 7200 2550 +Wire Wire Line + 4450 2550 4300 2550 +Wire Wire Line + 4300 2550 4300 3050 +Connection ~ 4300 3050 +Wire Wire Line + 4300 3050 5650 3050 +Wire Wire Line + 5800 2550 5650 2550 +Wire Wire Line + 5650 2550 5650 3050 +Connection ~ 5650 3050 +Wire Wire Line + 5650 3050 7050 3050 +$Comp +L power:VDD #PWR0102 +U 1 1 5B317A5C +P 4850 2050 +F 0 "#PWR0102" H 4850 1900 50 0001 C CNN +F 1 "VDD" H 4867 2223 50 0000 C CNN +F 2 "" H 4850 2050 50 0001 C CNN +F 3 "" H 4850 2050 50 0001 C CNN + 1 4850 2050 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0103 +U 1 1 5B317A78 +P 3450 2050 +F 0 "#PWR0103" H 3450 1900 50 0001 C CNN +F 1 "VDD" H 3467 2223 50 0000 C CNN +F 2 "" H 3450 2050 50 0001 C CNN +F 3 "" H 3450 2050 50 0001 C CNN + 1 3450 2050 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0104 +U 1 1 5B317A8D +P 6200 2050 +F 0 "#PWR0104" H 6200 1900 50 0001 C CNN +F 1 "VDD" H 6217 2223 50 0000 C CNN +F 2 "" H 6200 2050 50 0001 C CNN +F 3 "" H 6200 2050 50 0001 C CNN + 1 6200 2050 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0105 +U 1 1 5B317AC0 +P 7600 2050 +F 0 "#PWR0105" H 7600 1900 50 0001 C CNN +F 1 "VDD" H 7617 2223 50 0000 C CNN +F 2 "" H 7600 2050 50 0001 C CNN +F 3 "" H 7600 2050 50 0001 C CNN + 1 7600 2050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8000 2550 8500 2550 +Wire Wire Line + 8500 800 8500 2550 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B317D00 +P 8650 3750 +F 0 "V2" H 8878 3796 50 0000 L CNN +F 1 "VSOURCE" H 8878 3705 50 0000 L CNN +F 2 "" H 8650 3750 50 0001 C CNN +F 3 "" H 8650 3750 50 0001 C CNN +F 4 "V" H 8650 3750 50 0001 C CNN "Spice_Primitive" +F 5 "dc 5" H 8650 3750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8650 3750 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8650 3750 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0106 +U 1 1 5B317D44 +P 8650 3450 +F 0 "#PWR0106" H 8650 3300 50 0001 C CNN +F 1 "VDD" H 8667 3623 50 0000 C CNN +F 2 "" H 8650 3450 50 0001 C CNN +F 3 "" H 8650 3450 50 0001 C CNN + 1 8650 3450 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0107 +U 1 1 5B317D91 +P 8650 4250 +F 0 "#PWR0107" H 8650 4000 50 0001 C CNN +F 1 "GND" H 8655 4077 50 0000 C CNN +F 2 "" H 8650 4250 50 0001 C CNN +F 3 "" H 8650 4250 50 0001 C CNN + 1 8650 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8650 4250 8650 4050 +Text GLabel 4100 2000 0 50 Output ~ 0 +q0 +Text GLabel 5500 2000 0 50 Output ~ 0 +q1 +Text GLabel 6900 2000 0 50 Output ~ 0 +q2 +Text GLabel 8050 2000 0 50 Output ~ 0 +q3 +Wire Wire Line + 8150 2350 8050 2350 +Wire Wire Line + 6900 2000 6900 2350 +Connection ~ 6900 2350 +Wire Wire Line + 6900 2350 7200 2350 +Wire Wire Line + 5500 2000 5500 2350 +Connection ~ 5500 2350 +Wire Wire Line + 5500 2350 5800 2350 +Wire Wire Line + 4100 2000 4100 2350 +Connection ~ 4100 2350 +Wire Wire Line + 4100 2350 4450 2350 +$Comp +L power:GND #PWR0108 +U 1 1 5B318EAA +P 8650 2350 +F 0 "#PWR0108" H 8650 2100 50 0001 C CNN +F 1 "GND" H 8655 2177 50 0000 C CNN +F 2 "" H 8650 2350 50 0001 C CNN +F 3 "" H 8650 2350 50 0001 C CNN + 1 8650 2350 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B318EFC +P 8300 2350 +F 0 "R1" V 8093 2350 50 0000 C CNN +F 1 "10meg" V 8184 2350 50 0000 C CNN +F 2 "" V 8230 2350 50 0001 C CNN +F 3 "~" H 8300 2350 50 0001 C CNN + 1 8300 2350 + 0 1 1 0 +$EndComp +Wire Wire Line + 8450 2350 8650 2350 +Wire Wire Line + 8050 2000 8050 2350 +Connection ~ 8050 2350 +Wire Wire Line + 8050 2350 8000 2350 +Text GLabel 2150 3150 0 50 Output ~ 0 +clk +Wire Wire Line + 2150 3150 2650 3150 +Connection ~ 2650 3150 +Wire Wire Line + 2650 3150 2650 2550 +$Comp +L johnson_counter-rescue:D_FLIPFLOP-sim_logic X2 +U 1 1 5B321572 +P 4650 2450 +F 0 "X2" H 4850 2178 50 0000 C CNN +F 1 "D_FLIPFLOP" H 4850 2087 50 0000 C CNN +F 2 "" H 4650 2450 50 0001 C CNN +F 3 "" H 4650 2450 50 0001 C CNN +F 4 "X" H 4650 2450 50 0001 C CNN "Spice_Primitive" +F 5 "DFLIPFLOP" H 4650 2450 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4650 2450 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Music/kicad-simulation-examples-master/libs/spice_models.lib" H 4650 2450 50 0001 C CNN "Spice_Lib_File" + 1 4650 2450 + 1 0 0 -1 +$EndComp +$Comp +L johnson_counter-rescue:D_FLIPFLOP-sim_logic X3 +U 1 1 5B3215CA +P 6000 2450 +F 0 "X3" H 6200 2178 50 0000 C CNN +F 1 "D_FLIPFLOP" H 6200 2087 50 0000 C CNN +F 2 "" H 6000 2450 50 0001 C CNN +F 3 "" H 6000 2450 50 0001 C CNN +F 4 "X" H 6000 2450 50 0001 C CNN "Spice_Primitive" +F 5 "DFLIPFLOP" H 6000 2450 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6000 2450 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Music/kicad-simulation-examples-master/libs/spice_models.lib" H 6000 2450 50 0001 C CNN "Spice_Lib_File" + 1 6000 2450 + 1 0 0 -1 +$EndComp +$Comp +L johnson_counter-rescue:D_FLIPFLOP-sim_logic X4 +U 1 1 5B321632 +P 7400 2450 +F 0 "X4" H 7600 2178 50 0000 C CNN +F 1 "D_FLIPFLOP" H 7600 2087 50 0000 C CNN +F 2 "" H 7400 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN +F 4 "X" H 7400 2450 50 0001 C CNN "Spice_Primitive" +F 5 "DFLIPFLOP" H 7400 2450 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7400 2450 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Music/kicad-simulation-examples-master/libs/spice_models.lib" H 7400 2450 50 0001 C CNN "Spice_Lib_File" + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B32175C +P 2650 3900 +F 0 "V1" H 2878 3946 50 0000 L CNN +F 1 "VSOURCE" H 2878 3855 50 0000 L CNN +F 2 "" H 2650 3900 50 0001 C CNN +F 3 "" H 2650 3900 50 0001 C CNN +F 4 "V" H 2650 3900 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pwl(0 0 5m 0 5.005m 5 10m 5 10.005m 0 15m 0 15.005m 5 20m 5)" H 2650 3900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2650 3900 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2650 3900 + 1 0 0 -1 +$EndComp +Text Notes 5200 4150 0 50 ~ 0 +.tran .25m 20m +$EndSCHEMATC diff --git a/digital ciruits/johnson_counter/sym-lib-table b/digital ciruits/johnson_counter/sym-lib-table new file mode 100644 index 0000000..eb15306 --- /dev/null +++ b/digital ciruits/johnson_counter/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (lib (name sim_logic)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/new_file/libs/sim_logic.lib)(options "")(descr "")) + (lib (name johnson_counter-rescue)(type Legacy)(uri ${KIPRJMOD}/johnson_counter-rescue.lib)(options "")(descr "")) +) diff --git a/digital ciruits/libs/sim_logic.dcm b/digital ciruits/libs/sim_logic.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/libs/sim_logic.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/libs/sim_logic.lib b/digital ciruits/libs/sim_logic.lib new file mode 100644 index 0000000..5221cde --- /dev/null +++ b/digital ciruits/libs/sim_logic.lib @@ -0,0 +1,166 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# CMOS_NAND3 +# +DEF CMOS_NAND3 X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "CMOS_NAND3" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 0 200 R 50 50 1 1 I +X C C -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# CMOS_NOT +# +DEF CMOS_NOT X 0 20 Y N 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "CMOS_NOT" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 400 0 0 200 0 -200 400 0 N +X A A -200 0 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 300 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# D_FLIPFLOP +# +DEF D_FLIPFLOP X 0 40 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "D_FLIPFLOP" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S 0 200 400 -200 0 1 0 N +X D 1 -200 100 200 R 50 50 1 1 I +X CLK 2 -200 -100 200 R 50 50 1 1 I C +X Q 3 600 100 200 L 50 50 1 1 O +X nQ 4 600 -100 200 L 50 50 1 1 O I +X VDD 5 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# D_LATCH +# +DEF D_LATCH X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "D_LATCH" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S 0 200 400 -200 0 1 0 N +X D 1 -200 100 200 R 50 50 1 1 I +X E 2 -200 -100 200 R 50 50 1 1 I +X Q 3 600 100 200 L 50 50 1 1 O +X nQ 4 600 -100 200 L 50 50 1 1 O I +X VDD 5 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# +# NOR +# +DEF NOR X 0 40 Y Y 1 F N +F0 "X" -100 -50 39 H V C CNN +F1 "NOR" -100 -100 39 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -250 -250 50 -250 0 1 0 N +S -250 100 -250 -250 0 1 0 N +S 50 100 -250 100 0 1 0 N +S 50 100 50 -250 0 1 0 N +X A 1 -450 0 200 R 50 28 1 1 I +X B 2 -450 -150 200 R 50 28 1 1 I +X Out 3 250 -150 200 L 50 31 1 1 O +X VDD 4 250 0 200 L 50 28 1 1 I +ENDDRAW +ENDDEF +# +# +# basic_gates:jkff +# +DEF basic_gates:jkff X 0 40 Y Y 1 F N +F0 "X" 0 -350 50 H V C CNN +F1 "basic_gates:jkff" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -350 250 350 -300 0 1 0 N +X J 1 -450 200 100 R 50 50 1 1 I +X clk 2 -450 0 100 R 50 50 1 1 I +X k 3 -450 -200 100 R 50 50 1 1 I +X vdd 4 0 350 100 D 50 50 1 1 O +X q 5 450 150 100 L 50 50 1 1 O +X nq 6 450 -200 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# XNOR +# +DEF XNOR X 0 40 Y Y 1 F N +F0 "X" -100 300 39 H V C CNN +F1 "XNOR" -100 250 39 H V C CNN +F2 "" -150 350 50 H I C CNN +F3 "" -150 350 50 H I C CNN +DRAW +S -250 100 50 100 0 1 0 N +S -250 450 -250 100 0 1 0 N +S 50 100 50 450 0 1 0 N +S 50 450 -250 450 0 1 0 N +X A 1 -450 350 200 R 50 28 1 1 I +X B 2 -450 200 200 R 50 28 1 1 I +X Out 3 250 200 200 L 50 28 1 1 O +X VDD 4 250 350 200 L 50 28 1 1 I +ENDDRAW +ENDDEF +# +# +# XOR +# +DEF XOR X 0 40 Y Y 1 F N +F0 "X" 0 50 39 H V C CNN +F1 "XOR" 0 0 39 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -150 -150 150 -150 0 1 0 N +S -150 200 -150 -150 0 1 0 N +S 150 200 -150 200 0 1 0 N +S 150 200 150 -150 0 1 0 N +X A 1 -350 100 200 R 50 28 1 1 I +X B 2 -350 -100 200 R 50 28 1 1 I +X Out 3 350 -50 200 L 50 28 1 1 O +X VDD 4 350 100 200 L 50 28 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/libs/spice_models.lib b/digital ciruits/libs/spice_models.lib new file mode 100644 index 0000000..fd1d721 --- /dev/null +++ b/digital ciruits/libs/spice_models.lib @@ -0,0 +1,131 @@ +* ---------------------------------------------------------------------------- +* Models for KiCad-ngspice +* ---------------------------------------------------------------------------- + +* ---------------------------------------------------------------------------- +* Generic models (public domain) +* ---------------------------------------------------------------------------- + +* These are generics for pspice.lib transistors +.model qnpn npn +.model qpnp pnp + +* These are generics for pspice.lib mosfets +.model mnmos nmos level=8 version=3.3.0 +.model mpmos pmos level=8 version=3.3.0 + +* General transistors +.model npn npn +.model pnp pnp + +* ---------------------------------------------------------------------------- +* Subcircuits (logic gates) +* ---------------------------------------------------------------------------- + +.SUBCKT NOT A Out VDD +* Nodes: +MM1 Out A VDD VDD MPMOS +MM2 Out A 0 0 MNMOS +.ENDS NOT + +.SUBCKT NAND A B Out VDD +* Nodes: +MM1 Out A VDD VDD MPMOS +MM2 Out A 1 1 MNMOS +MM4 Out B VDD VDD MPMOS +MM3 1 B 0 0 MNMOS +.ENDS NAND + +.SUBCKT NAND3 A B C Out VDD +MM1 Out A VDD VDD MPMOS +MM2 Out A 1 1 MNMOS +MM4 Out B VDD VDD MPMOS +MM3 1 B 2 2 MNMOS +MM6 Out C VDD VDD MPMOS +MM5 2 C 0 0 MNMOS +.ENDS NAND3 + +.SUBCKT DLATCH D E Q nQ VDD +* Nodes: +XX1 1 nQ Q VDD NAND +XX2 D E 1 VDD NAND +XX3 1 E 2 VDD NAND +XX4 Q 2 nQ VDD NAND +.ENDS DLATCH + +.SUBCKT DFLIPFLOP D CLK Q nQ VDD +XX1 1 nQ Q VDD NAND +XX2 4 CLK 1 VDD NAND +XX3 1 CLK 3 2 VDD NAND3 +XX4 Q 2 nQ VDD NAND +XX5 3 1 4 VDD NAND +XX6 2 D 3 VDD NAND +.ENDS DFLIPFLOP +.SUBCKT AND 1 2 3 4 +X1 1 2 Net-_X1-PadOut_ 4 NAND +X2 Net-_X1-PadOut_ Net-_X1-PadOut_ 3 4 NAND +R1 GND 3 10meg +.ENDS AND +.SUBCKT OR 1 2 3 4 +X2 2 2 Net-_X2-PadOut_ 4 NAND +X1 1 1 Net-_X1-PadOut_ 4 NAND +X3 Net-_X1-PadOut_ Net-_X2-PadOut_ 3 4 NAND +.ENDS OR +.SUBCKT JKFLIPFLOP 1 2 3 4 5 6 +X3 Net-_X1-PadOut_ Net-_X3-PadB_ q12 4 NAND +X1 6 1 2 Net-_X1-PadOut_ 4 NAND3 +X2 2 3 5 Net-_X2-PadOut_ 4 NAND3 +X4 q12 Net-_X2-PadOut_ Net-_X3-PadB_ 4 NAND +X6 q12 Net-_X5-PadOut_ Net-_X6-PadOut_ 4 NAND +X7 Net-_X5-PadOut_ Net-_X3-PadB_ Net-_X7-PadOut_ 4 NAND +X9 Net-_X6-PadOut_ 6 5 4 NAND +X8 5 Net-_X7-PadOut_ 6 4 NAND +X5 2 Net-_X5-PadOut_ 4 NOT +.ENDS JKFLIPFLOP +.SUBCKT XOR 1 2 3 4 +X1 1 2 Net-_X1-PadOut_ 4 NAND +X3 Net-_X1-PadOut_ 2 Net-_X3-PadOut_ 4 NAND +X2 1 Net-_X1-PadOut_ Net-_X2-PadOut_ 4 NAND +X4 Net-_X2-PadOut_ Net-_X3-PadOut_ 3 4 NAND +.ENDS XOR + +.SUBCKT XNOR 1 2 3 4 +X1 1 2 Net-_X1-PadOut_ 4 NAND +X3 Net-_X1-PadOut_ 2 Net-_X3-PadOut_ 4 NAND +X2 1 Net-_X1-PadOut_ Net-_X2-PadOut_ 4 NAND +X4 Net-_X2-PadOut_ Net-_X3-PadOut_ Net-_X4-PadOut_ 4 NAND +X5 Net-_X4-PadOut_ Net-_X4-PadOut_ 3 4 NAND +.ENDS XNOR +.SUBCKT NOR 1 2 3 4 +X1 1 1 Net-_X1-PadOut_ 4 NAND +X2 2 2 Net-_X2-PadOut_ 4 NAND +X3 Net-_X1-PadOut_ Net-_X2-PadOut_ Net-_X3-PadOut_ 4 NAND +X4 Net-_X3-PadOut_ Net-_X3-PadOut_ 3 4 NAND +.ENDS NOR + + + +* ---------------------------------------------------------------------------- +* Manufacturer supplier models (used under license) +* ---------------------------------------------------------------------------- + +*ZETEX BC108 Spice model Last Revision 23/3/00 +* +* (C) 1991 ZETEX PLC +* +* The copyright in this model and the design embodied belong to +* Zetex PLC ("Zetex"). It is supplied free of charge by Zetex for +* the purpose of research and design and may be used or copied +* intact (including this notice) for that purpose only. All other +* rights are reserved. The model is believed accurate but no +* condition or warranty as to its merchantability or fitness for +* purpose is given and no liability in respect of any use is +* accepted by Zetex PLC, its distributors or agent. +* +* Zetex PLC, Fields New Road, Chadderton, Oldham OL9 8NP +* +.MODEL BC108 NPN IS =1.8E-14 ISE=5.0E-14 NF =.9955 NE =1.46 BF =400 ++ BR =35.5 IKF=.14 IKR=.03 ISC=1.72E-13 NC =1.27 NR =1.005 ++ RB =.56 RE =.6 RC =.25 VAF=80 VAR=12.5 ++ CJE=13E-12 CJC=4E-12 VJC=.54 MJC=.33 ++ TF =.64E-9 TR =50.72E-9 diff --git a/digital ciruits/masterslave_jkff/_saved_masterslave_jkff.cir b/digital ciruits/masterslave_jkff/_saved_masterslave_jkff.cir new file mode 100644 index 0000000..b834d50 --- /dev/null +++ b/digital ciruits/masterslave_jkff/_saved_masterslave_jkff.cir @@ -0,0 +1,20 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" +X3 Net-_X1-PadOut_ Net-_X3-PadB_ q12 4 NAND +X1 6 1 Net-_X1-PadC_ Net-_X1-PadOut_ 4 NAND3 +X2 Net-_X1-PadC_ 3 5 Net-_X2-PadOut_ 4 NAND3 +X4 q12 Net-_X2-PadOut_ Net-_X3-PadB_ 4 NAND +X6 q12 Net-_X5-PadOut_ Net-_X6-PadOut_ 4 NAND +X7 Net-_X5-PadOut_ Net-_X3-PadB_ Net-_X7-PadOut_ 4 NAND +X9 Net-_X6-PadOut_ 6 5 4 NAND +X8 5 Net-_X7-PadOut_ 6 4 NAND +X5 Net-_X1-PadC_ Net-_X5-PadOut_ 4 NOT +R1 GND 5 10meg +R2 GND 6 10meg +V2 1 GND dc 3.3 +V1 3 GND dc 3.3 +V3 2 GND dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3) +V4 4 GND dc 3.3 +X10 2 Net-_X1-PadC_ 4 NOT +.tran .25m 50m +.end diff --git a/digital ciruits/masterslave_jkff/_saved_masterslave_jkff.pro b/digital ciruits/masterslave_jkff/_saved_masterslave_jkff.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/masterslave_jkff/_saved_masterslave_jkff.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff-cache.lib b/digital ciruits/masterslave_jkff/masterslave_jkff-cache.lib new file mode 100644 index 0000000..cc591bc --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff-cache.lib @@ -0,0 +1,101 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND3 +# +DEF sim_logic:CMOS_NAND3 X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND3" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 0 200 R 50 50 1 1 I +X C C -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NOT +# +DEF sim_logic:CMOS_NOT X 0 20 Y N 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NOT" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 400 0 0 200 0 -200 400 0 N +X A A -200 0 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 300 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff.bak b/digital ciruits/masterslave_jkff/masterslave_jkff.bak new file mode 100644 index 0000000..f462218 --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff.bak @@ -0,0 +1,564 @@ +EESchema Schematic File Version 4 +LIBS:masterslave_jkff-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L sim_logic:CMOS_NAND X3 +U 1 1 5B29F141 +P 5450 3250 +F 0 "X3" H 5650 2978 50 0000 C CNN +F 1 "CMOS_NAND" H 5650 2887 50 0000 C CNN +F 2 "" H 5450 3250 50 0001 C CNN +F 3 "" H 5450 3250 50 0001 C CNN +F 4 "X" H 5450 3250 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5450 3250 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5450 3250 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5450 3250 50 0001 C CNN "Spice_Lib_File" + 1 5450 3250 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X1 +U 1 1 5B29F238 +P 3600 3300 +F 0 "X1" H 3800 3028 50 0000 C CNN +F 1 "CMOS_NAND3" H 3800 2937 50 0000 C CNN +F 2 "" H 3600 3300 50 0001 C CNN +F 3 "" H 3600 3300 50 0001 C CNN +F 4 "X" H 3600 3300 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 3600 3300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3600 3300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 3600 3300 50 0001 C CNN "Spice_Lib_File" + 1 3600 3300 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X2 +U 1 1 5B29F2F2 +P 3650 4550 +F 0 "X2" H 3850 4278 50 0000 C CNN +F 1 "CMOS_NAND3" H 3850 4187 50 0000 C CNN +F 2 "" H 3650 4550 50 0001 C CNN +F 3 "" H 3650 4550 50 0001 C CNN +F 4 "X" H 3650 4550 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 3650 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3650 4550 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 3650 4550 50 0001 C CNN "Spice_Lib_File" + 1 3650 4550 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X4 +U 1 1 5B29F3E9 +P 5500 4500 +F 0 "X4" H 5700 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 5700 4137 50 0000 C CNN +F 2 "" H 5500 4500 50 0001 C CNN +F 3 "" H 5500 4500 50 0001 C CNN +F 4 "X" H 5500 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5500 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5500 4500 50 0001 C CNN "Spice_Lib_File" + 1 5500 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X6 +U 1 1 5B29F421 +P 7050 3200 +F 0 "X6" H 7250 2928 50 0000 C CNN +F 1 "CMOS_NAND" H 7250 2837 50 0000 C CNN +F 2 "" H 7050 3200 50 0001 C CNN +F 3 "" H 7050 3200 50 0001 C CNN +F 4 "X" H 7050 3200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 7050 3200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7050 3200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 7050 3200 50 0001 C CNN "Spice_Lib_File" + 1 7050 3200 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X7 +U 1 1 5B29F51D +P 7150 4500 +F 0 "X7" H 7350 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 7350 4137 50 0000 C CNN +F 2 "" H 7150 4500 50 0001 C CNN +F 3 "" H 7150 4500 50 0001 C CNN +F 4 "X" H 7150 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 7150 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7150 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 7150 4500 50 0001 C CNN "Spice_Lib_File" + 1 7150 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X9 +U 1 1 5B29F56B +P 8650 3200 +F 0 "X9" H 8850 2928 50 0000 C CNN +F 1 "CMOS_NAND" H 8850 2837 50 0000 C CNN +F 2 "" H 8650 3200 50 0001 C CNN +F 3 "" H 8650 3200 50 0001 C CNN +F 4 "X" H 8650 3200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 8650 3200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8650 3200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 8650 3200 50 0001 C CNN "Spice_Lib_File" + 1 8650 3200 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X8 +U 1 1 5B29F5E4 +P 8600 4500 +F 0 "X8" H 8800 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 8800 4137 50 0000 C CNN +F 2 "" H 8600 4500 50 0001 C CNN +F 3 "" H 8600 4500 50 0001 C CNN +F 4 "X" H 8600 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 8600 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8600 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 8600 4500 50 0001 C CNN "Spice_Lib_File" + 1 8600 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NOT X5 +U 1 1 5B29F6B5 +P 5550 5800 +F 0 "X5" H 5750 5528 50 0000 C CNN +F 1 "CMOS_NOT" H 5750 5437 50 0000 C CNN +F 2 "" H 5550 5800 50 0001 C CNN +F 3 "" H 5550 5800 50 0001 C CNN +F 4 "X" H 5550 5800 50 0001 C CNN "Spice_Primitive" +F 5 "NOT" H 5550 5800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 5800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5550 5800 50 0001 C CNN "Spice_Lib_File" + 1 5550 5800 + 1 0 0 -1 +$EndComp +Text GLabel 1250 4000 0 50 Input ~ 0 +2 +Text GLabel 2100 3450 0 50 Input ~ 0 +1 +Text GLabel 2050 4450 0 50 Input ~ 0 +3 +Wire Wire Line + 2100 4000 2500 4000 +Wire Wire Line + 3000 4000 3000 3400 +Wire Wire Line + 3000 3400 3400 3400 +Wire Wire Line + 3000 4000 3000 4450 +Wire Wire Line + 3000 4450 3450 4450 +Connection ~ 3000 4000 +Wire Wire Line + 2100 3450 2500 3450 +Wire Wire Line + 2500 3450 2500 3300 +Wire Wire Line + 2500 3300 3400 3300 +Wire Wire Line + 2050 4450 2050 4550 +Wire Wire Line + 2050 4550 3450 4550 +Wire Wire Line + 4200 3300 4200 3150 +Wire Wire Line + 4200 3150 5250 3150 +Wire Wire Line + 4250 4550 4250 4600 +Wire Wire Line + 4250 4600 5300 4600 +Wire Wire Line + 6100 4500 6100 4600 +Wire Wire Line + 6100 4600 6300 4600 +Wire Wire Line + 6050 3250 6050 3100 +Wire Wire Line + 6050 3100 6150 3100 +Wire Wire Line + 2500 4000 2500 5800 +Wire Wire Line + 2500 5800 5350 5800 +Connection ~ 2500 4000 +Wire Wire Line + 2500 4000 3000 4000 +Wire Wire Line + 6150 5800 6500 5800 +Wire Wire Line + 6500 5800 6500 4400 +Wire Wire Line + 6500 3300 6850 3300 +Wire Wire Line + 6950 4400 6500 4400 +Connection ~ 6500 4400 +Wire Wire Line + 6500 4400 6500 3300 +Wire Wire Line + 7750 4500 7750 4600 +Wire Wire Line + 7750 4600 8400 4600 +Wire Wire Line + 7650 3200 7650 3100 +Wire Wire Line + 7650 3100 8450 3100 +Wire Wire Line + 8450 3300 8150 3300 +Wire Wire Line + 8150 3300 8150 3700 +Wire Wire Line + 8150 3700 9600 3700 +Wire Wire Line + 9600 3700 9600 4500 +Wire Wire Line + 9600 4500 9200 4500 +Wire Wire Line + 8400 4400 8200 4400 +Wire Wire Line + 8200 4400 8200 3800 +Wire Wire Line + 8200 3800 9450 3800 +Wire Wire Line + 9450 3800 9450 3200 +Wire Wire Line + 9450 3200 9250 3200 +Wire Wire Line + 5250 3350 4800 3350 +Wire Wire Line + 4800 3350 4800 3800 +Wire Wire Line + 4800 3800 6300 3800 +Wire Wire Line + 6300 3800 6300 4600 +Connection ~ 6300 4600 +Wire Wire Line + 6300 4600 6950 4600 +Wire Wire Line + 5300 4400 5100 4400 +Wire Wire Line + 5100 4400 5100 3900 +Wire Wire Line + 5100 3900 6200 3900 +Wire Wire Line + 6200 3900 6200 3100 +Connection ~ 6200 3100 +Wire Wire Line + 6200 3100 6850 3100 +$Comp +L Device:R R1 +U 1 1 5B2A209E +P 10300 3200 +F 0 "R1" V 10093 3200 50 0000 C CNN +F 1 "10meg" V 10184 3200 50 0000 C CNN +F 2 "" V 10230 3200 50 0001 C CNN +F 3 "~" H 10300 3200 50 0001 C CNN + 1 10300 3200 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR06 +U 1 1 5B2A2ACE +P 10750 3200 +F 0 "#PWR06" H 10750 2950 50 0001 C CNN +F 1 "GND" H 10755 3027 50 0000 C CNN +F 2 "" H 10750 3200 50 0001 C CNN +F 3 "" H 10750 3200 50 0001 C CNN + 1 10750 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10750 3200 10450 3200 +Connection ~ 9450 3200 +$Comp +L Device:R R2 +U 1 1 5B2A3E5E +P 10300 4500 +F 0 "R2" V 10093 4500 50 0000 C CNN +F 1 "10meg" V 10184 4500 50 0000 C CNN +F 2 "" V 10230 4500 50 0001 C CNN +F 3 "~" H 10300 4500 50 0001 C CNN + 1 10300 4500 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR05 +U 1 1 5B2A3E9F +P 10600 4500 +F 0 "#PWR05" H 10600 4250 50 0001 C CNN +F 1 "GND" H 10605 4327 50 0000 C CNN +F 2 "" H 10600 4500 50 0001 C CNN +F 3 "" H 10600 4500 50 0001 C CNN + 1 10600 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10600 4500 10450 4500 +Wire Wire Line + 10150 4500 10100 4500 +Wire Wire Line + 3400 3200 2600 3200 +Wire Wire Line + 2600 3200 2600 2100 +Wire Wire Line + 3450 4650 3450 5150 +Wire Wire Line + 3450 5150 9750 5150 +Wire Wire Line + 9750 5150 9750 3200 +Wire Wire Line + 9750 3200 9450 3200 +Text GLabel 9950 4050 0 50 Output ~ 0 +6 +Wire Wire Line + 9950 4050 10100 4050 +Wire Wire Line + 10100 4050 10100 4500 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B2AA56F +P 1300 2000 +F 0 "V2" H 1528 2046 50 0000 L CNN +F 1 "VSOURCE" H 1528 1955 50 0000 L CNN +F 2 "" H 1300 2000 50 0001 C CNN +F 3 "" H 1300 2000 50 0001 C CNN +F 4 "V" H 1300 2000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 1300 2000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1300 2000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1300 2000 + 1 0 0 -1 +$EndComp +Text GLabel 1150 1450 0 50 Input ~ 0 +1 +$Comp +L power:GND #PWR02 +U 1 1 5B2AA5E3 +P 1300 2650 +F 0 "#PWR02" H 1300 2400 50 0001 C CNN +F 1 "GND" H 1305 2477 50 0000 C CNN +F 2 "" H 1300 2650 50 0001 C CNN +F 3 "" H 1300 2650 50 0001 C CNN + 1 1300 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 2300 1300 2650 +Wire Wire Line + 1300 1700 1300 1450 +Wire Wire Line + 1300 1450 1150 1450 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B2ACCD6 +P 1150 5150 +F 0 "V1" H 1378 5196 50 0000 L CNN +F 1 "VSOURCE" H 1378 5105 50 0000 L CNN +F 2 "" H 1150 5150 50 0001 C CNN +F 3 "" H 1150 5150 50 0001 C CNN +F 4 "V" H 1150 5150 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 1150 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1150 5150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1150 5150 + 1 0 0 -1 +$EndComp +Text GLabel 950 4450 0 50 Input ~ 0 +3 +Wire Wire Line + 950 4450 1150 4450 +Wire Wire Line + 1150 4450 1150 4850 +$Comp +L power:GND #PWR01 +U 1 1 5B2AE376 +P 1100 5850 +F 0 "#PWR01" H 1100 5600 50 0001 C CNN +F 1 "GND" H 1105 5677 50 0000 C CNN +F 2 "" H 1100 5850 50 0001 C CNN +F 3 "" H 1100 5850 50 0001 C CNN + 1 1100 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 5850 1100 5450 +Wire Wire Line + 1100 5450 1150 5450 +Text GLabel 3550 2550 0 50 Input ~ 0 +4 +Wire Wire Line + 3800 2900 3800 2550 +Wire Wire Line + 3800 2550 3550 2550 +Text GLabel 5400 2500 0 50 Input ~ 0 +4 +Wire Wire Line + 5400 2500 5650 2500 +Wire Wire Line + 5650 2500 5650 2850 +Text GLabel 6950 2450 0 50 Input ~ 0 +4 +Wire Wire Line + 7250 2800 7250 2450 +Wire Wire Line + 7250 2450 6950 2450 +Text GLabel 8550 2450 0 50 Input ~ 0 +4 +Wire Wire Line + 8850 2800 8850 2450 +Wire Wire Line + 8850 2450 8550 2450 +Text GLabel 8550 3950 0 50 Input ~ 0 +4 +Wire Wire Line + 8800 4100 8800 3950 +Wire Wire Line + 8800 3950 8550 3950 +Text GLabel 7150 3900 0 50 Input ~ 0 +4 +Wire Wire Line + 7350 4100 7350 3900 +Wire Wire Line + 7350 3900 7150 3900 +Text GLabel 5400 4000 0 50 Input ~ 0 +4 +Wire Wire Line + 5700 4100 5700 4000 +Wire Wire Line + 5700 4000 5400 4000 +Text GLabel 3650 4000 0 50 Input ~ 0 +4 +Wire Wire Line + 3850 4150 3850 4000 +Wire Wire Line + 3850 4000 3650 4000 +Text GLabel 5100 5300 0 50 Input ~ 0 +4 +Wire Wire Line + 5750 5500 5750 5300 +Wire Wire Line + 5750 5300 5100 5300 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B2C1078 +P 2300 6550 +F 0 "V3" H 2528 6596 50 0000 L CNN +F 1 "VSOURCE" H 2528 6505 50 0000 L CNN +F 2 "" H 2300 6550 50 0001 C CNN +F 3 "" H 2300 6550 50 0001 C CNN +F 4 "V" H 2300 6550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3)" H 2300 6550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2300 6550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2300 6550 + 1 0 0 -1 +$EndComp +Text GLabel 2100 5850 0 50 Input ~ 0 +2 +$Comp +L power:GND #PWR03 +U 1 1 5B2C1180 +P 2300 7050 +F 0 "#PWR03" H 2300 6800 50 0001 C CNN +F 1 "GND" H 2305 6877 50 0000 C CNN +F 2 "" H 2300 7050 50 0001 C CNN +F 3 "" H 2300 7050 50 0001 C CNN + 1 2300 7050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2300 7050 2300 6850 +Wire Wire Line + 2300 6250 2300 5850 +Wire Wire Line + 2300 5850 2100 5850 +$Comp +L pspice:VSOURCE V4 +U 1 1 5B2C5F12 +P 3900 6950 +F 0 "V4" H 4128 6996 50 0000 L CNN +F 1 "VSOURCE" H 4128 6905 50 0000 L CNN +F 2 "" H 3900 6950 50 0001 C CNN +F 3 "" H 3900 6950 50 0001 C CNN +F 4 "V" H 3900 6950 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 3900 6950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3900 6950 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3900 6950 + 1 0 0 -1 +$EndComp +Text GLabel 3850 6250 0 50 Input ~ 0 +4 +$Comp +L power:GND #PWR04 +U 1 1 5B2C5FB4 +P 3900 7350 +F 0 "#PWR04" H 3900 7100 50 0001 C CNN +F 1 "GND" H 3905 7177 50 0000 C CNN +F 2 "" H 3900 7350 50 0001 C CNN +F 3 "" H 3900 7350 50 0001 C CNN + 1 3900 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 7350 3900 7250 +Wire Wire Line + 3900 6650 3900 6250 +Wire Wire Line + 3900 6250 3850 6250 +Text Notes 7650 6150 0 50 ~ 0 +.tran .25m 50m +Text GLabel 6150 2600 0 50 Output ~ 0 +q12 +Wire Wire Line + 6150 2600 6300 2600 +Wire Wire Line + 6300 2600 6300 2850 +Wire Wire Line + 6300 2850 6150 2850 +Wire Wire Line + 6150 2850 6150 3100 +Connection ~ 6150 3100 +Wire Wire Line + 6150 3100 6200 3100 +Wire Wire Line + 1250 3700 1250 4000 +Wire Wire Line + 2100 3700 2100 4000 +Connection ~ 10100 4500 +Connection ~ 9600 4500 +Connection ~ 9750 3200 +Text GLabel 9800 2700 0 50 Output ~ 0 +5 +Wire Wire Line + 10100 3200 10150 3200 +Wire Wire Line + 9750 3200 10100 3200 +Connection ~ 10100 3200 +Wire Wire Line + 10100 2700 10100 3200 +Wire Wire Line + 9800 2700 10100 2700 +Wire Wire Line + 2600 2100 10050 2100 +Wire Wire Line + 10100 4500 10050 4500 +Wire Wire Line + 10050 4500 9600 4500 +Connection ~ 10050 4500 +Wire Wire Line + 10050 2100 10050 4500 +Wire Wire Line + 1250 3700 2100 3700 +$EndSCHEMATC diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff.cir b/digital ciruits/masterslave_jkff/masterslave_jkff.cir new file mode 100644 index 0000000..b834d50 --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff.cir @@ -0,0 +1,20 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" +X3 Net-_X1-PadOut_ Net-_X3-PadB_ q12 4 NAND +X1 6 1 Net-_X1-PadC_ Net-_X1-PadOut_ 4 NAND3 +X2 Net-_X1-PadC_ 3 5 Net-_X2-PadOut_ 4 NAND3 +X4 q12 Net-_X2-PadOut_ Net-_X3-PadB_ 4 NAND +X6 q12 Net-_X5-PadOut_ Net-_X6-PadOut_ 4 NAND +X7 Net-_X5-PadOut_ Net-_X3-PadB_ Net-_X7-PadOut_ 4 NAND +X9 Net-_X6-PadOut_ 6 5 4 NAND +X8 5 Net-_X7-PadOut_ 6 4 NAND +X5 Net-_X1-PadC_ Net-_X5-PadOut_ 4 NOT +R1 GND 5 10meg +R2 GND 6 10meg +V2 1 GND dc 3.3 +V1 3 GND dc 3.3 +V3 2 GND dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3) +V4 4 GND dc 3.3 +X10 2 Net-_X1-PadC_ 4 NOT +.tran .25m 50m +.end diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff.kicad_pcb b/digital ciruits/masterslave_jkff/masterslave_jkff.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff.pro b/digital ciruits/masterslave_jkff/masterslave_jkff.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff.sch b/digital ciruits/masterslave_jkff/masterslave_jkff.sch new file mode 100644 index 0000000..ccdebf2 --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff.sch @@ -0,0 +1,587 @@ +EESchema Schematic File Version 4 +LIBS:masterslave_jkff-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L sim_logic:CMOS_NAND X3 +U 1 1 5B29F141 +P 5450 3250 +F 0 "X3" H 5650 2978 50 0000 C CNN +F 1 "CMOS_NAND" H 5650 2887 50 0000 C CNN +F 2 "" H 5450 3250 50 0001 C CNN +F 3 "" H 5450 3250 50 0001 C CNN +F 4 "X" H 5450 3250 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5450 3250 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5450 3250 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5450 3250 50 0001 C CNN "Spice_Lib_File" + 1 5450 3250 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X1 +U 1 1 5B29F238 +P 3600 3300 +F 0 "X1" H 3800 3028 50 0000 C CNN +F 1 "CMOS_NAND3" H 3800 2937 50 0000 C CNN +F 2 "" H 3600 3300 50 0001 C CNN +F 3 "" H 3600 3300 50 0001 C CNN +F 4 "X" H 3600 3300 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 3600 3300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3600 3300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 3600 3300 50 0001 C CNN "Spice_Lib_File" + 1 3600 3300 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X2 +U 1 1 5B29F2F2 +P 3650 4550 +F 0 "X2" H 3850 4278 50 0000 C CNN +F 1 "CMOS_NAND3" H 3850 4187 50 0000 C CNN +F 2 "" H 3650 4550 50 0001 C CNN +F 3 "" H 3650 4550 50 0001 C CNN +F 4 "X" H 3650 4550 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 3650 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3650 4550 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 3650 4550 50 0001 C CNN "Spice_Lib_File" + 1 3650 4550 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X4 +U 1 1 5B29F3E9 +P 5500 4500 +F 0 "X4" H 5700 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 5700 4137 50 0000 C CNN +F 2 "" H 5500 4500 50 0001 C CNN +F 3 "" H 5500 4500 50 0001 C CNN +F 4 "X" H 5500 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5500 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5500 4500 50 0001 C CNN "Spice_Lib_File" + 1 5500 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X6 +U 1 1 5B29F421 +P 7050 3200 +F 0 "X6" H 7250 2928 50 0000 C CNN +F 1 "CMOS_NAND" H 7250 2837 50 0000 C CNN +F 2 "" H 7050 3200 50 0001 C CNN +F 3 "" H 7050 3200 50 0001 C CNN +F 4 "X" H 7050 3200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 7050 3200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7050 3200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 7050 3200 50 0001 C CNN "Spice_Lib_File" + 1 7050 3200 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X7 +U 1 1 5B29F51D +P 7150 4500 +F 0 "X7" H 7350 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 7350 4137 50 0000 C CNN +F 2 "" H 7150 4500 50 0001 C CNN +F 3 "" H 7150 4500 50 0001 C CNN +F 4 "X" H 7150 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 7150 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7150 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 7150 4500 50 0001 C CNN "Spice_Lib_File" + 1 7150 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X9 +U 1 1 5B29F56B +P 8650 3200 +F 0 "X9" H 8850 2928 50 0000 C CNN +F 1 "CMOS_NAND" H 8850 2837 50 0000 C CNN +F 2 "" H 8650 3200 50 0001 C CNN +F 3 "" H 8650 3200 50 0001 C CNN +F 4 "X" H 8650 3200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 8650 3200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8650 3200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 8650 3200 50 0001 C CNN "Spice_Lib_File" + 1 8650 3200 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X8 +U 1 1 5B29F5E4 +P 8600 4500 +F 0 "X8" H 8800 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 8800 4137 50 0000 C CNN +F 2 "" H 8600 4500 50 0001 C CNN +F 3 "" H 8600 4500 50 0001 C CNN +F 4 "X" H 8600 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 8600 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8600 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 8600 4500 50 0001 C CNN "Spice_Lib_File" + 1 8600 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NOT X5 +U 1 1 5B29F6B5 +P 5550 5800 +F 0 "X5" H 5750 5528 50 0000 C CNN +F 1 "CMOS_NOT" H 5750 5437 50 0000 C CNN +F 2 "" H 5550 5800 50 0001 C CNN +F 3 "" H 5550 5800 50 0001 C CNN +F 4 "X" H 5550 5800 50 0001 C CNN "Spice_Primitive" +F 5 "NOT" H 5550 5800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 5800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5550 5800 50 0001 C CNN "Spice_Lib_File" + 1 5550 5800 + 1 0 0 -1 +$EndComp +Text GLabel 450 4000 0 50 Input ~ 0 +2 +Text GLabel 2100 3450 0 50 Input ~ 0 +1 +Text GLabel 2050 4450 0 50 Input ~ 0 +3 +Wire Wire Line + 3000 3400 3400 3400 +Wire Wire Line + 3000 4450 3450 4450 +Wire Wire Line + 2100 3450 2500 3450 +Wire Wire Line + 2500 3450 2500 3300 +Wire Wire Line + 2500 3300 3400 3300 +Wire Wire Line + 2050 4450 2050 4550 +Wire Wire Line + 2050 4550 3450 4550 +Wire Wire Line + 4200 3300 4200 3150 +Wire Wire Line + 4200 3150 5250 3150 +Wire Wire Line + 4250 4550 4250 4600 +Wire Wire Line + 4250 4600 5300 4600 +Wire Wire Line + 6100 4500 6100 4600 +Wire Wire Line + 6100 4600 6300 4600 +Wire Wire Line + 6050 3250 6050 3100 +Wire Wire Line + 6050 3100 6150 3100 +Wire Wire Line + 2500 5800 5350 5800 +Wire Wire Line + 6150 5800 6500 5800 +Wire Wire Line + 6500 5800 6500 4400 +Wire Wire Line + 6500 3300 6850 3300 +Wire Wire Line + 6950 4400 6500 4400 +Connection ~ 6500 4400 +Wire Wire Line + 6500 4400 6500 3300 +Wire Wire Line + 7750 4500 7750 4600 +Wire Wire Line + 7750 4600 8400 4600 +Wire Wire Line + 7650 3200 7650 3100 +Wire Wire Line + 7650 3100 8450 3100 +Wire Wire Line + 8450 3300 8150 3300 +Wire Wire Line + 8150 3300 8150 3700 +Wire Wire Line + 8150 3700 9600 3700 +Wire Wire Line + 9600 3700 9600 4500 +Wire Wire Line + 9600 4500 9200 4500 +Wire Wire Line + 8400 4400 8200 4400 +Wire Wire Line + 8200 4400 8200 3800 +Wire Wire Line + 8200 3800 9450 3800 +Wire Wire Line + 9450 3800 9450 3200 +Wire Wire Line + 9450 3200 9250 3200 +Wire Wire Line + 5250 3350 4800 3350 +Wire Wire Line + 4800 3350 4800 3800 +Wire Wire Line + 4800 3800 6300 3800 +Wire Wire Line + 6300 3800 6300 4600 +Connection ~ 6300 4600 +Wire Wire Line + 6300 4600 6950 4600 +Wire Wire Line + 5300 4400 5100 4400 +Wire Wire Line + 5100 4400 5100 3900 +Wire Wire Line + 5100 3900 6200 3900 +Wire Wire Line + 6200 3900 6200 3100 +Connection ~ 6200 3100 +Wire Wire Line + 6200 3100 6850 3100 +$Comp +L Device:R R1 +U 1 1 5B2A209E +P 10300 3200 +F 0 "R1" V 10093 3200 50 0000 C CNN +F 1 "10meg" V 10184 3200 50 0000 C CNN +F 2 "" V 10230 3200 50 0001 C CNN +F 3 "~" H 10300 3200 50 0001 C CNN + 1 10300 3200 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR06 +U 1 1 5B2A2ACE +P 10750 3200 +F 0 "#PWR06" H 10750 2950 50 0001 C CNN +F 1 "GND" H 10755 3027 50 0000 C CNN +F 2 "" H 10750 3200 50 0001 C CNN +F 3 "" H 10750 3200 50 0001 C CNN + 1 10750 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10750 3200 10450 3200 +Connection ~ 9450 3200 +$Comp +L Device:R R2 +U 1 1 5B2A3E5E +P 10300 4500 +F 0 "R2" V 10093 4500 50 0000 C CNN +F 1 "10meg" V 10184 4500 50 0000 C CNN +F 2 "" V 10230 4500 50 0001 C CNN +F 3 "~" H 10300 4500 50 0001 C CNN + 1 10300 4500 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR05 +U 1 1 5B2A3E9F +P 10600 4500 +F 0 "#PWR05" H 10600 4250 50 0001 C CNN +F 1 "GND" H 10605 4327 50 0000 C CNN +F 2 "" H 10600 4500 50 0001 C CNN +F 3 "" H 10600 4500 50 0001 C CNN + 1 10600 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10600 4500 10450 4500 +Wire Wire Line + 10150 4500 10100 4500 +Wire Wire Line + 3400 3200 2600 3200 +Wire Wire Line + 2600 3200 2600 2100 +Wire Wire Line + 3450 4650 3450 5150 +Wire Wire Line + 3450 5150 9750 5150 +Wire Wire Line + 9750 5150 9750 3200 +Wire Wire Line + 9750 3200 9450 3200 +Text GLabel 9950 4050 0 50 Output ~ 0 +6 +Wire Wire Line + 9950 4050 10100 4050 +Wire Wire Line + 10100 4050 10100 4500 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B2AA56F +P 1300 2000 +F 0 "V2" H 1528 2046 50 0000 L CNN +F 1 "VSOURCE" H 1528 1955 50 0000 L CNN +F 2 "" H 1300 2000 50 0001 C CNN +F 3 "" H 1300 2000 50 0001 C CNN +F 4 "V" H 1300 2000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 1300 2000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1300 2000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1300 2000 + 1 0 0 -1 +$EndComp +Text GLabel 1150 1450 0 50 Input ~ 0 +1 +$Comp +L power:GND #PWR02 +U 1 1 5B2AA5E3 +P 1300 2650 +F 0 "#PWR02" H 1300 2400 50 0001 C CNN +F 1 "GND" H 1305 2477 50 0000 C CNN +F 2 "" H 1300 2650 50 0001 C CNN +F 3 "" H 1300 2650 50 0001 C CNN + 1 1300 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 2300 1300 2650 +Wire Wire Line + 1300 1700 1300 1450 +Wire Wire Line + 1300 1450 1150 1450 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B2ACCD6 +P 1150 5150 +F 0 "V1" H 1378 5196 50 0000 L CNN +F 1 "VSOURCE" H 1378 5105 50 0000 L CNN +F 2 "" H 1150 5150 50 0001 C CNN +F 3 "" H 1150 5150 50 0001 C CNN +F 4 "V" H 1150 5150 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 1150 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1150 5150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1150 5150 + 1 0 0 -1 +$EndComp +Text GLabel 950 4450 0 50 Input ~ 0 +3 +Wire Wire Line + 950 4450 1150 4450 +Wire Wire Line + 1150 4450 1150 4850 +$Comp +L power:GND #PWR01 +U 1 1 5B2AE376 +P 1100 5850 +F 0 "#PWR01" H 1100 5600 50 0001 C CNN +F 1 "GND" H 1105 5677 50 0000 C CNN +F 2 "" H 1100 5850 50 0001 C CNN +F 3 "" H 1100 5850 50 0001 C CNN + 1 1100 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 5850 1100 5450 +Wire Wire Line + 1100 5450 1150 5450 +Text GLabel 3550 2550 0 50 Input ~ 0 +4 +Wire Wire Line + 3800 2900 3800 2550 +Wire Wire Line + 3800 2550 3550 2550 +Text GLabel 5400 2500 0 50 Input ~ 0 +4 +Wire Wire Line + 5400 2500 5650 2500 +Wire Wire Line + 5650 2500 5650 2850 +Text GLabel 6950 2450 0 50 Input ~ 0 +4 +Wire Wire Line + 7250 2800 7250 2450 +Wire Wire Line + 7250 2450 6950 2450 +Text GLabel 8550 2450 0 50 Input ~ 0 +4 +Wire Wire Line + 8850 2800 8850 2450 +Wire Wire Line + 8850 2450 8550 2450 +Text GLabel 8550 3950 0 50 Input ~ 0 +4 +Wire Wire Line + 8800 4100 8800 3950 +Wire Wire Line + 8800 3950 8550 3950 +Text GLabel 7150 3900 0 50 Input ~ 0 +4 +Wire Wire Line + 7350 4100 7350 3900 +Wire Wire Line + 7350 3900 7150 3900 +Text GLabel 5400 4000 0 50 Input ~ 0 +4 +Wire Wire Line + 5700 4100 5700 4000 +Wire Wire Line + 5700 4000 5400 4000 +Text GLabel 3650 4000 0 50 Input ~ 0 +4 +Wire Wire Line + 3850 4150 3850 4000 +Wire Wire Line + 3850 4000 3650 4000 +Text GLabel 5100 5300 0 50 Input ~ 0 +4 +Wire Wire Line + 5750 5500 5750 5300 +Wire Wire Line + 5750 5300 5100 5300 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B2C1078 +P 2300 6550 +F 0 "V3" H 2528 6596 50 0000 L CNN +F 1 "VSOURCE" H 2528 6505 50 0000 L CNN +F 2 "" H 2300 6550 50 0001 C CNN +F 3 "" H 2300 6550 50 0001 C CNN +F 4 "V" H 2300 6550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3)" H 2300 6550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2300 6550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2300 6550 + 1 0 0 -1 +$EndComp +Text GLabel 2100 5850 0 50 Input ~ 0 +2 +$Comp +L power:GND #PWR03 +U 1 1 5B2C1180 +P 2300 7050 +F 0 "#PWR03" H 2300 6800 50 0001 C CNN +F 1 "GND" H 2305 6877 50 0000 C CNN +F 2 "" H 2300 7050 50 0001 C CNN +F 3 "" H 2300 7050 50 0001 C CNN + 1 2300 7050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2300 7050 2300 6850 +Wire Wire Line + 2300 6250 2300 5850 +Wire Wire Line + 2300 5850 2100 5850 +$Comp +L pspice:VSOURCE V4 +U 1 1 5B2C5F12 +P 3900 6950 +F 0 "V4" H 4128 6996 50 0000 L CNN +F 1 "VSOURCE" H 4128 6905 50 0000 L CNN +F 2 "" H 3900 6950 50 0001 C CNN +F 3 "" H 3900 6950 50 0001 C CNN +F 4 "V" H 3900 6950 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 3900 6950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3900 6950 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3900 6950 + 1 0 0 -1 +$EndComp +Text GLabel 3850 6250 0 50 Input ~ 0 +4 +$Comp +L power:GND #PWR04 +U 1 1 5B2C5FB4 +P 3900 7350 +F 0 "#PWR04" H 3900 7100 50 0001 C CNN +F 1 "GND" H 3905 7177 50 0000 C CNN +F 2 "" H 3900 7350 50 0001 C CNN +F 3 "" H 3900 7350 50 0001 C CNN + 1 3900 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 7350 3900 7250 +Wire Wire Line + 3900 6650 3900 6250 +Wire Wire Line + 3900 6250 3850 6250 +Text Notes 7650 6150 0 50 ~ 0 +.tran .25m 50m +Text GLabel 6150 2600 0 50 Output ~ 0 +q12 +Wire Wire Line + 6150 2600 6300 2600 +Wire Wire Line + 6300 2600 6300 2850 +Wire Wire Line + 6300 2850 6150 2850 +Wire Wire Line + 6150 2850 6150 3100 +Connection ~ 6150 3100 +Wire Wire Line + 6150 3100 6200 3100 +Connection ~ 10100 4500 +Connection ~ 9600 4500 +Connection ~ 9750 3200 +Text GLabel 9800 2700 0 50 Output ~ 0 +5 +Wire Wire Line + 10100 3200 10150 3200 +Wire Wire Line + 9750 3200 10100 3200 +Connection ~ 10100 3200 +Wire Wire Line + 10100 2700 10100 3200 +Wire Wire Line + 9800 2700 10100 2700 +Wire Wire Line + 2600 2100 10050 2100 +Wire Wire Line + 10100 4500 10050 4500 +Wire Wire Line + 10050 4500 9600 4500 +Connection ~ 10050 4500 +Wire Wire Line + 10050 2100 10050 4500 +$Comp +L sim_logic:CMOS_NOT X10 +U 1 1 5B2B88B8 +P 650 4000 +F 0 "X10" H 850 3728 50 0000 C CNN +F 1 "CMOS_NOT" H 850 3637 50 0000 C CNN +F 2 "" H 650 4000 50 0001 C CNN +F 3 "" H 650 4000 50 0001 C CNN +F 4 "X" H 650 4000 50 0001 C CNN "Spice_Primitive" +F 5 "NOT" H 650 4000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 650 4000 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 650 4000 50 0001 C CNN "Spice_Lib_File" + 1 650 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 3400 3000 3950 +Wire Wire Line + 1250 4000 1750 4000 +Wire Wire Line + 2050 4000 2050 3950 +Connection ~ 3000 3950 +Wire Wire Line + 3000 3950 3000 4450 +Wire Wire Line + 1750 4000 1750 5650 +Wire Wire Line + 1750 5650 2500 5650 +Wire Wire Line + 2500 5650 2500 5800 +Connection ~ 1750 4000 +Wire Wire Line + 1750 4000 2050 4000 +Text GLabel 650 3650 0 50 Input ~ 0 +4 +Wire Wire Line + 650 3650 850 3650 +Wire Wire Line + 850 3650 850 3700 +Wire Wire Line + 2050 3950 3000 3950 +$EndSCHEMATC diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff.sub b/digital ciruits/masterslave_jkff/masterslave_jkff.sub new file mode 100644 index 0000000..bf1b45a --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff.sub @@ -0,0 +1,14 @@ + +.SUBCKT JKFLIPFLOP 1 2 3 4 5 6 +.include "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" +X3 Net-_X1-PadOut_ Net-_X3-PadB_ q12 4 NAND +X1 6 1 Net-_X1-PadC_ Net-_X1-PadOut_ 4 NAND3 +X2 Net-_X1-PadC_ 3 5 Net-_X2-PadOut_ 4 NAND3 +X4 q12 Net-_X2-PadOut_ Net-_X3-PadB_ 4 NAND +X6 q12 Net-_X5-PadOut_ Net-_X6-PadOut_ 4 NAND +X7 Net-_X5-PadOut_ Net-_X3-PadB_ Net-_X7-PadOut_ 4 NAND +X9 Net-_X6-PadOut_ 6 5 4 NAND +X8 5 Net-_X7-PadOut_ 6 4 NAND +X5 Net-_X1-PadC_ Net-_X5-PadOut_ 4 NOT +X10 2 Net-_X1-PadC_ 4 NOT +.ends diff --git a/digital ciruits/masterslave_jkff/sym-lib-table b/digital ciruits/masterslave_jkff/sym-lib-table new file mode 100644 index 0000000..47f3275 --- /dev/null +++ b/digital ciruits/masterslave_jkff/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sim_logic)(type Legacy)(uri /home/akshay/Downloads/kicad-simulation-examples-master/libs/sim_logic.lib)(options "")(descr "")) +) diff --git a/digital ciruits/nor_sub/_saved_nor_sub-cache.lib b/digital ciruits/nor_sub/_saved_nor_sub-cache.lib new file mode 100644 index 0000000..d33fa10 --- /dev/null +++ b/digital ciruits/nor_sub/_saved_nor_sub-cache.lib @@ -0,0 +1,84 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# nor_sub:NOR +# +DEF nor_sub:NOR X 0 40 Y Y 1 F N +F0 "X" -100 -50 39 H V C CNN +F1 "nor_sub:NOR" -100 -100 39 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -250 -250 50 -250 0 1 0 N +S -250 100 -250 -250 0 1 0 N +S 50 100 -250 100 0 1 0 N +S 50 100 50 -250 0 1 0 N +X A 1 -450 0 200 R 50 28 1 1 I +X B 2 -450 -150 200 R 50 28 1 1 I +X Out 3 250 -150 200 L 50 31 1 1 O +X VDD 4 250 0 200 L 50 28 1 1 I +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/nor_sub/_saved_nor_sub.cir b/digital ciruits/nor_sub/_saved_nor_sub.cir new file mode 100644 index 0000000..7a1377d --- /dev/null +++ b/digital ciruits/nor_sub/_saved_nor_sub.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +.include "/home/akshay/Desktop/digital ciruits/libs/fossee_spice_models.lib" +V1 a GND pulse(0 3.3 0 0 0 50m 100m) +V3 VDD GND dc 3.3 +V2 b GND pulse(0 3.3 50m 0 0 50m 100m) +R1 GND Out 10meg +X1 a b Out VDD NOR +.tran .25m 30m +.end diff --git a/digital ciruits/nor_sub/_saved_nor_sub.pro b/digital ciruits/nor_sub/_saved_nor_sub.pro new file mode 100644 index 0000000..148e9ed --- /dev/null +++ b/digital ciruits/nor_sub/_saved_nor_sub.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice + diff --git a/digital ciruits/nor_sub/b3v33check.log b/digital ciruits/nor_sub/b3v33check.log new file mode 100644 index 0000000..27ec4ed --- /dev/null +++ b/digital ciruits/nor_sub/b3v33check.log @@ -0,0 +1,4 @@ +BSIM3v3.3.0 Parameter Checking.
+Model = mpmos
+Warning: Pd = 0 is less than W.
+Warning: Ps = 0 is less than W.
diff --git a/digital ciruits/nor_sub/nor_sub-cache.lib b/digital ciruits/nor_sub/nor_sub-cache.lib new file mode 100644 index 0000000..108bc84 --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub-cache.lib @@ -0,0 +1,84 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:NOR +# +DEF sim_logic:NOR X 0 40 Y Y 1 F N +F0 "X" -100 -50 39 H V C CNN +F1 "sim_logic:NOR" -100 -100 39 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -250 -250 50 -250 0 1 0 N +S -250 100 -250 -250 0 1 0 N +S 50 100 -250 100 0 1 0 N +S 50 100 50 -250 0 1 0 N +X A 1 -450 0 200 R 50 28 1 1 I +X B 2 -450 -150 200 R 50 28 1 1 I +X Out 3 250 -150 200 L 50 31 1 1 O +X VDD 4 250 0 200 L 50 28 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/nor_sub/nor_sub-rescue.dcm b/digital ciruits/nor_sub/nor_sub-rescue.dcm new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub-rescue.dcm diff --git a/digital ciruits/nor_sub/nor_sub-rescue.lib b/digital ciruits/nor_sub/nor_sub-rescue.lib new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub-rescue.lib diff --git a/digital ciruits/nor_sub/nor_sub.bak b/digital ciruits/nor_sub/nor_sub.bak new file mode 100644 index 0000000..2e0eec9 --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 4 +LIBS:nor_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B294AD5 +P 3300 3750 +F 0 "V1" H 3528 3796 50 0000 L CNN +F 1 "VSOURCE" H 3528 3705 50 0000 L CNN +F 2 "" H 3300 3750 50 0001 C CNN +F 3 "" H 3300 3750 50 0001 C CNN +F 4 "V" H 3300 3750 50 0001 C CNN "Spice_Primitive" +F 5 "pulse(0 3.3 0 0 0 50m 100m)" H 3300 3750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3300 3750 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B294B5F +P 7750 4350 +F 0 "V3" H 7978 4396 50 0000 L CNN +F 1 "VSOURCE" H 7978 4305 50 0000 L CNN +F 2 "" H 7750 4350 50 0001 C CNN +F 3 "" H 7750 4350 50 0001 C CNN +F 4 "V" H 7750 4350 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 7750 4350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7750 4350 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7750 4350 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B294BE6 +P 4050 4250 +F 0 "V2" H 4278 4296 50 0000 L CNN +F 1 "VSOURCE" H 4278 4205 50 0000 L CNN +F 2 "" H 4050 4250 50 0001 C CNN +F 3 "" H 4050 4250 50 0001 C CNN +F 4 "V" H 4050 4250 50 0001 C CNN "Spice_Primitive" +F 5 "pulse(0 3.3 50m 0 0 50m 100m)" H 4050 4250 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4050 4250 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B294C95 +P 6600 3650 +F 0 "R1" V 6393 3650 50 0000 C CNN +F 1 "10meg" V 6484 3650 50 0000 C CNN +F 2 "" V 6530 3650 50 0001 C CNN +F 3 "~" H 6600 3650 50 0001 C CNN + 1 6600 3650 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 5B294D70 +P 7750 4900 +F 0 "#PWR0101" H 7750 4650 50 0001 C CNN +F 1 "GND" H 7755 4727 50 0000 C CNN +F 2 "" H 7750 4900 50 0001 C CNN +F 3 "" H 7750 4900 50 0001 C CNN + 1 7750 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0102 +U 1 1 5B294D8C +P 4050 4750 +F 0 "#PWR0102" H 4050 4500 50 0001 C CNN +F 1 "GND" H 4055 4577 50 0000 C CNN +F 2 "" H 4050 4750 50 0001 C CNN +F 3 "" H 4050 4750 50 0001 C CNN + 1 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0103 +U 1 1 5B294DA1 +P 3300 4250 +F 0 "#PWR0103" H 3300 4000 50 0001 C CNN +F 1 "GND" H 3305 4077 50 0000 C CNN +F 2 "" H 3300 4250 50 0001 C CNN +F 3 "" H 3300 4250 50 0001 C CNN + 1 3300 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 3350 4100 3350 +Wire Wire Line + 3300 3350 3300 3450 +Wire Wire Line + 4050 3950 4050 3650 +Wire Wire Line + 4050 3650 4400 3650 +Wire Wire Line + 4050 4550 4050 4750 +Wire Wire Line + 3300 4050 3300 4250 +$Comp +L power:GND #PWR0104 +U 1 1 5B294E99 +P 7000 3800 +F 0 "#PWR0104" H 7000 3550 50 0001 C CNN +F 1 "GND" H 7005 3627 50 0000 C CNN +F 2 "" H 7000 3800 50 0001 C CNN +F 3 "" H 7000 3800 50 0001 C CNN + 1 7000 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3650 7000 3650 +Wire Wire Line + 7000 3650 7000 3800 +Wire Wire Line + 7750 4650 7750 4900 +Text GLabel 6350 3450 0 50 Output ~ 0 +Out +Wire Wire Line + 6350 3450 6350 3650 +Connection ~ 6350 3650 +Wire Wire Line + 6350 3650 6450 3650 +Text GLabel 4000 3000 0 50 Output ~ 0 +a +Text GLabel 4350 3500 0 50 Output ~ 0 +b +Wire Wire Line + 4350 3500 4400 3500 +Wire Wire Line + 4400 3500 4400 3650 +Connection ~ 4400 3650 +Wire Wire Line + 4000 3000 4100 3000 +Wire Wire Line + 4100 3000 4100 3350 +Connection ~ 4100 3350 +$Comp +L power:VDD #PWR0105 +U 1 1 5B295DE6 +P 7750 3900 +F 0 "#PWR0105" H 7750 3750 50 0001 C CNN +F 1 "VDD" H 7767 4073 50 0000 C CNN +F 2 "" H 7750 3900 50 0001 C CNN +F 3 "" H 7750 3900 50 0001 C CNN + 1 7750 3900 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0106 +U 1 1 5B295E02 +P 6500 3300 +F 0 "#PWR0106" H 6500 3150 50 0001 C CNN +F 1 "VDD" H 6517 3473 50 0000 C CNN +F 2 "" H 6500 3300 50 0001 C CNN +F 3 "" H 6500 3300 50 0001 C CNN + 1 6500 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 3350 6500 3300 +Wire Wire Line + 7750 3900 7750 4050 +$Comp +L fossee_sim_logic:NOR X1 +U 1 1 5B3322EA +P 5700 3350 +F 0 "X1" H 5600 3591 39 0000 C CNN +F 1 "NOR" H 5600 3516 39 0000 C CNN +F 2 "" H 5700 3350 50 0001 C CNN +F 3 "" H 5700 3350 50 0001 C CNN +F 4 "X" H 5700 3350 50 0001 C CNN "Spice_Primitive" +F 5 "NOR" H 5700 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5700 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Desktop/digital ciruits/libs/fossee_spice_models.lib" H 5700 3350 50 0001 C CNN "Spice_Lib_File" + 1 5700 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4100 3350 5250 3350 +Wire Wire Line + 5250 3650 5250 3500 +Wire Wire Line + 5950 3350 6500 3350 +Wire Wire Line + 5950 3500 5950 3650 +Wire Wire Line + 5950 3650 6350 3650 +Wire Wire Line + 4400 3650 5250 3650 +Text Notes 6900 5450 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/digital ciruits/nor_sub/nor_sub.bck b/digital ciruits/nor_sub/nor_sub.bck new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/nor_sub/nor_sub.cir b/digital ciruits/nor_sub/nor_sub.cir new file mode 100644 index 0000000..7e1bbf0 --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +.include "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib" +V1 a GND pulse(0 3.3 0 0 0 50m 100m) +V3 VDD GND dc 3.3 +V2 b GND pulse(0 3.3 50m 0 0 50m 100m) +R1 GND Out 10meg +X1 a b Out VDD NOR +.tran .25m 30m +.end diff --git a/digital ciruits/nor_sub/nor_sub.dcm b/digital ciruits/nor_sub/nor_sub.dcm new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/nor_sub/nor_sub.kicad_pcb b/digital ciruits/nor_sub/nor_sub.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/nor_sub/nor_sub.lib b/digital ciruits/nor_sub/nor_sub.lib new file mode 100644 index 0000000..f2fc99d --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.lib @@ -0,0 +1,23 @@ +EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# NOR
+#
+DEF NOR X 0 40 Y Y 1 F N
+F0 "X" -100 -50 39 H V C CNN
+F1 "NOR" -100 -100 39 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -250 -250 50 -250 0 1 0 N
+S -250 100 -250 -250 0 1 0 N
+S 50 100 -250 100 0 1 0 N
+S 50 100 50 -250 0 1 0 N
+X A 1 -450 0 200 R 50 28 1 1 I
+X B 2 -450 -150 200 R 50 28 1 1 I
+X Out 3 250 -150 200 L 50 31 1 1 O
+X VDD 4 250 0 200 L 50 28 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/nor_sub/nor_sub.pro b/digital ciruits/nor_sub/nor_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/nor_sub/nor_sub.sch b/digital ciruits/nor_sub/nor_sub.sch new file mode 100644 index 0000000..00de794 --- /dev/null +++ b/digital ciruits/nor_sub/nor_sub.sch @@ -0,0 +1,208 @@ +EESchema Schematic File Version 4 +LIBS:nor_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B294AD5 +P 3300 3750 +F 0 "V1" H 3528 3796 50 0000 L CNN +F 1 "VSOURCE" H 3528 3705 50 0000 L CNN +F 2 "" H 3300 3750 50 0001 C CNN +F 3 "" H 3300 3750 50 0001 C CNN +F 4 "V" H 3300 3750 50 0001 C CNN "Spice_Primitive" +F 5 "pulse(0 3.3 0 0 0 50m 100m)" H 3300 3750 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3300 3750 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B294B5F +P 7750 4350 +F 0 "V3" H 7978 4396 50 0000 L CNN +F 1 "VSOURCE" H 7978 4305 50 0000 L CNN +F 2 "" H 7750 4350 50 0001 C CNN +F 3 "" H 7750 4350 50 0001 C CNN +F 4 "V" H 7750 4350 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 7750 4350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7750 4350 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7750 4350 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B294BE6 +P 4050 4250 +F 0 "V2" H 4278 4296 50 0000 L CNN +F 1 "VSOURCE" H 4278 4205 50 0000 L CNN +F 2 "" H 4050 4250 50 0001 C CNN +F 3 "" H 4050 4250 50 0001 C CNN +F 4 "V" H 4050 4250 50 0001 C CNN "Spice_Primitive" +F 5 "pulse(0 3.3 50m 0 0 50m 100m)" H 4050 4250 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4050 4250 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B294C95 +P 6600 3650 +F 0 "R1" V 6393 3650 50 0000 C CNN +F 1 "10meg" V 6484 3650 50 0000 C CNN +F 2 "" V 6530 3650 50 0001 C CNN +F 3 "~" H 6600 3650 50 0001 C CNN + 1 6600 3650 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0101 +U 1 1 5B294D70 +P 7750 4900 +F 0 "#PWR0101" H 7750 4650 50 0001 C CNN +F 1 "GND" H 7755 4727 50 0000 C CNN +F 2 "" H 7750 4900 50 0001 C CNN +F 3 "" H 7750 4900 50 0001 C CNN + 1 7750 4900 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0102 +U 1 1 5B294D8C +P 4050 4750 +F 0 "#PWR0102" H 4050 4500 50 0001 C CNN +F 1 "GND" H 4055 4577 50 0000 C CNN +F 2 "" H 4050 4750 50 0001 C CNN +F 3 "" H 4050 4750 50 0001 C CNN + 1 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0103 +U 1 1 5B294DA1 +P 3300 4250 +F 0 "#PWR0103" H 3300 4000 50 0001 C CNN +F 1 "GND" H 3305 4077 50 0000 C CNN +F 2 "" H 3300 4250 50 0001 C CNN +F 3 "" H 3300 4250 50 0001 C CNN + 1 3300 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 3350 4100 3350 +Wire Wire Line + 3300 3350 3300 3450 +Wire Wire Line + 4050 3950 4050 3650 +Wire Wire Line + 4050 3650 4400 3650 +Wire Wire Line + 4050 4550 4050 4750 +Wire Wire Line + 3300 4050 3300 4250 +$Comp +L power:GND #PWR0104 +U 1 1 5B294E99 +P 7000 3800 +F 0 "#PWR0104" H 7000 3550 50 0001 C CNN +F 1 "GND" H 7005 3627 50 0000 C CNN +F 2 "" H 7000 3800 50 0001 C CNN +F 3 "" H 7000 3800 50 0001 C CNN + 1 7000 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3650 7000 3650 +Wire Wire Line + 7000 3650 7000 3800 +Wire Wire Line + 7750 4650 7750 4900 +Text GLabel 6350 3450 0 50 Output ~ 0 +Out +Wire Wire Line + 6350 3450 6350 3650 +Connection ~ 6350 3650 +Wire Wire Line + 6350 3650 6450 3650 +Text GLabel 4000 3000 0 50 Output ~ 0 +a +Text GLabel 4350 3500 0 50 Output ~ 0 +b +Wire Wire Line + 4350 3500 4400 3500 +Wire Wire Line + 4400 3500 4400 3650 +Connection ~ 4400 3650 +Wire Wire Line + 4000 3000 4100 3000 +Wire Wire Line + 4100 3000 4100 3350 +Connection ~ 4100 3350 +$Comp +L power:VDD #PWR0105 +U 1 1 5B295DE6 +P 7750 3900 +F 0 "#PWR0105" H 7750 3750 50 0001 C CNN +F 1 "VDD" H 7767 4073 50 0000 C CNN +F 2 "" H 7750 3900 50 0001 C CNN +F 3 "" H 7750 3900 50 0001 C CNN + 1 7750 3900 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0106 +U 1 1 5B295E02 +P 6500 3300 +F 0 "#PWR0106" H 6500 3150 50 0001 C CNN +F 1 "VDD" H 6517 3473 50 0000 C CNN +F 2 "" H 6500 3300 50 0001 C CNN +F 3 "" H 6500 3300 50 0001 C CNN + 1 6500 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 3350 6500 3300 +Wire Wire Line + 7750 3900 7750 4050 +Wire Wire Line + 4100 3350 5250 3350 +Wire Wire Line + 5250 3650 5250 3500 +Wire Wire Line + 5950 3350 6500 3350 +Wire Wire Line + 5950 3500 5950 3650 +Wire Wire Line + 5950 3650 6350 3650 +Wire Wire Line + 4400 3650 5250 3650 +Text Notes 6900 5450 0 50 ~ 0 +.tran .25m 30m +$Comp +L sim_logic:NOR X1 +U 1 1 5B332768 +P 5700 3350 +F 0 "X1" H 5600 3591 39 0000 C CNN +F 1 "NOR" H 5600 3516 39 0000 C CNN +F 2 "" H 5700 3350 50 0001 C CNN +F 3 "" H 5700 3350 50 0001 C CNN +F 4 "X" H 5700 3350 50 0001 C CNN "Spice_Primitive" +F 5 "NOR" H 5700 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5700 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib" H 5700 3350 50 0001 C CNN "Spice_Lib_File" + 1 5700 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/digital ciruits/nor_sub/sym-lib-table b/digital ciruits/nor_sub/sym-lib-table new file mode 100644 index 0000000..24d3d6a --- /dev/null +++ b/digital ciruits/nor_sub/sym-lib-table @@ -0,0 +1,7 @@ +(sym_lib_table + (lib (name Logic_Gates)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/nor_sub/Logic_Gates.lib)(options "")(descr "")) + (lib (name nor_sub-rescue)(type Legacy)(uri ${KIPRJMOD}/nor_sub-rescue.lib)(options "")(descr "")) + (lib (name nor_sub)(type Legacy)(uri "/home/akshay/Desktop/digital ciruits/nor_sub/nor_sub.lib")(options "")(descr "")) + (lib (name fossee_sim_logic)(type Legacy)(uri "/home/akshay/Desktop/digital ciruits/libs/fossee_sim_logic.lib")(options "")(descr "")) + (lib (name sim_logic)(type Legacy)(uri "/home/akshay/Desktop/digital ciruits/libs/sim_logic.lib")(options "")(descr "")) +) diff --git a/digital ciruits/or_sub/Logic_Gates.bck b/digital ciruits/or_sub/Logic_Gates.bck new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/or_sub/Logic_Gates.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/or_sub/Logic_Gates.dcm b/digital ciruits/or_sub/Logic_Gates.dcm new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/or_sub/Logic_Gates.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/or_sub/Logic_Gates.lib b/digital ciruits/or_sub/Logic_Gates.lib new file mode 100644 index 0000000..37a3300 --- /dev/null +++ b/digital ciruits/or_sub/Logic_Gates.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# OR
+#
+DEF OR X 0 40 Y Y 1 F N
+F0 "X" 0 50 50 H V C CNN
+F1 "OR" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -200 150 200 -200 0 1 0 N
+X A 1 -400 100 200 R 50 39 1 1 I
+X B 2 -400 -100 200 R 50 39 1 1 I
+X OUT 3 400 -150 200 L 50 39 1 1 O
+X VDD 4 400 100 200 L 50 39 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/or_sub/b3v33check.log b/digital ciruits/or_sub/b3v33check.log new file mode 100644 index 0000000..27ec4ed --- /dev/null +++ b/digital ciruits/or_sub/b3v33check.log @@ -0,0 +1,4 @@ +BSIM3v3.3.0 Parameter Checking.
+Model = mpmos
+Warning: Pd = 0 is less than W.
+Warning: Ps = 0 is less than W.
diff --git a/digital ciruits/or_sub/basic_logicgates.bck b/digital ciruits/or_sub/basic_logicgates.bck new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/or_sub/basic_logicgates.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/or_sub/basic_logicgates.dcm b/digital ciruits/or_sub/basic_logicgates.dcm new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/or_sub/basic_logicgates.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/or_sub/or_sub-cache.lib b/digital ciruits/or_sub/or_sub-cache.lib new file mode 100644 index 0000000..3c0f171 --- /dev/null +++ b/digital ciruits/or_sub/or_sub-cache.lib @@ -0,0 +1,81 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# or_sub-rescue:OR-Logic_Gates +# +DEF or_sub-rescue:OR-Logic_Gates X 0 40 Y Y 1 F N +F0 "X" 0 50 50 H V C CNN +F1 "or_sub-rescue:OR-Logic_Gates" 0 -50 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -200 150 200 -200 0 1 0 N +X A 1 -400 100 200 R 50 39 1 1 I +X B 2 -400 -100 200 R 50 39 1 1 I +X OUT 3 400 -150 200 L 50 39 1 1 O +X VDD 4 400 100 200 L 50 39 1 1 I +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/or_sub/or_sub-rescue.dcm b/digital ciruits/or_sub/or_sub-rescue.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/or_sub/or_sub-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/or_sub/or_sub-rescue.lib b/digital ciruits/or_sub/or_sub-rescue.lib new file mode 100644 index 0000000..a170803 --- /dev/null +++ b/digital ciruits/or_sub/or_sub-rescue.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# OR-Logic_Gates +# +DEF OR-Logic_Gates X 0 40 Y Y 1 F N +F0 "X" 0 50 50 H V C CNN +F1 "OR-Logic_Gates" 0 -50 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -200 150 200 -200 0 1 0 N +X A 1 -400 100 200 R 50 39 1 1 I +X B 2 -400 -100 200 R 50 39 1 1 I +X OUT 3 400 -150 200 L 50 39 1 1 O +X VDD 4 400 100 200 L 50 39 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/or_sub/or_sub.bak b/digital ciruits/or_sub/or_sub.bak new file mode 100644 index 0000000..3d55da0 --- /dev/null +++ b/digital ciruits/or_sub/or_sub.bak @@ -0,0 +1,202 @@ +EESchema Schematic File Version 4 +LIBS:or_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L or_sub-rescue:OR-Logic_Gates X1 +U 1 1 5B28CA7D +P 5200 2800 +F 0 "X1" H 5200 3125 50 0000 C CNN +F 1 "OR" H 5200 3034 50 0000 C CNN +F 2 "" H 5200 2800 50 0001 C CNN +F 3 "" H 5200 2800 50 0001 C CNN +F 4 "X" H 5200 2800 50 0001 C CNN "Spice_Primitive" +F 5 "OR" H 5200 2800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5200 2800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Desktop/digital ciruits/libs/fossee_spice_models.lib" H 5200 2800 50 0001 C CNN "Spice_Lib_File" + 1 5200 2800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28CADB +P 2950 2950 +F 0 "V1" H 3178 2996 50 0000 L CNN +F 1 "VSOURCE" H 3178 2905 50 0000 L CNN +F 2 "" H 2950 2950 50 0001 C CNN +F 3 "" H 2950 2950 50 0001 C CNN +F 4 "V" H 2950 2950 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 2950 2950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2950 2950 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2950 2950 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28CB19 +P 3600 3150 +F 0 "V2" H 3828 3196 50 0000 L CNN +F 1 "VSOURCE" H 3828 3105 50 0000 L CNN +F 2 "" H 3600 3150 50 0001 C CNN +F 3 "" H 3600 3150 50 0001 C CNN +F 4 "V" H 3600 3150 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 3600 3150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3600 3150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3600 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2850 3850 2850 +Wire Wire Line + 4800 2850 4800 2900 +Wire Wire Line + 4800 2700 3250 2700 +Wire Wire Line + 3250 2700 3250 2450 +Wire Wire Line + 3250 2450 3150 2450 +Wire Wire Line + 2950 2450 2950 2650 +$Comp +L power:GND #PWR01 +U 1 1 5B28CBA8 +P 2950 3450 +F 0 "#PWR01" H 2950 3200 50 0001 C CNN +F 1 "GND" H 2955 3277 50 0000 C CNN +F 2 "" H 2950 3450 50 0001 C CNN +F 3 "" H 2950 3450 50 0001 C CNN + 1 2950 3450 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR02 +U 1 1 5B28CBDE +P 3600 3650 +F 0 "#PWR02" H 3600 3400 50 0001 C CNN +F 1 "GND" H 3605 3477 50 0000 C CNN +F 2 "" H 3600 3650 50 0001 C CNN +F 3 "" H 3600 3650 50 0001 C CNN + 1 3600 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 3650 3600 3450 +Wire Wire Line + 2950 3450 2950 3250 +$Comp +L power:VDD #PWR03 +U 1 1 5B28CCFB +P 5700 2700 +F 0 "#PWR03" H 5700 2550 50 0001 C CNN +F 1 "VDD" V 5717 2828 50 0000 L CNN +F 2 "" H 5700 2700 50 0001 C CNN +F 3 "" H 5700 2700 50 0001 C CNN + 1 5700 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 5600 2700 5700 2700 +$Comp +L power:VDD #PWR05 +U 1 1 5B28CD78 +P 8250 1800 +F 0 "#PWR05" H 8250 1650 50 0001 C CNN +F 1 "VDD" H 8267 1973 50 0000 C CNN +F 2 "" H 8250 1800 50 0001 C CNN +F 3 "" H 8250 1800 50 0001 C CNN + 1 8250 1800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR06 +U 1 1 5B28CEDD +P 8250 2750 +F 0 "#PWR06" H 8250 2500 50 0001 C CNN +F 1 "GND" H 8255 2577 50 0000 C CNN +F 2 "" H 8250 2750 50 0001 C CNN +F 3 "" H 8250 2750 50 0001 C CNN + 1 8250 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8250 2000 8250 1800 +Wire Wire Line + 8250 2600 8250 2750 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28D041 +P 8250 2300 +F 0 "V3" H 8478 2346 50 0000 L CNN +F 1 "VSOURCE" H 8478 2255 50 0000 L CNN +F 2 "" H 8250 2300 50 0001 C CNN +F 3 "" H 8250 2300 50 0001 C CNN +F 4 "V" H 8250 2300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 8250 2300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8250 2300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8250 2300 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B28D0EC +P 6350 2950 +F 0 "R1" V 6557 2950 50 0000 C CNN +F 1 "10meg" V 6466 2950 50 0000 C CNN +F 2 "" V 6280 2950 50 0001 C CNN +F 3 "~" H 6350 2950 50 0001 C CNN + 1 6350 2950 + 0 -1 -1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28D219 +P 6750 3100 +F 0 "#PWR04" H 6750 2850 50 0001 C CNN +F 1 "GND" H 6755 2927 50 0000 C CNN +F 2 "" H 6750 3100 50 0001 C CNN +F 3 "" H 6750 3100 50 0001 C CNN + 1 6750 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 2950 6050 2950 +Wire Wire Line + 6500 2950 6750 2950 +Wire Wire Line + 6750 2950 6750 3100 +Text GLabel 6050 2850 0 50 Output ~ 0 +out +Wire Wire Line + 6050 2850 6050 2950 +Connection ~ 6050 2950 +Wire Wire Line + 6050 2950 6200 2950 +Text GLabel 3150 2250 0 50 Input ~ 0 +a +Text GLabel 3850 2750 0 50 Input ~ 0 +b +Wire Wire Line + 3150 2250 3150 2450 +Connection ~ 3150 2450 +Wire Wire Line + 3150 2450 2950 2450 +Wire Wire Line + 3850 2750 3850 2850 +Connection ~ 3850 2850 +Wire Wire Line + 3850 2850 4800 2850 +Text Notes 6500 5000 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/digital ciruits/or_sub/or_sub.cir b/digital ciruits/or_sub/or_sub.cir new file mode 100644 index 0000000..4724833 --- /dev/null +++ b/digital ciruits/or_sub/or_sub.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +.include "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib" +X1 a b out VDD OR +V1 a GND dc 0 pulse(0 3.3 0 0 0 50m 100m) +V2 b GND dc 0 pulse(0 3.3 50m 0 0 50m 100m) +V3 VDD GND dc 3.3 +R1 out GND 10meg +.tran .25m 30m +.end diff --git a/digital ciruits/or_sub/or_sub.kicad_pcb b/digital ciruits/or_sub/or_sub.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/or_sub/or_sub.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/or_sub/or_sub.pro b/digital ciruits/or_sub/or_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/or_sub/or_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/or_sub/or_sub.sch b/digital ciruits/or_sub/or_sub.sch new file mode 100644 index 0000000..cc5bcaf --- /dev/null +++ b/digital ciruits/or_sub/or_sub.sch @@ -0,0 +1,202 @@ +EESchema Schematic File Version 4 +LIBS:or_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L or_sub-rescue:OR-Logic_Gates X1 +U 1 1 5B28CA7D +P 5200 2800 +F 0 "X1" H 5200 3125 50 0000 C CNN +F 1 "OR" H 5200 3034 50 0000 C CNN +F 2 "" H 5200 2800 50 0001 C CNN +F 3 "" H 5200 2800 50 0001 C CNN +F 4 "X" H 5200 2800 50 0001 C CNN "Spice_Primitive" +F 5 "OR" H 5200 2800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5200 2800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib" H 5200 2800 50 0001 C CNN "Spice_Lib_File" + 1 5200 2800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28CADB +P 2950 2950 +F 0 "V1" H 3178 2996 50 0000 L CNN +F 1 "VSOURCE" H 3178 2905 50 0000 L CNN +F 2 "" H 2950 2950 50 0001 C CNN +F 3 "" H 2950 2950 50 0001 C CNN +F 4 "V" H 2950 2950 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 2950 2950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2950 2950 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2950 2950 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28CB19 +P 3600 3150 +F 0 "V2" H 3828 3196 50 0000 L CNN +F 1 "VSOURCE" H 3828 3105 50 0000 L CNN +F 2 "" H 3600 3150 50 0001 C CNN +F 3 "" H 3600 3150 50 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CNN +F 3 "" H 8250 2300 50 0001 C CNN +F 4 "V" H 8250 2300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 8250 2300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8250 2300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 8250 2300 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B28D0EC +P 6350 2950 +F 0 "R1" V 6557 2950 50 0000 C CNN +F 1 "10meg" V 6466 2950 50 0000 C CNN +F 2 "" V 6280 2950 50 0001 C CNN +F 3 "~" H 6350 2950 50 0001 C CNN + 1 6350 2950 + 0 -1 -1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28D219 +P 6750 3100 +F 0 "#PWR04" H 6750 2850 50 0001 C CNN +F 1 "GND" H 6755 2927 50 0000 C CNN +F 2 "" H 6750 3100 50 0001 C CNN +F 3 "" H 6750 3100 50 0001 C CNN + 1 6750 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 2950 6050 2950 +Wire Wire Line + 6500 2950 6750 2950 +Wire Wire Line + 6750 2950 6750 3100 +Text GLabel 6050 2850 0 50 Output ~ 0 +out +Wire Wire Line + 6050 2850 6050 2950 +Connection ~ 6050 2950 +Wire Wire Line + 6050 2950 6200 2950 +Text GLabel 3150 2250 0 50 Input ~ 0 +a +Text GLabel 3850 2750 0 50 Input ~ 0 +b +Wire Wire Line + 3150 2250 3150 2450 +Connection ~ 3150 2450 +Wire Wire Line + 3150 2450 2950 2450 +Wire Wire Line + 3850 2750 3850 2850 +Connection ~ 3850 2850 +Wire Wire Line + 3850 2850 4800 2850 +Text Notes 6500 5000 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/digital ciruits/or_sub/sym-lib-table b/digital ciruits/or_sub/sym-lib-table new file mode 100644 index 0000000..905d1e2 --- /dev/null +++ b/digital ciruits/or_sub/sym-lib-table @@ -0,0 +1,5 @@ +(sym_lib_table + (lib (name basic_logicgates)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/or_sub/basic_logicgates.lib)(options "")(descr "")) + (lib (name Logic_Gates)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/or_sub/Logic_Gates.lib)(options "")(descr "")) + (lib (name or_sub-rescue)(type Legacy)(uri ${KIPRJMOD}/or_sub-rescue.lib)(options "")(descr "")) +) diff --git a/digital ciruits/xor_sub/b3v33check.log b/digital ciruits/xor_sub/b3v33check.log new file mode 100644 index 0000000..27ec4ed --- /dev/null +++ b/digital ciruits/xor_sub/b3v33check.log @@ -0,0 +1,4 @@ +BSIM3v3.3.0 Parameter Checking.
+Model = mpmos
+Warning: Pd = 0 is less than W.
+Warning: Ps = 0 is less than W.
diff --git a/digital ciruits/xor_sub/sym-lib-table b/digital ciruits/xor_sub/sym-lib-table new file mode 100644 index 0000000..a5c52cc --- /dev/null +++ b/digital ciruits/xor_sub/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table
+ (lib (name Logic_Gates)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/xor_sub/Logic_Gates.lib)(options "")(descr ""))
+ (lib (name xor_sub-rescue)(type Legacy)(uri ${KIPRJMOD}/xor_sub-rescue.lib)(options "")(descr ""))
+)
diff --git a/digital ciruits/xor_sub/xor_sub-cache.lib b/digital ciruits/xor_sub/xor_sub-cache.lib new file mode 100644 index 0000000..cfbf049 --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub-cache.lib @@ -0,0 +1,81 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# xor_sub-rescue:XOR-Logic_Gates +# +DEF xor_sub-rescue:XOR-Logic_Gates X 0 40 Y Y 1 F N +F0 "X" 0 50 50 H V C CNN +F1 "xor_sub-rescue:XOR-Logic_Gates" 0 -50 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -150 100 150 -100 0 1 0 N +X A 1 -350 50 200 R 50 39 1 1 I +X B 2 -350 -50 200 R 50 39 1 1 I +X Out 3 350 -50 200 L 50 39 1 1 O +X VDD 4 350 50 200 L 50 39 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/xor_sub/xor_sub-rescue.dcm b/digital ciruits/xor_sub/xor_sub-rescue.dcm new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/xor_sub/xor_sub-rescue.lib b/digital ciruits/xor_sub/xor_sub-rescue.lib new file mode 100644 index 0000000..ce7fe20 --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub-rescue.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# XOR-Logic_Gates
+#
+DEF XOR-Logic_Gates X 0 40 Y Y 1 F N
+F0 "X" 0 50 50 H V C CNN
+F1 "XOR-Logic_Gates" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -150 100 150 -100 0 1 0 N
+X A 1 -350 50 200 R 50 39 1 1 I
+X B 2 -350 -50 200 R 50 39 1 1 I
+X Out 3 350 -50 200 L 50 39 1 1 O
+X VDD 4 350 50 200 L 50 39 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/xor_sub/xor_sub.bak b/digital ciruits/xor_sub/xor_sub.bak new file mode 100644 index 0000000..a16f1e8 --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.bak @@ -0,0 +1,202 @@ +EESchema Schematic File Version 4
+LIBS:xor_sub-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L xor_sub-rescue:XOR-Logic_Gates X1
+U 1 1 5B29C95E
+P 5350 3150
+F 0 "X1" H 5350 3425 50 0000 C CNN
+F 1 "XOR" H 5350 3334 50 0000 C CNN
+F 2 "" H 5350 3150 50 0001 C CNN
+F 3 "" H 5350 3150 50 0001 C CNN
+F 4 "X" H 5350 3150 50 0001 C CNN "Spice_Primitive"
+F 5 "XOR" H 5350 3150 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 5350 3150 50 0001 C CNN "Spice_Netlist_Enabled"
+F 7 "C:\\Users\\Mind\\Downloads\\Kicad\\new_file\\libs\\spice_models.lib" H 5350 3150 50 0001 C CNN "Spice_Lib_File"
+ 1 5350 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B29C9FA
+P 3800 3300
+F 0 "V1" H 4028 3346 50 0000 L CNN
+F 1 "VSOURCE" H 4028 3255 50 0000 L CNN
+F 2 "" H 3800 3300 50 0001 C CNN
+F 3 "" H 3800 3300 50 0001 C CNN
+F 4 "V" H 3800 3300 50 0001 C CNN "Spice_Primitive"
+F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 3800 3300 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 3800 3300 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 3800 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L pspice:VSOURCE V3
+U 1 1 5B29CA60
+P 8400 3400
+F 0 "V3" H 8628 3446 50 0000 L CNN
+F 1 "VSOURCE" H 8628 3355 50 0000 L CNN
+F 2 "" H 8400 3400 50 0001 C CNN
+F 3 "" H 8400 3400 50 0001 C CNN
+F 4 "V" H 8400 3400 50 0001 C CNN "Spice_Primitive"
+F 5 "dc 3.3" H 8400 3400 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 8400 3400 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 8400 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L pspice:VSOURCE V2
+U 1 1 5B29CAF4
+P 4500 3650
+F 0 "V2" H 4728 3696 50 0000 L CNN
+F 1 "VSOURCE" H 4728 3605 50 0000 L CNN
+F 2 "" H 4500 3650 50 0001 C CNN
+F 3 "" H 4500 3650 50 0001 C CNN
+F 4 "V" H 4500 3650 50 0001 C CNN "Spice_Primitive"
+F 5 "dc 0 pulse(0 3.3 100m 0 0 50m 100m)" H 4500 3650 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 4500 3650 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 4500 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B29CB8E
+P 6250 3200
+F 0 "R1" V 6043 3200 50 0000 C CNN
+F 1 "10meg" V 6134 3200 50 0000 C CNN
+F 2 "" V 6180 3200 50 0001 C CNN
+F 3 "~" H 6250 3200 50 0001 C CNN
+ 1 6250 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L power:GND #PWR01
+U 1 1 5B29CC31
+P 3800 3800
+F 0 "#PWR01" H 3800 3550 50 0001 C CNN
+F 1 "GND" H 3805 3627 50 0000 C CNN
+F 2 "" H 3800 3800 50 0001 C CNN
+F 3 "" H 3800 3800 50 0001 C CNN
+ 1 3800 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #PWR02
+U 1 1 5B29CC70
+P 4500 4150
+F 0 "#PWR02" H 4500 3900 50 0001 C CNN
+F 1 "GND" H 4505 3977 50 0000 C CNN
+F 2 "" H 4500 4150 50 0001 C CNN
+F 3 "" H 4500 4150 50 0001 C CNN
+ 1 4500 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #PWR04
+U 1 1 5B29CC85
+P 6650 3400
+F 0 "#PWR04" H 6650 3150 50 0001 C CNN
+F 1 "GND" H 6655 3227 50 0000 C CNN
+F 2 "" H 6650 3400 50 0001 C CNN
+F 3 "" H 6650 3400 50 0001 C CNN
+ 1 6650 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5700 3200 6050 3200
+Wire Wire Line
+ 6400 3200 6650 3200
+Wire Wire Line
+ 6650 3200 6650 3400
+Wire Wire Line
+ 3800 3000 4100 3000
+Wire Wire Line
+ 5000 3000 5000 3100
+Wire Wire Line
+ 4500 3350 4500 3200
+Wire Wire Line
+ 4500 3200 4700 3200
+$Comp
+L power:VDD #PWR03
+U 1 1 5B29CD7F
+P 5800 3050
+F 0 "#PWR03" H 5800 2900 50 0001 C CNN
+F 1 "VDD" H 5817 3223 50 0000 C CNN
+F 2 "" H 5800 3050 50 0001 C CNN
+F 3 "" H 5800 3050 50 0001 C CNN
+ 1 5800 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:VDD #PWR05
+U 1 1 5B29CDB4
+P 8400 3050
+F 0 "#PWR05" H 8400 2900 50 0001 C CNN
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+F 2 "" H 8400 3050 50 0001 C CNN
+F 3 "" H 8400 3050 50 0001 C CNN
+ 1 8400 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #PWR06
+U 1 1 5B29CDF6
+P 8400 3750
+F 0 "#PWR06" H 8400 3500 50 0001 C CNN
+F 1 "GND" H 8405 3577 50 0000 C CNN
+F 2 "" H 8400 3750 50 0001 C CNN
+F 3 "" H 8400 3750 50 0001 C CNN
+ 1 8400 3750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8400 3100 8400 3050
+Wire Wire Line
+ 8400 3750 8400 3700
+Wire Wire Line
+ 5800 3050 5800 3100
+Wire Wire Line
+ 5800 3100 5700 3100
+Wire Wire Line
+ 3800 3800 3800 3600
+Wire Wire Line
+ 4500 4150 4500 3950
+Text GLabel 6050 2750 0 50 Output ~ 0
+out
+Wire Wire Line
+ 6050 2750 6050 3200
+Connection ~ 6050 3200
+Wire Wire Line
+ 6050 3200 6100 3200
+Text GLabel 4000 2650 0 50 Input ~ 0
+a
+Wire Wire Line
+ 4000 2650 4100 2650
+Wire Wire Line
+ 4100 2650 4100 3000
+Connection ~ 4100 3000
+Wire Wire Line
+ 4100 3000 5000 3000
+Text GLabel 4600 3100 0 50 Input ~ 0
+b
+Wire Wire Line
+ 4600 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 3200
+Connection ~ 4700 3200
+Wire Wire Line
+ 4700 3200 5000 3200
+$EndSCHEMATC
diff --git a/digital ciruits/xor_sub/xor_sub.bck b/digital ciruits/xor_sub/xor_sub.bck new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/xor_sub/xor_sub.cir b/digital ciruits/xor_sub/xor_sub.cir new file mode 100644 index 0000000..bae5429 --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +.include "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib" +X1 a b out VDD XOR +V1 a GND dc 0 pulse(0 3.3 0 0 0 50m 100m) +V3 VDD GND dc 3.3 +V2 b GND dc 0 pulse(0 3.3 100m 0 0 50m 100m) +R1 GND out 10meg +.tran .25m 30m +.end diff --git a/digital ciruits/xor_sub/xor_sub.dcm b/digital ciruits/xor_sub/xor_sub.dcm new file mode 100644 index 0000000..5dd71cb --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/xor_sub/xor_sub.kicad_pcb b/digital ciruits/xor_sub/xor_sub.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/xor_sub/xor_sub.lib b/digital ciruits/xor_sub/xor_sub.lib new file mode 100644 index 0000000..c0f9f17 --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.lib @@ -0,0 +1,23 @@ +EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# XOR
+#
+DEF XOR X 0 40 Y Y 1 F N
+F0 "X" 0 50 39 H V C CNN
+F1 "XOR" 0 0 39 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -150 -150 150 -150 0 1 0 N
+S -150 200 -150 -150 0 1 0 N
+S 150 200 -150 200 0 1 0 N
+S 150 200 150 -150 0 1 0 N
+X A 1 -350 100 200 R 50 28 1 1 I
+X B 2 -350 -100 200 R 50 28 1 1 I
+X Out 3 350 -50 200 L 50 28 1 1 O
+X VDD 4 350 100 200 L 50 28 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/xor_sub/xor_sub.pro b/digital ciruits/xor_sub/xor_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/xor_sub/xor_sub.sch b/digital ciruits/xor_sub/xor_sub.sch new file mode 100644 index 0000000..58aa1e5 --- /dev/null +++ b/digital ciruits/xor_sub/xor_sub.sch @@ -0,0 +1,204 @@ +EESchema Schematic File Version 4 +LIBS:xor_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L xor_sub-rescue:XOR-Logic_Gates X1 +U 1 1 5B29C95E +P 5350 3150 +F 0 "X1" H 5350 3425 50 0000 C CNN +F 1 "XOR" H 5350 3334 50 0000 C CNN +F 2 "" H 5350 3150 50 0001 C CNN +F 3 "" H 5350 3150 50 0001 C CNN +F 4 "X" H 5350 3150 50 0001 C CNN "Spice_Primitive" +F 5 "XOR" H 5350 3150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5350 3150 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib" H 5350 3150 50 0001 C CNN "Spice_Lib_File" + 1 5350 3150 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B29C9FA +P 3800 3300 +F 0 "V1" H 4028 3346 50 0000 L CNN +F 1 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