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Diffstat (limited to 'analog circuits/monostable/monostable.sch')
| -rw-r--r-- | analog circuits/monostable/monostable.sch | 332 |
1 files changed, 332 insertions, 0 deletions
diff --git a/analog circuits/monostable/monostable.sch b/analog circuits/monostable/monostable.sch new file mode 100644 index 0000000..6b12617 --- /dev/null +++ b/analog circuits/monostable/monostable.sch @@ -0,0 +1,332 @@ +EESchema Schematic File Version 4 +LIBS:monostable-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R2 +U 1 1 5B08D693 +P 3150 2900 +F 0 "R2" H 3220 2946 50 0000 L CNN +F 1 "10k" H 3220 2855 50 0000 L CNN +F 2 "" V 3080 2900 50 0001 C CNN +F 3 "~" H 3150 2900 50 0001 C CNN + 1 3150 2900 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B08D758 +P 3150 2050 +F 0 "R1" H 3220 2096 50 0000 L CNN +F 1 "240k" H 3220 2005 50 0000 L CNN +F 2 "" V 3080 2050 50 0001 C CNN +F 3 "~" H 3150 2050 50 0001 C CNN + 1 3150 2050 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B08D786 +P 5350 3100 +F 0 "R3" H 5420 3146 50 0000 L CNN +F 1 "150k" H 5420 3055 50 0000 L CNN +F 2 "" V 5280 3100 50 0001 C CNN +F 3 "~" H 5350 3100 50 0001 C CNN + 1 5350 3100 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B08D7C8 +P 6700 1850 +F 0 "C2" V 6448 1850 50 0000 C CNN +F 1 "0.03u" V 6539 1850 50 0000 C CNN +F 2 "" H 6738 1700 50 0001 C CNN +F 3 "~" H 6700 1850 50 0001 C CNN + 1 6700 1850 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B08D834 +P 5100 2550 +F 0 "C1" V 5250 2400 50 0000 C CNN +F 1 "0.0001u" V 5350 2450 50 0000 C CNN +F 2 "" H 5138 2400 50 0001 C CNN +F 3 "~" H 5100 2550 50 0001 C CNN + 1 5100 2550 + 0 1 1 0 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B08DAC0 +P 4400 3400 +F 0 "V2" H 4628 3446 50 0000 L CNN +F 1 "VSOURCE" H 4628 3355 50 0000 L CNN +F 2 "" H 4400 3400 50 0001 C CNN +F 3 "" H 4400 3400 50 0001 C CNN +F 4 "V" H 4400 3400 50 0001 C CNN "Spice_Primitive" +F 5 "pulse(0 3 100n 1n 1n 20n 100n)" H 4400 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4400 3400 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4400 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 2550 5350 2550 +$Comp +L power:GND #PWR01 +U 1 1 5B08DC9A +P 3150 3800 +F 0 "#PWR01" H 3150 3550 50 0001 C CNN +F 1 "GND" H 3155 3627 50 0000 C CNN +F 2 "" H 3150 3800 50 0001 C CNN +F 3 "" H 3150 3800 50 0001 C CNN + 1 3150 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG01 +U 1 1 5B08DCDA +P 3800 4000 +F 0 "#FLG01" H 3800 4075 50 0001 C CNN +F 1 "PWR_FLAG" H 3800 4174 50 0000 C CNN +F 2 "" H 3800 4000 50 0001 C CNN +F 3 "~" H 3800 4000 50 0001 C CNN + 1 3800 4000 + 1 0 0 -1 +$EndComp +$Comp +L Device:D D1 +U 1 1 5B08DD83 +P 5650 3100 +F 0 "D1" V 5604 3179 50 0000 L CNN +F 1 "D" V 5695 3179 50 0000 L CNN +F 2 "" H 5650 3100 50 0001 C CNN +F 3 "~" H 5650 3100 50 0001 C CNN +F 4 "D" H 5650 3100 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 5650 3100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5650 3100 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5650 3100 50 0001 C CNN "Spice_Node_Sequence" + 1 5650 3100 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 2950 5650 2550 +Connection ~ 5650 2550 +Wire Wire Line + 5650 2550 5750 2550 +Wire Wire Line + 5350 2950 5350 2550 +Connection ~ 5350 2550 +Wire Wire Line + 5350 2550 5650 2550 +Wire Wire Line + 4400 3700 4400 4000 +Wire Wire Line + 5350 3250 5350 3450 +Wire Wire Line + 5650 3250 5650 3450 +Wire Wire Line + 5650 3450 5350 3450 +Connection ~ 5350 3450 +Wire Wire Line + 5350 3450 5350 4000 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B08E08C +P 3150 1100 +F 0 "V1" H 3378 1146 50 0000 L CNN +F 1 "VSOURCE" H 3378 1055 50 0000 L CNN +F 2 "" H 3150 1100 50 0001 C CNN +F 3 "" H 3150 1100 50 0001 C CNN +F 4 "V" H 3150 1100 50 0001 C CNN "Spice_Primitive" +F 5 "dc 12" H 3150 1100 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3150 1100 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3150 1100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 4000 4400 4000 +Connection ~ 4400 4000 +Wire Wire Line + 3150 1900 3150 1400 +Wire Wire Line + 3150 2200 3150 2400 +Wire Wire Line + 4400 4000 5350 4000 +Wire Wire Line + 3150 3050 3150 3800 +Connection ~ 3150 2400 +Wire Wire Line + 3150 2400 3150 2750 +Wire Wire Line + 4400 2550 4400 3100 +$Comp +L power:GND #PWR02 +U 1 1 5B08EB5B +P 4000 800 +F 0 "#PWR02" H 4000 550 50 0001 C CNN +F 1 "GND" H 4005 627 50 0000 C CNN +F 2 "" H 4000 800 50 0001 C CNN +F 3 "" H 4000 800 50 0001 C CNN + 1 4000 800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 800 4000 800 +Wire Wire Line + 5750 1850 6550 1850 +Wire Wire Line + 6850 1850 7800 1850 +Wire Wire Line + 7800 1850 7800 2200 +Wire Wire Line + 7800 2450 6350 2450 +$Comp +L power:GND #PWR03 +U 1 1 5B08F52C +P 4400 4300 +F 0 "#PWR03" H 4400 4050 50 0001 C CNN +F 1 "GND" H 4405 4127 50 0000 C CNN +F 2 "" H 4400 4300 50 0001 C CNN +F 3 "" H 4400 4300 50 0001 C CNN + 1 4400 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4300 4400 4000 +Wire Wire Line + 3150 2400 5750 2400 +Text GLabel 8450 1850 0 50 Output ~ 0 +out +Wire Wire Line + 8450 1850 8450 2200 +Wire Wire Line + 8450 2200 7800 2200 +Connection ~ 7800 2200 +Wire Wire Line + 7800 2200 7800 2450 +Text GLabel 4450 2100 0 50 Input ~ 0 +in +Wire Wire Line + 4450 2100 4450 2550 +Wire Wire Line + 4400 2550 4450 2550 +Connection ~ 4450 2550 +Wire Wire Line + 4450 2550 4950 2550 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B331B7A +P 9400 1700 +F 0 "V3" H 9628 1746 50 0000 L CNN +F 1 "VSOURCE" H 9628 1655 50 0000 L CNN +F 2 "" H 9400 1700 50 0001 C CNN +F 3 "" H 9400 1700 50 0001 C CNN +F 4 "V" H 9400 1700 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 9400 1700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 9400 1700 50 0001 C CNN "Spice_Netlist_Enabled" + 1 9400 1700 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V4 +U 1 1 5B331BBD +P 9400 2600 +F 0 "V4" H 9628 2646 50 0000 L CNN +F 1 "VSOURCE" H 9628 2555 50 0000 L CNN +F 2 "" H 9400 2600 50 0001 C CNN +F 3 "" H 9400 2600 50 0001 C CNN +F 4 "V" H 9400 2600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 15" H 9400 2600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 9400 2600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 9400 2600 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR0101 +U 1 1 5B331C64 +P 9400 1400 +F 0 "#PWR0101" H 9400 1250 50 0001 C CNN +F 1 "VDD" H 9417 1573 50 0000 C CNN +F 2 "" H 9400 1400 50 0001 C CNN +F 3 "" H 9400 1400 50 0001 C CNN + 1 9400 1400 + 1 0 0 -1 +$EndComp +$Comp +L power:VSS #PWR0102 +U 1 1 5B331D28 +P 9750 3100 +F 0 "#PWR0102" H 9750 2950 50 0001 C CNN +F 1 "VSS" H 9767 3273 50 0000 C CNN +F 2 "" H 9750 3100 50 0001 C CNN +F 3 "" H 9750 3100 50 0001 C CNN + 1 9750 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 2900 9400 3100 +Wire Wire Line + 9400 3100 9750 3100 +$Comp +L power:GND #PWR0103 +U 1 1 5B332236 +P 9850 2250 +F 0 "#PWR0103" H 9850 2000 50 0001 C CNN +F 1 "GND" H 9855 2077 50 0000 C CNN +F 2 "" H 9850 2250 50 0001 C CNN +F 3 "" H 9850 2250 50 0001 C CNN + 1 9850 2250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 2300 9400 2250 +Wire Wire Line + 9850 2250 9400 2250 +Connection ~ 9400 2250 +Wire Wire Line + 9400 2250 9400 2000 +Wire Wire Line + 5750 1850 5750 2400 +Wire Wire Line + 6350 2450 6350 2600 +Wire Wire Line + 6350 2600 6500 2600 +Wire Wire Line + 6500 2600 6500 2850 +Wire Wire Line + 5900 2750 5900 2400 +Wire Wire Line + 5900 2400 5750 2400 +Connection ~ 5750 2400 +Wire Wire Line + 5750 2550 5750 2950 +Wire Wire Line + 5750 2950 5900 2950 +Text Notes 7750 4200 0 50 ~ 0 +.tran 15p 300n +$Comp +L Amplifier_Operational:AD8620 U1 +U 1 1 5B334902 +P 6200 2850 +F 0 "U1" H 6200 3217 50 0000 C CNN +F 1 "AD8620" H 6200 3126 50 0000 C CNN +F 2 "" H 6200 2850 50 0001 C CNN +F 3 "http://www.analog.com/media/en/technical-documentation/data-sheets/AD8610_8620.pdf" H 6200 2850 50 0001 C CNN + 1 6200 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC |