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path: root/digital ciruits/or_sub/or_sub.bak
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EESchema Schematic File Version 4
LIBS:or_sub-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L or_sub-rescue:OR-Logic_Gates X1
U 1 1 5B28CA7D
P 5200 2800
F 0 "X1" H 5200 3125 50  0000 C CNN
F 1 "OR" H 5200 3034 50  0000 C CNN
F 2 "" H 5200 2800 50  0001 C CNN
F 3 "" H 5200 2800 50  0001 C CNN
F 4 "X" H 5200 2800 50  0001 C CNN "Spice_Primitive"
F 5 "OR" H 5200 2800 50  0001 C CNN "Spice_Model"
F 6 "Y" H 5200 2800 50  0001 C CNN "Spice_Netlist_Enabled"
F 7 "/home/akshay/Desktop/digital ciruits/libs/fossee_spice_models.lib" H 5200 2800 50  0001 C CNN "Spice_Lib_File"
	1    5200 2800
	1    0    0    -1  
$EndComp
$Comp
L pspice:VSOURCE V1
U 1 1 5B28CADB
P 2950 2950
F 0 "V1" H 3178 2996 50  0000 L CNN
F 1 "VSOURCE" H 3178 2905 50  0000 L CNN
F 2 "" H 2950 2950 50  0001 C CNN
F 3 "" H 2950 2950 50  0001 C CNN
F 4 "V" H 2950 2950 50  0001 C CNN "Spice_Primitive"
F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 2950 2950 50  0001 C CNN "Spice_Model"
F 6 "Y" H 2950 2950 50  0001 C CNN "Spice_Netlist_Enabled"
	1    2950 2950
	1    0    0    -1  
$EndComp
$Comp
L pspice:VSOURCE V2
U 1 1 5B28CB19
P 3600 3150
F 0 "V2" H 3828 3196 50  0000 L CNN
F 1 "VSOURCE" H 3828 3105 50  0000 L CNN
F 2 "" H 3600 3150 50  0001 C CNN
F 3 "" H 3600 3150 50  0001 C CNN
F 4 "V" H 3600 3150 50  0001 C CNN "Spice_Primitive"
F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 3600 3150 50  0001 C CNN "Spice_Model"
F 6 "Y" H 3600 3150 50  0001 C CNN "Spice_Netlist_Enabled"
	1    3600 3150
	1    0    0    -1  
$EndComp
Wire Wire Line
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Wire Wire Line
	4800 2850 4800 2900
Wire Wire Line
	4800 2700 3250 2700
Wire Wire Line
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Wire Wire Line
	3250 2450 3150 2450
Wire Wire Line
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$Comp
L power:GND #PWR01
U 1 1 5B28CBA8
P 2950 3450
F 0 "#PWR01" H 2950 3200 50  0001 C CNN
F 1 "GND" H 2955 3277 50  0000 C CNN
F 2 "" H 2950 3450 50  0001 C CNN
F 3 "" H 2950 3450 50  0001 C CNN
	1    2950 3450
	1    0    0    -1  
$EndComp
$Comp
L power:GND #PWR02
U 1 1 5B28CBDE
P 3600 3650
F 0 "#PWR02" H 3600 3400 50  0001 C CNN
F 1 "GND" H 3605 3477 50  0000 C CNN
F 2 "" H 3600 3650 50  0001 C CNN
F 3 "" H 3600 3650 50  0001 C CNN
	1    3600 3650
	1    0    0    -1  
$EndComp
Wire Wire Line
	3600 3650 3600 3450
Wire Wire Line
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$Comp
L power:VDD #PWR03
U 1 1 5B28CCFB
P 5700 2700
F 0 "#PWR03" H 5700 2550 50  0001 C CNN
F 1 "VDD" V 5717 2828 50  0000 L CNN
F 2 "" H 5700 2700 50  0001 C CNN
F 3 "" H 5700 2700 50  0001 C CNN
	1    5700 2700
	0    1    1    0   
$EndComp
Wire Wire Line
	5600 2700 5700 2700
$Comp
L power:VDD #PWR05
U 1 1 5B28CD78
P 8250 1800
F 0 "#PWR05" H 8250 1650 50  0001 C CNN
F 1 "VDD" H 8267 1973 50  0000 C CNN
F 2 "" H 8250 1800 50  0001 C CNN
F 3 "" H 8250 1800 50  0001 C CNN
	1    8250 1800
	1    0    0    -1  
$EndComp
$Comp
L power:GND #PWR06
U 1 1 5B28CEDD
P 8250 2750
F 0 "#PWR06" H 8250 2500 50  0001 C CNN
F 1 "GND" H 8255 2577 50  0000 C CNN
F 2 "" H 8250 2750 50  0001 C CNN
F 3 "" H 8250 2750 50  0001 C CNN
	1    8250 2750
	1    0    0    -1  
$EndComp
Wire Wire Line
	8250 2000 8250 1800
Wire Wire Line
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$Comp
L pspice:VSOURCE V3
U 1 1 5B28D041
P 8250 2300
F 0 "V3" H 8478 2346 50  0000 L CNN
F 1 "VSOURCE" H 8478 2255 50  0000 L CNN
F 2 "" H 8250 2300 50  0001 C CNN
F 3 "" H 8250 2300 50  0001 C CNN
F 4 "V" H 8250 2300 50  0001 C CNN "Spice_Primitive"
F 5 "dc 3.3" H 8250 2300 50  0001 C CNN "Spice_Model"
F 6 "Y" H 8250 2300 50  0001 C CNN "Spice_Netlist_Enabled"
	1    8250 2300
	1    0    0    -1  
$EndComp
$Comp
L Device:R R1
U 1 1 5B28D0EC
P 6350 2950
F 0 "R1" V 6557 2950 50  0000 C CNN
F 1 "10meg" V 6466 2950 50  0000 C CNN
F 2 "" V 6280 2950 50  0001 C CNN
F 3 "~" H 6350 2950 50  0001 C CNN
	1    6350 2950
	0    -1   -1   0   
$EndComp
$Comp
L power:GND #PWR04
U 1 1 5B28D219
P 6750 3100
F 0 "#PWR04" H 6750 2850 50  0001 C CNN
F 1 "GND" H 6755 2927 50  0000 C CNN
F 2 "" H 6750 3100 50  0001 C CNN
F 3 "" H 6750 3100 50  0001 C CNN
	1    6750 3100
	1    0    0    -1  
$EndComp
Wire Wire Line
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Wire Wire Line
	6500 2950 6750 2950
Wire Wire Line
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Text GLabel 6050 2850 0    50   Output ~ 0
out
Wire Wire Line
	6050 2850 6050 2950
Connection ~ 6050 2950
Wire Wire Line
	6050 2950 6200 2950
Text GLabel 3150 2250 0    50   Input ~ 0
a
Text GLabel 3850 2750 0    50   Input ~ 0
b
Wire Wire Line
	3150 2250 3150 2450
Connection ~ 3150 2450
Wire Wire Line
	3150 2450 2950 2450
Wire Wire Line
	3850 2750 3850 2850
Connection ~ 3850 2850
Wire Wire Line
	3850 2850 4800 2850
Text Notes 6500 5000 0    50   ~ 0
.tran .25m 30m
$EndSCHEMATC