1 files changed, 83 insertions, 0 deletions
diff --git a/analog circuits/RL/RL.bak b/analog circuits/RL/RL.bak
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+EESchema Schematic File Version 4
+LIBS:RL-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+Title ""
+Date ""
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+$EndDescr
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+F 5 "pwl(0 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3550 3700 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 3550 3700 50  0001 C CNN "Spice_Netlist_Enabled"
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+$EndComp
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+F 3 "~" H 6500 3700 50  0001 C CNN
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+$EndComp
+$Comp
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