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path: root/analog circuits/BJT_frequency_response/BJT_frequency_response-cache.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device:C
#
DEF Device:C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device:C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device:R
#
DEF Device:R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device:R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Transistor_BJT:BC547
#
DEF Transistor_BJT:BC547 Q 0 0 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_BJT:BC547" 200 0 50 H V L CNN
F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
ALIAS BC546 BC548 BC549 BC550 BC337 BC338
$FPLIST
 TO?92*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X C 1 100 200 100 D 50 50 1 1 P
X B 2 -200 0 200 R 50 50 1 1 I
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power:GND
#
DEF power:GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power:GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# pspice:VSOURCE
#
DEF pspice:VSOURCE V 0 40 Y Y 1 F N
F0 "V" -250 300 50 H V C CNN
F1 "pspice:VSOURCE" 0 0 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 0 200 0 1 0 N
T 0 -320 -10 50 0 0 1 V Normal 0 C C
P 2 0 1 0 -250 -250 -250 150 F
P 3 0 1 0 -300 150 -250 250 -200 150 F
X E1 1 0 300 100 D 50 50 1 1 I
X E2 2 0 -300 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library