blob: 28aadfe72ee93c0ff6e4b6051ec8a903cf446b13 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device:R
#
DEF Device:R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device:R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power:GND
#
DEF power:GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power:GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# pspice:VSOURCE
#
DEF pspice:VSOURCE V 0 40 Y Y 1 F N
F0 "V" -250 300 50 H V C CNN
F1 "pspice:VSOURCE" 0 0 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 0 200 0 1 0 N
T 0 -320 -10 50 0 0 1 V Normal 0 C C
P 2 0 1 0 -250 -250 -250 150 F
P 3 0 1 0 -300 150 -250 250 -200 150 F
X E1 1 0 300 100 D 50 50 1 1 I
X E2 2 0 -300 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# sim_logic:CMOS_NAND
#
DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N
F0 "X" 0 -400 50 H V C CNN
F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
A 200 0 200 -899 899 0 1 0 N 200 -200 200 200
P 4 0 1 0 200 200 0 200 0 -200 200 -200 N
X A A -200 100 200 R 50 50 1 1 I
X B B -200 -100 200 R 50 50 1 1 I
X Out Out 600 0 200 L 50 50 1 1 O I
X VDD VDD 200 400 200 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
#End Library
|
