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Diffstat (limited to 'analog circuits/ac to dc converter/ac to dc converter.sch')
| -rw-r--r-- | analog circuits/ac to dc converter/ac to dc converter.sch | 290 |
1 files changed, 290 insertions, 0 deletions
diff --git a/analog circuits/ac to dc converter/ac to dc converter.sch b/analog circuits/ac to dc converter/ac to dc converter.sch new file mode 100644 index 0000000..85840c3 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.sch @@ -0,0 +1,290 @@ +EESchema Schematic File Version 4 +LIBS:ac to dc converter-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0CF0CE +P 2750 4550 +F 0 "V1" H 2978 4596 50 0000 L CNN +F 1 "VSOURCE" H 2978 4505 50 0000 L CNN +F 2 "" H 2750 4550 50 0001 C CNN +F 3 "" H 2750 4550 50 0001 C CNN +F 4 "V" H 2750 4550 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 250)" H 2750 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2750 4550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2750 4550 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0CF1A2 +P 3950 3600 +F 0 "R1" V 3743 3600 50 0000 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#PWR0101 +U 1 1 5B0D3840 +P 7450 5550 +F 0 "#PWR0101" H 7450 5300 50 0001 C CNN +F 1 "GND" H 7455 5377 50 0000 C CNN +F 2 "" H 7450 5550 50 0001 C CNN +F 3 "" H 7450 5550 50 0001 C CNN + 1 7450 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 5550 7450 5300 +Connection ~ 7450 5300 +Wire Wire Line + 7450 5300 7150 5300 +$Comp +L Device:D_Zener D5 +U 1 1 5B0D4B1F +P 8400 5150 +F 0 "D5" V 8354 5229 50 0000 L CNN +F 1 "D_Zener" V 8445 5229 50 0000 L CNN +F 2 "" H 8400 5150 50 0001 C CNN +F 3 "~" H 8400 5150 50 0001 C CNN +F 4 "D" H 8400 5150 50 0001 C CNN "Spice_Primitive" +F 5 "D1N750" H 8400 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8400 5150 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" H 8400 5150 50 0001 C CNN "Spice_Lib_File" + 1 8400 5150 + 0 1 1 0 +$EndComp +Text GLabel 7050 4050 0 50 Output ~ 0 +vd +Wire Wire Line + 7050 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5500 4700 + 1 0 0 -1 +$EndComp +Text Notes 8450 5800 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC |