diff options
| author | matt | 2006-08-16 03:49:35 +0000 |
|---|---|---|
| committer | matt | 2006-08-16 03:49:35 +0000 |
| commit | 91387b113c5fce022b74c85569c6f10fdf53b6f3 (patch) | |
| tree | 48afc9264f4b5c786b34c7d7ce13ee99295e6d50 /usrp-hw | |
| parent | ef5fd2df34e16a56c664d0ffeb04d1c0b426950f (diff) | |
| download | gnuradio-91387b113c5fce022b74c85569c6f10fdf53b6f3.tar.gz gnuradio-91387b113c5fce022b74c85569c6f10fdf53b6f3.tar.bz2 gnuradio-91387b113c5fce022b74c85569c6f10fdf53b6f3.zip | |
first checkin of usrp-hw
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3293 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp-hw')
160 files changed, 25076 insertions, 0 deletions
diff --git a/usrp-hw/ChangeLog b/usrp-hw/ChangeLog new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/usrp-hw/ChangeLog diff --git a/usrp-hw/basic-dboard/ChangeLog b/usrp-hw/basic-dboard/ChangeLog new file mode 100644 index 000000000..15f6f09f9 --- /dev/null +++ b/usrp-hw/basic-dboard/ChangeLog @@ -0,0 +1,25 @@ +2004-12-29 Matt Ettus <matt@ettus.com> + + * txmod.pcb, rxmod.pcb : + - Enlarged logic analyzer pins + - Added lots of silkscreen text + - Moved txmod mounting hole to match MBoard + +2004-11-05 Matt Ettus <matt@ettus.com> + + * txmod.pcb, rxmod.pcb : + - Enlarged and rerouted to fit the final USRP + +2004-10-08 Matt Ettus <matt@ettus.com> + + * txmod.sch : + - Removed net SIGDEL and SIGDEL_FILT + - Filtering performed on mboard, so removing C38, C39, R30, R31 + - Tool changed format a little on Text items + + * rxmod.sch : + - Removed SIGDEL and SIGDEL_FILT + - Removed R1, R2, C20, C21 for same reason as above + - Tool changed format a little on Text items + + * NB: Still need to make RX and TX connectors match diff --git a/usrp-hw/basic-dboard/gnetlistrc b/usrp-hw/basic-dboard/gnetlistrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/basic-dboard/gnetlistrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/basic-dboard/gschemrc b/usrp-hw/basic-dboard/gschemrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/basic-dboard/gschemrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/basic-dboard/netlist_cmd b/usrp-hw/basic-dboard/netlist_cmd new file mode 100755 index 000000000..20d39527c --- /dev/null +++ b/usrp-hw/basic-dboard/netlist_cmd @@ -0,0 +1,6 @@ +gsch2pcb rxmod.prj +gnetlist -g partslist3 -o rxmod.bom rxmod.sch + +gsch2pcb txmod.prj +gnetlist -g partslist3 -o txmod.bom txmod.sch + diff --git a/usrp-hw/basic-dboard/rxmod.pcb b/usrp-hw/basic-dboard/rxmod.pcb new file mode 100644 index 000000000..ac9fb286c --- /dev/null +++ b/usrp-hw/basic-dboard/rxmod.pcb @@ -0,0 +1,2567 @@ +# release: pcb-bin 1.99p +# date: Thu Dec 30 15:47:51 2004 +# user: matt (Matt Ettus) +# host: localhost.localdomain + +PCB["RX Daughterboard" 275000 250000] + +Grid[1000.00000000 0 0 1] +Cursor[92000 185000 -2.865306] +Thermal[0.500000] +DRC[699 400 800 800] +Flags(0x0000000000001ad8) +Groups("1,s:4,c:2:3:5,6,7,8:") +Styles["Signal,1000,4000,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,800,3600,2000,1000"] + +Symbol[' ' 1800] +( +) +Symbol['!' 1200] +( + SymbolLine[0 3500 0 4000 800] + SymbolLine[0 0 0 2500 800] +) +Symbol['"' 1200] +( + SymbolLine[0 0 0 1000 800] + SymbolLine[1000 0 1000 1000 800] +) +Symbol['#' 1200] +( + SymbolLine[0 2500 2000 2500 800] + SymbolLine[0 1500 2000 1500 800] + SymbolLine[1500 1000 1500 3000 800] + SymbolLine[500 1000 500 3000 800] +) +Symbol['$' 1200] +( + SymbolLine[1500 500 2000 1000 800] + SymbolLine[500 500 1500 500 800] + SymbolLine[0 1000 500 500 800] + SymbolLine[0 1000 0 1500 800] + SymbolLine[0 1500 500 2000 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[2000 2500 2000 3000 800] + SymbolLine[1500 3500 2000 3000 800] + SymbolLine[500 3500 1500 3500 800] + SymbolLine[0 3000 500 3500 800] + SymbolLine[1000 0 1000 4000 800] +) +Symbol['%' 1200] +( + SymbolLine[0 500 0 1000 800] + SymbolLine[0 500 500 0 800] + SymbolLine[500 0 1000 0 800] + SymbolLine[1000 0 1500 500 800] + SymbolLine[1500 500 1500 1000 800] + SymbolLine[1000 1500 1500 1000 800] + SymbolLine[500 1500 1000 1500 800] + SymbolLine[0 1000 500 1500 800] + SymbolLine[0 4000 4000 0 800] + SymbolLine[3500 4000 4000 3500 800] + SymbolLine[4000 3000 4000 3500 800] + SymbolLine[3500 2500 4000 3000 800] + SymbolLine[3000 2500 3500 2500 800] + SymbolLine[2500 3000 3000 2500 800] + SymbolLine[2500 3000 2500 3500 800] + SymbolLine[2500 3500 3000 4000 800] + SymbolLine[3000 4000 3500 4000 800] +) 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800] + SymbolLine[500 3500 1000 4000 800] +) +Symbol['|' 1200] +( + SymbolLine[0 0 0 4000 800] +) +Symbol['}' 1200] +( + SymbolLine[0 0 500 500 800] + SymbolLine[500 500 500 1500 800] + SymbolLine[500 1500 1000 2000 800] + SymbolLine[500 2500 1000 2000 800] + SymbolLine[500 2500 500 3500 800] + SymbolLine[0 4000 500 3500 800] +) +Symbol['~' 1200] +( + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 1000 2000 800] + SymbolLine[1000 2000 1500 2500 800] + SymbolLine[1500 2500 2000 2500 800] + SymbolLine[2000 2500 2500 2000 800] +) +Via[15000 235000 13200 2000 11000 12800 "" 0x0200000a] +Via[92500 132000 4000 2000 0 2000 "" 0x02000002] +Via[260000 15000 13200 2000 11000 12800 "" 0x0000000a] +Via[260000 235000 13200 2000 11000 12800 "" 0x0200000a] +Via[225500 85000 4000 2000 0 2000 "" 0x02000002] +Via[209000 83500 4000 2000 0 2000 "" 0x02000002] +Via[170000 85500 4000 2000 0 2000 "" 0x02000002] +Via[180000 77000 4000 2000 0 2000 "" 0x02000002] +Via[204500 174000 4000 2000 0 2000 "" 0x02000002] +Via[202500 120500 4000 2000 0 2000 "" 0x02000002] +Via[106000 123000 4000 2000 0 2000 "" 0x02000082] +Via[141499 139901 4000 2000 0 2000 "" 0x02000082] +Via[165500 79000 4000 2000 0 2000 "" 0x02020002] +Via[156792 122699 4000 2000 0 2000 "" 0x02000082] +Via[159900 135400 4000 2000 0 2000 "" 0x02000082] +Via[123500 127000 4000 2000 0 2000 "" 0x02000002] +Via[99500 141000 4000 2000 0 2000 "" 0x02000002] +Via[109500 127000 4000 2000 0 2000 "" 0x02000002] +Via[192000 156500 4000 2000 0 2000 "" 0x02000002] +Via[55000 55000 13200 2000 11000 12800 "" 0x0200000a] +Via[141499 133398 4000 2000 0 2000 "" 0x02000082] +Via[76000 179500 6000 2000 0 2800 "" 0x02000002] +Via[118286 190300 4000 2000 0 2000 "" 0x02020002] +Via[87000 91500 4000 2000 0 2000 "" 0x02020002] +Via[85000 115000 4000 2000 0 2000 "" 0x02020002] +Via[196500 198000 4000 2000 0 2000 "" 0x02020002] +Via[223000 113000 4000 2000 0 2000 "" 0x02020002] +Via[173500 124000 4000 2000 0 2000 "" 0x02020002] +Via[236000 145000 4000 2000 0 2000 "" 0x02020002] +Via[173500 144500 4000 2000 0 2000 "" 0x02020002] +Via[145000 187000 6000 2000 0 2800 "" 0x02020002] +Via[50600 200900 6000 2000 0 2800 "" 0x02000002] +Via[36500 169500 6000 2000 0 2800 "" 0x02000002] +Via[47000 167500 6000 2000 0 2800 "" 0x02000002] +Via[59000 179000 6000 2000 0 2800 "" 0x02000002] +Via[93500 186000 4000 2000 0 2000 "" 0x02000002] +Via[97500 190500 4000 2000 0 2000 "" 0x02000042] + +Element[0x00000000 "0603" "R3" "50" 158000 210000 -14000 -2000 0 100 0x00000000] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" 0x00000100] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000000 "MINICIRCUITS_CD542" "T2" "unknown" 229500 180500 -21000 -2000 0 100 0x00000000] +( + Pad[-10000 13200 -10000 16700 6500 3000 6500 "1" "1" 0x00004100] + Pad[0 13200 0 16700 6500 3000 6500 "2" "2" 0x00004100] + Pad[10000 13200 10000 16700 6500 3000 6500 "3" "3" 0x00004100] + Pad[10000 -16700 10000 -13200 6500 3000 6500 "4" "4" 0x00000100] + Pad[0 -16700 0 -13200 6500 3000 6500 "5" "5" 0x00000100] + Pad[-10000 -16700 -10000 -13200 6500 3000 6500 "6" "6" 0x00000100] + ElementLine [-14200 -21000 -14200 -2500 1000] + ElementLine [-14200 2500 -14200 21000 1000] + ElementLine [-14200 -21000 14200 -21000 1000] + ElementLine [14200 -21000 14200 21000 1000] + ElementLine [-14200 21000 14200 21000 1000] + ElementArc [-14200 0 2500 2500 90 180 1000] + + ) + +Element[0x00000000 "0603" "C23" "10pF" 175500 154000 -4500 -5000 1 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000080 "PMC-REVERSE" "J2" "unknown" 94993 95811 -18000 9000 0 100 0x00000080] +( + Pin[-6693 7189 7200 2000 7200 5800 "" "1" 0x02004009] + Pin[128740 7189 7200 2000 7200 5800 "" "2" 0x02004009] + Pad[0 9900 0 19000 2400 1000 3400 "" "1" 0x00004080] + Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" 0x00000080] + Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" 0x00004080] + Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" 0x00004080] + Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" 0x00004080] + Pad[0 -4622 0 4478 2400 1000 3400 "" "2" 0x00000080] + Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" 0x00004080] + Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" 0x00000080] + Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" 0x00004080] + Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" 0x00000080] + Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" 0x00004080] + Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" 0x00000080] + Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" 0x00004080] + Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" 0x00000080] + Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" 0x00004080] + Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" 0x00000080] + Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" 0x00004080] + Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" 0x00000080] + Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" 0x00004080] + Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" 0x00000080] + Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" 0x00000080] + Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" 0x00000080] + Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" 0x00000080] + Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" 0x00000080] + Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" 0x00000080] + Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" 0x00000080] + Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" 0x00000080] + Pad[62992 -4622 62992 4478 2400 1000 3400 "" "34" 0x00000080] + Pad[66929 -4622 66929 4478 2400 1000 3400 "" "36" 0x00000080] + Pad[70866 -4622 70866 4478 2400 1000 3400 "" "38" 0x00000080] + Pad[74803 -4622 74803 4478 2400 1000 3400 "" "40" 0x00000080] + Pad[78740 -4622 78740 4478 2400 1000 3400 "" "42" 0x00000080] + Pad[82677 -4622 82677 4478 2400 1000 3400 "" "44" 0x00000080] + Pad[86614 -4622 86614 4478 2400 1000 3400 "" "46" 0x00000080] + Pad[90551 -4622 90551 4478 2400 1000 3400 "" "48" 0x00000080] + Pad[98425 -4622 98425 4478 2400 1000 3400 "" "52" 0x00000080] + Pad[94488 -4622 94488 4478 2400 1000 3400 "" "50" 0x00000080] + Pad[102362 -4622 102362 4478 2400 1000 3400 "" "54" 0x00000080] + Pad[106299 -4622 106299 4478 2400 1000 3400 "" "56" 0x00000080] + Pad[110236 -4622 110236 4478 2400 1000 3400 "" "58" 0x00000080] + Pad[114173 -4622 114173 4478 2400 1000 3400 "" "60" 0x00000080] + Pad[3937 -4622 3937 4478 2400 1000 3400 "" "4" 0x00000080] + Pad[43307 9900 43307 19000 2400 1000 3400 "" "23" 0x00004080] + Pad[47244 9900 47244 19000 2400 1000 3400 "" "25" 0x00004080] + Pad[51181 9900 51181 19000 2400 1000 3400 "" "27" 0x00004080] + Pad[55118 9900 55118 19000 2400 1000 3400 "" "29" 0x00004080] + Pad[59055 9900 59055 19000 2400 1000 3400 "" "31" 0x00004080] + Pad[62992 9900 62992 19000 2400 1000 3400 "" "33" 0x00004080] + Pad[66929 9900 66929 19000 2400 1000 3400 "" "35" 0x00004080] + Pad[70866 9900 70866 19000 2400 1000 3400 "" "37" 0x00004080] + Pad[74803 9900 74803 19000 2400 1000 3400 "" "39" 0x00004080] + Pad[78740 9900 78740 19000 2400 1000 3400 "" "41" 0x00004080] + Pad[82677 9900 82677 19000 2400 1000 3400 "" "43" 0x00004080] + Pad[86614 9900 86614 19000 2400 1000 3400 "" "45" 0x00004080] + Pad[90551 9900 90551 19000 2400 1000 3400 "" "47" 0x00004080] + Pad[94488 9900 94488 19000 2400 1000 3400 "" "49" 0x00004080] + Pad[98425 9900 98425 19000 2400 1000 3400 "" "51" 0x00004080] + Pad[102362 9900 102362 19000 2400 1000 3400 "" "53" 0x00004080] + Pad[106299 9900 106299 19000 2400 1000 3400 "" "55" 0x00004080] + Pad[110236 9900 110236 19000 2400 1000 3400 "" "57" 0x00004080] + Pad[114173 9900 114173 19000 2400 1000 3400 "" "59" 0x00004080] + Pad[118110 9900 118110 19000 2400 1000 3400 "" "61" 0x00004080] + Pad[122047 9900 122047 19000 2400 1000 3400 "" "63" 0x00004080] + Pad[118110 -4622 118110 4478 2400 1000 3400 "" "62" 0x00000080] + ElementLine [134000 -9000 134000 24000 1000] + ElementLine [-11000 24000 134000 24000 1000] + ElementLine [-11000 -9000 134000 -9000 1000] + ElementLine [-11000 -9000 -11000 24000 1000] + + ) + +Element[0x00000000 "0603" "R10" "50" 241000 152500 23500 4000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000000 "CONNECTOR-10-2" "J15" "unknown" 77000 40500 -17200 -13200 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x02004101] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" 0x02004001] + Pin[10000 0 6000 3000 6600 4000 "3" "3" 0x02004001] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" 0x02004001] + Pin[20000 0 6000 3000 6600 4000 "5" "5" 0x02004001] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" 0x02004001] + Pin[30000 0 6000 3000 6600 4000 "7" "7" 0x02004001] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" 0x02004001] + Pin[40000 0 6000 3000 6600 4000 "9" "9" 0x02004001] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" 0x02004001] + Pin[50000 0 6000 3000 6600 4000 "11" "11" 0x02004001] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" 0x02004001] + Pin[60000 0 6000 3000 6600 4000 "13" "13" 0x02004001] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" 0x02004001] + Pin[70000 0 6000 3000 6600 4000 "15" "15" 0x02004001] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" 0x02004001] + Pin[80000 0 6000 3000 6600 4000 "17" "17" 0x02004001] + Pin[80000 -10000 6000 3000 6600 4000 "18" "18" 0x02004001] + Pin[90000 0 6000 3000 6600 4000 "19" "19" 0x02004001] + Pin[90000 -10000 6000 3000 6600 4000 "20" "20" 0x02024001] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 95000 -15000 2000] + ElementLine [95000 -15000 95000 5000 2000] + ElementLine [-5000 5000 95000 5000 2000] + + ) + +Element[0x00000000 "CONNECTOR-5-2" "J17" "unknown" 183500 137500 49000 -12000 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x02004101] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" 0x02004001] + Pin[10000 0 6000 3000 6600 4000 "3" "3" 0x02004001] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" 0x02004001] + Pin[20000 0 6000 3000 6600 4000 "5" "5" 0x02004001] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" 0x02004001] + Pin[30000 0 6000 3000 6600 4000 "7" "7" 0x02004001] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" 0x02004001] + Pin[40000 0 6000 3000 6600 4000 "9" "9" 0x02024001] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" 0x02024001] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 45000 -15000 2000] + ElementLine [45000 -15000 45000 5000 2000] + ElementLine [-5000 5000 45000 5000 2000] + + ) + +Element[0x00000000 "SMA_VERT" "J18" "unknown" 160500 231500 -26000 -5000 0 100 0x00000000] +( + Pin[0 0 9000 3000 9000 6000 "1" "1" 0x02000001] + Pin[-10000 -10000 9000 3000 9000 6000 "2" "2" 0x02420001] + Pin[10000 -10000 9000 3000 9000 6000 "3" "3" 0x02420001] + Pin[-10000 10000 9000 3000 9000 6000 "4" "4" 0x02420001] + Pin[10000 10000 9000 3000 9000 6000 "5" "5" 0x02420001] + ElementLine [-16000 -16000 16000 -16000 1000] + ElementLine [-16000 -16000 -16000 16000 1000] + ElementLine [-16000 16000 16000 16000 1000] + ElementLine [16000 -16000 16000 16000 1000] + + ) + +Element[0x00000000 "SMA_VERT" "J19" "unknown" 223500 231500 -17000 -22000 0 100 0x00000000] +( + Pin[0 0 9000 3000 9000 6000 "1" "1" 0x02000001] + Pin[-10000 -10000 9000 3000 9000 6000 "2" "2" 0x02420001] + Pin[10000 -10000 9000 3000 9000 6000 "3" "3" 0x02420001] + Pin[-10000 10000 9000 3000 9000 6000 "4" "4" 0x02420001] + Pin[10000 10000 9000 3000 9000 6000 "5" "5" 0x02420001] + ElementLine [-16000 -16000 16000 -16000 1000] + ElementLine [-16000 -16000 -16000 16000 1000] + ElementLine [-16000 16000 16000 16000 1000] + ElementLine [16000 -16000 16000 16000 1000] + + ) + +Element[0x00000000 "0603" "R5" "50" 182500 154000 3500 5000 0 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000000 "0603" "R11" "50" 217500 152500 28000 4500 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000000 "0603" "C25" "10pF" 233500 152500 24500 4000 1 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000000 "0603" "C26" "10pF" 225000 152500 27000 4000 1 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000000 "0603" "R9" "50" 225500 210500 7000 -1500 0 100 0x00000000] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" 0x00000100] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element[0x00000000 "0603" "R8" "None" 200000 176500 -2500 -10500 0 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000000 "0603" "C24" ".1uF" 193000 187000 -7000 6000 0 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + + ) + +Element[0x00000000 "0603" "R6" "1K" 192500 176500 -3500 -10000 0 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000000 "0603" "R7" "1K" 200000 187000 500 6000 0 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000000 "MINICIRCUITS_CD542" "T1" "unknown" 170000 183000 -21000 -3000 0 100 0x00000000] +( + Pad[-10000 13200 -10000 16700 6500 3000 6500 "1" "1" 0x00004100] + Pad[0 13200 0 16700 6500 3000 6500 "2" "2" 0x00004100] + Pad[10000 13200 10000 16700 6500 3000 6500 "3" "3" 0x00004100] + Pad[10000 -16700 10000 -13200 6500 3000 6500 "4" "4" 0x00000100] + Pad[0 -16700 0 -13200 6500 3000 6500 "5" "5" 0x00000100] + Pad[-10000 -16700 -10000 -13200 6500 3000 6500 "6" "6" 0x00000100] + ElementLine [-14200 -21000 -14200 -2500 1000] + ElementLine [-14200 2500 -14200 21000 1000] + ElementLine [-14200 -21000 14200 -21000 1000] + ElementLine [14200 -21000 14200 21000 1000] + ElementLine [-14200 21000 14200 21000 1000] + ElementArc [-14200 0 2500 2500 90 180 1000] + + ) + +Element[0x00000000 "0603" "R4" "50" 159000 154000 -10500 1500 0 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000000 "0603" "C22" "10pF" 166000 154000 -1500 -5500 1 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000000 "0603" "R28" "0" 120000 184000 -2500 5500 0 100 0x00000000] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" 0x00000100] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J16" "unknown" 70500 162500 -16000 -9000 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x02004101] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" 0x02024001] + Pin[10000 0 6000 3000 6600 4000 "3" "3" 0x02004001] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" 0x02024001] + Pin[20000 0 6000 3000 6600 4000 "5" "5" 0x02004001] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" 0x02004001] + Pin[30000 0 6000 3000 6600 4000 "7" "7" 0x02004001] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" 0x02004001] + Pin[40000 0 6000 3000 6600 4000 "9" "9" 0x02004001] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" 0x02004001] + Pin[50000 0 6000 3000 6600 4000 "11" "11" 0x02004001] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" 0x02004001] + Pin[60000 0 6000 3000 6600 4000 "13" "13" 0x02004001] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" 0x02004001] + Pin[70000 0 6000 3000 6600 4000 "15" "15" 0x02004001] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" 0x02024001] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 75000 -15000 2000] + ElementLine [75000 -15000 75000 5000 2000] + ElementLine [-5000 5000 75000 5000 2000] + + ) + +Element[0x00000000 "SO8" "U1" "unknown" 88500 179000 18000 20000 0 100 0x00000000] +( + Pad[-1900 0 900 0 2000 3000 2000 "1" "1" 0x00000000] + Pad[-1900 5000 900 5000 2000 3000 2000 "2" "2" 0x00000100] + Pad[-1900 10000 900 10000 2000 3000 2000 "3" "3" 0x00000100] + Pad[-1900 15000 900 15000 2000 3000 2000 "4" "4" 0x00000100] + Pad[18500 15000 21300 15000 2000 3000 2000 "5" "5" 0x00004100] + Pad[18500 10000 21300 10000 2000 3000 2000 "6" "6" 0x00004100] + Pad[18500 5000 21300 5000 2000 3000 2000 "7" "7" 0x00004100] + Pad[18500 0 21300 0 2000 3000 2000 "8" "8" 0x00004100] + ElementLine [-2900 -2500 -2900 17500 1000] + ElementLine [-2900 17500 22300 17500 1000] + ElementLine [22300 -2500 22300 17500 1000] + ElementLine [7200 -2500 22300 -2500 1000] + ElementLine [-2900 -2500 12200 -2500 1000] + ElementArc [9700 -2500 2500 2500 0 180 1000] + + ) + +Element[0x00000080 "0603" "C490" "0.1uF" 121000 180500 -1500 -4300 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element[0x00000080 "0603" "C491" "0.1uF" 120500 197000 5000 5700 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element[0x00000080 "0603" "C475" "0.1uF" 103500 171500 -19000 1200 0 100 0x00000080] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000080 "0603" "C489" "0.1uF" 128000 187000 3500 6700 0 100 0x00000080] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000080 "SSOP16" "U410" "unknown" 109700 177200 -40700 12300 0 100 0x00000080] +( + Pad[-700 0 1500 0 1600 3000 2200 "1" "1" 0x00004080] + Pad[-700 2600 1500 2600 1600 3000 2200 "2" "2" 0x00004180] + Pad[-700 5100 1500 5100 1600 3000 2200 "3" "3" 0x00004180] + Pad[-700 7700 1500 7700 1600 3000 2200 "4" "4" 0x00004180] + Pad[-700 10300 1500 10300 1600 3000 2200 "5" "5" 0x00004180] + Pad[-700 12800 1500 12800 1600 3000 2200 "6" "6" 0x00004180] + Pad[-700 15400 1500 15400 1600 3000 2200 "7" "7" 0x00004180] + Pad[-700 17900 1500 17900 1600 3000 2200 "8" "8" 0x00004180] + Pad[-21900 18000 -19700 18000 1600 3000 2200 "9" "9" 0x00000180] + Pad[-21900 15400 -19700 15400 1600 3000 2200 "10" "10" 0x00000180] + Pad[-21900 12900 -19700 12900 1600 3000 2200 "11" "11" 0x00000180] + Pad[-21900 10300 -19700 10300 1600 3000 2200 "12" "12" 0x00000180] + Pad[-21900 7700 -19700 7700 1600 3000 2200 "13" "13" 0x00000180] + Pad[-21900 5200 -19700 5200 1600 3000 2200 "14" "14" 0x00000180] + Pad[-21900 2600 -19700 2600 1600 3000 2200 "15" "15" 0x00000180] + Pad[-21900 100 -19700 100 1600 3000 2200 "16" "16" 0x00000180] + ElementLine [2300 -1200 2300 19200 1000] + ElementLine [-22700 19200 2300 19200 1000] + ElementLine [-22700 -1200 -22700 19200 1000] + ElementLine [-22700 -1200 -9000 -1200 1000] + ElementLine [-11400 -1200 2300 -1200 1000] + ElementArc [-10200 -1200 1200 1200 0 180 1000] + + ) + +Element[0x00000080 "0603" "C492" "0.1uF" 37500 200500 -4500 -4800 0 100 0x00000080] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J24" "unknown" 10500 132500 19800 -3100 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x02000101] + Pin[10000 0 6000 3000 6600 4000 "2" "2" 0x02020001] + Pin[0 10000 6000 3000 6600 4000 "3" "3" 0x02000001] + Pin[10000 10000 6000 3000 6600 4000 "4" "4" 0x02020001] + Pin[0 20000 6000 3000 6600 4000 "5" "5" 0x02000001] + Pin[10000 20000 6000 3000 6600 4000 "6" "6" 0x02020001] + Pin[0 30000 6000 3000 6600 4000 "7" "7" 0x02000001] + Pin[10000 30000 6000 3000 6600 4000 "8" "8" 0x02020001] + Pin[0 40000 6000 3000 6600 4000 "9" "9" 0x02000001] + Pin[10000 40000 6000 3000 6600 4000 "10" "10" 0x02020001] + Pin[0 50000 6000 3000 6600 4000 "11" "11" 0x02000001] + Pin[10000 50000 6000 3000 6600 4000 "12" "12" 0x02020001] + Pin[0 60000 6000 3000 6600 4000 "13" "13" 0x02000001] + Pin[10000 60000 6000 3000 6600 4000 "14" "14" 0x02020001] + Pin[0 70000 6000 3000 6600 4000 "15" "15" 0x02000001] + Pin[10000 70000 6000 3000 6600 4000 "16" "16" 0x02020001] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 5000 5000 5000 1000] + ElementLine [-5000 -5000 15000 -5000 2000] + ElementLine [15000 -5000 15000 75000 2000] + ElementLine [-5000 75000 15000 75000 2000] + ElementLine [-5000 -5000 -5000 75000 2000] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J25" "unknown" 11000 15000 19200 -2600 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x02000101] + Pin[10000 0 6000 3000 6600 4000 "2" "2" 0x02020001] + Pin[0 10000 6000 3000 6600 4000 "3" "3" 0x02000001] + Pin[10000 10000 6000 3000 6600 4000 "4" "4" 0x02020001] + Pin[0 20000 6000 3000 6600 4000 "5" "5" 0x02000001] + Pin[10000 20000 6000 3000 6600 4000 "6" "6" 0x02020001] + Pin[0 30000 6000 3000 6600 4000 "7" "7" 0x02000001] + Pin[10000 30000 6000 3000 6600 4000 "8" "8" 0x02020001] + Pin[0 40000 6000 3000 6600 4000 "9" "9" 0x02000001] + Pin[10000 40000 6000 3000 6600 4000 "10" "10" 0x02020001] + Pin[0 50000 6000 3000 6600 4000 "11" "11" 0x02000001] + Pin[10000 50000 6000 3000 6600 4000 "12" "12" 0x02020001] + Pin[0 60000 6000 3000 6600 4000 "13" "13" 0x02000001] + Pin[10000 60000 6000 3000 6600 4000 "14" "14" 0x02020001] + Pin[0 70000 6000 3000 6600 4000 "15" "15" 0x02000001] + Pin[10000 70000 6000 3000 6600 4000 "16" "16" 0x02020001] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 5000 5000 5000 1000] + ElementLine [-5000 -5000 15000 -5000 2000] + ElementLine [15000 -5000 15000 75000 2000] + ElementLine [-5000 75000 15000 75000 2000] + ElementLine [-5000 -5000 -5000 75000 2000] + + ) + +Element[0x00000000 "DB9M" "J27" "unknown" 56500 208500 47300 13000 0 150 0x00000000] +( + Pin[0 -600 6000 3000 6600 3500 "1" "1" 0x02004101] + Pin[10800 -600 6000 3000 6600 3500 "2" "2" 0x02004001] + Pin[21600 -600 6000 3000 6600 3500 "3" "3" 0x02004001] + Pin[32400 -600 6000 3000 6600 3500 "4" "4" 0x02004001] + Pin[43200 -600 6000 3000 6600 3500 "5" "5" 0x02024001] + Pin[5400 10600 6000 3000 6600 3500 "6" "6" 0x02004001] + Pin[16200 10600 6000 3000 6600 3500 "7" "7" 0x02004001] + Pin[27000 10600 6000 3000 6600 3500 "8" "8" 0x02004001] + Pin[37800 10600 6000 3000 6600 3500 "9" "9" 0x02004001] + Pin[-27000 5000 13000 3000 13600 12500 "C1" "10" 0x02004001] + Pin[70200 5000 13000 3000 13600 12500 "C2" "11" 0x02004001] + ElementLine [37800 14600 37800 28000 2500] + ElementLine [27000 14600 27000 28000 2500] + ElementLine [16200 14600 16200 28000 2500] + ElementLine [5400 14600 5400 28000 2500] + ElementLine [43200 3400 43200 28000 2500] + ElementLine [32400 3400 32400 28000 2500] + ElementLine [21600 3400 21600 28000 2500] + ElementLine [10800 3400 10800 28000 2500] + ElementLine [0 3400 0 28000 2500] + ElementLine [-16000 38500 59200 38500 1500] + ElementLine [59200 28000 59200 38500 2500] + ElementLine [-16000 28000 59200 28000 2500] + ElementLine [-16000 28000 -16000 38500 2500] + ElementLine [64200 38500 64200 41500 1500] + ElementLine [76200 38500 76200 41500 1500] + ElementLine [-21000 38500 -21000 41500 1500] + ElementLine [-33000 38500 -33000 41500 1500] + ElementLine [-39000 41500 82200 41500 1500] + ElementLine [82200 38500 82200 41500 1500] + ElementLine [-39000 38500 82200 38500 1500] + ElementLine [-39000 38500 -39000 41500 1500] + + ) +Layer(1 "solder") +( + Line[197355 100289 197500 100616 1000 2000 0x00000000] + Line[212993 91311 213000 87500 1000 2000 0x00000000] + Line[213000 87500 216500 84000 1000 2000 0x00000000] + Line[216500 84000 224500 84000 1000 2000 0x00000000] + Line[224500 84000 225500 85000 1000 2000 0x00000000] + Line[208993 92811 209000 83500 1000 2000 0x00000000] + Line[189493 92311 189500 87000 1000 2000 0x00000000] + Line[189500 87000 184500 82000 1000 2000 0x00000000] + Line[184500 82000 173500 82000 1000 2000 0x00000000] + Line[173500 82000 170000 85500 1000 2000 0x00000000] + Line[186500 76500 180500 76500 1000 2000 0x00000000] + Line[193000 83000 192993 91811 1000 2000 0x00000000] + Line[180500 76500 180500 77500 1000 2000 0x00000000] + Line[161993 114811 161500 114500 1000 2000 0x00000000] + Line[142237 114811 142500 115256 1000 2000 0x00000000] + Line[200993 91811 201000 84000 1000 2000 0x00000000] + Line[201000 84000 208000 77000 1000 2000 0x00000000] + Line[208000 77000 224000 77000 1000 2000 0x00000000] + Line[224000 77000 250000 103000 1000 2000 0x00000000] + Line[250000 103000 250000 169000 1000 2000 0x00000000] + Line[250000 169000 244500 174500 1000 2000 0x00000000] + Line[244500 174500 205000 174500 1000 2000 0x00000000] + Line[205000 174500 204500 174000 1000 2000 0x00000000] + Line[189493 114811 189500 121500 1000 2000 0x00000000] + Line[189500 121500 183500 127500 1000 2000 0x00000000] + Line[193493 114811 193500 127500 1000 2000 0x00000000] + Line[197493 115311 197500 121500 1000 2000 0x00000000] + Line[197500 121500 203500 127500 1000 2000 0x00000000] + Line[212993 114811 213000 117500 1000 2000 0x00000000] + Line[213000 118000 215500 120500 1000 2000 0x00000000] + Line[215500 120500 224500 120500 1000 2000 0x00000000] + Line[224500 120500 229500 125500 1000 2000 0x00000000] + Line[229500 125500 229500 139000 1000 2000 0x00000000] + Line[229500 139000 224500 144000 1000 2000 0x00000000] + Line[224500 144000 220000 144000 1000 2000 0x00000000] + Line[220000 144000 213500 137500 1000 2000 0x00000000] + Line[204993 114811 205000 116500 1000 2000 0x00000000] + Line[204993 116311 208500 120000 1000 2000 0x00000000] + Line[201493 114811 201500 119500 1000 2000 0x00000000] + Line[208500 120000 208500 130000 1000 2000 0x00000000] + Line[208500 130000 205500 132500 1000 2000 0x00000000] + Line[205500 132500 198500 132500 1000 2000 0x00000000] + Line[198500 132500 193500 137500 1000 2000 0x00000000] + Line[208993 114811 209000 117000 1000 2000 0x00000000] + Line[209000 117000 209500 117500 1000 2000 0x00000000] + Line[209500 117500 209500 118000 1000 2000 0x00000000] + Line[209500 118000 214500 123000 1000 2000 0x00000000] + Line[214500 123000 216000 123000 1000 2000 0x00000000] + Line[216000 123000 218500 125500 1000 2000 0x00000000] + Line[218500 125500 218500 130500 1000 2000 0x00000000] + Line[218500 130500 216500 132500 1000 2000 0x00000000] + Line[216500 132500 210500 132500 1000 2000 0x00000000] + Line[201500 119500 202500 120500 1000 2000 0x00000000] + Line[210500 132500 208500 133500 1000 2000 0x00000000] + Line[208500 133500 204500 137500 1000 2000 0x00000000] + Line[87000 30500 87000 31000 1000 2000 0x00000000] + Line[87000 31000 92000 36000 1000 2000 0x00000000] + Line[92000 36000 92000 74500 1000 2000 0x00000000] + Line[92000 74500 102500 85000 1000 2000 0x00000000] + Line[102500 85000 102493 92811 1000 2000 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Line[118493 91811 119500 93000 1000 2000 0x00000000] + Line[117000 40000 117000 40500 1000 2000 0x00000000] + Line[117000 74500 122500 80000 1000 2000 0x00000000] + Line[122500 80000 122493 92311 1000 2000 0x00000000] + Line[117000 30500 122000 35500 1000 2000 0x00000000] + Line[122000 35500 122000 74000 1000 2000 0x00000000] + Line[122000 74000 126500 78500 1000 2000 0x00000000] + Line[126500 78500 126493 92311 1000 2000 0x00000000] + Line[126493 92311 127000 93000 1000 2000 0x00000000] + Line[127000 41000 127000 73500 1000 2000 0x00000000] + Line[127000 73500 130500 77000 1000 2000 0x00000000] + Line[130500 77000 130493 95811 1000 2000 0x00000000] + Line[127000 30500 127000 31000 1000 2000 0x00000000] + Line[127000 31000 132000 36000 1000 2000 0x00000000] + Line[132000 36000 132000 73500 1000 2000 0x00000000] + Line[132000 73500 134500 76000 1000 2000 0x00000000] + Line[134500 76000 134493 92311 1000 2000 0x00000000] + Line[134493 92311 135000 93000 1000 2000 0x00000000] + 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Line[157000 31000 162000 36000 1000 2000 0x00000000] + Line[162000 36000 162000 59500 1000 2000 0x00000000] + Line[162000 59500 158000 63500 1000 2000 0x00000000] + Line[158000 63500 157993 91311 1000 2000 0x00000000] + Line[161993 91811 162000 64500 1000 2000 0x00000000] + Line[162000 64500 167000 59500 1000 2000 0x00000000] + Line[167000 59500 167000 41000 1000 2000 0x00000000] + Line[102993 114811 98930 114811 1000 2000 0x00000000] + Line[98493 114811 98500 121000 1000 2000 0x00000000] + Line[134363 114811 134500 115130 1000 2000 0x00000000] + Line[193000 83000 186500 76500 1000 2000 0x00000000] + Line[98500 121000 75500 144000 1000 2000 0x00000000] + Line[75500 144000 75500 156500 1000 2000 0x00000000] + Line[75500 156500 80500 161500 1000 2000 0x00000000] + Line[80500 161500 80500 162500 1000 2000 0x00000000] + Line[106000 123000 115000 123000 1000 1000 0x00000080] + Line[102867 114811 103000 115000 1000 2000 0x00000000] + Line[90500 152500 92699 152500 1000 1000 0x00000080] + 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197000 192500 1000 2000 0x00000000] + Line[197000 192500 197000 198000 1000 2000 0x00000000] + Line[239500 197200 233500 203200 1000 2000 0x00000000] + Line[233500 203200 233500 222000 1000 2000 0x00000000] + Line[227900 209600 228000 209500 1000 2000 0x00000000] + Line[228000 209500 233000 209500 1000 2000 0x00000000] + Line[103499 157302 103499 157302 1000 1000 0x00000080] + Line[120101 142899 120101 142899 1000 1000 0x00000080] + Line[139198 129898 139198 129898 1000 1000 0x00000080] + Line[130500 152500 130500 152500 1000 1000 0x00000080] + Line[130500 162500 130500 162500 1000 1000 0x00000080] + Line[144999 124097 144999 124097 1000 1000 0x00000080] + Line[110500 152500 110500 152500 1000 1000 0x00000080] + Line[126059 136941 126059 136941 1000 1000 0x00000080] + Line[103801 157000 103801 157000 1000 1000 0x00000080] + Line[101801 159000 101801 159000 1000 1000 0x00000080] + Line[50600 200900 70000 182000 1000 2000 0x00000020] + Line[122500 186500 117500 189500 1000 2000 0x00000000] + Text[224500 48000 0 100 "COMPONENT" 0x00000000] +) +Layer(5 "GND-comp") +( +) +Layer(6 "Vcc-comp") +( +) +Layer(7 "GND") +( +) +Layer(8 "internal") +( +) +Layer(9 "silk") +( + Text[224500 43000 0 100 "BACK SILK" 0x00000080] +) +Layer(10 "silk") +( + Line[64000 192000 64000 115000 1000 2000 0x00000020] + Line[64000 115000 135000 115000 1000 2000 0x00000024] + Line[85000 115000 85000 175000 1000 2000 0x00000024] + Line[105000 115000 105000 176000 1000 2000 0x00000024] + Line[116000 115000 116000 179000 1000 2000 0x00000024] + Line[135000 115000 135000 179000 1000 2000 0x00000024] + Line[64000 125000 135000 125000 1000 2000 0x00000024] + Text[224500 34000 0 100 "SILK" 0x00000000] + Text[110200 85300 0 298 "BasicRX" 0x00000000] + Text[165400 22600 1 100 "DGND" 0x00000000] + Text[27500 160500 1 100 "DGND" 0x00000000] + Text[67300 143400 1 100 "DGND" 0x00000000] + Text[28500 56500 1 100 "DGND" 0x00000000] + Text[10700 107300 1 78 "io_rx[8]" 0x00000000] + Text[8600 225900 1 78 "io_rx[0]" 0x00000000] + Text[2100 4500 0 78 "io_rx[15]" 0x00000000] + Text[6800 125600 1 78 "io_rx[7]" 0x00000000] + Text[155400 21600 1 78 "io_rx[1]" 0x00000000] + Text[166400 65600 1 78 "io_rx[0]" 0x00000000] + Text[105400 65600 1 78 "io_rx[12]" 0x00000000] + Text[95400 65600 1 78 "io_rx[14]" 0x00000000] + Text[145400 65600 1 78 "io_rx[4]" 0x00000000] + Text[135400 65600 1 78 "io_rx[6]" 0x00000000] + Text[125400 65600 1 78 "io_rx[8]" 0x00000000] + Text[156100 65400 1 78 "io_rx[2]" 0x00000000] + Text[115400 65600 1 78 "io_rx[10]" 0x00000000] + Text[86000 22800 1 78 "io_rx[15]" 0x00000000] + Text[95800 22500 1 78 "io_rx[13]" 0x00000000] + Text[105900 21900 1 78 "io_rx[11]" 0x00000000] + Text[115100 21900 1 78 "io_rx[9]" 0x00000000] + Text[125400 21600 1 78 "io_rx[7]" 0x00000000] + Text[135400 21600 1 78 "io_rx[5]" 0x00000000] + Text[145400 21600 1 78 "io_rx[3]" 0x00000000] + Text[78300 143400 1 100 "DGND" 0x00000000] + Text[136300 145400 1 100 "DGND" 0x00000000] + Text[178000 217000 0 144 "RX-B" 0x00000000] + Text[242000 216000 0 144 "RX-A" 0x00000000] + Text[59000 196000 0 122 "RS232" 0x00000000] + Text[88000 144000 1 100 "A1" 0x00000000] + Text[88000 175000 1 100 "A0" 0x00000000] + Text[98000 139000 1 100 "SDA" 0x00000000] + Text[96000 170000 0 78 "SCL" 0x00000000] + Text[118000 144000 1 100 "SCLK" 0x00000000] + Text[128000 145000 1 100 "SEN_RX" 0x00000000] + Text[129000 179000 1 100 "SDI" 0x00000000] + Text[119000 180000 1 100 "SDO" 0x00000000] + Text[139000 185000 1 100 "Reset" 0x00000000] + Text[108000 144000 1 100 "RXD" 0x00000000] + Text[106000 170000 0 78 "TXD" 0x00000000] + Text[67000 191000 1 100 "3.3V_Dig" 0x00000000] + Text[79000 177000 1 100 "6V" 0x00000000] + Text[69000 118000 0 100 "PWR" 0x00000000] + Text[121000 117000 0 100 "SPI" 0x00000000] + Text[90000 118000 0 100 "I2C" 0x00000000] + Text[107000 118000 0 78 "232" 0x00000000] + Text[211000 120000 1 100 "DAC_C" 0x00000000] + Text[180000 120000 1 100 "DAC_D" 0x00000000] + Text[203000 156000 1 56 "ADC_A1" 0x00000000] + Text[180000 145000 0 56 "3.3VA" 0x00000000] + Text[192000 120000 1 100 "DAC_A" 0x00000000] + Text[201000 119000 1 100 "DAC_B" 0x00000000] + Text[208000 144000 0 56 "ADC_B1" 0x00000000] + Text[194000 156000 1 56 "ADCREF" 0x00000000] + Text[225000 121000 1 78 "AGND" 0x00000000] + Text[230000 145000 1 78 "AGND" 0x00000000] +) +NetList() +( + Net("TXD" "(unknown)") + ( + Connect("J27-3") + Connect("U410-14") + ) + Net("RXD" "(unknown)") + ( + Connect("J27-2") + Connect("U410-13") + ) + Net("CTS" "(unknown)") + ( + Connect("J27-8") + Connect("U410-8") + ) + Net("RTS" "(unknown)") + ( + Connect("J27-7") + Connect("U410-7") + ) + Net("unnamed_net14" "(unknown)") + ( + Connect("U410-5") + Connect("C489-2") + ) + Net("unnamed_net13" "(unknown)") + ( + Connect("U410-4") + Connect("C489-1") + ) + Net("unnamed_net12" "(unknown)") + ( + Connect("U410-3") + Connect("C475-2") + ) + Net("unnamed_net11" "(unknown)") + ( + Connect("U410-1") + Connect("C475-1") + ) + Net("unnamed_net10" "(unknown)") + ( + Connect("U410-6") + Connect("C491-1") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("U410-2") + Connect("C490-1") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("R10-1") + Connect("T2-4") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("R11-1") + Connect("T2-6") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("R9-1") + Connect("T2-1") + Connect("J19-1") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("R8-2") + Connect("T2-5") + Connect("T2-2") + Connect("C24-1") + Connect("R7-1") + Connect("R6-2") + Connect("T1-5") + Connect("T1-2") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("R5-1") + Connect("T1-4") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("R4-1") + Connect("T1-6") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("R3-1") + Connect("T1-3") + Connect("J18-1") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("R28-2") + Connect("U1-7") + ) + Net("AUX_ADC_B1" "(unknown)") + ( + Connect("J17-7") + Connect("J2-61") + ) + Net("AUX_ADC_A1" "(unknown)") + ( + Connect("J17-5") + Connect("J2-59") + ) + Net("AUX_ADC_REF" "(unknown)") + ( + Connect("J17-3") + Connect("J2-57") + ) + Net("AUX_DAC_C" "(unknown)") + ( + Connect("J17-8") + Connect("J2-55") + ) + Net("AUX_DAC_B" "(unknown)") + ( + Connect("J17-6") + Connect("J2-53") + ) + Net("AUX_DAC_A" "(unknown)") + ( + Connect("J17-4") + Connect("J2-51") + ) + Net("AUX_DAC_D" "(unknown)") + ( + Connect("J17-2") + Connect("J2-49") + ) + Net("SEN_RX" "(unknown)") + ( + Connect("J16-14") + Connect("J2-35") + ) + Net("VINP_A" "(unknown)") + ( + Connect("C25-1") + Connect("R10-2") + Connect("J2-62") + ) + Net("VINN_A" "(unknown)") + ( + Connect("C26-1") + Connect("R11-2") + Connect("J2-60") + ) + Net("VREF" "(unknown)") + ( + Connect("R8-1") + Connect("J2-56") + ) + Net("VINN_B" "(unknown)") + ( + Connect("C23-1") + Connect("R5-2") + Connect("J2-52") + ) + Net("VINP_B" "(unknown)") + ( + Connect("C22-1") + Connect("R4-2") + Connect("J2-50") + ) + Net("AVDD" "(unknown)") + ( + Connect("J17-1") + Connect("R6-1") + Connect("J2-45") + Connect("J2-43") + Connect("J2-46") + Connect("J2-44") + ) + Net("AGND" "(unknown)") + ( + Connect("J17-9") + Connect("J17-10") + Connect("C26-2") + Connect("C25-2") + Connect("R9-2") + Connect("T2-3") + Connect("J19-5") + Connect("J19-4") + Connect("J19-3") + Connect("J19-2") + Connect("R7-2") + Connect("C24-2") + Connect("C23-2") + Connect("C22-2") + Connect("R3-2") + Connect("T1-1") + Connect("J18-5") + Connect("J18-4") + Connect("J18-3") + Connect("J18-2") + Connect("J2-63") + Connect("J2-47") + Connect("J2-41") + Connect("J2-64") + Connect("J2-58") + Connect("J2-54") + Connect("J2-48") + Connect("J2-42") + ) + Net("io_rx_00" "(unknown)") + ( + Connect("U410-10") + Connect("J24-15") + Connect("J15-19") + Connect("J2-36") + ) + Net("io_rx_01" "(unknown)") + ( + Connect("U410-9") + Connect("J24-13") + Connect("J15-18") + Connect("J2-34") + ) + Net("io_rx_02" "(unknown)") + ( + Connect("J24-11") + Connect("J15-17") + Connect("J2-32") + ) + Net("io_rx_03" "(unknown)") + ( + Connect("J24-9") + Connect("J15-16") + Connect("J2-30") + ) + Net("io_rx_04" "(unknown)") + ( + Connect("J24-7") + Connect("J15-15") + Connect("J2-28") + ) + Net("SDI" "(unknown)") + ( + Connect("J16-13") + Connect("J2-33") + ) + Net("SDO" "(unknown)") + ( + Connect("J16-11") + Connect("J2-31") + ) + Net("SCLK" "(unknown)") + ( + Connect("J16-12") + Connect("J2-29") + ) + Net("RESET" "(unknown)") + ( + Connect("J16-15") + Connect("J2-27") + ) + Net("io_rx_05" "(unknown)") + ( + Connect("J24-5") + Connect("J15-14") + Connect("J2-26") + ) + Net("RS232_RXD" "(unknown)") + ( + Connect("U410-12") + Connect("J16-10") + Connect("J2-25") + ) + Net("io_rx_06" "(unknown)") + ( + Connect("J24-3") + Connect("J15-13") + Connect("J2-24") + ) + Net("RS232_TXD" "(unknown)") + ( + Connect("U410-11") + Connect("J16-9") + Connect("J2-23") + ) + Net("io_rx_07" "(unknown)") + ( + Connect("J24-1") + Connect("J15-12") + Connect("J2-22") + ) + Net("I2C_A0" "(unknown)") + ( + Connect("J16-5") + Connect("U1-1") + Connect("J2-21") + ) + Net("io_rx_08" "(unknown)") + ( + Connect("J25-15") + Connect("J15-11") + Connect("J2-20") + ) + Net("I2C_A1" "(unknown)") + ( + Connect("J16-6") + Connect("U1-2") + Connect("J2-19") + ) + Net("io_rx_09" "(unknown)") + ( + Connect("J25-13") + Connect("J15-10") + Connect("J2-18") + ) + Net("SDA" "(unknown)") + ( + Connect("J16-8") + Connect("U1-5") + Connect("J2-17") + ) + Net("io_rx_10" "(unknown)") + ( + Connect("J25-11") + Connect("J15-9") + Connect("J2-16") + ) + Net("SCL" "(unknown)") + ( + Connect("J16-7") + Connect("U1-6") + Connect("J2-15") + ) + Net("io_rx_11" "(unknown)") + ( + Connect("J25-9") + Connect("J15-8") + Connect("J2-14") + ) + Net("CLKOUT2" "(unknown)") + ( + Connect("J2-13") + ) + Net("io_rx_12" "(unknown)") + ( + Connect("J25-7") + Connect("J15-7") + Connect("J2-12") + ) + Net("CLKOUT1" "(unknown)") + ( + Connect("J2-11") + ) + Net("io_rx_13" "(unknown)") + ( + Connect("J25-5") + Connect("J15-6") + Connect("J2-10") + ) + Net("io_rx_14" "(unknown)") + ( + Connect("J25-3") + Connect("J15-5") + Connect("J2-8") + ) + Net("DVDD" "(unknown)") + ( + Connect("C492-1") + Connect("U410-16") + Connect("J16-1") + Connect("U1-8") + Connect("U1-3") + Connect("J2-9") + Connect("J2-7") + ) + Net("io_rx_15" "(unknown)") + ( + Connect("J25-1") + Connect("J15-4") + Connect("J2-6") + ) + Net("5V" "(unknown)") + ( + Connect("J16-3") + Connect("J2-5") + Connect("J2-3") + ) + Net("GND" "(unknown)") + ( + Connect("C492-2") + Connect("J27-5") + Connect("U410-15") + Connect("C491-2") + Connect("C490-2") + Connect("J25-6") + Connect("J25-4") + Connect("J25-14") + Connect("J25-12") + Connect("J25-10") + Connect("J25-16") + Connect("J25-8") + Connect("J25-2") + Connect("J24-6") + Connect("J24-4") + Connect("J24-14") + Connect("J24-12") + Connect("J24-10") + Connect("J24-16") + Connect("J24-8") + Connect("J24-2") + Connect("J16-16") + Connect("J16-4") + Connect("J16-2") + Connect("J15-20") + Connect("R28-1") + Connect("U1-4") + Connect("J2-37") + Connect("J2-38") + Connect("J2-2") + Connect("J2-1") + ) +) diff --git a/usrp-hw/basic-dboard/rxmod.prj b/usrp-hw/basic-dboard/rxmod.prj new file mode 100644 index 000000000..f84364897 --- /dev/null +++ b/usrp-hw/basic-dboard/rxmod.prj @@ -0,0 +1,6 @@ +# List all schematics +schematics rxmod.sch + +output-name rxmod + +elements-dir ./pkg/newlib diff --git a/usrp-hw/basic-dboard/rxmod.sch b/usrp-hw/basic-dboard/rxmod.sch new file mode 100644 index 000000000..af44ff39f --- /dev/null +++ b/usrp-hw/basic-dboard/rxmod.sch @@ -0,0 +1,1122 @@ +v 20040111 1 +C 76100 43400 1 180 1 pmc64.sym +{ +T 76800 30200 5 10 1 1 0 2 1 +refdes=J2 +T 76100 43400 5 10 0 1 90 6 1 +footprint=PMC-REVERSE +} +N 77600 38300 79300 38300 4 +{ +T 77900 38300 5 10 1 1 0 0 1 +netname=RS232_RXD +} +N 77600 38700 79300 38700 4 +{ +T 77900 38700 5 10 1 1 0 0 1 +netname=RS232_TXD +} +C 76000 30500 1 90 0 generic-power.sym +{ +T 75750 30700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 76000 30700 76200 30700 4 +N 77600 39500 78900 39500 4 +{ +T 78000 39500 5 10 1 1 0 0 1 +netname=I2C_A1 +} +C 78200 43000 1 90 0 gnd-1.sym +N 77600 43100 77900 43100 4 +C 75600 43200 1 270 0 gnd-1.sym +N 76200 43100 75900 43100 4 +C 77800 30900 1 270 0 generic-power.sym +{ +T 78050 30700 5 10 1 1 270 3 1 +net=AGND:1 +} +N 77800 30700 77600 30700 4 +N 77600 36300 78800 36300 4 +{ +T 77700 36300 5 10 1 1 0 0 1 +netname=SEN_RX +} +C 75700 36000 1 270 0 gnd-1.sym +N 76200 35900 76000 35900 4 +C 78100 35800 1 90 0 gnd-1.sym +N 77600 35900 77800 35900 4 +C 76000 34900 1 90 0 generic-power.sym +{ +T 75750 35100 5 10 1 1 90 3 1 +net=AGND:1 +} +N 76000 35100 76200 35100 4 +C 77800 35300 1 270 0 generic-power.sym +{ +T 78050 35100 5 10 1 1 270 3 1 +net=AGND:1 +} +N 77800 35100 77600 35100 4 +N 77600 31500 79200 31500 4 +{ +T 77600 31500 5 10 1 1 0 0 1 +netname=AUX_ADC_A1 +} +N 77600 31100 79200 31100 4 +{ +T 77600 31100 5 10 1 1 0 0 1 +netname=AUX_ADC_B1 +} +C 76000 31700 1 90 0 generic-power.sym +{ +T 75750 31900 5 10 1 1 90 3 1 +net=AGND:1 +} +N 76000 31900 76200 31900 4 +C 76000 32500 1 90 0 generic-power.sym +{ +T 75750 32700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 76000 32700 76200 32700 4 +C 76000 33700 1 90 0 generic-power.sym +{ +T 75750 33900 5 10 1 1 90 3 1 +net=AGND:1 +} +N 76000 33900 76200 33900 4 +N 74600 31100 76200 31100 4 +{ +T 74600 31100 5 10 1 1 0 0 1 +netname=VINP_A +} +N 74600 31500 76200 31500 4 +{ +T 74600 31500 5 10 1 1 0 0 1 +netname=VINN_A +} +N 74600 33500 76200 33500 4 +{ +T 74600 33500 5 10 1 1 0 0 1 +netname=VINP_B +} +N 74600 33100 76200 33100 4 +{ +T 74600 33100 5 10 1 1 0 0 1 +netname=VINN_B +} +N 76200 32300 74600 32300 4 +{ +T 74700 32300 5 10 1 1 0 0 1 +netname=VREF +} +C 77800 34100 1 270 0 generic-power.sym +{ +T 78050 33900 5 10 1 1 270 3 1 +net=AGND:1 +} +N 77800 33900 77600 33900 4 +C 78400 34500 1 270 0 generic-power.sym +{ +T 78650 34300 5 10 1 1 270 3 1 +net=AVDD:1 +} +N 77600 34700 78100 34700 4 +N 77600 34300 78400 34300 4 +C 78100 34900 1 270 0 generic-power.sym +{ +T 78350 34700 5 10 1 1 270 3 1 +net=AVDD:1 +} +C 78300 42900 1 270 0 generic-power.sym +{ +T 78550 42700 5 10 1 1 270 3 1 +net=5V:1 +} +C 75400 34500 1 90 1 generic-power.sym +{ +T 75150 34300 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 76200 34300 75400 34300 4 +N 76200 34700 75700 34700 4 +C 75700 34900 1 90 1 generic-power.sym +{ +T 75450 34700 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 77600 42700 78300 42700 4 +N 77600 42300 78100 42300 4 +C 78100 41700 1 270 0 generic-power.sym +{ +T 78350 41500 5 10 1 1 270 3 1 +net=DVDD:1 +} +N 77600 41500 78100 41500 4 +N 77600 41900 77900 41900 4 +N 78100 42300 78100 42700 4 +N 77900 41900 77900 41500 4 +N 74200 42300 76200 42300 4 +{ +T 74500 42300 5 10 1 1 0 0 1 +netname=io_rx_15 +} +N 74200 41900 76200 41900 4 +{ +T 74500 41900 5 10 1 1 0 0 1 +netname=io_rx_14 +} +N 74200 40700 76200 40700 4 +{ +T 74500 40700 5 10 1 1 0 0 1 +netname=io_rx_11 +} +N 74200 41500 76200 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0x02000002] +Via[146000 117000 4000 2000 0 2000 "" 0x02000002] +Via[130000 118000 4000 2000 0 2000 "" 0x02000002] +Via[134000 124000 4000 2000 0 2000 "" 0x02000002] +Via[193000 175000 4000 2000 0 2000 "" 0x02000002] +Via[208000 174000 4000 2000 0 2000 "" 0x02000002] +Via[201000 166000 4000 2000 0 2000 "" 0x02020002] +Via[181000 174000 4000 2000 0 2000 "" 0x02000002] +Via[178000 184000 4000 2000 0 2000 "" 0x02020002] +Via[148000 62000 4000 2000 0 2000 "" 0x02020002] +Via[90000 139000 4000 2000 0 2000 "" 0x02020002] +Via[90000 157000 4000 2000 0 2000 "" 0x02020002] +Via[184000 126000 4000 2000 0 2000 "" 0x02020002] +Via[217000 127000 4000 2000 0 2000 "" 0x02020002] +Via[108000 126000 4000 2000 0 2000 "" 0x02000002] +Via[111000 56000 4000 2000 0 2000 "" 0x02000002] +Via[217000 174000 4000 2000 0 2000 "" 0x02020002] +Via[174000 126000 4000 2000 0 2000 "" 0x02020002] +Via[55000 195000 13200 2000 0 12800 "" 0x0200000a] +Via[53000 71000 6000 2000 0 2800 "" 0x02000002] +Via[59000 66000 6000 2000 0 2800 "" 0x02000002] +Via[45000 86000 6000 2000 0 2800 "" 0x02000002] +Via[79000 108000 6000 2000 0 2800 "" 0x02020002] +Via[72000 90000 6000 2000 0 2800 "" 0x02020002] + +Element[0x00000000 "SO8" "U52" "unknown" 106000 57000 -14000 8000 0 100 0x00000000] +( + Pad[-1900 0 900 0 2000 3000 2000 "1" "1" 0x00000000] + Pad[-1900 5000 900 5000 2000 3000 2000 "2" "2" 0x00000100] + Pad[-1900 10000 900 10000 2000 3000 2000 "3" "3" 0x00000100] + Pad[-1900 15000 900 15000 2000 3000 2000 "4" "4" 0x00000100] + Pad[18500 15000 21300 15000 2000 3000 2000 "5" "5" 0x00004100] + Pad[18500 10000 21300 10000 2000 3000 2000 "6" "6" 0x00004100] + Pad[18500 5000 21300 5000 2000 3000 2000 "7" "7" 0x00004100] + Pad[18500 0 21300 0 2000 3000 2000 "8" "8" 0x00004100] + ElementLine [-2900 -2500 12200 -2500 1000] + ElementLine [7200 -2500 22300 -2500 1000] + ElementLine [22300 -2500 22300 17500 1000] + ElementLine [-2900 17500 22300 17500 1000] + ElementLine [-2900 -2500 -2900 17500 1000] + ElementArc [9700 -2500 2500 2500 0 180 1000] + + ) + +Element[0x00000000 "0603" "R29" "0" 137000 62000 -5000 -9000 0 100 0x00000000] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000100] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000100] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000000 "0603" "C41" "10pF" 220000 136000 -1000 -6000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000080 "PMC-REVERSE" "J44" "unknown" 94993 139811 -21000 12000 0 100 0x00000080] +( + Pin[-6693 7189 7200 2000 7200 5600 "" "1" 0x02004009] + Pin[128740 7189 7200 2000 7200 5600 "" "2" 0x02004029] + Pad[0 9900 0 19000 2400 1000 3400 "" "1" 0x000040a0] + Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" 0x000000a0] + Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" 0x00004080] + Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" 0x000040a0] + Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" 0x000040a0] + Pad[0 -4622 0 4478 2400 1000 3400 "" "2" 0x000000a0] + Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" 0x000040a0] + Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" 0x000000a0] + Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" 0x000040a0] + Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" 0x000000a0] + Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" 0x000040a0] + Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" 0x000000a0] + Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" 0x000040a0] + Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" 0x000000a0] + Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" 0x000040a0] + Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" 0x000000a0] + Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" 0x000040a0] + Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" 0x000000a0] + Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" 0x000040a0] + Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" 0x000000a0] + Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" 0x000000a0] + Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" 0x000000a0] + Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" 0x000000a0] + Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" 0x000000a0] + Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" 0x000000a0] + Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" 0x000000a0] + Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" 0x000000a0] + Pad[62992 -4622 62992 4478 2400 1000 3400 "" "34" 0x000000a0] + Pad[66929 -4622 66929 4478 2400 1000 3400 "" "36" 0x000000a0] + Pad[70866 -4622 70866 4478 2400 1000 3400 "" "38" 0x000000a0] + Pad[74803 -4622 74803 4478 2400 1000 3400 "" "40" 0x000000a0] + Pad[78740 -4622 78740 4478 2400 1000 3400 "" "42" 0x000000a0] + Pad[82677 -4622 82677 4478 2400 1000 3400 "" "44" 0x000000a0] + Pad[86614 -4622 86614 4478 2400 1000 3400 "" "46" 0x000000a0] + Pad[90551 -4622 90551 4478 2400 1000 3400 "" "48" 0x000000a0] + Pad[98425 -4622 98425 4478 2400 1000 3400 "" "52" 0x000000a0] + Pad[94488 -4622 94488 4478 2400 1000 3400 "" "50" 0x000000a0] + Pad[102362 -4622 102362 4478 2400 1000 3400 "" "54" 0x000000a0] + Pad[106299 -4622 106299 4478 2400 1000 3400 "" "56" 0x000000a0] + Pad[110236 -4622 110236 4478 2400 1000 3400 "" "58" 0x000000a0] + Pad[114173 -4622 114173 4478 2400 1000 3400 "" "60" 0x000000a0] + Pad[3937 -4622 3937 4478 2400 1000 3400 "" "4" 0x000000a0] + Pad[43307 9900 43307 19000 2400 1000 3400 "" "23" 0x000040a0] + Pad[47244 9900 47244 19000 2400 1000 3400 "" "25" 0x000040a0] + Pad[51181 9900 51181 19000 2400 1000 3400 "" "27" 0x000040a0] + Pad[55118 9900 55118 19000 2400 1000 3400 "" "29" 0x000040a0] + Pad[59055 9900 59055 19000 2400 1000 3400 "" "31" 0x000040a0] + Pad[62992 9900 62992 19000 2400 1000 3400 "" "33" 0x000040a0] + Pad[66929 9900 66929 19000 2400 1000 3400 "" "35" 0x000040a0] + Pad[70866 9900 70866 19000 2400 1000 3400 "" "37" 0x000040a0] + Pad[74803 9900 74803 19000 2400 1000 3400 "" "39" 0x000040a0] + Pad[78740 9900 78740 19000 2400 1000 3400 "" "41" 0x000040a0] + Pad[82677 9900 82677 19000 2400 1000 3400 "" "43" 0x000040a0] + Pad[86614 9900 86614 19000 2400 1000 3400 "" "45" 0x000040a0] + Pad[90551 9900 90551 19000 2400 1000 3400 "" "47" 0x000040a0] + Pad[94488 9900 94488 19000 2400 1000 3400 "" "49" 0x000040a0] + Pad[98425 9900 98425 19000 2400 1000 3400 "" "51" 0x000040a0] + Pad[102362 9900 102362 19000 2400 1000 3400 "" "53" 0x000040a0] + Pad[106299 9900 106299 19000 2400 1000 3400 "" "55" 0x000040a0] + Pad[110236 9900 110236 19000 2400 1000 3400 "" "57" 0x000040a0] + Pad[114173 9900 114173 19000 2400 1000 3400 "" "59" 0x000040a0] + Pad[118110 9900 118110 19000 2400 1000 3400 "" "61" 0x000040a0] + Pad[122047 9900 122047 19000 2400 1000 3400 "" "63" 0x000040a0] + Pad[118110 -4622 118110 4478 2400 1000 3400 "" "62" 0x000000a0] + ElementLine [134000 -9000 134000 24000 1000] + ElementLine [-11000 24000 134000 24000 1000] + ElementLine [-11000 -9000 134000 -9000 1000] + ElementLine [-11000 -9000 -11000 24000 1000] + + ) + +Element[0x00000000 "SMA_VERT" "J49" "unknown" 169000 228000 -16000 -23000 0 100 0x00000000] +( + Pin[0 0 9000 3000 9000 6000 "1" "1" 0x02000001] + Pin[-10000 10000 9000 3000 9000 6000 "2" "2" 0x02420001] + Pin[-10000 -10000 9000 3000 9000 6000 "3" "3" 0x02420001] + Pin[10000 10000 9000 3000 9000 6000 "4" "4" 0x02420001] + Pin[10000 -10000 9000 3000 9000 6000 "5" "5" 0x02420001] + ElementLine [-16000 -16000 16000 -16000 1000] + ElementLine [16000 -16000 16000 16000 1000] + ElementLine [16000 16000 -16000 16000 1000] + ElementLine [-16000 16000 -16000 -16000 1000] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J46" "unknown" 86000 96000 77000 1000 0 100 0x00000000] +( + Pin[0 0 6000 3000 6000 4000 "1" "1" 0x02004101] + Pin[0 -10000 6000 3000 6000 4000 "2" "2" 0x02024001] + Pin[10000 0 6000 3000 6000 4000 "3" "3" 0x02004001] + Pin[10000 -10000 6000 3000 6000 4000 "4" "4" 0x02024001] + Pin[20000 0 6000 3000 6000 4000 "5" "5" 0x02004001] + Pin[20000 -10000 6000 3000 6000 4000 "6" "6" 0x02004001] + Pin[30000 0 6000 3000 6000 4000 "7" "7" 0x02004001] + Pin[30000 -10000 6000 3000 6000 4000 "8" "8" 0x02004001] + Pin[40000 0 6000 3000 6000 4000 "9" "9" 0x02004001] + Pin[40000 -10000 6000 3000 6000 4000 "10" "10" 0x02004001] + Pin[50000 0 6000 3000 6000 4000 "11" "11" 0x02004001] + Pin[50000 -10000 6000 3000 6000 4000 "12" "12" 0x02004001] + Pin[60000 0 6000 3000 6000 4000 "13" "13" 0x02004001] + Pin[60000 -10000 6000 3000 6000 4000 "14" "14" 0x02004001] + Pin[70000 0 6000 3000 6000 4000 "15" "15" 0x02004001] + Pin[70000 -10000 6000 3000 6000 4000 "16" "16" 0x02024001] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 75000 -15000 2000] + ElementLine [75000 -15000 75000 5000 2000] + ElementLine [-5000 5000 75000 5000 2000] + + ) + +Element[0x00000000 "MINICIRCUITS_CD542" "T50" "unknown" 218000 180000 -14000 23000 0 100 0x00000000] +( + Pad[-10000 13200 -10000 16700 6500 3000 6500 "1" "1" 0x00004100] + Pad[0 13200 0 16700 6500 3000 6500 "2" "2" 0x00004100] + Pad[10000 13200 10000 16700 6500 3000 6500 "3" "3" 0x00004100] + Pad[10000 -16700 10000 -13200 6500 3000 6500 "4" "4" 0x00000100] + Pad[0 -16700 0 -13200 6500 3000 6500 "5" "5" 0x00000100] + Pad[-10000 -16700 -10000 -13200 6500 3000 6500 "6" "6" 0x00000100] + ElementLine [-14200 21000 14200 21000 1000] + ElementLine [14200 -21000 14200 21000 1000] + ElementLine [-14200 -21000 14200 -21000 1000] + ElementLine [-14200 2500 -14200 21000 1000] + ElementLine [-14200 -21000 -14200 -2500 1000] + ElementArc [-14200 0 2500 2500 90 180 1000] + + ) + +Element[0x00000000 "SMA_VERT" "J48" "unknown" 226000 228000 7000 -22000 0 100 0x00000000] +( + Pin[0 0 9000 3000 9000 6000 "1" "1" 0x02000001] + Pin[-10000 10000 9000 3000 9000 6000 "2" "2" 0x02420001] + Pin[-10000 -10000 9000 3000 9000 6000 "3" "3" 0x02420001] + Pin[10000 10000 9000 3000 9000 6000 "4" "4" 0x02420001] + Pin[10000 -10000 9000 3000 9000 6000 "5" "5" 0x02420001] + ElementLine [-16000 -16000 16000 -16000 1000] + ElementLine [16000 -16000 16000 16000 1000] + ElementLine [16000 16000 -16000 16000 1000] + ElementLine [-16000 16000 -16000 -16000 1000] + + ) + +Element[0x00000000 "0603" "R36" "100" 183000 148000 5000 -2000 0 100 0x00000000] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" 0x00000100] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + + ) + +Element[0x00000000 "CONNECTOR-5-2" "J47" "unknown" 189000 96000 -17000 -12000 0 100 0x00000000] +( + Pin[0 0 6000 3000 6000 4000 "1" "1" 0x02004101] + Pin[0 -10000 6000 3000 6000 4000 "2" "2" 0x02004001] + Pin[10000 0 6000 3000 6000 4000 "3" "3" 0x02004001] + Pin[10000 -10000 6000 3000 6000 4000 "4" "4" 0x02004001] + Pin[20000 0 6000 3000 6000 4000 "5" "5" 0x02004001] + Pin[20000 -10000 6000 3000 6000 4000 "6" "6" 0x02004001] + Pin[30000 0 6000 3000 6000 4000 "7" "7" 0x02004001] + Pin[30000 -10000 6000 3000 6000 4000 "8" "8" 0x02004001] + Pin[40000 0 6000 3000 6000 4000 "9" "9" 0x02424001] + Pin[40000 -10000 6000 3000 6000 4000 "10" "10" 0x02424001] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 45000 -15000 2000] + ElementLine [45000 -15000 45000 5000 2000] + ElementLine [-5000 5000 45000 5000 2000] + + ) + +Element[0x00000000 "0603" "C43" "10pF" 187000 136000 -5000 -13000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000000 "0603" "R35" "50" 173000 136000 -2000 -14000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000000 "0603" "C42" "10pF" 180000 136000 -3000 -6000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000000 "0603" "R37" "50" 194000 136000 -2000 -5000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000000 "0603" "R32" "50" 206000 136000 -2000 -6000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000000 "0603" "C40" "10pF" 213000 136000 -3000 -6000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000000 "0603" "R33" "100" 214000 147000 -15000 -2000 0 100 0x00000000] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" 0x00000100] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + + ) + +Element[0x00000000 "MINICIRCUITS_CD542" "T51" "unknown" 183000 180000 4000 23000 0 100 0x00000000] +( + Pad[-10000 13200 -10000 16700 6500 3000 6500 "1" "1" 0x00004100] + Pad[0 13200 0 16700 6500 3000 6500 "2" "2" 0x00004100] + Pad[10000 13200 10000 16700 6500 3000 6500 "3" "3" 0x00004100] + Pad[10000 -16700 10000 -13200 6500 3000 6500 "4" "4" 0x00000120] + Pad[0 -16700 0 -13200 6500 3000 6500 "5" "5" 0x00000100] + Pad[-10000 -16700 -10000 -13200 6500 3000 6500 "6" "6" 0x00000100] + ElementLine [-14200 21000 14200 21000 1000] + ElementLine [14200 -21000 14200 21000 1000] + ElementLine [-14200 -21000 14200 -21000 1000] + ElementLine [-14200 2500 -14200 21000 1000] + ElementLine [-14200 -21000 -14200 -2500 1000] + ElementArc [-14200 0 2500 2500 90 180 1000] + + ) + +Element[0x00000000 "0603" "R34" "50" 227000 136000 -2000 -6000 1 100 0x00000000] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000100] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000100] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element[0x00000000 "CONNECTOR-10-2" "J45" "unknown" 45000 237000 45000 -38000 0 100 0x00000000] +( + Pin[0 0 6000 3000 6000 4000 "1" "1" 0x02004101] + Pin[0 -10000 6000 3000 6000 4000 "2" "2" 0x02004001] + Pin[10000 0 6000 3000 6000 4000 "3" "3" 0x02004001] + Pin[10000 -10000 6000 3000 6000 4000 "4" "4" 0x02004001] + Pin[20000 0 6000 3000 6000 4000 "5" "5" 0x02004001] + Pin[20000 -10000 6000 3000 6000 4000 "6" "6" 0x02004001] + Pin[30000 0 6000 3000 6000 4000 "7" "7" 0x02004001] + Pin[30000 -10000 6000 3000 6000 4000 "8" "8" 0x02004001] + Pin[40000 0 6000 3000 6000 4000 "9" "9" 0x02004001] + Pin[40000 -10000 6000 3000 6000 4000 "10" "10" 0x02004001] + Pin[50000 0 6000 3000 6000 4000 "11" "11" 0x02004001] + Pin[50000 -10000 6000 3000 6000 4000 "12" "12" 0x02004001] + Pin[60000 0 6000 3000 6000 4000 "13" "13" 0x02004001] + Pin[60000 -10000 6000 3000 6000 4000 "14" "14" 0x02004001] + Pin[70000 0 6000 3000 6000 4000 "15" "15" 0x02004001] + Pin[70000 -10000 6000 3000 6000 4000 "16" "16" 0x02004001] + Pin[80000 0 6000 3000 6000 4000 "17" "17" 0x02004001] + Pin[80000 -10000 6000 3000 6000 4000 "18" "18" 0x02004001] + Pin[90000 0 6000 3000 6000 4000 "19" "19" 0x02004001] + Pin[90000 -10000 6000 3000 6000 4000 "20" "20" 0x02424001] + ElementLine [-5000 5000 95000 5000 2000] + ElementLine [95000 -15000 95000 5000 2000] + ElementLine [-5000 -15000 95000 -15000 2000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -5000 5000 -5000 1000] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J50" "unknown" 19000 137000 -3500 -81500 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x02000101] + Pin[-10000 0 6000 3000 6600 4000 "2" "2" 0x02020001] + Pin[0 -10000 6000 3000 6600 4000 "3" "3" 0x02000001] + Pin[-10000 -10000 6000 3000 6600 4000 "4" "4" 0x02020001] + Pin[0 -20000 6000 3000 6600 4000 "5" "5" 0x02000001] + Pin[-10000 -20000 6000 3000 6600 4000 "6" "6" 0x02020001] + Pin[0 -30000 6000 3000 6600 4000 "7" "7" 0x02000001] + Pin[-10000 -30000 6000 3000 6600 4000 "8" "8" 0x02020001] + Pin[0 -40000 6000 3000 6600 4000 "9" "9" 0x02000001] + Pin[-10000 -40000 6000 3000 6600 4000 "10" "10" 0x02020001] + Pin[0 -50000 6000 3000 6600 4000 "11" "11" 0x02000001] + Pin[-10000 -50000 6000 3000 6600 4000 "12" "12" 0x02020001] + Pin[0 -60000 6000 3000 6600 4000 "13" "13" 0x02000001] + Pin[-10000 -60000 6000 3000 6600 4000 "14" "14" 0x02020001] + Pin[0 -70000 6000 3000 6600 4000 "15" "15" 0x02000001] + Pin[-10000 -70000 6000 3000 6600 4000 "16" "16" 0x02020001] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [-15000 5000 5000 5000 2000] + ElementLine [-15000 -75000 -15000 5000 2000] + ElementLine [-15000 -75000 5000 -75000 2000] + ElementLine [5000 -75000 5000 5000 2000] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J51" "unknown" 19000 238000 -1000 -82000 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x02000101] + Pin[-10000 0 6000 3000 6600 4000 "2" "2" 0x02020001] + Pin[0 -10000 6000 3000 6600 4000 "3" "3" 0x02000001] + Pin[-10000 -10000 6000 3000 6600 4000 "4" "4" 0x02020001] + Pin[0 -20000 6000 3000 6600 4000 "5" "5" 0x02000001] + Pin[-10000 -20000 6000 3000 6600 4000 "6" "6" 0x02020001] + Pin[0 -30000 6000 3000 6600 4000 "7" "7" 0x02000001] + Pin[-10000 -30000 6000 3000 6600 4000 "8" "8" 0x02020001] + Pin[0 -40000 6000 3000 6600 4000 "9" "9" 0x02000001] + Pin[-10000 -40000 6000 3000 6600 4000 "10" "10" 0x02020001] + Pin[0 -50000 6000 3000 6600 4000 "11" "11" 0x02000001] + Pin[-10000 -50000 6000 3000 6600 4000 "12" "12" 0x02020001] + Pin[0 -60000 6000 3000 6600 4000 "13" "13" 0x02000001] + Pin[-10000 -60000 6000 3000 6600 4000 "14" "14" 0x02020001] + Pin[0 -70000 6000 3000 6600 4000 "15" "15" 0x02000001] + Pin[-10000 -70000 6000 3000 6600 4000 "16" "16" 0x02020001] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [-15000 5000 5000 5000 2000] + ElementLine [-15000 -75000 -15000 5000 2000] + ElementLine [-15000 -75000 5000 -75000 2000] + ElementLine [5000 -75000 5000 5000 2000] + + ) + +Element[0x00000000 "0603" "C490" "0.1uF" 63100 88000 -6200 6800 0 100 0x00000000] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" 0x00000100] + Pad[-900 2400 900 2400 2400 2000 3000 "2" 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"io_tx[8]" 0x00000000] + Text[245000 214000 0 122 "TX_A" 0x00000000] + Text[187000 215000 0 122 "TX_B" 0x00000000] + Text[80000 205000 0 100 "io_tx[15:0]" 0x00000000] + Text[134000 244000 0 100 "0" 0x00000000] + Text[124000 216000 0 100 "1" 0x00000000] + Text[133000 220000 1 100 "DGND" 0x00000000] + Text[124000 244000 0 100 "2" 0x00000000] + Text[114000 216000 0 100 "3" 0x00000000] + Text[114000 244000 0 100 "4" 0x00000000] + Text[104000 216000 0 100 "5" 0x00000000] + Text[104000 244000 0 100 "6" 0x00000000] + Text[92000 216000 0 100 "7" 0x00000000] + Text[94000 244000 0 100 "8" 0x00000000] + Text[83000 216000 0 100 "9" 0x00000000] + Text[82000 244000 0 100 "10" 0x00000000] + Text[73000 216000 0 100 "11" 0x00000000] + Text[72000 244000 0 100 "12" 0x00000000] + Text[62000 216000 0 100 "13" 0x00000000] + Text[62000 244000 0 100 "14" 0x00000000] + Text[52000 216000 0 100 "15" 0x00000000] + Text[192000 5000 0 166 "RS232" 0x00000000] + Text[197000 79000 1 100 "DAC_A" 0x00000000] + Text[207000 79000 1 100 "DAC_B" 0x00000000] + Text[217000 79000 1 100 "DAC_C" 0x00000000] + Text[187000 79000 1 100 "DAC_D" 0x00000000] + Text[228000 79000 1 100 "AGND" 0x00000000] + Text[208000 119000 1 78 "ADC_A2" 0x00000000] + Text[218000 119000 1 78 "ADC_B2" 0x00000000] + Text[199000 121000 1 78 "ADC_REF" 0x00000000] + Text[228000 114000 1 78 "AGND" 0x00000000] + Text[183000 103000 0 78 "3.3VA" 0x00000000] + Text[84000 74500 0 100 "DGND" 0x00000000] + Text[85000 118000 1 100 "3.3VD" 0x00000000] + Text[94500 110500 1 100 "6V" 0x00000000] + Text[104500 111500 1 100 "A0" 0x00000000] + Text[114000 114500 1 100 "SCL" 0x00000000] + Text[125000 114000 1 100 "TXD" 0x00000000] + Text[134500 114500 1 100 "SDO" 0x00000000] + Text[144500 114500 1 100 "SDI" 0x00000000] + Text[154000 120000 1 100 "RESET" 0x00000000] + Text[154000 78500 1 78 "DGND" 0x00000000] + Text[144000 79000 1 78 "SEN_TX" 0x00000000] + Text[135000 78500 1 78 "SCLK" 0x00000000] + Text[121000 75500 0 78 "RXD" 0x00000000] + Text[103000 75500 0 78 "A1" 0x00000000] + Text[110000 75500 0 78 "SDA" 0x00000000] + Text[86000 122500 0 100 "PWR" 0x00000000] + Text[107000 118500 0 100 "I2C" 0x00000000] + Text[138500 123000 0 100 "SPI" 0x00000000] + Text[125000 132500 1 100 "232" 0x00000000] +) +NetList() +( + Net("TXD" "(unknown)") + ( + Connect("J27-3") + Connect("U410-14") + ) + Net("RXD" "(unknown)") + ( + Connect("J27-2") + Connect("U410-13") + ) + Net("CTS" "(unknown)") + ( + Connect("J27-8") + Connect("U410-8") + ) + Net("RTS" "(unknown)") + ( + Connect("J27-7") + Connect("U410-7") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("U410-5") + Connect("C489-2") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("U410-4") + Connect("C489-1") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("U410-3") + Connect("C475-2") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("U410-1") + Connect("C475-1") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("U410-6") + Connect("C491-1") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("U410-2") + Connect("C490-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("T51-3") + Connect("J49-1") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("T50-3") + Connect("J48-1") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("R29-2") + Connect("U52-7") + ) + Net("IOUTN_A" "(unknown)") + ( + Connect("R33-2") + Connect("R34-1") + Connect("C41-1") + Connect("T50-4") + Connect("J44-61") + ) + Net("IOUTP_A" "(unknown)") + ( + Connect("R33-1") + Connect("R32-1") + Connect("C40-1") + Connect("T50-6") + Connect("J44-59") + ) + Net("REFIO" "(unknown)") + ( + Connect("J44-55") + ) + Net("IOUTP_B" "(unknown)") + ( + Connect("R36-1") + Connect("R35-1") + Connect("C42-1") + Connect("T51-6") + Connect("J44-51") + ) + Net("IOUTN_B" "(unknown)") + ( + Connect("R36-2") + Connect("R37-1") + Connect("C43-1") + Connect("T51-4") + Connect("J44-49") + ) + Net("io_tx_00" "(unknown)") + ( + Connect("U410-10") + Connect("J50-15") + Connect("J45-19") + Connect("J44-35") + ) + Net("AUX_ADC_B2" "(unknown)") + ( + Connect("J47-7") + Connect("J44-62") + ) + Net("AUX_ADC_A2" "(unknown)") + ( + Connect("J47-5") + Connect("J44-60") + ) + Net("AUX_ADC_REF" "(unknown)") + ( + Connect("J47-3") + Connect("J44-58") + ) + Net("AUX_DAC_C" "(unknown)") + ( + Connect("J47-8") + Connect("J44-56") + ) + Net("AUX_DAC_B" "(unknown)") + ( + Connect("J47-6") + Connect("J44-54") + ) + Net("AUX_DAC_A" "(unknown)") + ( + Connect("J47-4") + Connect("J44-52") + ) + Net("AUX_DAC_D" "(unknown)") + ( + Connect("J47-2") + Connect("J44-50") + ) + Net("AVDD" "(unknown)") + ( + Connect("J47-1") + Connect("J44-45") + Connect("J44-43") + Connect("J44-46") + Connect("J44-44") + ) + Net("AGND" "(unknown)") + ( + Connect("J47-9") + Connect("J47-10") + Connect("R37-2") + Connect("C43-2") + Connect("C42-2") + Connect("R35-2") + Connect("T51-5") + Connect("T51-2") + Connect("T51-1") + Connect("J49-5") + Connect("J49-4") + Connect("J49-3") + Connect("J49-2") + Connect("R34-2") + Connect("C41-2") + Connect("C40-2") + Connect("R32-2") + Connect("T50-5") + Connect("T50-2") + Connect("T50-1") + Connect("J48-5") + Connect("J48-4") + Connect("J48-3") + Connect("J48-2") + Connect("J44-63") + Connect("J44-57") + Connect("J44-53") + Connect("J44-47") + Connect("J44-41") + Connect("J44-64") + Connect("J44-48") + Connect("J44-42") + ) + Net("SEN_TX" "(unknown)") + ( + Connect("J46-14") + Connect("J44-36") + ) + Net("SDI" "(unknown)") + ( + Connect("J46-13") + Connect("J44-34") + ) + Net("SDO" "(unknown)") + ( + Connect("J46-11") + Connect("J44-32") + ) + Net("SCLK" "(unknown)") + ( + Connect("J46-12") + Connect("J44-30") + ) + Net("RESET" "(unknown)") + ( + Connect("J46-15") + Connect("J44-28") + ) + Net("io_tx_01" "(unknown)") + ( + Connect("U410-9") + Connect("J50-13") + Connect("J45-18") + Connect("J44-33") + ) + Net("io_tx_02" "(unknown)") + ( + Connect("J50-11") + Connect("J45-17") + Connect("J44-31") + ) + Net("io_tx_03" "(unknown)") + ( + Connect("J50-9") + Connect("J45-16") + Connect("J44-29") + ) + Net("io_tx_04" "(unknown)") + ( + Connect("J50-7") + Connect("J45-15") + Connect("J44-27") + ) + Net("RS232_RXD" "(unknown)") + ( + Connect("U410-12") + Connect("J46-10") + Connect("J44-26") + ) + Net("io_tx_05" "(unknown)") + ( + Connect("J50-5") + Connect("J45-14") + Connect("J44-25") + ) + Net("RS232_TXD" "(unknown)") + ( + Connect("U410-11") + Connect("J46-9") + Connect("J44-24") + ) + Net("io_tx_06" "(unknown)") + ( + Connect("J50-3") + Connect("J45-13") + Connect("J44-23") + ) + Net("I2C_A0" "(unknown)") + ( + Connect("J46-5") + Connect("U52-1") + Connect("J44-22") + ) + Net("io_tx_07" "(unknown)") + ( + Connect("J50-1") + Connect("J45-12") + Connect("J44-21") + ) + Net("I2C_A1" "(unknown)") + ( + Connect("J46-6") + Connect("U52-2") + Connect("J44-20") + ) + Net("io_tx_08" "(unknown)") + ( + Connect("J51-15") + Connect("J45-11") + Connect("J44-19") + ) + Net("SDA" "(unknown)") + ( + Connect("J46-8") + Connect("U52-5") + Connect("J44-18") + ) + Net("io_tx_09" "(unknown)") + ( + Connect("J51-13") + Connect("J45-10") + Connect("J44-17") + ) + Net("SCL" "(unknown)") + ( + Connect("J46-7") + Connect("U52-6") + Connect("J44-16") + ) + Net("io_tx_10" "(unknown)") + ( + Connect("J51-11") + Connect("J45-9") + Connect("J44-15") + ) + Net("io_tx_11" "(unknown)") + ( + Connect("J51-9") + Connect("J45-8") + Connect("J44-13") + ) + Net("io_tx_12" "(unknown)") + ( + Connect("J51-7") + Connect("J45-7") + Connect("J44-11") + ) + Net("io_tx_13" "(unknown)") + ( + Connect("J51-5") + Connect("J45-6") + Connect("J44-9") + ) + Net("DVDD" "(unknown)") + ( + Connect("C492-1") + Connect("U410-16") + Connect("J46-1") + Connect("U52-8") + Connect("U52-3") + Connect("J44-10") + Connect("J44-8") + ) + Net("io_tx_14" "(unknown)") + ( + Connect("J51-3") + Connect("J45-5") + Connect("J44-7") + ) + Net("io_tx_15" "(unknown)") + ( + Connect("J51-1") + Connect("J45-4") + Connect("J44-5") + ) + Net("5V" "(unknown)") + ( + Connect("J46-3") + Connect("J44-6") + Connect("J44-4") + ) + Net("GND" "(unknown)") + ( + Connect("C492-2") + Connect("J27-5") + Connect("U410-15") + Connect("C491-2") + Connect("C490-2") + Connect("J51-6") + Connect("J51-4") + Connect("J51-14") + Connect("J51-12") + Connect("J51-10") + Connect("J51-16") + Connect("J51-8") + Connect("J51-2") + Connect("J50-6") + Connect("J50-4") + Connect("J50-14") + Connect("J50-12") + Connect("J50-10") + Connect("J50-16") + Connect("J50-8") + Connect("J50-2") + Connect("J46-16") + Connect("J46-4") + Connect("J46-2") + Connect("J45-20") + Connect("R29-1") + Connect("U52-4") + Connect("J44-37") + Connect("J44-38") + Connect("J44-2") + Connect("J44-1") + ) +) diff --git a/usrp-hw/basic-dboard/txmod.prj b/usrp-hw/basic-dboard/txmod.prj new file mode 100644 index 000000000..47c099368 --- /dev/null +++ b/usrp-hw/basic-dboard/txmod.prj @@ -0,0 +1,6 @@ +# List all schematics +schematics txmod.sch + +output-name txmod + +elements-dir ./pkg/newlib diff --git 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800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] + SymbolLine[2000 2000 2000 3500 800] +) +Symbol['v' 1200] +( + SymbolLine[0 2000 0 3000 800] + SymbolLine[0 3000 1000 4000 800] + SymbolLine[1000 4000 2000 3000 800] + SymbolLine[2000 2000 2000 3000 800] +) +Symbol['w' 1200] +( + SymbolLine[0 2000 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 1000 4000 800] + SymbolLine[1000 4000 1500 3500 800] + SymbolLine[1500 2000 1500 3500 800] + SymbolLine[1500 3500 2000 4000 800] + SymbolLine[2000 4000 2500 4000 800] + SymbolLine[2500 4000 3000 3500 800] + SymbolLine[3000 2000 3000 3500 800] +) +Symbol['x' 1200] +( + SymbolLine[0 2000 2000 4000 800] + SymbolLine[0 4000 2000 2000 800] +) +Symbol['y' 1200] +( + SymbolLine[0 2000 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[2000 2000 2000 5000 800] + SymbolLine[1500 5500 2000 5000 800] + SymbolLine[500 5500 1500 5500 800] + SymbolLine[0 5000 500 5500 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] +) +Symbol['z' 1200] +( + SymbolLine[0 2000 2000 2000 800] + SymbolLine[0 4000 2000 2000 800] + SymbolLine[0 4000 2000 4000 800] +) +Symbol['{' 1200] +( + SymbolLine[500 500 1000 0 800] + SymbolLine[500 500 500 1500 800] + SymbolLine[0 2000 500 1500 800] + SymbolLine[0 2000 500 2500 800] + SymbolLine[500 2500 500 3500 800] + SymbolLine[500 3500 1000 4000 800] +) +Symbol['|' 1200] +( + SymbolLine[0 0 0 4000 800] +) +Symbol['}' 1200] +( + SymbolLine[0 0 500 500 800] + SymbolLine[500 500 500 1500 800] + SymbolLine[500 1500 1000 2000 800] + SymbolLine[500 2500 1000 2000 800] + SymbolLine[500 2500 500 3500 800] + SymbolLine[0 4000 500 3500 800] +) +Symbol['~' 1200] +( + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 1000 2000 800] + SymbolLine[1000 2000 1500 2500 800] + SymbolLine[1500 2500 2000 2500 800] + SymbolLine[2000 2500 2500 2000 800] +) +Via[15000 235000 13200 2000 11000 12800 "" "hole"] +Via[92500 132000 4000 2000 0 2000 "" ""] +Via[260000 15000 13200 2000 11000 12800 "" "hole"] +Via[260000 235000 13200 2000 11000 12800 "" "hole"] +Via[82000 199000 4000 2000 0 2000 "" "thermal(1)"] +Via[55000 55000 13200 2000 11000 12800 "" "hole"] +Via[223000 113000 4000 2000 0 2000 "" "thermal(1)"] +Via[141499 133398 4000 2000 0 2000 "" "auto"] +Via[85000 115000 4000 2000 0 2000 "" "thermal(1)"] +Via[202500 120500 4000 2000 0 2000 "" ""] +Via[106000 123000 4000 2000 0 2000 "" "auto"] +Via[141499 139901 4000 2000 0 2000 "" "auto"] +Via[165500 79000 4000 2000 0 2000 "" "thermal(1)"] +Via[156792 122699 4000 2000 0 2000 "" "auto"] +Via[159900 135400 4000 2000 0 2000 "" "auto"] +Via[123500 127000 4000 2000 0 2000 "" ""] +Via[99500 141000 4000 2000 0 2000 "" ""] +Via[109500 127000 4000 2000 0 2000 "" ""] +Via[87000 91500 4000 2000 0 2000 "" "thermal(1)"] +Via[188000 74000 4000 2000 0 2000 "" ""] +Via[194000 74000 4000 2000 0 2000 "" ""] +Via[211000 74000 4000 2000 0 2000 "" ""] +Via[216000 77000 4000 2000 0 2000 "" ""] +Via[196000 162000 4000 2000 0 2000 "" "thermal(1)"] +Via[224000 195000 4000 2000 0 2000 "" "thermal(1)"] +Via[157000 196000 4000 2000 0 2000 "" "thermal(1)"] +Via[159000 189000 4000 2000 0 2000 "" "usetherm,thermal(2)"] +Via[226000 188000 4000 2000 0 2000 "" "usetherm,thermal(2)"] +Via[198000 186000 4000 2000 0 2000 "" "usetherm,thermal(2)"] +Via[206000 178000 3600 2000 0 2000 "" ""] +Via[229000 199000 3600 2000 0 2000 "" ""] +Via[128000 183000 3600 2000 0 2000 "" ""] +Via[137000 176000 3600 2000 0 2000 "" ""] +Via[191000 231000 3600 2000 0 2000 "" "thermal(2)"] + +Element["" "0603" "R3" "49.9" 167000 209000 6000 -2000 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "R32" "24.9" 245000 217000 4000 -1200 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["onsolder" "PMC-REVERSE" "J2" "unknown" 94993 95811 -18000 9000 0 100 "auto"] +( + Pin[-6693 7189 7200 2000 7200 5800 "" "1" "hole,edge2"] + Pin[128740 7189 7200 2000 7200 5800 "" "2" "hole,edge2"] + Pad[0 9900 0 19000 2400 1000 3400 "" "1" "auto,edge2"] + Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" "auto"] + Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" "auto,edge2"] + Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" "auto,edge2"] + Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" "auto,edge2"] + Pad[0 -4622 0 4478 2400 1000 3400 "" "2" "auto"] + Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" "auto,edge2"] + Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" "auto"] + Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" "auto,edge2"] + Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" "auto"] + Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" "auto,edge2"] + Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" "auto"] + Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" "auto,edge2"] + Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" "auto"] + Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" "auto,edge2"] + Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" "auto"] + Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" "auto,edge2"] + Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" "auto"] + Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" "auto,edge2"] + Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" "auto"] + Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" "auto"] + Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" "auto"] + Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" "auto"] + Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" "auto"] + Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" "auto"] + Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" "auto"] + Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" "auto"] + Pad[62992 -4622 62992 4478 2400 1000 3400 "" "34" "auto"] + Pad[66929 -4622 66929 4478 2400 1000 3400 "" "36" "auto"] + Pad[70866 -4622 70866 4478 2400 1000 3400 "" "38" "auto"] + Pad[74803 -4622 74803 4478 2400 1000 3400 "" "40" "auto"] + Pad[78740 -4622 78740 4478 2400 1000 3400 "" "42" "auto"] + Pad[82677 -4622 82677 4478 2400 1000 3400 "" "44" "auto"] + Pad[86614 -4622 86614 4478 2400 1000 3400 "" "46" "auto"] + Pad[90551 -4622 90551 4478 2400 1000 3400 "" "48" "auto"] + Pad[98425 -4622 98425 4478 2400 1000 3400 "" "52" "auto"] + Pad[94488 -4622 94488 4478 2400 1000 3400 "" "50" "auto"] + Pad[102362 -4622 102362 4478 2400 1000 3400 "" "54" "auto"] + Pad[106299 -4622 106299 4478 2400 1000 3400 "" "56" "auto"] + Pad[110236 -4622 110236 4478 2400 1000 3400 "" "58" "auto"] + Pad[114173 -4622 114173 4478 2400 1000 3400 "" "60" "auto"] + Pad[3937 -4622 3937 4478 2400 1000 3400 "" "4" "auto"] + Pad[43307 9900 43307 19000 2400 1000 3400 "" "23" "auto,edge2"] + Pad[47244 9900 47244 19000 2400 1000 3400 "" "25" "auto,edge2"] + Pad[51181 9900 51181 19000 2400 1000 3400 "" "27" "auto,edge2"] + Pad[55118 9900 55118 19000 2400 1000 3400 "" "29" "auto,edge2"] + Pad[59055 9900 59055 19000 2400 1000 3400 "" "31" "auto,edge2"] + Pad[62992 9900 62992 19000 2400 1000 3400 "" "33" "auto,edge2"] + Pad[66929 9900 66929 19000 2400 1000 3400 "" "35" "auto,edge2"] + Pad[70866 9900 70866 19000 2400 1000 3400 "" "37" "auto,edge2"] + Pad[74803 9900 74803 19000 2400 1000 3400 "" "39" "auto,edge2"] + Pad[78740 9900 78740 19000 2400 1000 3400 "" "41" "auto,edge2"] + Pad[82677 9900 82677 19000 2400 1000 3400 "" "43" "auto,edge2"] + Pad[86614 9900 86614 19000 2400 1000 3400 "" "45" "auto,edge2"] + Pad[90551 9900 90551 19000 2400 1000 3400 "" "47" "auto,edge2"] + Pad[94488 9900 94488 19000 2400 1000 3400 "" "49" "auto,edge2"] + Pad[98425 9900 98425 19000 2400 1000 3400 "" "51" "auto,edge2"] + Pad[102362 9900 102362 19000 2400 1000 3400 "" "53" "auto,edge2"] + Pad[106299 9900 106299 19000 2400 1000 3400 "" "55" "auto,edge2"] + Pad[110236 9900 110236 19000 2400 1000 3400 "" "57" "auto,edge2"] + Pad[114173 9900 114173 19000 2400 1000 3400 "" "59" "auto,edge2"] + Pad[118110 9900 118110 19000 2400 1000 3400 "" "61" "auto,edge2"] + Pad[122047 9900 122047 19000 2400 1000 3400 "" "63" "auto,edge2"] + Pad[118110 -4622 118110 4478 2400 1000 3400 "" "62" "auto"] + ElementLine [134000 -9000 134000 24000 1000] + ElementLine [-11000 24000 134000 24000 1000] + ElementLine [-11000 -9000 134000 -9000 1000] + ElementLine [-11000 -9000 -11000 24000 1000] + + ) + +Element["" "0603" "R10" "49.9" 218000 170500 4500 5000 1 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "CONNECTOR-10-2" "J15" "unknown" 77000 40500 -17200 -13200 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square,edge2"] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" "edge2"] + Pin[10000 0 6000 3000 6600 4000 "3" "3" "edge2"] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" "edge2"] + Pin[20000 0 6000 3000 6600 4000 "5" "5" "edge2"] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" "edge2"] + Pin[30000 0 6000 3000 6600 4000 "7" "7" "edge2"] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" "edge2"] + Pin[40000 0 6000 3000 6600 4000 "9" "9" "edge2"] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" "edge2"] + Pin[50000 0 6000 3000 6600 4000 "11" "11" "edge2"] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" "edge2"] + Pin[60000 0 6000 3000 6600 4000 "13" "13" "edge2"] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" "edge2"] + Pin[70000 0 6000 3000 6600 4000 "15" "15" "edge2"] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" "edge2"] + Pin[80000 0 6000 3000 6600 4000 "17" "17" "edge2"] + Pin[80000 -10000 6000 3000 6600 4000 "18" "18" "edge2"] + Pin[90000 0 6000 3000 6600 4000 "19" "19" "edge2"] + Pin[90000 -10000 6000 3000 6600 4000 "20" "20" "edge2,thermal(1)"] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 95000 -15000 2000] + ElementLine [95000 -15000 95000 5000 2000] + ElementLine [-5000 5000 95000 5000 2000] + + ) + +Element["" "CONNECTOR-5-2" "J17" "unknown" 183500 137500 49000 -12000 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square,usetherm,edge2,thermal(2)"] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" "edge2"] + Pin[10000 0 6000 3000 6600 4000 "3" "3" "edge2"] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" "edge2"] + Pin[20000 0 6000 3000 6600 4000 "5" "5" "edge2"] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" "edge2"] + Pin[30000 0 6000 3000 6600 4000 "7" "7" "edge2"] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" "edge2"] + Pin[40000 0 6000 3000 6600 4000 "9" "9" "edge2,thermal(1)"] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" "edge2,thermal(1)"] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 45000 -15000 2000] + ElementLine [45000 -15000 45000 5000 2000] + ElementLine [-5000 5000 45000 5000 2000] + + ) + +Element["" "SMA_VERT" "J18" "unknown" 160500 231500 17000 12000 0 100 ""] +( + Pin[0 0 9000 3000 9000 6000 "1" "1" ""] + Pin[-10000 -10000 9000 3000 9000 6000 "2" "2" "thermal(1,6)"] + Pin[10000 -10000 9000 3000 9000 6000 "3" "3" "thermal(1,6)"] + Pin[-10000 10000 9000 3000 9000 6000 "4" "4" "thermal(1,6)"] + Pin[10000 10000 9000 3000 9000 6000 "5" "5" "thermal(1,6)"] + ElementLine [-16000 -16000 16000 -16000 1000] + ElementLine [-16000 -16000 -16000 16000 1000] + ElementLine [-16000 16000 16000 16000 1000] + ElementLine [16000 -16000 16000 16000 1000] + + ) + +Element["" "SMA_VERT" "J19" "unknown" 223500 231500 18000 11000 0 100 ""] +( + Pin[0 0 9000 3000 9000 6000 "1" "1" ""] + Pin[-10000 -10000 9000 3000 9000 6000 "2" "2" "thermal(1,6)"] + Pin[10000 -10000 9000 3000 9000 6000 "3" "3" "thermal(1,6)"] + Pin[-10000 10000 9000 3000 9000 6000 "4" "4" "thermal(1,6)"] + Pin[10000 10000 9000 3000 9000 6000 "5" "5" "thermal(1,6)"] + ElementLine [-16000 -16000 16000 -16000 1000] + ElementLine [-16000 -16000 -16000 16000 1000] + ElementLine [-16000 16000 16000 16000 1000] + ElementLine [16000 -16000 16000 16000 1000] + + ) + +Element["" "0603" "R5" "49.9" 166000 174000 3500 -3000 0 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R11" "49.9" 231000 171000 5000 3500 1 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["onsolder" "0603" "C25" "82pF" 216000 81000 -3000 -4500 0 100 "auto"] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 2700 4200 -2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element["onsolder" "0603" "C26" "82pF" 206000 81000 -4000 -4000 0 100 "auto"] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 2700 4200 -2700 600] + + ) + +Element["" "0603" "R9" "49.9" 229000 211000 5000 -1500 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "C24" ".1uF" 197000 175000 3000 -9000 0 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element["" "0603" "R6" "1K" 188500 179500 -10500 -4000 0 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R7" "1K" 189000 170000 -5500 -10000 0 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R4" "49.9" 158000 174000 -10500 1500 0 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["onsolder" "0603" "C22" "82pF" 186000 81000 -6500 -4500 0 100 "auto"] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 2700 4200 -2700 600] + + ) + +Element["" "0603" "R28" "0" 120000 184000 -6500 4500 0 100 ""] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" "selected,square"] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "CONNECTOR-8-2" "J16" "unknown" 70500 162500 -16000 -9000 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square,edge2"] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" "edge2,thermal(1)"] + Pin[10000 0 6000 3000 6600 4000 "3" "3" "edge2"] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" "edge2,thermal(1)"] + Pin[20000 0 6000 3000 6600 4000 "5" "5" "edge2"] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" "edge2"] + Pin[30000 0 6000 3000 6600 4000 "7" "7" "edge2"] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" "edge2"] + Pin[40000 0 6000 3000 6600 4000 "9" "9" "edge2"] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" "edge2"] + Pin[50000 0 6000 3000 6600 4000 "11" "11" "edge2"] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" "edge2"] + Pin[60000 0 6000 3000 6600 4000 "13" "13" "edge2"] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" "edge2"] + Pin[70000 0 6000 3000 6600 4000 "15" "15" "edge2"] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" "edge2,thermal(1)"] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 75000 -15000 2000] + ElementLine [75000 -15000 75000 5000 2000] + ElementLine [-5000 5000 75000 5000 2000] + + ) + +Element["" "0603" "R37" "348" 156000 209000 -16000 -2200 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "CONNECTOR-8-2" "J24" "unknown" 10500 132500 19800 -3100 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square"] + Pin[10000 0 6000 3000 6600 4000 "2" "2" "thermal(1)"] + Pin[0 10000 6000 3000 6600 4000 "3" "3" ""] + Pin[10000 10000 6000 3000 6600 4000 "4" "4" "thermal(1)"] + Pin[0 20000 6000 3000 6600 4000 "5" "5" ""] + Pin[10000 20000 6000 3000 6600 4000 "6" "6" "thermal(1)"] + Pin[0 30000 6000 3000 6600 4000 "7" "7" ""] + Pin[10000 30000 6000 3000 6600 4000 "8" "8" "thermal(1)"] + Pin[0 40000 6000 3000 6600 4000 "9" "9" ""] + Pin[10000 40000 6000 3000 6600 4000 "10" "10" "thermal(1)"] + Pin[0 50000 6000 3000 6600 4000 "11" "11" ""] + Pin[10000 50000 6000 3000 6600 4000 "12" "12" "thermal(1)"] + Pin[0 60000 6000 3000 6600 4000 "13" "13" ""] + Pin[10000 60000 6000 3000 6600 4000 "14" "14" "thermal(1)"] + Pin[0 70000 6000 3000 6600 4000 "15" "15" ""] + Pin[10000 70000 6000 3000 6600 4000 "16" "16" "thermal(1)"] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 5000 5000 5000 1000] + ElementLine [-5000 -5000 15000 -5000 2000] + ElementLine [15000 -5000 15000 75000 2000] + ElementLine [-5000 75000 15000 75000 2000] + ElementLine [-5000 -5000 -5000 75000 2000] + + ) + +Element["" "CONNECTOR-8-2" "J25" "unknown" 11000 15000 19200 -2600 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square"] + Pin[10000 0 6000 3000 6600 4000 "2" "2" "thermal(1)"] + Pin[0 10000 6000 3000 6600 4000 "3" "3" ""] + Pin[10000 10000 6000 3000 6600 4000 "4" "4" "thermal(1)"] + Pin[0 20000 6000 3000 6600 4000 "5" "5" ""] + Pin[10000 20000 6000 3000 6600 4000 "6" "6" "thermal(1)"] + Pin[0 30000 6000 3000 6600 4000 "7" "7" ""] + Pin[10000 30000 6000 3000 6600 4000 "8" "8" "thermal(1)"] + Pin[0 40000 6000 3000 6600 4000 "9" "9" ""] + Pin[10000 40000 6000 3000 6600 4000 "10" "10" "thermal(1)"] + Pin[0 50000 6000 3000 6600 4000 "11" "11" ""] + Pin[10000 50000 6000 3000 6600 4000 "12" "12" "thermal(1)"] + Pin[0 60000 6000 3000 6600 4000 "13" "13" ""] + Pin[10000 60000 6000 3000 6600 4000 "14" "14" "thermal(1)"] + Pin[0 70000 6000 3000 6600 4000 "15" "15" ""] + Pin[10000 70000 6000 3000 6600 4000 "16" "16" "thermal(1)"] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 5000 5000 5000 1000] + ElementLine [-5000 -5000 15000 -5000 2000] + ElementLine [15000 -5000 15000 75000 2000] + ElementLine [-5000 75000 15000 75000 2000] + ElementLine [-5000 -5000 -5000 75000 2000] + + ) + +Element["" "0603" "R33" "348" 245000 208000 4000 -1200 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R34" "348" 246000 193000 5000 -2200 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "SO8" "U1" "unknown" 88500 179000 18000 20000 0 100 ""] +( + Pad[-1900 0 900 0 2000 3000 2000 "1" "1" ""] + Pad[-1900 5000 900 5000 2000 3000 2000 "2" "2" "square"] + Pad[-1900 10000 900 10000 2000 3000 2000 "3" "3" "square"] + Pad[-1900 15000 900 15000 2000 3000 2000 "4" "4" "square"] + Pad[18500 15000 21300 15000 2000 3000 2000 "5" "5" "square,edge2"] + Pad[18500 10000 21300 10000 2000 3000 2000 "6" "6" "square,edge2"] + Pad[18500 5000 21300 5000 2000 3000 2000 "7" "7" "square,edge2"] + Pad[18500 0 21300 0 2000 3000 2000 "8" "8" "square,edge2"] + ElementLine [-2900 -2500 -2900 17500 1000] + ElementLine [-2900 17500 22300 17500 1000] + ElementLine [22300 -2500 22300 17500 1000] + ElementLine [7200 -2500 22300 -2500 1000] + ElementLine [-2900 -2500 12200 -2500 1000] + ElementArc [9700 -2500 2500 2500 0 180 1000] + + ) + +Element["" "SO8" "U2" "unknown" 225000 194000 -3000 -15000 0 100 ""] +( + Pad[7000 7500 13500 7500 2000 1000 3000 "1" "1" "square,edge2"] + Pad[7000 2500 13500 2500 2000 1000 3000 "2" "2" "square,edge2"] + Pad[7000 -2500 13500 -2500 2000 1000 3000 "3" "3" "square,edge2"] + Pad[7000 -7500 13500 -7500 2000 1000 3000 "4" "4" "square,edge2"] + Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "5" "5" "square"] + Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "6" "6" "square"] + Pad[-13500 2500 -7000 2500 2000 1000 3000 "7" "7" "square"] + Pad[-13500 7500 -7000 7500 2000 1000 3000 "8" "8" "square"] + ElementLine [-15500 9500 -2500 9500 1000] + ElementLine [2500 9500 15500 9500 1000] + ElementLine [-15500 -9500 -15500 9500 1000] + ElementLine [-15500 -9500 15500 -9500 1000] + ElementLine [15500 -9500 15500 9500 1000] + ElementArc [0 9500 2500 2500 180 180 1000] + + ) + +Element["" "0603" "R30" "348" 218000 211000 -15000 -1200 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["onsolder" "0603" "C23" "82pF" 196000 81000 -5000 -4500 0 100 "auto"] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 2700 4200 -2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element["" "0603" "R31" "348" 205000 194000 -12000 -4200 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R36" "348" 184000 209000 4000 -2200 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R38" "348" 139000 196000 -8200 4000 1 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R39" "348" 178000 195000 3000 800 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "SO8" "U3" "unknown" 158000 195000 -3000 -14000 0 100 ""] +( + Pad[7000 7500 13500 7500 2000 1000 3000 "1" "1" "square,edge2"] + Pad[7000 2500 13500 2500 2000 1000 3000 "2" "2" "square,edge2"] + Pad[7000 -2500 13500 -2500 2000 1000 3000 "3" "3" "square,edge2"] + Pad[7000 -7500 13500 -7500 2000 1000 3000 "4" "4" "square,edge2"] + Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "5" "5" "square"] + Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "6" "6" "square"] + Pad[-13500 2500 -7000 2500 2000 1000 3000 "7" "7" "square"] + Pad[-13500 7500 -7000 7500 2000 1000 3000 "8" "8" "square"] + ElementLine [-15500 9500 -2500 9500 1000] + ElementLine [2500 9500 15500 9500 1000] + ElementLine [-15500 -9500 -15500 9500 1000] + ElementLine [-15500 -9500 15500 -9500 1000] + ElementLine [15500 -9500 15500 9500 1000] + ElementArc [0 9500 2500 2500 180 180 1000] + + ) + +Element["" "0603" "R35" "24.9" 184000 219400 4000 -2200 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "C50" ".1uF" 184000 229000 -2000 6800 0 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "found,square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) +Layer(1 "solder") +( + Line[197355 100289 197500 100616 1000 2000 ""] + Line[141499 139901 141499 139901 1000 1000 "auto"] + Line[223000 113000 217040 112811 1000 2000 ""] + Line[165493 90823 165500 79500 1000 2000 ""] + Line[225000 191000 229000 195000 800 2000 "clearline"] + Line[130426 114811 130433 115000 1000 1000 "auto"] + Line[94871 91311 87000 91500 1000 2000 ""] + Line[156792 122699 156792 122699 1000 1000 "auto"] + Line[20500 202500 23000 200000 1000 2000 "clearline"] + Line[140500 162500 140500 162500 1000 1000 "auto"] + Line[165859 114811 165859 91311 1000 2000 ""] + Line[219000 191000 225000 191000 800 2000 "clearline"] + Line[94993 114811 85000 115000 1000 2000 ""] + Line[161993 114811 161500 114500 1000 2000 ""] + Line[142237 114811 142500 115256 1000 2000 ""] + Line[177500 131500 177500 130500 1000 2000 ""] + Line[107199 148000 107199 148000 1000 1000 "auto"] + Line[73000 162500 71000 162500 1000 2000 "clearline"] + Line[92500 132000 102500 122000 1000 2000 ""] + Line[183500 137500 177500 131500 1000 2000 ""] + Line[177670 114811 177677 142177 1000 2000 ""] + Line[102500 122000 102500 120000 1000 2000 ""] + Line[94993 91189 94993 114811 1000 2000 ""] + Line[189493 114811 189500 121500 1000 2000 ""] + Line[189500 121500 183500 127500 1000 2000 ""] + Line[193493 114811 193500 127500 1000 2000 ""] + Line[197493 115311 197500 121500 1000 2000 ""] + Line[197500 121500 203500 127500 1000 2000 ""] + Line[212993 114811 213000 117500 1000 2000 ""] + Line[213000 118000 215500 120500 1000 2000 ""] + Line[215500 120500 224500 120500 1000 2000 ""] + Line[224500 120500 229500 125500 1000 2000 ""] + Line[229500 125500 229500 139000 1000 2000 ""] + Line[229500 139000 224500 144000 1000 2000 ""] + Line[224500 144000 220000 144000 1000 2000 ""] + Line[220000 144000 213500 137500 1000 2000 ""] + Line[204993 114811 205000 116500 1000 2000 ""] + Line[204993 116311 208500 120000 1000 2000 ""] + Line[201493 114811 201500 119500 1000 2000 ""] + Line[208500 120000 208500 130000 1000 2000 ""] + Line[208500 130000 205500 132500 1000 2000 ""] + Line[205500 132500 198500 132500 1000 2000 ""] + Line[198500 132500 193500 137500 1000 2000 ""] + Line[208993 114811 209000 117000 1000 2000 ""] + Line[209000 117000 209500 117500 1000 2000 ""] + Line[209500 117500 209500 118000 1000 2000 ""] + Line[209500 118000 214500 123000 1000 2000 ""] + Line[214500 123000 216000 123000 1000 2000 ""] + Line[216000 123000 218500 125500 1000 2000 ""] + Line[218500 125500 218500 130500 1000 2000 ""] + Line[218500 130500 216500 132500 1000 2000 ""] + Line[216500 132500 210500 132500 1000 2000 ""] + Line[201500 119500 202500 120500 1000 2000 ""] + Line[210500 132500 208500 133500 1000 2000 ""] + Line[208500 133500 204500 137500 1000 2000 ""] + Line[87000 30500 87000 31000 1000 2000 ""] + Line[87000 31000 92000 36000 1000 2000 ""] + Line[92000 36000 92000 74500 1000 2000 ""] + Line[92000 74500 102500 85000 1000 2000 ""] + Line[102500 85000 102493 92811 1000 2000 ""] + Line[97000 40500 97000 76000 1000 2000 ""] + Line[97000 76000 106500 85500 1000 2000 ""] + Line[106500 85500 106493 92311 1000 2000 ""] + Line[106493 92311 107000 93000 1000 2000 ""] + Line[97000 30500 97500 30500 1000 2000 ""] + Line[97500 30500 102000 35000 1000 2000 ""] + Line[102000 35000 102000 76000 1000 2000 ""] + Line[102000 76000 110500 84500 1000 2000 ""] + Line[110500 84500 110493 92311 1000 2000 ""] + Line[110493 92311 111000 93000 1000 2000 ""] + Line[107000 40500 107000 74500 1000 2000 ""] + Line[107000 74500 107500 75000 1000 2000 ""] + Line[107500 75000 114500 82000 1000 2000 ""] + Line[114500 82000 114493 91811 1000 2000 ""] + Line[107000 30500 112000 35500 1000 2000 ""] + Line[112000 35500 112000 74500 1000 2000 ""] + Line[112000 74500 118500 81000 1000 2000 ""] + Line[118500 81000 118493 91811 1000 2000 ""] + Line[118493 91811 119500 93000 1000 2000 ""] + Line[117000 40000 117000 40500 1000 2000 ""] + Line[117000 74500 122500 80000 1000 2000 ""] + Line[122500 80000 122493 92311 1000 2000 ""] + Line[117000 30500 122000 35500 1000 2000 ""] + Line[122000 35500 122000 74000 1000 2000 ""] + Line[122000 74000 126500 78500 1000 2000 ""] + Line[126500 78500 126493 92311 1000 2000 ""] + Line[126493 92311 127000 93000 1000 2000 ""] + Line[127000 41000 127000 73500 1000 2000 ""] + Line[127000 73500 130500 77000 1000 2000 ""] + Line[130500 77000 130493 95811 1000 2000 ""] + Line[127000 30500 127000 31000 1000 2000 ""] + Line[127000 31000 132000 36000 1000 2000 ""] + Line[132000 36000 132000 73500 1000 2000 ""] + Line[132000 73500 134500 76000 1000 2000 ""] + Line[134500 76000 134493 92311 1000 2000 ""] + Line[134493 92311 135000 93000 1000 2000 ""] + Line[134993 92811 134500 93000 1000 2000 ""] + Line[137000 40500 136993 89811 1000 2000 ""] + Line[136993 89811 138000 91000 1000 2000 ""] + Line[137000 30500 141500 35000 1000 2000 ""] + Line[141500 35000 141493 91311 1000 2000 ""] + Line[147000 41000 145500 42500 1000 2000 ""] + Line[145500 42500 145493 91811 1000 2000 ""] + Line[145493 91811 146000 92000 1000 2000 ""] + Line[147000 30500 147500 30500 1000 2000 ""] + Line[147500 30500 151500 34500 1000 2000 ""] + Line[151500 34500 151500 53000 1000 2000 ""] + Line[151500 53000 148500 56000 1000 2000 ""] + Line[148500 56000 148500 89500 1000 2000 ""] + Line[148500 89500 149993 90811 1000 2000 ""] + Line[157000 40500 157000 56500 1000 2000 ""] + Line[157000 56500 154000 59500 1000 2000 ""] + Line[154000 59500 153993 93311 1000 2000 ""] + Line[157000 30500 157000 31000 1000 2000 ""] + Line[157000 31000 162000 36000 1000 2000 ""] + Line[162000 36000 162000 59500 1000 2000 ""] + Line[162000 59500 158000 63500 1000 2000 ""] + Line[158000 63500 157993 91311 1000 2000 ""] + Line[161993 91811 162000 64500 1000 2000 ""] + Line[162000 64500 167000 59500 1000 2000 ""] + Line[167000 59500 167000 41000 1000 2000 ""] + Line[102993 114811 98930 114811 1000 2000 ""] + Line[98493 114811 98500 121000 1000 2000 ""] + Line[134363 114811 134500 115130 1000 2000 ""] + Line[94993 91189 94878 91500 1000 2000 ""] + Line[98500 121000 75500 144000 1000 2000 ""] + Line[75500 144000 75500 156500 1000 2000 ""] + Line[75500 156500 80500 161500 1000 2000 ""] + Line[80500 161500 80500 162500 1000 2000 ""] + Line[106000 123000 115000 123000 1000 1000 "auto"] + Line[102867 114811 103000 115000 1000 2000 ""] + Line[90500 152500 92699 152500 1000 1000 "auto"] + Line[12000 15500 11000 15500 1000 2000 ""] + Line[99199 146000 99697 146000 1000 1000 "auto"] + Line[167000 40500 167000 41000 1000 2000 ""] + Line[17000 10500 12000 15500 1000 2000 ""] + Line[137992 115119 138307 115000 1000 1000 "auto"] + Line[137992 115119 137999 117200 1000 1000 "auto"] + Line[67000 10500 17000 10500 1000 2000 ""] + Line[106000 149199 106000 158000 1000 1000 "auto"] + Line[87000 30500 67000 10500 1000 2000 ""] + Line[145500 42500 145500 40500 1000 2000 ""] + Line[141499 139901 141500 139900 1000 1000 "auto"] + Line[202172 103000 205229 99747 1000 2000 ""] + Line[146174 114811 146181 141900 1000 1000 "auto"] + Line[145000 143081 146181 141900 1000 1000 "auto"] + Line[145000 143081 145000 158000 1000 1000 "auto"] + Line[185500 103000 202172 103000 1000 2000 ""] + Line[157985 114811 157992 121499 1000 1000 "auto"] + Line[185544 100289 185544 108811 1000 2000 ""] + Line[161922 114811 161929 133399 1000 1000 "auto"] + Line[161929 133399 160692 134636 1000 1000 "auto"] + Line[106493 115811 106500 115000 1000 2000 ""] + Line[106493 114811 110493 114811 1000 2000 ""] + Line[165859 91189 165500 91012 1000 2000 ""] + Line[141500 139900 141500 139900 1000 1000 "auto"] + Line[197500 103000 217000 103000 1000 2000 ""] + Line[197493 100427 197500 103000 1000 2000 ""] + Line[55000 55000 57000 55000 1000 1000 ""] + Line[145500 40500 147000 40500 1000 2000 ""] + Line[213103 91311 213000 91500 1000 2000 ""] + Line[213103 114811 213000 115000 1000 2000 ""] + Line[209166 114811 209000 115000 1000 2000 ""] + Line[204993 116311 205000 115000 1000 2000 ""] + Line[204993 114811 205236 115000 1000 2000 ""] + Line[201292 114811 201500 115000 1000 2000 ""] + Line[147000 40500 147000 41000 1000 2000 ""] + Line[197355 115311 197500 115500 1000 2000 ""] + Line[193418 114811 193500 115000 1000 2000 ""] + Line[189481 114811 189500 115000 1000 2000 ""] + Line[127000 40500 127000 41000 1000 2000 ""] + Line[161686 114311 161500 114500 1000 1000 "auto"] + Line[161922 114811 162000 115000 1000 1000 "auto"] + Line[117000 40500 117000 40000 1000 2000 ""] + Line[142237 115067 142500 115256 1000 2000 ""] + Line[203500 137500 204500 137500 1000 2000 ""] + Line[209166 92811 209000 93000 1000 2000 ""] + Line[80500 162500 80500 163000 1000 2000 ""] + Line[217040 91189 217040 114311 1000 2000 ""] + Line[142237 115067 142244 139156 1000 1000 "auto"] + Line[189481 92311 189500 92500 1000 2000 ""] + Line[80500 162500 80500 163000 1000 2000 ""] + Line[193418 91811 193000 92000 1000 2000 ""] + Line[98500 121000 98500 121500 1000 2000 ""] + Line[161922 91811 162000 92000 1000 2000 ""] + Line[98930 114811 98500 115000 1000 2000 ""] + Line[157985 91311 158000 91500 1000 2000 ""] + Line[117000 40500 117000 74500 1000 2000 ""] + Line[154048 93311 154000 93500 1000 2000 ""] + Line[161922 114547 161693 114500 1000 1000 "auto"] + Line[150111 90811 150000 91000 1000 2000 ""] + Line[102500 120000 106493 115811 1000 2000 ""] + Line[146174 91811 146000 92000 1000 2000 ""] + Line[157992 121499 156792 122699 1000 1000 "auto"] + Line[142237 91311 141500 91500 1000 2000 ""] + Line[145000 158000 140500 162500 1000 1000 "auto"] + Line[138300 90811 138000 91000 1000 2000 ""] + Line[229000 195000 229000 199000 800 2000 "clearline"] + Line[134363 92811 134500 93000 1000 2000 ""] + Line[142244 139156 141500 139900 1000 1000 "auto"] + Line[130426 95811 130500 96000 1000 2000 ""] + Line[106000 158000 110500 162500 1000 1000 "auto"] + Line[126489 92811 127000 93000 1000 2000 ""] + Line[107199 148000 106000 149199 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"3.3VA" ""] + Text[192000 120000 1 100 "DAC_A" ""] + Text[201000 119000 1 100 "DAC_B" ""] + Text[208000 144000 0 56 "ADC_B1" ""] + Text[194000 156000 1 56 "ADCREF" ""] + Text[225000 121000 1 78 "AGND" ""] + Text[80000 245000 0 100 "" ""] + Text[33000 240000 0 130 "(c) 2006 Ettus Research LLC" ""] + Text[32000 232000 0 130 "DC-50 MHz Receiver" ""] + Text[33000 220000 0 200 "LFRX" ""] +) +NetList() +( + Net("5V" "(unknown)") + ( + Connect("J2-3") + Connect("J2-5") + Connect("J16-3") + ) + Net("AGND" "(unknown)") + ( + Connect("C22-2") + Connect("C23-2") + Connect("C24-2") + Connect("C25-2") + Connect("C26-2") + Connect("C50-2") + Connect("J2-41") + Connect("J2-42") + Connect("J2-47") + Connect("J2-48") + Connect("J2-54") + Connect("J2-58") + Connect("J2-63") + Connect("J2-64") + Connect("J17-9") + Connect("J17-10") + Connect("J18-2") + Connect("J18-3") + Connect("J18-4") + Connect("J18-5") + Connect("J19-2") + Connect("J19-3") + Connect("J19-4") + Connect("J19-5") + Connect("R3-2") + Connect("R7-2") + Connect("R9-2") + Connect("R32-1") + Connect("R35-1") + Connect("U2-6") + Connect("U3-6") + ) + Net("AUX_ADC_A1" "(unknown)") + ( + Connect("J2-59") + Connect("J17-5") + ) + Net("AUX_ADC_B1" "(unknown)") + ( + Connect("J2-61") + Connect("J17-7") + ) + Net("AUX_ADC_REF" "(unknown)") + ( + Connect("J2-57") + Connect("J17-3") + ) + Net("AUX_DAC_A" "(unknown)") + ( + Connect("J2-51") + Connect("J17-4") + ) + Net("AUX_DAC_B" "(unknown)") + ( + Connect("J2-53") + Connect("J17-6") + ) + Net("AUX_DAC_C" "(unknown)") + ( + Connect("J2-55") + Connect("J17-8") + ) + Net("AUX_DAC_D" "(unknown)") + ( + Connect("J2-49") + Connect("J17-2") + ) + Net("AVDD" "(unknown)") + ( + Connect("C50-1") + Connect("J2-43") + Connect("J2-44") + Connect("J2-45") + Connect("J2-46") + Connect("J17-1") + Connect("R6-1") + Connect("U2-3") + Connect("U3-3") + ) + Net("CLKOUT1" "(unknown)") + ( + Connect("J2-11") + ) + Net("CLKOUT2" "(unknown)") + ( + Connect("J2-13") + ) + Net("DVDD" "(unknown)") + ( + Connect("J2-7") + Connect("J2-9") + Connect("J16-1") + Connect("U1-3") + Connect("U1-8") + ) + Net("GND" "(unknown)") + ( + Connect("J2-1") + Connect("J2-2") + Connect("J2-37") + Connect("J2-38") + Connect("J15-20") + Connect("J16-2") + Connect("J16-4") + Connect("J16-16") + Connect("J24-2") + Connect("J24-4") + Connect("J24-6") + Connect("J24-8") + Connect("J24-10") + Connect("J24-12") + Connect("J24-14") + Connect("J24-16") + Connect("J25-2") + Connect("J25-4") + Connect("J25-6") + Connect("J25-8") + Connect("J25-10") + Connect("J25-12") + Connect("J25-14") + Connect("J25-16") + Connect("R28-1") + Connect("U1-4") + ) + Net("I2C_A0" "(unknown)") + ( + Connect("J2-21") + Connect("J16-5") + Connect("U1-1") + ) + Net("I2C_A1" "(unknown)") + ( + Connect("J2-19") + Connect("J16-6") + Connect("U1-2") + ) + Net("io_rx_00" "(unknown)") + ( + Connect("J2-36") + Connect("J15-19") + Connect("J24-15") + ) + Net("io_rx_01" "(unknown)") + ( + Connect("J2-34") + Connect("J15-18") + Connect("J24-13") + ) + Net("io_rx_02" "(unknown)") + ( + Connect("J2-32") + Connect("J15-17") + Connect("J24-11") + ) + Net("io_rx_03" "(unknown)") + ( + Connect("J2-30") + Connect("J15-16") + Connect("J24-9") + ) + Net("io_rx_04" "(unknown)") + ( + Connect("J2-28") + Connect("J15-15") + Connect("J24-7") + ) + Net("io_rx_05" "(unknown)") + ( + Connect("J2-26") + Connect("J15-14") + Connect("J24-5") + ) + Net("io_rx_06" "(unknown)") + ( + Connect("J2-24") + Connect("J15-13") + Connect("J24-3") + ) + Net("io_rx_07" "(unknown)") + ( + Connect("J2-22") + Connect("J15-12") + Connect("J24-1") + ) + Net("io_rx_08" "(unknown)") + ( + Connect("J2-20") + Connect("J15-11") + Connect("J25-15") + ) + Net("io_rx_09" "(unknown)") + ( + Connect("J2-18") + Connect("J15-10") + Connect("J25-13") + ) + Net("io_rx_10" "(unknown)") + ( + Connect("J2-16") + Connect("J15-9") + Connect("J25-11") + ) + Net("io_rx_11" "(unknown)") + ( + Connect("J2-14") + Connect("J15-8") + Connect("J25-9") + ) + Net("io_rx_12" "(unknown)") + ( + Connect("J2-12") + Connect("J15-7") + Connect("J25-7") + ) + Net("io_rx_13" "(unknown)") + ( + Connect("J2-10") + Connect("J15-6") + Connect("J25-5") + ) + Net("io_rx_14" "(unknown)") + ( + Connect("J2-8") + Connect("J15-5") + Connect("J25-3") + ) + Net("io_rx_15" "(unknown)") + ( + Connect("J2-6") + Connect("J15-4") + Connect("J25-1") + ) + Net("RESET" "(unknown)") + ( + Connect("J2-27") + Connect("J16-15") + ) + Net("RS232_RXD" "(unknown)") + ( + Connect("J2-25") + Connect("J16-10") + ) + Net("RS232_TXD" "(unknown)") + ( + Connect("J2-23") + Connect("J16-9") + ) + Net("SCL" "(unknown)") + ( + Connect("J2-15") + Connect("J16-7") + Connect("U1-6") + ) + Net("SCLK" "(unknown)") + ( + Connect("J2-29") + Connect("J16-12") + ) + Net("SDA" "(unknown)") + ( + Connect("J2-17") + Connect("J16-8") + Connect("U1-5") + ) + Net("SDI" "(unknown)") + ( + Connect("J2-33") + Connect("J16-13") + ) + Net("SDO" "(unknown)") + ( + Connect("J2-31") + Connect("J16-11") + ) + Net("SEN_RX" "(unknown)") + ( + Connect("J2-35") + Connect("J16-14") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("R28-2") + Connect("U1-7") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("J18-1") + Connect("R3-1") + Connect("R37-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("R4-1") + Connect("R38-2") + Connect("U3-5") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("R5-1") + Connect("R39-2") + Connect("U3-4") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("J19-1") + Connect("R9-1") + Connect("R30-1") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("R10-1") + Connect("R31-2") + Connect("U2-5") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("R11-1") + Connect("R34-2") + Connect("U2-4") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("R37-2") + Connect("R38-1") + Connect("U3-8") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("R36-2") + Connect("R39-1") + Connect("U3-1") + ) + Net("unnamed_net10" "(unknown)") + ( + Connect("R35-2") + Connect("R36-1") + ) + Net("unnamed_net11" "(unknown)") + ( + Connect("R30-2") + Connect("R31-1") + Connect("U2-8") + ) + Net("unnamed_net12" "(unknown)") + ( + Connect("R33-2") + Connect("R34-1") + Connect("U2-1") + ) + Net("unnamed_net13" "(unknown)") + ( + Connect("R32-2") + Connect("R33-1") + ) + Net("V_BIAS" "(unknown)") + ( + Connect("C24-1") + Connect("R6-2") + Connect("R7-1") + Connect("U2-2") + Connect("U3-2") + ) + Net("VINN_A" "(unknown)") + ( + Connect("C26-1") + Connect("J2-60") + Connect("R11-2") + ) + Net("VINN_B" "(unknown)") + ( + Connect("C23-1") + Connect("J2-52") + Connect("R5-2") + ) + Net("VINP_A" "(unknown)") + ( + Connect("C25-1") + Connect("J2-62") + Connect("R10-2") + ) + Net("VINP_B" "(unknown)") + ( + Connect("C22-1") + Connect("J2-50") + Connect("R4-2") + ) + Net("VREF" "(unknown)") + ( + Connect("J2-56") + ) +) diff --git a/usrp-hw/basic-lf/lfrx.prj b/usrp-hw/basic-lf/lfrx.prj new file mode 100644 index 000000000..5f20a95a5 --- /dev/null +++ b/usrp-hw/basic-lf/lfrx.prj @@ -0,0 +1,6 @@ +# List all schematics +schematics lfrx.sch + +output-name lfrx + +elements-dir ../pkg/newlib diff --git a/usrp-hw/basic-lf/lfrx.sch b/usrp-hw/basic-lf/lfrx.sch new file mode 100644 index 000000000..a5e2a8792 --- /dev/null +++ b/usrp-hw/basic-lf/lfrx.sch @@ -0,0 +1,1116 @@ +v 20050820 1 +C 75900 43000 1 180 1 pmc64.sym +{ +T 76600 29800 5 10 1 1 0 2 1 +refdes=J2 +T 75900 43000 5 10 0 1 90 6 1 +footprint=PMC-REVERSE +} +N 77400 37900 79100 37900 4 +{ +T 77700 37900 5 10 1 1 0 0 1 +netname=RS232_RXD +} +N 77400 38300 79100 38300 4 +{ +T 77700 38300 5 10 1 1 0 0 1 +netname=RS232_TXD +} +C 75800 30100 1 90 0 generic-power.sym +{ +T 75550 30300 5 10 1 1 90 3 1 +net=AGND:1 +} +N 75800 30300 76000 30300 4 +N 77400 39100 78700 39100 4 +{ +T 77800 39100 5 10 1 1 0 0 1 +netname=I2C_A1 +} +C 78000 42600 1 90 0 gnd-1.sym +N 77400 42700 77700 42700 4 +C 75400 42800 1 270 0 gnd-1.sym +N 76000 42700 75700 42700 4 +C 77600 30500 1 270 0 generic-power.sym +{ +T 77850 30300 5 10 1 1 270 3 1 +net=AGND:1 +} +N 77600 30300 77400 30300 4 +N 77400 35900 78600 35900 4 +{ +T 77500 35900 5 10 1 1 0 0 1 +netname=SEN_RX +} +C 75500 35600 1 270 0 gnd-1.sym +N 76000 35500 75800 35500 4 +C 77900 35400 1 90 0 gnd-1.sym +N 77400 35500 77600 35500 4 +C 75800 34500 1 90 0 generic-power.sym +{ +T 75550 34700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 75800 34700 76000 34700 4 +C 77600 34900 1 270 0 generic-power.sym +{ +T 77850 34700 5 10 1 1 270 3 1 +net=AGND:1 +} +N 77600 34700 77400 34700 4 +N 77400 31100 79000 31100 4 +{ +T 77400 31100 5 10 1 1 0 0 1 +netname=AUX_ADC_A1 +} +N 77400 30700 79000 30700 4 +{ +T 77400 30700 5 10 1 1 0 0 1 +netname=AUX_ADC_B1 +} +C 75800 31300 1 90 0 generic-power.sym +{ +T 75550 31500 5 10 1 1 90 3 1 +net=AGND:1 +} +N 75800 31500 76000 31500 4 +C 75800 32100 1 90 0 generic-power.sym +{ +T 75550 32300 5 10 1 1 90 3 1 +net=AGND:1 +} +N 75800 32300 76000 32300 4 +C 75800 33300 1 90 0 generic-power.sym +{ +T 75550 33500 5 10 1 1 90 3 1 +net=AGND:1 +} +N 75800 33500 76000 33500 4 +N 74400 30700 76000 30700 4 +{ +T 74400 30700 5 10 1 1 0 0 1 +netname=VINP_A +} +N 74400 31100 76000 31100 4 +{ +T 74400 31100 5 10 1 1 0 0 1 +netname=VINN_A +} +N 74400 33100 76000 33100 4 +{ +T 74400 33100 5 10 1 1 0 0 1 +netname=VINP_B +} +N 74400 32700 76000 32700 4 +{ +T 74400 32700 5 10 1 1 0 0 1 +netname=VINN_B +} +N 76000 31900 74400 31900 4 +{ +T 74500 31900 5 10 1 1 0 0 1 +netname=VREF +} +C 77600 33700 1 270 0 generic-power.sym +{ +T 77850 33500 5 10 1 1 270 3 1 +net=AGND:1 +} +N 77600 33500 77400 33500 4 +C 78200 34100 1 270 0 generic-power.sym +{ +T 78450 33900 5 10 1 1 270 3 1 +net=AVDD:1 +} +N 77400 34300 77900 34300 4 +N 77400 33900 78200 33900 4 +C 77900 34500 1 270 0 generic-power.sym +{ +T 78150 34300 5 10 1 1 270 3 1 +net=AVDD:1 +} +C 78100 42500 1 270 0 generic-power.sym +{ +T 78350 42300 5 10 1 1 270 3 1 +net=5V:1 +} +C 75200 34100 1 90 1 generic-power.sym +{ +T 74950 33900 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 76000 33900 75200 33900 4 +N 76000 34300 75500 34300 4 +C 75500 34500 1 90 1 generic-power.sym +{ +T 75250 34300 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 77400 42300 78100 42300 4 +N 77400 41900 77900 41900 4 +C 77900 41300 1 270 0 generic-power.sym +{ +T 78150 41100 5 10 1 1 270 3 1 +net=DVDD:1 +} +N 77400 41100 77900 41100 4 +N 77400 41500 77700 41500 4 +N 77900 41900 77900 42300 4 +N 77700 41500 77700 41100 4 +N 74000 41900 76000 41900 4 +{ +T 74300 41900 5 10 1 1 0 0 1 +netname=io_rx_15 +} +N 74000 41500 76000 41500 4 +{ +T 74300 41500 5 10 1 1 0 0 1 +netname=io_rx_14 +} +N 74000 40300 76000 40300 4 +{ +T 74300 40300 5 10 1 1 0 0 1 +netname=io_rx_11 +} +N 74000 41100 76000 41100 4 +{ +T 74300 41100 5 10 1 1 0 0 1 +netname=io_rx_13 +} +N 74000 40700 76000 40700 4 +{ +T 74300 40700 5 10 1 1 0 0 1 +netname=io_rx_12 +} +N 74000 39100 76000 39100 4 +{ +T 74300 39100 5 10 1 1 0 0 1 +netname=io_rx_08 +} +N 74000 39900 76000 39900 4 +{ +T 74300 39900 5 10 1 1 0 0 1 +netname=io_rx_10 +} +N 74000 39500 76000 39500 4 +{ +T 74300 39500 5 10 1 1 0 0 1 +netname=io_rx_09 +} +N 74000 37900 76000 37900 4 +{ +T 74300 37900 5 10 1 1 0 0 1 +netname=io_rx_05 +} +N 74000 38700 76000 38700 4 +{ +T 74300 38700 5 10 1 1 0 0 1 +netname=io_rx_07 +} +N 74000 38300 76000 38300 4 +{ +T 74300 38300 5 10 1 1 0 0 1 +netname=io_rx_06 +} +N 74000 36700 76000 36700 4 +{ +T 74300 36700 5 10 1 1 0 0 1 +netname=io_rx_02 +} +N 74000 37500 76000 37500 4 +{ +T 74300 37500 5 10 1 1 0 0 1 +netname=io_rx_04 +} +N 74000 37100 76000 37100 4 +{ +T 74300 37100 5 10 1 1 0 0 1 +netname=io_rx_03 +} +N 74000 35900 76000 35900 4 +{ +T 74300 35900 5 10 1 1 0 0 1 +netname=io_rx_00 +} +N 74000 36300 76000 36300 4 +{ +T 74300 36300 5 10 1 1 0 0 1 +netname=io_rx_01 +} +C 65600 29400 0 0 0 title-bordered-C.sym +T 82500 30300 5 10 1 1 0 0 1 +date=$Date: 2006/01/13 18:46:59 $ +T 84400 30000 5 10 1 1 0 0 1 +rev=$Revision: 1.4 $ +T 84500 29700 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 80300 30000 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/basic-lf/lfrx.sch,v $ +T 83700 30700 8 14 1 1 0 4 1 +title=LFRX Daughterboard +T 81300 29700 9 10 1 0 0 0 1 +1 +T 82100 29700 9 10 1 0 0 0 1 +1 +N 77400 40700 78800 40700 4 +{ +T 77600 40700 5 10 1 1 0 0 1 +netname=CLKOUT1 +} +N 77400 40300 78800 40300 4 +{ +T 77500 40300 5 10 1 1 0 0 1 +netname=CLKOUT2 +} +N 77400 39900 78500 39900 4 +{ +T 77700 39900 5 10 1 1 0 0 1 +netname=SCL +} +N 77400 39500 78500 39500 4 +{ +T 77700 39500 5 10 1 1 0 0 1 +netname=SDA +} +N 77400 37100 78800 37100 4 +{ +T 77800 37100 5 10 1 1 0 0 1 +netname=SCLK +} +N 77400 36700 78800 36700 4 +{ +T 77800 36700 5 10 1 1 0 0 1 +netname=SDO +} +N 77400 36300 78800 36300 4 +{ +T 77800 36300 5 10 1 1 0 0 1 +netname=SDI +} +N 77400 32700 79100 32700 4 +{ +T 77600 32700 5 10 1 1 0 0 1 +netname=AUX_DAC_A +} +N 77400 32300 79100 32300 4 +{ +T 77600 32300 5 10 1 1 0 0 1 +netname=AUX_DAC_B +} +N 77400 31900 79100 31900 4 +{ +T 77600 31900 5 10 1 1 0 0 1 +netname=AUX_DAC_C +} +N 77400 31500 79100 31500 4 +{ +T 77500 31500 5 10 1 1 0 0 1 +netname=AUX_ADC_REF +} +N 77400 33100 79100 33100 4 +{ +T 77600 33100 5 10 1 1 0 0 1 +netname=AUX_DAC_D +} +C 76300 44700 1 0 0 24Cxx-1.sym +{ +T 76800 45900 5 10 1 1 0 0 1 +refdes=U1 +T 76300 44700 5 10 0 1 0 0 1 +footprint=SO8 +T 76600 44500 5 10 1 1 0 0 1 +device=24LC025B +T 76600 44100 5 10 1 1 0 0 1 +net=GND:4 +T 76600 44300 5 10 1 1 0 0 1 +net=DVDD:8 +} +N 77600 45000 79000 45000 4 +{ +T 78500 45000 5 10 1 1 0 0 1 +netname=SCL +} +N 77600 44800 79000 44800 4 +{ +T 78500 44800 5 10 1 1 0 0 1 +netname=SDA +} +C 78600 45300 1 180 0 resistor-1.sym +{ +T 78500 45300 5 10 1 1 0 0 1 +value=0 +T 78600 45300 5 10 0 1 180 0 1 +footprint=0603 +T 77600 45300 5 10 1 1 0 0 1 +refdes=R28 +} +N 77600 45200 77700 45200 4 +C 79000 45100 1 90 0 gnd-1.sym +N 78600 45200 78700 45200 4 +C 69200 36700 1 0 0 header20-2.sym +{ +T 69800 40800 5 10 1 1 0 0 1 +refdes=J15 +T 69200 36700 5 10 0 1 0 0 1 +footprint=CONNECTOR 10 2 +} +C 71100 36800 1 90 0 gnd-1.sym +N 70600 36900 70800 36900 4 +N 67200 36900 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"edge2"] + Pin[30000 -10000 6000 3000 6000 4000 "8" "8" "edge2"] + Pin[40000 0 6000 3000 6000 4000 "9" "9" "edge2,thermal(1,6)"] + Pin[40000 -10000 6000 3000 6000 4000 "10" "10" "edge2,thermal(1,6)"] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 45000 -15000 2000] + ElementLine [45000 -15000 45000 5000 2000] + ElementLine [-5000 5000 45000 5000 2000] + + ) + +Element["onsolder" "0603" "R35" "25" 186000 175500 -18000 -2500 2 100 "auto"] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + + ) + +Element["" "0603" "R37" "500" 158500 192500 -16500 -3000 0 100 ""] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + + ) + +Element["" "0603" "R32" "500" 212500 197000 -12500 3500 0 100 ""] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + + ) + +Element["onsolder" "0603" "R33" "25" 216000 176000 31500 -2500 2 100 "auto"] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + + ) + +Element["" "0603" "R34" "25" 247000 210000 3500 -5000 0 100 ""] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" "square"] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + + ) + +Element["" "CONNECTOR-10-2" "J45" "unknown" 45000 237000 45000 -38000 0 100 ""] +( + Pin[0 0 6000 3000 6000 4000 "1" "1" "square,edge2"] + Pin[0 -10000 6000 3000 6000 4000 "2" "2" "edge2"] + Pin[10000 0 6000 3000 6000 4000 "3" "3" "edge2"] + Pin[10000 -10000 6000 3000 6000 4000 "4" "4" "edge2"] + Pin[20000 0 6000 3000 6000 4000 "5" "5" "edge2"] + Pin[20000 -10000 6000 3000 6000 4000 "6" "6" "edge2"] + Pin[30000 0 6000 3000 6000 4000 "7" "7" "edge2"] + Pin[30000 -10000 6000 3000 6000 4000 "8" "8" "edge2"] + Pin[40000 0 6000 3000 6000 4000 "9" "9" "edge2"] + Pin[40000 -10000 6000 3000 6000 4000 "10" "10" "edge2"] + Pin[50000 0 6000 3000 6000 4000 "11" "11" "edge2"] + Pin[50000 -10000 6000 3000 6000 4000 "12" "12" "edge2"] + Pin[60000 0 6000 3000 6000 4000 "13" "13" "edge2"] + Pin[60000 -10000 6000 3000 6000 4000 "14" "14" "edge2"] + Pin[70000 0 6000 3000 6000 4000 "15" "15" "edge2"] + Pin[70000 -10000 6000 3000 6000 4000 "16" "16" "edge2"] + Pin[80000 0 6000 3000 6000 4000 "17" "17" "edge2"] + Pin[80000 -10000 6000 3000 6000 4000 "18" "18" "edge2"] + Pin[90000 0 6000 3000 6000 4000 "19" "19" "edge2"] + Pin[90000 -10000 6000 3000 6000 4000 "20" "20" "edge2,thermal(1,6)"] + ElementLine [-5000 5000 95000 5000 2000] + ElementLine [95000 -15000 95000 5000 2000] + ElementLine [-5000 -15000 95000 -15000 2000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -5000 5000 -5000 1000] + + ) + +Element["" "TSOT23-95P-280L1-6N__LTC_S6_Package" "U3" "unknown" 77500 29000 -15000 -7200 0 100 ""] +( + Pad[-6350 -3700 -3950 -3700 2400 2000 4400 "" "1" "square"] + Pad[-6350 0 -3950 0 2400 2000 4400 "" "2" "square"] + Pad[-6350 3700 -3950 3700 2400 2000 4400 "" "3" "square"] + Pad[3950 3700 6350 3700 2400 2000 4400 "" "4" "square,edge2"] + Pad[3950 0 6350 0 2400 2000 4400 "" "5" "square,edge2"] + Pad[3950 -3700 6350 -3700 2400 2000 4400 "" "6" "square,edge2"] + ElementLine [1750 5700 1750 2200 1000] + ElementLine [-1750 5700 1750 5700 1000] + ElementLine [-1750 2200 -1750 5700 1000] + ElementLine [1750 -5700 1750 -2200 1000] + ElementLine [-525 -5700 1750 -5700 1000] + ElementLine [-1750 -4475 -525 -5700 1000] + ElementLine [-1750 -2200 -1750 -4475 1000] + + ) + +Element["" "CONNECTOR-8-2" "J51" "unknown" 19000 238000 -1000 -82000 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square"] + Pin[-10000 0 6000 3000 6600 4000 "2" "2" "thermal(1)"] + Pin[0 -10000 6000 3000 6600 4000 "3" "3" ""] + Pin[-10000 -10000 6000 3000 6600 4000 "4" "4" "thermal(1)"] + Pin[0 -20000 6000 3000 6600 4000 "5" "5" ""] + Pin[-10000 -20000 6000 3000 6600 4000 "6" "6" "thermal(1)"] + Pin[0 -30000 6000 3000 6600 4000 "7" "7" ""] + Pin[-10000 -30000 6000 3000 6600 4000 "8" "8" "thermal(1)"] + Pin[0 -40000 6000 3000 6600 4000 "9" "9" ""] + Pin[-10000 -40000 6000 3000 6600 4000 "10" "10" "thermal(1)"] + Pin[0 -50000 6000 3000 6600 4000 "11" "11" ""] + Pin[-10000 -50000 6000 3000 6600 4000 "12" "12" "thermal(1)"] + Pin[0 -60000 6000 3000 6600 4000 "13" "13" ""] + Pin[-10000 -60000 6000 3000 6600 4000 "14" "14" "thermal(1)"] + Pin[0 -70000 6000 3000 6600 4000 "15" "15" ""] + Pin[-10000 -70000 6000 3000 6600 4000 "16" "16" "thermal(1)"] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [-15000 5000 5000 5000 2000] + ElementLine [-15000 -75000 -15000 5000 2000] + ElementLine [-15000 -75000 5000 -75000 2000] + ElementLine [5000 -75000 5000 5000 2000] + + ) + +Element["" "0603" "R1" "68.1K" 76500 39500 5500 -1700 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] 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-2700 4200 2700 600] + + ) + +Element["onsolder" "0603" "R5" "225" 208500 184000 21700 3000 3 100 "auto"] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["onsolder" "0603" "R6" "225" 187500 183500 -20300 1000 3 100 "auto"] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R7" "500" 181500 203000 5000 -1700 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine 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900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "1206" "C3" "10uF" 113000 29000 -3500 9600 0 100 ""] +( + Pad[-1800 4800 1800 4800 4800 2000 5400 "1" "1" "square"] + Pad[-1800 -4800 1800 -4800 4800 2000 5400 "2" "2" "square"] + ElementLine [-5400 -8400 -5400 8400 1000] + ElementLine [-5400 -8400 5400 -8400 1000] + ElementLine [5400 -8400 5400 8400 1000] + ElementLine [-5400 8400 5400 8400 1000] + + ) + +Element["" "0603" "C4" "22pF" 76500 46500 5500 -1700 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "0603" "C10" "220pF" 149500 38000 6000 1800 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [4200 -2700 -4200 -2700 600] + ElementLine [4200 2700 4200 -2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "1206" "C11" "10uF" 147500 19500 11000 -5400 0 100 ""] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "square"] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "square"] + ElementLine [8400 -5400 -8400 -5400 1000] + ElementLine [8400 5400 8400 -5400 1000] + ElementLine [-8400 5400 8400 5400 1000] + ElementLine [-8400 -5400 -8400 5400 1000] + + ) + +Element["" "0603" "C6" "0.1uF" 201000 187500 -1500 -8700 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "0603" "C12" "0.1uF" 149500 31000 6500 -3700 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [4200 -2700 -4200 -2700 600] + ElementLine [4200 2700 4200 -2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["onsolder" "0603" "C14" "20pF" 211000 168500 15000 -2200 2 100 "auto"] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "auto,square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element["" "0603" "C8" "0.1uF" 259500 189000 -2500 -7700 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 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"L2" "22uH" 95000 34500 -4000 -13900 0 100 ""] +( + Pad[-1800 -4800 1800 -4800 4800 2000 5400 "1" "1" "square"] + Pad[-1800 4800 1800 4800 4800 2000 5400 "2" "2" "square"] + ElementLine [5400 -8400 5400 8400 1000] + ElementLine [-5400 8400 5400 8400 1000] + ElementLine [-5400 -8400 -5400 8400 1000] + ElementLine [-5400 -8400 5400 -8400 1000] + + ) + +Element["" "SO8" "U1" "unknown" 235500 191000 -1500 1000 0 100 ""] +( + Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "1" "1" "square"] + Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "2" "2" "square"] + Pad[-13500 2500 -7000 2500 2000 1000 3000 "3" "3" "square"] + Pad[-13500 7500 -7000 7500 2000 1000 3000 "4" "4" "square"] + Pad[7000 7500 13500 7500 2000 1000 3000 "5" "5" "square,edge2"] + Pad[7000 2500 13500 2500 2000 1000 3000 "6" "6" "square,edge2"] + Pad[7000 -2500 13500 -2500 2000 1000 3000 "7" "7" "square,edge2"] + Pad[7000 -7500 13500 -7500 2000 1000 3000 "8" "8" "square,edge2"] + ElementLine [15500 -9500 2500 -9500 1000] + ElementLine [-15500 -9500 -2500 -9500 1000] + ElementLine [15500 9500 15500 -9500 1000] + ElementLine [-15500 9500 15500 9500 1000] + ElementLine [-15500 -9500 -15500 9500 1000] + ElementArc [0 -9500 2500 2500 0 180 1000] + + ) + +Element["" "SO8" "U2" "unknown" 180000 190000 -3000 -15000 0 100 ""] +( + Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "1" "1" "square"] + Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "2" "2" "square"] + Pad[-13500 2500 -7000 2500 2000 1000 3000 "3" "3" "square"] + Pad[-13500 7500 -7000 7500 2000 1000 3000 "4" "4" "square"] + Pad[7000 7500 13500 7500 2000 1000 3000 "5" "5" "square,edge2"] + Pad[7000 2500 13500 2500 2000 1000 3000 "6" "6" "square,edge2"] + Pad[7000 -2500 13500 -2500 2000 1000 3000 "7" "7" "square,edge2"] + Pad[7000 -7500 13500 -7500 2000 1000 3000 "8" "8" "square,edge2"] + ElementLine [15500 -9500 2500 -9500 1000] + ElementLine [-15500 -9500 -2500 -9500 1000] + ElementLine [15500 9500 15500 -9500 1000] + ElementLine [-15500 9500 15500 9500 1000] + ElementLine [-15500 -9500 -15500 9500 1000] + ElementArc [0 -9500 2500 2500 0 180 1000] + + ) + +Element["onsolder" "PMC-REVERSE" "J44" "unknown" 94993 139811 -21000 12000 0 100 "auto"] +( + Pin[-6693 7189 7200 2000 7200 5600 "" "1" "hole,edge2"] + Pin[128740 7189 7200 2000 7200 5600 "" "2" "hole,edge2"] + Pad[0 9900 0 19000 2400 1000 3400 "" "1" "auto,edge2"] + Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" "auto"] + Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" "auto,edge2"] + Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" "auto,edge2"] + Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" "auto,edge2"] + Pad[0 -4622 0 4478 2400 1000 3400 "" "2" "auto"] + Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" "auto,edge2"] + Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" "auto"] + Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" "auto,edge2"] + Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" "auto"] + Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" "auto,edge2"] + Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" "auto"] + Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" "auto,edge2"] + Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" "auto"] + Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" "auto,edge2"] + Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" "auto"] + Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" "auto,edge2"] + Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" "auto"] + Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" "auto,edge2"] + Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" "auto"] + Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" "auto"] + Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" "auto"] + Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" "auto"] + Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" "auto"] + Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" "auto"] + Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" "auto"] + Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" "auto"] + Pad[62992 -4622 62992 4478 2400 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Connect("J44-38") + Connect("J45-20") + Connect("J46-2") + Connect("J46-4") + Connect("J46-16") + Connect("J50-2") + Connect("J50-4") + Connect("J50-6") + Connect("J50-8") + Connect("J50-10") + Connect("J50-12") + Connect("J50-14") + Connect("J50-16") + Connect("J51-2") + Connect("J51-4") + Connect("J51-6") + Connect("J51-8") + Connect("J51-10") + Connect("J51-12") + Connect("J51-14") + Connect("J51-16") + Connect("R29-1") + Connect("U52-4") + ) + Net("I2C_A0" "(unknown)") + ( + Connect("J44-22") + Connect("J46-5") + Connect("U52-1") + ) + Net("I2C_A1" "(unknown)") + ( + Connect("J44-20") + Connect("J46-6") + Connect("U52-2") + ) + Net("io_tx_00" "(unknown)") + ( + Connect("J44-35") + Connect("J45-19") + Connect("J50-15") + ) + Net("io_tx_01" "(unknown)") + ( + Connect("J44-33") + Connect("J45-18") + Connect("J50-13") + ) + Net("io_tx_02" "(unknown)") + ( + Connect("J44-31") + Connect("J45-17") + Connect("J50-11") + ) + Net("io_tx_03" "(unknown)") + ( + Connect("J44-29") + Connect("J45-16") + Connect("J50-9") + ) + Net("io_tx_04" "(unknown)") + ( + Connect("J44-27") + Connect("J45-15") + Connect("J50-7") + ) + Net("io_tx_05" "(unknown)") + ( + Connect("J44-25") + Connect("J45-14") + Connect("J50-5") + ) + Net("io_tx_06" "(unknown)") + ( + Connect("J44-23") + Connect("J45-13") + Connect("J50-3") + ) + Net("io_tx_07" "(unknown)") + ( + Connect("J44-21") + Connect("J45-12") + Connect("J50-1") + ) + Net("io_tx_08" "(unknown)") + ( + Connect("J44-19") + Connect("J45-11") + Connect("J51-15") + ) + Net("io_tx_09" "(unknown)") + ( + Connect("J44-17") + Connect("J45-10") + Connect("J51-13") + ) + Net("io_tx_10" "(unknown)") + ( + Connect("J44-15") + Connect("J45-9") + Connect("J51-11") + ) + Net("io_tx_11" "(unknown)") + ( + Connect("J44-13") + Connect("J45-8") + Connect("J51-9") + ) + Net("io_tx_12" "(unknown)") + ( + Connect("J44-11") + Connect("J45-7") + Connect("J51-7") + ) + Net("io_tx_13" "(unknown)") + ( + Connect("J44-9") + Connect("J45-6") + Connect("J51-5") + ) + Net("io_tx_14" "(unknown)") + ( + Connect("J44-7") + Connect("J45-5") + Connect("J51-3") + ) + Net("io_tx_15" "(unknown)") + ( + Connect("J44-5") + Connect("J45-4") + Connect("J51-1") + ) + Net("IOUTN_A" "(unknown)") + ( + Connect("C14-2") + Connect("J44-61") + Connect("R3-2") + Connect("R33-1") + ) + Net("IOUTN_B" "(unknown)") + ( + Connect("C15-2") + Connect("J44-49") + Connect("R6-2") + Connect("R35-1") + ) + Net("IOUTP_A" "(unknown)") + ( + Connect("C14-1") + Connect("J44-59") + Connect("R5-2") + Connect("R39-1") + ) + Net("IOUTP_B" "(unknown)") + ( + Connect("C15-1") + Connect("J44-51") + Connect("R8-2") + Connect("R36-1") + ) + Net("REFIO" "(unknown)") + ( + Connect("J44-55") + ) + Net("RESET" "(unknown)") + ( + Connect("J44-28") + Connect("J46-15") + ) + Net("RS232_RXD" "(unknown)") + ( + Connect("J44-26") + Connect("J46-10") + ) + Net("RS232_TXD" "(unknown)") + ( + Connect("J44-24") + Connect("J46-9") + ) + Net("SCL" "(unknown)") + ( + Connect("J44-16") + Connect("J46-7") + Connect("U52-6") + ) + Net("SCLK" "(unknown)") + ( + Connect("J44-30") + Connect("J46-12") + ) + Net("SDA" "(unknown)") + ( + Connect("J44-18") + Connect("J46-8") + Connect("U52-5") + ) + Net("SDI" "(unknown)") + ( + Connect("J44-34") + Connect("J46-13") + ) + Net("SDO" "(unknown)") + ( + Connect("J44-32") + Connect("J46-11") + ) + Net("SEN_TX" "(unknown)") + ( + Connect("J44-36") + Connect("J46-14") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("R29-2") + Connect("U52-7") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("J48-1") + Connect("R40-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("C33-2") + Connect("R4-1") + Connect("R34-2") + Connect("U1-6") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("C31-1") + Connect("R34-1") + Connect("R40-2") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("C1-2") + Connect("L1-2") + Connect("U3-1") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("C2-2") + Connect("C5-2") + Connect("FB1-1") + Connect("L1-1") + Connect("U3-6") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("C1-1") + Connect("L2-1") + Connect("U3-5") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("C4-2") + Connect("R1-1") + Connect("R2-2") + Connect("U3-3") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("R1-2") + Connect("U3-4") + ) + Net("unnamed_net10" "(unknown)") + ( + Connect("C3-1") + Connect("C4-1") + Connect("C20-2") + Connect("C21-2") + Connect("FB2-1") + Connect("L2-2") + Connect("R2-1") + ) + Net("unnamed_net11" "(unknown)") + ( + Connect("R5-1") + Connect("R32-1") + Connect("U1-3") + ) + Net("unnamed_net12" "(unknown)") + ( + Connect("C33-1") + Connect("R3-1") + Connect("R4-2") + Connect("U1-2") + ) + Net("unnamed_net13" "(unknown)") + ( + Connect("J49-1") + Connect("R41-1") + ) + Net("unnamed_net14" "(unknown)") + ( + Connect("C34-2") + Connect("R7-1") + Connect("R38-2") + Connect("U2-6") + ) + Net("unnamed_net15" "(unknown)") + ( + Connect("C32-1") + Connect("R38-1") + Connect("R41-2") + ) + Net("unnamed_net16" "(unknown)") + ( + Connect("R8-1") + Connect("R37-1") + Connect("U2-3") + ) + Net("unnamed_net17" "(unknown)") + ( + Connect("C34-1") + Connect("R6-1") + Connect("R7-2") + Connect("U2-2") + ) +) diff --git a/usrp-hw/basic-lf/lftx.prj b/usrp-hw/basic-lf/lftx.prj new file mode 100644 index 000000000..4068f7ae9 --- /dev/null +++ b/usrp-hw/basic-lf/lftx.prj @@ -0,0 +1,6 @@ +# List all schematics +schematics lftx.sch + +output-name lftx + +elements-dir ../pkg/newlib diff --git a/usrp-hw/basic-lf/lftx.sch b/usrp-hw/basic-lf/lftx.sch new file mode 100644 index 000000000..1b5cad7a8 --- /dev/null +++ b/usrp-hw/basic-lf/lftx.sch @@ -0,0 +1,1348 @@ +v 20050820 1 +C 78000 43300 1 180 0 pmc64.sym +{ +T 77300 30100 5 10 1 1 0 8 1 +refdes=J44 +T 78000 43300 5 10 0 1 270 2 1 +footprint=PMC-REVERSE +} +N 79500 38200 77900 38200 4 +{ +T 79400 38200 5 10 1 1 0 6 1 +netname=RS232_RXD +} +N 79500 38600 77900 38600 4 +{ +T 79400 38600 5 10 1 1 0 6 1 +netname=RS232_TXD +} +N 79000 39800 77900 39800 4 +{ +T 78700 39800 5 10 1 1 0 6 1 +netname=SDA +} +N 79000 40200 77900 40200 4 +{ +T 78700 40200 5 10 1 1 0 6 1 +netname=SCL +} +C 78400 41200 1 270 1 generic-power.sym +{ +T 78650 41400 5 10 1 1 90 5 1 +net=DVDD:1 +} +C 75900 42900 1 270 1 gnd-1.sym +N 76500 43000 76200 43000 4 +C 78500 43100 1 90 1 gnd-1.sym +N 77900 43000 78200 43000 4 +C 78100 30400 1 270 1 generic-power.sym +{ +T 78350 30600 5 10 1 1 90 5 1 +net=AGND:1 +} +N 78100 30600 77900 30600 4 +N 79300 37400 77900 37400 4 +{ +T 78900 37400 5 10 1 1 0 6 1 +netname=SCLK +} +N 79300 37800 77900 37800 4 +{ +T 78900 37800 5 10 1 1 0 6 1 +netname=RESET +} +N 79300 37000 77900 37000 4 +{ +T 78900 37000 5 10 1 1 0 6 1 +netname=SDO +} +N 79100 36200 77900 36200 4 +{ +T 79000 36200 5 10 1 1 0 6 1 +netname=SEN_TX +} +C 76000 35700 1 270 1 gnd-1.sym +N 76500 35800 76300 35800 4 +C 78400 35900 1 90 1 gnd-1.sym +N 77900 35800 78100 35800 4 +C 78100 34800 1 270 1 generic-power.sym +{ +T 78350 35000 5 10 1 1 90 5 1 +net=AGND:1 +} +N 78100 35000 77900 35000 4 +C 76300 35200 1 90 1 generic-power.sym +{ +T 76050 35000 5 10 1 1 270 5 1 +net=AGND:1 +} +N 76300 35000 76500 35000 4 +N 79300 36600 77900 36600 4 +{ +T 78900 36600 5 10 1 1 0 6 1 +netname=SDI +} +N 79600 33400 77900 33400 4 +{ +T 79400 33400 5 10 1 1 0 6 1 +netname=AUX_DAC_D +} +N 79600 33000 77900 33000 4 +{ +T 79400 33000 5 10 1 1 0 6 1 +netname=AUX_DAC_A +} +N 79600 32600 77900 32600 4 +{ +T 79400 32600 5 10 1 1 0 6 1 +netname=AUX_DAC_B +} +N 79600 32200 77900 32200 4 +{ +T 79400 32200 5 10 1 1 0 6 1 +netname=AUX_DAC_C +} +N 79500 31400 77900 31400 4 +{ +T 79500 31400 5 10 1 1 0 6 1 +netname=AUX_ADC_A2 +} +N 79600 31800 77900 31800 4 +{ +T 79500 31800 5 10 1 1 0 6 1 +netname=AUX_ADC_REF +} +N 79500 31000 77900 31000 4 +{ +T 79500 31000 5 10 1 1 0 6 1 +netname=AUX_ADC_B2 +} +C 76300 30400 1 90 0 generic-power.sym +{ +T 76050 30600 5 10 1 1 270 5 1 +net=AGND:1 +} +N 76300 30600 76500 30600 4 +C 76300 31600 1 90 0 generic-power.sym +{ +T 76050 31800 5 10 1 1 270 5 1 +net=AGND:1 +} +N 76300 31800 76500 31800 4 +C 76300 32400 1 90 0 generic-power.sym +{ +T 76050 32600 5 10 1 1 270 5 1 +net=AGND:1 +} +N 76300 32600 76500 32600 4 +C 76300 33600 1 90 0 generic-power.sym +{ +T 76050 33800 5 10 1 1 270 5 1 +net=AGND:1 +} +N 76300 33800 76500 33800 4 +N 74900 31400 76500 31400 4 +{ +T 75900 31400 5 10 1 1 0 6 1 +netname=IOUTP_A +} +N 74900 31000 76500 31000 4 +{ +T 75900 31000 5 10 1 1 0 6 1 +netname=IOUTN_A +} +N 74900 33000 76500 33000 4 +{ +T 75900 33000 5 10 1 1 0 6 1 +netname=IOUTP_B +} +N 74900 33400 76500 33400 4 +{ +T 75900 33400 5 10 1 1 0 6 1 +netname=IOUTN_B +} +N 76500 32200 74900 32200 4 +{ +T 75800 32200 5 10 1 1 0 6 1 +netname=REFIO +} +C 78100 33600 1 270 1 generic-power.sym +{ +T 78350 33800 5 10 1 1 90 5 1 +net=AGND:1 +} +N 78100 33800 77900 33800 4 +C 78700 34400 1 270 0 generic-power.sym +{ +T 78950 34200 5 10 1 1 90 5 1 +net=AVDD:1 +} +N 77900 34600 78400 34600 4 +N 77900 34200 78700 34200 4 +C 78400 34800 1 270 0 generic-power.sym +{ +T 78650 34600 5 10 1 1 90 5 1 +net=AVDD:1 +} +N 76500 34200 75700 34200 4 +N 76500 34600 76000 34600 4 +C 76000 34800 1 90 1 generic-power.sym +{ +T 75750 34600 5 10 1 1 270 5 1 +net=AVDD:1 +} +C 75700 34400 1 90 1 generic-power.sym +{ +T 75450 34200 5 10 1 1 270 5 1 +net=AVDD:1 +} +N 77900 42200 78200 42200 4 +N 77900 42600 78600 42600 4 +C 78600 42400 1 270 1 generic-power.sym +{ +T 78850 42600 5 10 1 1 90 5 1 +net=5V:1 +} +N 78400 41400 77900 41400 4 +N 77900 41800 78200 41800 4 +N 78200 41800 78200 41400 4 +N 78200 42200 78200 42600 4 +N 76500 42200 74500 42200 4 +{ +T 75700 42200 5 10 1 1 0 6 1 +netname=io_tx_15 +} +N 76500 41800 74500 41800 4 +{ +T 75700 41800 5 10 1 1 0 6 1 +netname=io_tx_14 +} +N 76500 40600 74500 40600 4 +{ +T 75700 40600 5 10 1 1 0 6 1 +netname=io_tx_11 +} +N 76500 41400 74500 41400 4 +{ +T 75700 41400 5 10 1 1 0 6 1 +netname=io_tx_13 +} +N 76500 41000 74500 41000 4 +{ +T 75700 41000 5 10 1 1 0 6 1 +netname=io_tx_12 +} +N 76500 39400 74500 39400 4 +{ +T 75700 39400 5 10 1 1 0 6 1 +netname=io_tx_08 +} +N 76500 40200 74500 40200 4 +{ +T 75700 40200 5 10 1 1 0 6 1 +netname=io_tx_10 +} +N 76500 39800 74500 39800 4 +{ +T 75700 39800 5 10 1 1 0 6 1 +netname=io_tx_09 +} +N 76500 38200 74500 38200 4 +{ +T 75700 38200 5 10 1 1 0 6 1 +netname=io_tx_05 +} +N 76500 39000 74500 39000 4 +{ +T 75700 39000 5 10 1 1 0 6 1 +netname=io_tx_07 +} +N 76500 38600 74500 38600 4 +{ +T 75700 38600 5 10 1 1 0 6 1 +netname=io_tx_06 +} +N 76500 37000 74500 37000 4 +{ +T 75700 37000 5 10 1 1 0 6 1 +netname=io_tx_02 +} +N 76500 37800 74500 37800 4 +{ +T 75700 37800 5 10 1 1 0 6 1 +netname=io_tx_04 +} +N 76500 37400 74500 37400 4 +{ +T 75700 37400 5 10 1 1 0 6 1 +netname=io_tx_03 +} +N 76500 36200 74500 36200 4 +{ +T 75700 36200 5 10 1 1 0 6 1 +netname=io_tx_00 +} +N 76500 36600 74500 36600 4 +{ +T 75700 36600 5 10 1 1 0 6 1 +netname=io_tx_01 +} +C 65600 29400 0 0 0 title-bordered-C.sym +T 82500 30300 5 10 1 1 0 0 1 +date=$Date: 2006/02/23 18:07:25 $ +T 84400 30000 5 10 1 1 0 0 1 +rev=$Revision: 1.9 $ +T 84500 29700 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 80300 30000 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/basic-lf/lftx.sch,v $ +T 83700 30700 8 14 1 1 0 4 1 +title=LFTX Daughterboard +T 81300 29700 9 10 1 0 0 0 1 +1 +T 82100 29700 9 10 1 0 0 0 1 +1 +C 76600 44600 1 0 0 24Cxx-1.sym +{ +T 77100 45800 5 10 1 1 0 0 1 +refdes=U52 +T 76600 44600 5 10 0 1 0 0 1 +footprint=SO8 +T 76900 44400 5 10 1 1 0 0 1 +device=24LC025B +T 76900 44000 5 10 1 1 0 0 1 +net=GND:4 +T 76900 44200 5 10 1 1 0 0 1 +net=DVDD:8 +} +N 77900 44900 79300 44900 4 +{ +T 78800 44900 5 10 1 1 0 0 1 +netname=SCL +} +N 77900 44700 79300 44700 4 +{ +T 78800 44700 5 10 1 1 0 0 1 +netname=SDA +} +C 78900 45200 1 180 0 resistor-1.sym +{ +T 78800 45200 5 10 1 1 0 0 1 +value=0 +T 78900 45200 5 10 0 1 180 0 1 +footprint=0603 +T 77900 45200 5 10 1 1 0 0 1 +refdes=R29 +} +N 77900 45100 78000 45100 4 +C 79300 45000 1 90 0 gnd-1.sym +N 78900 45100 79000 45100 4 +C 69200 37000 1 0 0 header20-2.sym +{ +T 69800 41100 5 10 1 1 0 0 1 +refdes=J45 +T 69200 37000 5 10 0 1 0 0 1 +footprint=CONNECTOR 10 2 +} +N 70600 40400 72600 40400 4 +{ +T 71400 40400 5 10 1 1 0 0 1 +netname=io_tx_15 +} +N 67200 40000 69200 40000 4 +{ +T 68000 40000 5 10 1 1 0 0 1 +netname=io_tx_14 +} +N 70600 39600 72600 39600 4 +{ +T 71400 39600 5 10 1 1 0 0 1 +netname=io_tx_11 +} +N 70600 40000 72600 40000 4 +{ +T 71400 40000 5 10 1 1 0 0 1 +netname=io_tx_13 +} +N 67200 39600 69200 39600 4 +{ +T 68000 39600 5 10 1 1 0 0 1 +netname=io_tx_12 +} +N 67200 38800 69200 38800 4 +{ +T 68000 38800 5 10 1 1 0 0 1 +netname=io_tx_08 +} +N 67200 39200 69200 39200 4 +{ +T 68000 39200 5 10 1 1 0 0 1 +netname=io_tx_10 +} +N 70600 39200 72600 39200 4 +{ +T 71400 39200 5 10 1 1 0 0 1 +netname=io_tx_09 +} +N 70600 38400 72600 38400 4 +{ +T 71400 38400 5 10 1 1 0 0 1 +netname=io_tx_05 +} +N 70600 38800 72600 38800 4 +{ +T 71400 38800 5 10 1 1 0 0 1 +netname=io_tx_07 +} +N 67200 38400 69200 38400 4 +{ +T 68000 38400 5 10 1 1 0 0 1 +netname=io_tx_06 +} +N 67200 37600 69200 37600 4 +{ +T 68000 37600 5 10 1 1 0 0 1 +netname=io_tx_02 +} +N 67200 38000 69200 38000 4 +{ +T 68000 38000 5 10 1 1 0 0 1 +netname=io_tx_04 +} +N 70600 38000 72600 38000 4 +{ +T 71400 38000 5 10 1 1 0 0 1 +netname=io_tx_03 +} +N 67200 37200 69200 37200 4 +{ +T 68000 37200 5 10 1 1 0 0 1 +netname=io_tx_00 +} +N 70600 37600 72600 37600 4 +{ +T 71400 37600 5 10 1 1 0 0 1 +netname=io_tx_01 +} +N 70600 37200 70900 37200 4 +C 71200 37100 1 90 0 gnd-1.sym +C 69200 33000 1 0 0 header16-1.sym +{ +T 69700 36300 5 10 1 1 0 0 1 +refdes=J46 +T 69200 33000 5 10 0 1 0 0 1 +footprint=CONNECTOR 8 2 +} +N 67800 34800 69200 34800 4 +{ +T 68000 34800 5 10 1 1 0 0 1 +netname=SCL +} +N 70600 34800 72000 34800 4 +{ +T 70800 34800 5 10 1 1 0 0 1 +netname=SDA +} +N 67800 34400 69200 34400 4 +{ +T 68000 34400 5 10 1 1 0 0 1 +netname=RS232_TXD +} +N 70600 34400 72000 34400 4 +{ +T 70800 34400 5 10 1 1 0 0 1 +netname=RS232_RXD +} +N 70600 33600 72000 33600 4 +{ +T 70800 33600 5 10 1 1 0 0 1 +netname=SEN_TX +} +N 67800 33600 69200 33600 4 +{ +T 68000 33600 5 10 1 1 0 0 1 +netname=SDI +} +N 67800 34000 69200 34000 4 +{ +T 68000 34000 5 10 1 1 0 0 1 +netname=SDO +} +N 70600 34000 72000 34000 4 +{ +T 70800 34000 5 10 1 1 0 0 1 +netname=SCLK +} +N 67600 30600 69200 30600 4 +{ +T 67600 30600 5 10 1 1 0 0 1 +netname=AUX_ADC_B2 +} +N 67600 31000 69200 31000 4 +{ +T 67600 31000 5 10 1 1 0 0 1 +netname=AUX_ADC_A2 +} +N 67500 31400 69200 31400 4 +{ +T 67600 31400 5 10 1 1 0 0 1 +netname=AUX_ADC_REF +} +N 70600 30600 72300 30600 4 +{ +T 70800 30600 5 10 1 1 0 0 1 +netname=AUX_DAC_C +} +N 70600 31000 72300 31000 4 +{ +T 70800 31000 5 10 1 1 0 0 1 +netname=AUX_DAC_B +} +N 70600 31400 72300 31400 4 +{ +T 70800 31400 5 10 1 1 0 0 1 +netname=AUX_DAC_A +} +C 71200 30400 1 270 0 generic-power.sym +{ +T 71450 30200 5 10 1 1 270 3 1 +net=AGND:1 +} +N 71200 30200 70600 30200 4 +C 68900 31600 1 90 0 generic-power.sym +{ +T 68650 31800 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 69200 31800 68900 31800 4 +N 70600 31800 72300 31800 4 +{ +T 70800 31800 5 10 1 1 0 0 1 +netname=AUX_DAC_D +} +N 75600 45100 76600 45100 4 +{ +T 75700 45100 5 10 1 1 0 0 1 +netname=I2C_A1 +} +N 75600 45300 76600 45300 4 +{ +T 75700 45300 5 10 1 1 0 0 1 +netname=I2C_A0 +} +C 75600 44700 1 90 0 generic-power.sym +{ +T 75350 44900 5 10 1 1 90 3 1 +net=DVDD:1 +} +N 75600 44900 76600 44900 4 +N 77900 39400 79200 39400 4 +{ +T 78300 39400 5 10 1 1 0 0 1 +netname=I2C_A1 +} +N 77900 39000 79200 39000 4 +{ +T 78300 39000 5 10 1 1 0 0 1 +netname=I2C_A0 +} +N 69200 33200 67800 33200 4 +{ +T 68600 33200 5 10 1 1 0 6 1 +netname=RESET +} +N 80000 44400 81300 44400 4 +{ +T 80100 44400 5 10 1 1 0 0 1 +netname=IOUTP_A +} +N 80000 44000 81300 44000 4 +{ +T 80100 44000 5 10 1 1 0 0 1 +netname=IOUTN_A +} +C 86500 43700 1 0 1 SMA-5.sym +{ +T 86500 44500 5 10 1 1 0 6 1 +refdes=J48 +T 86500 43700 5 10 0 1 0 0 1 +footprint=SMA_VERT +} +C 86600 42800 1 180 0 generic-power.sym +{ +T 86400 42550 5 10 1 1 180 3 1 +net=AGND:1 +} +N 86400 43700 86400 42800 4 +C 79900 44600 1 90 1 capacitor-1.sym +{ +T 79600 43900 5 10 1 1 0 6 1 +refdes=C14 +T 79600 44300 5 10 1 1 0 6 1 +value=20pF +T 79900 44600 5 10 0 1 180 2 1 +footprint=0603 +} +C 81300 42800 1 180 0 generic-power.sym +{ +T 81100 42550 5 10 1 1 0 5 1 +net=AGND:1 +} +C 81200 31500 1 180 1 generic-power.sym +{ +T 81400 31250 5 10 1 1 0 5 1 +net=AGND:1 +} +C 81200 43900 1 90 1 resistor-1.sym +{ +T 80900 43500 5 10 1 1 0 6 1 +refdes=R33 +T 80900 43300 5 10 1 1 0 6 1 +value=25 +T 81200 43900 5 10 0 1 90 6 1 +footprint=0603 +} +C 84500 44100 1 0 1 resistor-1.sym +{ +T 84200 44400 5 10 1 1 0 6 1 +refdes=R34 +T 84200 43900 5 10 1 1 0 6 1 +value=25 +T 84500 44100 5 10 0 1 180 2 1 +footprint=0603 +} +N 69200 36000 68600 36000 4 +C 68600 35800 1 90 0 generic-power.sym +{ +T 68350 36000 5 10 1 1 90 3 1 +net=DVDD:1 +} +C 71200 35900 1 90 0 gnd-1.sym +N 70600 36000 70900 36000 4 +N 69200 35600 68800 35600 4 +C 68800 35400 1 90 0 generic-power.sym +{ +T 68550 35600 5 10 1 1 90 3 1 +net=5V:1 +} +C 69200 30000 1 0 0 header10-2.sym +{ +T 69800 32100 5 10 1 1 0 0 1 +refdes=J47 +T 69200 30000 5 10 0 1 0 0 1 +footprint=CONNECTOR 5 2 +} +N 68600 30200 69200 30200 4 +C 68600 30000 1 90 0 generic-power.sym +{ +T 68350 30200 5 10 1 1 90 3 1 +net=AGND:1 +} +C 71200 35500 1 90 0 gnd-1.sym +N 70600 35600 70900 35600 4 +C 71200 33100 1 90 0 gnd-1.sym +N 70600 33200 70900 33200 4 +N 70600 35200 71900 35200 4 +{ +T 70800 35200 5 10 1 1 0 0 1 +netname=I2C_A1 +} +N 67800 35200 69200 35200 4 +{ +T 68000 35200 5 10 1 1 0 0 1 +netname=I2C_A0 +} +C 67800 41700 1 0 0 header16-1.sym +{ +T 68300 45000 5 10 1 1 0 0 1 +refdes=J50 +T 67800 41700 5 10 0 1 0 0 1 +footprint=CONNECTOR 8 2 +} +C 72000 41700 1 0 0 header16-1.sym +{ +T 72500 45000 5 10 1 1 0 0 1 +refdes=J51 +T 72000 41700 5 10 0 1 0 0 1 +footprint=CONNECTOR 8 2 +} +N 69200 43500 69500 43500 4 +C 69800 43400 1 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39400 4 +N 82400 40300 82200 40300 4 +N 82300 39400 82500 39400 4 +N 81100 40200 81100 40300 4 +N 81100 39100 81100 39300 4 +C 82200 40600 1 0 1 resistor-1.sym +{ +T 82000 40400 5 10 1 1 0 6 1 +refdes=R8 +T 81600 40400 5 10 1 1 0 6 1 +value=225 +T 82200 40600 5 10 0 1 180 2 1 +footprint=0603 +} +N 82200 40700 82400 40700 4 +C 80900 41900 1 0 0 generic-power.sym +{ +T 81100 42150 5 10 1 1 180 5 1 +net=AGND:1 +} +C 81000 40800 1 270 1 resistor-1.sym +{ +T 81300 41200 5 10 1 1 180 6 1 +refdes=R36 +T 81300 41400 5 10 1 1 180 6 1 +value=25 +T 81000 40800 5 10 0 1 270 6 1 +footprint=0603 +} +N 81100 40800 81100 40700 4 +N 81100 41900 81100 41700 4 +C 82400 40800 1 90 0 resistor-1.sym +{ +T 82100 41200 5 10 1 1 180 0 1 +refdes=R37 +T 82100 41400 5 10 1 1 180 0 1 +value=500 +T 82400 40800 5 10 0 1 270 8 1 +footprint=0603 +} +N 82300 40700 82300 40800 4 +C 82100 41900 1 0 0 generic-power.sym +{ +T 82300 42150 5 10 1 1 180 5 1 +net=AGND:1 +} +N 82300 41900 82300 41700 4 +N 80000 40700 80000 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86700 35700 5 10 1 1 0 6 1 +refdes=C11 +T 86400 35400 5 10 1 1 0 0 1 +value=10uF +T 85800 35800 5 10 0 1 270 2 1 +footprint=1206 +} +C 85800 36300 1 180 1 capacitor-1.sym +{ +T 86700 36200 5 10 1 1 0 6 1 +refdes=C12 +T 86800 35900 5 10 1 1 0 6 1 +value=0.1uF +T 85800 36300 5 10 0 1 270 2 1 +footprint=0603 +} +N 86900 35100 86900 36100 4 +C 81300 31500 1 0 1 capacitor-1.sym +{ +T 80700 31800 5 10 1 1 0 6 1 +refdes=C5 +T 80800 31500 5 10 1 1 0 6 1 +value=220pF +T 81300 31500 5 10 0 1 90 2 1 +footprint=0603 +} +N 80200 31700 80200 34300 4 +N 80200 31700 80400 31700 4 +N 81300 31700 81400 31700 4 +C 80300 34300 1 90 0 inductor-1.sym +{ +T 80000 34500 5 10 1 1 90 0 1 +refdes=FB1 +T 80300 34300 5 10 0 1 90 0 1 +footprint=1206 +} +C 85800 34100 1 90 0 inductor-1.sym +{ +T 85500 34300 5 10 1 1 90 0 1 +refdes=FB2 +T 85800 34100 5 10 0 1 90 0 1 +footprint=1206 +} +N 80200 35200 80200 35400 4 +N 85700 36200 85700 35000 4 +C 86100 32400 1 270 1 capacitor-1.sym +{ +T 86600 33000 5 10 1 1 0 6 1 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10 1 1 0 6 1 +refdes=R41 +T 85400 40200 5 10 1 1 0 6 1 +value=25 +T 85700 40400 5 10 0 1 180 2 1 +footprint=0603 +} +N 84500 40500 84800 40500 4 +N 85700 40500 85900 40500 4 +N 86300 40000 86300 39100 4 +C 84800 40200 1 90 1 capacitor-1.sym +{ +T 84500 39500 5 10 1 1 0 6 1 +refdes=C32 +T 84500 39900 5 10 1 1 0 6 1 +value=100pF +T 84800 40200 5 10 0 1 180 2 1 +footprint=0603 +} +N 84600 40200 84600 40500 4 +N 84600 39300 84600 39200 4 +N 84600 39200 86300 39200 4 +C 82500 39100 1 180 1 capacitor-1.sym +{ +T 83200 38800 5 10 1 1 90 6 1 +refdes=C34 +T 82800 38800 5 10 1 1 90 6 1 +value=4.7pF +T 82500 39100 5 10 0 1 270 2 1 +footprint=0603 +} +C 82500 42800 1 180 1 capacitor-1.sym +{ +T 83200 42500 5 10 1 1 90 6 1 +refdes=C33 +T 82800 42500 5 10 1 1 90 6 1 +value=4.7pF +T 82500 42800 5 10 0 1 270 2 1 +footprint=0603 +} +N 83500 42600 83500 44200 4 +N 83500 42600 83400 42600 4 +N 82500 42600 82300 42600 4 +N 82300 42600 82300 44000 4 +N 83500 38900 83500 40500 4 +N 82300 38900 82300 40300 4 +N 82300 38900 82500 38900 4 +N 83400 38900 83500 38900 4 diff --git a/usrp-hw/basic-lf/netlist_cmd b/usrp-hw/basic-lf/netlist_cmd new file mode 100755 index 000000000..1d45ba0c4 --- /dev/null +++ b/usrp-hw/basic-lf/netlist_cmd @@ -0,0 +1,6 @@ +gsch2pcb lfrx.prj +gnetlist -g partslist3 -o lfrx.bom lfrx.sch + +gsch2pcb lftx.prj +gnetlist -g partslist3 -o lftx.bom lftx.sch + diff --git a/usrp-hw/pkg/newlib/1008 b/usrp-hw/pkg/newlib/1008 new file mode 100644 index 000000000..b7e3228b4 --- /dev/null +++ b/usrp-hw/pkg/newlib/1008 @@ -0,0 +1,28 @@ +# Examining Arg = -v +# Examining Arg = x=100 +# Found (x, 100) in argument list +# Examining Arg = y=40 +# Found (y, 40) in argument list +# Examining Arg = g=50 +# Found (g, 50) in argument list +# Examining Arg = l=115 +# Found (l, 115) in argument list +# Examining Arg = w=110 +# Found (w, 110) in argument list +# Examining Arg = description=SMD_1008 +# Found (description, SMD_1008) in argument list +Element[0x00000000 "SMD_1008" "" "" 0 0 0 0 3 100 0x00000000] +( +# Part input parameters: w=110, l=115, x=100, y=40, g=50 +# Pad is higher than wide, so draw pad line vertically. +# Create two pads. + Pad(-45 -30 -45 30 40 20 48 "Pad_1" "1" 0x00000100) + Pad(45 -30 45 30 40 20 48 "Pad_2" "2" 0x00000100) +# Using maximum pad size def for . +# Using maximum pad size def for w. +# Create package body outline on silk layer. + ElementLine(-91 -76 91 -76 12) + ElementLine(-91 76 91 76 12) + ElementLine(-91 -76 -91 76 12) + ElementLine(91 -76 91 76 12) +) diff --git a/usrp-hw/pkg/newlib/ADT1-1WT b/usrp-hw/pkg/newlib/ADT1-1WT new file mode 100644 index 000000000..7724e78b2 --- /dev/null +++ b/usrp-hw/pkg/newlib/ADT1-1WT @@ -0,0 +1,20 @@ +# release: pcb-bin 1.99p +# date: Sat Feb 7 13:32:03 2004 +# user: matt () +# host: localhost.localdomain + +Element[0x00000000 "" "" "" 185071 169000 0 0 0 100 0x00000000] +( + Pad[7500 2500 7500 12500 6500 1000 3400 "" "6" 0x00000100] + Pad[17500 2500 17500 12500 6500 1000 3400 "" "5" 0x00004000] + Pad[27500 2500 27500 12500 6500 1000 3400 "" "4" 0x00004000] + Pad[7500 22500 7500 32500 6500 1000 3400 "" "1" 0x00000000] + Pad[17500 22500 17500 32500 6500 1000 3400 "" "2" 0x00004000] + Pad[27500 22500 27500 32500 6500 1000 3400 "" "3" 0x00004000] + ElementLine [0 0 0 35000 1000] + ElementLine [0 35000 35000 35000 1000] + ElementLine [35000 35000 35000 0 1000] + ElementLine [35000 0 0 0 1000] + ElementArc [7500 36500 2000 2000 0 360 1000] + ) + diff --git a/usrp-hw/pkg/newlib/CP-24 b/usrp-hw/pkg/newlib/CP-24 new file mode 100644 index 000000000..f91e18429 --- /dev/null +++ b/usrp-hw/pkg/newlib/CP-24 @@ -0,0 +1,34 @@ + +Element[0x00000000 "" "" "" 8661 8268 0 0 0 100 0x00000000] +( + Pad[-4921 -7873 -4921 -5904 1181 1000 2181 "" "24" 0x00000100] + Pad[4922 -7873 4922 -5904 1181 1000 2181 "" "19" 0x00000100] + Pad[2953 -7873 2953 -5904 1181 1000 2181 "" "20" 0x00000100] + Pad[985 -7873 985 -5904 1181 1000 2181 "" "21" 0x00000100] + Pad[-984 -7873 -984 -5904 1181 1000 2181 "" "22" 0x00000100] + Pad[-2953 -7873 -2953 -5904 1181 1000 2181 "" "23" 0x00000100] + Pad[2953 6103 2953 8072 1181 1000 2181 "" "11" 0x00004100] + Pad[985 6103 985 8072 1181 1000 2181 "" "10" 0x00004100] + Pad[-984 6103 -984 8072 1181 1000 2181 "" "9" 0x00004100] + Pad[-2953 6103 -2953 8072 1181 1000 2181 "" "8" 0x00004100] + Pad[-4921 6103 -4921 8072 1181 1000 2181 "" "7" 0x00004100] + Pad[-8070 5117 -6102 5117 1181 1000 2181 "" "6" 0x00000100] + Pad[4922 6103 4922 8072 1181 1000 2181 "" "12" 0x00004100] + Pad[5906 5117 7874 5117 1181 1000 2181 "" "13" 0x00004100] + Pad[5906 3149 7874 3149 1181 1000 2181 "" "14" 0x00004100] + Pad[5906 1181 7874 1181 1181 1000 2181 "" "15" 0x00004100] + Pad[5906 -787 7874 -787 1181 1000 2181 "" "16" 0x00004100] + Pad[5906 -2755 7874 -2755 1181 1000 2181 "" "17" 0x00004100] + Pad[-8070 3149 -6102 3149 1181 1000 2181 "" "5" 0x00000100] + Pad[-8070 1181 -6102 1181 1181 1000 2181 "" "4" 0x00000100] + Pad[-8070 -787 -6102 -787 1181 1000 2181 "" "3" 0x00000100] + Pad[-8070 -2755 -6102 -2755 1181 1000 2181 "" "2" 0x00000100] + Pad[-8070 -4723 -6102 -4723 1181 1000 2181 "" "1" 0x00000100] + Pad[5906 -4723 7874 -4723 1181 1000 2181 "" "18" 0x00004100] + ElementLine [-8071 -7873 7677 -7873 1000] + ElementLine [7677 -7873 7677 7875 1000] + ElementLine [7677 7875 -8071 7875 1000] + ElementLine [-8071 7875 -8071 -7873 1000] + ElementArc [-6692 -5906 787 787 0 360 1000] + + ) diff --git a/usrp-hw/pkg/newlib/CTS_OSC b/usrp-hw/pkg/newlib/CTS_OSC new file mode 100644 index 000000000..ccbe67d91 --- /dev/null +++ b/usrp-hw/pkg/newlib/CTS_OSC @@ -0,0 +1,16 @@ + +Element["" "" "" "" 38880 49670 0 0 0 100 ""] +( + Pad[-20 -17190 -20 -15190 7100 1596 8696 "" "4" "square"] + Pad[19980 -17190 19980 -15190 7100 1596 8696 "" "3" "square"] + Pad[-20 -690 -20 1310 7100 1596 8696 "" "1" "square,edge2"] + Pad[19980 -690 19980 1310 7100 1596 8696 "" "2" "square,edge2"] + ElementLine [-6020 -23190 25980 -23190 699] + ElementLine [-6020 -23190 -6020 7310 699] + ElementLine [-6020 7310 25980 7310 699] + ElementLine [25980 -23190 25980 7310 699] + ElementLine [-6010 -4300 -5980 -4300 699] + ElementLine [-5980 -4300 -2880 -7400 699] + ElementLine [-2880 -7400 -5850 -10370 699] + + ) diff --git a/usrp-hw/pkg/newlib/CTS_OSC.pcb b/usrp-hw/pkg/newlib/CTS_OSC.pcb new file mode 100644 index 000000000..28ceaddf1 --- /dev/null +++ b/usrp-hw/pkg/newlib/CTS_OSC.pcb @@ -0,0 +1,841 @@ +# release: pcb-bin 1.99q +# date: Tue Jun 7 21:39:25 2005 +# user: matt (Matt Ettus) +# host: localhost.localdomain + +PCB["" 600000 500000] + +Grid[10.00000000 0 0 0] +Cursor[40000 41115 -2.407497] +Thermal[0.500000] +DRC[699 400 699 499] +Flags(0x0000000000000040) +Groups("1,s:4,c:2:3:5,6,7,8:") +Styles["Signal,7099,3599,1799,798:Power,699,5999,3499,999:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"] + +Symbol[' ' 1800] +( +) +Symbol['!' 1200] +( + SymbolLine[0 4500 0 5000 800] + SymbolLine[0 1000 0 3500 800] +) +Symbol['"' 1200] +( + SymbolLine[0 1000 0 2000 800] + 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800] + SymbolLine[0 2500 1000 2500 800] +) +Symbol['u' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 3000 2000 4500 800] +) +Symbol['v' 1200] +( + SymbolLine[0 3000 0 4000 800] + SymbolLine[0 4000 1000 5000 800] + SymbolLine[1000 5000 2000 4000 800] + SymbolLine[2000 3000 2000 4000 800] +) +Symbol['w' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[1000 5000 1500 4500 800] + SymbolLine[1500 3000 1500 4500 800] + SymbolLine[1500 4500 2000 5000 800] + SymbolLine[2000 5000 2500 5000 800] + SymbolLine[2500 5000 3000 4500 800] + SymbolLine[3000 3000 3000 4500 800] +) +Symbol['x' 1200] +( + SymbolLine[0 3000 2000 5000 800] + SymbolLine[0 5000 2000 3000 800] +) +Symbol['y' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[2000 3000 2000 6000 800] + SymbolLine[1500 6500 2000 6000 800] + SymbolLine[500 6500 1500 6500 800] + SymbolLine[0 6000 500 6500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] +) +Symbol['z' 1200] +( + SymbolLine[0 3000 2000 3000 800] + SymbolLine[0 5000 2000 3000 800] + SymbolLine[0 5000 2000 5000 800] +) +Symbol['{' 1200] +( + SymbolLine[500 1500 1000 1000 800] + SymbolLine[500 1500 500 2500 800] + SymbolLine[0 3000 500 2500 800] + SymbolLine[0 3000 500 3500 800] + SymbolLine[500 3500 500 4500 800] + SymbolLine[500 4500 1000 5000 800] +) +Symbol['|' 1200] +( + SymbolLine[0 1000 0 5000 800] +) +Symbol['}' 1200] +( + SymbolLine[0 1000 500 1500 800] + SymbolLine[500 1500 500 2500 800] + SymbolLine[500 2500 1000 3000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[500 3500 500 4500 800] + SymbolLine[0 5000 500 4500 800] +) +Symbol['~' 1200] +( + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1000 3000 800] + SymbolLine[1000 3000 1500 3500 800] + SymbolLine[1500 3500 2000 3500 800] + SymbolLine[2000 3500 2500 3000 800] +) + +Element["" "" "" "" 38880 49670 0 0 0 100 ""] +( + Pad[-20 -17190 -20 -15190 7100 1596 8696 "" "1" "square"] + Pad[19980 -17190 19980 -15190 7100 1596 8696 "" "2" "square"] + Pad[-20 -690 -20 1310 7100 1596 8696 "" "3" "square,edge2"] + Pad[19980 -690 19980 1310 7100 1596 8696 "" "4" "selected,square,edge2"] + ElementLine [-2880 -7400 -5850 -10370 699] + ElementLine [-5980 -4300 -2880 -7400 699] + ElementLine [-6010 -4300 -5980 -4300 699] + ElementLine [25980 -23190 25980 7310 699] + ElementLine [-6020 7310 25980 7310 699] + ElementLine [-6020 -23190 -6020 7310 699] + ElementLine [-6020 -23190 25980 -23190 699] + + ) +Layer(1 "solder") +( +) +Layer(2 "GND") +( +) +Layer(3 "Vcc") +( +) +Layer(4 "component") +( +) +Layer(5 "OTHER5") +( +) +Layer(6 "OTHER6") +( +) +Layer(7 "OTHER7") +( +) +Layer(8 "OTHER8") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( +) diff --git a/usrp-hw/pkg/newlib/CVS/Entries b/usrp-hw/pkg/newlib/CVS/Entries new file mode 100644 index 000000000..74d1e104c --- /dev/null +++ b/usrp-hw/pkg/newlib/CVS/Entries @@ -0,0 +1,15 @@ +/ADT1-1WT/1.1/Sat Apr 17 01:36:35 2004// +/CP-24/1.1/Sat Apr 17 01:36:35 2004// +/LQFP128/1.1/Sat Apr 17 01:36:35 2004// +/PMC/1.1/Sat Apr 17 01:36:35 2004// +/PMC-REVERSE/1.1/Sat Apr 17 01:36:35 2004// +/PQ240/1.1/Sat Apr 17 01:36:35 2004// +/TQFP100/1.1/Sat Apr 17 01:36:35 2004// +/1008/1.1/Thu Jan 27 01:27:55 2005// +/HC49US/1.1/Fri Jan 14 05:20:39 2005// +/MT4937DI5/1.1/Tue Feb 8 03:13:13 2005// +/SOT23-5-LOCAL/1.1/Thu Jan 13 19:23:05 2005// +/SOT23-6/1.1/Tue Jan 11 16:48:41 2005// +/SOT23_5_LOCAL/1.1/Thu Jan 13 19:23:05 2005// +/smtgen.pl/1.1/Thu Jan 27 01:16:56 2005// +D diff --git a/usrp-hw/pkg/newlib/CVS/Repository b/usrp-hw/pkg/newlib/CVS/Repository new file mode 100644 index 000000000..a2df94231 --- /dev/null +++ b/usrp-hw/pkg/newlib/CVS/Repository @@ -0,0 +1 @@ +usrp-hw/pkg/newlib diff --git a/usrp-hw/pkg/newlib/CVS/Root b/usrp-hw/pkg/newlib/CVS/Root new file mode 100644 index 000000000..5cda80542 --- /dev/null +++ b/usrp-hw/pkg/newlib/CVS/Root @@ -0,0 +1 @@ +:ext:localhost:/opt/usrp-hw-cvs diff --git a/usrp-hw/pkg/newlib/HC49US b/usrp-hw/pkg/newlib/HC49US new file mode 100644 index 000000000..2fcbf0e31 --- /dev/null +++ b/usrp-hw/pkg/newlib/HC49US @@ -0,0 +1,12 @@ + +Element[0x00000000 "" "" "" 70748 75055 0 0 0 100 0x00000000] +( + Pad[5905 0 21653 0 6000 2000 8000 "" "2" 0x00004100] + Pad[-21654 0 -5906 0 6000 2000 8000 "" "1" 0x00000100] + ElementLine [-25591 -9842 25590 -9842 1000] + ElementLine [25590 -9842 25590 9843 1000] + ElementLine [25590 9843 -25591 9843 1000] + ElementLine [-25591 9843 -25591 -9842 1000] + + ) + diff --git a/usrp-hw/pkg/newlib/LQFP128 b/usrp-hw/pkg/newlib/LQFP128 new file mode 100644 index 000000000..faab84e13 --- /dev/null +++ b/usrp-hw/pkg/newlib/LQFP128 @@ -0,0 +1,137 @@ +Element(0x00000000 "LQFP128" "" "128 pin QFP" 0 0 3 100 0x00000000) +( +Pad( -1 70 21 70 6 "1" 0x00000100) +Pad( -1 86 21 86 6 "2" 0x00000100) +Pad( -1 102 21 102 6 "3" 0x00000100) +Pad( -1 118 21 118 6 "4" 0x00000100) +Pad( -1 133 21 133 6 "5" 0x00000100) +Pad( -1 149 21 149 6 "6" 0x00000100) +Pad( -1 165 21 165 6 "7" 0x00000100) +Pad( -1 181 21 181 6 "8" 0x00000100) +Pad( -1 196 21 196 6 "9" 0x00000100) +Pad( -1 212 21 212 6 "10" 0x00000100) +Pad( -1 228 21 228 6 "11" 0x00000100) +Pad( -1 244 21 244 6 "12" 0x00000100) +Pad( -1 259 21 259 6 "13" 0x00000100) +Pad( -1 275 21 275 6 "14" 0x00000100) +Pad( -1 291 21 291 6 "15" 0x00000100) +Pad( -1 307 21 307 6 "16" 0x00000100) +Pad( -1 322 21 322 6 "17" 0x00000100) +Pad( -1 338 21 338 6 "18" 0x00000100) +Pad( -1 354 21 354 6 "19" 0x00000100) +Pad( -1 370 21 370 6 "20" 0x00000100) +Pad( -1 385 21 385 6 "21" 0x00000100) +Pad( -1 401 21 401 6 "22" 0x00000100) +Pad( -1 417 21 417 6 "23" 0x00000100) +Pad( -1 433 21 433 6 "24" 0x00000100) +Pad( -1 448 21 448 6 "25" 0x00000100) +Pad( -1 464 21 464 6 "26" 0x00000100) +Pad( -1 480 21 480 6 "27" 0x00000100) +Pad( -1 496 21 496 6 "28" 0x00000100) +Pad( -1 511 21 511 6 "29" 0x00000100) +Pad( -1 527 21 527 6 "30" 0x00000100) +Pad( -1 543 21 543 6 "31" 0x00000100) +Pad( -1 559 21 559 6 "32" 0x00000100) +Pad( 70 631 70 608 6 "33" 0x00000100) +Pad( 86 631 86 608 6 "34" 0x00000100) +Pad( 102 631 102 608 6 "35" 0x00000100) +Pad( 118 631 118 608 6 "36" 0x00000100) +Pad( 133 631 133 608 6 "37" 0x00000100) +Pad( 149 631 149 608 6 "38" 0x00000100) +Pad( 165 631 165 608 6 "39" 0x00000100) +Pad( 181 631 181 608 6 "40" 0x00000100) +Pad( 196 631 196 608 6 "41" 0x00000100) +Pad( 212 631 212 608 6 "42" 0x00000100) +Pad( 228 631 228 608 6 "43" 0x00000100) +Pad( 244 631 244 608 6 "44" 0x00000100) +Pad( 259 631 259 608 6 "45" 0x00000100) +Pad( 275 631 275 608 6 "46" 0x00000100) +Pad( 291 631 291 608 6 "47" 0x00000100) +Pad( 307 631 307 608 6 "48" 0x00000100) +Pad( 322 631 322 608 6 "49" 0x00000100) +Pad( 338 631 338 608 6 "50" 0x00000100) +Pad( 354 631 354 608 6 "51" 0x00000100) +Pad( 370 631 370 608 6 "52" 0x00000100) +Pad( 385 631 385 608 6 "53" 0x00000100) +Pad( 401 631 401 608 6 "54" 0x00000100) +Pad( 417 631 417 608 6 "55" 0x00000100) +Pad( 433 631 433 608 6 "56" 0x00000100) +Pad( 448 631 448 608 6 "57" 0x00000100) +Pad( 464 631 464 608 6 "58" 0x00000100) +Pad( 480 631 480 608 6 "59" 0x00000100) +Pad( 496 631 496 608 6 "60" 0x00000100) +Pad( 511 631 511 608 6 "61" 0x00000100) +Pad( 527 631 527 608 6 "62" 0x00000100) +Pad( 543 631 543 608 6 "63" 0x00000100) +Pad( 559 631 559 608 6 "64" 0x00000100) +Pad( 631 559 608 559 6 "65" 0x00000100) +Pad( 631 543 608 543 6 "66" 0x00000100) +Pad( 631 527 608 527 6 "67" 0x00000100) +Pad( 631 511 608 511 6 "68" 0x00000100) +Pad( 631 496 608 496 6 "69" 0x00000100) +Pad( 631 480 608 480 6 "70" 0x00000100) +Pad( 631 464 608 464 6 "71" 0x00000100) +Pad( 631 448 608 448 6 "72" 0x00000100) +Pad( 631 433 608 433 6 "73" 0x00000100) +Pad( 631 417 608 417 6 "74" 0x00000100) +Pad( 631 401 608 401 6 "75" 0x00000100) +Pad( 631 385 608 385 6 "76" 0x00000100) +Pad( 631 370 608 370 6 "77" 0x00000100) +Pad( 631 354 608 354 6 "78" 0x00000100) +Pad( 631 338 608 338 6 "79" 0x00000100) +Pad( 631 322 608 322 6 "80" 0x00000100) +Pad( 631 307 608 307 6 "81" 0x00000100) +Pad( 631 291 608 291 6 "82" 0x00000100) +Pad( 631 275 608 275 6 "83" 0x00000100) +Pad( 631 259 608 259 6 "84" 0x00000100) +Pad( 631 244 608 244 6 "85" 0x00000100) +Pad( 631 228 608 228 6 "86" 0x00000100) +Pad( 631 212 608 212 6 "87" 0x00000100) +Pad( 631 196 608 196 6 "88" 0x00000100) +Pad( 631 181 608 181 6 "89" 0x00000100) +Pad( 631 165 608 165 6 "90" 0x00000100) +Pad( 631 149 608 149 6 "91" 0x00000100) +Pad( 631 133 608 133 6 "92" 0x00000100) +Pad( 631 118 608 118 6 "93" 0x00000100) +Pad( 631 102 608 102 6 "94" 0x00000100) +Pad( 631 86 608 86 6 "95" 0x00000100) +Pad( 631 70 608 70 6 "96" 0x00000100) +Pad( 559 -1 559 21 6 "97" 0x00000100) +Pad( 543 -1 543 21 6 "98" 0x00000100) +Pad( 527 -1 527 21 6 "99" 0x00000100) +Pad( 511 -1 511 21 6 "100" 0x00000100) +Pad( 496 -1 496 21 6 "101" 0x00000100) +Pad( 480 -1 480 21 6 "102" 0x00000100) +Pad( 464 -1 464 21 6 "103" 0x00000100) +Pad( 448 -1 448 21 6 "104" 0x00000100) +Pad( 433 -1 433 21 6 "105" 0x00000100) +Pad( 417 -1 417 21 6 "106" 0x00000100) +Pad( 401 -1 401 21 6 "107" 0x00000100) +Pad( 385 -1 385 21 6 "108" 0x00000100) +Pad( 370 -1 370 21 6 "109" 0x00000100) +Pad( 354 -1 354 21 6 "110" 0x00000100) +Pad( 338 -1 338 21 6 "111" 0x00000100) +Pad( 322 -1 322 21 6 "112" 0x00000100) +Pad( 307 -1 307 21 6 "113" 0x00000100) +Pad( 291 -1 291 21 6 "114" 0x00000100) +Pad( 275 -1 275 21 6 "115" 0x00000100) +Pad( 259 -1 259 21 6 "116" 0x00000100) +Pad( 244 -1 244 21 6 "117" 0x00000100) +Pad( 228 -1 228 21 6 "118" 0x00000100) +Pad( 212 -1 212 21 6 "119" 0x00000100) +Pad( 196 -1 196 21 6 "120" 0x00000100) +Pad( 181 -1 181 21 6 "121" 0x00000100) +Pad( 165 -1 165 21 6 "122" 0x00000100) +Pad( 149 -1 149 21 6 "123" 0x00000100) +Pad( 133 -1 133 21 6 "124" 0x00000100) +Pad( 118 -1 118 21 6 "125" 0x00000100) +Pad( 102 -1 102 21 6 "126" 0x00000100) +Pad( 86 -1 86 21 6 "127" 0x00000100) +Pad( 70 -1 70 21 6 "128" 0x00000100) +ElementLine ( 75 25 604 25 20 ) +ElementLine ( 604 25 604 604 20 ) +ElementLine ( 604 604 25 604 20 ) +ElementLine ( 25 604 25 75 20 ) +ElementLine ( 25 75 75 25 20 ) +Mark(0 0) +) diff --git a/usrp-hw/pkg/newlib/MT4937DI5 b/usrp-hw/pkg/newlib/MT4937DI5 new file mode 100644 index 000000000..d301f305f --- /dev/null +++ b/usrp-hw/pkg/newlib/MT4937DI5 @@ -0,0 +1,34 @@ + +Element[0x00000000 "" "" "" 399300 254200 0 0 0 100 0x00000000] +( + Pin[-297800 -700 7500 2000 8100 4000 "" "18" 0x00004001] + Pin[-280300 -700 7500 2000 8100 4000 "" "17" 0x00004001] + Pin[-262800 -700 7500 2000 8100 4000 "" "16" 0x00004001] + Pin[-245300 -700 7500 2000 8100 4000 "" "15" 0x00004001] + Pin[-227800 -700 7500 2000 8100 4000 "" "14" 0x00004001] + Pin[-210300 -700 7500 2000 8100 4000 "" "13" 0x00004001] + Pin[-192800 -700 7500 2000 8100 4000 "" "12" 0x00004001] + Pin[-175300 -700 7500 2000 8100 4000 "" "11" 0x00004001] + Pin[-157800 -700 7500 2000 8100 4000 "" "10" 0x00004001] + Pin[-140300 -700 7500 2000 8100 4000 "" "9" 0x00004001] + Pin[-122800 -700 7500 2000 8100 4000 "" "8" 0x00004001] + Pin[-105300 -700 7500 2000 8100 4000 "" "7" 0x00004001] + Pin[-87800 -700 7500 2000 8100 4000 "" "6" 0x00004001] + Pin[-70300 -700 7500 2000 8100 4000 "" "5" 0x00004001] + Pin[-52800 -700 7500 2000 8100 4000 "" "4" 0x00004001] + Pin[-35300 -700 7500 2000 8100 4000 "" "3" 0x00004001] + Pin[-17800 -700 7500 2000 8100 4000 "" "2" 0x00004001] + Pin[-300 -700 7500 2000 8100 4000 "" "1" 0x00004001] + Pin[-303400 -10900 6000 2000 6600 4000 "" "21" 0x00004001] + Pin[-303400 -147500 6000 2000 6600 4000 "" "22" 0x00004001] + Pin[5300 -147500 6000 2000 6600 4000 "" "23" 0x00004001] + Pin[5300 -10900 6000 2000 6600 4000 "" "24" 0x00004001] + ElementLine [-312200 9200 -312200 -157200 1000] + ElementLine [-312200 -157200 14400 -157200 1000] + ElementLine [14400 -157200 14700 -156900 1000] + ElementLine [14700 -156900 14400 -156600 1000] + ElementLine [14400 -156600 14400 11300 1000] + ElementLine [14400 11300 -311600 11300 1000] + ElementLine [-312200 9000 -312200 11400 1000] + + ) diff --git a/usrp-hw/pkg/newlib/PMC b/usrp-hw/pkg/newlib/PMC new file mode 100644 index 000000000..e6a02f745 --- /dev/null +++ b/usrp-hw/pkg/newlib/PMC @@ -0,0 +1,79 @@ +# release: pcb-bin 1.99p +# date: Sat Feb 7 13:32:03 2004 +# user: matt () +# host: localhost.localdomain + +Element[0x00000000 "" "" "" 185071 169000 0 0 0 100 0x00000000] +( + Pin[-6693 -7189 7200 2000 7200 5800 "" "1" 0x00004009] + Pin[128740 -7189 7200 2000 7200 5800 "" "2" 0x00004009] + Pad[0 -19000 0 -9900 2400 1000 3400 "" "2" 0x00000000] + Pad[122047 -4478 122047 4622 2400 1000 3400 "" "63" 0x00004000] + Pad[7874 -19000 7874 -9900 2400 1000 3400 "" "6" 0x00000000] + Pad[3937 -19000 3937 -9900 2400 1000 3400 "" "4" 0x00000000] + Pad[11811 -19000 11811 -9900 2400 1000 3400 "" "8" 0x00000000] + Pad[0 -4478 0 4622 2400 1000 3400 "" "1" 0x00004000] + Pad[15748 -19000 15748 -9900 2400 1000 3400 "" "10" 0x00000000] + Pad[7874 -4478 7874 4622 2400 1000 3400 "" "5" 0x00004000] + Pad[19685 -19000 19685 -9900 2400 1000 3400 "" "12" 0x00000000] + Pad[11811 -4478 11811 4622 2400 1000 3400 "" "7" 0x00004000] + Pad[23622 -19000 23622 -9900 2400 1000 3400 "" "14" 0x00000000] + Pad[15748 -4478 15748 4622 2400 1000 3400 "" "9" 0x00004000] + Pad[27559 -19000 27559 -9900 2400 1000 3400 "" "16" 0x00000000] + Pad[19685 -4478 19685 4622 2400 1000 3400 "" "11" 0x00004000] + Pad[31496 -19000 31496 -9900 2400 1000 3400 "" "18" 0x00000000] + Pad[23622 -4478 23622 4622 2400 1000 3400 "" "13" 0x00004000] + Pad[35433 -19000 35433 -9900 2400 1000 3400 "" "20" 0x00000000] + Pad[27559 -4478 27559 4622 2400 1000 3400 "" "15" 0x00004000] + Pad[39370 -19000 39370 -9900 2400 1000 3400 "" "22" 0x00000000] + Pad[31496 -4478 31496 4622 2400 1000 3400 "" "17" 0x00004000] + Pad[35433 -4478 35433 4622 2400 1000 3400 "" "19" 0x00004000] + Pad[39370 -4478 39370 4622 2400 1000 3400 "" "21" 0x00004000] + Pad[43307 -4478 43307 4622 2400 1000 3400 "" "23" 0x00004000] + Pad[47244 -4478 47244 4622 2400 1000 3400 "" "25" 0x00004000] + Pad[51181 -4478 51181 4622 2400 1000 3400 "" "27" 0x00004000] + Pad[55118 -4478 55118 4622 2400 1000 3400 "" "29" 0x00004000] + Pad[59055 -4478 59055 4622 2400 1000 3400 "" "31" 0x00004000] + Pad[62992 -4478 62992 4622 2400 1000 3400 "" "33" 0x00004000] + Pad[66929 -4478 66929 4622 2400 1000 3400 "" "35" 0x00004000] + Pad[70866 -4478 70866 4622 2400 1000 3400 "" "37" 0x00004000] + Pad[74803 -4478 74803 4622 2400 1000 3400 "" "39" 0x00004000] + Pad[78740 -4478 78740 4622 2400 1000 3400 "" "41" 0x00004000] + Pad[82677 -4478 82677 4622 2400 1000 3400 "" "43" 0x00004000] + Pad[86614 -4478 86614 4622 2400 1000 3400 "" "45" 0x00004000] + Pad[90551 -4478 90551 4622 2400 1000 3400 "" "47" 0x00004000] + Pad[98425 -4478 98425 4622 2400 1000 3400 "" "51" 0x00004000] + Pad[94488 -4478 94488 4622 2400 1000 3400 "" "49" 0x00004000] + Pad[102362 -4478 102362 4622 2400 1000 3400 "" "53" 0x00004000] + Pad[106299 -4478 106299 4622 2400 1000 3400 "" "55" 0x00004000] + Pad[110236 -4478 110236 4622 2400 1000 3400 "" "57" 0x00004000] + Pad[114173 -4478 114173 4622 2400 1000 3400 "" "59" 0x00004000] + Pad[3937 -4478 3937 4622 2400 1000 3400 "" "3" 0x00004000] + Pad[43307 -19000 43307 -9900 2400 1000 3400 "" "24" 0x00000000] + Pad[47244 -19000 47244 -9900 2400 1000 3400 "" "26" 0x00000000] + Pad[51181 -19000 51181 -9900 2400 1000 3400 "" "28" 0x00000000] + Pad[55118 -19000 55118 -9900 2400 1000 3400 "" "30" 0x00000000] + Pad[59055 -19000 59055 -9900 2400 1000 3400 "" "32" 0x00000000] + Pad[62992 -19000 62992 -9900 2400 1000 3400 "" "34" 0x00000000] + Pad[66929 -19000 66929 -9900 2400 1000 3400 "" "36" 0x00000000] + Pad[70866 -19000 70866 -9900 2400 1000 3400 "" "38" 0x00000000] + Pad[74803 -19000 74803 -9900 2400 1000 3400 "" "40" 0x00000000] + Pad[78740 -19000 78740 -9900 2400 1000 3400 "" "42" 0x00000000] + Pad[82677 -19000 82677 -9900 2400 1000 3400 "" "44" 0x00000000] + Pad[86614 -19000 86614 -9900 2400 1000 3400 "" "46" 0x00000000] + Pad[90551 -19000 90551 -9900 2400 1000 3400 "" "48" 0x00000000] + Pad[94488 -19000 94488 -9900 2400 1000 3400 "" "50" 0x00000000] + Pad[98425 -19000 98425 -9900 2400 1000 3400 "" "52" 0x00000000] + Pad[102362 -19000 102362 -9900 2400 1000 3400 "" "54" 0x00000000] + Pad[106299 -19000 106299 -9900 2400 1000 3400 "" "56" 0x00000000] + Pad[110236 -19000 110236 -9900 2400 1000 3400 "" "58" 0x00000000] + Pad[114173 -19000 114173 -9900 2400 1000 3400 "" "60" 0x00000000] + Pad[118110 -19000 118110 -9900 2400 1000 3400 "" "62" 0x00000000] + Pad[122047 -19000 122047 -9900 2400 1000 3400 "" "64" 0x00000000] + Pad[118110 -4478 118110 4622 2400 1000 3400 "" "61" 0x00004000] + ElementLine [134000 -24000 134000 9000 1000] + ElementLine [-11000 -24000 134000 -24000 1000] + ElementLine [134000 9000 -11000 9000 1000] + ElementLine [-11000 9000 -11000 -24000 1000] + ) + diff --git a/usrp-hw/pkg/newlib/PMC-REVERSE b/usrp-hw/pkg/newlib/PMC-REVERSE new file mode 100644 index 000000000..7be4ecdbf --- /dev/null +++ b/usrp-hw/pkg/newlib/PMC-REVERSE @@ -0,0 +1,79 @@ +# release: pcb-bin 1.99p +# date: Sat Feb 7 13:32:03 2004 +# user: matt () +# host: localhost.localdomain + +Element[0x00000000 "" "" "" 185071 169000 0 0 0 100 0x00000000] +( + Pin[-6693 -7189 7200 2000 7200 5800 "" "1" 0x00004009] + Pin[128740 -7189 7200 2000 7200 5800 "" "2" 0x00004009] + Pad[0 -19000 0 -9900 2400 1000 3400 "" "1" 0x00000000] + Pad[122047 -4478 122047 4622 2400 1000 3400 "" "64" 0x00004000] + Pad[7874 -19000 7874 -9900 2400 1000 3400 "" "5" 0x00000000] + Pad[3937 -19000 3937 -9900 2400 1000 3400 "" "3" 0x00000000] + Pad[11811 -19000 11811 -9900 2400 1000 3400 "" "7" 0x00000000] + Pad[0 -4478 0 4622 2400 1000 3400 "" "2" 0x00004000] + Pad[15748 -19000 15748 -9900 2400 1000 3400 "" "9" 0x00000000] + Pad[7874 -4478 7874 4622 2400 1000 3400 "" "6" 0x00004000] + Pad[19685 -19000 19685 -9900 2400 1000 3400 "" "11" 0x00000000] + Pad[11811 -4478 11811 4622 2400 1000 3400 "" "8" 0x00004000] + Pad[23622 -19000 23622 -9900 2400 1000 3400 "" "13" 0x00000000] + Pad[15748 -4478 15748 4622 2400 1000 3400 "" "10" 0x00004000] + Pad[27559 -19000 27559 -9900 2400 1000 3400 "" "15" 0x00000000] + Pad[19685 -4478 19685 4622 2400 1000 3400 "" "12" 0x00004000] + Pad[31496 -19000 31496 -9900 2400 1000 3400 "" "17" 0x00000000] + Pad[23622 -4478 23622 4622 2400 1000 3400 "" "14" 0x00004000] + Pad[35433 -19000 35433 -9900 2400 1000 3400 "" "19" 0x00000000] + Pad[27559 -4478 27559 4622 2400 1000 3400 "" "16" 0x00004000] + Pad[39370 -19000 39370 -9900 2400 1000 3400 "" "21" 0x00000000] + Pad[31496 -4478 31496 4622 2400 1000 3400 "" "18" 0x00004000] + Pad[35433 -4478 35433 4622 2400 1000 3400 "" "20" 0x00004000] + Pad[39370 -4478 39370 4622 2400 1000 3400 "" "22" 0x00004000] + Pad[43307 -4478 43307 4622 2400 1000 3400 "" "24" 0x00004000] + Pad[47244 -4478 47244 4622 2400 1000 3400 "" "26" 0x00004000] + Pad[51181 -4478 51181 4622 2400 1000 3400 "" "28" 0x00004000] + Pad[55118 -4478 55118 4622 2400 1000 3400 "" "30" 0x00004000] + Pad[59055 -4478 59055 4622 2400 1000 3400 "" "32" 0x00004000] + Pad[62992 -4478 62992 4622 2400 1000 3400 "" "34" 0x00004000] + Pad[66929 -4478 66929 4622 2400 1000 3400 "" "36" 0x00004000] + Pad[70866 -4478 70866 4622 2400 1000 3400 "" "38" 0x00004000] + Pad[74803 -4478 74803 4622 2400 1000 3400 "" "40" 0x00004000] + Pad[78740 -4478 78740 4622 2400 1000 3400 "" "42" 0x00004000] + Pad[82677 -4478 82677 4622 2400 1000 3400 "" "44" 0x00004000] + Pad[86614 -4478 86614 4622 2400 1000 3400 "" "46" 0x00004000] + Pad[90551 -4478 90551 4622 2400 1000 3400 "" "48" 0x00004000] + Pad[98425 -4478 98425 4622 2400 1000 3400 "" "52" 0x00004000] + Pad[94488 -4478 94488 4622 2400 1000 3400 "" "50" 0x00004000] + Pad[102362 -4478 102362 4622 2400 1000 3400 "" "54" 0x00004000] + Pad[106299 -4478 106299 4622 2400 1000 3400 "" "56" 0x00004000] + Pad[110236 -4478 110236 4622 2400 1000 3400 "" "58" 0x00004000] + Pad[114173 -4478 114173 4622 2400 1000 3400 "" "60" 0x00004000] + Pad[3937 -4478 3937 4622 2400 1000 3400 "" "4" 0x00004000] + Pad[43307 -19000 43307 -9900 2400 1000 3400 "" "23" 0x00000000] + Pad[47244 -19000 47244 -9900 2400 1000 3400 "" "25" 0x00000000] + Pad[51181 -19000 51181 -9900 2400 1000 3400 "" "27" 0x00000000] + Pad[55118 -19000 55118 -9900 2400 1000 3400 "" "29" 0x00000000] + Pad[59055 -19000 59055 -9900 2400 1000 3400 "" "31" 0x00000000] + Pad[62992 -19000 62992 -9900 2400 1000 3400 "" "33" 0x00000000] + Pad[66929 -19000 66929 -9900 2400 1000 3400 "" "35" 0x00000000] + Pad[70866 -19000 70866 -9900 2400 1000 3400 "" "37" 0x00000000] + Pad[74803 -19000 74803 -9900 2400 1000 3400 "" "39" 0x00000000] + Pad[78740 -19000 78740 -9900 2400 1000 3400 "" "41" 0x00000000] + Pad[82677 -19000 82677 -9900 2400 1000 3400 "" "43" 0x00000000] + Pad[86614 -19000 86614 -9900 2400 1000 3400 "" "45" 0x00000000] + Pad[90551 -19000 90551 -9900 2400 1000 3400 "" "47" 0x00000000] + Pad[94488 -19000 94488 -9900 2400 1000 3400 "" "49" 0x00000000] + Pad[98425 -19000 98425 -9900 2400 1000 3400 "" "51" 0x00000000] + Pad[102362 -19000 102362 -9900 2400 1000 3400 "" "53" 0x00000000] + Pad[106299 -19000 106299 -9900 2400 1000 3400 "" "55" 0x00000000] + Pad[110236 -19000 110236 -9900 2400 1000 3400 "" "57" 0x00000000] + Pad[114173 -19000 114173 -9900 2400 1000 3400 "" "59" 0x00000000] + Pad[118110 -19000 118110 -9900 2400 1000 3400 "" "61" 0x00000000] + Pad[122047 -19000 122047 -9900 2400 1000 3400 "" "63" 0x00000000] + Pad[118110 -4478 118110 4622 2400 1000 3400 "" "62" 0x00004000] + ElementLine [134000 -24000 134000 9000 1000] + ElementLine [-11000 -24000 134000 -24000 1000] + ElementLine [134000 9000 -11000 9000 1000] + ElementLine [-11000 9000 -11000 -24000 1000] + ) + diff --git a/usrp-hw/pkg/newlib/PQ240 b/usrp-hw/pkg/newlib/PQ240 new file mode 100644 index 000000000..73984729d --- /dev/null +++ b/usrp-hw/pkg/newlib/PQ240 @@ -0,0 +1,249 @@ +Element(0x00000000 "pq240" "" "240 pin QFP" 0 0 3 100 0x00000000) +( +Pad( -2 100 25 100 9 "1" 0x00000100) +Pad( -2 120 25 120 9 "2" 0x00000100) +Pad( -2 139 25 139 9 "3" 0x00000100) +Pad( -2 159 25 159 9 "4" 0x00000100) +Pad( -2 179 25 179 9 "5" 0x00000100) +Pad( -2 198 25 198 9 "6" 0x00000100) +Pad( -2 218 25 218 9 "7" 0x00000100) +Pad( -2 238 25 238 9 "8" 0x00000100) +Pad( -2 257 25 257 9 "9" 0x00000100) +Pad( -2 277 25 277 9 "10" 0x00000100) +Pad( -2 297 25 297 9 "11" 0x00000100) +Pad( -2 316 25 316 9 "12" 0x00000100) +Pad( -2 336 25 336 9 "13" 0x00000100) +Pad( -2 356 25 356 9 "14" 0x00000100) +Pad( -2 375 25 375 9 "15" 0x00000100) +Pad( -2 395 25 395 9 "16" 0x00000100) +Pad( -2 415 25 415 9 "17" 0x00000100) +Pad( -2 435 25 435 9 "18" 0x00000100) +Pad( -2 454 25 454 9 "19" 0x00000100) +Pad( -2 474 25 474 9 "20" 0x00000100) +Pad( -2 494 25 494 9 "21" 0x00000100) +Pad( -2 513 25 513 9 "22" 0x00000100) +Pad( -2 533 25 533 9 "23" 0x00000100) +Pad( -2 553 25 553 9 "24" 0x00000100) +Pad( -2 572 25 572 9 "25" 0x00000100) +Pad( -2 592 25 592 9 "26" 0x00000100) +Pad( -2 612 25 612 9 "27" 0x00000100) +Pad( -2 631 25 631 9 "28" 0x00000100) +Pad( -2 651 25 651 9 "29" 0x00000100) +Pad( -2 671 25 671 9 "30" 0x00000100) +Pad( -2 690 25 690 9 "31" 0x00000100) +Pad( -2 710 25 710 9 "32" 0x00000100) +Pad( -2 730 25 730 9 "33" 0x00000100) +Pad( -2 749 25 749 9 "34" 0x00000100) +Pad( -2 769 25 769 9 "35" 0x00000100) +Pad( -2 789 25 789 9 "36" 0x00000100) +Pad( -2 809 25 809 9 "37" 0x00000100) +Pad( -2 828 25 828 9 "38" 0x00000100) +Pad( -2 848 25 848 9 "39" 0x00000100) +Pad( -2 868 25 868 9 "40" 0x00000100) +Pad( -2 887 25 887 9 "41" 0x00000100) +Pad( -2 907 25 907 9 "42" 0x00000100) +Pad( -2 927 25 927 9 "43" 0x00000100) +Pad( -2 946 25 946 9 "44" 0x00000100) +Pad( -2 966 25 966 9 "45" 0x00000100) +Pad( -2 986 25 986 9 "46" 0x00000100) +Pad( -2 1005 25 1005 9 "47" 0x00000100) +Pad( -2 1025 25 1025 9 "48" 0x00000100) +Pad( -2 1045 25 1045 9 "49" 0x00000100) +Pad( -2 1064 25 1064 9 "50" 0x00000100) +Pad( -2 1084 25 1084 9 "51" 0x00000100) +Pad( -2 1104 25 1104 9 "52" 0x00000100) +Pad( -2 1124 25 1124 9 "53" 0x00000100) +Pad( -2 1143 25 1143 9 "54" 0x00000100) +Pad( -2 1163 25 1163 9 "55" 0x00000100) +Pad( -2 1183 25 1183 9 "56" 0x00000100) +Pad( -2 1202 25 1202 9 "57" 0x00000100) +Pad( -2 1222 25 1222 9 "58" 0x00000100) +Pad( -2 1242 25 1242 9 "59" 0x00000100) +Pad( -2 1261 25 1261 9 "60" 0x00000100) +Pad( 100 1364 100 1336 9 "61" 0x00000100) +Pad( 120 1364 120 1336 9 "62" 0x00000100) +Pad( 139 1364 139 1336 9 "63" 0x00000100) +Pad( 159 1364 159 1336 9 "64" 0x00000100) +Pad( 179 1364 179 1336 9 "65" 0x00000100) +Pad( 198 1364 198 1336 9 "66" 0x00000100) +Pad( 218 1364 218 1336 9 "67" 0x00000100) +Pad( 238 1364 238 1336 9 "68" 0x00000100) +Pad( 257 1364 257 1336 9 "69" 0x00000100) +Pad( 277 1364 277 1336 9 "70" 0x00000100) +Pad( 297 1364 297 1336 9 "71" 0x00000100) +Pad( 316 1364 316 1336 9 "72" 0x00000100) +Pad( 336 1364 336 1336 9 "73" 0x00000100) +Pad( 356 1364 356 1336 9 "74" 0x00000100) +Pad( 375 1364 375 1336 9 "75" 0x00000100) +Pad( 395 1364 395 1336 9 "76" 0x00000100) +Pad( 415 1364 415 1336 9 "77" 0x00000100) +Pad( 435 1364 435 1336 9 "78" 0x00000100) +Pad( 454 1364 454 1336 9 "79" 0x00000100) +Pad( 474 1364 474 1336 9 "80" 0x00000100) +Pad( 494 1364 494 1336 9 "81" 0x00000100) +Pad( 513 1364 513 1336 9 "82" 0x00000100) +Pad( 533 1364 533 1336 9 "83" 0x00000100) +Pad( 553 1364 553 1336 9 "84" 0x00000100) +Pad( 572 1364 572 1336 9 "85" 0x00000100) +Pad( 592 1364 592 1336 9 "86" 0x00000100) +Pad( 612 1364 612 1336 9 "87" 0x00000100) +Pad( 631 1364 631 1336 9 "88" 0x00000100) +Pad( 651 1364 651 1336 9 "89" 0x00000100) +Pad( 671 1364 671 1336 9 "90" 0x00000100) +Pad( 690 1364 690 1336 9 "91" 0x00000100) +Pad( 710 1364 710 1336 9 "92" 0x00000100) +Pad( 730 1364 730 1336 9 "93" 0x00000100) +Pad( 749 1364 749 1336 9 "94" 0x00000100) +Pad( 769 1364 769 1336 9 "95" 0x00000100) +Pad( 789 1364 789 1336 9 "96" 0x00000100) +Pad( 809 1364 809 1336 9 "97" 0x00000100) +Pad( 828 1364 828 1336 9 "98" 0x00000100) +Pad( 848 1364 848 1336 9 "99" 0x00000100) +Pad( 868 1364 868 1336 9 "100" 0x00000100) +Pad( 887 1364 887 1336 9 "101" 0x00000100) +Pad( 907 1364 907 1336 9 "102" 0x00000100) +Pad( 927 1364 927 1336 9 "103" 0x00000100) +Pad( 946 1364 946 1336 9 "104" 0x00000100) +Pad( 966 1364 966 1336 9 "105" 0x00000100) +Pad( 986 1364 986 1336 9 "106" 0x00000100) +Pad(1005 1364 1005 1336 9 "107" 0x00000100) +Pad(1025 1364 1025 1336 9 "108" 0x00000100) +Pad(1045 1364 1045 1336 9 "109" 0x00000100) +Pad(1064 1364 1064 1336 9 "110" 0x00000100) +Pad(1084 1364 1084 1336 9 "111" 0x00000100) +Pad(1104 1364 1104 1336 9 "112" 0x00000100) +Pad(1124 1364 1124 1336 9 "113" 0x00000100) +Pad(1143 1364 1143 1336 9 "114" 0x00000100) +Pad(1163 1364 1163 1336 9 "115" 0x00000100) +Pad(1183 1364 1183 1336 9 "116" 0x00000100) +Pad(1202 1364 1202 1336 9 "117" 0x00000100) +Pad(1222 1364 1222 1336 9 "118" 0x00000100) +Pad(1242 1364 1242 1336 9 "119" 0x00000100) +Pad(1261 1364 1261 1336 9 "120" 0x00000100) +Pad(1364 1261 1336 1261 9 "121" 0x00000100) +Pad(1364 1242 1336 1242 9 "122" 0x00000100) +Pad(1364 1222 1336 1222 9 "123" 0x00000100) +Pad(1364 1202 1336 1202 9 "124" 0x00000100) +Pad(1364 1183 1336 1183 9 "125" 0x00000100) +Pad(1364 1163 1336 1163 9 "126" 0x00000100) +Pad(1364 1143 1336 1143 9 "127" 0x00000100) +Pad(1364 1124 1336 1124 9 "128" 0x00000100) +Pad(1364 1104 1336 1104 9 "129" 0x00000100) +Pad(1364 1084 1336 1084 9 "130" 0x00000100) +Pad(1364 1064 1336 1064 9 "131" 0x00000100) +Pad(1364 1045 1336 1045 9 "132" 0x00000100) +Pad(1364 1025 1336 1025 9 "133" 0x00000100) +Pad(1364 1005 1336 1005 9 "134" 0x00000100) +Pad(1364 986 1336 986 9 "135" 0x00000100) +Pad(1364 966 1336 966 9 "136" 0x00000100) +Pad(1364 946 1336 946 9 "137" 0x00000100) +Pad(1364 927 1336 927 9 "138" 0x00000100) +Pad(1364 907 1336 907 9 "139" 0x00000100) +Pad(1364 887 1336 887 9 "140" 0x00000100) +Pad(1364 868 1336 868 9 "141" 0x00000100) +Pad(1364 848 1336 848 9 "142" 0x00000100) +Pad(1364 828 1336 828 9 "143" 0x00000100) +Pad(1364 809 1336 809 9 "144" 0x00000100) +Pad(1364 789 1336 789 9 "145" 0x00000100) +Pad(1364 769 1336 769 9 "146" 0x00000100) +Pad(1364 749 1336 749 9 "147" 0x00000100) +Pad(1364 730 1336 730 9 "148" 0x00000100) +Pad(1364 710 1336 710 9 "149" 0x00000100) +Pad(1364 690 1336 690 9 "150" 0x00000100) +Pad(1364 671 1336 671 9 "151" 0x00000100) +Pad(1364 651 1336 651 9 "152" 0x00000100) +Pad(1364 631 1336 631 9 "153" 0x00000100) +Pad(1364 612 1336 612 9 "154" 0x00000100) +Pad(1364 592 1336 592 9 "155" 0x00000100) +Pad(1364 572 1336 572 9 "156" 0x00000100) +Pad(1364 553 1336 553 9 "157" 0x00000100) +Pad(1364 533 1336 533 9 "158" 0x00000100) +Pad(1364 513 1336 513 9 "159" 0x00000100) +Pad(1364 494 1336 494 9 "160" 0x00000100) +Pad(1364 474 1336 474 9 "161" 0x00000100) +Pad(1364 454 1336 454 9 "162" 0x00000100) +Pad(1364 435 1336 435 9 "163" 0x00000100) +Pad(1364 415 1336 415 9 "164" 0x00000100) +Pad(1364 395 1336 395 9 "165" 0x00000100) +Pad(1364 375 1336 375 9 "166" 0x00000100) +Pad(1364 356 1336 356 9 "167" 0x00000100) +Pad(1364 336 1336 336 9 "168" 0x00000100) +Pad(1364 316 1336 316 9 "169" 0x00000100) +Pad(1364 297 1336 297 9 "170" 0x00000100) +Pad(1364 277 1336 277 9 "171" 0x00000100) +Pad(1364 257 1336 257 9 "172" 0x00000100) +Pad(1364 238 1336 238 9 "173" 0x00000100) +Pad(1364 218 1336 218 9 "174" 0x00000100) +Pad(1364 198 1336 198 9 "175" 0x00000100) +Pad(1364 179 1336 179 9 "176" 0x00000100) +Pad(1364 159 1336 159 9 "177" 0x00000100) +Pad(1364 139 1336 139 9 "178" 0x00000100) +Pad(1364 120 1336 120 9 "179" 0x00000100) +Pad(1364 100 1336 100 9 "180" 0x00000100) +Pad(1261 -2 1261 25 9 "181" 0x00000100) +Pad(1242 -2 1242 25 9 "182" 0x00000100) +Pad(1222 -2 1222 25 9 "183" 0x00000100) +Pad(1202 -2 1202 25 9 "184" 0x00000100) +Pad(1183 -2 1183 25 9 "185" 0x00000100) +Pad(1163 -2 1163 25 9 "186" 0x00000100) +Pad(1143 -2 1143 25 9 "187" 0x00000100) +Pad(1124 -2 1124 25 9 "188" 0x00000100) +Pad(1104 -2 1104 25 9 "189" 0x00000100) +Pad(1084 -2 1084 25 9 "190" 0x00000100) +Pad(1064 -2 1064 25 9 "191" 0x00000100) +Pad(1045 -2 1045 25 9 "192" 0x00000100) +Pad(1025 -2 1025 25 9 "193" 0x00000100) +Pad(1005 -2 1005 25 9 "194" 0x00000100) +Pad( 986 -2 986 25 9 "195" 0x00000100) +Pad( 966 -2 966 25 9 "196" 0x00000100) +Pad( 946 -2 946 25 9 "197" 0x00000100) +Pad( 927 -2 927 25 9 "198" 0x00000100) +Pad( 907 -2 907 25 9 "199" 0x00000100) +Pad( 887 -2 887 25 9 "200" 0x00000100) +Pad( 868 -2 868 25 9 "201" 0x00000100) +Pad( 848 -2 848 25 9 "202" 0x00000100) +Pad( 828 -2 828 25 9 "203" 0x00000100) +Pad( 809 -2 809 25 9 "204" 0x00000100) +Pad( 789 -2 789 25 9 "205" 0x00000100) +Pad( 769 -2 769 25 9 "206" 0x00000100) +Pad( 749 -2 749 25 9 "207" 0x00000100) +Pad( 730 -2 730 25 9 "208" 0x00000100) +Pad( 710 -2 710 25 9 "209" 0x00000100) +Pad( 690 -2 690 25 9 "210" 0x00000100) +Pad( 671 -2 671 25 9 "211" 0x00000100) +Pad( 651 -2 651 25 9 "212" 0x00000100) +Pad( 631 -2 631 25 9 "213" 0x00000100) +Pad( 612 -2 612 25 9 "214" 0x00000100) +Pad( 592 -2 592 25 9 "215" 0x00000100) +Pad( 572 -2 572 25 9 "216" 0x00000100) +Pad( 553 -2 553 25 9 "217" 0x00000100) +Pad( 533 -2 533 25 9 "218" 0x00000100) +Pad( 513 -2 513 25 9 "219" 0x00000100) +Pad( 494 -2 494 25 9 "220" 0x00000100) +Pad( 474 -2 474 25 9 "221" 0x00000100) +Pad( 454 -2 454 25 9 "222" 0x00000100) +Pad( 435 -2 435 25 9 "223" 0x00000100) +Pad( 415 -2 415 25 9 "224" 0x00000100) +Pad( 395 -2 395 25 9 "225" 0x00000100) +Pad( 375 -2 375 25 9 "226" 0x00000100) +Pad( 356 -2 356 25 9 "227" 0x00000100) +Pad( 336 -2 336 25 9 "228" 0x00000100) +Pad( 316 -2 316 25 9 "229" 0x00000100) +Pad( 297 -2 297 25 9 "230" 0x00000100) +Pad( 277 -2 277 25 9 "231" 0x00000100) +Pad( 257 -2 257 25 9 "232" 0x00000100) +Pad( 238 -2 238 25 9 "233" 0x00000100) +Pad( 218 -2 218 25 9 "234" 0x00000100) +Pad( 198 -2 198 25 9 "235" 0x00000100) +Pad( 179 -2 179 25 9 "236" 0x00000100) +Pad( 159 -2 159 25 9 "237" 0x00000100) +Pad( 139 -2 139 25 9 "238" 0x00000100) +Pad( 120 -2 120 25 9 "239" 0x00000100) +Pad( 100 -2 100 25 9 "240" 0x00000100) +ElementLine ( 80 30 1331 30 20 ) +ElementLine ( 1331 30 1331 1331 20 ) +ElementLine ( 1331 1331 30 1331 20 ) +ElementLine ( 30 1331 30 80 20 ) +ElementLine ( 30 80 80 30 20 ) +Mark(0 0) +) diff --git a/usrp-hw/pkg/newlib/SOT23-5-LOCAL b/usrp-hw/pkg/newlib/SOT23-5-LOCAL new file mode 100644 index 000000000..b13ad361f --- /dev/null +++ b/usrp-hw/pkg/newlib/SOT23-5-LOCAL @@ -0,0 +1,16 @@ +Element(0x0 "" "" "" -44 -121 0 100 0x0) +( + Pad(-64 -37 -40 -37 24 "" "1" 0x0100) + Pad(-64 0 -40 0 24 "" "2" 0x0100) + Pad(-64 37 -40 37 24 "" "3" 0x0100) + Pad(40 37 64 37 24 "" "4" 0x0100) + Pad(40 -37 64 -37 24 "" "5" 0x0100) + ElementLine(-18 -22 -18 -49 10) + ElementLine(-18 -49 -5 -61 10) + ElementLine(-5 -61 18 -61 10) + ElementLine(18 -61 18 -22 10) + ElementLine(-18 22 -18 61 10) + ElementLine(-18 61 18 61 10) + ElementLine(18 61 18 22 10) + Mark(0 0) +) diff --git a/usrp-hw/pkg/newlib/SOT23-6 b/usrp-hw/pkg/newlib/SOT23-6 new file mode 100644 index 000000000..85956b2e2 --- /dev/null +++ b/usrp-hw/pkg/newlib/SOT23-6 @@ -0,0 +1,17 @@ +Element(0x0 "SOT-23-LTC-S6" "" "" -44 -121 0 100 0x0) +( + Pad(-64 -37 -40 -37 24 "" "1" 0x0100) + Pad(-64 0 -40 0 24 "" "2" 0x0100) + Pad(-64 37 -40 37 24 "" "3" 0x0100) + Pad(40 37 64 37 24 "" "4" 0x0100) + Pad(40 0 64 0 24 "" "5" 0x0100) + Pad(40 -37 64 -37 24 "" "6" 0x0100) + ElementLine(-18 -22 -18 -49 10) + ElementLine(-18 -49 -5 -61 10) + ElementLine(-5 -61 18 -61 10) + ElementLine(18 -61 18 -22 10) + ElementLine(-18 22 -18 61 10) + ElementLine(-18 61 18 61 10) + ElementLine(18 61 18 22 10) + Mark(0 0) +) diff --git a/usrp-hw/pkg/newlib/SOT23_5_LOCAL b/usrp-hw/pkg/newlib/SOT23_5_LOCAL new file mode 120000 index 000000000..b8ce7e546 --- /dev/null +++ b/usrp-hw/pkg/newlib/SOT23_5_LOCAL @@ -0,0 +1 @@ +SOT23-5-LOCAL
\ No newline at end of file diff --git a/usrp-hw/pkg/newlib/SOT_23_6_LOCAL b/usrp-hw/pkg/newlib/SOT_23_6_LOCAL new file mode 100644 index 000000000..b13ad361f --- /dev/null +++ b/usrp-hw/pkg/newlib/SOT_23_6_LOCAL @@ -0,0 +1,16 @@ +Element(0x0 "" "" "" -44 -121 0 100 0x0) +( + Pad(-64 -37 -40 -37 24 "" "1" 0x0100) + Pad(-64 0 -40 0 24 "" "2" 0x0100) + Pad(-64 37 -40 37 24 "" "3" 0x0100) + Pad(40 37 64 37 24 "" "4" 0x0100) + Pad(40 -37 64 -37 24 "" "5" 0x0100) + ElementLine(-18 -22 -18 -49 10) + ElementLine(-18 -49 -5 -61 10) + ElementLine(-5 -61 18 -61 10) + ElementLine(18 -61 18 -22 10) + ElementLine(-18 22 -18 61 10) + ElementLine(-18 61 18 61 10) + ElementLine(18 61 18 22 10) + Mark(0 0) +) diff --git a/usrp-hw/pkg/newlib/TQFP100 b/usrp-hw/pkg/newlib/TQFP100 new file mode 100644 index 000000000..32f34ffa9 --- /dev/null +++ b/usrp-hw/pkg/newlib/TQFP100 @@ -0,0 +1,109 @@ +Element(0x00000000 "pq100" "" "100 pin QFP" 0 0 3 100 0x00000000) +( +Pad( -2 78 25 78 9 "1" 0x00000100) +Pad( -2 98 25 98 9 "2" 0x00000100) +Pad( -2 118 25 118 9 "3" 0x00000100) +Pad( -2 137 25 137 9 "4" 0x00000100) +Pad( -2 157 25 157 9 "5" 0x00000100) +Pad( -2 177 25 177 9 "6" 0x00000100) +Pad( -2 196 25 196 9 "7" 0x00000100) +Pad( -2 216 25 216 9 "8" 0x00000100) +Pad( -2 236 25 236 9 "9" 0x00000100) +Pad( -2 255 25 255 9 "10" 0x00000100) +Pad( -2 275 25 275 9 "11" 0x00000100) +Pad( -2 295 25 295 9 "12" 0x00000100) +Pad( -2 314 25 314 9 "13" 0x00000100) +Pad( -2 334 25 334 9 "14" 0x00000100) +Pad( -2 354 25 354 9 "15" 0x00000100) +Pad( -2 374 25 374 9 "16" 0x00000100) +Pad( -2 393 25 393 9 "17" 0x00000100) +Pad( -2 413 25 413 9 "18" 0x00000100) +Pad( -2 433 25 433 9 "19" 0x00000100) +Pad( -2 452 25 452 9 "20" 0x00000100) +Pad( -2 472 25 472 9 "21" 0x00000100) +Pad( -2 492 25 492 9 "22" 0x00000100) +Pad( -2 511 25 511 9 "23" 0x00000100) +Pad( -2 531 25 531 9 "24" 0x00000100) +Pad( -2 551 25 551 9 "25" 0x00000100) +Pad( 78 632 78 603 9 "26" 0x00000100) +Pad( 98 632 98 603 9 "27" 0x00000100) +Pad( 118 632 118 603 9 "28" 0x00000100) +Pad( 137 632 137 603 9 "29" 0x00000100) +Pad( 157 632 157 603 9 "30" 0x00000100) +Pad( 177 632 177 603 9 "31" 0x00000100) +Pad( 196 632 196 603 9 "32" 0x00000100) +Pad( 216 632 216 603 9 "33" 0x00000100) +Pad( 236 632 236 603 9 "34" 0x00000100) +Pad( 255 632 255 603 9 "35" 0x00000100) +Pad( 275 632 275 603 9 "36" 0x00000100) +Pad( 295 632 295 603 9 "37" 0x00000100) +Pad( 314 632 314 603 9 "38" 0x00000100) +Pad( 334 632 334 603 9 "39" 0x00000100) +Pad( 354 632 354 603 9 "40" 0x00000100) +Pad( 374 632 374 603 9 "41" 0x00000100) +Pad( 393 632 393 603 9 "42" 0x00000100) +Pad( 413 632 413 603 9 "43" 0x00000100) +Pad( 433 632 433 603 9 "44" 0x00000100) +Pad( 452 632 452 603 9 "45" 0x00000100) +Pad( 472 632 472 603 9 "46" 0x00000100) +Pad( 492 632 492 603 9 "47" 0x00000100) +Pad( 511 632 511 603 9 "48" 0x00000100) +Pad( 531 632 531 603 9 "49" 0x00000100) +Pad( 551 632 551 603 9 "50" 0x00000100) +Pad( 632 551 603 551 9 "51" 0x00000100) +Pad( 632 531 603 531 9 "52" 0x00000100) +Pad( 632 511 603 511 9 "53" 0x00000100) +Pad( 632 492 603 492 9 "54" 0x00000100) +Pad( 632 472 603 472 9 "55" 0x00000100) +Pad( 632 452 603 452 9 "56" 0x00000100) +Pad( 632 433 603 433 9 "57" 0x00000100) +Pad( 632 413 603 413 9 "58" 0x00000100) +Pad( 632 393 603 393 9 "59" 0x00000100) +Pad( 632 374 603 374 9 "60" 0x00000100) +Pad( 632 354 603 354 9 "61" 0x00000100) +Pad( 632 334 603 334 9 "62" 0x00000100) +Pad( 632 314 603 314 9 "63" 0x00000100) +Pad( 632 295 603 295 9 "64" 0x00000100) +Pad( 632 275 603 275 9 "65" 0x00000100) +Pad( 632 255 603 255 9 "66" 0x00000100) +Pad( 632 236 603 236 9 "67" 0x00000100) +Pad( 632 216 603 216 9 "68" 0x00000100) +Pad( 632 196 603 196 9 "69" 0x00000100) +Pad( 632 177 603 177 9 "70" 0x00000100) +Pad( 632 157 603 157 9 "71" 0x00000100) +Pad( 632 137 603 137 9 "72" 0x00000100) +Pad( 632 118 603 118 9 "73" 0x00000100) +Pad( 632 98 603 98 9 "74" 0x00000100) +Pad( 632 78 603 78 9 "75" 0x00000100) +Pad( 551 -2 551 25 9 "76" 0x00000100) +Pad( 531 -2 531 25 9 "77" 0x00000100) +Pad( 511 -2 511 25 9 "78" 0x00000100) +Pad( 492 -2 492 25 9 "79" 0x00000100) +Pad( 472 -2 472 25 9 "80" 0x00000100) +Pad( 452 -2 452 25 9 "81" 0x00000100) +Pad( 433 -2 433 25 9 "82" 0x00000100) +Pad( 413 -2 413 25 9 "83" 0x00000100) +Pad( 393 -2 393 25 9 "84" 0x00000100) +Pad( 374 -2 374 25 9 "85" 0x00000100) +Pad( 354 -2 354 25 9 "86" 0x00000100) +Pad( 334 -2 334 25 9 "87" 0x00000100) +Pad( 314 -2 314 25 9 "88" 0x00000100) +Pad( 295 -2 295 25 9 "89" 0x00000100) +Pad( 275 -2 275 25 9 "90" 0x00000100) +Pad( 255 -2 255 25 9 "91" 0x00000100) +Pad( 236 -2 236 25 9 "92" 0x00000100) +Pad( 216 -2 216 25 9 "93" 0x00000100) +Pad( 196 -2 196 25 9 "94" 0x00000100) +Pad( 177 -2 177 25 9 "95" 0x00000100) +Pad( 157 -2 157 25 9 "96" 0x00000100) +Pad( 137 -2 137 25 9 "97" 0x00000100) +Pad( 118 -2 118 25 9 "98" 0x00000100) +Pad( 98 -2 98 25 9 "99" 0x00000100) +Pad( 78 -2 78 25 9 "100" 0x00000100) +ElementLine ( 80 30 599 30 20 ) +ElementLine ( 599 30 599 599 20 ) +ElementLine ( 599 599 30 599 20 ) +ElementLine ( 30 599 30 80 20 ) +ElementLine ( 30 80 80 30 20 ) +Mark(0 0) +) diff --git a/usrp-hw/pkg/newlib/TSOT23-95P-280L1-6N__LTC_S6_Package b/usrp-hw/pkg/newlib/TSOT23-95P-280L1-6N__LTC_S6_Package new file mode 100644 index 000000000..f82fb3b5d --- /dev/null +++ b/usrp-hw/pkg/newlib/TSOT23-95P-280L1-6N__LTC_S6_Package @@ -0,0 +1,16 @@ +Element[0x0 "TSOT23-95P-280L1-6N__LTC_S6_Package" "" "" 0 0 -5500 -11700 0 100 0x0] +( + Pad[-6350 -3700 -3950 -3700 2400 2000 4400 "" "1" 0x0100] + Pad[-6350 0 -3950 0 2400 2000 4400 "" "2" 0x0100] + Pad[-6350 3700 -3950 3700 2400 2000 4400 "" "3" 0x0100] + Pad[3950 3700 6350 3700 2400 2000 4400 "" "4" 0x0100] + Pad[3950 0 6350 0 2400 2000 4400 "" "5" 0x0100] + Pad[3950 -3700 6350 -3700 2400 2000 4400 "" "6" 0x0100] + ElementLine[-1750 -2200 -1750 -4475 1000] + ElementLine[-1750 -4475 -525 -5700 1000] + ElementLine[-525 -5700 1750 -5700 1000] + ElementLine[1750 -5700 1750 -2200 1000] + ElementLine[-1750 2200 -1750 5700 1000] + ElementLine[-1750 5700 1750 5700 1000] + ElementLine[1750 5700 1750 2200 1000] +) diff --git a/usrp-hw/pkg/newlib/smtgen.pl b/usrp-hw/pkg/newlib/smtgen.pl new file mode 100755 index 000000000..7b00710fb --- /dev/null +++ b/usrp-hw/pkg/newlib/smtgen.pl @@ -0,0 +1,336 @@ +#! /usr/bin/env perl +# +# smtgen.pl -- Perl script which generates PCB land patterns for two pad +# passives. +# +# Copyright (C) 2005 Stuart D. Brorson. +# +#====================================================================== +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA +#====================================================================== +# +# Revision history +# +# 20050117 -- Initial release. SDB. +# +#====================================================================== + + +use POSIX; + +# global variables +$VERBOSE = 0; # set to 1 for lots of spew +$l = $w = $x = $y = $g = -1; # initialize geometry to unrealistic value. + + +# These numbers taken from the Cutler-Hammer design guidelines doc which is +# avaliable on the web at the San Diego chapter of the IPC: +# http://dcchapters.ipc.org/SanDiego/library1.htm +# Note that they are very conservative numbers & produce large land patterns. +# You can replace them with number more to your liking if desired. +# +$SilkWidth = 12; # Silkscreen line width +$SilkClearance = 20+$SilkWidth/2; # Clearance from end of pad metal to beginning of silk. +$MaskClearance = 8; # Clearance from end of pad metal to beginning of mask. +$PadPlaneClearance = 20; # Clearance from end of pad metal to any + # surrounding metal planes. This can be made smaller if + # desired. + +$description = ""; # Text which is put into the footprint +$pcb_name = ""; +$value = ""; + +$UsageString = " +=============================================================================== +smtgen -- Copyright 2005 by Stuart Brorson. This script is GPL'ed software +Please look at the source to read licencing details. + +This script creates PCB footprint files for two pad SMT passives such as 0805 +resistors and caps. You specify the actual pad dimensions on the command +line, and the program outputs (to STDOUT) the corresponding newlib footprint. +Redirect STDOUT to a file when you want to store your results. + + +Args: + + -v (Optional) Use verbose mode when running (for debug purposes). + --help (Optional) Prints this help menu. + y=<number> (Mandatory) Set pad width to <number>. Dimensions are mils. Refer to + pad drawing below for explanation of geometric parameters. + x=<number> (Mandatory) Set pad length to <number>. Dimensions are mils. Refer to + pad drawing below for explanation of geometric parameters. + g=<number> (Mandatory) Set pad to pad distance to <number>. Dimensions are mils. + Refer to pad drawing below for explanation of geometric parameters. + l=<number> (Optional) Set footprint length to <number>. Dimensions are mils. + Refer to pad drawing below for explanation of geometric parameters. + If this is not declared, then the silkscreen is placed one clearance distance + away from the pad edge. + w=<number> (Optional) Set footprint width to <number>. Dimensions are mils. + Refer to pad drawing below for explanation of geometric parameters. + If this is not declared, then the silkscreen is placed one clearance distance + away from the pad edge. + description (Optional) String description which goes into Element declaration. + value (Optional) String description which goes into Element declaration. + pcb_name (Optional) String description (of refdes) which goes into Element declaration. + + +Example usage: + +perl smtgen.pl -v l=85 w=55 g=32 x=38 y=59 description=SMD_Res_0805 + +All values are in mil. The pad is always drawn horizontally. smtgen assumes +the following geometrical description of the landing pattern: + + + |<-------------------- l -------------------->| + | | + | | + | | + + --- ************************************************* + ^ * * + | * -------------- -------------- * --- + | * | | | | * ^ + * | | | | * | + w * | | + | | * x + * | | | \\ | * | + | * | | | \\| * v + | * -------------- -------------\\ * --- + v * \\ * + --- **********************************************\\** + \\ \\ + | | | |\\ \\------ Pad. + | | | | \\ + |<--- y -->|<-- g -->|<--- y -->| \\ + \\------ Silkscreen outline. + + +=============================================================================== +"; + + +# Get args. +@ArgList = @ARGV; +ParseArgs(@ArgList); # Args are global variables, so they just appear after this call. + + +################# Write out Element preamble #################### +print("Element[0x00000000 \"$description\" \"$pcb_name\" \"$value\" 0 0 0 0 3 100 0x00000000]\n"); +print("(\n"); + +print("# Part input parameters: w=$w, l=$l, x=$x, y=$y, g=$g \n"); + +################# This bit creates the two pads #################### + +if ($y > $x) { + # pad is longer than wide, so draw pad line horizontally + print_verbose("# Pad is wider than high, so draw pad line horizontally.\n"); + $wp = $y - $x; # length of line defining pad + $t = ceil($x); # pad thickness parameter + + # Note that units are screwey here. x1 & y1 are PCB's units + # units (x increases to the right, y increases down). Above, x and y + # were those defined by the IPC to describe footprints. + ($x1, $y1) = ( -ceil( ($g/2 + $y/2)), 0); # center point of left pad. + ($x1L, $y1B) = ( ceil($x1-$wp/2), 0) ; # start point of left pad. + ($x1R, $y1T) = ( ceil($x1+$wp/2), 0 ); # end point of left pad. + + ($x2, $y2) = ( ceil(+($g/2 + $y/2)), 0); # center point of right pad. + ($x2L, $y2B) = ( ceil($x2-$wp/2), 0 ); # start point of left pad. + ($x2R, $y2T) = ( ceil($x2+$wp/2), 0 ); # end point of left pad. +} else { + # pad is higher than wide, so draw pad line vertically + print_verbose("# Pad is higher than wide, so draw pad line vertically.\n"); + $hp = $x - $y; # length of line defining pad + $t = ceil($y); # pad thickness parameter + + ($x1, $y1) = ( ceil( -($g/2 + $y/2)), 0); # center point of left pad. + ($x1L, $y1B) = ( $x1, -ceil($hp/2)) ; # start point of left pad. + ($x1R, $y1T) = ( $x1, ceil($hp/2)); # end point of left pad. + + ($x2, $y2) = ( ceil(+($g/2 + $y/2)), 0); # center point of right pad. + ($x2L, $y2B) = ( $x2, -ceil($hp/2)) ; # start point of left pad. + ($x2R, $y2T) = ( $x2, ceil($hp/2)); # end point of left pad. +} + +$Mask = $t + $MaskClearance; + +print("# Create two pads.\n"); +print(" Pad($x1L $y1B $x1R $y1T $t $PadPlaneClearance $Mask \"Pad_1\" \"1\" 0x00000100)\n"); +print(" Pad($x2L $y2B $x2R $y2T $t $PadPlaneClearance $Mask \"Pad_2\" \"2\" 0x00000100)\n"); + + +################# Create the four silk lines #################### +# The silkscreen lines are either determined by the larger of: +# the body width (WxL), or +# the max extent of the pads + $SilkClearance + +# X extents: +if (ceil($l/2) > ceil($g/2 + $y + $SilkClearance)) { + # User's l is larger. Use it. + print_verbose("# Using user's def for l.\n"); + $XL_M = - ceil($l/2); + $XL_P = ceil($l/2); +} else { + # Silk defined by pad size is larger. + print_verbose("# Using maximum pad size def for .\n"); + $XL_M = - ceil($g/2 + $y + $SilkClearance); + $XL_P = ceil($g/2 + $y + $SilkClearance); +} + +# Y extents: +if (ceil($w/2) > ceil($x/2 + $SilkClearance)) { + # User's w is larger. Use it. + print_verbose("# Using user's def for w.\n"); + $YL_M = - ceil($w/2); + $YL_P = ceil($w/2); +} else { + # Silk defined by pad size is larger. + print_verbose("# Using maximum pad size def for w.\n"); + $YL_M = - ceil($x/2 + $SilkClearance); + $YL_P = ceil($x/2 + $SilkClearance); +} + +print("# Create package body outline on silk layer.\n"); +print(" ElementLine($XL_M $YL_M $XL_P $YL_M $SilkWidth)\n"); +print(" ElementLine($XL_M $YL_P $XL_P $YL_P $SilkWidth)\n"); +print(" ElementLine($XL_M $YL_M $XL_M $YL_P $SilkWidth)\n"); +print(" ElementLine($XL_P $YL_M $XL_P $YL_P $SilkWidth)\n"); + + +################# Write out closing paren #################### +print(")\n"); + +exit(0); + + +######################### Subs ######################## +sub ParseArgs { +# This subroutine runs through the arg list submitted on the command line +# and stuffs the values found into the appropriate variable. If an +# inappropriate value is found, it just prints out the usage info and +# calls exit(-1). Remember that all variables in Perl are global unless +# otherwise declared; I take advantage of this feature heavily! :-) + my $Arg; + + # First figure out if we are in verbose mode. + foreach $Arg (@_) { + #match -v + if ( $Arg =~ m/-v/ ) { + $VERBOSE = 1; + break; + } + } + + # OK, having settled that, we now process real args. + foreach $Arg (@_) { + print_verbose("# Examining Arg = $Arg\n"); + + # match w= + if ( $Arg =~ m/w=[\d+][\.]*[\d]*/ ) { + ($ArgType, $w) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $w) in argument list\n"); + } + + # match l= + elsif ( $Arg =~ m/l=[\d+][\.]*[\d]*/ ) { + ($ArgType, $l) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $l) in argument list\n"); + } + + # match g= + elsif ( $Arg =~ m/g=[\d+][\.]*[\d]*/ ) { + ($ArgType, $g) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $g) in argument list\n"); + } + + #match x= + elsif ( $Arg =~ m/x=[\d+][\.]*[\d]*/ ) { + ($ArgType, $x) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $x) in argument list\n"); + } + + #match y= + elsif ( $Arg =~ m/y=[\d+][\.]*[\d]*/ ) { + ($ArgType, $y) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $y) in argument list\n"); + } + + #match description= + elsif ( $Arg =~ m/description=\w/ ) { + ($ArgType, $description) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $description) in argument list\n"); + } + + #match pcb_name= + elsif ( $Arg =~ m/pcb_name=\w/ ) { + ($ArgType, $pcb_name) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $pcb_name) in argument list\n"); + } + + #match value= + elsif ( $Arg =~ m/value=\w/ ) { + ($ArgType, $value) = split(/=/, $Arg); + print_verbose("# Found ($ArgType, $value) in argument list\n"); + } + + #match -v + elsif ( $Arg =~ m/-v/ ) { + break; + } + + #match ---help + elsif ( $Arg =~ m/--help/ ) { + print($UsageString); + exit(0); + } + + #match -h + elsif ( $Arg =~ m/-h/ ) { + print($UsageString); + exit(0); + } + + + # Unknown token on input line. + else { + print("Unknown token on input line. Required parameters are:\n"); + print(" x=<pad width (vertical) in mils>\n"); + print(" y=<pad length (horizontal) in mils>\n"); + print(" g=<pad to pad distance in mils>\n"); + print("Example usage:\n"); + print(" perl smtgen.pl x=30 y=25 g=25\n"); + print("type \"perl smtgen.pl --help\" for more information.\n\n"); + exit(-1) + } + } # foreach + + if ( ($x == -1) || ($y == -1) || ($g == -1) ) { + # We didn't get enough information. Tell user and exit. + printf("You need to specify x, y, and g on the command line. One\n"); + printf("or more of those parameters was missing. Please try again.\n"); + exit(-1); + } + + return + +} + +sub print_verbose() { + if ($VERBOSE == 1) { + print(@_); + } + return +} diff --git a/usrp-hw/sym/SMA-5.sym b/usrp-hw/sym/SMA-5.sym new file mode 100644 index 000000000..d882dffa3 --- /dev/null +++ b/usrp-hw/sym/SMA-5.sym @@ -0,0 +1,48 @@ +v 20030901 +V 150 450 150 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 350 650 5 10 0 0 0 0 +device=SMA5 +V 150 450 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 300 100 0 1 0 1 +{ +T 150 100 5 8 1 1 0 0 +pinnumber=2 +T 150 100 5 8 0 0 0 0 +pinseq=2 +} +L 200 500 185 485 3 0 0 0 -1 -1 +P 200 500 500 500 1 0 1 +{ +T 350 550 5 8 1 1 0 0 +pinnumber=1 +T 350 550 5 8 0 0 0 0 +pinseq=1 +} +L 100 300 104 307 3 0 0 0 -1 -1 +T 0 800 8 10 1 1 0 0 +refdes=J? +T 0 0 8 10 0 1 0 0 +class=IO +T 0 0 8 10 0 1 0 0 +pins=2 +P 100 300 100 0 1 0 1 +{ +T 250 100 5 8 1 1 0 0 +pinnumber=3 +T 150 100 5 8 0 0 0 0 +pinseq=3 +} +P 100 300 100 0 1 0 1 +{ +T 350 100 5 8 1 1 0 0 +pinnumber=4 +T 150 100 5 8 0 0 0 0 +pinseq=4 +} +P 100 300 100 0 1 0 1 +{ +T 450 100 5 8 1 1 0 0 +pinnumber=5 +T 150 100 5 8 0 0 0 0 +pinseq=5 +} diff --git a/usrp-hw/sym/T1-1T.sym b/usrp-hw/sym/T1-1T.sym new file mode 100644 index 000000000..565f70914 --- /dev/null +++ b/usrp-hw/sym/T1-1T.sym @@ -0,0 +1,68 @@ +v 20030901 +T 0 1400 8 10 1 1 0 0 +refdes=T? +A 500 1200 98 270 180 3 0 0 0 -1 -1 +A 500 1000 98 270 180 3 0 0 0 -1 -1 +A 500 800 98 270 180 3 0 0 0 -1 -1 +A 500 600 100 270 180 3 0 0 0 -1 -1 +A 1000 1200 98 90 180 3 0 0 0 -1 -1 +A 500 400 98 270 180 3 0 0 0 -1 -1 +A 500 200 98 270 180 3 0 0 0 -1 -1 +A 1000 1000 98 90 180 3 0 0 0 -1 -1 +A 1000 800 98 90 180 3 0 0 0 -1 -1 +A 1000 600 98 90 180 3 0 0 0 -1 -1 +A 1000 400 98 90 180 3 0 0 0 -1 -1 +A 1000 200 98 90 180 3 0 0 0 -1 -1 +L 500 1300 200 1300 3 0 0 0 -1 -1 +L 500 100 200 100 3 0 0 0 -1 -1 +L 1000 1300 1300 1300 3 0 0 0 -1 -1 +L 1000 100 1300 100 3 0 0 0 -1 -1 +L 700 1400 700 0 3 0 0 0 -1 -1 +L 800 1400 800 0 3 0 0 0 -1 -1 +P 200 1300 0 1300 1 0 1 +{ +T 200 1100 3 10 1 1 0 0 +pinnumber=6 +T 300 1400 5 10 0 0 0 0 +pinseq=6 +} +P 200 100 0 100 1 0 1 +{ +T 200 200 3 10 1 1 0 0 +pinnumber=4 +T 200 0 5 10 0 0 0 0 +pinseq=4 +} +P 1300 1300 1500 1300 1 0 1 +{ +T 1300 1100 3 10 1 1 0 0 +pinnumber=3 +T 1300 1400 5 10 0 0 0 0 +pinseq=3 +} +P 1300 100 1500 100 1 0 1 +{ +T 1300 200 3 10 1 1 0 0 +pinnumber=1 +T 1300 0 5 10 0 0 0 0 +pinseq=1 +} +T 0 1600 8 10 0 0 0 0 +device=T1-1T +L 500 700 200 700 3 0 0 0 -1 -1 +P 200 700 0 700 1 0 1 +{ +T 200 800 3 10 1 1 0 0 +pinnumber=2 +T 200 600 5 10 0 0 0 0 +pinseq=2 +} +P 200 700 0 700 1 0 1 +{ +T 400 800 3 10 1 1 0 0 +pinnumber=5 +T 200 600 5 10 0 0 0 0 +pinseq=5 +} +T 340 797 3 15 1 0 0 0 +, diff --git a/usrp-hw/sym/generated/ad813x.src b/usrp-hw/sym/generated/ad813x.src new file mode 100644 index 000000000..037dbf543 --- /dev/null +++ b/usrp-hw/sym/generated/ad813x.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD813X +device=AD813X +refdes=U? +footprint=SO8 +description=Differential Amplifier +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +8 in line l +IN +2 in line l VOCM +1 in line l -IN +3 pwr line t V+ +5 out line r -OUT +7 in line r NC +4 out line r +OUT +6 pwr line b V- diff --git a/usrp-hw/sym/generated/ad8347-BIAS.src b/usrp-hw/sym/generated/ad8347-BIAS.src new file mode 100644 index 000000000..060ba6de1 --- /dev/null +++ b/usrp-hw/sym/generated/ad8347-BIAS.src @@ -0,0 +1,56 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8347-BIAS +device=AD8347 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .8-2.7GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 2 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +5 in line l VCMO +13 in line l IOFS +16 in line l QOFS +14 out line r VREF +15 in line l ENBL diff --git a/usrp-hw/sym/generated/ad8347-MIX.src b/usrp-hw/sym/generated/ad8347-MIX.src new file mode 100644 index 000000000..9416dbd8d --- /dev/null +++ b/usrp-hw/sym/generated/ad8347-MIX.src @@ -0,0 +1,61 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8347-MIX +device=AD8347 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .8-2.7GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 3 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +28 in line l LOIP +1 in line l _LOIN_ +20 in line r VDT1 +8 out line r IMXO +22 out line r QMXO +18 in line r VDT2 +11 in line l RFIP +10 in line l _RFIN_ +17 in line l VGIN +19 out line l VAGC diff --git a/usrp-hw/sym/generated/ad8347-OUT.src b/usrp-hw/sym/generated/ad8347-OUT.src new file mode 100644 index 000000000..115ce5ed7 --- /dev/null +++ b/usrp-hw/sym/generated/ad8347-OUT.src @@ -0,0 +1,57 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8347-OUT +device=AD8347 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .8-2.7GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 4 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 out line r IOPP +3 out line r _IOPN_ +25 out line r QOPP +26 out line r _QOPN_ +6 in line l IAIN +24 in line l QAIN diff --git a/usrp-hw/sym/generated/ad8347-PWR.src b/usrp-hw/sym/generated/ad8347-PWR.src new file mode 100644 index 000000000..40bbab6d9 --- /dev/null +++ b/usrp-hw/sym/generated/ad8347-PWR.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8347-PWR +device=AD8347 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .8-2.7GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 1 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 pwr line l VPOS1 +12 pwr line l VPOS2 +21 pwr line l VPOS3 +27 pwr line r COM1 +9 pwr line r COM2 +7 pwr line r COM3 +23 pwr line r COM3 diff --git a/usrp-hw/sym/generated/ad8348-BIAS.src b/usrp-hw/sym/generated/ad8348-BIAS.src new file mode 100644 index 000000000..600db4cdd --- /dev/null +++ b/usrp-hw/sym/generated/ad8348-BIAS.src @@ -0,0 +1,57 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8348-BIAS +device=AD8348 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .05-1GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 2 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +5 in line l VCMO +13 in line l IOFS +16 in line l QOFS +14 out line r VREF +15 in line l ENBL +24 in line l ENVG diff --git a/usrp-hw/sym/generated/ad8348-MIX.src b/usrp-hw/sym/generated/ad8348-MIX.src new file mode 100644 index 000000000..61be60bc0 --- /dev/null +++ b/usrp-hw/sym/generated/ad8348-MIX.src @@ -0,0 +1,60 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8348-MIX +device=AD8348 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .05-1GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 3 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l LOIP +28 in line l _LOIN_ +8 out line r IMXO +21 out line r QMXO +11 in line l IFIP +10 in line l _IFIN_ +18 in line l MXIP +19 in line l _MXIN_ +17 in line l VGIN diff --git a/usrp-hw/sym/generated/ad8348-OUT.src b/usrp-hw/sym/generated/ad8348-OUT.src new file mode 100644 index 000000000..b9c5ad308 --- /dev/null +++ b/usrp-hw/sym/generated/ad8348-OUT.src @@ -0,0 +1,57 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8348-OUT +device=AD8348 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .05-1GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 4 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 out line r IOPP +3 out line r _IOPN_ +25 out line r QOPP +26 out line r _QOPN_ +6 in line l IAIN +23 in line l QAIN diff --git a/usrp-hw/sym/generated/ad8348-PWR.src b/usrp-hw/sym/generated/ad8348-PWR.src new file mode 100644 index 000000000..36ec8241b --- /dev/null +++ b/usrp-hw/sym/generated/ad8348-PWR.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD8348-PWR +device=AD8348 +refdes=U? +footprint=TSSOP28/0.65 +description=Analog Devices .05-1GHz Quadrature Demodulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=Part 1 of 4 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 pwr line l VPOS1 +12 pwr line l VPOS2 +20 pwr line l VPOS3 +27 pwr line r COM1 +9 pwr line r COM2 +7 pwr line r COM3 +22 pwr line r COM3 diff --git a/usrp-hw/sym/generated/ad834X-MIX.src b/usrp-hw/sym/generated/ad834X-MIX.src new file mode 100644 index 000000000..1a798ce81 --- /dev/null +++ b/usrp-hw/sym/generated/ad834X-MIX.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD834X-MIX +device=AD834X +refdes=U? +footprint=TSSOP16-65-PAD +description=Analog Devices Quadrature Modulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=AD8345, AD8346, and AD8349 are pin-compatible +comment=Part 2 of 2 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l IBBP +2 in line l _IBBN_ +16 in line l QBBP +15 in line l _QBBN_ +11 out line r VOUT +6 in line l LOIP +5 in line l _LOIN_ diff --git a/usrp-hw/sym/generated/ad834X-PWR.src b/usrp-hw/sym/generated/ad834X-PWR.src new file mode 100644 index 000000000..f9ea47f7d --- /dev/null +++ b/usrp-hw/sym/generated/ad834X-PWR.src @@ -0,0 +1,60 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD834X-PWR +device=AD834X +refdes=U? +footprint=TSSOP16-65-PAD +description=Analog Devices Quadrature Modulator +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=AD8345, AD8346, and AD8349 are pin-compatible +comment=Part 1 of 2 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 pwr line r COM1 +10 pwr line r COM2 +3 pwr line r COM3 +9 pwr line r COM3 +13 pwr line r COM3 +14 pwr line r COM3 +7 pwr line l VPS1 +12 pwr line l VPS2 +8 in line l ENBL diff --git a/usrp-hw/sym/generated/ad9238-A.src b/usrp-hw/sym/generated/ad9238-A.src new file mode 100644 index 000000000..81d605fef --- /dev/null +++ b/usrp-hw/sym/generated/ad9238-A.src @@ -0,0 +1,70 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9238-A +device=AD9238 +refdes=U? +footprint=LQFP64 +description=Analog Devices 12-bit 60 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 in line l VIN+\_A +3 in line l _VIN-\_A_ +44 out line r D0\_A +45 out line r D1\_A +46 out line r D2\_A +47 out line r D3\_A +48 out line r D4\_A +49 out line r D5\_A +50 out line r D6\_A +51 out line r D7\_A +54 out line r D8\_A +55 out line r D9\_A +56 out line r D10\_A +57 out line r D11\_A +58 out line r OTR\_A +59 in dot l _OEB\_A_ +60 in line l PDWN\_A +63 clk clk l CLK\_A + diff --git a/usrp-hw/sym/generated/ad9238-B.src b/usrp-hw/sym/generated/ad9238-B.src new file mode 100644 index 000000000..161d0b101 --- /dev/null +++ b/usrp-hw/sym/generated/ad9238-B.src @@ -0,0 +1,70 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9238-B +device=AD9238 +refdes=U? +footprint=LQFP64 +description=Analog Devices 12-bit 60 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 4 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +14 in line l _VIN-\_B_ +15 in line l VIN+\_B +18 clk clk l CLK\_B +21 in line l PDWN\_B +22 in dot l _OEB\_B_ +25 out line r D0\_B +26 out line r D1\_B +27 out line r D2\_B +30 out line r D3\_B +31 out line r D4\_B +32 out line r D5\_B +33 out line r D6\_B +34 out line r D7\_B +35 out line r D8\_B +36 out line r D9\_B +37 out line r D10\_B +38 out line r D11\_B +39 out line r OTR\_B + diff --git a/usrp-hw/sym/generated/ad9238-CTRL.src b/usrp-hw/sym/generated/ad9238-CTRL.src new file mode 100644 index 000000000..5f5093d8a --- /dev/null +++ b/usrp-hw/sym/generated/ad9238-CTRL.src @@ -0,0 +1,67 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9238-CTRL +device=AD9238 +refdes=U? +footprint=LQFP64 +description=Analog Devices 12-bit 60 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +19 in line l DCS +20 in line l DFS +61 in line l MUX\_SELECT +62 in line l SHARED\_REF +23 tp line l NC1 +24 tp line l NC2 +42 tp line l NC3 +43 tp line l NC4 +8 in line r VREF +9 in line r SENSE +6 in line r REFT\_A +11 in line r REFT\_B +7 in line r REFB\_A +10 in line r REFB\_B + + diff --git a/usrp-hw/sym/generated/ad9238-PWR.src b/usrp-hw/sym/generated/ad9238-PWR.src new file mode 100644 index 000000000..bb57908d4 --- /dev/null +++ b/usrp-hw/sym/generated/ad9238-PWR.src @@ -0,0 +1,66 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9238-PWR +device=AD9238 +refdes=U? +footprint=LQFP64 +description=Analog Devices 12-bit 60 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line r AGND1 +4 pwr line r AGND2 +5 pwr line l AVDD1 +12 pwr line l AVDD2 +13 pwr line r AGND3 +16 pwr line r AGND4 +17 pwr line l AVDD3 +28 pwr line r DGND1 +29 pwr line l DVDD1 +40 pwr line r DGND2 +41 pwr line l DVDD2 +52 pwr line l DVDD3 +53 pwr line r DGND3 +64 pwr line l AVDD4 + diff --git a/usrp-hw/sym/generated/ad9510-CTRL.src b/usrp-hw/sym/generated/ad9510-CTRL.src new file mode 100644 index 000000000..fdac25f0b --- /dev/null +++ b/usrp-hw/sym/generated/ad9510-CTRL.src @@ -0,0 +1,57 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9510-CTRL +device=AD9510 +refdes=U? +footprint=LFCSP64 +description=Clock Divider and PLL +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=AD9510 +comment=Part 2 of 5 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +16 in line l FUNCTION +17 out line l STATUS +18 in line l SCLK +19 io line l SDIO +20 out line l SDO +21 in line l CSB diff --git a/usrp-hw/sym/generated/ad9510-OUTA.src b/usrp-hw/sym/generated/ad9510-OUTA.src new file mode 100644 index 000000000..25c5ea5f8 --- /dev/null +++ b/usrp-hw/sym/generated/ad9510-OUTA.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9510-OUTA +device=AD9510 +refdes=U? +footprint=LFCSP64 +description=Clock Divider and PLL +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=AD9510 +comment=Part 4 of 5 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +58 out line r OUT0\_P +57 out dot r _OUT0\_N_ +54 out line r OUT1\_P +53 out dot r _OUT1\_N_ +35 out line r OUT2\_P +34 out dot r _OUT2\_N_ +29 out line r OUT3\_P +28 out dot r _OUT3\_N_ diff --git a/usrp-hw/sym/generated/ad9510-OUTB.src b/usrp-hw/sym/generated/ad9510-OUTB.src new file mode 100644 index 000000000..f4bd03ca0 --- /dev/null +++ b/usrp-hw/sym/generated/ad9510-OUTB.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9510-OUTA +device=AD9510 +refdes=U? +footprint=LFCSP64 +description=Clock Divider and PLL +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=AD9510 +comment=Part 5 of 5 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +47 out line r OUT4\_P +46 out dot r _OUT4\_N_ +43 out line r OUT5\_P +42 out dot r _OUT5\_N_ +39 out line r OUT6\_P +38 out dot r _OUT6\_N_ +25 out line r OUT7\_P +24 out dot r _OUT7\_N_ diff --git a/usrp-hw/sym/generated/ad9510-PLL.src b/usrp-hw/sym/generated/ad9510-PLL.src new file mode 100644 index 000000000..715831981 --- /dev/null +++ b/usrp-hw/sym/generated/ad9510-PLL.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9510-PLL +device=AD9510 +refdes=U? +footprint=LFCSP64 +description=Clock Divider and PLL +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=AD9510 +comment=Part 3 of 5 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 clk clk l REFIN\_P +2 clk dotclk l _REFIN\_N_ +14 clk clk l CLK1\_P +15 clk dotclk l _CLK1\_N_ +10 clk clk l CLK2\_P +11 clk dotclk l _CLK2\_N_ +6 out line r CP diff --git a/usrp-hw/sym/generated/ad9510-PWR.src b/usrp-hw/sym/generated/ad9510-PWR.src new file mode 100644 index 000000000..5cfe60509 --- /dev/null +++ b/usrp-hw/sym/generated/ad9510-PWR.src @@ -0,0 +1,87 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9510-PWR +device=AD9510 +refdes=U? +footprint=LFCSP64 +description=Clock Divider and PLL +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=AD9510 +comment=Part 1 of 5 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 pwr line l VS +9 pwr line l VS +13 pwr line l VS +23 pwr line l VS +26 pwr line l VS +30 pwr line l VS +31 pwr line l VS +33 pwr line l VS +36 pwr line l VS +37 pwr line l VS +40 pwr line l VS +41 pwr line l VS +44 pwr line l VS +45 pwr line l VS +48 pwr line l VS +51 pwr line l VS +52 pwr line l VS +56 pwr line l VS +59 pwr line l VS +60 pwr line l VS +64 pwr line l VS +5 pwr line l Vcp +3 pwr line r GND +7 pwr line r GND +8 pwr line r GND +12 pwr line r GND +22 pwr line r GND +27 pwr line r GND +32 pwr line r GND +49 pwr line r GND +50 pwr line r GND +55 pwr line r GND +62 pwr line r GND +65 pwr line r GND\_EP +61 in line b RSET +63 in line b CPRSET diff --git a/usrp-hw/sym/generated/ad9513-CLK.src b/usrp-hw/sym/generated/ad9513-CLK.src new file mode 100644 index 000000000..8fa2998da --- /dev/null +++ b/usrp-hw/sym/generated/ad9513-CLK.src @@ -0,0 +1,60 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9513-CLK +device=AD9513 +refdes=U? +footprint=LFCSP32 +description=Clock Divider +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=ADF4360 +comment=Part 2 of 3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 clk clk l CLK +3 clk dotclk l _CLKB_ +5 in line b SYNCB +28 out line r OUT0 +27 out dot r _OUT0B_ +23 out line r OUT1 +22 out dot r _OUT1B_ +19 out line r OUT2 +18 out dot r _OUT2B_ diff --git a/usrp-hw/sym/generated/ad9513-CTRL.src b/usrp-hw/sym/generated/ad9513-CTRL.src new file mode 100644 index 000000000..50602a30d --- /dev/null +++ b/usrp-hw/sym/generated/ad9513-CTRL.src @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9513-CTRL +device=AD9513 +refdes=U? +footprint=LFCSP32 +description=Clock Divider +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=ADF4360 +comment=Part 3 of 3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +6 pwr line l VREF +7 in line r S10 +8 in line r S9 +9 in line r S8 +10 in line r S7 +11 in line r S6 +12 in line r S5 +13 in line r S4 +14 in line r S3 +15 in line r S2 +16 in line r S1 +25 in line r S0 diff --git a/usrp-hw/sym/generated/ad9513-PWR.src b/usrp-hw/sym/generated/ad9513-PWR.src new file mode 100644 index 000000000..012142373 --- /dev/null +++ b/usrp-hw/sym/generated/ad9513-PWR.src @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9513-PWR +device=AD9513 +refdes=U? +footprint=LFCSP32 +description=Clock Divider +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=ADF4360 +comment=Part 1 of 3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line l VS +4 pwr line l VS +17 pwr line l VS +20 pwr line l VS +21 pwr line l VS +24 pwr line l VS +26 pwr line l VS +29 pwr line l VS +30 pwr line l VS +31 pwr line r GND +33 pwr line r GND\_EP +32 in line b RSET diff --git a/usrp-hw/sym/generated/ad9767-CH1.src b/usrp-hw/sym/generated/ad9767-CH1.src new file mode 100644 index 000000000..42ecaa7b3 --- /dev/null +++ b/usrp-hw/sym/generated/ad9767-CH1.src @@ -0,0 +1,70 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9767-CH1 +device=AD9767 +refdes=U? +footprint=LQFP48 +description=125 MS/s 14-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l DB13\_P1 +2 in line l DB12\_P1 +3 in line l DB11\_P1 +4 in line l DB10\_P1 +5 in line l DB9\_P1 +6 in line l DB8\_P1 +7 in line l DB7\_P1 +8 in line l DB6\_P1 +9 in line l DB5\_P1 +10 in line l DB4\_P1 +11 in line l DB3\_P1 +12 in line l DB2\_P1 +13 in line l DB1\_P1 +14 in line l DB0\_P1 +17 clk line r WRT1 +18 clk line r CLK1 +45 out line r IOUT\_B1 +46 out line r IOUT\_A1 + diff --git a/usrp-hw/sym/generated/ad9767-CH2.src b/usrp-hw/sym/generated/ad9767-CH2.src new file mode 100644 index 000000000..af4c677a8 --- /dev/null +++ b/usrp-hw/sym/generated/ad9767-CH2.src @@ -0,0 +1,69 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9767-CH2 +device=AD9767 +refdes=U? +footprint=LQFP48 +description=125 MS/s 14-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 4 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +23 in line l DB13\_P2 +24 in line l DB12\_P2 +25 in line l DB11\_P2 +26 in line l DB10\_P2 +27 in line l DB9\_P2 +28 in line l DB8\_P2 +29 in line l DB7\_P2 +30 in line l DB6\_P2 +31 in line l DB5\_P2 +32 in line l DB4\_P2 +33 in line l DB3\_P2 +34 in line l DB2\_P2 +35 in line l DB1\_P2 +36 in line l DB0\_P2 +20 clk line r WRT2 +19 clk line r CLK2 +40 out line r IOUT\_B2 +39 out line r IOUT\_A2 diff --git a/usrp-hw/sym/generated/ad9767-CTRL.src b/usrp-hw/sym/generated/ad9767-CTRL.src new file mode 100644 index 000000000..c2dfe9412 --- /dev/null +++ b/usrp-hw/sym/generated/ad9767-CTRL.src @@ -0,0 +1,57 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9767-CTRL +device=AD9767 +refdes=U? +footprint=LQFP48 +description=125 MS/s 14-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +37 in line l SLEEP +41 in line r FSADJ2 +42 in line l GAINCTRL +43 in line r REFIO +44 in line r FSADJ1 +48 in line l MODE diff --git a/usrp-hw/sym/generated/ad9767-PWR.src b/usrp-hw/sym/generated/ad9767-PWR.src new file mode 100644 index 000000000..805dc3043 --- /dev/null +++ b/usrp-hw/sym/generated/ad9767-PWR.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9767-PWR +device=AD9767 +refdes=U? +footprint=LQFP48 +description=125 MS/s 14-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +15 pwr line r DCOM1 +16 pwr line l DVDD1 +21 pwr line r DCOM2 +22 pwr line l DVDD2 +38 pwr line r ACOM +47 pwr line l AVDD + diff --git a/usrp-hw/sym/generated/ad9777-CH1.src b/usrp-hw/sym/generated/ad9777-CH1.src new file mode 100644 index 000000000..9f0e7b3f1 --- /dev/null +++ b/usrp-hw/sym/generated/ad9777-CH1.src @@ -0,0 +1,70 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9777-CH1 +device=AD9777 +refdes=U? +footprint=TQFP80 +description=400 MS/s 16-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +11 in line l DB15\_P1 +12 in line l DB14\_P1 +13 in line l DB13\_P1 +14 in line l DB12\_P1 +15 in line l DB11\_P1 +16 in line l DB10\_P1 +19 in line l DB9\_P1 +20 in line l DB8\_P1 +21 in line l DB7\_P1 +22 in line l DB6\_P1 +23 in line l DB5\_P1 +24 in line l DB4\_P1 +27 in line l DB3\_P1 +28 in line l DB2\_P1 +29 in line l DB1\_P1 +30 in line l DB0\_P1 +73 out line r IOUT1\_P +72 out line r _IOUT1\_N_ + diff --git a/usrp-hw/sym/generated/ad9777-CH2.src b/usrp-hw/sym/generated/ad9777-CH2.src new file mode 100644 index 000000000..686a5ddc6 --- /dev/null +++ b/usrp-hw/sym/generated/ad9777-CH2.src @@ -0,0 +1,69 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9777-CH2 +device=AD9777 +refdes=U? +footprint=TQFP80 +description=400 MS/s 16-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 4 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +31 in line l DB15\_P2/IQSEL +32 in line l DB14\_P2/ONEPORTCLK +33 in line l DB13\_P2 +34 in line l DB12\_P2 +37 in line l DB11\_P2 +38 in line l DB10\_P2 +39 in line l DB9\_P2 +40 in line l DB8\_P2 +41 in line l DB7\_P2 +42 in line l DB6\_P2 +45 in line l DB5\_P2 +46 in line l DB4\_P2 +47 in line l DB3\_P2 +48 in line l DB2\_P2 +49 in line l DB1\_P2 +50 in line l DB0\_P2 +69 out line r IOUT2\_P +68 out line r _IOUT2\_N_ diff --git a/usrp-hw/sym/generated/ad9777-CTRL.src b/usrp-hw/sym/generated/ad9777-CTRL.src new file mode 100644 index 000000000..d92b05cf5 --- /dev/null +++ b/usrp-hw/sym/generated/ad9777-CTRL.src @@ -0,0 +1,65 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9777-CTRL +device=AD9777 +refdes=U? +footprint=TQFP80 +description=400 MS/s 16-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +5 clk clk l CLK\_P +6 clk dotclk l _CLK\_N_ +2 in line r LPF +8 out line r DATACLK/PLL\_LOCK + +60 in line r FSADJ1 +59 in line r FSADJ2 +58 in line r REFIO +57 in line l RESET + +53 in line l SDO +54 in line l SDIO +55 in line l SCLK +56 in line l CSB diff --git a/usrp-hw/sym/generated/ad9777-PWR.src b/usrp-hw/sym/generated/ad9777-PWR.src new file mode 100644 index 000000000..f5080daef --- /dev/null +++ b/usrp-hw/sym/generated/ad9777-PWR.src @@ -0,0 +1,83 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD9777-PWR +device=AD9777 +refdes=U? +footprint=TQFP80 +description=400 MS/s 16-bit DAC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line l CLKVDD +3 pwr line l CLKVDD +4 pwr line r CLKGND +7 pwr line r CLKGND +9 pwr line r DGND +17 pwr line r DGND +25 pwr line r DGND +35 pwr line r DGND +44 pwr line r DGND +52 pwr line r DGND +10 pwr line l DVDD +18 pwr line l DVDD +26 pwr line l DVDD +36 pwr line l DVDD +43 pwr line l DVDD +51 pwr line l DVDD +61 pwr line l AVDD +63 pwr line l AVDD +65 pwr line l AVDD +76 pwr line l AVDD +78 pwr line l AVDD +80 pwr line l AVDD +62 pwr line r AGND +64 pwr line r AGND +66 pwr line r AGND +67 pwr line r AGND +70 pwr line r AGND +71 pwr line r AGND +74 pwr line r AGND +75 pwr line r AGND +77 pwr line r AGND +79 pwr line r AGND diff --git a/usrp-hw/sym/generated/ad986X-ACTRL.src b/usrp-hw/sym/generated/ad986X-ACTRL.src new file mode 100644 index 000000000..5c56cfe64 --- /dev/null +++ b/usrp-hw/sym/generated/ad986X-ACTRL.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD986X-ACTRL +device=AD986X +refdes=U? +footprint=LQFP128 +description=MxFE +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 5 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +21 io line l REFIO +22 out line l FSADJ +101 pwr line r REFT\_B +102 pwr line r REFB\_B +121 pwr line r REFT\_A +120 pwr line r REFB\_A +111 pwr line r VREF diff --git a/usrp-hw/sym/generated/ad986X-AUX.src b/usrp-hw/sym/generated/ad986X-AUX.src new file mode 100644 index 000000000..3bd6024f4 --- /dev/null +++ b/usrp-hw/sym/generated/ad986X-AUX.src @@ -0,0 +1,60 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2200 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD986X-AUX +device=AD986X +refdes=U? +footprint=LQFP128 +description=MxFE +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 6 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l AUX\_ADC\_A1 +128 in line l AUX\_ADC\_A2 +126 in line l AUX\_ADC\_B1 +125 in line l AUX\_ADC\_B2 +127 io line l AUX\_ADC\_REF +5 out line r SIGDELT +6 out line r AUX\_DAC\_A +7 out line r AUX\_DAC\_B +8 out line r AUX\_DAC\_C diff --git a/usrp-hw/sym/generated/ad986X-CLK.src b/usrp-hw/sym/generated/ad986X-CLK.src new file mode 100644 index 000000000..0e1a9adac --- /dev/null +++ b/usrp-hw/sym/generated/ad986X-CLK.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD986X-CLK +device=AD986X +refdes=U? +footprint=LQFP128 +description=MxFE +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 7 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +10 out line r DLL\_Lock +14 in line l OSC1 +15 out line l OSC2 +17 in line l CLKSEL +64 out line r CLKOUT2 +65 out line r CLKOUT1 +12 out line l NC diff --git a/usrp-hw/sym/generated/ad986X-CTRL.src b/usrp-hw/sym/generated/ad986X-CTRL.src new file mode 100644 index 000000000..179ff2447 --- /dev/null +++ b/usrp-hw/sym/generated/ad986X-CTRL.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD986X-CTRL +device=AD986X +refdes=U? +footprint=LQFP128 +description=MxFE +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 4 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +54 clk clk l SCLK +55 out line l SDO +56 io line l SDIO +57 in dot l _SEN_ +63 in line l RESETB +95 out line l AUX\_SPI\_do +96 clk clk l AUX\_SPI\_clk +97 in line l AUX\_SPI\_csb diff --git a/usrp-hw/sym/generated/ad986X-PWR.src b/usrp-hw/sym/generated/ad986X-PWR.src new file mode 100644 index 000000000..6493262dc --- /dev/null +++ b/usrp-hw/sym/generated/ad986X-PWR.src @@ -0,0 +1,99 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD986X-PWR +device=AD986X +refdes=U? +footprint=LQFP128 +description=MxFE +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +98 pwr line l AVDD +99 pwr line l AVDD +104 pwr line l AVDD +105 pwr line l AVDD +117 pwr line l AVDD +118 pwr line l AVDD +123 pwr line l AVDD +124 pwr line l AVDD +18 pwr line l AVDD +20 pwr line l AVDD +23 pwr line l AVDD +32 pwr line l AVDD +13 pwr line l AVDD +3 pwr line l AVDD +4 pwr line l AVDD +33 pwr line l DVDD +36 pwr line l DVDD +53 pwr line l DVDD +59 pwr line l DVDD +61 pwr line l DVDD +66 pwr line l DVDD +93 pwr line l DVDD +100 pwr line r AGND +103 pwr line r AGND +106 pwr line r AGND +109 pwr line r AGND +110 pwr line r AGND +112 pwr line r AGND +113 pwr line r AGND +116 pwr line r AGND +119 pwr line r AGND +122 pwr line r AGND +19 pwr line r AGND +24 pwr line r AGND +27 pwr line r AGND +28 pwr line r AGND +31 pwr line r AGND +11 pwr line r AGND +16 pwr line r AGND +2 pwr line r AGND +9 pwr line r AGND +34 pwr line r DGND +35 pwr line r DGND +52 pwr line r DGND +58 pwr line r DGND +60 pwr line r DGND +67 pwr line r DGND +94 pwr line r DGND diff --git a/usrp-hw/sym/generated/ad986X-RX.src b/usrp-hw/sym/generated/ad986X-RX.src new file mode 100644 index 000000000..dd4eb1788 --- /dev/null +++ b/usrp-hw/sym/generated/ad986X-RX.src @@ -0,0 +1,80 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD986X-RX +device=AD986X +refdes=U? +footprint=LQFP128 +description=MxFE +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +107 in line l VINB +108 in line l _VINB_ +114 in line l _VINA_ +115 in line l VINA +92 out line r RXSYNC +68 out line r DA0 +69 out line r DA1 +70 out line r DA2 +71 out line r DA3 +72 out line r DA4 +73 out line r DA5 +74 out line r DA6 +75 out line r DA7 +76 out line r DA8 +77 out line r DA9 +78 out line r DA10 +79 out line r DA11 +80 out line r DB0 +81 out line r DB1 +82 out line r DB2 +83 out line r DB3 +84 out line r DB4 +85 out line r DB5 +86 out line r DB6 +87 out line r DB7 +88 out line r DB8 +89 out line r DB9 +90 out line r DB10 +91 out line r DB11 diff --git a/usrp-hw/sym/generated/ad986X-TX.src b/usrp-hw/sym/generated/ad986X-TX.src new file mode 100644 index 000000000..94bff1fa5 --- /dev/null +++ b/usrp-hw/sym/generated/ad986X-TX.src @@ -0,0 +1,71 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=AD986X-TX +device=AD986X +refdes=U? +footprint=LQFP128 +description=MxFE +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +25 out line r _IOUTA_ +26 out line r IOUTA +30 out line r _IOUTB_ +29 out line r IOUTB +62 in line l MODE\\TXBLANK +51 in line l TXSYNC +50 in line l TX0 +49 in line l TX1 +48 in line l TX2 +47 in line l TX3 +46 in line l TX4 +45 in line l TX5 +44 in line l TX6 +43 in line l TX7 +42 in line l TX8 +41 in line l TX9 +40 in line l TX10 +39 in line l TX11 +38 in line l TX12 +37 in line l TX13 diff --git a/usrp-hw/sym/generated/adf4360-ANLG.src b/usrp-hw/sym/generated/adf4360-ANLG.src new file mode 100644 index 000000000..17cbbaa66 --- /dev/null +++ b/usrp-hw/sym/generated/adf4360-ANLG.src @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=ADF4360-ANLG +device=ADF4360 +refdes=U? +footprint=CP-24 +description=Family of VCO/PLL Combo chips +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=ADF4360-1 through -7 +comment=Part 3 of 3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 out line r RFOUTA +5 out line r _RFOUTB_ +9 io line r L1/AGND +10 io line r L2/AGND +24 out line r CP +16 in line l REFin +14 io line l Cn +13 out line l Rset +12 io line l Cc +7 in line l Vtune + + diff --git a/usrp-hw/sym/generated/adf4360-DIG.src b/usrp-hw/sym/generated/adf4360-DIG.src new file mode 100644 index 000000000..001a86fd2 --- /dev/null +++ b/usrp-hw/sym/generated/adf4360-DIG.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=ADF4360-DIG +device=ADF4360 +refdes=U? +footprint=CP-24 +description=Family of VCO/PLL Combo chips +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=ADF4360-1 through -7 +comment=Part 2 of 3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +17 clk line l CLK +18 in line l DATA +19 in line l LE +20 out line r MUXOUT +23 in line l CE + + diff --git a/usrp-hw/sym/generated/adf4360-PWR.src b/usrp-hw/sym/generated/adf4360-PWR.src new file mode 100644 index 000000000..f2a1d3551 --- /dev/null +++ b/usrp-hw/sym/generated/adf4360-PWR.src @@ -0,0 +1,62 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=ADF4360-PWR +device=ADF4360 +refdes=U? +footprint=CP-24 +description=Family of VCO and PLL Combo chips +documentation=http://www.analog.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=ADF4360-1 through -7 +comment=Part 1 of 3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line r CP\_GND +2 pwr line l AVdd +3 pwr line r AGND +6 pwr line l Vvco +8 pwr line r AGND +11 pwr line r AGND +15 pwr line r DGND +21 pwr line l DVdd +22 pwr line r AGND + + diff --git a/usrp-hw/sym/generated/adp3336.src b/usrp-hw/sym/generated/adp3336.src new file mode 100644 index 000000000..6f9a0897c --- /dev/null +++ b/usrp-hw/sym/generated/adp3336.src @@ -0,0 +1,61 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=ADP3336 +device=ADP3336 +refdes=U? +footprint=MSOP8 +description=Analog Devices Adjustable LDO +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Needs a pad in the middle for thermal +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +7 pwr line l In +8 pwr line l In +6 in line l _SD_ + +1 pwr line r Out +2 pwr line r Out +3 pwr line r Out +5 in line r FB + +4 pwr line l GND diff --git a/usrp-hw/sym/generated/bs2s7hz1204.src b/usrp-hw/sym/generated/bs2s7hz1204.src new file mode 100644 index 000000000..c94d3f07b --- /dev/null +++ b/usrp-hw/sym/generated/bs2s7hz1204.src @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=BS2S7HZ1204 +device=BS2S7HZ1204 +refdes=U? +footprint=BS2S7HZ1204 +description=Sharp Microelectronics DBS Tuner +documentation=http://www.sharpsma.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment=NC pins -- 1,3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 pwr line l VLNB +11 pwr line l 5V +9 pwr line l 3.3V +10 pwr line l VTUN +6 in line l AGC +7 out line r IOUT +8 out line r QOUT +13 io line l SCL +14 io line l SDA +3 in line r NC +5 in line r NC +12 in line r NC diff --git a/usrp-hw/sym/generated/cy7c68013-tq100-BUS.src b/usrp-hw/sym/generated/cy7c68013-tq100-BUS.src new file mode 100644 index 000000000..bd892a702 --- /dev/null +++ b/usrp-hw/sym/generated/cy7c68013-tq100-BUS.src @@ -0,0 +1,81 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY7C68013-TQ100-BUS +device=CY7C68013-TQ100 +refdes=U? +footprint=TQFP100 +description=Cypress FX2 USB2 Interface +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +54 out line r CTL0 +55 out line r CTL1 +56 out line r CTL2 +51 out line r CTL3 +52 out line r CTL4 +76 out line r CTL5 +3 in line r RDY0 +4 in line r RDY1 +5 in line r RDY2 +6 in line r RDY3 +7 in line r RDY4 +8 in line r RDY5 +26 clk clk l IFCLK +34 io line r FD0 +35 io line r FD1 +36 io line r FD2 +37 io line r FD3 +44 io line r FD4 +45 io line r FD5 +46 io line r FD6 +47 io line r FD7 +80 io line r FD8 +81 io line r FD9 +82 io line r FD10 +83 io line r FD11 +95 io line r FD12 +96 io line r FD13 +97 io line r FD14 +98 io line r FD15 + diff --git a/usrp-hw/sym/generated/cy7c68013-tq100-CTRL.src b/usrp-hw/sym/generated/cy7c68013-tq100-CTRL.src new file mode 100644 index 000000000..c4c63d5a1 --- /dev/null +++ b/usrp-hw/sym/generated/cy7c68013-tq100-CTRL.src @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY7C68013-TQ100-CTRL +device=CY7C68013-TQ100 +refdes=U? +footprint=TQFP100 +description=Cypress FX2 USB2 Interface +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +10 out line l XTALOUT +11 in line l XTALIN +17 io line l D+ +18 io dot l D- +27 in line r RESERVED +28 out line r BKPT +31 out dot r _RD_ +32 out dot r _WR_ +77 in dot r _RESET_ +79 in dot r _WAKEUP_ +100 out line l CLKOUT + diff --git a/usrp-hw/sym/generated/cy7c68013-tq100-MISC.src b/usrp-hw/sym/generated/cy7c68013-tq100-MISC.src new file mode 100644 index 000000000..fbd69d7a4 --- /dev/null +++ b/usrp-hw/sym/generated/cy7c68013-tq100-MISC.src @@ -0,0 +1,65 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY7C68013-TQ100-MISC +device=CY7C68013-TQ100 +refdes=U? +footprint=TQFP100 +description=Cypress FX2 USB2 Interface +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 7 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +13 tp line l NC +14 tp line l NC +15 tp line l NC +22 in line l INT4 +84 in dot l _INT5_ +23 in line l T0 +24 in line l T1 +25 in line l T2 +29 io line r SCL +30 io line r SDA +40 out line r TxD0 +41 in line r RxD0 +42 out line r TxD1 +43 in line r RxD1 diff --git a/usrp-hw/sym/generated/cy7c68013-tq100-PA.src b/usrp-hw/sym/generated/cy7c68013-tq100-PA.src new file mode 100644 index 000000000..0fdbf69ec --- /dev/null +++ b/usrp-hw/sym/generated/cy7c68013-tq100-PA.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY7C68013-TQ100-PA +device=CY7C68013-TQ100 +refdes=U? +footprint=TQFP100 +description=Cypress FX2 USB2 Interface +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 4 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +67 io line r PA0 +68 io line r PA1 +69 io line r PA2 +70 io line r PA3 +71 io line r PA4 +72 io line r PA5 +73 io line r PA6 +74 io line r PA7 diff --git a/usrp-hw/sym/generated/cy7c68013-tq100-PC.src b/usrp-hw/sym/generated/cy7c68013-tq100-PC.src new file mode 100644 index 000000000..fa16d5c1f --- /dev/null +++ b/usrp-hw/sym/generated/cy7c68013-tq100-PC.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY7C68013-TQ100-PC +device=CY7C68013-TQ100 +refdes=U? +footprint=TQFP100 +description=Cypress FX2 USB2 Interface +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 5 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +57 io line r PC0 +58 io line r PC1 +59 io line r PC2 +60 io line r PC3 +61 io line r PC4 +62 io line r PC5 +63 io line r PC6 +64 io line r PC7 diff --git a/usrp-hw/sym/generated/cy7c68013-tq100-PE.src b/usrp-hw/sym/generated/cy7c68013-tq100-PE.src new file mode 100644 index 000000000..aca4ca63a --- /dev/null +++ b/usrp-hw/sym/generated/cy7c68013-tq100-PE.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY7C68013-TQ100-PE +device=CY7C68013-TQ100 +refdes=U? +footprint=TQFP100 +description=Cypress FX2 USB2 Interface +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 6 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +86 io line r PE0/T0OUT +87 io line r PE1/T1OUT +88 io line r PE2/T2OUT +89 io line r PE3/RXD0OUT +90 io line r PE4/RXD1OUT +91 io line r PE5/INT6 +92 io line r PE6/T2EX +93 io line r PE7/GPIFADR8 diff --git a/usrp-hw/sym/generated/cy7c68013-tq100-PWR.src b/usrp-hw/sym/generated/cy7c68013-tq100-PWR.src new file mode 100644 index 000000000..7f5f92e71 --- /dev/null +++ b/usrp-hw/sym/generated/cy7c68013-tq100-PWR.src @@ -0,0 +1,75 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY7C68013-TQ100-PWR +device=CY7C68013-TQ100 +refdes=U? +footprint=TQFP100 +description=Cypress FX2 USB2 Interface +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 7 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line l VCC +2 pwr line r GND +9 pwr line l AVCC +12 pwr line r AGND +16 pwr line l VCC +19 pwr line r GND +20 pwr line l VCC +21 pwr line r GND +33 pwr line l VCC +38 pwr line l VCC +39 pwr line r GND +48 pwr line r GND +49 pwr line l VCC +50 pwr line r GND +53 pwr line l VCC +65 pwr line r GND +66 pwr line l VCC +75 pwr line r GND +78 pwr line l VCC +85 pwr line l VCC +94 pwr line r GND +99 pwr line r GND + + diff --git a/usrp-hw/sym/generated/ep1c12-pq240-CFG.src b/usrp-hw/sym/generated/ep1c12-pq240-CFG.src new file mode 100644 index 000000000..e773107dc --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-CFG.src @@ -0,0 +1,66 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-CFG +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +25 in line l DATA0 +26 in dot l _nCONFIG_ +36 io line l DCLK +145 io line l CONF\_DONE +146 io dot l _nSTATUS_ +32 out dot l _nCEO_ +33 in dot l _nCE_ +34 in line l MSEL0 +35 in line l MSEL1 +1 io line r INIT\_DONE/IO +3 io line r CLKUSR/IO +24 io line r _nCSO_/IO +37 io line r ASDO/IO +239 io line r DEV\_OE/IO +240 io line r _DEV\CLRn_/IO diff --git a/usrp-hw/sym/generated/ep1c12-pq240-CLKA.src b/usrp-hw/sym/generated/ep1c12-pq240-CLKA.src new file mode 100644 index 000000000..b0d6d2baf --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-CLKA.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-CLKA +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 4 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +28 clk clk l CLK0 +29 clk clk l CLK1 +38 io line r PLL1\_OUTp/IO +39 io line r _PLL1\_OUTn_/IO diff --git a/usrp-hw/sym/generated/ep1c12-pq240-CLKB.src b/usrp-hw/sym/generated/ep1c12-pq240-CLKB.src new file mode 100644 index 000000000..145d21916 --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-CLKB.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-CLKB +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 5 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +143 io line r _PLL2\_OUTn_/IO +144 io line r PLL2\_OUTp/IO +152 clk clk l CLK3 +153 clk clk l CLK2 diff --git a/usrp-hw/sym/generated/ep1c12-pq240-IO1.src b/usrp-hw/sym/generated/ep1c12-pq240-IO1.src new file mode 100644 index 000000000..d9f61ce79 --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-IO1.src @@ -0,0 +1,93 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-IO1 +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 6 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 io line l INIT\_DONE/IO +2 io line l IO +3 io line l CLKUSR/IO +4 io line l IO +5 io line l IO +6 io line l IO +7 io line l IO +8 io line l IO +11 io line l IO +12 io line l IO +13 io line l IO +14 io line l IO +15 io line l IO +16 io line l IO +17 io line l IO +18 io line l IO +19 io line l IO +20 io line l IO +21 io line l IO +23 io line l IO +24 io line l _nCSO_/IO +37 io line l ASDO/IO +38 io line l PLL1\_OUTp/IO +39 io line l _PLL1\_OUTn_/IO +41 io line l IO +42 io line l IO +43 io line l IO +44 io line l IO +45 io line l IO +46 io line l IO +47 io line l IO +48 io line l IO +49 io line l IO +50 io line l IO +53 io line l IO +54 io line l IO +55 io line l IO +56 io line l IO +57 io line l IO +58 io line l IO +59 io line l IO +60 io line l IO diff --git a/usrp-hw/sym/generated/ep1c12-pq240-IO2.src b/usrp-hw/sym/generated/ep1c12-pq240-IO2.src new file mode 100644 index 000000000..9934197e4 --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-IO2.src @@ -0,0 +1,93 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-IO2 +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 7 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +181 io line l IO +182 io line l IO +183 io line l IO +184 io line l IO +185 io line l IO +186 io line l IO +187 io line l IO +188 io line l IO +193 io line l IO +194 io line l IO +195 io line l IO +196 io line l IO +197 io line l IO +200 io line l IO +201 io line l IO +202 io line l IO +203 io line l IO +206 io line l IO +207 io line l IO +208 io line l IO +213 io line l IO +214 io line l IO +215 io line l IO +216 io line l IO +217 io line l IO +218 io line l IO +219 io line l IO +222 io line l IO +223 io line l IO +224 io line l IO +225 io line l IO +226 io line l IO +227 io line l IO +228 io line l IO +233 io line l IO +234 io line l IO +235 io line l IO +236 io line l IO +237 io line l IO +238 io line l IO +239 io line l DEV\_OE/IO +240 io line l _DEV\CLRn_/IO diff --git a/usrp-hw/sym/generated/ep1c12-pq240-IO3.src b/usrp-hw/sym/generated/ep1c12-pq240-IO3.src new file mode 100644 index 000000000..79fb4151c --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-IO3.src @@ -0,0 +1,94 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-IO3 +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 8 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +121 io line l IO +122 io line l IO +123 io line l IO +124 io line l IO +125 io line l IO +126 io line l IO +127 io line l IO +128 io line l IO +131 io line l IO +132 io line l IO +133 io line l IO +134 io line l IO +135 io line l IO +136 io line l IO +137 io line l IO +138 io line l IO +139 io line l IO +140 io line l IO +141 io line l IO +143 io line l _PLL2\_OUTn_/IO +144 io line l PLL2\_OUTp/IO +156 io line l IO +158 io line l IO +159 io line l IO +160 io line l IO +161 io line l IO +162 io line l IO +163 io line l IO +164 io line l IO +165 io line l IO +166 io line l IO +167 io line l IO +168 io line l IO +169 io line l IO +170 io line l IO +173 io line l IO +174 io line l IO +175 io line l IO +176 io line l IO +177 io line l IO +178 io line l IO +179 io line l IO +180 io line l IO diff --git a/usrp-hw/sym/generated/ep1c12-pq240-IO4.src b/usrp-hw/sym/generated/ep1c12-pq240-IO4.src new file mode 100644 index 000000000..34b4fb022 --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-IO4.src @@ -0,0 +1,93 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-IO4 +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 9 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +61 io line l IO +62 io line l IO +63 io line l IO +64 io line l IO +65 io line l IO +66 io line l IO +67 io line l IO +68 io line l IO +73 io line l IO +74 io line l IO +75 io line l IO +76 io line l IO +77 io line l IO +78 io line l IO +79 io line l IO +82 io line l IO +83 io line l IO +84 io line l IO +85 io line l IO +86 io line l IO +87 io line l IO +88 io line l IO +93 io line l IO +94 io line l IO +95 io line l IO +98 io line l IO +99 io line l IO +100 io line l IO +101 io line l IO +104 io line l IO +105 io line l IO +106 io line l IO +107 io line l IO +108 io line l IO +113 io line l IO +114 io line l IO +115 io line l IO +116 io line l IO +117 io line l IO +118 io line l IO +119 io line l IO +120 io line l IO diff --git a/usrp-hw/sym/generated/ep1c12-pq240-JTAG.src b/usrp-hw/sym/generated/ep1c12-pq240-JTAG.src new file mode 100644 index 000000000..672a09441 --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-JTAG.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-JTAG +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +147 clk clk l TCK +148 in line l TMS +149 out line l TDO +155 in line l TDI diff --git a/usrp-hw/sym/generated/ep1c12-pq240-PWR.src b/usrp-hw/sym/generated/ep1c12-pq240-PWR.src new file mode 100644 index 000000000..047d87955 --- /dev/null +++ b/usrp-hw/sym/generated/ep1c12-pq240-PWR.src @@ -0,0 +1,105 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=yes +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP1C12-PQ240-PWR +device=EP1C12-PQ240 +refdes=U? +footprint=PQ240 +description=Altera Cyclone EP1C12 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 9 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +9 pwr line l VCCIO1 +10 pwr line r GND +22 pwr line l VCCIO1 +27 pwr line l VCCA\_PLL1 +30 pwr line r GNDA\_PLL1 +31 pwr line r GNDG\_PLL1 +40 pwr line r GND +51 pwr line l VCCIO1 +52 pwr line r GND +69 pwr line r GND +70 pwr line l VCCIO4 +71 pwr line r GND +72 pwr line l VCCINT +80 pwr line r GND +81 pwr line l VCCINT +89 pwr line r GND +90 pwr line l VCCINT +91 pwr line r GND +92 pwr line l VCCIO4 +96 pwr line r GND +97 pwr line l VCCINT +102 pwr line r GND +103 pwr line l VCCINT +109 pwr line r GND +110 pwr line l VCCINT +111 pwr line r GND +112 pwr line l VCCIO4 +129 pwr line r GND +130 pwr line l VCCIO3 +142 pwr line r GND +150 pwr line r GNDG\_PLL2 +151 pwr line r GNDA\_PLL2 +154 pwr line l VCCA\_PLL2 +157 pwr line l VCCIO3 +171 pwr line r GND +172 pwr line l VCCIO3 +189 pwr line l VCCIO2 +190 pwr line r GND +191 pwr line l VCCINT +192 pwr line r GND +198 pwr line l VCCINT +199 pwr line r GND +204 pwr line l VCCINT +205 pwr line r GND +209 pwr line l VCCIO2 +210 pwr line r GND +211 pwr line l VCCINT +212 pwr line r GND +220 pwr line l VCCINT +221 pwr line r GND +229 pwr line l VCCINT +230 pwr line r GND +231 pwr line l VCCIO2 +232 pwr line r GND diff --git a/usrp-hw/sym/generated/ep2c20-f484-CFG.src b/usrp-hw/sym/generated/ep2c20-f484-CFG.src new file mode 100644 index 000000000..5d0083824 --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-CFG.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-CFG +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +L6 in line l DCLK +K4 in line l DATA0 +K1 in line l _nCE_ +L4 in line l _nCONFIG_ +N20 in line l _nSTATUS_ +N18 in line l CONF\_DONE +N17 in line l MSEL1 +M17 in line l MSEL0 diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO1.src b/usrp-hw/sym/generated/ep2c20-f484-IO1.src new file mode 100644 index 000000000..079c87005 --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO1.src @@ -0,0 +1,92 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO1 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +M1 clk clk r CLK2/LVDSCLK1P +M2 clk clk r CLK3/_LVDSCLK1N_ +M5 io line l IO/LVDS15P +M6 io line l IO/_LVDS15N_ +N1 io line l IO/LVDS14P +N2 io line l IO/_LVDS14N_ +P1 io line l IO/LVDS13P +P2 io line l IO/_LVDS13N_ +N6 io line l IO +P3 io line l IO/VREFB1N0 +N3 io line l IO/LVDS12P +N4 io line l IO/_LVDS12N_ +R8 io line l IO/LVDS11P +R7 io line l IO/_LVDS11N_ +P5 io line l IO/LVDS10P +P6 io line l IO/_LVDS10N_ +R1 io line l IO/LVDS9P +R2 io line l IO/_LVDS9N_ +T1 io line l IO/LVDS8P +T2 io line l IO/_LVDS8N_ +U1 io line l IO/LVDS7P +U2 io line l IO/_LVDS7N_ +R5 io line l IO/LVDS6P +R6 io line l IO/_LVDS6N_ +V1 io line l IO/LVDS5P +V2 io line l IO/_LVDS5N_ +T5 io line l IO/LVDS4P +T6 io line l IO/_LVDS4N_ +T3 io line l IO +U3 io line l IO/VREFB1N1 +W1 io line l IO/LVDS3P +W2 io line l IO/_LVDS3N_ +Y1 io line l IO/LVDS2P +Y2 io line l IO/_LVDS2N_ +W3 io line l IO/LVDS1P +W4 io line l IO/_LVDS1N_ +Y3 io line l IO/LVDS0P +Y4 io line l IO/_LVDS0N_ +W5 io line l IO +U4 io line l IO/PLL1\_OUTP +V4 io line l IO/_PLL1\_OUTN_ diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO2.src b/usrp-hw/sym/generated/ep2c20-f484-IO2.src new file mode 100644 index 000000000..2c351c93d --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO2.src @@ -0,0 +1,84 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO2 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +C4 io line r IO/ASDO +C3 io line r IO/_nCSO_ +D3 io line r IO/LVDS26P/CRC\_ERROR +D4 io line r IO/_LVDS26N_/CLKUSR +D5 io line l IO/PLL3\_OUTP +D6 io line l IO/_PLL3\_OUTN_ +E3 io line l IO/LVDS25P +E4 io line l IO/_LVDS25N_ +C1 io line l IO/LVDS24P +C2 io line l IO/_LVDS24N_ +F4 io line l IO/VREFB2N0 +G6 io line l IO/LVDS23P +G5 io line l IO/_LVDS23N_ +F3 io line l IO +D1 io line l IO/LVDS22P +D2 io line l IO/_LVDS22N_ +G3 io line l IO/LVDS21P +H4 io line l IO/_LVDS21N_ +H5 io line l IO/LVDS20P +H6 io line l IO/_LVDS20N_ +E1 io line l IO/LVDS19P +E2 io line l IO/_LVDS19N_ +F1 io line l IO/LVDS18P +F2 io line l IO/_LVDS18N_ +H1 io line l IO/LVDS17P +H2 io line l IO/_LVDS17N_ +L8 io line l IO +H3 io line l IO/VREFB2N1 +J4 io line l IO +J1 io line l IO/LVDS16P +J2 io line l IO/_LVDS16N_ +L1 clk clk r CLK0/LVDSCLK0P +L2 clk clk r CLK1/_LVDSCLK0N_ diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO3.src b/usrp-hw/sym/generated/ep2c20-f484-IO3.src new file mode 100644 index 000000000..bc44343a5 --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO3.src @@ -0,0 +1,94 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO3 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +D12 clk clk r CLK10/_LVDSCLK5N_ +E12 clk clk r CLK11/LVDSCLK5P +B11 io line l IO/_LVDS44N_ +A11 io line l IO/LVDS44P +E11 io line l IO/_LVDS43N_ +D11 io line l IO/LVDS43P +H11 io line l IO/_LVDS42N_ +G11 io line l IO/LVDS42P +B10 io line l IO/_LVDS41N_ +A10 io line l IO/LVDS41P +F11 io line l IO/_LVDS40N_ +F10 io line l IO/LVDS40P +C10 io line l IO/VREFB3N0 +B9 io line l IO/_LVDS39N_ +A9 io line l IO/LVDS39P +H10 io line l IO/_LVDS38N_ +H9 io line l IO/LVDS38P +E9 io line l IO/_LVDS37N_ +D9 io line l IO/LVDS37P +B8 io line l IO/_LVDS36N_ +A8 io line l IO/LVDS36P +B7 io line l IO/_LVDS35N_ +A7 io line l IO/LVDS35P +F9 io line l IO/_LVDS34N_ +E8 io line l IO/LVDS34P +D8 io line l IO/_LVDS33N_ +C9 io line l IO/LVDS33P +D7 io line l IO +F8 io line l IO/_LVDS32N_ +G8 io line l IO/LVDS32P +H8 io line l IO +C7 io line l IO/VREFB3N1 +E7 io line l IO +G7 io line l IO/_LVDS31N_ +H7 io line l IO/LVDS31P +B6 io line l IO/_LVDS30N_ +A6 io line l IO/LVDS30P +B5 io line l IO/_LVDS29N_ +A5 io line l IO/LVDS29P +B4 io line l IO/_LVDS28N_ +A4 io line l IO/LVDS28P +A3 io line l IO/LVDS27P +B3 io line l IO/_LVDS27N_/_DEV\_CLRn_ diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO4.src b/usrp-hw/sym/generated/ep2c20-f484-IO4.src new file mode 100644 index 000000000..98168dc6b --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO4.src @@ -0,0 +1,91 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO4 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +C18 io line l IO/_LVDS61N_ +C17 io line l IO/LVDS61P +B20 io line l IO/_LVDS60N_ +A20 io line l IO/LVDS60P +B19 io line l IO/_LVDS59N_ +A19 io line l IO/LVDS59P +B18 io line l IO/_LVDS58N_ +A18 io line l IO/LVDS58P +G16 io line l IO/_LVDS57N_ +H15 io line l IO/LVDS57P +C16 io line l IO/VREFB4N0 +D16 io line l IO/_LVDS56N_ +E15 io line l IO/LVDS56P +H14 io line l IO/_LVDS55N_ +J14 io line l IO/LVDS55P +D15 io line l IO/_LVDS54N_ +C14 io line l IO/LVDS54P +G15 io line l IO/_LVDS53N_ +F15 io line l IO/LVDS53P +H13 io line l IO +B17 io line l IO/_LVDS52N_ +A17 io line l IO/LVDS52P +E14 io line l IO/_LVDS51N_ +D14 io line l IO/LVDS51P +F14 io line l IO/_LVDS50N_ +F13 io line l IO/LVDS50P +B16 io line l IO/_LVDS49N_ +A16 io line l IO/LVDS49P +B15 io line l IO/_LVDS48N_ +A15 io line l IO/LVDS48P +H12 io line l IO +C13 io line l IO/VREFB4N1 +F12 io line l IO/_LVDS47N_ +G12 io line l IO/LVDS47P +B14 io line l IO/_LVDS46N_ +A14 io line l IO/LVDS46P +B13 io line l IO/_LVDS45N_ +A13 io line l IO/LVDS45P +B12 io line r CLK8/_LVDSCLK4N_ +A12 io line r CLK9/LVDSCLK4P diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO5.src b/usrp-hw/sym/generated/ep2c20-f484-IO5.src new file mode 100644 index 000000000..d35117dff --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO5.src @@ -0,0 +1,90 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO5 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +L21 clk clk r CLK5/_LVDSCLK2N_ +L22 clk clk r CLK4/LVDSCLK2P +L19 io line l IO/_LVDS77N_ +L18 io line l IO/LVDS77P +K21 io line l IO/_LVDS76N_ +K22 io line l IO/LVDS76P +J21 io line l IO/_LVDS75N_ +J22 io line l IO/LVDS75P +J20 io line l IO/_LVDS74N_ +H19 io line l IO/LVDS74P +K20 io line l IO/VREFB5N1 +J19 io line l IO/_LVDS73N_ +J18 io line l IO/LVDS73P +J17 io line l IO/_LVDS72N_ +H16 io line l IO/LVDS72P +J15 io line l IO +G21 io line l IO/_LVDS71N_ +G22 io line l IO/LVDS71P +F21 io line l IO/_LVDS70N_ +F22 io line l IO/LVDS70P +H18 io line l IO/_LVDS69N_ +H17 io line l IO/LVDS69P +E21 io line l IO/_LVDS68N_ +E22 io line l IO/LVDS68P +D21 io line l IO/_LVDS67N_ +D22 io line l IO/LVDS67P +G17 io line l IO/_LVDS66N_ +G18 io line l IO/LVDS66P +G20 io line l IO/VREFB5N0 +E20 io line l IO/_LVDS65N_ +F20 io line l IO/LVDS65P +C21 io line l IO/_LVDS64N_ +C22 io line l IO/LVDS64P +C19 io line l IO/_LVDS63N_ +C20 io line l IO/LVDS63P +D19 io line l IO/_LVDS62N_ +D20 io line l IO/LVDS62P +E19 io line l IO/PLL2\_OUTP +E18 io line l IO/PLL2\_OUTN diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO6.src b/usrp-hw/sym/generated/ep2c20-f484-IO6.src new file mode 100644 index 000000000..aecaf3c0f --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO6.src @@ -0,0 +1,87 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO6 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +Y18 io line l IO +V19 io line r IO/_LVDS91N_/INIT\_DONE +W20 io line r IO/LVDS91P/_nCEO_ +Y19 io line l IO/_LVDS90N_ +Y20 io line l IO/LVDS90P +U18 io line l IO/_PLL4\_OUTN_ +T18 io line l IO/PLL4\_OUTP +U19 io line l IO/_LVDS89N_ +V20 io line l IO/LVDS89P +W21 io line l IO/_LVDS88N_ +W22 io line l IO/LVDS88P +U20 io line l IO/VREFB6N1 +R17 io line l IO +Y21 io line l IO/_LVDS87N_ +Y22 io line l IO/LVDS87P +V21 io line l IO/_LVDS86N_ +V22 io line l IO/LVDS86P +U21 io line l IO/_LVDS85N_ +U22 io line l IO/LVDS85P +R18 io line l IO/_LVDS84N_ +R19 io line l IO/LVDS84P +P17 io line l IO/_LVDS83N_ +P18 io line l IO/LVDS83P +T21 io line l IO/_LVDS82N_ +T22 io line l IO/LVDS82P +R21 io line l IO/_LVDS81N_ +R22 io line l IO/LVDS81P +R20 io line l IO/VREFB6N0 +P15 io line l IO/_LVDS80N_ +N15 io line l IO/LVDS80P +N21 io line l IO/_LVDS79N_ +N22 io line l IO/LVDS79P +M19 io line l IO/_LVDS78N_ +M18 io line l IO/LVDS78P +M21 clk clk r CLK7/_LVDSCLK3N_ +M22 clk clk r CLK6/LVDSCLK3P diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO7.src b/usrp-hw/sym/generated/ep2c20-f484-IO7.src new file mode 100644 index 000000000..c67eae887 --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO7.src @@ -0,0 +1,81 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO7 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +W12 clk clk r CLK13/LVDSCLK6P +V12 clk clk r CLK12/_LVDSCLK6N_ +AB12 io line l IO/LVDS108P +AA12 io line l IO/_LVDS108N_ +AB13 io line l IO/LVDS107P +AA13 io line l IO/_LVDS107N_ +T12 io line l IO/LVDS106P +U13 io line l IO/_LVDS106N_ +Y13 io line l IO/VREFB7N1 +R12 io line l IO +AB14 io line l IO/LVDS105P +AA14 io line l IO/_LVDS105N_ +AB15 io line l IO/LVDS104P +AA15 io line l IO/_LVDS104N_ +AB16 io line l IO/LVDS103P +AA16 io line l IO/_LVDS103N_ +W14 io line l IO/LVDS102P +V14 io line l IO/_LVDS102N_ +AB17 io line l IO/LVDS101P +AA17 io line l IO/_LVDS101N_ +R13 io line l IO +U14 io line l IO/LVDS100P +T15 io line l IO/_LVDS100N_ +Y14 io line l IO/LVDS99P +W15 io line l IO/_LVDS99N_ +R14 io line l IO/LVDS98P +R15 io line l IO/_LVDS98N_ +AB18 io line l IO/LVDS97P +AA18 io line l IO/_LVDS97N_ +Y16 io line l IO/VREFB7N0 diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO8.src b/usrp-hw/sym/generated/ep2c20-f484-IO8.src new file mode 100644 index 000000000..f86bfd65e --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO8.src @@ -0,0 +1,94 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO8 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +AA3 io line l IO/_LVDS127N_/DEV\_OE +AB3 io line l IO/LVDS127P +AB4 io line l IO/LVDS126P +AA4 io line l IO/_LVDS126N_ +Y5 io line l IO/LVDS125P +Y6 io line l IO/_LVDS125N_ +AB5 io line l IO/LVDS124P +AA5 io line l IO/_LVDS124N_ +T8 io line l IO/LVDS123P +T7 io line l IO/_LVDS123N_ +U8 io line l IO +Y7 io line l IO/VREFB8N1 +P9 io line l IO/LVDS122P +P8 io line l IO/_LVDS122N_ +AB6 io line l IO/LVDS121P +AA6 io line l IO/_LVDS121N_ +V8 io line l IO/LVDS120P +W7 io line l IO/_LVDS120N_ +W8 io line l IO/LVDS119P +V9 io line l IO/_LVDS119N_ +AB7 io line l IO/LVDS118P +AA7 io line l IO/_LVDS118N_ +Y9 io line l IO/LVDS117P +W9 io line l IO/_LVDS117N_ +U9 io line l IO/LVDS116P +U10 io line l IO/_LVDS116N_ +R10 io line l IO/LVDS115P +R9 io line l IO/_LVDS115N_ +AB8 io line l IO/LVDS114P +AA8 io line l IO/_LVDS114N_ +Y10 io line l IO/VREFB8N0 +AB9 io line l IO/LVDS113P +AA9 io line l IO/_LVDS113N_ +T11 io line l IO/LVDS112P +R11 io line l IO/_LVDS112N_ +W11 io line l IO/LVDS111P +V11 io line l IO/_LVDS111N_ +AB10 io line l IO/LVDS110P +AA10 io line l IO/_LVDS110N_ +AB11 io line l IO/LVDS109P +AA11 io line l IO/_LVDS109N_ +U11 clk clk r CLK15/LVDSCLK7P +U12 clk clk r CLK14/_LVDSCLK7N_ diff --git a/usrp-hw/sym/generated/ep2c20-f484-JTAG.src b/usrp-hw/sym/generated/ep2c20-f484-JTAG.src new file mode 100644 index 000000000..06369b4ef --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-JTAG.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-JTAG +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +K5 io line l TDI +K2 clk clk l TCK +K6 io line l TMS +L5 io line l TDO diff --git a/usrp-hw/sym/generated/ep2c20-f484-NC.src b/usrp-hw/sym/generated/ep2c20-f484-NC.src new file mode 100644 index 000000000..26058932e --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-NC.src @@ -0,0 +1,82 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-NC +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +G1 io line l NC +G2 io line l NC +H21 io line l NC +H22 io line l NC +J3 io line l NC +J5 io line l NC +J6 io line l NC +J8 io line l NC +J9 io line l NC +K8 io line l NC +K15 io line l NC +K17 io line l NC +K18 io line l NC +L7 io line l NC +L15 io line l NC +L16 io line l NC +L17 io line l NC +M7 io line l NC +M8 io line l NC +M15 io line l NC +M16 io line l NC +N5 io line l NC +N8 io line l NC +P4 io line l NC +P14 io line l NC +P19 io line l NC +P20 io line l NC +P21 io line l NC +P22 io line l NC +R4 io line l NC +W18 io line l NC diff --git a/usrp-hw/sym/generated/ep2c20-f484-PWR.src b/usrp-hw/sym/generated/ep2c20-f484-PWR.src new file mode 100644 index 000000000..5c1b77485 --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-PWR.src @@ -0,0 +1,190 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-PWR +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +U5 pwr line r GND\_PLL1 +U6 pwr line l VCCD\_PLL1 +U7 pwr line l VCCA\_PLL1 +V7 pwr line r GNDA\_PLL1 +V5 pwr line r GND\_PLL1 + +E16 pwr line r GNDA\_PLL2 +E17 pwr line r GND\_PLL2 +F16 pwr line l VCCA\_PLL2 +F17 pwr line l VCCD\_PLL2 +F18 pwr line r GND\_PLL2 + +F5 pwr line r GND\_PLL3 +E5 pwr line l VCCD\_PLL3 +F6 pwr line r GND\_PLL3 +F7 pwr line r GNDA\_PLL3 +E6 pwr line l VCCA\_PLL3 + +V18 pwr line r GND\_PLL4 +U17 pwr line l VCCD\_PLL4 +T17 pwr line r GND\_PLL4 +V16 pwr line r GNDA\_PLL4 +U16 pwr line l VCCA\_PLL4 + +K10 pwr line r GND +K11 pwr line r GND +K12 pwr line r GND +K13 pwr line r GND +L10 pwr line r GND +L11 pwr line r GND +L12 pwr line r GND +L13 pwr line r GND +M10 pwr line r GND +M11 pwr line r GND +M12 pwr line r GND +M13 pwr line r GND +N10 pwr line r GND +N11 pwr line r GND +N12 pwr line r GND +N13 pwr line r GND +A1 pwr line r GND +A22 pwr line r GND +AA2 pwr line r GND +AA21 pwr line r GND +AB1 pwr line r GND +AB22 pwr line r GND +B2 pwr line r GND +B21 pwr line r GND +C5 pwr line r GND +C8 pwr line r GND +C15 pwr line r GND +D10 pwr line r GND +D13 pwr line r GND +D18 pwr line r GND +F19 pwr line r GND +G4 pwr line r GND +G10 pwr line r GND +G13 pwr line r GND +H20 pwr line r GND +K3 pwr line r GND +K7 pwr line r GND +K16 pwr line r GND +K19 pwr line r GND +M4 pwr line r GND +N7 pwr line r GND +N16 pwr line r GND +N19 pwr line r GND +R3 pwr line r GND +T10 pwr line r GND +T13 pwr line r GND +T20 pwr line r GND +V3 pwr line r GND +V6 pwr line r GND +V17 pwr line r GND +W10 pwr line r GND +W13 pwr line r GND +W19 pwr line r GND +Y8 pwr line r GND +Y15 pwr line r GND + +J10 pwr line l VccInt +J11 pwr line l VccInt +J12 pwr line l VccInt +J13 pwr line l VccInt +K9 pwr line l VccInt +K14 pwr line l VccInt +L9 pwr line l VccInt +L14 pwr line l VccInt +M9 pwr line l VccInt +M14 pwr line l VccInt +N9 pwr line l VccInt +N14 pwr line l VccInt +P10 pwr line l VccInt +P11 pwr line l VccInt +P12 pwr line l VccInt +P13 pwr line l VccInt + +AA1 pwr line l VccIO1 +M3 pwr line l VccIO1 +P7 pwr line l VccIO1 +T4 pwr line l VccIO1 + +B1 pwr line l VccIO2 +J7 pwr line l VccIO2 +L3 pwr line l VccIO2 + +A2 pwr line l VccIO3 +C6 pwr line l VccIO3 +C11 pwr line l VccIO3 +E10 pwr line l VccIO3 +G9 pwr line l VccIO3 + +A21 pwr line l VccIO4 +C12 pwr line l VccIO4 +D17 pwr line l VccIO4 +E13 pwr line l VccIO4 +G14 pwr line l VccIO4 + +B22 pwr line l VccIO5 +G19 pwr line l VccIO5 +J16 pwr line l VccIO5 +L20 pwr line l VccIO5 + +AA22 pwr line l VccIO6 +M20 pwr line l VccIO6 +P16 pwr line l VccIO6 +T19 pwr line l VccIO6 + +AB21 pwr line l VccIO7 +T14 pwr line l VccIO7 +V13 pwr line l VccIO7 +W17 pwr line l VccIO7 +Y12 pwr line l VccIO7 + +AB2 pwr line l VccIO8 +T9 pwr line l VccIO8 +V10 pwr line l VccIO8 +W6 pwr line l VccIO8 +Y11 pwr line l VccIO8 diff --git a/usrp-hw/sym/generated/hmc174ms8.src b/usrp-hw/sym/generated/hmc174ms8.src new file mode 100644 index 000000000..1cedb39e4 --- /dev/null +++ b/usrp-hw/sym/generated/hmc174ms8.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=HMC174MS8 +device=HMC174MS8 +refdes=U? +footprint=MSOP8 +description=Hittite Microwave T/R Switch +documentation=http://www.hittite.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 pwr line l Vdd +3 io line r RFC +8 io line l RF2 +5 io line l RF1 +1 in line l A +2 in line l B +6 pwr line l GND +7 pwr line l GND + diff --git a/usrp-hw/sym/generated/lm2940imp.src b/usrp-hw/sym/generated/lm2940imp.src new file mode 100644 index 000000000..fcd2ec59e --- /dev/null +++ b/usrp-hw/sym/generated/lm2940imp.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=LM2940IMP +device=LM2940IMP +refdes=U? +footprint=SOT223 +description=National Fixed LDO +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Pin 4 is tab +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +3 pwr line l Vout +1 pwr line l Vin +2 pwr line r GND +4 pwr line r GND diff --git a/usrp-hw/sym/generated/lt1085.src b/usrp-hw/sym/generated/lt1085.src new file mode 100644 index 000000000..faa294004 --- /dev/null +++ b/usrp-hw/sym/generated/lt1085.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=LT1085CM-3.3 +device=LT1085CM-3.3 +refdes=U? +footprint=LINEAR_DD +description=Linear Tech Fixed LDO +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Pin 4 is tab +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +3 pwr line l VIN +1 pwr line l GND +2 pwr line r VOUT +4 pwr line r VOUT diff --git a/usrp-hw/sym/generated/lt3462.src b/usrp-hw/sym/generated/lt3462.src new file mode 100644 index 000000000..fbd956b32 --- /dev/null +++ b/usrp-hw/sym/generated/lt3462.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=LT3462 +device=LT3462 +refdes=U? +footprint=TSOT23-95P-280L1-6N__LTC_S6_Package +description=Linear Tech Adjustable Negative DC-DC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Needs a pad in the middle for thermal +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line l SW +6 pwr line l Vin +2 pwr line l GND + +5 in line r D +3 in line r FB +4 in line r SDREF diff --git a/usrp-hw/sym/generated/ltc2284-A.src b/usrp-hw/sym/generated/ltc2284-A.src new file mode 100644 index 000000000..dd5a5c984 --- /dev/null +++ b/usrp-hw/sym/generated/ltc2284-A.src @@ -0,0 +1,72 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=LTC2284-A +device=LTC2284 +refdes=U? +footprint=QFN64 +description=Linear Technology Dual 14-bit 105 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l VIN+\_A +2 in line l _VIN-\_A_ +8 clk clk l CLK\_A +41 out line r D0\_A +42 out line r D1\_A +43 out line r D2\_A +44 out line r D3\_A +45 out line r D4\_A +46 out line r D5\_A +47 out line r D6\_A +48 out line r D7\_A +51 out line r D8\_A +52 out line r D9\_A +53 out line r D10\_A +54 out line r D11\_A +55 out line r D12\_A +56 out line r D13\_A +57 out line r OVF\_A +58 in dot l _OEB\_A_ +59 in line l PDWN\_A + diff --git a/usrp-hw/sym/generated/ltc2284-B.src b/usrp-hw/sym/generated/ltc2284-B.src new file mode 100644 index 000000000..1d05ccc20 --- /dev/null +++ b/usrp-hw/sym/generated/ltc2284-B.src @@ -0,0 +1,71 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=LTC2284-A +device=LTC2284 +refdes=U? +footprint=QFN64 +description=Linear Technology Dual 14-bit 105 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +16 in line l VIN+\_B +15 in line l _VIN-\_B_ +9 clk clk l CLK\_B +24 out line r D0\_B +25 out line r D1\_B +26 out line r D2\_B +27 out line r D3\_B +28 out line r D4\_B +29 out line r D5\_B +30 out line r D6\_B +33 out line r D7\_B +34 out line r D8\_B +35 out line r D9\_B +36 out line r D10\_B +37 out line r D11\_B +38 out line r D12\_B +39 out line r D13\_B +40 out line r OVF\_B +23 in dot l _OEB\_B_ +22 in line l PDWN\_B diff --git a/usrp-hw/sym/generated/ltc2284-CTRL.src b/usrp-hw/sym/generated/ltc2284-CTRL.src new file mode 100644 index 000000000..0c2257178 --- /dev/null +++ b/usrp-hw/sym/generated/ltc2284-CTRL.src @@ -0,0 +1,65 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=LTC2284-CTRL +device=LTC2284 +refdes=U? +footprint=QFN64 +description=Linear Technology Dual 14-bit 105 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +3 in line l REFH\_A +4 in line l REFH\_A +5 in line l REFL\_A +6 in line l REFL\_A +13 in line l REFH\_B +14 in line l REFH\_B +11 in line l REFL\_B +12 in line l REFL\_B +62 in line r SENSE\_A +19 in line r SENSE\_B +21 in line r MUX +60 in line r MODE +61 in line r VCM\_A +20 in line r VCM\_B diff --git a/usrp-hw/sym/generated/ltc2284-PWR.src b/usrp-hw/sym/generated/ltc2284-PWR.src new file mode 100644 index 000000000..b5180f970 --- /dev/null +++ b/usrp-hw/sym/generated/ltc2284-PWR.src @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=LTC2284-PWR +device=LTC2284 +refdes=U? +footprint=QFN64 +description=Linear Technology Dual 14-bit 105 MS/s ADC +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +17 pwr line r GND +64 pwr line r GND +65 pwr line r GND\_EP +7 pwr line l AVdd +10 pwr line l AVdd +18 pwr line l AVdd +63 pwr line l AVdd +31 pwr line r DGND +50 pwr line r DGND +32 pwr line l DVdd +49 pwr line l DVdd + diff --git a/usrp-hw/sym/generated/make_symbols b/usrp-hw/sym/generated/make_symbols new file mode 100755 index 000000000..b0cec58f5 --- /dev/null +++ b/usrp-hw/sym/generated/make_symbols @@ -0,0 +1,126 @@ +#!/bin/sh + +tragesym ad9238-PWR.src ad9238-PWR.sym +tragesym ad9238-CTRL.src ad9238-CTRL.sym +tragesym ad9238-A.src ad9238-A.sym +tragesym ad9238-B.src ad9238-B.sym + +tragesym ltc2284-PWR.src ltc2284-PWR.sym +tragesym ltc2284-CTRL.src ltc2284-CTRL.sym +tragesym ltc2284-A.src ltc2284-A.sym +tragesym ltc2284-B.src ltc2284-B.sym + +tragesym ad9777-PWR.src ad9777-PWR.sym +tragesym ad9777-CTRL.src ad9777-CTRL.sym +tragesym ad9777-CH1.src ad9777-CH1.sym +tragesym ad9777-CH2.src ad9777-CH2.sym + +tragesym ad9767-PWR.src ad9767-PWR.sym +tragesym ad9767-CTRL.src ad9767-CTRL.sym +tragesym ad9767-CH1.src ad9767-CH1.sym +tragesym ad9767-CH2.src ad9767-CH2.sym + +tragesym cy7c68013-tq100-PWR.src cy7c68013-tq100-PWR.sym +tragesym cy7c68013-tq100-CTRL.src cy7c68013-tq100-CTRL.sym +tragesym cy7c68013-tq100-BUS.src cy7c68013-tq100-BUS.sym +tragesym cy7c68013-tq100-PA.src cy7c68013-tq100-PA.sym +tragesym cy7c68013-tq100-PC.src cy7c68013-tq100-PC.sym +tragesym cy7c68013-tq100-PE.src cy7c68013-tq100-PE.sym +tragesym cy7c68013-tq100-MISC.src cy7c68013-tq100-MISC.sym + +tragesym ep1c12-pq240-PWR.src ep1c12-pq240-PWR.sym +tragesym ep1c12-pq240-CFG.src ep1c12-pq240-CFG.sym +tragesym ep1c12-pq240-IO1.src ep1c12-pq240-IO1.sym +tragesym ep1c12-pq240-IO2.src ep1c12-pq240-IO2.sym +tragesym ep1c12-pq240-IO3.src ep1c12-pq240-IO3.sym +tragesym ep1c12-pq240-IO4.src ep1c12-pq240-IO4.sym +tragesym ep1c12-pq240-CLKA.src ep1c12-pq240-CLKA.sym +tragesym ep1c12-pq240-CLKB.src ep1c12-pq240-CLKB.sym +tragesym ep1c12-pq240-JTAG.src ep1c12-pq240-JTAG.sym + +tragesym ep2c20-f484-JTAG.src ep2c20-f484-JTAG.sym +tragesym ep2c20-f484-CFG.src ep2c20-f484-CFG.sym +tragesym ep2c20-f484-PWR.src ep2c20-f484-PWR.sym +tragesym ep2c20-f484-NC.src ep2c20-f484-NC.sym +tragesym ep2c20-f484-IO1.src ep2c20-f484-IO1.sym +tragesym ep2c20-f484-IO2.src ep2c20-f484-IO2.sym +tragesym ep2c20-f484-IO3.src ep2c20-f484-IO3.sym +tragesym ep2c20-f484-IO4.src ep2c20-f484-IO4.sym +tragesym ep2c20-f484-IO5.src ep2c20-f484-IO5.sym +tragesym ep2c20-f484-IO6.src ep2c20-f484-IO6.sym +tragesym ep2c20-f484-IO7.src ep2c20-f484-IO7.sym +tragesym ep2c20-f484-IO8.src ep2c20-f484-IO8.sym + +tragesym max211x-PWR.src max211x-PWR.sym +tragesym max211x-PLL.src max211x-PLL.sym +tragesym max211x-SIG.src max211x-SIG.sym +tragesym max211x-DIG.src max211x-DIG.sym + +tragesym max355x-PWR.src max355x-PWR.sym +tragesym max355x-DIG.src max355x-DIG.sym +tragesym max355x-PLL.src max355x-PLL.sym +tragesym max355x-BIAS.src max355x-BIAS.sym +tragesym max355x-RF.src max355x-RF.sym +tragesym max355x-IF.src max355x-IF.sym + +tragesym saw.src saw.sym +tragesym lt3462.src lt3462.sym + +tragesym tps777xx-pwp.src tps777xx-pwp.sym +tragesym lt1085.src lt1085.sym +tragesym adp3336.src adp3336.sym +tragesym lm2940imp.src lm2940imp.sym +tragesym mic5216.src mic5216.sym +tragesym va1t1ur2076.src va1t1ur2076.sym +tragesym mt4736py5.src mt4736py5.sym +tragesym mt4937di5.src mt4937di5.sym +tragesym bs2s7hz1204.src bs2s7hz1204.sym +tragesym hmc174ms8.src hmc174ms8.sym +tragesym max502x.src max502x.sym +tragesym ad813x.src ad813x.sym + +tragesym vctcxo.src vctcxo.sym + +tragesym ad986X-PWR.src ad986X-PWR.sym +tragesym ad986X-CLK.src ad986X-CLK.sym +tragesym ad986X-CTRL.src ad986X-CTRL.sym +tragesym ad986X-ACTRL.src ad986X-ACTRL.sym +tragesym ad986X-AUX.src ad986X-AUX.sym +tragesym ad986X-TX.src ad986X-TX.sym +tragesym ad986X-RX.src ad986X-RX.sym + +tragesym ad834X-PWR.src ad834X-PWR.sym +tragesym ad834X-MIX.src ad834X-MIX.sym + +tragesym adf4360-PWR.src adf4360-PWR.sym +tragesym adf4360-DIG.src adf4360-DIG.sym +tragesym adf4360-ANLG.src adf4360-ANLG.sym + +tragesym ad8347-PWR.src ad8347-PWR.sym +tragesym ad8347-BIAS.src ad8347-BIAS.sym +tragesym ad8347-MIX.src ad8347-MIX.sym +tragesym ad8347-OUT.src ad8347-OUT.sym + +tragesym ad8348-PWR.src ad8348-PWR.sym +tragesym ad8348-BIAS.src ad8348-BIAS.sym +tragesym ad8348-MIX.src ad8348-MIX.sym +tragesym ad8348-OUT.src ad8348-OUT.sym + +tragesym ad9513-PWR.src ad9513-PWR.sym +tragesym ad9513-CLK.src ad9513-CLK.sym +tragesym ad9513-CTRL.src ad9513-CTRL.sym + +tragesym ad9510-PWR.src ad9510-PWR.sym +tragesym ad9510-PLL.src ad9510-PLL.sym +tragesym ad9510-CTRL.src ad9510-CTRL.sym +tragesym ad9510-OUTA.src ad9510-OUTA.sym +tragesym ad9510-OUTB.src ad9510-OUTB.sym + +tragesym max128X.src max128X.sym +tragesym max5742.src max5742.sym + +tragesym max282X-TX.src max282X-TX.sym +tragesym max282X-RX.src max282X-RX.sym +tragesym max282X-PWR.src max282X-PWR.sym +tragesym max282X-CTRL.src max282X-CTRL.sym + diff --git a/usrp-hw/sym/generated/max128X.src b/usrp-hw/sym/generated/max128X.src new file mode 100644 index 000000000..9d0aa7c5f --- /dev/null +++ b/usrp-hw/sym/generated/max128X.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX128X +device=MAX128X +refdes=U? +footprint=SOT23-8 +description=Maxim Dual 12-bit serial ADC +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line t Vdd +4 pwr line b GND +2 in line r Ain1 +3 in line r Ain2 +5 in line r Ref +6 in line l CNVST +7 out line l Dout +8 in clk l SCLK diff --git a/usrp-hw/sym/generated/max211x-DIG.src b/usrp-hw/sym/generated/max211x-DIG.src new file mode 100644 index 000000000..b7a5a274b --- /dev/null +++ b/usrp-hw/sym/generated/max211x-DIG.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX211X-DIG +device=MAX211X +refdes=U? +footprint=QFN40_6_EP +description=Maxim DBS Tuner, max2116 (se) or 2118 (diff) +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- + +8 pwr line r Vreg1 +28 pwr line r Vreg2 + +15 in line l AS2 +26 in line l AS1 +32 in line l AS0 +27 io line l SDA +29 io line l SCL diff --git a/usrp-hw/sym/generated/max211x-PLL.src b/usrp-hw/sym/generated/max211x-PLL.src new file mode 100644 index 000000000..94c14f030 --- /dev/null +++ b/usrp-hw/sym/generated/max211x-PLL.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX211X-PLL +device=MAX211X +refdes=U? +footprint=QFN40_6_EP +description=Maxim DBS Tuner, max2116 (se) or 2118 (diff) +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +16 in line r Vtune +17 out line r CPout + +21 in line l XTAL+ +22 in line l _XTAL-_ +24 out line l XTALOUT +23 out line l CNTOUT/NC + diff --git a/usrp-hw/sym/generated/max211x-PWR.src b/usrp-hw/sym/generated/max211x-PWR.src new file mode 100644 index 000000000..305a9b9a0 --- /dev/null +++ b/usrp-hw/sym/generated/max211x-PWR.src @@ -0,0 +1,74 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX211X-PWR +device=MAX211X +refdes=U? +footprint=QFN40_6_EP +description=Maxim DBS Tuner, max2116 (se) or 2118 (diff) +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- + +2 in line r IDC+ +1 in line r _IDC-_ +39 in line r QDC+ +40 in line r _QDC-_ +14 in line r LOFLT +20 in line r CFLT + +3 pwr line l VccRF1 +12 pwr line l VccLO +13 pwr line l VccVCO +19 pwr line l VccPX +30 pwr line l VccDIG +35 pwr line l VccBB +38 pwr line l VccRF2 + +6 in line l GND +9 in line l GND +11 in line l GND +18 in line l GND +25 in line l GND +31 in line l GND +10 pwr line l GND-PADTEST +41 pwr line l GNDPAD diff --git a/usrp-hw/sym/generated/max211x-SIG.src b/usrp-hw/sym/generated/max211x-SIG.src new file mode 100644 index 000000000..0f0602fa7 --- /dev/null +++ b/usrp-hw/sym/generated/max211x-SIG.src @@ -0,0 +1,59 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX211X-SIG +device=MAX211X +refdes=U? +footprint=QFN40_6_EP +description=Maxim DBS Tuner, max2116 (se) or 2118 (diff) +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +5 in line l RFIN+ +4 in line l _RFIN-_ + +7 in line l GC1 + +37 out line r IOUT+ +36 out line r NC/_IOUT-_ +34 out line r QOUT+ +33 out line r NC/_QOUT-_ diff --git a/usrp-hw/sym/generated/max282X-CTRL.src b/usrp-hw/sym/generated/max282X-CTRL.src new file mode 100644 index 000000000..2e15763cb --- /dev/null +++ b/usrp-hw/sym/generated/max282X-CTRL.src @@ -0,0 +1,69 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX282X-CTRL +device=MAX282X +refdes=U? +footprint=TQFN56 +description=Maxim 2.4 and 5 GHz transceiver +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 2 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +26 in line r DIN +27 in clk r SCLK +28 in line r _CS_ +30 in line b Rosc +33 out line b CPout +36 in line b Tune +39 in line l _SHDN_ +41 in line l RXENA +13 in line l TXENA +42 in line l RXHP +29 out line l LD +48 in line l B1 +50 in line l B2 +53 in line l B3 +54 in line l B4 +56 in line l B5 +1 in line l B6 +3 in line l B7 diff --git a/usrp-hw/sym/generated/max282X-PWR.src b/usrp-hw/sym/generated/max282X-PWR.src new file mode 100644 index 000000000..239ca80aa --- /dev/null +++ b/usrp-hw/sym/generated/max282X-PWR.src @@ -0,0 +1,74 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX282X-TX +device=MAX282X +refdes=U? +footprint=TQFN56 +description=Maxim 2.4 and 5 GHz transceiver +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 1 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 pwr line l Vcc +10 pwr line l Vcc +15 pwr line l Vcc +20 pwr line l Vcc +22 pwr line l Vcc +25 pwr line l Vcc +31 pwr line l Vcc +38 pwr line l Vcc +47 pwr line l Vcc +49 pwr line l Vcc +52 pwr line l Vcc +55 pwr line l Vcc +5 pwr line r GND +7 pwr line r GND +24 pwr line r GND +32 pwr line r GND +34 pwr line r GND +35 pwr line r GND +51 pwr line r GND +57 pwr line r GND\_EP +21 in line b Rbias +37 in line b Bypass +23 out line b Vref diff --git a/usrp-hw/sym/generated/max282X-RX.src b/usrp-hw/sym/generated/max282X-RX.src new file mode 100644 index 000000000..eae398f05 --- /dev/null +++ b/usrp-hw/sym/generated/max282X-RX.src @@ -0,0 +1,58 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX282X-RX +device=MAX282X +refdes=U? +footprint=TQFN56 +description=Maxim 2.4 and 5 GHz transceiver +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 4 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +6 in line l RXRFH +40 out line r RSSI +46 out line r RXBBI+ +45 out line r _RXBBI-_ +44 out line r RXBBQ+ +43 out line r _RXBBQ-_ +4 in line l RXRFL diff --git a/usrp-hw/sym/generated/max282X-TX.src b/usrp-hw/sym/generated/max282X-TX.src new file mode 100644 index 000000000..e8c6cd624 --- /dev/null +++ b/usrp-hw/sym/generated/max282X-TX.src @@ -0,0 +1,60 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX282X-TX +device=MAX282X +refdes=U? +footprint=TQFN56 +description=Maxim 2.4 and 5 GHz transceiver +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=Part 3 of 4 +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +8 out line r TXRFH+ +9 out line r _TXRFH-_ +16 in line l TXBBI+ +17 in line l _TXBBI-_ +18 in line l TXBBQ+ +19 in line l _TXBBQ-_ +11 out line r TXRFL+ +12 out line r _TXRFL-_ +14 out line r PABIAS diff --git a/usrp-hw/sym/generated/max355x-BIAS.src b/usrp-hw/sym/generated/max355x-BIAS.src new file mode 100644 index 000000000..404884615 --- /dev/null +++ b/usrp-hw/sym/generated/max355x-BIAS.src @@ -0,0 +1,56 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX355X-BIAS +device=MAX355X +refdes=U? +footprint=QFN48_7_EP +description=Maxim TV Tuner, max3550/1/3 +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +48 in line l LNABias +46 in line l Bias +9 in line l LOCFlt1 +29 in line l LOCFlt2 +17 io line l NC + diff --git a/usrp-hw/sym/generated/max355x-DIG.src b/usrp-hw/sym/generated/max355x-DIG.src new file mode 100644 index 000000000..502a1dfe4 --- /dev/null +++ b/usrp-hw/sym/generated/max355x-DIG.src @@ -0,0 +1,57 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX355X-DIG +device=MAX355X +refdes=U? +footprint=QFN48_7_EP +description=Maxim TV Tuner, max3550/1/3 +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +22 in line l OSCIN +21 out line l OSCOUT +16 out line r DIV/LD +13 in line r SCL/SCLK +14 in line r SDA/SDI +12 in line r ADDR1/_CS_ +11 in line r ADDR2/NC diff --git a/usrp-hw/sym/generated/max355x-IF.src b/usrp-hw/sym/generated/max355x-IF.src new file mode 100644 index 000000000..09714741f --- /dev/null +++ b/usrp-hw/sym/generated/max355x-IF.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX355X-IF +device=MAX355X +refdes=U? +footprint=QFN48_7_EP +description=Maxim TV Tuner, max3550/1/3 +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +38 in line l IFin+ +39 in line l _IFin-_ +42 out line r IFOut2+ +43 out line r _IFOut2-_ +40 in line l IFVGA diff --git a/usrp-hw/sym/generated/max355x-PLL.src b/usrp-hw/sym/generated/max355x-PLL.src new file mode 100644 index 000000000..f03466606 --- /dev/null +++ b/usrp-hw/sym/generated/max355x-PLL.src @@ -0,0 +1,54 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX355X-PLL +device=MAX355X +refdes=U? +footprint=QFN48_7_EP +description=Maxim TV Tuner, max3550/1/3 +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +8 in line l Tune1 +18 out line l CPout1 +30 in line r Tune2 +26 out line r CPout2 diff --git a/usrp-hw/sym/generated/max355x-PWR.src b/usrp-hw/sym/generated/max355x-PWR.src new file mode 100644 index 000000000..6f42c0f8a --- /dev/null +++ b/usrp-hw/sym/generated/max355x-PWR.src @@ -0,0 +1,73 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX355X-PWR +device=MAX355X +refdes=U? +footprint=QFN48_7_EP +description=Maxim TV Tuner, max3550/1/3 +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line l Vcc +5 pwr line l Vcc +7 pwr line l Vcc +15 pwr line l Vcc +19 pwr line l Vcc +25 pwr line l Vcc +27 pwr line l Vcc +31 pwr line l Vcc +33 pwr line l Vcc +37 pwr line l Vcc +41 pwr line l Vcc +44 pwr line l Vcc +4 pwr line r GND +6 pwr line r GND +10 pwr line r GND +20 pwr line r GND +23 pwr line r GND +24 pwr line r GND +28 pwr line r GND +32 pwr line r GND +34 pwr line r GND +45 pwr line r GND +49 pwr line r GND\_PAD diff --git a/usrp-hw/sym/generated/max355x-RF.src b/usrp-hw/sym/generated/max355x-RF.src new file mode 100644 index 000000000..7fd6ac95c --- /dev/null +++ b/usrp-hw/sym/generated/max355x-RF.src @@ -0,0 +1,56 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX355X-RF +device=MAX355X +refdes=U? +footprint=QFN48_7_EP +description=Maxim TV Tuner, max3550/1/3 +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 in line l RFIn+ +3 in line l _RFIn-_ +35 out line r IFOut1+ +36 out line r _IFOut1-_ +47 in line l RFVGA + diff --git a/usrp-hw/sym/generated/max502x.src b/usrp-hw/sym/generated/max502x.src new file mode 100644 index 000000000..f0bdad3bc --- /dev/null +++ b/usrp-hw/sym/generated/max502x.src @@ -0,0 +1,57 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX502X +device=MAX502X +refdes=U? +footprint=SOT23 +description=Maxim PWM Steup-up DC-DC Conv +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +5 pwr line l VCC +4 in line l _SHDN_ +1 pwr line l PGND +2 pwr line l GND +6 io line r LX +3 in line r FB diff --git a/usrp-hw/sym/generated/max5742.src b/usrp-hw/sym/generated/max5742.src new file mode 100644 index 000000000..def043685 --- /dev/null +++ b/usrp-hw/sym/generated/max5742.src @@ -0,0 +1,60 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MAX5742 +device=MAX5742 +refdes=U? +footprint=uMAX10 +description=Quad 12-bit serial DAC +documentation=http://www.maxim-ic.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +3 pwr line t Vdd +4 pwr line b GND +2 in clk l SCLK +1 in line l _CS_ +5 in line l Din +7 out line r OUTA +8 out line r OUTB +9 out line r OUTC +10 out line r OUTD +6 in line l Ref diff --git a/usrp-hw/sym/generated/mic5216.src b/usrp-hw/sym/generated/mic5216.src new file mode 100644 index 000000000..efcaa8d79 --- /dev/null +++ b/usrp-hw/sym/generated/mic5216.src @@ -0,0 +1,56 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MIC5216-5.0BM5 +device=MIC5216-5.0BM5 +refdes=U? +footprint=SOT23_5_LOCAL +description=Micrel Fixed LDO +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line l VIN +2 pwr line l GND +3 pwr line l ENB +5 pwr line r VOUT +4 pwr line r FLAG diff --git a/usrp-hw/sym/generated/mt4736py5.src b/usrp-hw/sym/generated/mt4736py5.src new file mode 100644 index 000000000..79ba177cc --- /dev/null +++ b/usrp-hw/sym/generated/mt4736py5.src @@ -0,0 +1,64 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MT4736PY5 +device=MT4736PY5 +refdes=U? +footprint=MT4736PY5 +description=Microtune Cable Modem Tuner +documentation=http://www.microtune.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l REV\_CH +5 in line l AGC +6 io line l ADC\_IO +9 io line l SCL +10 io line l SDA +11 out line l I2C\_ADDR +4 pwr line r B1\_5V +8 pwr line r B2\_5V +12 out line r IFOUT\_P +13 out line r _IFOUT\_N_ +2 in line r NC +3 in line r NC +7 in line r NC diff --git a/usrp-hw/sym/generated/mt4937di5.src b/usrp-hw/sym/generated/mt4937di5.src new file mode 100644 index 000000000..feb462608 --- /dev/null +++ b/usrp-hw/sym/generated/mt4937di5.src @@ -0,0 +1,81 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MT4937DI5 +device=MT4937DI5 +refdes=U? +footprint=MT4937DI5 +description=Microtune Cable Modem Tuner +documentation=http://www.microtune.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- + +7 in line l RFAGC +16 in line l IFAGC + +3 pwr line r VS1 +6 pwr line r VS2 +10 pwr line r VS3 +15 pwr line r VS4 + +13 in line l AS2 +11 io line l SCL2 +12 io line l SDA2 + +14 in line r NC + +4 in line r AS1 +8 io line r SCL1 +9 io line r SDA1 + +1 in line r Upstream1 +2 in line r Upstream1 +5 in line r TXEN + +17 out line l out+ +18 out line l _out-_ + +21 pwr line r GND +22 pwr line r GND +23 pwr line r GND +24 pwr line r GND diff --git a/usrp-hw/sym/generated/saw.src b/usrp-hw/sym/generated/saw.src new file mode 100644 index 000000000..756204918 --- /dev/null +++ b/usrp-hw/sym/generated/saw.src @@ -0,0 +1,56 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=SAW +device=SAW +refdes=U? +footprint=SIP5 +description=SAW Filter Epcos B39440-X6965-D100 +documentation=NA +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l In +2 in line l In-GND +3 pwr line l GND +4 out line l Out1 +5 out line l Out2 diff --git a/usrp-hw/sym/generated/template.src b/usrp-hw/sym/generated/template.src new file mode 100644 index 000000000..3595d7c7c --- /dev/null +++ b/usrp-hw/sym/generated/template.src @@ -0,0 +1,51 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name= +device= +refdes=U? +footprint= +description= +documentation= +author= +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- diff --git a/usrp-hw/sym/generated/tps777xx-pwp.src b/usrp-hw/sym/generated/tps777xx-pwp.src new file mode 100644 index 000000000..ea37838e8 --- /dev/null +++ b/usrp-hw/sym/generated/tps777xx-pwp.src @@ -0,0 +1,71 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=TPS777XX-PWP +device=TPS777XX-PWP +refdes=U? +footprint=PWP-20 +description=TI LDO Voltage regulators Vout=XX +documentation=http://focus.ti.com/docs/prod/folders/print/tps77715.html +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +6 pwr line l IN +7 pwr line l IN +5 in dot l _EN_ +4 io line l NC +8 io line l NC +3 pwr line l GND +1 pwr line l GND/HSINK +2 pwr line l GND/HSINK +9 pwr line l GND/HSINK +10 pwr line l GND/HSINK +13 pwr line r OUT +14 pwr line r OUT +15 in line r FB/NC +16 io line r _RESET_/PG +17 io line r NC +18 io line r NC +11 pwr line r GND/HSINK +12 pwr line r GND/HSINK +19 pwr line r GND/HSINK +20 pwr line r GND/HSINK diff --git a/usrp-hw/sym/generated/va1t1ur2076.src b/usrp-hw/sym/generated/va1t1ur2076.src new file mode 100644 index 000000000..6c00834c8 --- /dev/null +++ b/usrp-hw/sym/generated/va1t1ur2076.src @@ -0,0 +1,62 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=VA1T1UR2076 +device=VA1T1UR2076 +refdes=U? +footprint=VA1T1UR2076 +description=Sharp Microelectronics DTV Tuner +documentation=http://www.sharpsma.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +comment=NC pins -- 1,3 +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 pwr line l BB\_5V +5 pwr line l B1\_5V +6 pwr line l B2\_5V +9 out line l BT\_30V\_MON +4 out line l RFAGC\_MON +7 io line l SCL +8 io line l SDA +10 in line l IFAGC +11 out line r IFOUT\_P +12 out line r _IFOUT\_N_ +100 pwr line l GND\_CASE diff --git a/usrp-hw/sym/generated/vctcxo.src b/usrp-hw/sym/generated/vctcxo.src new file mode 100644 index 000000000..64b9a5f6a --- /dev/null +++ b/usrp-hw/sym/generated/vctcxo.src @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=VCTCXO +device=VCTCXO +refdes=U? +footprint=vctcxo +description=VCTCXO +documentation=N/A +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +3 out line r OUT +1 in line r ENB/TUNE +4 pwr line l Vcc +2 pwr line l GND diff --git a/usrp-hw/sym/gschemrc b/usrp-hw/sym/gschemrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/sym/gschemrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/sym/header4-1.sym b/usrp-hw/sym/header4-1.sym new file mode 100644 index 000000000..66c38f24f --- /dev/null +++ b/usrp-hw/sym/header4-1.sym @@ -0,0 +1,42 @@ +v 20030901 +T 100 450 8 10 0 0 0 0 +device=HEADER4 +T 400 1700 8 10 1 1 0 0 +refdes=J? +T 100 650 8 10 0 0 0 0 +class=IO +T 100 850 8 10 0 0 0 0 +pins=3 +P 0 1400 300 1400 1 0 0 +{ +T 100 1450 5 8 1 1 0 0 +pinnumber=1 +T 100 1450 5 8 0 0 0 0 +pinseq=1 +} +P 0 1000 300 1000 1 0 0 +{ +T 100 1050 5 8 1 1 0 0 +pinnumber=2 +T 100 1050 5 8 0 0 0 0 +pinseq=2 +} +P 0 600 300 600 1 0 0 +{ +T 100 650 5 8 1 1 0 0 +pinnumber=3 +T 100 650 5 8 0 0 0 0 +pinseq=3 +} +B 300 0 400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 400 700 400 3 0 0 0 -1 -1 +L 300 1200 700 1200 3 0 0 0 -1 -1 +L 300 800 700 800 3 0 0 0 -1 -1 +P 0 200 300 200 1 0 0 +{ +T 100 250 5 8 1 1 0 0 +pinnumber=4 +T 100 250 5 8 0 0 0 0 +pinseq=4 +} +L 300 400 700 400 3 0 0 0 -1 -1 diff --git a/usrp-hw/sym/hmc311st89.sym b/usrp-hw/sym/hmc311st89.sym new file mode 100644 index 000000000..94d0d099e --- /dev/null +++ b/usrp-hw/sym/hmc311st89.sym @@ -0,0 +1,41 @@ +v 20040111 1 +T 600 1300 8 10 1 1 0 0 1 +refdes=U? +P 1500 700 1700 700 1 0 1 +{ +T 1600 500 3 10 1 1 0 6 1 +pinnumber=3 +T 1400 800 5 10 0 0 0 6 1 +pinseq=3 +} +P 700 300 700 0 1 0 1 +{ +T 700 100 3 10 1 1 0 6 1 +pinnumber=4 +T 800 300 5 10 0 0 90 0 1 +pinseq=4 +} +P 200 700 0 700 1 0 1 +{ +T 200 500 3 10 1 1 0 6 1 +pinnumber=1 +T 200 800 5 10 0 0 0 6 1 +pinseq=1 +} +T 100 600 8 10 0 0 0 0 1 +device=HMC311ST89 +P 900 400 900 0 1 0 1 +{ +T 1000 100 3 10 1 1 0 3 1 +pinnumber=2 +T 1000 100 5 10 0 0 90 0 1 +pinseq=2 +} +L 200 1300 200 100 3 0 0 0 -1 -1 +L 200 100 1500 700 3 0 0 0 -1 -1 +L 1500 700 200 1300 3 0 0 0 -1 -1 +T 700 700 9 10 1 0 0 4 2 +HMC311- +ST89 +T 1500 1300 8 10 0 1 0 0 1 +footprint=SOT89 diff --git a/usrp-hw/sym/mga6x563.sym b/usrp-hw/sym/mga6x563.sym new file mode 100644 index 000000000..f7fc2561c --- /dev/null +++ b/usrp-hw/sym/mga6x563.sym @@ -0,0 +1,52 @@ +v 20040111 1 +T 600 1300 8 10 1 1 0 0 1 +refdes=U? +P 1500 700 1700 700 1 0 1 +{ +T 1600 500 3 10 1 1 0 6 1 +pinnumber=6 +T 1400 800 5 10 0 0 0 6 1 +pinseq=6 +} +P 900 1000 900 1200 1 0 1 +{ +T 1000 1000 3 10 1 1 0 0 1 +pinnumber=4 +T 800 1000 5 10 0 0 270 0 1 +pinseq=4 +} +P 200 700 0 700 1 0 1 +{ +T 200 500 3 10 1 1 0 6 1 +pinnumber=3 +T 200 800 5 10 0 0 0 6 1 +pinseq=3 +} +P 600 300 600 0 1 0 1 +{ +T 700 100 3 10 1 1 0 3 1 +pinnumber=1 +T 500 100 5 10 0 0 270 0 1 +pinseq=1 +} +T 300 700 8 10 0 0 0 0 1 +device=MGA6x563 +P 900 400 900 0 1 0 1 +{ +T 1000 100 3 10 1 1 0 3 1 +pinnumber=2 +T 1000 100 5 10 0 0 90 0 1 +pinseq=2 +} +P 1200 500 1200 0 1 0 1 +{ +T 1300 100 3 10 1 1 0 3 1 +pinnumber=5 +T 1300 100 5 10 0 0 90 0 1 +pinseq=5 +} +L 200 1300 200 100 3 0 0 0 -1 -1 +L 200 100 1500 700 3 0 0 0 -1 -1 +L 1500 700 200 1300 3 0 0 0 -1 -1 +T 800 700 9 10 1 0 0 4 1 +MGA6x563 diff --git a/usrp-hw/sym/mga82563.sym b/usrp-hw/sym/mga82563.sym new file mode 100644 index 000000000..9b72828a9 --- /dev/null +++ b/usrp-hw/sym/mga82563.sym @@ -0,0 +1,52 @@ +v 20040111 1 +T 600 1300 8 10 1 1 0 0 1 +refdes=U? +P 1500 700 1700 700 1 0 1 +{ +T 1600 500 3 10 1 1 0 6 1 +pinnumber=6 +T 1400 800 5 10 0 0 0 6 1 +pinseq=6 +} +P 400 200 400 0 1 0 1 +{ +T 500 100 3 10 1 1 0 3 1 +pinnumber=4 +T 500 200 5 10 0 0 90 0 1 +pinseq=4 +} +P 200 700 0 700 1 0 1 +{ +T 200 500 3 10 1 1 0 6 1 +pinnumber=3 +T 200 800 5 10 0 0 0 6 1 +pinseq=3 +} +P 600 300 600 0 1 0 1 +{ +T 700 100 3 10 1 1 0 3 1 +pinnumber=1 +T 500 100 5 10 0 0 270 0 1 +pinseq=1 +} +T 300 700 8 10 0 0 0 0 1 +device=MGA82563 +P 900 400 900 0 1 0 1 +{ +T 1000 100 3 10 1 1 0 3 1 +pinnumber=2 +T 1000 100 5 10 0 0 90 0 1 +pinseq=2 +} +P 1200 500 1200 0 1 0 1 +{ +T 1300 100 3 10 1 1 0 3 1 +pinnumber=5 +T 1300 100 5 10 0 0 90 0 1 +pinseq=5 +} +L 200 1300 200 100 3 0 0 0 -1 -1 +L 200 100 1500 700 3 0 0 0 -1 -1 +L 1500 700 200 1300 3 0 0 0 -1 -1 +T 800 700 9 10 1 0 0 4 1 +MGA82563 diff --git a/usrp-hw/sym/nmos-sot23.sym b/usrp-hw/sym/nmos-sot23.sym new file mode 100644 index 000000000..435830e23 --- /dev/null +++ b/usrp-hw/sym/nmos-sot23.sym @@ -0,0 +1,54 @@ +v 20040111 1 +T 600 500 5 10 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 600 500 5 10 0 0 0 0 1 +numslots=0 +T 600 500 5 10 0 0 0 0 1 +description=generic N channel MOS transistor (enhancement type) +L 250 600 500 600 3 0 0 0 -1 -1 +L 250 200 500 200 3 0 0 0 -1 -1 +L 250 400 350 450 3 0 0 0 -1 -1 +L 250 400 350 350 3 0 0 0 -1 -1 +P 0 200 200 200 1 0 0 +{ +T 0 300 5 10 0 1 0 0 1 +pinnumber=1 +T 0 300 9 10 0 1 0 0 1 +pinlabel=1 +T 0 300 5 10 0 0 0 0 1 +pinseq=1 +T 0 300 5 10 0 0 0 0 1 +pintype=pass +} +P 500 600 500 800 1 0 1 +{ +T 300 700 5 10 0 1 0 0 1 +pinnumber=3 +T 300 700 9 10 0 1 0 0 1 +pinlabel=3 +T 300 700 5 10 0 0 0 0 1 +pinseq=3 +T 300 700 5 10 0 0 0 0 1 +pintype=pass +} +P 500 200 500 0 1 0 1 +{ +T 300 0 5 10 0 1 0 0 1 +pinnumber=2 +T 300 0 9 10 0 1 0 0 1 +pinlabel=2 +T 300 0 5 10 0 0 0 0 1 +pinseq=2 +T 300 0 5 10 0 0 0 0 1 +pintype=pass +} +T 700 600 8 10 1 1 0 0 1 +refdes=Q? +L 250 675 250 525 3 0 0 0 -1 -1 +L 250 475 250 325 3 0 0 0 -1 -1 +L 250 275 250 125 3 0 0 0 -1 -1 +L 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a/usrp-hw/sym/saw2400-SAWTEK855916.sym b/usrp-hw/sym/saw2400-SAWTEK855916.sym new file mode 100644 index 000000000..e207d6dfb --- /dev/null +++ b/usrp-hw/sym/saw2400-SAWTEK855916.sym @@ -0,0 +1,85 @@ +v 20040111 1 +T 51400 30100 8 10 1 1 0 6 1 +refdes=U? +T 50000 30050 9 10 1 0 0 0 2 +SAWTEK855916 +2.4 GHz +T 50000 30250 5 10 0 0 0 0 1 +device=SAWTEK855916 +T 50000 30450 5 10 0 0 0 0 1 +footprint=SAWTEK855916 +T 50000 30650 5 10 0 0 0 0 1 +author=mettus +T 50000 30850 5 10 0 0 0 0 1 +documentation=NA +T 50000 31050 5 10 0 0 0 0 1 +description=SAW Filter 2.4GHz +T 50000 31250 5 10 0 0 0 0 1 +numslots=0 +P 49700 29600 50000 29600 1 0 0 +{ +T 49900 29650 5 8 1 1 0 6 1 +pinnumber=2 +T 49900 29550 5 8 0 1 0 8 1 +pinseq=2 +T 50050 29600 9 8 1 1 0 0 1 +pinlabel=In +T 50050 29600 5 8 0 1 0 2 1 +pintype=in +} +P 50400 28900 50400 29200 1 0 0 +{ +T 50400 29050 5 8 1 1 0 6 1 +pinnumber=1 +T 50450 29100 5 8 0 1 90 8 1 +pinseq=1 +T 50350 29300 9 8 0 1 0 3 1 +pinlabel=GND +T 50400 29250 5 8 0 1 90 2 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000000000..c9f77f9c3 --- /dev/null +++ b/usrp-hw/sym/single-opamp.sym @@ -0,0 +1,46 @@ +v 20040111 1 +L 200 800 200 0 3 0 0 0 -1 -1 +L 200 800 800 400 3 0 0 0 -1 -1 +T 600 600 5 10 0 0 0 0 1 +device=OPERATIONAL_AMPLIFIER +L 800 400 200 0 3 0 0 0 -1 -1 +L 300 650 300 550 3 0 0 0 -1 -1 +L 250 600 350 600 3 0 0 0 -1 -1 +L 250 200 350 200 3 0 0 0 -1 -1 +P 0 600 200 600 1 0 0 +{ +T 0 600 5 10 1 1 0 0 1 +pinnumber=3 +T 0 600 5 10 0 1 0 0 1 +pinseq=3 +} +P 0 200 200 200 1 0 0 +{ +T 100 200 5 10 1 1 0 0 1 +pinnumber=2 +T 0 200 5 10 0 1 0 0 1 +pinseq=2 +} +P 800 400 1000 400 1 0 1 +{ +T 800 400 5 10 1 1 0 0 1 +pinnumber=6 +T 800 400 5 10 0 1 0 0 1 +pinseq=6 +} +P 500 600 500 800 1 0 1 +{ +T 500 700 5 10 1 1 0 0 1 +pinnumber=7 +T 500 700 5 10 1 1 0 0 1 +pinseq=7 +} +P 500 200 500 0 1 0 1 +{ +T 500 200 5 10 0 1 0 0 1 +pinseq=4 +T 500 100 5 10 1 1 0 0 1 +pinnumber=4 +} +T 700 600 8 10 1 1 0 0 1 +refdes=U? |