diff options
Diffstat (limited to 'usrp-hw/sym/generated/ep2c20-f484-IO1.src')
| -rw-r--r-- | usrp-hw/sym/generated/ep2c20-f484-IO1.src | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/usrp-hw/sym/generated/ep2c20-f484-IO1.src b/usrp-hw/sym/generated/ep2c20-f484-IO1.src new file mode 100644 index 000000000..079c87005 --- /dev/null +++ b/usrp-hw/sym/generated/ep2c20-f484-IO1.src @@ -0,0 +1,92 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=yes +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EP2C20-F484-IO1 +device=EP2C20-F484 +refdes=U? +footprint=FG484 +description=EP2C20 Cyclone II FPGA +documentation=http://www.altera.com +author=mettus +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +M1 clk clk r CLK2/LVDSCLK1P +M2 clk clk r CLK3/_LVDSCLK1N_ +M5 io line l IO/LVDS15P +M6 io line l IO/_LVDS15N_ +N1 io line l IO/LVDS14P +N2 io line l IO/_LVDS14N_ +P1 io line l IO/LVDS13P +P2 io line l IO/_LVDS13N_ +N6 io line l IO +P3 io line l IO/VREFB1N0 +N3 io line l IO/LVDS12P +N4 io line l IO/_LVDS12N_ +R8 io line l IO/LVDS11P +R7 io line l IO/_LVDS11N_ +P5 io line l IO/LVDS10P +P6 io line l IO/_LVDS10N_ +R1 io line l IO/LVDS9P +R2 io line l IO/_LVDS9N_ +T1 io line l IO/LVDS8P +T2 io line l IO/_LVDS8N_ +U1 io line l IO/LVDS7P +U2 io line l IO/_LVDS7N_ +R5 io line l IO/LVDS6P +R6 io line l IO/_LVDS6N_ +V1 io line l IO/LVDS5P +V2 io line l IO/_LVDS5N_ +T5 io line l IO/LVDS4P +T6 io line l IO/_LVDS4N_ +T3 io line l IO +U3 io line l IO/VREFB1N1 +W1 io line l IO/LVDS3P +W2 io line l IO/_LVDS3N_ +Y1 io line l IO/LVDS2P +Y2 io line l IO/_LVDS2N_ +W3 io line l IO/LVDS1P +W4 io line l IO/_LVDS1N_ +Y3 io line l IO/LVDS0P +Y4 io line l IO/_LVDS0N_ +W5 io line l IO +U4 io line l IO/PLL1\_OUTP +V4 io line l IO/_PLL1\_OUTN_ |