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+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# rotate_labels rotates the pintext of top and bottom pins
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)"
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=2800
+pinwidthvertikal=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20030525
+name=EP2C20-F484-IO2
+device=EP2C20-F484
+refdes=U?
+footprint=FG484
+description=EP2C20 Cyclone II FPGA
+documentation=http://www.altera.com
+author=mettus
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the Vcc or GND name
+# label represents the pinlabel.
+# negation lines can be added with _Q_
+# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+C4 io line r IO/ASDO
+C3 io line r IO/_nCSO_
+D3 io line r IO/LVDS26P/CRC\_ERROR
+D4 io line r IO/_LVDS26N_/CLKUSR
+D5 io line l IO/PLL3\_OUTP
+D6 io line l IO/_PLL3\_OUTN_
+E3 io line l IO/LVDS25P
+E4 io line l IO/_LVDS25N_
+C1 io line l IO/LVDS24P
+C2 io line l IO/_LVDS24N_
+F4 io line l IO/VREFB2N0
+G6 io line l IO/LVDS23P
+G5 io line l IO/_LVDS23N_
+F3 io line l IO
+D1 io line l IO/LVDS22P
+D2 io line l IO/_LVDS22N_
+G3 io line l IO/LVDS21P
+H4 io line l IO/_LVDS21N_
+H5 io line l IO/LVDS20P
+H6 io line l IO/_LVDS20N_
+E1 io line l IO/LVDS19P
+E2 io line l IO/_LVDS19N_
+F1 io line l IO/LVDS18P
+F2 io line l IO/_LVDS18N_
+H1 io line l IO/LVDS17P
+H2 io line l IO/_LVDS17N_
+L8 io line l IO
+H3 io line l IO/VREFB2N1
+J4 io line l IO
+J1 io line l IO/LVDS16P
+J2 io line l IO/_LVDS16N_
+L1 clk clk r CLK0/LVDSCLK0P
+L2 clk clk r CLK1/_LVDSCLK0N_