Import vests testsuite

463 files changed, 38391 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_01.vhd
new file mode 100644
index 0000000..9444ed8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_01.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_01 is
+
+end entity ap_a_01;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_01 is
+
+  signal clk : std_ulogic;
+
+begin
+
+  process (clk) is
+
+                  -- code from book
+
+                  -- end code from book
+
+  begin
+
+    if
+
+      -- code from book
+
+      clk'event and (To_X01(clk) = '1') and (To_X01(clk'last_value) = '0')
+
+      -- end code from book
+
+    then
+      report "rising edge on clk";
+    end if;
+
+  end process;
+
+  clk <= '0', '1' after 10 ns, '0' after 20 ns,
+         '1' after 30 ns, '0' after 40 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd
new file mode 100644
index 0000000..c7a4a5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_02 is
+
+end entity ap_a_02;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_02 is
+
+  -- code from book
+
+  -- end code from book
+
+begin
+
+  b1 : block is
+               signal sulv : std_ulogic_vector(7 downto 0);
+             signal slv : std_logic_vector(7 downto 0);
+  begin
+    -- code from book
+
+    sulv <= To_stdulogicvector ( slv );
+
+    -- end code from book
+    slv <= "10101010";
+  end block b1;
+
+  b2 : block is
+               signal sulv : std_ulogic_vector(7 downto 0);
+             signal slv : std_logic_vector(7 downto 0);
+  begin
+    -- code from book
+
+    slv <= To_stdlogicvector ( sulv );
+
+    -- end code from book
+    sulv <= "00001111";
+  end block b2;
+
+  b3 : block is
+               signal a, ena, y : std_logic;
+  begin
+    -- code from book
+
+    y <= a when ena = '1' else
+         'Z';
+
+    -- end code from book
+    ena <= '0', '1' after 20 ns, '0' after 40 ns;
+    a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
+  end block b3;
+
+  b4 : block is
+               signal a, ena, y : std_logic;
+  begin
+    -- code from book
+
+    y <= a when ena = '1' else
+         'H';
+
+    -- end code from book
+    ena <= '0', '1' after 20 ns, '0' after 40 ns;
+    a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
+  end block b4;
+
+  b5 : block is
+               signal a, b, x, s, y : std_logic;
+  begin
+    -- code from book
+
+    y <= a when x = '1' else
+         b when s = '1' else
+         '-';
+
+    -- end code from book
+    x <= '0', '1' after 20 ns, '0' after 40 ns;
+    s <= '0', '1' after 60 ns, '0' after 80 ns;
+    a <= '0', '1' after 10 ns, '0' after 30 ns,
+         '1' after 50 ns, '0' after 70 ns,
+         '1' after 90 ns;
+    b <= '0', '1' after 15 ns, '0' after 35 ns,
+         '1' after 55 ns, '0' after 75 ns,
+         '1' after 95 ns;
+  end block b5;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_03.vhd
new file mode 100644
index 0000000..87ddfbc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_03.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_03 is
+
+end entity ap_a_03;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.numeric_std.all;
+
+architecture test of ap_a_03 is
+begin
+
+  b1 : block is
+               -- code from book
+
+               type unsigned is array ( natural range <> ) of std_logic;
+             type signed is array ( natural range <> ) of std_logic;
+
+             -- end code from book
+  begin
+  end block b1;
+
+
+  b2 : block is
+               -- code from book
+
+               signal a: integer := 0;
+             signal b: signed (4 downto 0 );
+
+             -- end code from book
+  begin
+    a <= 0, 5 after 10 ns, -5 after 20 ns, 8 after 30 ns;
+    -- code from book
+
+    b <= To_signed ( a, b'length );
+
+    -- end code from book
+
+    process (b) is
+    begin
+
+      -- code from book
+
+      if std_match ( b, "0-000" ) then
+        -- . . .
+
+        -- end code from book
+        report "b matches";
+      else
+        report "b does not match";
+      end if;    
+    end process;
+
+    
+
+  end block b2;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_04.vhd
new file mode 100644
index 0000000..529feda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_04.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_04 is
+
+end entity ap_a_04;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_04 is
+
+  signal a, b, y : std_ulogic;
+
+begin
+
+  -- code from book
+
+  y <= a or b;
+
+  -- end code from book
+
+  a <= '0', '1' after 10 ns;
+  b <= '0', '1' after 5 ns, '0' after 10 ns, '1' after 15 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_05.vhd
new file mode 100644
index 0000000..c2b8470
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_05.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_05 is
+
+end entity ap_a_05;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_05 is
+
+  signal a, b, y, x : std_ulogic;
+
+begin
+
+  -- code from book
+
+  y <= a when x = '1' else
+       b;
+
+  -- end code from book
+
+  x <= '0', '1' after 20 ns;
+  a <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+  b <= '0', '1' after 15 ns, '0' after 25 ns, '1' after 35 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_06.vhd
new file mode 100644
index 0000000..43daac2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_06.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_06 is
+
+end entity ap_a_06;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_06 is
+
+  signal a, ts, x : std_ulogic;
+
+begin
+
+  -- code from book
+
+  ts <= a when x = '1' else
+        'Z';
+
+  -- end code from book
+
+  x <= '0', '1' after 20 ns;
+  a <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_07.vhd
new file mode 100644
index 0000000..d7481fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_07.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bidir_buffer is
+                 port ( bidir : inout std_logic_vector;
+                        ena : in std_ulogic;
+                        going_out : in std_ulogic_vector;
+                        coming_in : out std_ulogic_vector );
+               end entity bidir_buffer;
+
+--------------------------------------------------
+
+               architecture behavior of bidir_buffer is
+-- code from book
+
+                 constant hi_impedance : std_logic_vector(bidir'range) := (others => 'Z');
+                 -- . . .
+
+-- end code from book
+               begin
+-- code from book
+
+                 bidir <= To_stdlogicvector(going_out) when ena = '1' else
+                          hi_impedance;
+                 coming_in <= To_stdulogicvector(bidir);
+
+-- end code from book
+               end architecture behavior;
+
+
+
+               entity ap_a_07 is
+               end entity ap_a_07;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+               architecture test of ap_a_07 is
+
+                 signal bidir : std_logic_vector(3 downto 0);
+                 signal going_out, coming_in : std_ulogic_vector(3 downto 0);
+                 signal ena : std_ulogic;
+
+               begin
+
+                 dut : entity work.bidir_buffer
+                   port map ( bidir, ena, going_out, coming_in );
+
+                 ena <= '0', '1' after 10 ns, '0' after 30 ns;
+
+                 going_out <= "0000", "1111" after 20 ns;
+
+                 bidir <= "ZZZZ", "0000" after 40 ns, "1111" after 50 ns, "ZZZZ" after 60 ns;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_08.vhd
new file mode 100644
index 0000000..6d69213
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_08.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity entname is
+               end entity entname;
+
+
+
+               architecture rtl of entname is
+
+                 -- code from book
+
+                 subtype state_type is std_ulogic_vector(3 downto 0);
+                 constant s0 : state_type := "0001";
+                 constant s1 : state_type := "0010";
+                 constant s2 : state_type := "0100";
+                 constant s3 : state_type := "1000";
+
+                 -- end code from book
+
+                 signal state, next_state : state_type;
+                 signal con1, con2, con3 : std_ulogic;
+                 signal out1, out2 : std_ulogic;
+                 signal clk, reset : std_ulogic;
+
+               begin
+                 state_logic : process (state, con1, con2, con3) is
+                 begin
+                   case state is
+                     when s0 =>
+                       out1 <= '0';
+                       out2 <= '0';
+                       next_state <= s1; 
+                     when s1 =>
+                       out1 <= '1';
+                       if con1 = '1' then
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                     when s2 =>
+                       out2 <= '1';
+                       next_state <= s3;
+                     when s3 =>
+                       if con2 = '0' then
+                         next_state <= s3;
+                       elsif con3 = '0' then
+                         out1 <= '0';
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                     when others =>
+                       null;
+                   end case;
+                 end process state_logic;
+
+                 state_register : process (clk, reset) is
+                 begin
+                   if reset = '0' then
+                     state <= s0;
+                   elsif rising_edge(clk) then
+                     state <= next_state;
+                   end if;
+                 end process state_register;
+
+
+                 clk_gen : process is
+                 begin
+                   clk <= '0', '1' after 10 ns;
+                   wait for 20 ns;
+                 end process clk_gen;
+
+                 reset <= '0', '1' after 40 ns;
+
+                 con1 <= '0', '1' after 100 ns, '0' after 120 ns;
+
+                 con2 <= '0', '1' after 160 ns;
+
+                 con3 <= '0', '1' after 220 ns;
+
+
+               end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd
new file mode 100644
index 0000000..52e558c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_09 is
+
+end entity ap_a_09;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_09 is
+
+  signal a, b, c, d : integer := 0;
+
+begin
+
+  b1 : block is
+               signal y : integer;
+  begin
+    -- code from book
+
+    y <= a + b + c + d;
+
+    -- end code from book
+  end block b1;
+
+  b2 : block is
+               signal y : integer;
+  begin
+    -- code from book
+
+    y <= ( a + b ) + ( c + d );
+
+    -- end code from book
+  end block b2;
+
+  stimulus : process is
+  begin
+    a <= 1; wait for 10 ns;
+    b <= 2; wait for 10 ns;
+    c <= 3; wait for 10 ns;
+    d <= 4; wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_10.vhd
new file mode 100644
index 0000000..198029e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_10.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_10 is
+end entity ap_a_10;
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+library stimulus;  
+use stimulus.stimulus_generators.all;
+
+architecture test of ap_a_10 is
+
+  signal a, b, c, d : std_ulogic;
+  signal test_vector : std_ulogic_vector(1 to 4);
+
+begin
+
+  b1 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book
+
+    y <= a or b or c or d;
+
+    -- end code from book
+  end block b1;
+
+  b2 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book
+
+    y <= ( a or b ) or ( c or d );
+
+    -- end code from book
+  end block b2;
+
+  b3 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book (syntax error)
+
+    -- y <= a or b or c and d;
+
+    -- end code from book
+  end block b3;
+
+  b4 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book
+
+    y <= ( a or b ) or ( c and d );
+
+    -- end code from book
+  end block b4;
+
+  stimulus : all_possible_values(test_vector, 10 ns);
+
+  (a, b, c, d) <= test_vector;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_01.vhd
new file mode 100644
index 0000000..9b7c90a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_01.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_01 is
+end entity fg_a_01;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_01 is
+
+  signal clk, d : std_ulogic;
+
+begin
+
+  stimulus : process is
+  begin
+    clk <= '0';  d <= '0';  wait for 10 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    d <= '1';  wait for 10 ns;
+    clk <= '1', '0' after 20 ns;  d <= '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+
+  b1 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process (clk) is
+    begin
+      if rising_edge(clk) then
+        q <= d;
+      end if;
+    end process;
+
+    -- end code from book
+
+  end block b1;
+
+
+  b2 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process is
+    begin
+      wait until rising_edge(clk);
+      q <= d;
+    end process;
+
+    -- end code from book
+
+  end block b2;
+
+
+  b3 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    q <= d when rising_edge(clk) else
+         q;
+
+    -- end code from book
+
+  end block b3;
+
+
+  b4 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    b : block ( rising_edge(clk)
+                and not clk'stable ) is
+    begin
+      q <= guarded d;
+    end block b;
+
+    -- end code from book
+
+  end block b4;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_02.vhd
new file mode 100644
index 0000000..f603f5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_02.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_02 is
+
+end entity fg_a_02;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_02 is
+
+  signal clk, a, b : std_ulogic;
+
+begin
+
+  stimulus : process is
+  begin
+    clk <= '0';  a <= '0';  b <= '0';  wait for 10 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    b <= '1';  wait for 10 ns;
+    clk <= '1', '0' after 20 ns;  a <= '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+
+  b1 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process (clk) is
+                    variable d : std_ulogic;
+    begin
+      if a = b then
+        d := '1';
+      else
+        d := '0';
+      end if;
+      if rising_edge(clk) then
+        q <= d;
+      end if;
+    end process;
+
+    -- end code from book
+
+  end block b1;
+
+
+
+  b2 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process (clk) is
+    begin
+      if rising_edge(clk) then
+        if a = b then
+          q <= '1';
+        else
+          q <= '0';
+        end if;
+      end if;
+    end process;
+
+    -- end code from book
+
+  end block b2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_03.vhd
new file mode 100644
index 0000000..d3a6af0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_03.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity add_and_sub is
+                 port ( a, b, c : in natural;
+                        y : out natural;
+                        ovf : out std_ulogic );
+               end entity add_and_sub;
+
+--------------------------------------------------
+
+               library ieee;  use ieee.numeric_std.all;
+
+               architecture rtl of add_and_sub is
+                 signal stage2, stage3 : unsigned ( 8 downto 0 );
+               begin
+                 stage2 <= To_unsigned(a, 9) + to_unsigned(b, 9);  -- "+" from numeric_std
+                 stage3 <= stage2 - c;              -- "-" from numeric_std
+                 y <= To_integer(stage3) ;
+                 ovf <= stage3(8);
+               end rtl;
+
+-- end code from book
+
+
+
+               entity fg_a_03 is
+               end entity fg_a_03;
+
+
+               library ieee;
+               use ieee.std_logic_1164.all, ieee.numeric_std.all;
+
+               architecture test of fg_a_03 is
+
+                 signal a, b, c, y : natural := 0;
+                 signal ovf : std_ulogic;
+
+               begin
+
+                 dut : entity work.add_and_sub
+                   port map ( a, b, c, y, ovf );
+
+                 stimulus : process is
+                 begin
+                   wait for 10 ns;
+                   a <= 2;  b <= 5;  c <= 3;  wait for 10 ns;
+                   a <= 192;  b <= 192;  wait for 10 ns;
+                   a <= 10;  b <= 11;  c <= 22;  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_04.vhd
new file mode 100644
index 0000000..1e1da2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_04.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_04 is
+
+end entity fg_a_04;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_04 is
+
+  signal clk, reset, d, q, q_n : std_ulogic;
+
+begin
+
+  -- code from book
+
+  ff1 : process (reset, clk) is
+  begin
+    if reset = '1' then
+      q <= '0';
+    elsif rising_edge(clk) then
+      q <= d;
+    end if;
+  end process ff1;
+
+  q_n <= not q;
+
+  -- end code from book
+
+  stimulus : process is
+  begin
+    reset <= '0';  clk <= '0';  d <= '1';  wait for 10 ns;
+    reset <= '1', '0' after 30 ns;
+    clk <= '1' after 10 ns, '0' after 20 ns;
+    wait for 40 ns;
+    clk <= '1', '0' after 20 ns;
+    d <= '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_05.vhd
new file mode 100644
index 0000000..7304b82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_05.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_05 is
+
+end entity fg_a_05;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_05 is
+
+  signal clk, reset, a, b, x, q : std_ulogic;
+
+begin
+
+  -- code from book
+
+  ff2 : process (reset, clk) is
+  begin
+    if reset = '1' then
+      q <= '0';
+    elsif rising_edge(clk) then
+      if x = '1' then
+        q <= a;
+      else
+        q <= b;
+      end if;
+    end if;
+  end process ff2;
+
+  -- end code from book
+
+  stimulus : process is
+  begin
+    reset <= '0';  clk <= '0';  x <= '1'; a <= '1'; b <= '0';  wait for 10 ns;
+    reset <= '1', '0' after 30 ns;
+    clk <= '1' after 10 ns, '0' after 20 ns;
+    wait for 40 ns;
+    clk <= '1', '0' after 2 ns,
+           '1' after 12 ns, '0' after 14 ns,
+           '1' after 17 ns, '0' after 19 ns,
+           '1' after 22 ns, '0' after 24 ns,
+           '1' after 27 ns, '0' after 29 ns,
+           '1' after 32 ns, '0' after 34 ns,
+           '1' after 37 ns, '0' after 39 ns,
+           '1' after 42 ns, '0' after 44 ns,
+           '1' after 47 ns, '0' after 49 ns;
+    a <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
+    b <= '0' after 15 ns, '1' after 25 ns, '0' after 35 ns, '1' after 45 ns;
+    x <= '0' after 30 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd
new file mode 100644
index 0000000..bc62919
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_06 is
+
+end entity fg_a_06;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_06 is
+
+  -- code from book
+
+  constant terminal_count : integer := 2**6 - 1;
+  subtype counter_range is integer range 0 to terminal_count;
+  signal count : counter_range;
+  -- . . .
+
+  -- end code from book
+
+  signal clk, reset : std_ulogic;
+
+begin
+
+  -- code from book
+
+  counter6 : process (reset, clk)
+  begin
+    if reset = '0' then
+      count <= 0;
+    elsif rising_edge(clk) then
+      if count < terminal_count then
+        count <= count + 1;
+      else
+        count <= 0;
+      end if;
+    end if;
+  end process counter6;
+
+  -- end code from book
+
+  stimulus : process is
+  begin
+    reset <= '1';  clk <= '0';  wait for 10 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    reset <= '0', '1' after 30 ns;
+    clk <= '1' after 10 ns, '0' after 20 ns;
+    wait for 40 ns;
+    for i in 1 to terminal_count + 10 loop
+      clk <= '1', '0' after 10 ns;
+      wait for 20 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd
new file mode 100644
index 0000000..ebf0574
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bidir_buffer is
+                 port ( bidir : inout std_logic;
+                        ena : in std_ulogic;
+                        going_out : in std_ulogic;
+                        coming_in : out std_ulogic );
+               end entity bidir_buffer;
+
+--------------------------------------------------
+
+               architecture behavior of bidir_buffer is
+               begin
+                 bidir <= going_out when ena = '1' else
+                          'Z';
+                 coming_in <= bidir;
+               end architecture behavior;
+
+-- end code from book
+
+
+
+               entity fg_a_07 is
+               end entity fg_a_07;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               architecture test of fg_a_07 is
+
+                 signal bidir : std_logic;
+                 signal ena, going_out, coming_in : std_ulogic;
+
+               begin
+
+                 dut : entity work.bidir_buffer
+                   port map ( bidir, ena, going_out, coming_in );
+
+                 ena <= '0', '1' after 10 ns, '0' after 30 ns;
+
+                 going_out <= '0', '1' after 20 ns;
+
+                 bidir <= 'Z', '0' after 40 ns, '1' after 50 ns, 'Z' after 60 ns;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_08.vhd
new file mode 100644
index 0000000..f11d4fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_08.vhd
@@ -0,0 +1,105 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity entname is
+               end entity entname;
+
+-- end not in book
+
+
+               architecture rtl of entname is
+
+                 type state_type is (s0, s1, s2, s3);
+                 signal state, next_state : state_type;
+                 signal con1, con2, con3 : std_ulogic;
+                 signal out1, out2 : std_ulogic;
+                 signal clk, reset : std_ulogic;
+                 -- . . .
+
+               begin
+                 state_logic : process (state, con1, con2, con3) is
+                 begin
+                   case state is
+                     when s0 =>
+                       out1 <= '0';
+                       out2 <= '0';
+                       next_state <= s1; 
+                     when s1 =>
+                       out1 <= '1';
+                       if con1 = '1' then
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                     when s2 =>
+                       out2 <= '1';
+                       next_state <= s3;
+                     when s3 =>
+                       if con2 = '0' then
+                         next_state <= s3;
+                       elsif con3 = '0' then
+                         out1 <= '0';
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                   end case;
+                 end process state_logic;
+
+                 state_register : process (clk, reset) is
+                 begin
+                   if reset = '0' then
+                     state <= s0;
+                   elsif rising_edge(clk) then
+                     state <= next_state;
+                   end if;
+                 end process state_register;
+
+                 -- . . .
+
+                 -- not in book
+
+                 clk_gen : process is
+                 begin
+                   clk <= '0', '1' after 10 ns;
+                   wait for 20 ns;
+                 end process clk_gen;
+
+                 reset <= '0', '1' after 40 ns;
+
+                 con1 <= '0', '1' after 100 ns, '0' after 120 ns;
+
+                 con2 <= '0', '1' after 160 ns;
+
+                 con3 <= '0', '1' after 220 ns;
+
+                 -- end not in book
+
+               end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_09.vhd
new file mode 100644
index 0000000..1baf1da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_09.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_09.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_09 is
+end entity fg_a_09;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_09 is
+
+  signal clk25M, resetl : std_ulogic;
+  signal data, odat : std_ulogic_vector(7 downto 0);
+
+begin
+
+  -- code from book
+
+  wrong_way : process ( clk25M, resetl, data )
+  begin
+    if resetl = '0' then
+      odat <= B"0000_0000";
+    elsif rising_edge(clk25M) then
+      odat <= data;
+    elsif data = B"0000_0000" then
+      odat <= B"0000_0001";
+    end if;
+  end process wrong_way;
+
+  -- end code from book
+
+  data <= odat(6 downto 0) & '0';
+
+  clk_gen : process is
+  begin
+    clk25M <= '0', '1' after 10 ns;
+    wait for 20 ns;
+  end process clk_gen;
+
+  resetl <= '1', '0' after 20 ns, '1' after 60 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_10.vhd
new file mode 100644
index 0000000..064d6c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_10.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_10.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_10 is
+end entity fg_a_10;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_10 is
+
+  signal clk25M, resetl : std_ulogic;
+  signal data, odat : std_ulogic_vector(7 downto 0);
+
+begin
+
+  -- code from book
+
+  right_way : process ( clk25M, resetl )
+  begin
+    if resetl = '0' then
+      odat <= B"0000_0000";
+    elsif rising_edge(clk25M) then
+      if data = B"0000_0000" then
+        odat <= B"0000_0001";
+      else
+        odat <= data;
+      end if;
+    end if;
+  end process right_way;
+
+  -- end code from book
+
+  data <= odat(6 downto 0) & '0';
+
+  clk_gen : process is
+  begin
+    clk25M <= '0', '1' after 10 ns;
+    wait for 20 ns;
+  end process clk_gen;
+
+  resetl <= '1', '0' after 20 ns, '1' after 60 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd
new file mode 100644
index 0000000..cb4887d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_11.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity RAM16x1 is
+                 port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
+                        \d\, \we\ : in std_ulogic;
+                        \o\ : out std_ulogic );
+               end entity RAM16x1;
+
+
+               architecture a of RAM16x1 is
+               begin
+               end architecture a;
+
+
+
+               entity fg_a_11 is
+               end entity fg_a_11;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               architecture test of fg_a_11 is
+
+                 -- code from book
+
+                 component RAM16x1 is
+                                     port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
+                                            \d\, \we\ : in std_ulogic;
+                                            \o\ : out std_ulogic );
+                 end component RAM16x1;
+                 -- . . .
+
+                 -- end code from book
+
+                 signal address : std_ulogic_vector(3 downto 0);
+                 signal raminp, ramout : std_ulogic_vector(15 downto 0);
+                 signal write_enable : std_ulogic;
+
+               begin
+
+                 -- code from book
+
+                 g1 : for i in 0 to 15 generate
+                   rama : component RAM16x1
+                     port map ( \a<0>\ => address(0),
+                                \a<1>\ => address(1),
+                                \a<2>\ => address(2),
+                                \a<3>\ => address(3),
+                                \d\ => raminp ( i ),
+                                \we\ => write_enable,
+                                \o\ => ramout ( i ) );
+                 end generate g1;
+
+                 -- end code from book
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic.vhd
new file mode 100644
index 0000000..064ff92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_arithmetic.vhd,v 1.2 2001-10-25 01:24:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------------
+--
+--  Bit-vector arithmetic package interface.
+--  
+--  Does arithmetic and logical operations on bit vectors, treating them
+--  as either unsigned or signed (two's complement) integers.  Leftmost bit
+--  is most-significant or sign bit, rightmost bit is least-significant
+--  bit.  Dyadic operations need the two arguments to be of the same
+--  length; however, their index ranges and directions may differ.  Results
+--  must be of the same length as the operands.
+--  
+--------------------------------------------------------------------------
+
+package bv_arithmetic is
+
+  function bv_to_natural ( bv : in bit_vector ) return natural;
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector;
+
+  function bv_to_integer ( bv : in bit_vector ) return integer;
+
+  function integer_to_bv ( int : in integer;
+      	      	      	   length : in natural ) return bit_vector;
+
+  procedure bv_add ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean );
+
+  function "+" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_sub ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean );
+
+  function "-" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_addu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean );
+
+  function bv_addu ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_subu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean );
+
+  function bv_subu ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_neg ( bv : in bit_vector;
+                     bv_result : out bit_vector;
+                     overflow : out boolean );
+
+  function "-" ( bv : in bit_vector ) return bit_vector;
+
+  procedure bv_mult ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean );
+
+  function "*" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_multu ( bv1, bv2 : in bit_vector;
+      	       	       bv_result : out bit_vector;
+		       overflow : out boolean );
+
+  function bv_multu ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_div ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     div_by_zero : out boolean;
+                     overflow : out boolean );
+
+  function "/" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      bv_remainder : out bit_vector;
+		      div_by_zero : out boolean );
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      div_by_zero : out boolean );
+
+  function bv_divu ( bv1, bv2 : in bit_vector )  return bit_vector;
+
+  function bv_lt ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_le ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_gt ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_ge ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_sext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector;
+
+  function bv_zext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector;
+
+end package bv_arithmetic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd
new file mode 100644
index 0000000..41267bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd
@@ -0,0 +1,647 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_arithmetic_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package body bv_arithmetic is
+
+  ----------------------------------------------------------------
+  --  Type conversions
+  ----------------------------------------------------------------
+
+  function bv_to_natural ( bv : in bit_vector ) return natural is
+
+    variable result : natural := 0;
+
+  begin
+    for index in bv'range loop
+      result := result * 2 + bit'pos( bv(index) );
+    end loop;
+    return result;
+  end function bv_to_natural;
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : natural := nat;
+    variable result : bit_vector(length - 1 downto 0) := (others => '0');
+
+  begin
+    for index in result'reverse_range loop
+      result(index) := bit'val( temp rem 2 );
+      temp := temp / 2;
+      exit when temp = 0;
+    end loop;
+    return result;
+  end function natural_to_bv;
+
+  function bv_to_integer ( bv : in bit_vector ) return integer is
+
+    variable temp : bit_vector(bv'range);
+    variable result : integer := 0;
+
+  begin
+    if bv(bv'left) = '1' then	  -- negative number
+      temp := not bv;
+    else
+      temp := bv;
+    end if;
+    for index in bv'range loop	  -- sign bit of temp = '0'
+      result := result * 2 + bit'pos( temp(index) );
+    end loop;
+    if bv(bv'left) = '1' then
+      result := (-result) - 1;
+    end if;
+    return result;
+  end function bv_to_integer;
+
+  function integer_to_bv ( int : in integer;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : integer;
+    variable result : bit_vector(length - 1 downto 0) := (others => '0');
+
+  begin
+    if int < 0 then
+      temp := - (int + 1);
+    else
+      temp := int;
+    end if;
+    for index in result'reverse_range loop
+      result(index) := bit'val( temp rem 2 );
+      temp := temp / 2;
+      exit when temp = 0;
+    end loop;
+    if int < 0 then
+      result := not result;
+      result(result'left) := '1';
+    end if;
+    return result;
+  end function integer_to_bv;
+
+  ----------------------------------------------------------------
+  --  Arithmetic operations
+  ----------------------------------------------------------------
+
+  procedure bv_add ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_add: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor op2(index) xor carry_in;
+        carry_out := (op1(index) and op2(index))
+                     or (carry_in and (op1(index) xor op2(index)));
+      end loop;
+      bv_result := result;
+      overflow := carry_out /= carry_in;
+    end if;
+  end procedure bv_add;
+
+  function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report """+"": operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor op2(index) xor carry_in;
+        carry_out := (op1(index) and op2(index))
+                     or (carry_in and (op1(index) xor op2(index)));
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+  procedure bv_sub ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean ) is
+
+    -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '1';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_sub: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor (not op2(index)) xor carry_in;
+        carry_out := (op1(index) and (not op2(index)))
+                     or (carry_in and (op1(index) xor (not op2(index))));
+      end loop;
+      bv_result := result;
+      overflow := carry_out /= carry_in;
+    end if;
+  end procedure bv_sub;
+
+  function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '1';
+
+  begin
+    if bv1'length /= bv2'length then
+      report """-"": operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor (not op2(index)) xor carry_in;
+        carry_out := (op1(index) and (not op2(index)))
+                     or (carry_in and (op1(index) xor (not op2(index))));
+      end loop;
+    end if;
+    return result;
+  end function "-";
+
+  procedure bv_addu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_addu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor carry;
+        carry := (op1(index) and op2(index))
+                 or (carry and (op1(index) xor op2(index)));
+      end loop;
+      bv_result := result;
+      overflow := carry = '1';
+    end if;
+  end procedure bv_addu;
+
+  function bv_addu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "bv_addu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor carry;
+        carry := (op1(index) and op2(index))
+                 or (carry and (op1(index) xor op2(index)));
+      end loop;
+    end if;
+    return result;
+  end function bv_addu;
+
+  procedure bv_subu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable borrow : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_subu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor borrow;
+        borrow := (not op1(index) and op2(index))
+                  or (borrow and not (op1(index) xor op2(index)));
+      end loop;
+      bv_result := result;
+      overflow := borrow = '1';
+    end if;
+  end procedure bv_subu;
+
+  function bv_subu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable borrow : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "bv_subu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor borrow;
+        borrow := (not op1(index) and op2(index))
+                  or (borrow and not (op1(index) xor op2(index)));
+      end loop;
+    end if;
+    return result;
+  end function bv_subu;
+
+  procedure bv_neg ( bv : in bit_vector;
+                     bv_result : out bit_vector;
+                     overflow : out boolean ) is
+
+    constant zero : bit_vector(bv'range) := (others => '0');
+
+  begin
+    bv_sub( zero, bv, bv_result, overflow );
+  end procedure bv_neg;
+
+
+  function "-" ( bv : in bit_vector ) return bit_vector is
+
+    constant zero : bit_vector(bv'range) := (others => '0');
+
+  begin
+    return zero - bv;
+  end function "-";
+
+  procedure bv_mult ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean ) is
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable multu_result : bit_vector(bv1'range);
+    variable multu_overflow : boolean;
+    variable abs_min_int : bit_vector(bv1'range) := (others => '0');
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_mult: operands of different lengths"
+        severity failure;
+    else
+      abs_min_int(bv1'left) := '1';
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      bv_multu(op1, op2, multu_result, multu_overflow);
+      if negative_result then
+        overflow := multu_overflow or (multu_result > abs_min_int);
+        bv_result := - multu_result;
+      else
+        overflow := multu_overflow or (multu_result(multu_result'left) = '1');
+        bv_result := multu_result;
+      end if;
+    end if;
+  end procedure bv_mult;
+
+  function "*" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable result : bit_vector(bv1'range);
+
+  begin
+    if bv1'length /= bv2'length then
+      report """*"": operands of different lengths"
+        severity failure;
+    else
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      result := bv_multu(op1, op2);
+      if negative_result then
+        result := - result;
+      end if;
+    end if;
+    return result;
+  end function "*";
+
+  procedure bv_multu ( bv1, bv2 : in bit_vector;
+      	       	       bv_result : out bit_vector;
+		       overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    constant len : natural := bv1'length;
+    constant accum_len : natural := len * 2;
+    variable accum : bit_vector(accum_len - 1 downto 0) := (others => '0');
+    constant zero : bit_vector(accum_len - 1 downto len):= (others => '0');
+    variable addu_overflow : boolean;
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_multu: operands of different lengths"
+        severity failure;
+    else
+      for count in 0 to len - 1 loop
+        if op2(count) = '1' then
+          bv_addu( accum(count + len - 1 downto count), op1,
+                   accum(count + len - 1 downto count), addu_overflow);
+          accum(count + len) := bit'val(boolean'pos(addu_overflow));
+        end if;
+      end loop;
+      bv_result := accum(len - 1 downto 0);
+      overflow := accum(accum_len-1 downto len) /= zero;
+    end if;
+  end procedure bv_multu;
+
+  function bv_multu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    -- Use bv_multu with overflow detection, but ignore overflow flag
+
+    variable result : bit_vector(bv1'range);
+    variable tmp_overflow : boolean;
+
+  begin
+    bv_multu(bv1, bv2, result, tmp_overflow);
+    return result;
+  end function bv_multu;
+
+  procedure bv_div ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     div_by_zero : out boolean;
+                     overflow : out boolean ) is
+
+    --  Need overflow, in case divide b"10...0" (min_int) by -1
+    --  Don't use bv_to_int, in case size bigger than host machine!
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable divu_result : bit_vector(bv1'range);
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_div: operands of different lengths"
+        severity failure;
+    else
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      bv_divu(op1, op2, divu_result, div_by_zero);
+      if negative_result then
+        overflow := false;
+        bv_result := - divu_result;
+      else
+        overflow := divu_result(divu_result'left) = '1';
+        bv_result := divu_result;
+      end if;
+    end if;
+  end procedure bv_div;
+
+  function "/" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable result : bit_vector(bv1'range);
+
+  begin
+    if bv1'length /= bv2'length then
+      report """/"": operands of different lengths"
+        severity failure;
+    else
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      result := bv_divu(op1, op2);
+      if negative_result then
+        result := - result;
+      end if;
+    end if;
+    return result;
+  end function "/";
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      bv_remainder : out bit_vector;
+		      div_by_zero : out boolean ) is
+
+    constant len : natural := bv1'length;
+    constant zero_divisor : bit_vector(len-1 downto 0) := (others => '0');
+    alias dividend : bit_vector(bv1'length-1 downto 0) is bv1;
+    variable divisor : bit_vector(bv2'length downto 0) := '0' & bv2;
+    variable quotient : bit_vector(len-1 downto 0);
+    variable remainder : bit_vector(len downto 0) := (others => '0');
+    variable ignore_overflow  : boolean;
+
+  begin
+    if bv1'length /= bv2'length
+      or bv1'length /= bv_quotient'length or bv1'length /= bv_remainder'length then
+      report "bv_divu: operands of different lengths"
+        severity failure;
+    else
+      --  check for zero divisor
+      if bv2 = zero_divisor then
+        div_by_zero := true;
+        return;
+      end if;
+      --  perform division
+      for iter in len-1 downto 0 loop
+        if remainder(len) = '0' then
+          remainder := remainder sll 1;
+          remainder(0) := dividend(iter);
+          bv_sub(remainder, divisor, remainder, ignore_overflow);
+        else
+          remainder := remainder sll 1;
+          remainder(0) := dividend(iter);
+          bv_add(remainder, divisor, remainder, ignore_overflow);
+        end if;
+        quotient(iter) := not remainder(len);
+      end loop;
+      if remainder(len) = '1' then
+        bv_add(remainder, divisor, remainder, ignore_overflow);
+      end if;
+      bv_quotient := quotient;
+      bv_remainder := remainder(len - 1 downto 0);
+      div_by_zero := false;
+    end if;
+  end procedure bv_divu;
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      div_by_zero : out boolean ) is
+
+    variable ignore_remainder : bit_vector(bv_quotient'range);
+
+  begin
+    bv_divu(bv1, bv2, bv_quotient, ignore_remainder, div_by_zero);
+  end procedure bv_divu;
+
+  function bv_divu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    variable result : bit_vector(bv1'range);
+    variable tmp_div_by_zero : boolean;
+
+  begin
+    bv_divu(bv1, bv2, result, tmp_div_by_zero);
+    return result;
+  end function bv_divu;
+
+  ----------------------------------------------------------------
+  --  Arithmetic comparison operators.
+  --  Perform comparisons on bit vector encoded signed integers.
+  --  (For unsigned integers, built in lexical comparison does
+  --  the required operation.)
+  ----------------------------------------------------------------
+
+  function bv_lt ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_lt: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 < tmp2;
+  end function bv_lt;
+
+  function bv_le ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_le: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 <= tmp2;
+  end function bv_le;
+
+  function bv_gt ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_gt: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 > tmp2;
+  end function bv_gt;
+
+  function bv_ge ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_ged: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 >= tmp2;
+  end function bv_ge;
+
+  ----------------------------------------------------------------
+  --  Extension operators - convert a bit vector to a longer one
+  ----------------------------------------------------------------
+
+  function bv_sext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector is
+
+    alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
+    variable result : bit_vector(length - 1 downto 0) := (others => bv(bv'left));
+    variable src_length : natural := bv'length;
+
+  begin
+    if src_length > length then
+      src_length := length;
+    end if;
+    result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
+    return result;
+  end function bv_sext;
+
+  function bv_zext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector is
+
+    alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
+    variable result : bit_vector(length - 1 downto 0) := (others => '0');
+    variable src_length : natural := bv'length;
+
+  begin
+    if src_length > length then
+      src_length := length;
+    end if;
+    result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
+    return result;
+  end function bv_zext;
+
+end package body bv_arithmetic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_images.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images.vhd
new file mode 100644
index 0000000..435d504
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_images.vhd,v 1.2 2001-10-25 01:24:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------------
+--
+--  bv_images package specification.
+--
+--  Functions that return the string image of values.
+--  Each image is a correctly formed literal according to the
+--  rules of VHDL-93.
+--
+--------------------------------------------------------------------------
+
+package bv_images is
+
+  -- Image of bit vector as binary bit string literal
+  -- (in the format B"...")
+  -- Length of result is bv'length + 3
+
+  function image (bv : in bit_vector) return string;
+
+  -- Image of bit vector as octal bit string literal
+  -- (in the format O"...")
+  -- Length of result is (bv'length+2)/3 + 3
+
+  function image_octal (bv : in bit_vector) return string;
+
+  -- Image of bit vector as hex bit string literal
+  -- (in the format X"...")
+  -- Length of result is (bv'length+3)/4 + 3
+
+  function image_hex (bv : in bit_vector) return string;
+
+end bv_images;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_images_body.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images_body.vhd
new file mode 100644
index 0000000..285bb55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images_body.vhd
@@ -0,0 +1,168 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_images_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------------
+--
+--  bv_images package body.
+--
+--  Functions that return the string image of values.
+--  Each image is a correctly formed literal according to the
+--  rules of VHDL-93.
+--
+--------------------------------------------------------------------------
+
+package body bv_images is
+
+
+  -- Image of bit vector as binary bit string literal
+  -- (in the format B"...")
+  -- Length of result is bv'length + 3
+
+  function image (bv : in bit_vector) return string is
+
+    alias bv_norm : bit_vector(1 to bv'length) is bv;
+    variable result : string(1 to bv'length + 3);
+
+  begin
+    result(1) := 'B';
+    result(2) := '"';
+    for index in bv_norm'range loop
+      if bv_norm(index) = '0' then
+        result(index + 2) := '0';
+      else
+        result(index + 2) := '1';
+      end if;
+    end loop;
+    result(bv'length + 3) := '"';
+    return result;
+  end image;
+
+  ----------------------------------------------------------------
+
+  -- Image of bit vector as octal bit string literal
+  -- (in the format O"...")
+  -- Length of result is (bv'length+2)/3 + 3
+
+  function image_octal (bv : in bit_vector) return string is
+
+    constant nr_digits : natural := (bv'length + 2) / 3;
+    variable result : string(1 to nr_digits + 3);
+    variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0');
+    variable three_bits : bit_vector(0 to 2);
+    variable digit : character;
+
+  begin
+    result(1) := 'O';
+    result(2) := '"';
+    bits(bits'right - bv'length + 1 to bits'right) := bv;
+    for index in 0 to nr_digits - 1 loop
+      three_bits := bits(3*index to 3*index + 2);
+      case three_bits is
+	when b"000" =>
+	  digit := '0';
+	when b"001" =>
+	  digit := '1';
+	when b"010" =>
+	  digit := '2';
+	when b"011" =>
+	  digit := '3';
+	when b"100" =>
+	  digit := '4';
+	when b"101" =>
+	  digit := '5';
+	when b"110" =>
+	  digit := '6';
+	when b"111" =>
+	  digit := '7';
+      end case;
+      result(index + 3) := digit;
+    end loop;
+    result(nr_digits + 3) := '"';
+    return result;
+  end image_octal;
+
+  ----------------------------------------------------------------
+
+  -- Image of bit vector as hex bit string literal
+  -- (in the format X"...")
+  -- Length of result is (bv'length+3)/4 + 3
+
+  function image_hex (bv : in bit_vector) return string is
+
+    constant nr_digits : natural := (bv'length + 3) / 4;
+    variable result : string(1 to nr_digits + 3);
+    variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0');
+    variable four_bits : bit_vector(0 to 3);
+    variable digit : character;
+
+  begin
+    result(1) := 'X';
+    result(2) := '"';
+    bits(bits'right - bv'length + 1 to bits'right) := bv;
+    for index in 0 to nr_digits - 1 loop
+      four_bits := bits(4*index to 4*index + 3);
+      case four_bits is
+	when b"0000" =>
+	  digit := '0';
+	when b"0001" =>
+	  digit := '1';
+	when b"0010" =>
+	  digit := '2';
+	when b"0011" =>
+	  digit := '3';
+	when b"0100" =>
+	  digit := '4';
+	when b"0101" =>
+	  digit := '5';
+	when b"0110" =>
+	  digit := '6';
+	when b"0111" =>
+	  digit := '7';
+	when b"1000" =>
+	  digit := '8';
+	when b"1001" =>
+	  digit := '9';
+	when b"1010" =>
+	  digit := 'A';
+	when b"1011" =>
+	  digit := 'B';
+	when b"1100" =>
+	  digit := 'C';
+	when b"1101" =>
+	  digit := 'D';
+	when b"1110" =>
+	  digit := 'E';
+	when b"1111" =>
+	  digit := 'F';
+      end case;
+      result(index + 3) := digit;
+    end loop;
+    result(nr_digits + 3) := '"';
+    return result;
+  end image_hex;
+
+
+end bv_images;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_07.vhd
new file mode 100644
index 0000000..557661e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_07.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_07.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity reg4 is
+  port ( d0, d1, d2, d3, en, clk : in bit;
+         q0, q1, q2, q3 : out  bit );
+end entity reg4;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd
new file mode 100644
index 0000000..cfd5862
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behav of reg4 is
+begin
+
+  storage : process is
+                      variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
+  begin 
+    if en = '1' and clk = '1' then
+      stored_d0 := d0;
+      stored_d1 := d1;
+      stored_d2 := d2;
+      stored_d3 := d3;
+    end if;
+    q0 <= stored_d0 after 5 ns;
+    q1 <= stored_d1 after 5 ns;
+    q2 <= stored_d2 after 5 ns;
+    q3 <= stored_d3 after 5 ns;
+    wait on d0, d1, d2, d3, en, clk;
+  end process storage;
+
+end architecture behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_10.vhd
new file mode 100644
index 0000000..6f53a63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_10.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity d_latch is
+  port ( d, clk : in bit;  q : out bit );
+end d_latch;
+
+
+entity and2 is
+  port ( a, b : in bit;  y : out bit );
+end and2;
+
+
+architecture basic of d_latch is
+begin
+
+  latch_behavior : process is
+  begin
+    if clk = '1' then
+      q <= d after 2 ns;
+    end if;
+    wait on clk, d;
+  end process latch_behavior;
+
+end architecture basic;
+
+
+architecture basic of and2 is
+begin
+
+  and2_behavior : process is
+  begin
+    y <= a and b after 2 ns;
+    wait on a, b;
+  end process and2_behavior;
+
+end architecture basic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_11.vhd
new file mode 100644
index 0000000..2ab34ce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_11.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture struct of reg4 is
+
+  signal int_clk : bit;
+
+begin
+
+  bit0 : entity work.d_latch(basic)
+    port map (d0, int_clk, q0);
+  bit1 : entity work.d_latch(basic)
+    port map (d1, int_clk, q1);
+  bit2 : entity work.d_latch(basic)
+    port map (d2, int_clk, q2);
+  bit3 : entity work.d_latch(basic)
+    port map (d3, int_clk, q3);
+
+  gate : entity work.and2(basic)
+    port map (en, clk, int_clk);
+
+end architecture struct;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_13.vhd
new file mode 100644
index 0000000..9925044
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_13.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench is
+end entity test_bench;
+
+architecture test_reg4 of test_bench is
+
+  signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(behav)
+    port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
+
+  stimulus : process is
+  begin
+    d0 <= '1';  d1 <= '1';  d2 <= '1';  d3 <= '1';
+    en <= '0';  clk <= '0';
+    wait for 20 ns;
+    en <= '1';  wait for 20 ns;
+    clk <= '1';  wait for 20 ns;
+    d0 <= '0';  d1 <= '0';  d2 <= '0';  d3 <= '0';  wait for 20 ns;
+    en <= '0';  wait for 20 ns;
+    -- . . .
+    wait;
+  end process stimulus;
+
+end architecture test_reg4;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd
new file mode 100644
index 0000000..a1e2fcc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_01_01 is
+
+end entity test_bench_01_01;
+
+architecture test_reg4_behav of test_bench_01_01 is
+
+  signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(behav)
+    port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
+               q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+  stimulus : process is
+  begin
+    wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1010");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    clk <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0101");	wait for 20 ns;
+    clk <= '0';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0000");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1111");	wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_reg4_behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd
new file mode 100644
index 0000000..e33d48f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_tb_01_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_01_02 is
+
+end entity test_bench_01_02;
+
+architecture test_reg4_struct of test_bench_01_02 is
+
+  signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(struct)
+    port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
+               q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+  stimulus : process is
+  begin
+    wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1010");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    clk <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0101");	wait for 20 ns;
+    clk <= '0';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0000");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1111");	wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_reg4_struct;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_03.vhd
new file mode 100644
index 0000000..a20ad20
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_03.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_tb_01_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity shift_adder is
+  port ( addend : in integer;  augend : in integer;
+  sum : out integer;
+  add_control : in bit );
+end entity shift_adder;
+
+architecture behavior of shift_adder is
+begin
+end architecture behavior;
+
+------------------------------------------------------------------------
+
+entity reg is
+  port ( d : in integer;  q : out integer;
+  en : in bit;  reset : in bit );
+end entity reg;
+
+architecture behavior of reg is
+begin
+end architecture behavior;
+
+------------------------------------------------------------------------
+
+entity shift_reg is
+  port ( d : in integer;  q : out bit;
+  load : in bit;  clk : in bit );
+end entity shift_reg;
+
+architecture behavior of shift_reg is
+begin
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_fg_02_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_fg_02_01.vhd
new file mode 100644
index 0000000..0358642
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_fg_02_01.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_02_fg_02_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture sample of ent is
+
+  constant pi : real := 3.14159;
+
+begin
+
+  process is
+            variable counter : integer;
+  begin
+    -- . . .         --  statements using pi and counter
+  end process;
+
+end architecture sample;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_tb_02_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_tb_02_01.vhd
new file mode 100644
index 0000000..226a855
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_tb_02_01.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_02_tb_02_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ent is
+
+end entity ent;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd
new file mode 100644
index 0000000..c200d1b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_01.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_01 is
+end entity ch_03_01;
+
+architecture test of ch_03_01 is
+
+  signal en : bit := '0';
+  signal data_in : integer := 0;
+
+begin
+
+  process_3_1_a : process (en, data_in) is
+
+                                          variable stored_value : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    if en = '1' then
+      stored_value := data_in;
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_a;
+
+  stimulus : process is
+  begin
+    en <= '1' after 10 ns, '0' after 20 ns;
+    data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_02.vhd
new file mode 100644
index 0000000..b05946f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_02.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_02 is
+end entity ch_03_02;
+
+architecture test of ch_03_02 is
+
+  signal sel : integer range 0 to 1 := 0;
+  signal input_0 : integer := 0;
+  signal input_1 : integer := 10;
+  signal result : integer;
+
+begin
+
+  process_3_1_b : process (sel, input_0, input_1) is
+  begin
+
+    -- code from book:
+
+    if sel = 0 then
+      result <= input_0;  -- executed if sel = 0
+    else
+      result <= input_1;  -- executed if sel /= 0
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_b;
+
+  stimulus : process is
+  begin
+    sel <= 1 after 40 ns;
+    input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
+    input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd
new file mode 100644
index 0000000..3882ce1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_03 is
+end entity ch_03_03;
+
+architecture test of ch_03_03 is
+begin
+
+  process_3_1_c : process is
+
+                            type mode_type is (immediate, other_mode);
+                          type opcode_type is (load, add, subtract, other_opcode);
+
+                          variable mode : mode_type;
+                          variable opcode : opcode_type;
+                          constant immed_operand : integer := 1;
+                          constant memory_operand : integer := 2;
+                          constant address_operand : integer := 3;
+                          variable operand : integer;
+
+                          procedure procedure_3_1_c is
+                          begin
+
+                            -- code from book:
+
+                            if mode = immediate then
+                              operand := immed_operand;
+                            elsif opcode = load or opcode = add or opcode = subtract then
+                              operand := memory_operand;
+                            else
+                              operand := address_operand;
+                            end if;
+
+                            -- end of code from book
+
+                          end procedure_3_1_c;
+
+  begin
+    mode := immediate;
+    procedure_3_1_c;
+
+    mode := other_mode;
+    opcode := load;
+    procedure_3_1_c;
+
+    opcode := add;
+    procedure_3_1_c;
+
+    opcode := subtract;
+    procedure_3_1_c;
+
+    opcode := other_opcode;
+    procedure_3_1_c;
+
+    wait;
+  end process process_3_1_c;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd
new file mode 100644
index 0000000..439e463
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_04 is
+end entity ch_03_04;
+
+architecture test of ch_03_04 is
+
+  type opcode_type is (opcode_1, opcode_2, halt_opcode);
+  signal opcode : opcode_type := opcode_1;
+
+  signal halt_indicator : boolean := false;
+
+begin
+
+  process_3_1_d : process (opcode) is
+
+                                     variable PC : integer := 0;
+                                   constant effective_address : integer := 1;
+                                   variable executing : boolean := true;
+
+  begin
+
+    -- code from book:
+
+    if opcode = halt_opcode then
+      PC := effective_address;
+      executing := false;
+      halt_indicator <= true;
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_d;
+
+  stimulus : process is
+  begin
+    opcode <= opcode_2 after 100 ns, halt_opcode after 200 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_05.vhd
new file mode 100644
index 0000000..506ef5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_05.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_05 is
+end entity ch_03_05;
+
+architecture test of ch_03_05 is
+
+  type phase_type is (wash, other_phase);
+  signal phase : phase_type := other_phase;
+
+  type cycle_type is (delicate_cycle, other_cycle);
+  signal cycle_select : cycle_type := delicate_cycle;
+
+  type speed_type is (slow, fast);
+  signal agitator_speed : speed_type := slow;
+
+  signal agitator_on : boolean := false;
+
+begin
+
+  process_3_1_e : process (phase, cycle_select) is
+  begin
+
+    -- code from book:
+
+    if phase = wash then
+      if cycle_select = delicate_cycle then
+        agitator_speed <= slow;
+      else
+        agitator_speed <= fast;
+      end if;
+      agitator_on <= true;
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_e;
+
+  stimulus : process is
+  begin
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= wash;			wait for 100 ns;
+    cycle_select <= delicate_cycle;	wait for 100 ns;
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= other_phase;		wait for 100 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_06.vhd
new file mode 100644
index 0000000..49e2db4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_06.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_06.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_06 is
+end entity ch_03_06;
+
+architecture test of ch_03_06 is
+
+  -- code from book:
+  
+  type alu_func is (pass1, pass2, add, subtract);
+  
+  -- end of code from book
+  
+  signal func : alu_func := pass1;
+  signal operand1 : integer := 10;
+  signal operand2 : integer := 3;
+
+begin
+
+  process_03_2_a : process (func, operand1, operand2) is
+
+                                                        variable result : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    case func is
+      when pass1 =>
+        result := operand1;
+      when pass2 =>
+        result := operand2;
+      when add =>
+        result := operand1 + operand2;
+      when subtract =>
+        result := operand1 - operand2;
+    end case;
+
+    -- end of code from book
+
+  end process process_03_2_a;
+
+  stimulus : process is
+  begin
+    func <= pass2 after 10 ns,
+	    add after 20 ns,
+	    subtract after 30 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd
new file mode 100644
index 0000000..cdc0639
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_07 is
+end entity ch_03_07;
+
+architecture test of ch_03_07 is
+begin
+
+  process_03_2_b : process is
+
+                             -- code from book:
+
+                             subtype index_mode is integer range 0 to 3;
+
+                           variable instruction_register : integer range 0 to 2**16 - 1;
+
+                           -- end of code from book
+
+                           variable index_value : integer;
+                           constant accumulator_A : integer := 1;
+                           constant accumulator_B : integer := 2;
+                           constant index_register : integer := 3;
+
+  begin
+
+    for i in index_mode loop
+      instruction_register := i * 2**12;
+
+      -- code from book:
+
+      case index_mode'((instruction_register / 2**12) rem 2**2) is
+        when 0 =>
+          index_value := 0;
+        when 1 =>
+          index_value := accumulator_A;
+        when 2 =>
+          index_value := accumulator_B;
+        when 3 =>
+          index_value := index_register;
+      end case;
+
+      -- end of code from book
+
+    end loop;
+
+    wait;
+  end process process_03_2_b;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_08.vhd
new file mode 100644
index 0000000..d81c77d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_08.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_08 is
+end entity ch_03_08;
+
+architecture test of ch_03_08 is
+begin
+
+  process_03_2_c : process is
+
+                             -- code from book:
+
+                             type opcodes is
+                           (nop, add, subtract, load, store, jump, jumpsub, branch, halt);
+
+                           subtype control_transfer_opcodes is opcodes range jump to branch;
+
+                           -- end of code from book
+
+                           variable opcode : opcodes;
+                           variable operand : integer;
+                           constant memory_operand : integer := 1;
+                           constant address_operand : integer := 2;
+
+  begin
+
+    for i in opcodes loop
+      opcode := i;
+
+      -- code from book:
+
+      case opcode is
+        when load | add | subtract =>
+          operand := memory_operand;
+        when store | jump | jumpsub | branch =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      --
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+        when branch downto store =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      -- end of code from book
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+          -- code from book: (MTI bug mt011)
+          -- when control_transfer_opcodes | store =>
+          --   operand := address_operand;
+          -- end of code from book
+        when others =>
+          operand := 0;
+      end case;
+
+    end loop;
+
+    wait;
+  end process process_03_2_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_10.vhd
new file mode 100644
index 0000000..36b7a48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_10.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_10 is
+end entity ch_03_10;
+
+architecture test of ch_03_10 is
+
+  type opcode_type is (nop, add, subtract);
+
+  signal opcode : opcode_type := nop;
+
+begin
+
+  process_3_3_a : process (opcode) is
+
+                                     variable Acc : integer := 0;
+                                   constant operand : integer := 1;
+
+  begin
+
+    -- code from book:
+
+    case opcode is
+      when add =>
+        Acc := Acc + operand;
+      when subtract =>
+        Acc := Acc - operand;
+      when nop =>
+        null;
+    end case;
+
+    -- end of code from book
+
+  end process process_3_3_a;
+
+  stimulus : process is
+  begin
+    opcode <= add after 10 ns, subtract after 20 ns, nop after 30 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd
new file mode 100644
index 0000000..3bce6fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_11.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_11 is
+end entity ch_03_11;
+
+architecture test of ch_03_11 is
+
+  signal sensitivity_list : bit := '0';
+
+begin
+
+  -- code from book:
+
+  -- make "sensitivity_list" roman italic
+  control_section : process ( sensitivity_list ) is
+  begin
+    null;
+  end process control_section;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_12.vhd
new file mode 100644
index 0000000..4583ac9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_12.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_12.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_12 is
+end entity ch_03_12;
+
+architecture test of ch_03_12 is
+begin
+
+  process_3_4_a : process is
+
+                            constant condition, condition_1,
+                          condition_2, condition_3 : boolean := true;
+                          variable index : integer;
+
+  begin
+
+    -- code from book: syntax check only
+
+    -- change "condition" to roman italic
+
+    -- not in book:
+    loop
+      -- end not in book
+
+      if condition then
+        exit;
+      end if;
+
+      -- not in book:
+    end loop;
+    -- end not in book
+
+    --
+
+    -- change "condition" to roman italic
+
+    loop
+      -- . . .
+      exit when condition;
+      -- . . .
+    end loop;
+    -- . . .      -- control transferred to here
+    -- when condition becomes true within the loop
+
+    --
+
+    loop_name : loop
+      -- . . .
+      exit loop_name;
+      -- . . .
+    end loop loop_name ;
+
+    --
+
+    -- change conditions to roman italic with hyphens
+
+    outer : loop
+      -- . . .
+      inner : loop
+        -- . . .
+        exit outer when condition_1; -- exit 1
+        -- . . .
+        exit when condition_2;       -- exit 2
+        -- . . .
+      end loop inner;
+      -- . . .                      -- target A
+      exit outer when condition_3;   -- exit 3
+      -- . . .
+    end loop outer;
+    -- . . .                        -- target B
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      next when condition;
+      -- statement_2;
+    end loop;
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      if not condition then
+        -- statement_2;
+      end if;
+    end loop;
+
+    --
+
+    while index > 0 loop
+      -- . . .      -- statement A: do something with index
+    end loop;
+    -- . . .    -- statement B
+
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_a;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_13.vhd
new file mode 100644
index 0000000..d06e8c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_13.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_13.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_13 is
+end entity ch_03_13;
+
+architecture test of ch_03_13 is
+
+  signal count_out : integer;
+
+begin
+
+  process_3_4_b : process is
+  begin
+
+    -- code from book:
+
+    for count_value in 0 to 127 loop
+      count_out <= count_value;
+      wait for 5 ns;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_b;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_14.vhd
new file mode 100644
index 0000000..4d03128
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_14.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_14.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_14 is
+end entity ch_03_14;
+
+architecture test of ch_03_14 is
+
+  -- code from book:
+
+  type controller_state is (initial, idle, active, error);
+
+  -- end of code from book
+
+  signal current_state : controller_state := initial;
+
+begin
+
+  process_3_4_c : process is
+  begin
+
+    -- code from book:
+
+    for state in controller_state loop
+      -- . . .
+      -- not in book:
+      current_state <= state;
+      wait for 10 ns;
+      -- end not in book
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_c;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_16.vhd
new file mode 100644
index 0000000..0974eda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_16.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_16.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_16 is
+end entity ch_03_16;
+
+architecture test of ch_03_16 is
+begin
+
+  -- code from book:
+
+  hiding_example : process is
+                             variable a, b : integer;
+  begin
+    a := 10;
+    for a in 0 to 7 loop
+      b := a;
+    end loop;
+    -- a = 10, and b = 7
+    -- . . .
+    -- not in book:
+    wait;
+    -- end not in book
+  end process hiding_example;
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_17.vhd
new file mode 100644
index 0000000..fe89441
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_17.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_17.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_17 is
+end entity ch_03_17;
+
+architecture test of ch_03_17 is
+begin
+
+  process_3_4_f : process is
+  begin
+
+    -- code from book:
+
+    for i in 10 to 1 loop
+      -- . . .
+    end loop;
+
+    for i in 10 downto 1 loop
+      -- . . .
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_f;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_18.vhd
new file mode 100644
index 0000000..b5c1e34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_18.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_18 is
+end entity ch_03_18;
+
+architecture test of ch_03_18 is
+begin
+
+  process_3_5_a : process is
+
+                            constant initial_value : natural := 10;
+                          constant max_value : natural := 8;
+                          constant current_character : character := 'A';
+                          constant input_string : string := "012ABC";
+                          constant free_memory : natural := 0;
+                          constant low_water_limit : natural := 1024;
+                          constant packet_length : natural := 0;
+                          constant clock_pulse_width : delay_length := 10 ns;
+                          constant min_clock_width : delay_length := 20 ns;
+                          constant last_position : natural := 10;
+                          constant first_position : natural := 5;
+                          constant number_of_entries : natural := 0;
+
+  begin
+
+    -- code from book:
+
+    assert initial_value <= max_value;
+
+    --
+
+    assert initial_value <= max_value
+                            report "initial value too large";
+
+    --
+
+    assert current_character >= '0' and current_character <= '9'
+                                                             report "Input number " & input_string & " contains a non-digit";
+
+    --
+
+    assert free_memory >= low_water_limit
+      report "low on memory, about to start garbage collect"
+      severity note;
+
+    --
+
+    assert packet_length /= 0
+      report "empty network packet received"
+      severity warning;
+
+    --
+
+    assert clock_pulse_width >= min_clock_width
+      severity error;
+
+    --
+
+    assert (last_position - first_position + 1) = number_of_entries
+      report "inconsistency in buffer model"
+      severity failure;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_5_a;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_19.vhd
new file mode 100644
index 0000000..0cfa747
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_19.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_19.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_19 is
+end entity ch_03_19;
+
+architecture test of ch_03_19 is
+
+  subtype data_type is integer;
+
+  signal transmit_data : data_type := 0;
+
+begin
+
+  -- code from book:
+  
+  transmit_element : process (transmit_data) is
+                                               -- . . .      -- variable declarations
+  begin
+    report "transmit_element: data = "
+      & data_type'image(transmit_data);
+    -- . . .
+  end process transmit_element;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    transmit_data <= 10 after 10 ns, 20 after 20 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_20.vhd
new file mode 100644
index 0000000..e94699f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_20.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_20.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_20 is
+end entity ch_03_20;
+
+architecture test of ch_03_20 is
+begin
+
+  process_3_5_c : process is
+  begin
+
+    -- code from book:
+
+    assert false
+      report "Initialization complete" severity note;
+
+    --
+
+    report "Initialization complete";
+
+    -- end of code from book
+
+    wait;
+  end process process_3_5_c;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_01.vhd
new file mode 100644
index 0000000..68f3bb5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_01.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity thermostat is
+  port ( desired_temp, actual_temp : in integer;
+         heater_on : out boolean );
+end entity thermostat;
+
+architecture example of thermostat is
+begin
+
+  controller : process (desired_temp, actual_temp) is
+  begin
+    if actual_temp < desired_temp - 2 then
+      heater_on <= true;
+    elsif actual_temp > desired_temp + 2 then
+      heater_on <= false;
+    end if;
+  end process controller;
+
+end architecture example;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_02.vhd
new file mode 100644
index 0000000..d7efef6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_02.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_02.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- test code:
+
+use work.test_bench_03_02.all;
+
+-- end test code
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity mux4 is
+                 port ( sel : in sel_range;
+                        d0, d1, d2, d3 : in std_ulogic;
+                        z : out std_ulogic );
+               end entity mux4;
+
+               architecture demo of mux4 is
+               begin
+
+                 out_select : process (sel, d0, d1, d2, d3) is
+                 begin
+                   case sel is
+                     when 0 => 
+                       z <= d0;
+                     when 1 => 
+                       z <= d1;
+                     when 2 => 
+                       z <= d2;
+                     when 3 => 
+                       z <= d3;
+                   end case;
+                 end process out_select;
+
+               end architecture demo;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd
new file mode 100644
index 0000000..b1b8053
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity counter is
+  port ( clk : in bit;  count : out natural );
+end entity counter;
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+                          variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      wait until clk = '1';
+      count_value := (count_value + 1) mod 16;
+      count <= count_value;
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd
new file mode 100644
index 0000000..25ffb55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity counter is
+  port ( clk, reset : in bit;  count : out natural );
+end entity counter;
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+                          variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      loop
+        wait until clk = '1' or reset = '1';
+        exit when reset = '1';
+        count_value := (count_value + 1) mod 16;
+        count <= count_value;
+      end loop;
+      -- at this point, reset = '1'
+      count_value := 0;
+      count <= count_value;
+      wait until reset = '0';
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd
new file mode 100644
index 0000000..773bd6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_05.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity cos is
+  port ( theta : in real;  result : out real );
+end entity cos;
+
+architecture series of cos is
+begin
+
+  summation : process (theta) is
+                                variable sum, term : real;
+                              variable n : natural;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    n := 0;
+    while abs term > abs (sum / 1.0E6) loop
+      n := n + 2;
+      term := (-term) * theta**2 / real(((n-1) * n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd
new file mode 100644
index 0000000..5536560
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture fixed_length_series of cos is
+begin
+
+  summation : process (theta) is
+                                variable sum, term : real;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    for n in 1 to 9 loop
+      term := (-term) * theta**2 / real(((2*n-1) * 2*n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture fixed_length_series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd
new file mode 100644
index 0000000..3460c94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity SR_flipflop is
+  port ( S, R : in bit;  Q : out bit );
+end entity SR_flipflop;
+
+architecture checking of SR_flipflop is
+begin
+
+  set_reset : process (S, R) is
+  begin
+    assert S = '1' nand R = '1';
+    if S = '1' then
+      Q <= '1';
+    end if;
+    if R = '1' then
+      Q <= '0';
+    end if;
+  end process set_reset;
+
+end architecture checking;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_08.vhd
new file mode 100644
index 0000000..23e8738
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_08.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity max3 is
+  port ( a, b, c : in integer;  z : out integer );
+end entity max3;
+
+architecture check_error of max3 is
+begin
+
+  maximizer : process (a, b, c)
+    variable result : integer;
+  begin
+    if a > b then
+      if a > c then
+        result := a;
+      else
+        result := a;  -- Oops!  Should be: result := c;
+      end if;
+    elsif  b > c then
+      result := b;
+    else
+      result := c;
+    end if;
+    assert result >= a and result >= b and result >= c
+      report "inconsistent result for maximum"
+      severity failure;
+    z <= result;
+  end process maximizer;
+
+end architecture check_error;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_09.vhd
new file mode 100644
index 0000000..b54fc47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_09.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_09.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity edge_triggered_register is
+  port ( clock : in bit; 
+         d_in : in real;  d_out : out real );
+end entity edge_triggered_register;
+
+architecture check_timing of edge_triggered_register is
+begin
+
+  store_and_check : process (clock) is
+                                      variable stored_value : real;
+                                    variable pulse_start : time;
+  begin
+    case clock is
+      when '1' =>
+        pulse_start := now;
+        stored_value := d_in;
+        d_out <= stored_value;
+      when '0' =>
+        assert now = 0 ns or (now - pulse_start) >= 5 ns
+          report "clock pulse too short"; 
+    end case;
+  end process store_and_check;
+
+end architecture check_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd
new file mode 100644
index 0000000..8d34304
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_01 is
+end entity test_bench_03_01;
+
+architecture test_thermostat_example of test_bench_03_01 is
+
+  signal desired_temp, actual_temp : integer := 25;
+  signal heater_on : boolean := false;
+
+begin
+
+  dut : entity work.thermostat(example)
+    port map ( desired_temp => desired_temp, actual_temp => actual_temp,
+               heater_on => heater_on );
+
+  stimulus : process is
+  begin
+    wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 21;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 29;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 21;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 29;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+
+    desired_temp <= 30;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 29;		wait for 5 sec;
+    actual_temp <= 30;		wait for 5 sec;
+    actual_temp <= 31;		wait for 5 sec;
+    actual_temp <= 32;		wait for 5 sec;
+    actual_temp <= 33;		wait for 5 sec;
+    actual_temp <= 34;		wait for 5 sec;
+    actual_temp <= 35;		wait for 5 sec;
+    actual_temp <= 34;		wait for 5 sec;
+    actual_temp <= 33;		wait for 5 sec;
+    actual_temp <= 32;		wait for 5 sec;
+    actual_temp <= 31;		wait for 5 sec;
+    actual_temp <= 30;		wait for 5 sec;
+
+    wait;
+  end process stimulus;
+
+end architecture test_thermostat_example;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_02.vhd
new file mode 100644
index 0000000..27369e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_02.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package test_bench_03_02 is
+
+  -- following type used in Figure 3-02
+
+  -- code from book:
+
+  type sel_range is range 0 to 3;
+
+  -- end of code from book
+
+end package test_bench_03_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_03.vhd
new file mode 100644
index 0000000..1f802b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_03.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_03 is
+end entity test_bench_03_03;
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+architecture test_mux4_demo of test_bench_03_03 is
+
+  signal sel : work.test_bench_03_02.sel_range := 0;
+  signal d0, d1, d2, d3, z : std_ulogic;
+
+begin
+
+  dut : entity work.mux4(demo)
+    port map ( sel => sel,
+               d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+               z => z );
+
+  stimulus : process is
+  begin
+    wait for 5 ns;
+    d0 <= '1';			wait for 5 ns;
+    d1 <= 'H';			wait for 5 ns;
+    sel <= 1;	wait for 5 ns;
+    d1 <= 'L';			wait for 5 ns;
+    sel <= 2;	wait for 5 ns;
+    d0 <= '0';			wait for 5 ns;
+    d2 <= '1';			wait for 5 ns;
+    d2 <= '0';			wait for 5 ns;
+    sel <= 3;	wait for 5 ns;
+    d3 <= '1';			wait for 5 ns;
+    d3 <= '0';			wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_mux4_demo;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_04.vhd
new file mode 100644
index 0000000..618a5f1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_04.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_04.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_04 is
+end entity test_bench_03_04;
+
+architecture test_counter_behavior of test_bench_03_04 is
+
+  signal clk : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, count => count );
+
+  stimulus : process is
+  begin
+    for cycle_count in 1 to 100 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_counter_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_05.vhd
new file mode 100644
index 0000000..0fb83ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_05.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_05 is
+end entity test_bench_03_05;
+
+architecture test_counter_behavior of test_bench_03_05 is
+
+  signal clk, reset : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, reset => reset, count => count );
+
+  stimulus : process is
+  begin
+
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '1' after 15 ns;
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '0' after 15 ns;
+    for cycle_count in 1 to 30 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_counter_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_06.vhd
new file mode 100644
index 0000000..9dacdd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_06.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_06.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_06 is
+end entity test_bench_03_06;
+
+architecture test_cos_series of test_bench_03_06 is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+                       constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_cos_series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_07.vhd
new file mode 100644
index 0000000..a9ec05d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_07.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_07 is
+end entity test_bench_03_07;
+
+architecture test_cos_fixed_length_series of test_bench_03_07 is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(fixed_length_series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+                       constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_cos_fixed_length_series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_08.vhd
new file mode 100644
index 0000000..62b9640
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_08.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_08.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_08 is
+end entity test_bench_03_08;
+
+architecture test_SR_flipflop_checking of test_bench_03_08 is
+
+  signal S, R, Q : bit := '0';
+
+begin
+
+  dut : entity work.SR_flipflop(checking)
+    port map ( S => S, R => R, Q => Q );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '1';	R <= '1';	wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_SR_flipflop_checking;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_09.vhd
new file mode 100644
index 0000000..be67916
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_09.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_09.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_09 is
+end entity test_bench_03_09;
+
+architecture test_max3_check_error of test_bench_03_09 is
+
+  signal a, b, c, z : integer := 0;
+
+begin
+
+  dut : entity work.max3(check_error)
+    port map ( a => a, b => b, c => c, z => z );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    a <= 7;				wait for 10 ns;
+    b <= 10;		wait for 10 ns;
+    c <= 15;	wait for 10 ns;
+    a <= 12;				wait for 10 ns;
+    a <= 20;				wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_max3_check_error;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_10.vhd
new file mode 100644
index 0000000..82a549e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_10.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_10 is
+end entity test_bench_03_10;
+
+architecture test_edge_triggered_register_check_timing of test_bench_03_10 is
+
+  signal clock : bit := '0'; 
+  signal d_in, d_out : real := 0.0;
+
+begin
+
+  dut : entity work.edge_triggered_register(check_timing)
+    port map ( clock => clock, d_in => d_in, d_out => d_out );
+
+  stumulus : process is
+
+  begin
+    wait for 20 ns;
+
+    d_in <= 1.0;			wait for 10 ns;
+    clock <= '1', '0' after 10 ns;	wait for 20 ns;
+
+    d_in <= 2.0;			wait for 10 ns;
+    clock <= '1', '0' after 5 ns;	wait for 20 ns;
+
+    d_in <= 3.0;			wait for 10 ns;
+    clock <= '1', '0' after 4 ns;	wait for 20 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_edge_triggered_register_check_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_01.vhd
new file mode 100644
index 0000000..f9922f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_01.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_01 is
+
+end entity ch_04_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_01 is
+begin
+
+
+  block_04_1_a : block is
+
+                         -- code from book:
+
+                         type word is array (0 to 31) of bit;
+
+                       --
+
+                       type controller_state is (initial, idle, active, error);
+
+                       type state_counts is array (idle to error) of natural;
+
+                       -- end of code from book
+
+  begin
+  end block block_04_1_a;
+
+
+  process_04_1_a : process is
+
+                             -- code from book:
+
+                             type word is array (31 downto 0) of bit;
+
+                           --
+
+                           type controller_state is (initial, idle, active, error);
+
+                           --
+
+                           type state_counts is
+                             array (controller_state range idle to error) of natural;
+
+                           --
+
+                           subtype coeff_ram_address is integer range 0 to 63;
+                           type coeff_array is array (coeff_ram_address) of real;
+
+                           --
+
+                           variable buffer_register, data_register : word;
+                           variable counters : state_counts;
+                           variable coeff : coeff_array;
+
+                           -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    coeff(0) := 0.0;
+
+    counters(active) := counters(active) + 1;
+
+    data_register := buffer_register;
+
+    -- end of code from book
+
+    wait;
+  end process process_04_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_02.vhd
new file mode 100644
index 0000000..b3360e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_02.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_02 is
+
+end entity ch_04_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_02 is
+begin
+
+
+  process_04_1_b : process is
+
+                             -- code from book:
+
+                             type symbol is ('a', 't', 'd', 'h', digit, cr, error);
+                           type state is range 0 to 6;
+
+                           type transition_matrix is array (state, symbol) of state;
+
+                           variable transition_table : transition_matrix;
+
+                           -- end of code from book
+
+                           variable next_state : state;
+
+                           -- code from book:
+
+                           type point is array (1 to 3) of real;
+                           type matrix is array (1 to 3, 1 to 3) of real;
+
+                           variable p, q : point;
+                           variable transform : matrix;
+
+                           -- end of code from book
+
+  begin
+
+    next_state := 
+      -- code from book:
+
+      transition_table(5, 'd');
+
+
+    -- end of code from book
+
+    for i in 1 to 3 loop
+      for j in 1 to 3 loop
+        if i = j then
+          transform(i, j) := -1.0;
+        else
+          transform(i, j) := 0.0;
+        end if;
+      end loop;
+    end loop;
+    p := (1.0, 2.0, 3.0);
+
+    -- code from book:
+
+    for i in 1 to 3 loop
+      q(i) := 0.0;
+      for j in 1 to 3 loop
+        q(i) := q(i) + transform(i, j) * p(j);
+      end loop;
+    end loop;
+    -- end of code from book
+
+    wait;
+  end process process_04_1_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd
new file mode 100644
index 0000000..d30cad7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_04 is
+
+end entity ch_04_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_04 is
+begin
+
+
+  process_04_1_i : process is
+
+                             -- code from book:
+
+                             type A is array (1 to 4, 31 downto 0) of boolean;
+
+                           -- end of code from book
+
+                           variable free_map : bit_vector(1 to 10) := "0011010110";
+                           variable count : natural;
+
+  begin
+
+    -- code from book (just the conditions):
+
+    assert A'left(1) = 1;      assert A'low(1) = 1;
+    assert A'right(2) = 0 ;    assert A'high(2) = 31;
+
+    assert A'length(1) = 4;    assert A'length(2) = 32;
+
+    assert A'ascending(1) = true;    assert A'ascending(2) = false;
+
+    assert A'low = 1;    assert A'length = 4;
+
+    --
+
+    count := 0;
+    for index in free_map'range loop
+      if free_map(index) = '1' then
+        count := count + 1;
+      end if;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_04_1_i;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_05.vhd
new file mode 100644
index 0000000..cfe1ea8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_05.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_05.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_05 is
+
+end entity ch_04_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_05 is
+begin
+
+
+  process_04_2_a : process is
+
+                             -- code from book:
+
+                             type sample is array (natural range <>) of integer;
+
+                           variable short_sample_buf : sample(0 to 63);
+
+                           subtype long_sample is sample(0 to 255);
+                           variable new_sample_buf, old_sample_buf : long_sample;
+
+
+                           constant lookup_table : sample := ( 1 => 23, 3 => -16, 2 => 100, 4 => 11);
+
+                           constant beep_sample : sample := ( 127, 63, 0, -63, -127, -63, 0, 63 );
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_06.vhd
new file mode 100644
index 0000000..e1bcf87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_06.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_06 is
+
+end entity ch_04_06;
+
+
+----------------------------------------------------------------
+
+
+--library ieee;  use ieee.std_logic_1164.std_ulogic;
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ch_04_06 is
+
+  -- code from book:
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+  
+  --
+  
+  subtype std_ulogic_word is std_ulogic_vector(0 to 31);
+  
+  --
+  
+  signal csr_offset : std_ulogic_vector(2 downto 1);
+
+  -- end of code from book
+
+begin
+
+
+  process_04_2_b : process is
+
+                             -- code from book:
+
+                             type string is array (positive range <>) of character;
+
+                           --
+
+                           constant LCD_display_len : positive := 20;
+                           subtype LCD_display_string is string(1 to LCD_display_len);
+                           variable LCD_display : LCD_display_string := (others => ' ');
+
+                           --
+
+                           type bit_vector is array (natural range <>) of bit;
+
+                           --
+
+                           subtype byte is bit_vector(7 downto 0);
+
+                           --
+
+                           variable channel_busy_register : bit_vector(1 to 4);
+
+                           --
+
+                           constant ready_message  : string := "Ready     ";
+
+                           --
+
+                           variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
+
+                           --
+
+                           constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
+
+                           -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    channel_busy_register := b"0000";
+
+    -- end of code from book
+
+    wait;
+  end process process_04_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_07.vhd
new file mode 100644
index 0000000..675f609
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_07.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_07 is
+
+end entity ch_04_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_07 is
+begin
+
+
+  process_04_3_a : process is
+
+                             -- code from book:
+
+                             subtype pixel_row is bit_vector (0 to 15);
+                           variable current_row, mask : pixel_row;
+
+                           -- end of code from book
+
+  begin
+
+    current_row := "0000000011111111";
+    mask := "0000111111110000";
+
+    -- code from book:
+
+    current_row := current_row and not mask;
+    current_row := current_row xor X"FFFF";
+
+    -- end of code from book
+
+    -- code from book (conditions only):
+
+    assert B"10001010" sll 3  =  B"01010000";
+    assert B"10001010" sll -2  =  B"00100010";
+
+    assert B"10010111" srl 2  = B"00100101";
+    assert B"10010111" srl -6  =  B"11000000";
+
+    assert B"01001011" sra 3  =  B"00001001";
+    assert B"10010111" sra 3  =  B"11110010";
+    assert B"00001100" sla 2  =  B"00110000";
+    assert B"00010001" sla 2  =  B"01000111";
+
+    assert B"00010001" sra -2  =  B"01000111";
+    assert B"00110000" sla -2  =  B"00001100";
+
+    assert B"10010011" rol 1  =  B"00100111";
+    assert B"10010011" ror 1  =  B"11001001";
+
+    assert "abc" & 'd'  =  "abcd";
+    assert 'w' & "xyz"  =  "wxyz";
+    assert 'a' & 'b'  =  "ab";
+
+    -- end of code from book
+
+    wait;
+  end process process_04_3_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_08.vhd
new file mode 100644
index 0000000..de777a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_08.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_08 is
+
+end entity ch_04_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_08 is
+begin
+
+
+  process_04_3_b : process is
+
+                             -- code from book:
+
+                             type array1 is array (1 to 100) of integer;
+                           type array2 is array (100 downto 1) of integer;
+
+                           variable a1 : array1;
+                           variable a2 : array2;
+
+                           -- end of code from book
+
+  begin
+
+    a1(11 to 20) := a1(11 to 20);
+    a2(50 downto 41) := a2(50 downto 41);
+
+    a1(10 to 1) := a1(10 to 1);
+    a2(1 downto 10) := a2(1 downto 10);
+
+    a1(10 downto 1) := a1(10 downto 1);  -- illegal
+    a2(1 to 10) := a2(1 to 10);  -- illegal;
+
+    wait;
+  end process process_04_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_10.vhd
new file mode 100644
index 0000000..debb3e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_10.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_10.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_10 is
+
+end entity ch_04_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_10 is
+
+  -- code from book:
+
+  type time_stamp is record
+                       seconds : integer range 0 to 59;
+                       minutes : integer range 0 to 59;
+                       hours : integer range 0 to 23;
+                     end record time_stamp;
+
+  -- end of code from book
+
+begin
+
+
+  process_04_4_a : process is
+
+                             -- code from book:
+
+                             variable sample_time, current_time : time_stamp;
+
+                           --
+
+                           constant midday : time_stamp := (0, 0, 12);
+
+                           -- end of code from book
+
+                           constant clock : integer := 79;
+                           variable sample_hour : integer;
+
+  begin
+
+    current_time := (30, 15, 2);
+
+    -- code from book:
+
+    sample_time := current_time;
+
+    sample_hour := sample_time.hours;
+
+    current_time.seconds := clock mod 60;
+
+    -- end of code from book
+
+    wait;
+  end process process_04_4_a;
+
+
+  process_04_4_b : process is
+
+                             type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
+                           type reg_number is range 0 to 31;
+
+                           type instruction is record
+                                                 opcode : opcodes;
+                                                 source_reg1, source_reg2, dest_reg : reg_number;
+                                                 displacement : integer;
+                                               end record instruction;
+
+                           -- code from book:
+
+                           constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
+
+                           --
+
+                           constant nop_instr : instruction :=
+                             ( opcode => addu,
+                               source_reg1 | source_reg2 | dest_reg => 0,
+                               displacement => 0 );
+
+                           variable latest_event : time_stamp := (others => 0); -- initially midnight
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_4_b;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_01.vhd
new file mode 100644
index 0000000..d595916
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_01.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_01.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book:
+library ch4_pkgs;
+use ch4_pkgs.pk_04_01.all;
+-- end not in book
+
+
+entity coeff_ram is
+  port ( rd, wr : in bit;  addr : in coeff_ram_address;
+  d_in : in real;  d_out : out real );
+end entity coeff_ram;
+
+--------------------------------------------------
+
+architecture abstract of coeff_ram is
+begin
+
+  memory : process is
+                     type coeff_array is array (coeff_ram_address) of real;
+                   variable coeff : coeff_array;
+  begin
+    for index in coeff_ram_address loop
+      coeff(index) := 0.0;
+    end loop;
+    loop
+      wait on rd, wr, addr, d_in; 
+      if rd = '1' then
+        d_out <= coeff(addr);
+      end if;
+      if wr = '1' then
+        coeff(addr) := d_in;
+      end if;
+    end loop;
+  end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd
new file mode 100644
index 0000000..300f15a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_04_03 is
+
+end entity fg_04_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of fg_04_03 is
+begin
+
+  -- code from book:
+
+  modem_controller : process is
+
+                               type symbol is ('a', 't', 'd', 'h', digit, cr, other);
+                             type symbol_string is array (1 to 20) of symbol;
+                             type state is range 0 to 6;
+                             type transition_matrix is array (state, symbol) of state;
+
+                             constant next_state : transition_matrix :=
+                               ( 0 => ('a' => 1, others => 6),
+                                 1 => ('t' => 2, others => 6),
+                                 2 => ('d' => 3, 'h' => 5, others => 6),
+                                 3 => (digit => 4, others => 6),
+                                 4 => (digit => 4, cr => 0, others => 6),
+                                 5 => (cr => 0, others => 6),
+                                 6 => (cr => 0, others => 6) );
+
+                             variable command : symbol_string;
+                             variable current_state : state := 0;
+
+                             -- not in book:
+                             type sample_array is array (positive range <>) of symbol_string;
+                             constant sample_command : sample_array :=
+                               ( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
+                                 2 => ( 'a', 't', 'h', cr, others => other ),
+                                 3 => ( 'a', 't', other, other, cr, others => other ) );
+                             -- end not in book
+
+  begin
+    -- . . .
+    -- not in book:
+    for command_index in sample_command'range loop
+      command := sample_command(command_index);
+      -- end not in book
+      for index in 1 to 20 loop
+        current_state := next_state( current_state, command(index) );
+        case current_state is
+          -- . . .
+          -- not in book:
+          when 0 => exit;
+          when others => null;
+                         -- end not in book
+        end case;
+      end loop;
+      -- . . .
+      -- not in book:
+    end loop;
+    wait;
+    -- end not in book
+  end process modem_controller;
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_04.vhd
new file mode 100644
index 0000000..6be89a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_04.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity and_multiple is
+  port ( i : in bit_vector;  y : out bit );
+end entity and_multiple;
+
+--------------------------------------------------
+
+architecture behavioral of and_multiple is
+begin
+
+  and_reducer : process ( i ) is
+                                variable result : bit;
+  begin
+    result := '1';
+    for index in i'range loop
+      result := result and i(index);
+    end loop;
+    y <= result;
+  end process and_reducer;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_05.vhd
new file mode 100644
index 0000000..7bab6ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_05.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_05.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book:
+library ch4_pkgs;
+use ch4_pkgs.pk_04_02.all;
+-- end not in book:
+
+
+entity byte_swap is
+  port (input : in halfword;  output : out halfword);
+end entity byte_swap;
+
+--------------------------------------------------
+
+architecture behavior of byte_swap is
+
+begin
+
+  swap : process (input)
+  begin
+    output(8 to 15) <= input(0 to 7);
+    output(0 to 7) <= input(8 to 15);
+  end process swap;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_06.vhd
new file mode 100644
index 0000000..9e6ca87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_06.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture system_level of computer is
+
+  type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
+                   -- not in book:
+                   nop);
+  -- end not in book
+  type reg_number is range 0 to 31;
+  constant r0 : reg_number := 0;  constant r1 : reg_number := 1;  -- . . .
+  -- not in book:
+  constant r2 : reg_number := 2;
+  -- end not in book
+
+  type instruction is record
+                        opcode : opcodes;
+                        source_reg1, source_reg2, dest_reg : reg_number;
+                        displacement : integer;
+                      end record instruction;
+
+  type word is record
+                 instr : instruction;
+                 data : bit_vector(31 downto 0);
+               end record word;
+
+  signal address : natural;
+  signal read_word, write_word : word;
+  signal mem_read, mem_write : bit := '0';
+  signal mem_ready : bit := '0';
+
+begin
+
+  cpu : process is
+                  variable instr_reg : instruction;
+                variable PC : natural;
+                -- . . .    -- other declarations for register file, etc.
+  begin
+    address <= PC;
+    mem_read <= '1';
+    wait until mem_ready = '1';
+    instr_reg := read_word.instr;
+    mem_read <= '0';
+    -- not in book:
+    wait until mem_ready = '0';
+    -- end not in book
+    PC := PC + 4;
+    case instr_reg.opcode is  -- execute the instruction
+      -- . . .
+      -- not in book:
+      when others => null;
+                     -- end not in book
+    end case;
+  end process cpu;
+
+  memory : process is
+                     type memory_array is array (0 to 2**14 - 1) of word;
+                   variable store : memory_array :=
+                     (  0  => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
+                        1  => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
+                        -- . . .
+                        40  => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
+                        others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
+  begin
+    -- . . .
+    -- not in book:
+    wait until mem_read = '1';
+    read_word <= store(address);
+    mem_ready <= '1';
+    wait until mem_read = '0';
+    mem_ready <= '0';
+    -- end not in book
+  end process memory;
+
+end architecture system_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_01.vhd
new file mode 100644
index 0000000..a713f84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_01.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_pk_04_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package pk_04_01 is
+
+  subtype coeff_ram_address is integer range 0 to 63;
+
+end package pk_04_01;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_02.vhd
new file mode 100644
index 0000000..e749a9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_02.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_pk_04_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package pk_04_02 is
+
+  subtype halfword is bit_vector(0 to 15);
+
+end package pk_04_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_01.vhd
new file mode 100644
index 0000000..7fa037a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_01.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_01.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_04_01 is
+end entity test_bench_04_01;
+
+library ch4_pkgs;
+use ch4_pkgs.pk_04_02.all;
+
+architecture test_coeff_ram_abstract of test_bench_04_01 is
+
+  signal rd, wr : bit := '0';
+  signal addr : coeff_ram_address := 0;
+  signal d_in, d_out : real := 0.0;
+
+begin
+
+  dut : entity work.coeff_ram(abstract)
+    port map ( rd => rd, wr => wr,
+	       addr => addr,
+	       d_in => d_in, d_out => d_out );
+
+  stumulus : process is
+
+  begin
+    wait for 100 ns;
+
+    addr <= 10;  d_in <= 10.0;  wait for 10 ns;
+    wr <= '1';			wait for 10 ns;
+    d_in <= 20.0;  		wait for 10 ns;
+    wr <= '0';			wait for 70 ns;
+
+    addr <= 20;			wait for 10 ns;
+    rd <= '1';			wait for 10 ns;
+    addr <= 10;			wait for 10 ns;
+    rd <= '0';			wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_coeff_ram_abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd
new file mode 100644
index 0000000..a7181df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_04_02 is
+
+end entity test_bench_04_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test_and_multiple_behavioral of test_bench_04_02 is
+
+  -- code from book:
+
+  signal count_value : bit_vector(7 downto 0);
+  signal terminal_count : bit;
+
+  -- end of code from book
+
+begin
+
+  -- code from book:
+
+  tc_gate : entity work.and_multiple(behavioral)
+    port map ( i => count_value, y => terminal_count);
+
+  -- end of code from book
+
+  stumulus : process is
+  begin
+    wait for 10 ns;
+    count_value <= "10000000";	wait for 10 ns;
+    count_value <= "11111110";	wait for 10 ns;
+    count_value <= "01111111";	wait for 10 ns;
+    count_value <= "11111111";	wait for 10 ns;
+    count_value <= "00000000";	wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_and_multiple_behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_03.vhd
new file mode 100644
index 0000000..3a49f5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_03.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_03.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_04_03 is
+end entity test_bench_04_03;
+
+library ch4_pkgs;
+use ch4_pkgs.pk_04_02.all;
+
+architecture test_byte_swap_behavior of test_bench_04_03 is
+
+  signal input, output : halfword := x"0000";
+
+begin
+
+  dut : entity work.byte_swap(behavior)
+    port map ( input => input, output => output );
+
+  stumulus : process is
+  begin
+    wait for 10 ns;
+    input <= x"ff00";	wait for 10 ns;
+    input <= x"00ff";	wait for 10 ns;
+    input <= x"aa33";	wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_byte_swap_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_04.vhd
new file mode 100644
index 0000000..c6665ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_04.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity computer is
+
+end entity computer;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_01.vhd
new file mode 100644
index 0000000..6a01c62
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_01.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.tb_05_13.all;
+
+-- end not in book
+
+entity adder is
+  port ( a : in word;
+         b : in word;
+         sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_02.vhd
new file mode 100644
index 0000000..3ce3bb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_02.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.tb_05_13.all;
+
+-- end not in book
+
+entity adder is
+  port ( a, b : in word;
+         sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_03.vhd
new file mode 100644
index 0000000..326c8fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_03.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+         y : out bit );
+end entity and_or_inv;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_04.vhd
new file mode 100644
index 0000000..556c4b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_04.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity top_level is
+end entity top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_05.vhd
new file mode 100644
index 0000000..2afe050
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_05.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture abstract of adder is
+begin
+
+  add_a_b : process (a, b) is
+  begin
+    sum <= a + b;
+  end process add_a_b;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_06.vhd
new file mode 100644
index 0000000..e7c1c06
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_06.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_06 is
+
+end entity ch_05_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_06 is
+
+  signal y : bit := '0';
+  signal or_a_b : bit := '0';
+  signal clk : bit := '0';
+
+begin
+
+
+  process_05_3_a : process is
+  begin
+
+    -- code from book:
+
+    y <= not or_a_b after 5 ns;
+
+    -- end of code from book
+
+    wait on or_a_b;
+  end process process_05_3_a;
+
+
+  stimulus_05_3_a : process is
+  begin
+    or_a_b <= '1' after 20 ns,
+              '0' after 40 ns;
+    wait;
+  end process stimulus_05_3_a;
+
+
+  process_05_3_b : process is
+                             constant T_pw : delay_length := 10 ns;
+  begin
+
+    -- code from book:
+
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+
+    -- end of code from book
+
+    wait for 2*T_pw;
+  end process process_05_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd
new file mode 100644
index 0000000..1f69586
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_07 is
+
+end entity ch_05_07;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ch_05_07 is
+
+  signal clk, d : std_ulogic;
+
+  constant Tpw_clk : delay_length := 10 ns;
+  constant Tsu : delay_length := 4 ns;
+
+begin
+
+
+  process_05_3_c : process (clk, d) is
+  begin
+
+    -- code from book:
+
+    if clk'event and (clk = '1' or clk = 'H')
+      and (clk'last_value = '0' or clk'last_value = 'L') 
+    then
+      assert d'last_event >= Tsu
+        report "Timing error: d changed within setup time of clk";
+    end if;
+
+    -- end of code from book
+
+  end process process_05_3_c;
+
+
+  ----------------
+
+
+  process_05_3_d : process (clk, d) is
+  begin
+
+    -- code from book:
+
+    assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
+      report "Clock frequency too high";
+
+    -- end of code from book
+
+  end process process_05_3_d;
+
+
+  ----------------
+
+
+  process_05_3_e : process is
+  begin
+
+    -- code from book:
+
+    wait until clk = '1';
+
+    -- end of code from book
+
+    report "clk changed to '1'";
+  end process process_05_3_e;
+
+
+  ----------------
+
+
+  stimulus_05_3_c_d : process is
+  begin
+
+    clk <= '1' after  15 ns,
+           '0' after  30 ns,
+           '1' after  40 ns,
+           '0' after  50 ns,
+           'H' after  60 ns,
+           '0' after  70 ns,
+           '1' after  80 ns,
+           'L' after  90 ns,
+           'H' after 100 ns,
+           'L' after 120 ns,
+           '1' after 125 ns, -- should cause error
+           '0' after 130 ns; -- should cause error
+
+    d <= '1' after  35 ns,
+         '0' after  77 ns, -- should cause error
+         '1' after 102 ns;
+
+    wait;
+  end process stimulus_05_3_c_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_08.vhd
new file mode 100644
index 0000000..eb76352
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_08.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_08 is
+
+end entity ch_05_08;
+
+library stimulus;
+
+architecture test of ch_05_08 is
+
+  constant T_pd : delay_length := 5 ns;
+
+  signal a, b : bit := '0';
+  signal test_inputs : bit_vector(1 to 2);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+  block_05_3_f : block is
+
+                         signal sum, carry : bit;
+
+  begin
+
+    -- code from book:
+
+    half_add : process is
+    begin
+      sum <= a xor b after T_pd;
+      carry <= a and b after T_pd;
+      wait on a, b;
+    end process half_add;
+
+    -- end of code from book
+
+  end block block_05_3_f;
+
+  block_05_3_g : block is
+
+                         signal sum, carry : bit;
+
+  begin
+
+    -- code from book:
+
+    half_add : process (a, b) is
+    begin
+      sum <= a xor b after T_pd;
+      carry <= a and b after T_pd;
+    end process half_add;
+
+    -- end of code from book
+
+  end block block_05_3_g;
+
+  stimulus_05_3_f_g :
+    all_possible_values(test_inputs, 20 ns);
+
+  (a, b) <= test_inputs;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_09.vhd
new file mode 100644
index 0000000..fae70e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_09.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_09 is
+
+end entity ch_05_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_09 is
+
+  signal clk, reset, trigger, test0, test1 : bit := '0';
+
+begin
+
+
+  process_05_3_h : process is
+  begin
+
+    -- code from book:
+
+    wait until clk = '1';
+
+    -- end of code from book
+
+    report "clk rising edge detected";
+
+  end process process_05_3_h;
+
+
+  ----------------
+
+
+  process_05_3_i : process is
+  begin
+
+    -- code from book:
+
+    wait on clk until reset = '0';
+
+    -- end of code from book
+
+    report "synchronous reset detected";
+
+  end process process_05_3_i;
+
+
+  ----------------
+
+
+  process_05_3_j : process is
+  begin
+
+    -- code from book:
+
+    wait until trigger = '1' for 1 ms;
+
+    -- end of code from book
+
+    if trigger'event and trigger = '1' then
+      report "trigger rising edge detected";
+    else
+      report "trigger timeout";
+    end if;
+
+  end process process_05_3_j;
+
+
+  ----------------
+
+
+  -- code from book:
+
+  test_gen : process is
+  begin
+    test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
+    test1 <= '0' after 10 ns, '1' after 30 ns;
+    wait;
+  end process test_gen;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus_05_3_h_i_j : process is
+  begin
+    clk <= '1' after 10 ns, '0' after 20 ns,
+           '1' after 30 ns, '0' after 40 ns,
+           '1' after 50 ns, '0' after 60 ns,
+           '1' after 70 ns, '0' after 80 ns;
+    reset <= '1' after 45 ns, '0' after 75 ns;
+    trigger <= '1' after 10 ns, '0' after 20 ns,
+               '1' after 30 ns, '0' after 40 ns;
+    
+    wait;
+  end process stimulus_05_3_h_i_j;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_10.vhd
new file mode 100644
index 0000000..dba7d3f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_10.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_10.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_10 is
+
+end entity ch_05_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_10 is
+
+  signal data : bit_vector(7 downto 0) := X"FF";
+  signal s : bit := '0';
+
+begin
+
+
+  process_05_3_l : process is
+  begin
+    wait for 10 ns;
+
+    -- code from book:
+
+    data <= X"00";
+
+    -- end of code from book
+
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= '1';
+    -- . . .
+    if s = '1' then -- . . .
+      -- not in book
+      report "s is '1'";
+    else
+      report "s is '0'";
+    end if;
+    -- end not in boook
+
+    -- end of code from book
+
+    wait;
+  end process process_05_3_l;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd
new file mode 100644
index 0000000..ea1a103
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_11 is
+
+end entity ch_05_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_11 is
+
+  signal line_in, line_out : bit := '0';
+
+begin
+
+
+  -- code from book:
+
+  transmission_line : process (line_in) is
+  begin
+    line_out <= transport line_in after 500 ps;
+  end process transmission_line;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    line_in <= '1' after 2000 ps,
+               '0' after 4000 ps,
+               '1' after 6000 ps,
+               '0' after 6200 ps,
+               '1' after 8000 ps,
+               '0' after 8200 ps,
+               '1' after 8300 ps,
+               '0' after 8400 ps;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd
new file mode 100644
index 0000000..4e0b997
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_12 is
+
+end entity ch_05_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_12 is
+
+  signal top_a, bottom_a : bit := '0';
+  signal top_y, bottom_y : bit;
+
+begin
+
+
+  block_05_3_m : block is
+                         port ( a : in bit;  y : out bit := '1' );
+                       port map ( a => top_a, y => top_y );
+
+  begin
+
+    -- code from book:
+
+    inv : process (a) is
+    begin
+      y <= inertial not a after 3 ns;
+    end process inv;
+
+    -- end of code from book
+
+  end block block_05_3_m;
+
+
+  ----------------
+
+
+  block_05_3_n : block is
+                         port ( a : in bit;  y : out bit := '1' );
+                       port map ( a => bottom_a, y => bottom_y);
+
+  begin
+
+    -- code from book:
+
+    inv : process (a) is
+    begin
+      y <= reject 2 ns inertial not a after 3 ns;
+    end process inv;
+
+    -- end of code from book
+
+  end block block_05_3_n;
+
+
+  ----------------
+
+
+  stimulus_05_3_m_n : process is
+  begin
+    top_a <= '1' after 1 ns,
+             '0' after 6 ns,
+             '1' after 8 ns;
+    bottom_a <= '1' after 1 ns,
+                '0' after 6 ns,
+                '1' after 9 ns,
+                '0' after 11.5 ns,
+                '1' after 16 ns,
+                '0' after 18 ns,
+                '1' after 19 ns,
+                '0' after 20 ns;
+
+    wait;
+  end process stimulus_05_3_m_n;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_13.vhd
new file mode 100644
index 0000000..59c39e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_13.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_13 is
+
+end entity ch_05_13;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ch_05_13 is
+
+  signal s : std_ulogic;
+
+begin
+
+
+  process_05_3_o : process is
+  begin
+    s <= '1' after 11 ns,
+         'X' after 12 ns,
+         '1' after 14 ns,
+         '0' after 15 ns,
+         '1' after 16 ns,
+         '1' after 17 ns,
+         '1' after 20 ns,
+         '0' after 25 ns;
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= reject 5 ns inertial '1' after 8 ns;
+
+    -- end of code from book
+
+    wait;
+  end process process_05_3_o;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_14.vhd
new file mode 100644
index 0000000..8e54df6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_14.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_14 is
+
+end entity ch_05_14;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_14 is
+
+  signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
+
+begin
+
+
+  block_05_3_p : block is
+                         port ( next_PC : out integer );
+                       port map ( next_PC => functional_next_PC );
+  begin
+
+    -- code from book:
+
+    PC_incr : next_PC <= PC + 4 after 5 ns;
+
+    -- end of code from book
+
+  end block block_05_3_p;
+
+
+  ----------------
+
+
+  block_05_3_q : block is
+                         port ( next_PC : out integer );
+                       port map ( next_PC => equivalent_next_PC );
+  begin
+
+    -- code from book:
+
+    PC_incr : process is
+    begin
+      next_PC <= PC + 4 after 5 ns;
+      wait on PC;
+    end process PC_incr;
+
+    -- end of code from book
+
+  end block block_05_3_q;
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    for i in 1 to 10 loop
+      PC <= i after 20 ns;
+      wait for 20 ns;
+    end loop;
+    wait;
+  end process stimulus;
+
+  verifier :
+    assert functional_next_PC = equivalent_next_PC
+      report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_15.vhd
new file mode 100644
index 0000000..ce65681
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_15.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_15 is
+  generic ( extended_reset : boolean := false );
+end entity ch_05_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_15 is
+
+  signal functional_reset, equivalent_reset : bit := '0';
+
+begin
+
+
+  block_05_3_r : block is
+                         port ( reset : out bit );
+                       port map ( reset => functional_reset );
+  begin
+
+    -- code from book:
+
+    reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
+                         '1', '0' after 50 ns;
+
+    -- end of code from book
+
+  end block block_05_3_r;
+
+
+  ----------------
+
+
+  block_05_3_s : block is
+                         port ( reset : out bit );
+                       port map ( reset => equivalent_reset );
+  begin
+
+    -- code from book:
+
+    reset_gen : process is
+    begin
+      if extended_reset then
+        reset <= '1', '0' after 200 ns;
+      else
+        reset <= '1', '0' after 50 ns;
+      end if;
+      wait;
+    end process reset_gen;
+
+    -- end of code from book
+
+  end block block_05_3_s;
+
+
+  ----------------
+
+
+  verifier :
+    assert functional_reset = equivalent_reset
+      report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_16.vhd
new file mode 100644
index 0000000..2bb7ce4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_16.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_16 is
+
+end entity ch_05_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_16 is
+
+  constant Tpd_01 : time := 800 ps;
+  constant Tpd_10 : time := 500 ps;
+
+  signal a, z : bit;
+
+begin
+
+
+  -- code from book:
+
+  asym_delay : z <= transport a after Tpd_01 when a = '1' else
+                    a after Tpd_10;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    a <= '1' after 2000 ps,
+         '0' after 4000 ps,
+         '1' after 6000 ps,
+         '0' after 6200 ps;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd
new file mode 100644
index 0000000..ac43d35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_17.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_17 is
+
+end entity ch_05_17;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_17 is
+
+  signal s, r, q, q_n : bit := '0';
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+
+  -- code from book:
+
+  check : process is
+  begin
+    assert not (s = '1' and r = '1')
+      report "Incorrect use of S_R_flip_flop: s and r both '1'";
+    wait on s, r;
+  end process check;
+
+  -- end of code from book
+
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd
new file mode 100644
index 0000000..a4317ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity DRAM_controller is
+  port ( rd, wr, mem : in bit;
+         ras, cas, we, ready : out bit  );
+end entity DRAM_controller;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture fpld of DRAM_controller is
+begin
+end architecture fpld;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_18 is
+
+end entity ch_05_18;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_18 is
+
+
+
+begin
+
+
+  block_05_4_a : block is
+                         signal cpu_rd, cpu_wr, cpu_mem,
+                       mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+  begin
+
+    -- code from book:
+
+    main_mem_controller : entity work.DRAM_controller(fpld)
+      port map ( cpu_rd, cpu_wr, cpu_mem,
+                 mem_ras, mem_cas, mem_we, cpu_rdy );
+
+    -- end of code from book
+
+  end block block_05_4_a;
+
+
+  ----------------
+
+
+  block_05_4_b : block is
+                         signal cpu_rd, cpu_wr, cpu_mem,
+                       mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+  begin
+
+    -- code from book:
+
+    main_mem_controller : entity work.DRAM_controller(fpld)
+      port map ( rd => cpu_rd, wr => cpu_wr,
+                 mem => cpu_mem, ready => cpu_rdy,
+                 ras => mem_ras, cas => mem_cas, we => mem_we );
+
+    -- end of code from book
+
+  end block block_05_4_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_19.vhd
new file mode 100644
index 0000000..0c7a5cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_19.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_19.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_05_19 is
+
+  -- code from book:
+
+  subtype digit is bit_vector(3 downto 0);
+
+  -- end of code from book
+
+end package ch_05_19;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd
new file mode 100644
index 0000000..54f8ca9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package pk_05_20 is
+
+  -- code from book:
+
+  type FIFO_status is record
+                        nearly_full, nearly_empty, full, empty : bit;
+                      end record FIFO_status;
+
+  -- end of code from book
+
+end package pk_05_20;
+
+
+----------------------------------------------------------------
+
+
+use work.pk_05_20.all;
+
+entity FIFO is
+  port ( status : out FIFO_status;
+         other_ports : out bit );
+end entity FIFO;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_20 is
+
+end entity ch_05_20;
+
+
+----------------------------------------------------------------
+
+
+use work.pk_05_20.all;
+
+architecture test of ch_05_20 is
+
+  signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit;
+
+begin
+
+  -- code from book:
+
+  DMA_buffer : entity work.FIFO
+    port map ( -- . . ., 
+      status.nearly_full => start_flush,
+      status.nearly_empty => end_flush,
+      status.full => DMA_buffer_full,
+      status.empty => DMA_buffer_empty, -- . . . );
+      -- not in book
+      other_ports => open );
+  -- end not in book
+
+  -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_21.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_21.vhd
new file mode 100644
index 0000000..c53d4b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_21.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity and_gate is
+  port ( i : in bit_vector;  y : out bit );
+end entity and_gate;
+
+-- end of code from book
+
+architecture behavioral of and_gate is
+begin
+
+  reducer : process (i) is
+                          constant Tpd : delay_length := 2 ns;
+                        variable result : bit;
+  begin
+    result := '1';
+    for index in i'range loop
+      result := result and i(index);
+    end loop;
+    y <= result after Tpd;
+  end process reducer;
+
+end architecture behavioral;
+
+entity ch_05_21 is
+
+end entity ch_05_21;
+
+library stimulus;
+
+architecture test of ch_05_21 is
+
+  -- code from book:
+
+  signal serial_select, write_en, bus_clk, serial_wr : bit;
+
+  -- end of code from book
+
+  use stimulus.stimulus_generators.all;
+
+  signal test_input : bit_vector(2 downto 0);
+
+begin
+
+  -- code from book:
+
+  serial_write_gate : entity work.and_gate
+    port map ( i(1) => serial_select,
+               i(2) => write_en,
+               i(3) => bus_clk,
+               y => serial_wr );
+
+  -- end of code from book
+
+  stimulus : all_possible_values( bv => test_input,
+                                  delay_between_values => 10 ns );
+
+  (serial_select, write_en, bus_clk) <= test_input;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_22.vhd
new file mode 100644
index 0000000..bf12b3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_22.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity mux4 is
+  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+         z : out bit );
+end entity mux4;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of mux4 is
+begin
+
+  out_select : process (sel0, sel1, i0, i1, i2, i3) is
+                                                      subtype bits_2 is bit_vector(1 downto 0);
+  begin
+    case bits_2'(sel1, sel0) is
+      when "00" =>  z <= i0;
+      when "01" =>  z <= i1;
+      when "10" =>  z <= i2;
+      when "11" =>  z <= i3;
+    end case;
+  end process out_select;
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_22 is
+
+end entity ch_05_22;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_22 is
+
+  signal select_line, line0, line1, result_line : bit;
+
+begin
+
+
+  -- code from book:
+
+  a_mux : entity work.mux4
+    port map ( sel0 => select_line, i0 => line0, i1 => line1,
+               z => result_line,
+               sel1 => '0', i2 => '1', i3 => '1' );
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    wait for 5 ns;
+    line0 <= '1';				wait for 5 ns;
+    line1 <= '1';				wait for 5 ns;
+    select_line <= '1';	wait for 5 ns;
+    line1 <= '0';				wait for 5 ns;
+    line0 <= '0';				wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_23.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_23.vhd
new file mode 100644
index 0000000..858efe1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_23.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_23.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+         y : out bit );
+end entity and_or_inv;
+
+-- end of code from book
+
+architecture functional of and_or_inv is
+begin
+
+  func : y <= not ((a1 and a2) or (b1 and b2));
+
+end architecture functional;
+
+entity ch_05_23 is
+
+end entity ch_05_23;
+
+library stimulus;
+
+architecture test of ch_05_23 is
+
+  signal A, B, C, F : bit;
+  signal test_input : bit_vector(2 downto 0);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+  -- code from book:
+
+  f_cell : entity work.and_or_inv
+    port map (a1 => A, a2 => B, b1 => C, b2 => open, y => F);
+
+  -- end of code from book
+
+  stimulus : all_possible_values( bv => test_input,
+				  delay_between_values => 10 ns );
+
+  (A, B, C) <= test_input;
+
+  verifier :
+    postponed assert F = not ((A and B) or C)
+      report "function model produced unexpected result";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_24.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_24.vhd
new file mode 100644
index 0000000..f2ef085
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_24.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_24.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity and3 is
+  port ( a, b, c : in bit := '1';
+         z, not_z : out bit);
+end entity and3;
+
+-- end of code from book
+
+architecture functional of and3 is
+begin
+
+  non_inverting:
+    z <= a and b and c;
+
+  inverting:
+    not_z <= not (a and b and c);
+
+end architecture functional;
+
+entity ch_05_24 is
+
+end entity ch_05_24;
+
+library stimulus;
+
+architecture test of ch_05_24 is
+
+  signal s1, s2, ctrl1_a, ctrl1_b : bit;
+  signal test_input : bit_vector(1 to 2);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+
+  block_05_4_a : block is
+                         port ( ctrl1 : out bit );
+                       port map ( ctrl1 => ctrl1_a );
+  begin
+
+    -- code from book:
+
+    g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1);
+
+    -- end of code from book
+
+  end block block_05_4_a;
+
+  block_05_4_b : block is
+                         port ( ctrl1 : out bit );
+                       port map ( ctrl1 => ctrl1_b );
+  begin
+
+    -- code from book:
+
+    g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1,
+                                    c => open, z => open);
+
+    -- end of code from book
+
+  end block block_05_4_b;
+
+  stimulus : all_possible_values( bv => test_input,
+				  delay_between_values => 10 ns );
+
+  (s1, s2) <= test_input;
+
+  verifier :
+    assert ctrl1_a = ctrl1_b
+      report "versions differ";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd
new file mode 100644
index 0000000..d295388
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_25.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- VHDL-87
+
+
+entity mux4 is
+  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+         z : out bit );
+end mux4;
+
+
+----------------------------------------------------------------
+
+
+architecture functional of mux4 is
+begin
+
+  out_select : process (sel0, sel1, i0, i1, i2, i3)
+    subtype bits_2 is bit_vector(1 downto 0);
+  begin
+    case bits_2'(sel1, sel0) is
+      when "00" =>  z <= i0;
+      when "01" =>  z <= i1;
+      when "10" =>  z <= i2;
+      when "11" =>  z <= i3;
+    end case;
+  end process out_select;
+
+end functional;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_25 is
+
+end ch_05_25;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_25 is
+
+  signal select_line, line0, line1, result_line : bit;
+
+  -- code from book:
+
+  signal tied_0 : bit := '0';
+  signal tied_1 : bit := '1';
+
+  -- end of code from book
+
+  component mux4
+    port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+           z : out bit );
+  end component;
+
+  for all : mux4
+    use entity work.mux4;
+
+begin
+
+
+  a_mux : mux4
+
+    -- code from book:
+
+    port map ( sel0 => select_line, i0 => line0, i1 => line1,
+               z => result_line,
+               sel1 => tied_0, i2 => tied_1, i3 => tied_1 );
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process
+  begin
+    wait for 5 ns;
+    line0 <= '1';				wait for 5 ns;
+    line1 <= '1';				wait for 5 ns;
+    select_line <= '1';	wait for 5 ns;
+    line1 <= '0';				wait for 5 ns;
+    line0 <= '0';				wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+
+end test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_26.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_26.vhd
new file mode 100644
index 0000000..988994e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_26.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_26.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_26 is
+end entity ch_05_26;
+
+-- code from book:
+
+library widget_cells, wasp_lib;
+
+use widget_cells.reg32;
+
+-- end of code from book
+
+
+architecture test of ch_05_26 is
+
+  signal filter_clk, accum_en : bit;
+  signal sum, result : bit_vector(31 downto 0);
+
+begin
+
+
+  -- code from book:
+
+  accum : entity reg32
+    port map ( en => accum_en, clk => filter_clk, d => sum,
+               q => result );
+
+  -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_27.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_27.vhd
new file mode 100644
index 0000000..52727c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_27.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_27.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_27 is
+end entity ch_05_27;
+
+library wasp_lib;
+
+-- code from book:
+use wasp_lib.all;
+-- end of code from book
+
+architecture test of ch_05_27 is
+
+  signal clk, filter_clk : bit;
+
+begin
+
+  clk_pad : entity wasp_lib.in_pad
+    port map ( i => clk, z => filter_clk );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_01.vhd
new file mode 100644
index 0000000..86b9932
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_01.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+-- end not in book
+
+
+               entity program_ROM is
+                 port ( address : in std_ulogic_vector(14 downto 0);
+                        data : out std_ulogic_vector(7 downto 0);
+                        enable : in std_ulogic );
+
+                 subtype instruction_byte is bit_vector(7 downto 0);
+                 type program_array is array (0 to 2**14 - 1) of instruction_byte;
+                 constant program : program_array
+                   := ( X"32", X"3F", X"03",  -- LDA  $3F03
+                        X"71", X"23",         -- BLT    $23
+                        -- not in book
+                        others => X"00"
+                        -- end not in book
+                        -- . . .
+                        );
+
+               end entity program_ROM;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_02.vhd
new file mode 100644
index 0000000..6473ed1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_02.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture primitive of and_or_inv is
+
+  signal and_a, and_b : bit;
+  signal or_a_b : bit;
+
+begin
+
+  and_gate_a : process (a1, a2) is
+  begin
+    and_a <= a1 and a2;
+  end process and_gate_a;
+
+  and_gate_b : process (b1, b2) is
+  begin
+    and_b <= b1 and b2;
+  end process and_gate_b;
+
+  or_gate : process (and_a, and_b) is
+  begin
+    or_a_b <= and_a or and_b;
+  end process or_gate;
+
+  inv : process (or_a_b) is
+  begin
+    y <= not or_a_b;
+  end process inv;
+
+end architecture primitive;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_03.vhd
new file mode 100644
index 0000000..46e7b63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_03.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_03 is
+end entity fg_05_03;
+
+architecture test of fg_05_03 is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process (clk) is
+  begin
+    if clk = '0' then
+      clk <= '1' after T_pw, '0' after 2*T_pw;
+    end if;
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd
new file mode 100644
index 0000000..b4885e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_04 is
+end entity fg_05_04;
+
+architecture test of fg_05_04 is
+
+  constant prop_delay : time := 5 ns;
+
+  signal a, b, sel, z : bit;
+
+begin
+
+  -- code from book
+
+  mux : process (a, b, sel) is
+  begin
+    case sel is
+      when '0' =>
+	z <= a after prop_delay;
+      when '1' =>
+	z <= b after prop_delay;
+    end case;
+  end process mux;
+
+  -- end code from book
+
+
+  stimulus : process is
+                       subtype stim_vector_type is bit_vector(0 to 3);
+                     type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+                     constant stim_vector : stim_vector_array
+                       := ( "0000",
+                            "0010",
+                            "0100",
+                            "0111",
+                            "1001",
+                            "1010",
+                            "1101",
+                            "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a, b, sel) <= stim_vector(i)(0 to 2);
+      wait for 10 ns;
+      assert z = stim_vector(i)(3);
+    end loop;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_05.vhd
new file mode 100644
index 0000000..ce2ff17
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_05.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_05.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity edge_triggered_Dff is
+  port ( D : in bit;  clk : in bit;  clr : in bit;
+  Q : out bit );
+end entity edge_triggered_Dff;
+
+architecture behavioral of edge_triggered_Dff is
+begin
+
+  state_change : process (clk, clr) is
+  begin
+    if clr = '1' then
+      Q <= '0' after 2 ns;
+    elsif clk'event and clk = '1' then
+      Q <= D after 2 ns;
+    end if;
+  end process state_change;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd
new file mode 100644
index 0000000..995f997
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity mux2 is
+  port ( a, b, sel : in bit;
+         z : out bit );
+end entity mux2;
+
+--------------------------------------------------
+
+architecture behavioral of mux2 is
+
+  constant prop_delay : time := 2 ns;
+
+begin
+
+  slick_mux : process is
+  begin
+    case sel is
+      when '0' =>
+        z <= a after prop_delay;
+        wait on sel, a;
+      when '1' =>
+        z <= b after prop_delay;
+        wait on sel, b;
+    end case;
+  end process slick_mux;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_07.vhd
new file mode 100644
index 0000000..2197e8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_07.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_07 is
+end entity fg_05_07;
+
+architecture test of fg_05_07 is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process is
+  begin
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+    wait until clk = '0';
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_08.vhd
new file mode 100644
index 0000000..c2406c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_08.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_08 is
+end entity fg_05_08;
+
+architecture test of fg_05_08 is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process is
+  begin
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+    wait for 2*T_pw;
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_09.vhd
new file mode 100644
index 0000000..1d5119a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_09.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture abstract of computer_system is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address : natural;
+  signal read_data, write_data : word;
+  signal mem_read, mem_write : bit := '0';
+  signal mem_ready : bit := '0';
+
+begin
+
+  cpu : process is
+                  variable instr_reg : word;
+                variable PC : natural;
+                -- . . .    -- other declarations
+  begin
+    loop
+      address <= PC;
+      mem_read <= '1';
+      wait until mem_ready = '1';
+      instr_reg := read_data;
+      mem_read <= '0';
+      wait until mem_ready = '0';
+      PC := PC + 4;
+      -- . . .    -- execute the instruction
+    end loop;
+  end process cpu;
+
+  memory : process is
+                     type memory_array is array (0 to 2**14 - 1) of word;
+                   variable store : memory_array := (
+                     -- . . .
+                     -- not in book
+                     0 => X"0000_0000",
+                     1 => X"0000_0004",
+                     2 => X"0000_0008",
+                     3 => X"0000_000C",
+                     4 => X"0000_0010",
+                     5 => X"0000_0014",
+                     others => X"0000_0000"
+				        -- end not in book
+                     );
+  begin
+    wait until mem_read = '1' or mem_write = '1';
+    if mem_read = '1' then
+      read_data <= store( address / 4 );
+      mem_ready <= '1';
+      wait until mem_read = '0';
+      mem_ready <= '0';
+    else
+      -- . . .    -- perform write access
+    end if;
+  end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd
new file mode 100644
index 0000000..0aca507
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_12 is
+end entity fg_05_12;
+
+
+
+architecture test of fg_05_12 is
+
+  signal a, z : bit;
+
+begin
+
+  -- code from book
+
+  asym_delay : process (a) is
+                             constant Tpd_01 : time := 800 ps;
+                           constant Tpd_10 : time := 500 ps;
+  begin
+    if a = '1' then
+      z <= transport a after Tpd_01;
+    else  -- a = '0'
+      z <= transport a after Tpd_10;
+    end if;
+  end process asym_delay;
+
+  -- end code from book
+
+
+  stimulus : process is
+  begin
+    a <= '1' after 2000 ps,
+         '0' after 4000 ps,
+         '1' after 6000 ps,
+         '0' after 6200 ps;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd
new file mode 100644
index 0000000..953f982
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity and2 is
+                 port ( a, b : in std_ulogic;  y : out std_ulogic );
+               end entity and2;
+
+--------------------------------------------------
+
+               architecture detailed_delay of and2 is
+
+                 signal result : std_ulogic;
+
+               begin
+
+                 gate : process (a, b) is
+                 begin
+                   result <= a and b;
+                 end process gate;
+
+                 delay : process (result) is
+                 begin
+                   if result = '1' then
+                     y <= reject 400 ps inertial '1' after 1.5 ns;
+                   elsif result = '0' then
+                     y <= reject 300 ps inertial '0' after 1.2 ns;
+                   else
+                     y <= reject 300 ps inertial 'X' after 500 ps;
+                   end if;
+                 end process delay;
+
+               end architecture detailed_delay;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_17.vhd
new file mode 100644
index 0000000..52c312b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_17.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_17.vhd,v 1.5 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.5 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_17 is
+end entity fg_05_17;
+
+library stimulus;
+
+architecture test of fg_05_17 is
+
+  use stimulus.stimulus_generators.all;
+
+  signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+  signal functional_z, equivalent_z : bit;
+
+begin
+
+  functional_mux : block is
+                           port ( z : out bit );
+                         port map ( z => functional_z );
+  begin
+
+    -- code from book
+
+    zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+                d1 when sel1 = '0' and sel0 = '1' else
+                d2 when sel1 = '1' and sel0 = '0' else
+                d3 when sel1 = '1' and sel0 = '1';
+
+    -- end code from book
+
+  end block functional_mux;
+
+  equivalent_mux : block is
+                           port ( z : out bit );
+                         port map ( z => equivalent_z );
+  begin
+
+    -- code from book
+
+    zmux : process is
+    begin
+      if sel1 = '0' and sel0 = '0' then
+        z <= d0;
+      elsif sel1 = '0' and sel0 = '1' then
+        z <= d1;
+      elsif sel1 = '1' and sel0 = '0' then
+        z <= d2;
+      elsif sel1 = '1' and sel0 = '1' then
+        z <= d3;
+      end if;
+      wait on d0, d1, d2, d3, sel0, sel1;
+    end process zmux;
+
+    -- end code from book
+
+  end block equivalent_mux;
+
+  stimulus :
+    all_possible_values( bv(0) => sel0, bv(1) => sel1,
+			 bv(2) => d0, bv(3) => d1,
+			 bv(4) => d2, bv(5) => d3,
+			 delay_between_values => 10 ns );
+
+  verifier :
+    assert functional_z = equivalent_z
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_18.vhd
new file mode 100644
index 0000000..8b6e22f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_18.vhd,v 1.5 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.5 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_18 is
+end entity fg_05_18;
+
+library stimulus;
+
+architecture test of fg_05_18 is
+
+  use stimulus.stimulus_generators.all;
+
+  signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+  signal functional_z, equivalent_z : bit;
+
+begin
+
+  functional_mux : block is
+                           port ( z : out bit );
+                         port map ( z => functional_z );
+  begin
+
+    -- code from book
+
+    zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+                d1 when sel1 = '0' and sel0 = '1' else
+                d2 when sel1 = '1' and sel0 = '0' else
+                d3;
+
+    -- end code from book
+
+  end block functional_mux;
+
+  equivalent_mux : block is
+                           port ( z : out bit );
+                         port map ( z => equivalent_z );
+  begin
+
+    -- code from book
+
+    zmux : process is
+    begin
+      if sel1 = '0' and sel0 = '0' then
+        z <= d0;
+      elsif sel1 = '0' and sel0 = '1' then
+        z <= d1;
+      elsif sel1 = '1' and sel0 = '0' then
+        z <= d2;
+      else
+        z <= d3;
+      end if;
+      wait on d0, d1, d2, d3, sel0, sel1;
+    end process zmux;
+
+    -- end code from book
+
+  end block equivalent_mux;
+
+  stimulus :
+    all_possible_values( bv(0) => sel0, bv(1) => sel1,
+			 bv(2) => d0, bv(3) => d1,
+			 bv(4) => d2, bv(5) => d3,
+			 delay_between_values => 10 ns );
+
+  verifier :
+    assert functional_z = equivalent_z
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd
new file mode 100644
index 0000000..99e4c16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_19 is
+end entity fg_05_19;
+
+
+architecture test of fg_05_19 is
+
+  constant scheduling_delay : delay_length := 5 ns;
+
+  subtype request_type is natural range 0 to 20;
+  type server_status_type is (ready, busy);
+
+  signal first_priority_request,
+    first_normal_request,
+    reset_request : request_type := 0;
+  signal functional_request, equivalent_request : request_type;
+  signal priority_waiting : boolean := false;
+  signal server_status : server_status_type := busy;
+
+begin
+
+  functional_scheduler : block is
+                                 port ( request : out request_type );
+                               port map ( request => functional_request );
+  begin
+
+    -- code from book
+
+    scheduler :
+      request <= first_priority_request after scheduling_delay
+                 when priority_waiting and server_status = ready else
+                 first_normal_request after scheduling_delay
+                 when not priority_waiting and server_status = ready else
+                 unaffected
+                 when server_status = busy else
+                 reset_request after scheduling_delay;
+
+    -- end code from book
+
+  end block functional_scheduler;
+
+  --------------------------------------------------
+
+  equivalent_scheduler : block is
+                                 port ( request : out request_type );
+                               port map ( request => equivalent_request );
+  begin
+
+    -- code from book
+
+    scheduler : process is
+    begin
+      if priority_waiting and server_status = ready then
+        request <= first_priority_request after scheduling_delay;
+      elsif not priority_waiting and server_status = ready then
+        request <= first_normal_request after scheduling_delay;
+      elsif server_status = busy then
+        null;
+      else
+        request <= reset_request after scheduling_delay;
+      end if;
+      wait on first_priority_request, priority_waiting, server_status,
+        first_normal_request, reset_request;
+    end process scheduler;
+
+    -- end code from book
+
+  end block equivalent_scheduler;
+
+  --------------------------------------------------
+
+  stimulus : process is
+  begin
+    first_priority_request <= 10;	wait for 20 ns;
+    first_normal_request <= 5;		wait for 20 ns;
+    server_status <= ready;		wait for 20 ns;
+    server_status <= busy;		wait for 20 ns;
+    priority_waiting <= true;		wait for 20 ns;
+    server_status <= ready;		wait for 20 ns;
+    first_normal_request <= 7;		wait for 20 ns;
+    first_priority_request <= 12;	wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  verifier :
+    assert functional_request = equivalent_request
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_20.vhd
new file mode 100644
index 0000000..8c39d0d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_20.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_20 is
+end entity fg_05_20;
+
+
+architecture test of fg_05_20 is
+
+  constant Tpd : delay_length := 2 ns;
+
+  function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(1 to bv1'length) is bv1;
+    alias op2 : bit_vector(1 to bv2'length) is bv2;  
+    variable result : bit_vector(1 to bv1'length);
+    variable carry_in : bit;
+    variable carry_out : bit := '0';
+
+  begin
+    for index in result'reverse_range loop
+      carry_in := carry_out;  -- of previous bit
+      result(index) := op1(index) xor op2(index) xor carry_in;
+      carry_out := (op1(index) and op2(index))
+      	      	   or (carry_in and (op1(index) xor op2(index)));
+    end loop;
+    return result;
+  end function "+";
+
+  function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+    alias op1 : bit_vector(1 to bv1'length) is bv1;
+    alias op2 : bit_vector(1 to bv2'length) is bv2;  
+    variable result : bit_vector(1 to bv1'length);
+    variable carry_in : bit;
+    variable carry_out : bit := '1';
+
+  begin
+    for index in result'reverse_range loop
+      carry_in := carry_out;  -- of previous bit
+      result(index) := op1(index) xor (not op2(index)) xor carry_in;
+      carry_out := (op1(index) and (not op2(index)))
+      	      	   or (carry_in and (op1(index) xor (not op2(index))));
+    end loop;
+    return result;
+  end function "-";
+
+  type alu_function_type is (alu_pass_a, alu_add, alu_sub,
+			     alu_add_unsigned, alu_sub_unsigned,
+			     alu_and, alu_or);
+
+  signal alu_function : alu_function_type := alu_pass_a;
+  signal a, b : bit_vector(15 downto 0);
+  signal functional_result, equivalent_result : bit_vector(15 downto 0);
+
+begin
+
+  functional_alu : block is
+                           port ( result : out bit_vector(15 downto 0) );
+                         port map ( result => functional_result );
+  begin
+
+    -- code from book
+
+    alu : with alu_function select
+      result <=  a + b after Tpd   when alu_add | alu_add_unsigned,
+      a - b after Tpd   when alu_sub | alu_sub_unsigned,
+      a and b after Tpd when alu_and,
+      a or b after Tpd  when alu_or,
+      a after Tpd       when alu_pass_a;
+
+    -- end code from book
+
+  end block functional_alu;
+
+  --------------------------------------------------
+  
+  equivalent_alu : block is
+                           port ( result : out bit_vector(15 downto 0) );
+                         port map ( result => equivalent_result );
+  begin
+
+    -- code from book
+
+    alu : process is
+    begin
+      case alu_function is
+        when alu_add | alu_add_unsigned =>  result <= a + b after Tpd;
+        when alu_sub | alu_sub_unsigned =>  result <= a - b after Tpd;
+        when alu_and                    =>  result <= a and b after Tpd;
+        when alu_or                     =>  result <= a or b after Tpd;
+        when alu_pass_a                 =>  result <= a after Tpd;
+      end case;
+      wait on alu_function, a, b;
+    end process alu;
+
+    -- end code from book
+
+  end block equivalent_alu;
+
+  --------------------------------------------------
+
+  stimulus : process is
+  begin
+    alu_function <= alu_add;	wait for 10 ns;
+    a <= X"000A";		wait for 10 ns;
+    b <= X"0003";		wait for 10 ns;
+    alu_function <= alu_sub;	wait for 10 ns;
+    alu_function <= alu_and;	wait for 10 ns;
+    alu_function <= alu_or;	wait for 10 ns;
+    alu_function <= alu_pass_a;	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  verifier :
+    assert functional_result = equivalent_result
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_21.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_21.vhd
new file mode 100644
index 0000000..72eba37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_21.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity full_adder is
+  port ( a, b, c_in : bit;  s, c_out : out bit );
+end entity full_adder;
+
+architecture truth_table of full_adder is
+begin
+
+  with bit_vector'(a, b, c_in) select
+    (c_out, s) <= bit_vector'("00") when "000",
+    bit_vector'("01") when "001",
+    bit_vector'("01") when "010",
+    bit_vector'("10") when "011",
+    bit_vector'("01") when "100",
+    bit_vector'("10") when "101",
+    bit_vector'("10") when "110",
+    bit_vector'("11") when "111";
+
+end architecture truth_table;
+
+-- not in book
+
+entity fg_05_21 is
+end entity fg_05_21;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of fg_05_21 is
+
+  signal a, b, c_in, s, c_out : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  dut : entity work.full_adder
+    port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out );
+
+  all_possible_values ( test_vector, 10 ns );
+
+  (a, b, c_in) <= test_vector;
+
+end architecture test;
+
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd
new file mode 100644
index 0000000..b0bbd0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity S_R_flipflop is
+  port ( s, r : in bit;  q, q_n : out bit );
+end entity S_R_flipflop;
+
+--------------------------------------------------
+
+architecture functional of S_R_flipflop is
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+  check : assert not (s = '1' and r = '1')
+    report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end architecture functional;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd
new file mode 100644
index 0000000..70e4026
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_23.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity S_R_flipflop is
+  port ( s, r : in bit;  q, q_n : out bit );
+
+begin
+
+  check : assert not (s = '1' and r = '1')
+    report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end entity S_R_flipflop;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd
new file mode 100644
index 0000000..5c4e06c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_24.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ROM is
+  port ( address : in natural;
+         data : out bit_vector(0 to 7);
+         enable : in bit );
+
+begin
+
+  trace_reads : process (enable) is
+  begin
+    if enable = '1' then
+      report "ROM read at time " & time'image(now)
+        & " from address " & natural'image(address);
+    end if;
+  end process trace_reads;
+
+end entity ROM;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd
new file mode 100644
index 0000000..a608cc4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity reg4 is
+  port ( clk, clr, d0, d1, d2, d3 : in bit;
+         q0, q1, q2, q3 : out bit );
+end entity reg4;
+
+architecture struct of reg4 is
+begin
+
+  bit0 : entity work.edge_triggered_Dff(behavioral)
+    port map (d0, clk, clr, q0);
+  bit1 : entity work.edge_triggered_Dff(behavioral)
+    port map (d1, clk, clr, q1);
+  bit2 : entity work.edge_triggered_Dff(behavioral)
+    port map (d2, clk, clr, q2);
+  bit3 : entity work.edge_triggered_Dff(behavioral)
+    port map (d3, clk, clr, q3);
+
+end architecture struct;
+
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_27.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_27.vhd
new file mode 100644
index 0000000..c4596e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_27.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_27.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.counter_types.all;
+
+-- end not in book
+
+
+entity counter is
+  port ( clk, clr : in bit;
+         q0, q1 : out digit );
+end entity counter;
+
+--------------------------------------------------
+
+architecture registered of counter is
+
+  signal current_val0, current_val1, next_val0, next_val1 : digit;
+
+begin
+
+  val0_reg : entity work.reg4(struct)
+    port map ( d0 => next_val0(0), d1 => next_val0(1),
+               d2 => next_val0(2), d3 => next_val0(3),
+               q0 => current_val0(0), q1 => current_val0(1),
+               q2 => current_val0(2), q3 => current_val0(3),
+               clk => clk, clr => clr );
+
+  val1_reg : entity work.reg4(struct)
+    port map ( d0 => next_val1(0), d1 => next_val1(1),
+               d2 => next_val1(2), d3 => next_val1(3),
+               q0 => current_val1(0), q1 => current_val1(1),
+               q2 => current_val1(2), q3 => current_val1(3),
+               clk => clk, clr => clr );
+
+  incr0 : entity work.add_1(boolean_eqn) -- . . .;
+    -- not in book
+    port map ( d0 => current_val0(0), d1 => current_val0(1),
+               d2 => current_val0(2), d3 => current_val0(3),
+	       y0 => next_val0(0), y1 => next_val0(1),
+               y2 => next_val0(2), y3 => next_val0(3) );
+  -- end not in book
+
+  incr1 : entity work.add_1(boolean_eqn) -- . . .;
+    -- not in book
+    port map ( d0 => current_val1(0), d1 => current_val1(1),
+               d2 => current_val1(2), d3 => current_val1(3),
+	       y0 => next_val1(0), y1 => next_val1(1),
+               y2 => next_val1(2), y3 => next_val1(3) );
+  -- end not in book
+
+  buf0 : entity work.buf4(basic) -- . . .;
+    -- not in book
+    port map ( a0 => current_val0(0), a1 => current_val0(1),
+               a2 => current_val0(2), a3 => current_val0(3),
+	       y0 => q0(0), y1 => q0(1),
+               y2 => q0(2), y3 => q0(3) );
+  -- end not in book
+
+  buf1 : entity work.buf4(basic) -- . . .;
+    -- not in book
+    port map ( a0 => current_val1(0), a1 => current_val1(1),
+               a2 => current_val1(2), a3 => current_val1(3),
+	       y0 => q1(0), y1 => q1(1),
+               y2 => q1(2), y3 => q1(3) );
+  -- end not in book
+
+end architecture registered;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_28.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_28.vhd
new file mode 100644
index 0000000..78ebc0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_28.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_28.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity reg is
+  port ( d : in bit_vector(7 downto 0);
+         q : out bit_vector(7 downto 0);
+         clk : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+-- not in book
+
+entity microprocessor is
+end entity microprocessor;
+
+-- end not in book
+
+architecture RTL of microprocessor is
+
+  signal interrupt_req : bit;
+  signal interrupt_level : bit_vector(2 downto 0);
+  signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
+  signal program_status : bit_vector(7 downto 0);
+  signal clk_PSR : bit;
+  -- . . .
+
+begin
+
+  PSR : entity work.reg
+    port map ( d(7) => interrupt_req,
+               d(6 downto 4) => interrupt_level,
+               d(3) => carry_flag,     d(2) => negative_flag,
+               d(1) => overflow_flag,  d(0) => zero_flag,
+               q => program_status,
+               clk => clk_PSR );
+  -- . . .
+
+end architecture RTL;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_30.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_30.vhd
new file mode 100644
index 0000000..4237bc8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_30.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_30.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+library widget_cells, wasp_lib;
+
+architecture cell_based of filter is
+
+  -- declaration of signals, etc
+  -- . . .
+
+  -- not in book
+
+  signal clk, filter_clk, accum_en, carry : bit;
+  signal sum, alu_op1, alu_op2, result : bit_vector(31 downto 0);
+
+  -- end not in book
+
+begin
+
+  clk_pad : entity wasp_lib.in_pad
+    port map ( i => clk, z => filter_clk );
+
+  accum : entity widget_cells.reg32
+    port map ( en => accum_en, clk => filter_clk, d => sum,
+               q => result );
+
+  alu : entity work.adder
+    port map ( a => alu_op1, b => alu_op2, y => sum, c => carry );
+
+  -- other component instantiations
+  -- . . .
+
+end architecture cell_based;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_pk_test.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_pk_test.vhd
new file mode 100644
index 0000000..0771d81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_pk_test.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_pk_test.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package stimulus_generators is
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length );
+
+end package stimulus_generators;
+
+package body stimulus_generators is
+
+  type digit_table is array ( natural range 0 to 1 ) of bit;
+  constant digit : digit_table := ( '0', '1' );
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : natural := nat;
+    variable result : bit_vector(0 to length - 1);
+
+  begin
+    for index in result'reverse_range loop
+      result(index) := digit( temp rem 2 );
+      temp := temp / 2;
+    end loop;
+    return result;
+  end function natural_to_bv;
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= natural_to_bv(0, bv'length);
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= natural_to_bv(value, bv'length);
+    end loop;
+  end procedure all_possible_values;
+
+end package body stimulus_generators;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_01.vhd
new file mode 100644
index 0000000..764d324
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_01.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+	 y : out bit );
+end entity and_or_inv;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd
new file mode 100644
index 0000000..f3e942e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_02 is
+end entity tb_05_02;
+
+
+architecture test of tb_05_02 is
+
+  signal a1, a2, b1, b2, y : bit;
+
+begin
+
+  dut : entity work.and_or_inv(primitive)
+    port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
+	       y => y );
+
+  stimulus : process is
+                       subtype stim_vector_type is bit_vector(0 to 3);
+                     type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+                     constant stim_vector : stim_vector_array
+                       := ( "0000",
+                            "0001",
+                            "0010",
+                            "0011",
+                            "0100",
+                            "0101",
+                            "0110",
+                            "0111",
+                            "1000",
+                            "1001",
+                            "1010",
+                            "1011",
+                            "1100",
+                            "1101",
+                            "1110",
+                            "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a1, a2, b1, b2) <= stim_vector(i);
+      wait for 10 ns;
+      assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
+	               or (stim_vector(i)(2) and stim_vector(i)(3)) );
+    end loop;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_03.vhd
new file mode 100644
index 0000000..0539399
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_03.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_03 is
+end entity tb_05_03;
+
+
+architecture test of tb_05_03 is
+
+  signal D, clk, clr, Q : bit := '0';
+
+begin
+
+  dut : entity work.edge_triggered_Dff(behavioral)
+    port map ( D => D, clk => clk, clr => clr,
+	       Q => Q );
+
+  stimulus : process is
+  begin
+    D <= '1';	wait for 10 ns;
+    clk <= '1';	wait for 10 ns;
+    D <= '0';	wait for 10 ns;
+    clk <= '0';	wait for 10 ns;
+    D <= '1';	wait for 10 ns;
+    clr <= '1';	wait for 10 ns;
+    clk <= '1';	wait for 10 ns;
+    clr <= '0';	wait for 10 ns;
+    clk <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_04.vhd
new file mode 100644
index 0000000..0eb5f3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_04.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_04 is
+end entity tb_05_04;
+
+architecture test of tb_05_04 is
+
+  signal a, b, sel, z : bit;
+
+begin
+
+  dut : entity work.mux2(behavioral)
+    port map ( a => a, b => b, sel => sel, z => z );
+
+  stimulus : process is
+                       subtype stim_vector_type is bit_vector(0 to 3);
+                     type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+                     constant stim_vector : stim_vector_array
+                       := ( "0000",
+                            "0100",
+                            "1001",
+                            "1101",
+                            "0010",
+                            "0111",
+                            "1010",
+                            "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a, b, sel) <= stim_vector(i)(0 to 2);
+      wait for 10 ns;
+      assert z = stim_vector(i)(3);
+    end loop;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_05.vhd
new file mode 100644
index 0000000..1c90118
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_05.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_05 is
+end entity tb_05_05;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of tb_05_05 is
+
+  signal a, b : std_ulogic := '0';
+  signal y : std_ulogic;
+
+begin
+
+  dut : entity work.and2(detailed_delay)
+    port map ( a => a, b => b, y => y );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    a <= '1';	wait for 10 ns;
+    b <= '1';	wait for 10 ns;
+    b <= '0';	wait for 10 ns;
+
+    b <= '1', '0' after  250 ps;   wait for 10 ns;
+    b <= '1', '0' after  350 ps;   wait for 10 ns;
+    b <= '1', '0' after  450 ps;   wait for 10 ns;
+    b <= '1', '0' after  550 ps;   wait for 10 ns;
+    b <= '1', '0' after  650 ps;   wait for 10 ns;
+    b <= '1', '0' after  750 ps;   wait for 10 ns;
+    b <= '1', '0' after  850 ps;   wait for 10 ns;
+
+    b <= '1';	wait for 10 ns;
+    b <= '0', '1' after  250 ps;   wait for 10 ns;
+    b <= '0', '1' after  350 ps;   wait for 10 ns;
+    b <= '0', '1' after  450 ps;   wait for 10 ns;
+
+    b <= 'X';  wait for 10 ns;
+    b <= '0';  wait for 10 ns;
+    b <= 'X', '0' after 250 ps;   wait for 10 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_06.vhd
new file mode 100644
index 0000000..22e466d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_06.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_06 is
+end entity tb_05_06;
+
+
+architecture test of tb_05_06 is
+
+  signal s, r : bit := '0';
+  signal q, q_n : bit;
+
+begin
+
+  dut : entity work.S_R_flipflop(functional)
+    port map ( s => s, r => r, q => q, q_n => q_n );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd
new file mode 100644
index 0000000..8e4ecdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture functional of S_R_flipflop is
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+end architecture functional;
+
+
+entity tb_05_07 is
+end entity tb_05_07;
+
+
+architecture test of tb_05_07 is
+
+  signal s, r : bit := '0';
+  signal q, q_n : bit;
+
+begin
+
+  dut : entity work.S_R_flipflop(functional)
+    port map ( s => s, r => r, q => q, q_n => q_n );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd
new file mode 100644
index 0000000..09be1b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture do_nothing of ROM is
+begin
+end architecture do_nothing;
+
+
+entity tb_05_08 is
+end entity tb_05_08;
+
+
+architecture test of tb_05_08 is
+
+  signal address : natural := 0;
+  signal data : bit_vector(0 to 7);
+  signal enable : bit := '0';
+
+begin
+
+  dut : entity work.ROM(do_nothing)
+    port map ( address => address, data => data, enable => enable );
+
+  stimulus : process is
+  begin
+    wait for 100 ns;
+    address <= 1000;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+    address <= 1004;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+    address <= 1008;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_09.vhd
new file mode 100644
index 0000000..67ea946
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_09.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_09 is
+end entity tb_05_09;
+
+
+architecture test of tb_05_09 is
+
+  signal clk, clr, d0, d1, d2, d3 : bit := '0';
+  signal q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(struct)
+    port map ( clk => clk, clr => clr,
+	       d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+	       q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+  stimulus : process is
+  begin
+    (d3, d2, d1, d0) <= bit_vector'(b"1010");	wait for 10 ns;
+    clk <= '1';					wait for 10 ns;
+    (d3, d2, d1, d0) <= bit_vector'(b"0101");	wait for 10 ns;
+    clk <= '0';					wait for 10 ns;
+    (d3, d2, d1, d0) <= bit_vector'(b"1111");	wait for 10 ns;
+    clr <= '1';					wait for 10 ns;
+    clk <= '1';					wait for 10 ns;
+    clr <= '0';					wait for 10 ns;
+    clk <= '0';					wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd
new file mode 100644
index 0000000..9a82004
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity add_1 is
+  port ( d0, d1, d2, d3 : in bit;
+         y0, y1, y2, y3 : out  bit );
+end entity add_1;
+
+
+architecture boolean_eqn of add_1 is
+begin
+
+  y0 <= not d0 after 4 ns;
+
+  y1 <= (not d1 and d0)
+        or (d1 and not d0) after 4 ns;
+
+  y2 <= (not d2 and d1 and d0)
+	or (d2 and not (d1 and d0)) after 4 ns;
+
+  y3 <= (not d3 and d2 and d1 and d0)
+	or (d3 and not (d2 and d1 and d0)) after 4 ns;
+
+end architecture boolean_eqn;
+
+
+entity buf4 is
+  port ( a0, a1, a2, a3 : in bit;
+         y0, y1, y2, y3 : out  bit );
+end entity buf4;
+
+
+architecture basic of buf4 is
+begin
+
+  y0 <= a0 after 2 ns;
+  y1 <= a1 after 2 ns;
+  y2 <= a2 after 2 ns;
+  y3 <= a3 after 2 ns;
+
+end architecture basic;
+
+
+package counter_types is
+
+  subtype digit is bit_vector(3 downto 0);
+
+end package counter_types;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_11.vhd
new file mode 100644
index 0000000..4c11758
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_11.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_11 is
+end entity tb_05_11;
+
+
+use work.counter_types.all;
+
+architecture test of tb_05_11 is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : entity work.counter(registered)
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd
new file mode 100644
index 0000000..2410f1c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity in_pad is
+  port ( i : in bit;  z : out bit );
+end entity in_pad;
+
+
+entity reg32 is
+  port ( en : in bit;  clk : in bit;  d : in bit_vector(31 downto 0);
+  q : out bit_vector(31 downto 0) );
+end entity reg32;
+
+
+entity adder is
+  port ( a, b : in bit_vector(31 downto 0);
+         y : out bit_vector(31 downto 0);
+	 c : out bit );
+end entity adder;
+
+
+entity filter is
+end entity filter;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd
new file mode 100644
index 0000000..337443a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_13.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package tb_05_13 is
+
+  subtype word is integer;
+
+end package tb_05_13;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca-b.vhd
new file mode 100644
index 0000000..dbdeec0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca-b.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_acca-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of accumulator_adder is
+begin
+
+  behavior : process (a, b) is
+
+                              constant Tpd_in_out : time := 3 ns;
+                            variable carry_in : std_ulogic;
+                            variable carry_out : std_ulogic := '0';
+
+  begin
+    for index in 0 to 21 loop
+      carry_in := carry_out;  -- of previous bit
+      s(index) <= a(index) xor b(index) xor carry_in after Tpd_in_out;
+      carry_out := (a(index) and b(index))
+      	      	   or (carry_in and (a(index) xor b(index)));
+    end loop;
+    ovf <= carry_out xor carry_in after Tpd_in_out;  -- ovf is carry_out /= carry_in
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca.vhd
new file mode 100644
index 0000000..450ca29
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_acca.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity accumulator_adder is
+  port ( a, b : in std_ulogic_vector(21 downto 0);
+         s : out std_ulogic_vector(21 downto 0);
+         ovf : out std_ulogic );
+end entity accumulator_adder;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd
new file mode 100644
index 0000000..2e9a327
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_accr-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of accumulator_reg is
+begin
+
+  behavior : process (clk) is
+
+                             constant Tpd_clk_out : time := 3 ns;
+
+  begin
+    if rising_edge(clk) then
+      if To_X01(clr) = '1' then
+        q <= (others => '0') after Tpd_clk_out;
+      else
+        q <= d after Tpd_clk_out;
+      end if;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr.vhd
new file mode 100644
index 0000000..96cb4ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_accr.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity accumulator_reg is
+                 port ( clk : in std_ulogic;
+                        clr : in std_ulogic;
+                        d : in std_ulogic_vector(21 downto 0);
+                        q : out std_ulogic_vector(21 downto 0) );
+               end entity accumulator_reg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-b.vhd
new file mode 100644
index 0000000..6fb77e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-b.vhd
@@ -0,0 +1,114 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mac-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of mac is
+
+  constant Tpd_clk_out : time := 3 ns;
+
+  signal fp_x_real, fp_x_imag,
+    fp_y_real, fp_y_imag,
+    fp_s_real, fp_s_imag : real := 0.0;
+
+begin
+
+  x_real_converter : entity work.to_fp(behavioral)
+    port map ( x_real, fp_x_real );
+
+  x_imag_converter : entity work.to_fp(behavioral)
+    port map ( x_imag, fp_x_imag );
+
+  y_real_converter : entity work.to_fp(behavioral)
+    port map ( y_real, fp_y_real );
+
+  y_imag_converter : entity work.to_fp(behavioral)
+    port map ( y_imag, fp_y_imag );
+
+  behavior : process (clk) is
+
+                             variable input_x_real, input_x_imag, input_y_real, input_y_imag : real := 0.0;
+                           variable real_part_product_1, real_part_product_2,
+                             imag_part_product_1, imag_part_product_2 : real := 0.0;
+                           variable real_product, imag_product : real := 0.0;
+                           variable real_sum, imag_sum : real := 0.0;
+                           variable real_accumulator_ovf, imag_accumulator_ovf : boolean := false;
+
+                           type boolean_to_stdulogic_table is array (boolean) of std_ulogic;
+                           constant boolean_to_stdulogic : boolean_to_stdulogic_table
+                             := (false => '0', true => '1');
+
+  begin
+    if rising_edge(clk) then
+      -- work from the end of the pipeline back to the start, so as
+      -- not to overwrite previous results in pipeline registers before
+      -- they are used
+
+      -- update accumulator and generate outputs
+      if To_X01(clr) = '1' then
+        real_sum := 0.0;
+        real_accumulator_ovf := false;
+        imag_sum := 0.0;
+        imag_accumulator_ovf := false;
+      else
+        real_sum := real_product + real_sum;
+        real_accumulator_ovf := real_accumulator_ovf
+                                or real_sum < -16.0 or real_sum >= +16.0;
+        imag_sum := imag_product + imag_sum;
+        imag_accumulator_ovf := imag_accumulator_ovf 
+                                or imag_sum < -16.0 or imag_sum >= +16.0;
+      end if;
+      fp_s_real <= real_sum after Tpd_clk_out;
+      fp_s_imag <= imag_sum after Tpd_clk_out;
+      ovf <= boolean_to_stdulogic(
+        real_accumulator_ovf or imag_accumulator_ovf
+        or real_sum < -1.0 or real_sum >= +1.0
+        or imag_sum < -1.0 or imag_sum >= +1.0 )
+             after Tpd_clk_out;
+
+      -- update product registers using partial products
+      real_product := real_part_product_1 - real_part_product_2;
+      imag_product := imag_part_product_1 + imag_part_product_2;
+
+      -- update partial product registers using latched inputs
+      real_part_product_1 := input_x_real * input_y_real;
+      real_part_product_2 := input_x_imag * input_y_imag;
+      imag_part_product_1 := input_x_real * input_y_imag;
+      imag_part_product_2 := input_x_imag * input_y_real;
+
+      -- update input registers using MAC inputs
+      input_x_real := fp_x_real;
+      input_x_imag := fp_x_imag;
+      input_y_real := fp_y_real;
+      input_y_imag := fp_y_imag;
+    end if;
+  end process behavior;
+
+  s_real_converter : entity work.to_vector(behavioral)
+    port map ( fp_s_real, s_real );
+
+  s_imag_converter : entity work.to_vector(behavioral)
+    port map ( fp_s_imag, s_imag );
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd
new file mode 100644
index 0000000..a0f61b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd
@@ -0,0 +1,167 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture rtl of mac is
+
+  signal pipelined_x_real,
+    pipelined_x_imag,
+    pipelined_y_real, 
+    pipelined_y_imag : std_ulogic_vector(15 downto 0);
+  signal real_part_product_1, 
+    real_part_product_2,
+    imag_part_product_1, 
+    imag_part_product_2 : std_ulogic_vector(31 downto 0);
+  signal pipelined_real_part_product_1,
+    pipelined_real_part_product_2,
+    pipelined_imag_part_product_1,
+    pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
+  signal real_product, 
+    imag_product : std_ulogic_vector(32 downto 0);
+  signal pipelined_real_product,
+    pipelined_imag_product : std_ulogic_vector(19 downto 0);
+  signal real_sum,
+    imag_sum : std_ulogic_vector(21 downto 0);
+  signal real_accumulator_ovf,
+    imag_accumulator_ovf : std_ulogic;
+  signal pipelined_real_sum,
+    pipelined_imag_sum : std_ulogic_vector(21 downto 0);
+  signal pipelined_real_accumulator_ovf,
+    pipelined_imag_accumulator_ovf : std_ulogic;
+
+begin
+
+  x_real_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => x_real, q => pipelined_x_real );
+
+  x_imag_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
+
+  y_real_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => y_real, q => pipelined_y_real );
+
+  y_imag_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
+
+  real_mult_1 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_real, b => pipelined_y_real,
+	       p => real_part_product_1 );
+
+  real_mult_2 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_imag, b => pipelined_y_imag,
+	       p => real_part_product_2 );
+
+  imag_mult_1 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_real, b => pipelined_y_imag,
+	       p => imag_part_product_1 );
+
+  imag_mult_2 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_imag, b => pipelined_y_real,
+	       p => imag_part_product_2 );
+
+  real_part_product_reg_1 : entity work.reg(behavioral)
+    port map ( clk => clk, d => real_part_product_1,
+	       q => pipelined_real_part_product_1 );
+
+  real_part_product_reg_2 : entity work.reg(behavioral)
+    port map ( clk => clk, d => real_part_product_2,
+	       q => pipelined_real_part_product_2 );
+
+  imag_part_product_reg_1 : entity work.reg(behavioral)
+    port map ( clk => clk, d => imag_part_product_1,
+	       q => pipelined_imag_part_product_1 );
+
+  imag_part_product_reg_2 : entity work.reg(behavioral)
+    port map ( clk => clk, d => imag_part_product_2,
+	       q => pipelined_imag_part_product_2 );
+
+  real_product_subtracter : entity work.product_adder_subtracter(behavioral)
+    port map ( mode => '1',
+               a => pipelined_real_part_product_1,
+	       b => pipelined_real_part_product_2,
+	       s => real_product );
+
+  imag_product_adder : entity work.product_adder_subtracter(behavioral)
+    port map ( mode => '0',
+               a => pipelined_imag_part_product_1,
+	       b => pipelined_imag_part_product_2,
+	       s => imag_product );
+
+  real_product_reg : entity work.reg(behavioral)
+    port map ( clk => clk,
+	       d => real_product(32 downto 13),
+	       q => pipelined_real_product );
+
+  imag_product_reg : entity work.reg(behavioral)
+    port map ( clk => clk,
+	       d => imag_product(32 downto 13),
+	       q => pipelined_imag_product );
+
+  real_accumulator : entity work.accumulator_adder(behavioral)
+    port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
+	       a(20) => pipelined_real_product(19),
+	       a(21) => pipelined_real_product(19),
+	       b => pipelined_real_sum,
+	       s => real_sum,
+	       ovf => real_accumulator_ovf );
+
+  imag_accumulator : entity work.accumulator_adder(behavioral)
+    port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
+	       a(20) => pipelined_imag_product(19),
+	       a(21) => pipelined_imag_product(19),
+	       b => pipelined_imag_sum,
+	       s => imag_sum,
+	       ovf => imag_accumulator_ovf );
+
+  real_accumulator_reg : entity work.accumulator_reg(behavioral)
+    port map ( clk => clk, clr => clr,
+	       d => real_sum,  q => pipelined_real_sum );
+
+  imag_accumulator_reg : entity work.accumulator_reg(behavioral)
+    port map ( clk => clk, clr => clr,
+	       d => imag_sum,  q => pipelined_imag_sum );
+
+  real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
+    port map ( clk => clk,
+               set => real_accumulator_ovf, clr => clr,
+	       q => pipelined_real_accumulator_ovf );
+
+  imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
+    port map ( clk => clk,
+               set => imag_accumulator_ovf, clr => clr,
+	       q => pipelined_imag_accumulator_ovf );
+
+  s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
+
+  s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
+
+  result_overflow_logic : entity work.overflow_logic(behavioral)
+    port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
+	       imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
+	       real_sum => pipelined_real_sum(21 downto 17),
+	       imag_sum => pipelined_imag_sum(21 downto 17),
+	       ovf => ovf );
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac.vhd
new file mode 100644
index 0000000..7519f5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mac.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mac is
+  port ( clk, clr : in std_ulogic;
+         x_real : in std_ulogic_vector(15 downto 0);
+         x_imag : in std_ulogic_vector(15 downto 0);
+         y_real : in std_ulogic_vector(15 downto 0);
+         y_imag : in std_ulogic_vector(15 downto 0);
+         s_real : out std_ulogic_vector(15 downto 0);
+         s_imag : out std_ulogic_vector(15 downto 0);
+         ovf : out std_ulogic );
+end entity mac;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd
new file mode 100644
index 0000000..1d85d4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench_behavioral of mac_test is
+
+  signal clk, clr, ovf : std_ulogic := '0';
+  signal x_real, x_imag,
+    y_real, y_imag,
+    s_real, s_imag : std_ulogic_vector(15 downto 0);
+
+  type complex is record
+                    re, im : real;
+                  end record;
+
+  signal x, y, s : complex := (0.0, 0.0);
+
+  constant Tpw_clk : time := 50 ns;
+
+begin
+
+  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
+  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
+  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
+  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
+
+  dut : entity work.mac(behavioral)
+    port map ( clk, clr,
+               x_real, x_imag, y_real, y_imag, s_real, s_imag,
+               ovf );
+
+  s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
+  s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
+
+
+  clock_gen : process is
+  begin
+    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+    wait for 2 * Tpw_clk;
+  end process clock_gen;
+
+
+  stimulus : process is
+  begin
+    -- first sequence
+    clr <= '1';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '1';  wait until clk = '0';
+    x <= (+0.2, +0.2);  y <= (+0.2, +0.2);  clr <= '1';  wait until clk = '0';
+    x <= (+0.1, -0.1);  y <= (+0.1, +0.1);  clr <= '1';  wait until clk = '0';
+    x <= (+0.1, -0.1);  y <= (+0.1, +0.1);  clr <= '0';  wait until clk = '0';
+
+    -- should be (0.4, 0.58) when it falls out the other end
+
+    clr <= '0';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '0';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.1, +0.1);  clr <= '0';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '1';  wait until clk = '0';
+    x <= (-0.5, +0.5);  y <= (-0.5, +0.5);  clr <= '0';  wait until clk = '0';
+    clr <= '0';  wait until clk = '0';
+    clr <= '0';  wait until clk = '0';
+    clr <= '0';  wait until clk = '0';
+    clr <= '1';  wait until clk = '0';
+
+    wait;
+  end process stimulus;
+
+end architecture bench_behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-br.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-br.vhd
new file mode 100644
index 0000000..c6d3f56
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-br.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact-br.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench_rtl of mac_test is
+
+  signal clk, clr, ovf : std_ulogic := '0';
+  signal x_real, x_imag,
+    y_real, y_imag,
+    s_real, s_imag : std_ulogic_vector(15 downto 0);
+
+  type complex is record
+                    re, im : real;
+                  end record;
+
+  signal x, y, s : complex := (0.0, 0.0);
+
+  constant Tpw_clk : time := 50 ns;
+
+begin
+
+  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
+  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
+  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
+  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
+
+  dut : entity work.mac(rtl)
+    port map (clk, clr,
+              x_real, x_imag, y_real, y_imag, s_real, s_imag,
+              ovf );
+
+  s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
+  s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
+
+
+  clock_gen : process is
+  begin
+    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+    wait for 2 * Tpw_clk;
+  end process clock_gen;
+
+
+  stimulus : process is
+  begin
+    -- first sequence
+    clr <= '1';	wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);	clr <= '1';	wait until clk = '0';
+    x <= (+0.2, +0.2);	y <= (+0.2, +0.2);	clr <= '1';	wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);	clr <= '1';	wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);	clr <= '0';	wait until clk = '0';
+
+    -- should be (0.4, 0.58) when it falls out the other end
+
+    clr <= '0';	wait until clk = '0';
+    x <= ( 0.5,  0.5);	y <= ( 0.5,  0.5);	clr <= '0';	wait until clk = '0';
+    x <= ( 0.5,  0.5);	y <= ( 0.1,  0.1);	clr <= '0';	wait until clk = '0';
+    x <= ( 0.5,  0.5);	y <= ( 0.5,  0.5);	clr <= '1';	wait until clk = '0';
+    x <= (-0.5,  0.5);	y <= (-0.5,  0.5);	clr <= '0';	wait until clk = '0';
+    clr <= '0';	wait until clk = '0';
+    clr <= '0';	wait until clk = '0';
+    clr <= '0';	wait until clk = '0';
+    clr <= '1';	wait until clk = '0';
+
+    wait;
+  end process stimulus;
+
+end architecture bench_rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd
new file mode 100644
index 0000000..92685e1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd
@@ -0,0 +1,122 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench_verify of mac_test is
+
+  signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
+  signal x_real, x_imag,
+    y_real, y_imag,
+    behavioral_s_real, behavioral_s_imag,
+    rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
+
+  type complex is record
+                    re, im : real;
+                  end record;
+
+  signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
+
+  constant Tpw_clk : time := 50 ns;
+
+begin
+
+  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
+  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
+  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
+  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
+
+  dut_behavioral : entity work.mac(behavioral)
+    port map ( clk, clr,
+               x_real, x_imag, y_real, y_imag,
+               behavioral_s_real, behavioral_s_imag, behavioral_ovf );
+
+  dut_rtl : entity work.mac(rtl)
+    port map ( clk, clr,
+               x_real, x_imag, y_real, y_imag,
+               rtl_s_real, rtl_s_imag, rtl_ovf );
+
+  behavioral_s_real_converter :
+    entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
+  behavioral_s_imag_converter :
+    entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
+
+  rtl_s_real_converter :
+    entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
+  rtl_s_imag_converter :
+    entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
+
+
+  clock_gen : process is
+  begin
+    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+    wait for 2 * Tpw_clk;
+  end process clock_gen;
+
+
+  stimulus : process is
+  begin
+    -- first sequence
+    clr <= '1';  wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '1';	 wait until clk = '0';
+    x <= (+0.2, +0.2);	y <= (+0.2, +0.2);  clr <= '1';	 wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);  clr <= '1';	 wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);  clr <= '0';	 wait until clk = '0';
+
+    -- should be (0.4, 0.58) when it falls out the other end
+
+    clr <= '0';	 wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '0';	 wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.1, +0.1);  clr <= '0';	 wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '1';	 wait until clk = '0';
+    x <= (-0.5, +0.5);	y <= (-0.5, +0.5);  clr <= '0';	 wait until clk = '0';
+    clr <= '0';	 wait until clk = '0';
+    clr <= '0';	 wait until clk = '0';
+    clr <= '0';	 wait until clk = '0';
+    clr <= '1';	 wait until clk = '0';
+
+    wait;
+  end process stimulus;
+
+
+  verifier : process
+
+    constant epsilon : real := 4.0E-5;  -- 1-bit error in 15-bit mantissa
+
+  begin
+    wait until clk = '0';
+    assert behavioral_ovf = rtl_ovf
+      report "Overflow flags differ" severity error;
+    if behavioral_ovf = '0' and rtl_ovf = '0' then
+      assert abs (behavioral_s.re - rtl_s.re) < epsilon
+        report "Real sums differ" severity error;
+      assert abs (behavioral_s.im - rtl_s.im) < epsilon
+        report "Imag sums differ" severity error;
+    end if;
+  end process verifier;
+
+end architecture bench_verify;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact.vhd
new file mode 100644
index 0000000..34d8bf2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity mac_test is
+
+end entity mac_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult-b.vhd
new file mode 100644
index 0000000..c8b6cec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult-b.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mult-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of multiplier is
+begin
+
+  behavior : process (a, b) is
+
+                              constant Tpd_in_out : time := 40 ns;
+                            variable negative_result  : boolean;
+                            variable op1 : std_ulogic_vector(15 downto 0);
+                            variable op2 : std_ulogic_vector(15 downto 0);
+                            variable result : std_ulogic_vector(31 downto 0);
+                            variable carry_in, carry : std_ulogic;
+
+  begin
+    op1 := to_X01(a);
+    op2 := to_X01(b);
+    -- make both operands positive, remembering sign of result
+    negative_result := (op1(15) = '1') xor (op2(15) = '1');
+    if (op1(15) = '1') then
+      carry := '1';
+      for index in 0 to 15 loop
+        carry_in := carry;
+        carry := carry_in and not op1(index);
+        op1(index) := not op1(index) xor carry_in;
+      end loop;
+    end if;
+    if (op2(15) = '1') then
+      carry := '1';
+      for index in 0 to 15 loop
+        carry_in := carry;
+        carry := carry_in and not op2(index);
+        op2(index) := not op2(index) xor carry_in;
+      end loop;
+    end if;
+    -- do long multiplication
+    result := (others => '0');
+    for count in 0 to 15 loop
+      carry := '0';
+      if (op2(count) = '1') then
+        for index in 0 to 15 loop
+          carry_in := carry;
+          carry := (result(index+count) and op1(index))
+                   or (carry_in and (result(index+count) xor op1(index)));
+          result(index+count) := result(index+count) xor op1(index) xor carry_in;
+        end loop;
+        result(count+16) := carry;
+      end if;
+    end loop;
+    -- result now contains unsigned product, with binary point
+    -- between bits 30 and 29.  assign output with sign adjusted.
+    if negative_result then
+      carry := '1';
+      for index in 0 to 31 loop
+        carry_in := carry;
+        carry := carry_in and not result(index);
+        result(index) := not result(index) xor carry_in;
+      end loop;
+    end if;
+    p <= result after Tpd_in_out;
+  end process behavior;
+
+end architecture behavioral;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult.vhd
new file mode 100644
index 0000000..f6b2ea1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mult.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity multiplier is
+                 port ( a, b : in std_ulogic_vector(15 downto 0);
+                        p : out std_ulogic_vector(31 downto 0) );
+               end entity multiplier;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd
new file mode 100644
index 0000000..8edb61e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               architecture bench of multiplier_test is
+
+                 signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
+                 signal p : std_ulogic_vector(31 downto 0);
+
+               begin
+
+                 dut : entity work.multiplier(behavioral)
+                   port map (a, b, p);
+
+                 stimulus : process is
+                 begin
+                   a <= X"8000";  b <= X"8000";  --  -1 * -1
+                   wait for 50 ns;
+                   a <= X"0001";  b <= X"0001";  --  2**-15 * 2**-15
+                   wait for 50 ns;
+                   a <= X"0001";  b <= X"0000";  --  2**-15 * 0
+                   wait for 50 ns;
+                   a <= X"0000";  b <= X"0001";  --  0 * 2**-15
+                   wait for 50 ns;
+                   a <= X"0001";  b <= X"8000";  --  2**-15 * -1
+                   wait for 50 ns;
+                   a <= X"8000";  b <= X"0001";  --  -1 * 2**-15
+                   wait for 50 ns;
+                   a <= X"4000";  b <= X"4000";  --  0.5 * 0.5
+                   wait for 50 ns;
+                   a <= X"C000";  b <= X"4000";  --  -0.5 * 0.5
+                   wait for 50 ns;
+                   a <= X"4000";  b <= X"C000";  --  0.5 * -0.5
+                   wait for 50 ns;
+                   a <= X"C000";  b <= X"C000";  --  -0.5 * -0.5
+                   wait for 50 ns;
+                   wait;
+                 end process stimulus;
+
+               end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt.vhd
new file mode 100644
index 0000000..3befc73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_multt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity multiplier_test is
+
+end entity multiplier_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl-b.vhd
new file mode 100644
index 0000000..34d6d18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl-b.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_ovfl-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of overflow_logic is
+
+  constant Tpd_in_out : time := 3 ns;
+
+begin
+
+  ovf <= real_accumulator_ovf or imag_accumulator_ovf
+	 or ( real_sum(21) xor real_sum(20) )
+	 or ( real_sum(21) xor real_sum(19) )
+	 or ( real_sum(21) xor real_sum(18) )
+	 or ( real_sum(21) xor real_sum(17) )
+	 or ( imag_sum(21) xor imag_sum(20) )
+	 or ( imag_sum(21) xor imag_sum(19) )
+	 or ( imag_sum(21) xor imag_sum(18) )
+	 or ( imag_sum(21) xor imag_sum(17) ) after Tpd_in_out;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl.vhd
new file mode 100644
index 0000000..dcaa16c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_ovfl.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity overflow_logic is
+                 port ( real_accumulator_ovf, imag_accumulator_ovf : in std_ulogic;
+                        real_sum, imag_sum : std_ulogic_vector(21 downto 17);
+                        ovf : out std_ulogic );
+               end entity overflow_logic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas-b.vhd
new file mode 100644
index 0000000..8d0dfd2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas-b.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_pas-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of product_adder_subtracter is
+begin
+
+  behavior : process (a, b) is
+
+                              constant Tpd_in_out : time := 3 ns;
+                            variable op2 : std_ulogic_vector(b'range);
+                            variable carry_in : std_ulogic;
+                            variable carry_out : std_ulogic;
+
+  begin
+    carry_out := To_X01(mode);
+    if To_X01(mode) = '1' then
+      op2 := not b;
+    else
+      op2 := b;
+    end if;
+    for index in 0 to 31 loop
+      carry_in := carry_out;  -- of previous bit
+      s(index) <= a(index) xor op2(index) xor carry_in after Tpd_in_out;
+      carry_out := (a(index) and op2(index))
+      	      	   or (carry_in and (a(index) xor op2(index)));
+    end loop;
+    s(32) <= a(31) xor op2(31) xor carry_out after Tpd_in_out;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas.vhd
new file mode 100644
index 0000000..04e13bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_pas.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity product_adder_subtracter is
+                 port ( mode : in std_ulogic;
+                        a, b : in std_ulogic_vector(31 downto 0);
+                        s : out std_ulogic_vector(32 downto 0) );
+               end entity product_adder_subtracter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd
new file mode 100644
index 0000000..25081a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_reg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of reg is
+begin
+
+  behavior : process (clk) is
+  begin
+    if rising_edge(clk) then
+      q <= d;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg.vhd
new file mode 100644
index 0000000..9ea7c89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_reg.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity reg is
+                 port ( clk : in std_ulogic;
+                        d : in std_ulogic_vector;
+                        q : out std_ulogic_vector );
+               end entity reg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd
new file mode 100644
index 0000000..d1312f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_srff-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of synch_sr_ff is
+begin
+
+  behavior : process (clk) is
+
+                             constant Tpd_clk_out : time := 3 ns;
+
+  begin
+    if rising_edge(clk) then
+      if To_X01(clr) = '1' then
+        q <= '0' after Tpd_clk_out;
+      elsif To_X01(set) = '1' then
+        q <= '1' after Tpd_clk_out;
+      end if;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff.vhd
new file mode 100644
index 0000000..03f0fa2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_srff.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity synch_sr_ff is
+                 port ( clk : in std_ulogic;
+                        set, clr : in std_ulogic;
+                        q : out std_ulogic );
+               end entity synch_sr_ff;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd
new file mode 100644
index 0000000..b516476
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofp-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of to_fp is
+
+begin
+
+  behavior : process (vec) is
+
+                             variable temp : bit_vector(vec'range);
+                           variable negative : boolean;
+                           variable int_result : integer;
+
+  begin
+    temp := to_bitvector(vec);
+    negative := temp(temp'left) = '1';
+    if negative then
+      temp := not temp;
+    end if;
+    int_result := 0;
+    for index in vec'range loop	  -- sign bit of temp = '0'
+      int_result := int_result * 2 + bit'pos(temp(index));
+    end loop;
+    if negative then
+      int_result := (-int_result) - 1;
+    end if;
+    -- convert to floating point and scale to [-1, +1)
+    r <= real(int_result) / real(2**15);
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp.vhd
new file mode 100644
index 0000000..05934bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofp.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity to_fp is
+                 port ( vec : in std_ulogic_vector(15 downto 0);
+                        r : out real );
+               end entity to_fp;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd
new file mode 100644
index 0000000..8feb4ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofpt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               architecture bench of to_fp_test is
+
+                 signal vec : std_ulogic_vector(15 downto 0);
+                 signal r : real;
+
+               begin
+
+                 dut : entity work.to_fp(behavioral)
+                   port map (vec, r);
+
+                 stimulus : process is
+                 begin
+                   vec <= X"0000";  wait for 10 ns;
+                   vec <= X"8000";  wait for 10 ns;
+                   vec <= X"7FFF";  wait for 10 ns;
+                   vec <= X"4000";  wait for 10 ns;
+                   vec <= X"C000";  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt.vhd
new file mode 100644
index 0000000..8e47204
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofpt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity to_fp_test is
+
+end entity to_fp_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec-b.vhd
new file mode 100644
index 0000000..4574192
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec-b.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovec-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of to_vector is
+
+begin
+
+  behavior : process (r) is
+
+                           variable temp : integer range -2**15 to 2**15 - 1;
+                         variable negative : boolean;
+                         variable result : std_ulogic_vector(vec'range);
+
+  begin
+    -- scale to [-2**15, +2**15) and convert to integer
+    if r * real(2**15) < real(-2**15) then
+      temp := -2**15;
+    elsif r * real(2**15) >= real(2**15 - 1) then
+      temp := 2**15 - 1;
+    else
+      temp := integer(r * real(2**15));
+    end if;
+    negative := temp < 0;
+    if negative then
+      temp := -(temp + 1);
+    end if;
+    result := (others => '0');
+    for index in result'reverse_range loop
+      result(index) := to_X01(bit'val(temp rem 2));
+      temp := temp / 2;
+      exit when temp = 0;
+    end loop;
+    if negative then
+      result := not result;
+      result(result'left) := '1';
+    end if;
+    vec <= result;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec.vhd
new file mode 100644
index 0000000..1ae6b64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovec.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity to_vector is
+                 port ( r : in real;
+                        vec : out std_ulogic_vector(15 downto 0) );
+               end entity to_vector;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd
new file mode 100644
index 0000000..2f14d5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovect-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               architecture bench of to_vector_test is
+
+                 signal vec : std_ulogic_vector(15 downto 0);
+                 signal r : real := 0.0;
+
+               begin
+
+                 dut : entity work.to_vector(behavioral)
+                   port map (r, vec);
+
+                 stimulus : process is
+                 begin
+                   r <=  0.0;		wait for 10 ns;
+                   r <= -1.0;		wait for 10 ns;
+                   r <= -2.0;		wait for 10 ns;
+                   r <= +0.9999;	wait for 10 ns;
+                   r <= +2.0;		wait for 10 ns;
+                   r <= -0.5;		wait for 10 ns;
+                   r <= +0.5;		wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect.vhd
new file mode 100644
index 0000000..7bac2fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovect.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity to_vector_test is
+
+end entity to_vector_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_01.vhd
new file mode 100644
index 0000000..0e49262
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_01.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_01 is
+
+end entity ch_07_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_07_01 is
+begin
+
+
+  process_07_2_a : process is
+
+                             type t1 is (t1_1, t1_2);
+                           type t2 is (t2_1, t2_2);
+                           type t3 is (t3_1, t3_2);
+                           type t4 is (t4_1, t4_2);
+
+                           constant v4 : t4 := t4_1;
+
+                           constant val1 : t1 := t1_1;
+                           constant val2 : t2 := t2_1;
+                           variable var3 : t3 := t3_1;
+                           constant val4 : t4 := t4_1;
+
+                           -- code from book:
+
+                           procedure p ( f1 : in t1;  f2 : in t2;  f3 : out t3;  f4 : in t4 := v4 ) is
+                           begin
+                             -- . . .
+                           end procedure p;
+
+                           -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    p ( val1, val2, var3, val4 );
+    p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 );
+    p ( val1, val2, f4 => open, f3 => var3 );
+    p ( val1, val2, var3 );
+
+    -- end of code from book
+
+    wait;
+  end process process_07_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_02.vhd
new file mode 100644
index 0000000..74ac110
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_02.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_02 is
+
+end entity ch_07_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_07_02 is
+
+  constant val1 : integer := 1;
+
+  procedure p ( signal s1, s2 : in bit;  val1 : in integer ) is
+  begin
+    null;
+  end procedure p;
+
+begin
+
+
+  block_07_3_a : block is
+
+                         signal s1, s2 : bit;
+
+  begin
+
+    -- code from book:
+
+    call_proc : p ( s1, s2, val1 );
+
+    -- end of code from book
+
+  end block block_07_3_a;
+
+
+  ----------------
+
+
+  block_07_3_b : block is
+
+                         signal s1, s2 : bit;
+
+  begin
+
+    -- code from book:
+
+    call_proc : process is
+    begin
+      p ( s1, s2, val1 );
+      wait on s1, s2;
+    end process call_proc;
+
+    -- end of code from book
+
+  end block block_07_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_03.vhd
new file mode 100644
index 0000000..8cc3aa2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_03.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_03 is
+end entity ch_07_03;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture test of ch_07_03 is
+
+  constant T_delay_adder : delay_length := 10 ns;
+
+  -- code from book:
+
+  function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
+  begin
+    -- . . .
+    -- not in book
+    return bv1 + bv2;
+    -- end not in book
+  end function bv_add;
+
+  signal source1, source2, sum : bit_vector(0 to 31);
+
+  -- end of code from book
+
+begin
+
+  -- code from book:
+
+  adder : sum <= bv_add(source1, source2) after T_delay_adder;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    wait for 50 ns;
+    source1 <= X"00000002";  source2 <= X"00000003";  wait for 50 ns;
+    source2 <= X"FFFFFFF0";  wait for 50 ns;
+    source1 <= X"00000010";                           wait for 50 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_04.vhd
new file mode 100644
index 0000000..3c39a15
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_04.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_04 is
+
+  -- code from book:
+
+  impure function now return delay_length;
+
+  -- end of code from book
+
+  impure function now return delay_length is
+  begin
+    return std.standard.now;
+  end function now;
+
+  -- end of code from book
+
+end entity ch_07_04;
+
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd
new file mode 100644
index 0000000..2ee0eec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_05.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_05 is
+end entity ch_07_05;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture test of ch_07_05 is
+
+begin
+
+  process_07_5_a : process is
+
+                             -- code from book:
+
+                             procedure increment ( a : inout integer;   n : in integer := 1 ) is -- . . .
+    -- not in book
+  begin
+    a := a + n;
+  end procedure increment;
+  -- end not in book;
+
+  procedure increment ( a : inout bit_vector;  n : in bit_vector := B"1" ) is -- . . .
+    -- not in book
+  begin
+    a := a + n;
+  end procedure increment;
+  -- end not in book;
+
+  procedure increment ( a : inout bit_vector;  n : in integer := 1 ) is -- . . .
+    -- not in book
+  begin
+    a := a + integer_to_bv(n, a'length);
+  end procedure increment;
+  -- end not in book;
+
+  variable count_int : integer := 2;
+  variable count_bv : bit_vector (15 downto 0) := X"0002";
+
+  -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    increment ( count_int, 2 );
+    increment ( count_int );
+
+    increment ( count_bv, X"0002");
+    increment ( count_bv, 1 );
+
+    -- increment ( count_bv );
+
+    -- end of code from book
+
+    wait;
+  end process process_07_5_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd
new file mode 100644
index 0000000..874852c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_06 is
+end entity ch_07_06;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic;
+
+architecture test of ch_07_06 is
+begin
+
+  process_07_5_b : process is
+
+                             -- code from book:
+
+                             function "+" ( left, right : in bit_vector ) return bit_vector is
+  begin
+    -- . . .
+    -- not in book
+    return bv_arithmetic."+"(left, right);
+    -- end not in book
+  end function "+";
+
+  variable addr_reg : bit_vector(31 downto 0);
+  -- . . .
+
+  -- end of code from book
+
+  -- code from book:
+
+  function "abs" ( right : in bit_vector ) return bit_vector is
+  begin
+    -- . . .
+    -- not in book
+    if right(right'left) = '0' then
+      return right;
+    else
+      return bv_arithmetic."-"(right);
+    end if;
+    -- end not in book
+  end function "abs";
+
+  variable accumulator : bit_vector(31 downto 0);
+  -- . . .
+
+  -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    addr_reg := addr_reg + X"0000_0004";
+
+    -- end of code from book
+
+    accumulator := X"000000FF";
+
+    -- code from book:
+
+    accumulator := abs accumulator;
+
+    -- end of code from book
+
+    accumulator := X"FFFFFFFE";
+    accumulator := abs accumulator;
+
+    wait;
+  end process process_07_5_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_01.vhd
new file mode 100644
index 0000000..d632901
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_01.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_01 is
+end entity fg_07_01;
+
+
+
+architecture test of fg_07_01 is
+
+  shared variable average : real := 0.0;
+  type sample_array is array (positive range <>) of real;
+  constant samples : sample_array :=
+    ( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 );
+
+  -- code from book
+
+  procedure average_samples is
+    variable total : real := 0.0;
+  begin
+    assert samples'length > 0 severity failure;
+    for index in samples'range loop
+      total := total + samples(index);
+    end loop;
+    average := total / real(samples'length);
+  end procedure average_samples;
+
+  -- end code from book
+
+begin
+
+  -- code from book (in text)
+
+  average_samples;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_02.vhd
new file mode 100644
index 0000000..814f49b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_02.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity control_processor is
+  generic ( Tpd : delay_length := 3 ns );
+end entity control_processor;
+
+-- end not in book
+
+
+
+architecture rtl of control_processor is
+
+  type func_code is (add, subtract);
+
+  signal op1, op2, dest : integer;
+  signal Z_flag : boolean;
+  signal func : func_code;
+  -- . . .
+
+begin
+
+  alu : process is
+
+                  procedure do_arith_op is
+    variable result : integer;
+  begin
+    case func is
+      when add =>
+        result := op1 + op2;
+      when subtract =>
+        result := op1 - op2;
+    end case;
+    dest  <=  result after Tpd;
+    Z_flag  <=  result = 0 after Tpd;
+  end procedure do_arith_op;
+
+  begin
+    -- . . .
+    do_arith_op;
+    -- . . .
+    -- not in book
+    wait on op1, op2, func;
+    -- end not in book
+  end process alu;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    op1 <= 0;  op2 <= 0;	wait for 10 ns;
+    op1 <= 10; op2 <= 3;	wait for 10 ns;
+    func <= subtract;		wait for 10 ns;
+    op2 <= 10;			wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_03.vhd
new file mode 100644
index 0000000..e993b39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_03.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_03 is
+end entity fg_07_03;
+
+library bv_utilities;
+
+architecture interpreter of fg_07_03 is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address_bus, data_bus_in : word := X"0000_0000";
+  signal mem_read, mem_request, mem_ready : bit := '0';
+
+begin
+
+  -- code from book
+
+  instruction_interpreter : process is
+
+                                      variable mem_address_reg, mem_data_reg,
+                                    prog_counter, instr_reg, accumulator, index_reg : word;
+                                    -- . . .
+                                    -- not in book
+                                    type opcode_type is (load_mem);
+                                    constant opcode : opcode_type := load_mem;
+                                    constant displacement : word := X"0000_0010";
+                                    use bv_utilities.bv_arithmetic.all;
+                                    -- end not in book
+
+                                    procedure read_memory is
+                                    begin
+                                      address_bus <= mem_address_reg;
+                                      mem_read <= '1';
+                                      mem_request <= '1';
+                                      wait until mem_ready = '1';
+                                      mem_data_reg := data_bus_in;
+                                      mem_request <= '0';
+                                      wait until mem_ready = '0';
+                                    end procedure read_memory;
+
+  begin
+    -- . . .  -- initialization
+    loop
+      -- fetch next instruction
+      mem_address_reg := prog_counter;
+      read_memory;                           -- call procedure
+      instr_reg := mem_data_reg;
+      -- . . .
+      case opcode is
+        -- . . .
+        when load_mem =>
+          mem_address_reg := index_reg + displacement;
+          read_memory;                        -- call procedure
+          accumulator := mem_data_reg;
+          -- . . .
+      end case;
+    end loop;
+  end process instruction_interpreter;
+
+  -- end code from book
+
+
+  memory : process is
+  begin
+    wait until mem_request = '1';
+    data_bus_in <= X"1111_1111";
+    mem_ready <= '1';
+    wait until mem_request = '0';
+    mem_ready <= '0';
+  end process memory;
+
+end architecture interpreter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd
new file mode 100644
index 0000000..51f5154
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_04 is
+end entity fg_07_04;
+
+
+
+architecture test of fg_07_04 is
+
+  signal phase1, phase2, reg_file_write_en,
+    A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
+
+begin
+
+  -- code from book
+
+  control_sequencer : process is
+
+                                procedure control_write_back is
+  begin
+    wait until phase1 = '1';
+    reg_file_write_en <= '1';
+    wait until phase2 = '0';
+    reg_file_write_en <= '0';
+  end procedure control_write_back;
+
+  procedure control_arith_op is
+  begin
+    wait until phase1 = '1';
+    A_reg_out_en <= '1';
+    B_reg_out_en <= '1';
+    wait until phase1 = '0';
+    A_reg_out_en <= '0';
+    B_reg_out_en <= '0';
+    wait until phase2 = '1';
+    C_reg_load_en <= '1';
+    wait until phase2 = '0';
+    C_reg_load_en <= '0';
+    control_write_back;        -- call procedure
+  end procedure control_arith_op;
+
+  -- . . .
+
+  begin
+    -- . . .
+    control_arith_op;          -- call procedure
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process control_sequencer;
+
+  -- end code from book
+
+
+  clock_gen : process is
+  begin
+    phase1 <= '1' after 10 ns, '0' after 20 ns;
+    phase2 <= '1' after 30 ns, '0' after 40 ns;
+    wait for 40 ns;
+  end process clock_gen;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_05.vhd
new file mode 100644
index 0000000..4d07810
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_05.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_05 is
+end entity fg_07_05;
+
+
+architecture interpreter of fg_07_05 is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address_bus, data_bus_in : word := X"0000_0000";
+  signal mem_read, mem_request, mem_ready, reset : bit := '0';
+
+begin
+
+  -- code from book
+
+  instruction_interpreter : process is
+
+                                      -- . . .
+
+                                      -- not in book
+                                      variable mem_address_reg, mem_data_reg : word;
+                                    -- end not in book
+
+                                    procedure read_memory is
+                                    begin
+                                      address_bus <= mem_address_reg;
+                                      mem_read <= '1';
+                                      mem_request <= '1';
+                                      wait until mem_ready = '1' or reset = '1';
+                                      if reset = '1' then
+                                        return;
+                                      end if;
+                                      mem_data_reg := data_bus_in;
+                                      mem_request <= '0';
+                                      wait until mem_ready = '0';
+                                    end procedure read_memory;
+
+  begin
+    -- . . .    -- initialization
+    -- not in book
+    if reset = '1' then
+      wait until reset = '0';
+    end if;
+    -- end not in book
+    loop
+      -- . . .
+      read_memory;
+      exit when reset = '1';
+      -- . . .
+    end loop;
+  end process instruction_interpreter;
+
+  -- end code from book
+
+
+  memory : process is
+  begin
+    wait until mem_request = '1';
+    data_bus_in <= X"1111_1111";
+    mem_ready <= '1' after 10 ns;
+    wait until mem_request = '0';
+    mem_ready <= '0' after 10 ns;
+  end process memory;
+
+  reset <= '1' after 85 ns;
+
+end architecture interpreter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_06.vhd
new file mode 100644
index 0000000..95eb598
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_06.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_06.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_06 is
+end entity fg_07_06;
+
+
+architecture test of fg_07_06 is
+
+  type func_code is (add, subtract);
+
+  signal op1 : integer := 10;
+  signal op2 : integer := 3;
+  signal dest : integer := 0;
+  signal func : func_code := add;
+
+  signal Z_flag : boolean := false;
+
+  constant Tpd : delay_length := 3 ns;
+
+begin
+
+  stimulus : process is
+
+                       -- code from book
+
+                       procedure do_arith_op ( op : in func_code ) is
+    variable result : integer;
+  begin
+    case op is
+      when add =>
+        result := op1 + op2;
+      when subtract =>
+        result := op1 - op2;
+    end case;
+    dest  <=  result after Tpd;
+    Z_flag  <=  result = 0 after Tpd;
+  end procedure do_arith_op;
+
+  -- end code from book
+
+  begin
+    wait for 10 ns;
+
+    -- code from book (in text)
+
+    do_arith_op ( add );
+
+    -- end code from book
+
+    wait for 10 ns;
+
+    -- code from book (in text)
+
+    do_arith_op ( func );
+
+    -- end code from book
+
+    wait for 10 ns;
+    do_arith_op ( subtract );
+    wait for 10 ns;
+    op2 <= 10;
+    wait for 10 ns;
+    do_arith_op ( subtract );
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_07.vhd
new file mode 100644
index 0000000..72b5d81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_07.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_07 is
+end entity fg_07_07;
+
+
+architecture test of fg_07_07 is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code in book
+
+  procedure addu ( a, b : in word32;
+                   result : out word32;  overflow : out boolean ) is
+    variable sum : word32;
+    variable carry : bit := '0';
+  begin
+    for index in sum'reverse_range loop
+      sum(index) := a(index) xor b(index) xor carry;
+      carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) );
+    end loop;
+    result := sum;
+    overflow := carry = '1';
+  end procedure addu;
+
+  -- end code in book
+
+begin
+
+  stimulus : process is
+
+                       -- code in book (in text)
+
+                       variable PC, next_PC : word32;
+                     variable overflow_flag : boolean;
+                     -- . . .
+
+                     -- end code in book
+
+  begin
+    PC := X"0000_0010";
+
+    -- code in book (in text)
+
+    addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+    -- end code in book
+
+    PC := X"FFFF_FFFC";
+    addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_08.vhd
new file mode 100644
index 0000000..2f04590
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_08.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_08.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_08 is
+end entity fg_07_08;
+
+
+architecture test of fg_07_08 is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code in book
+
+  procedure negate ( a : inout word32 ) is
+    variable carry_in : bit := '1';
+    variable carry_out : bit;
+  begin
+    a := not a;
+    for index in a'reverse_range loop
+      carry_out :=  a(index) and carry_in;
+      a(index) := a(index) xor carry_in;
+      carry_in := carry_out;
+    end loop;
+  end procedure negate;
+
+  -- end code in book
+
+begin
+
+  stimulus : process is
+
+                       -- code in book (in text)
+
+                       variable op1 : word32;
+                     -- . . .
+
+                     -- end code in book
+
+  begin
+    op1 := X"0000_0002";
+
+    -- code in book (in text)
+
+    negate ( op1 );
+
+    -- end code in book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_09.vhd
new file mode 100644
index 0000000..96ea3dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_09.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity receiver is
+end entity receiver;
+
+
+-- code from book
+
+architecture behavioral of receiver is
+
+  -- . . .    -- type declarations, etc
+
+  -- not in book
+
+  subtype packet_index_range is integer range 1 to 8;
+  type packet_array is array (packet_index_range) of bit;
+
+  -- end not in book
+
+  signal recovered_data : bit;
+  signal recovered_clock : bit;
+  -- . . .
+
+  procedure receive_packet ( signal rx_data : in bit;
+                             signal rx_clock : in bit;
+                             data_buffer : out packet_array ) is
+  begin
+    for index in packet_index_range loop
+      wait until rx_clock = '1';
+      data_buffer(index) := rx_data;
+    end loop;
+  end procedure receive_packet;
+
+begin
+
+  packet_assembler : process is
+                               variable packet : packet_array;
+  begin
+    -- . . .
+    receive_packet ( recovered_data, recovered_clock, packet );
+    -- . . .
+  end process packet_assembler;
+
+  -- . . .
+
+
+  -- not in book
+
+  data_generator : recovered_data <= '1' after 5 ns,
+                                     '0' after 15 ns,
+                                     '1' after 25 ns,
+                                     '0' after 35 ns,
+                                     '0' after 45 ns,
+                                     '1' after 55 ns,
+                                     '0' after 65 ns,
+                                     '1' after 75 ns;
+
+  clock_generator : process is
+  begin
+    recovered_clock <= '0' after 2 ns, '1' after 10 ns;
+    wait for 10 ns;
+  end process clock_generator;
+
+  -- end not in book
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_10.vhd
new file mode 100644
index 0000000..5eabc8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_10.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity signal_generator is
+  generic ( period : delay_length := 20 ns;
+            pulse_count : natural := 5 );
+end entity signal_generator;
+
+-- end not in book
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture top_level of signal_generator is
+
+  signal raw_signal : std_ulogic;
+  -- . . .
+
+  procedure generate_pulse_train ( width, separation : in delay_length;
+                                   number : in natural;
+                                   signal s : out std_ulogic ) is
+  begin
+    for count in 1 to number loop
+      s <= '1', '0' after width;
+      wait for width + separation;
+    end loop;
+  end procedure generate_pulse_train;
+
+begin
+
+  raw_signal_generator : process is
+  begin
+    -- . . .
+    generate_pulse_train ( width => period / 2,
+                           separation => period - period / 2,
+                           number => pulse_count,
+                           s => raw_signal );
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process raw_signal_generator;
+
+  -- . . .
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd
new file mode 100644
index 0000000..ff33899
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_11.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_11 is
+end entity fg_07_11;
+
+
+
+architecture test of fg_07_11 is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code from book
+
+  procedure increment ( a : inout word32;  by : in word32 := X"0000_0001" ) is
+    variable sum : word32;
+    variable carry : bit := '0';
+  begin
+    for index in a'reverse_range loop
+      sum(index) := a(index) xor by(index) xor carry;
+      carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) );
+    end loop;
+    a := sum;
+  end procedure increment;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+                       variable count : word32 := X"0001_1100";
+
+  begin
+
+    -- code from book (in text)
+
+    increment(count, X"0000_0004");
+
+    increment(count);
+
+    increment(count, by => open);
+
+    -- end code from book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_12.vhd
new file mode 100644
index 0000000..5a2499d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_12.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_12 is
+end entity fg_07_12;
+
+
+
+architecture test of fg_07_12 is
+
+  -- code from book
+
+  procedure find_first_set ( v : in bit_vector;
+                             found : out boolean;
+                             first_set_index : out natural ) is
+  begin
+    for index in v'range loop
+      if v(index) = '1' then
+        found := true;
+        first_set_index := index;
+        return;
+      end if;
+    end loop;
+    found := false;
+  end procedure find_first_set;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+                       -- code from book (in text)
+
+                       variable int_req : bit_vector (7 downto 0);
+                     variable top_priority : natural;
+                     variable int_pending : boolean;
+                     -- . . .
+
+                     -- end code from book
+
+                     constant block_count : natural := 16;
+
+                     -- code from book (in text)
+
+                     variable free_block_map : bit_vector(0 to block_count-1);
+                     variable first_free_block : natural;
+                     variable free_block_found : boolean;
+                     -- . . .
+
+                     -- end code from book
+
+  begin
+    int_req := "00010000";
+
+    -- code from book (in text)
+
+    find_first_set ( int_req, int_pending, top_priority );
+
+    -- end code from book
+
+    free_block_map := (others => '0');
+
+    -- code from book (in text)
+
+    find_first_set ( free_block_map, free_block_found, first_free_block );
+
+    -- end code from book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_13.vhd
new file mode 100644
index 0000000..ee18696
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_13.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_13.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_13 is
+end entity fg_07_13;
+
+
+
+architecture test of fg_07_13 is
+
+  -- code from book
+
+  procedure bv_lt ( bv1, bv2 : in bit_vector;  result : out boolean ) is
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+  begin
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    result :=  tmp1 < tmp2;
+  end procedure bv_lt;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+                       subtype byte is bit_vector(0 to 7);
+                     variable result : boolean;
+
+  begin
+    bv_lt( byte'(X"02"), byte'(X"04"), result );
+    assert result;
+
+    bv_lt( byte'(X"02"), byte'(X"02"), result );
+    assert not result;
+
+    bv_lt( byte'(X"02"), byte'(X"02"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"04"), result );
+    assert result;
+
+    bv_lt( byte'(X"04"), byte'(X"FC"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"FC"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"FE"), result );
+    assert result;
+
+    bv_lt( byte'(X"FE"), byte'(X"FC"), result );
+    assert not result;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_14.vhd
new file mode 100644
index 0000000..f610e58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_14.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_14.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_14 is
+end entity fg_07_14;
+
+
+
+architecture test of fg_07_14 is
+
+  -- code from book
+
+  procedure check_setup ( signal data, clock : in bit;
+                          constant Tsu : in time ) is
+  begin
+    if clock'event and clock = '1' then
+      assert data'last_event >= Tsu
+        report "setup time violation" severity error;
+    end if;
+  end procedure check_setup;
+
+  -- end code from book
+
+  signal ready, phi2 : bit := '0';
+  constant Tsu_rdy_clk : delay_length := 4 ns;
+
+begin
+
+  -- code from book (in text)
+
+  check_ready_setup : check_setup ( data => ready, clock => phi2,
+                                    Tsu => Tsu_rdy_clk );
+
+  -- end code from book
+
+  clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
+
+  stimulus : ready <= '1' after 4 ns,
+                      '0' after 56 ns,
+                      '1' after 87 ns,
+                      '0' after 130 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_15.vhd
new file mode 100644
index 0000000..b54a85b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_15.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_15 is
+end entity fg_07_15;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_07_15 is
+
+  -- code from book
+
+  procedure generate_clock ( signal clk : out std_ulogic;
+                             constant Tperiod, Tpulse, Tphase : in time ) is
+  begin
+    wait for Tphase;
+    loop
+      clk <= '1', '0' after Tpulse;
+      wait for Tperiod;
+    end loop;
+  end procedure generate_clock;
+
+  -- end code from book
+
+  -- code from book (in text)
+
+  signal phi1, phi2 : std_ulogic := '0';
+  -- . . .
+
+  -- end code from book
+
+begin
+
+  -- code from book (in text)
+
+  gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
+                              Tphase => 0 ns );
+
+  gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
+                              Tphase => 25 ns );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_16.vhd
new file mode 100644
index 0000000..4069cc7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_16.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_16 is
+end entity fg_07_16;
+
+
+
+architecture test of fg_07_16 is
+
+  -- code from book
+
+  function limit ( value, min, max : integer ) return integer is
+  begin
+    if value > max then
+      return max;
+    elsif value < min then
+      return min;
+    else
+      return value;
+    end if;
+  end function limit;
+
+  -- end code from book
+
+begin
+
+  tester : process is
+
+                     variable new_temperature, current_temperature, increment : integer;
+                   variable new_motor_speed, old_motor_speed,
+                     scale_factor, error : integer;
+
+  begin
+
+    current_temperature := 75;
+    increment := 10;
+
+    -- code from book (in text)
+
+    new_temperature := limit ( current_temperature + increment, 10, 100 );
+
+    -- end code from book
+
+    increment := 60;
+    new_temperature := limit ( current_temperature + increment, 10, 100 );
+    increment := -100;
+    new_temperature := limit ( current_temperature + increment, 10, 100 );
+
+    old_motor_speed := 1000;
+    scale_factor := 5;
+    error := 5;
+
+    -- code from book (in text)
+
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limit ( error, -10, +10 );
+
+    -- end code from book
+
+    error := 15;
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limit ( error, -10, +10 );
+
+    error := -20;
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limit ( error, -10, +10 );
+
+    wait;
+  end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_17.vhd
new file mode 100644
index 0000000..ec60445
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_17.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_17.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_17 is
+end entity fg_07_17;
+
+
+
+architecture test of fg_07_17 is
+
+  -- code from book
+
+  function bv_to_natural ( bv : in bit_vector ) return natural is
+    variable result : natural := 0;
+  begin
+    for index in bv'range loop
+      result := result * 2 + bit'pos(bv(index));
+    end loop;
+    return result;
+  end function bv_to_natural;
+
+  -- end code from book
+
+  signal data : bit_vector(0 to 7);
+  constant address : bit_vector(0 to 3) := "0101";
+  constant Taccess : delay_length := 80 ns;
+
+begin
+
+  tester : process is
+
+                     constant rom_size : natural := 8;
+                   constant word_size : natural := 8;
+
+                   -- code from book (in text)
+
+                   type rom_array is array (natural range 0 to rom_size-1)
+                     of bit_vector(0 to word_size-1);
+                   variable rom_data : rom_array;
+
+                   -- end code from book
+
+  begin
+
+    rom_data := (X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07");
+
+    -- code from book (in text)
+
+    data <= rom_data ( bv_to_natural(address) ) after Taccess;
+
+    -- end code from book
+
+    wait;
+  end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_18.vhd
new file mode 100644
index 0000000..13a03b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_18.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_18 is
+end entity fg_07_18;
+
+
+architecture test of fg_07_18 is
+
+  constant target_host_id : natural := 10;
+  constant my_host_id : natural := 5;
+  type pkt_types is (control_pkt, other_pkt);
+  type pkt_header is record
+                       dest, src : natural;
+                       pkt_type : pkt_types;
+                       seq : natural;
+                     end record;
+
+begin
+
+  -- code from book
+
+  network_driver : process is
+
+                             constant seq_modulo : natural := 2**5;
+                           subtype seq_number is natural range 0 to seq_modulo-1;
+                           variable next_seq_number : seq_number := 0;
+                           -- . . .
+                           -- not in book
+                           variable new_header : pkt_header;
+                           -- end not in book
+
+                           impure function generate_seq_number return seq_number is
+                             variable number : seq_number;
+                           begin
+                             number := next_seq_number;
+                             next_seq_number := (next_seq_number + 1) mod seq_modulo;
+                             return number;
+                           end function generate_seq_number;
+
+  begin  -- network_driver
+    -- not in book
+    wait for 10 ns;
+    -- end not in book
+    -- . . .
+    new_header := pkt_header'( dest => target_host_id,
+                               src => my_host_id,
+                               pkt_type => control_pkt,
+                               seq => generate_seq_number );
+    -- . . .
+  end process network_driver;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_19.vhd
new file mode 100644
index 0000000..2201bfd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_19.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_19 is
+end entity fg_07_19;
+
+
+
+architecture test of fg_07_19 is
+
+  constant Thold_d_clk : delay_length := 3 ns;
+
+  signal clk, d : bit := '0';
+
+begin
+
+  -- code from book
+
+  hold_time_checker : process ( clk, d ) is
+                                           variable last_clk_edge_time : time := 0 fs;
+  begin
+    if clk'event and clk = '1' then
+      last_clk_edge_time := now;
+    end if;
+    if d'event then
+      assert now - last_clk_edge_time >= Thold_d_clk
+        report "hold time violation";
+    end if;
+  end process hold_time_checker;
+
+  -- end code from book
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  stimulus : d <= '1' after 15 ns,
+                  '0' after 53 ns,
+                  '1' after 72 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_20.vhd
new file mode 100644
index 0000000..793570c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_20.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_20.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+entity reg_ctrl is
+  port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
+         reg_rd, reg_wr : out std_ulogic );
+end entity reg_ctrl;
+
+architecture bool_eqn of reg_ctrl is
+begin
+
+  rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
+
+  rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
+                      and not cpu_clk;
+
+end architecture bool_eqn;
+
+-- end code from book
+
+entity fg_07_20 is
+
+end entity fg_07_20;
+
+library ieee;  
+use ieee.std_logic_1164.all;
+library stimulus;
+
+architecture test of fg_07_20 is
+
+  signal reg_addr_decoded, rd, wr, io_en,
+    cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
+  signal test_vector : std_ulogic_vector(1 to 5);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+  dut : entity work.reg_ctrl
+    port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
+
+  stimulus : process is
+  begin
+    all_possible_values( bv => test_vector,
+                         delay_between_values => 10 ns );
+    wait;
+  end process stimulus;
+
+  (reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_22.vhd
new file mode 100644
index 0000000..e74497f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_22.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity cache is
+end entity cache;
+
+-- end not in book
+
+
+
+architecture behavioral of cache is
+  -- not in book
+  subtype word is bit_vector(0 to 31);
+  signal mem_addr : natural;
+  signal mem_data_in : word;
+  signal mem_read, mem_ack : bit := '0';
+  -- end not in book
+begin
+
+  behavior : process is
+
+                       -- not in book
+                       constant block_size : positive := 4;
+                     type cache_block is array (0 to block_size - 1) of word;
+                     type store_array is array (0 to 15) of cache_block;
+                     variable data_store : store_array;
+                     variable entry_index : natural := 1;
+                     variable miss_base_address : natural := 16;
+                     -- end not in book
+
+                     -- . . .
+
+                     procedure read_block( start_address : natural;
+                                           entry : out cache_block ) is
+
+                       variable memory_address_reg : natural;
+                       variable memory_data_reg : word;
+
+                       procedure read_memory_word is
+                       begin
+                         mem_addr <= memory_address_reg;
+                         mem_read <= '1';
+                         wait until mem_ack = '1';
+                         memory_data_reg := mem_data_in;
+                         mem_read <= '0';
+                         wait until mem_ack = '0';
+                       end procedure read_memory_word;
+
+                     begin  -- read_block
+                       for offset in 0 to block_size - 1 loop
+                         memory_address_reg := start_address + offset;
+                         read_memory_word;
+                         entry(offset) := memory_data_reg;
+                       end loop;
+                     end procedure read_block;
+
+  begin  -- behavior
+    -- . . .
+    read_block( miss_base_address, data_store(entry_index) );
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process behavior;
+
+
+  -- not in book
+
+  memory : process is
+
+                     type store_array is array (0 to 31) of word;
+                   constant store : store_array :=
+                     ( X"00000000", X"00000001", X"00000002", X"00000003",
+                       X"00000004", X"00000005", X"00000006", X"00000007",
+                       X"00000008", X"00000009", X"0000000a", X"0000000b",
+                       X"0000000c", X"0000000d", X"0000000e", X"0000000f",
+                       X"00000010", X"00000011", X"00000012", X"00000013",
+                       X"00000014", X"00000015", X"00000016", X"00000017",
+                       X"00000018", X"00000019", X"0000001a", X"0000001b",
+                       X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
+
+  begin
+    wait until mem_read = '1';
+    mem_data_in <= store(mem_addr);
+    mem_ack <= '1';
+    wait until mem_read = '0';
+    mem_ack <= '0';
+  end process memory;
+
+  -- end not in book
+
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_01.vhd
new file mode 100644
index 0000000..0ceb91b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_01.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_08_01 is
+
+end entity ch_08_01;
+
+
+----------------------------------------------------------------
+
+
+library ieee;
+
+architecture test of ch_08_01 is
+begin
+
+
+  process_08_1_a : process is
+
+                             -- code from book:
+
+                             variable stored_state : ieee.std_logic_1164.std_ulogic;
+
+                           -- end of code from book
+
+  begin
+
+    wait;
+  end process process_08_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_02.vhd
new file mode 100644
index 0000000..1dc7826
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_02.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_08_02 is
+
+  -- code from book
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  procedure add ( a, b : in word32;
+                  result : out word32;  overflow : out boolean );
+
+  function "<" ( a, b : in word32 ) return boolean;
+
+  constant max_buffer_size : positive;
+
+  -- end code from book
+
+end package ch_08_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_03.vhd
new file mode 100644
index 0000000..0ab34d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_03.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_08_03 is
+
+end entity ch_08_03;
+
+
+----------------------------------------------------------------
+
+
+library ieee;
+
+architecture test of ch_08_03 is
+begin
+
+
+  process_08_3_a : process is
+
+                             -- code from book:
+
+                             use work.cpu_types;
+
+                           variable data_word : cpu_types.word;
+                           variable next_address : cpu_types.address;
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_08_3_a;
+
+
+  ----------------
+
+
+  process_08_3_b : process is
+
+                             -- code from book:
+
+                             use work.cpu_types.word, work.cpu_types.address;
+
+                           variable data_word : word;
+                           variable next_address : address;
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_08_3_b;
+
+
+  ----------------
+
+
+  block_08_3_c : block is
+
+                         -- code from book:
+
+                         use ieee.std_logic_1164.all;
+
+                       -- end of code from book
+
+  begin
+  end block block_08_3_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_04.vhd
new file mode 100644
index 0000000..8128cc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_04.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--library ieee;  use ieee.std_logic_1164.std_ulogic;
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity logic_block is
+                 port ( a, b : in std_ulogic;
+                        y, z : out std_ulogic );
+               end entity logic_block;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd
new file mode 100644
index 0000000..d349359
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+library std, work;  use std.standard.all;
+
+-- end of code from book
+
+
+                    entity ch_08_05 is
+
+                    end entity ch_08_05;
+
+
+----------------------------------------------------------------
+
+
+                    architecture test of ch_08_05 is
+                    begin
+
+
+                      process_08_4_a : process is
+
+                                                 constant a : integer := 10;
+                                               constant b : integer := 20;
+                                               variable result : boolean;
+
+                      begin
+
+                        -- code from book:
+
+                        result := std.standard."<" ( a, b );
+
+                        -- end of code from book
+
+                        wait;
+                      end process process_08_4_a;
+
+
+                    end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_01.vhd
new file mode 100644
index 0000000..ec531cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 24;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+end package cpu_types;
+
+-- end code from book
+
+
+
+package fg_08_01 is
+
+  constant status :
+    -- code from book
+    work.cpu_types.status_value
+    -- end code from book
+    :=
+    -- code from book
+    work.cpu_types.status_value'(work.cpu_types.fetch)
+    -- end code from book
+    ;
+
+end package fg_08_01;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_02.vhd
new file mode 100644
index 0000000..b81d636
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_02.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity address_decoder is
+  port ( addr : in work.cpu_types.address;
+         status : in work.cpu_types.status_value;
+         mem_sel, int_sel, io_sel : out bit );
+end entity address_decoder;
+
+--------------------------------------------------
+
+architecture functional of address_decoder is
+
+  constant mem_low : work.cpu_types.address := X"000000";
+  constant mem_high : work.cpu_types.address := X"EFFFFF";
+  constant io_low : work.cpu_types.address := X"F00000";
+  constant io_high : work.cpu_types.address := X"FFFFFF";
+
+begin
+
+  mem_decoder :
+    mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
+                          or work.cpu_types."="(status, work.cpu_types.mem_read)
+                          or work.cpu_types."="(status, work.cpu_types.mem_write) )
+               and addr >= mem_low
+   and addr <= mem_high else
+               '0';
+
+  int_decoder :
+    int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
+               '0';
+
+  io_decoder :
+    io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
+                         or work.cpu_types."="(status, work.cpu_types.io_write) )
+              and addr >= io_low
+  and addr <= io_high else
+              '0';
+
+end architecture functional;
+
+
+-- not in book
+
+entity fg_08_02 is
+end entity fg_08_02;
+
+
+architecture test of fg_08_02 is
+
+  use work.cpu_types.all;
+
+  signal addr : address := X"000000";
+  signal status : status_value := idle;
+  signal mem_sel, int_sel, io_sel : bit;
+
+begin
+
+  dut : entity work.address_decoder
+    port map ( addr => addr, status => status,
+               mem_sel => mem_sel, int_sel => int_sel, io_sel => io_sel );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"EFFFFF";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"F00000";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"FFFFFF";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_03.vhd
new file mode 100644
index 0000000..3847664
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_03.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package clock_pkg is
+
+                 constant Tpw : delay_length := 4 ns;
+
+                 signal clock_phase1, clock_phase2 : std_ulogic;
+
+               end package clock_pkg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_04.vhd
new file mode 100644
index 0000000..cf53a42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_04.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity phase_locked_clock_gen is
+                 port ( reference : in std_ulogic;
+                        phi1, phi2 : out std_ulogic );
+               end entity phase_locked_clock_gen;
+
+
+               architecture std_cell of phase_locked_clock_gen is
+
+                 --use work.clock_pkg.Tpw;
+                 use work.clock_pkg.all;
+
+               begin
+
+                 phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(reference);
+
+                 phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(reference);
+
+               end architecture std_cell;
+
+-- end not in book
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity io_controller is
+                 port ( ref_clock : in std_ulogic;  -- . . . );
+                        -- not in book
+                        other_port : in std_ulogic );
+                 -- end not in book
+               end entity io_controller;
+
+--------------------------------------------------
+
+               architecture top_level of io_controller is
+
+                 -- . . .
+
+                 -- not in book
+                 signal rd, wr, sel, width, burst : std_ulogic;
+                 signal addr : std_ulogic_vector(1 downto 0);
+                 signal ready : std_ulogic;
+                 signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+                   other_signal : std_ulogic;
+                 -- end not in book
+
+               begin
+
+                 internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
+                   port map ( reference => ref_clock,
+                              phi1 => work.clock_pkg.clock_phase1,
+                              phi2 => work.clock_pkg.clock_phase2 );
+
+                 the_bus_sequencer : entity work.bus_sequencer(fsm)
+                   port map ( rd, wr, sel, width, burst, addr(1 downto 0), ready,
+                              control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+                              -- . . . );
+                              other_signal );
+                 -- not in book
+
+                 -- . . .
+
+               end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd
new file mode 100644
index 0000000..e23e66c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bus_sequencer is
+                 port ( rd, wr, sel, width, burst : out std_ulogic;
+                        addr_low_2 : out std_ulogic_vector(1 downto 0);
+                        ready : out std_ulogic;
+                        control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+                        other_signal : out std_ulogic );
+               end entity bus_sequencer;
+
+----------------
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity state_register is
+                 port ( phi1, phi2 : in std_ulogic;
+                        next_state : in std_ulogic_vector(3 downto 0);
+                        current_state : out std_ulogic_vector(3 downto 0) );
+               end entity state_register;
+
+
+               architecture std_cell of state_register is
+
+               begin
+
+               end architecture std_cell;
+
+-- end not in book
+
+
+
+
+               architecture fsm of bus_sequencer is
+
+                 -- This architecture implements the sequencer as a finite state machine.
+                 -- NOTE: it uses the clock signals from clock_pkg to synchronize the fsm.
+
+                 signal next_state_vector : -- . . .;
+                   -- not in book
+                   std_ulogic_vector(3 downto 0);
+                 signal current_state_vector : std_ulogic_vector(3 downto 0);
+                 -- end not in book
+
+               begin
+
+                 bus_sequencer_state_register : entity work.state_register(std_cell)
+                   port map ( phi1 => work.clock_pkg.clock_phase1,
+                              phi2 => work.clock_pkg.clock_phase2,
+                              next_state => next_state_vector,
+                              -- . . . );
+                              -- not in book
+                              current_state => current_state_vector );
+                 -- end not in book
+
+                 -- . . .
+
+               end architecture fsm;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd
new file mode 100644
index 0000000..a8070f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 24;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+  subtype opcode is bit_vector(5 downto 0);
+
+  function extract_opcode ( instr_word : word ) return opcode;
+
+  constant op_nop : opcode := "000000";
+  constant op_breq : opcode := "000001";
+  constant op_brne : opcode := "000010";
+  constant op_add : opcode := "000011";
+  -- . . .
+
+end package cpu_types;
+
+
+
+-- not in book
+
+package body cpu_types is
+
+  function extract_opcode ( instr_word : word ) return opcode is
+  begin
+    return work.cpu_types.op_nop;
+  end function extract_opcode;
+
+end package body cpu_types;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_07.vhd
new file mode 100644
index 0000000..089cc34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_07.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+  interpreter : process is
+
+                          variable instr_reg : work.cpu_types.word;
+                        variable instr_opcode : work.cpu_types.opcode;
+
+  begin
+    -- . . .    -- initialize
+    loop
+      -- . . .    -- fetch instruction
+      instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
+      case instr_opcode is
+        when work.cpu_types.op_nop => null;
+        when work.cpu_types.op_breq => -- . . .
+          -- . . .
+          -- not in book
+        when others => null;
+                       -- end not in book
+      end case;
+    end loop;
+  end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd
new file mode 100644
index 0000000..a272ed2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd
@@ -0,0 +1,120 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_08.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package bit_vector_signed_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  function "-" ( bv : bit_vector ) return bit_vector;
+
+  function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  -- . . .
+
+end package bit_vector_signed_arithmetic;
+
+-- not in book
+library bv_utilities;
+use bv_utilities.bv_arithmetic;
+-- end not in book
+
+package body bit_vector_signed_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
+    -- not in book
+  begin
+    return bv_arithmetic."+"(bv1, bv2);
+  end function "+";
+  -- end not in book
+
+  function "-" ( bv : bit_vector ) return bit_vector is -- . . .
+    -- not in book
+  begin
+    return bv_arithmetic."-"(bv);
+  end function "-";
+  -- end not in book
+
+  function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
+    -- . . .
+  begin
+    -- not in book
+    -- . . .
+    return bv_arithmetic.bv_multu(bv1, bv2);
+    -- end not in book
+  end function mult_unsigned;
+
+  function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
+  begin
+    if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
+      return mult_unsigned(bv1, bv2);
+    elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
+      return -mult_unsigned(bv1, -bv2);
+    elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
+      return -mult_unsigned(-bv1, bv2);
+    else
+      return mult_unsigned(-bv1, -bv2);
+    end if;
+  end function "*";
+
+  -- . . .
+
+end package body bit_vector_signed_arithmetic;
+
+-- not in book
+
+entity fg_08_08 is
+end entity fg_08_08;
+
+library bv_utilities;
+use bv_utilities.bit_vector_signed_arithmetic.all;
+
+use std.textio.all;
+
+architecture test of fg_08_08 is
+begin
+
+  stimulus : process is
+                       variable L : line;
+  begin
+    write(L, X"0002" + X"0005");
+    writeline(output, L);
+    write(L, X"0002" + X"FFFE");
+    writeline(output, L);
+    write(L, - X"0005");
+    writeline(output, L);
+    write(L, - X"FFFE");
+    writeline(output, L);
+    write(L, X"0002" * X"0005");
+    writeline(output, L);
+    write(L, X"0002" * X"FFFD");
+    writeline(output, L);
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_09.vhd
new file mode 100644
index 0000000..c1f91a6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_09.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+  interpreter : process is
+
+                          use work.cpu_types.all;
+
+                        variable instr_reg : word;
+                        variable instr_opcode : opcode;
+
+  begin
+    -- . . .    -- initialize
+    loop
+      -- . . .    -- fetch instruction
+      instr_opcode := extract_opcode ( instr_reg );
+      case instr_opcode is
+        when op_nop => null;
+        when op_breq => -- . . .
+          -- . . .
+          -- not in book
+        when others => null;
+                       -- end not in book
+      end case;
+    end loop;
+  end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_10.vhd
new file mode 100644
index 0000000..85bca11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_10.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_08_10 is
+end entity fg_08_10;
+
+
+
+architecture test of fg_08_10 is
+
+  -- code from book
+
+  function "<" ( a, b : bit_vector ) return boolean is
+    variable tmp1 : bit_vector(a'range) := a;
+    variable tmp2 : bit_vector(b'range) := b;
+  begin
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return std.standard."<" ( tmp1, tmp2 );
+  end function "<";
+
+  -- end code from book
+
+  signal a, b : bit_vector(7 downto 0);
+  signal result : boolean;
+
+begin
+
+  dut : result <= a < b;
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    a <= X"02";  b <= X"04";  wait for 10 ns;
+    a <= X"02";  b <= X"02";  wait for 10 ns;
+    a <= X"02";  b <= X"01";  wait for 10 ns;
+    a <= X"02";  b <= X"FE";  wait for 10 ns;
+    a <= X"FE";  b <= X"02";  wait for 10 ns;
+    a <= X"FE";  b <= X"FE";  wait for 10 ns;
+    a <= X"FE";  b <= X"FC";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_01.vhd
new file mode 100644
index 0000000..4055f30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_01.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_09_01 is
+
+end entity ch_09_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_09_01 is
+begin
+
+
+  process_09_1_a : process is
+
+                             -- code from book:
+
+                             type register_array is array (0 to 15) of bit_vector(31 downto 0);
+
+                           type register_set is record
+                                                  general_purpose_registers : register_array;
+                                                  program_counter : bit_vector(31 downto 0);
+                                                  program_status : bit_vector(31 downto 0);
+                                                end record;
+
+                           variable CPU_registers : register_set;
+
+                           -- code revised to work around MTI bugs mt015 and mt016
+                           -- alias PSW is CPU_registers.program_status;
+                           -- alias PC is CPU_registers.program_counter;
+                           -- alias GPR is CPU_registers.general_purpose_registers;
+
+                           alias PSW : bit_vector(31 downto 0) is CPU_registers.program_status;
+                           alias PC : bit_vector(31 downto 0) is CPU_registers.program_counter;
+                           alias GPR : register_array is CPU_registers.general_purpose_registers;
+
+                           -- alias SP is CPU_registers.general_purpose_registers(15);
+
+                           alias SP : bit_vector(31 downto 0) is CPU_registers.general_purpose_registers(15);
+
+                           -- alias interrupt_level is PSW(30 downto 26);
+
+                           alias interrupt_level : bit_vector(30 downto 26) is PSW(30 downto 26);
+
+                           -- end revision
+
+                           -- end of code from book
+
+                           procedure procedure_09_1_b is
+
+                             -- code from book:
+
+                             -- code revised to work around MTI bug mt016
+                             -- alias SP is GPR(15);
+
+                             alias SP : bit_vector(31 downto 0) is GPR(15);
+
+                             -- end revision
+
+                             alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26);
+
+                             -- end of code from book
+
+                           begin
+                           end procedure procedure_09_1_b;
+
+  begin
+    wait;
+  end process process_09_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_02.vhd
new file mode 100644
index 0000000..39124a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_02.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_09_02 is
+
+end entity ch_09_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_09_02 is
+begin
+
+
+  process_09_2_a : process is
+
+                             -- code from book:
+
+                             alias binary_string is bit_vector;
+
+                           variable s1, s2 : binary_string(0 to 7);
+                           -- . . .
+
+                           -- end of code from book
+
+  begin
+
+    s1 := "10101010";
+    s2 := "11110000";
+
+    -- code from book:
+
+    s1 := s1 and not s2;
+
+    -- end of code from book
+
+    wait;
+  end process process_09_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_03.vhd
new file mode 100644
index 0000000..8b29747
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_03.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package system_types is
+
+  -- code from book
+
+  type system_status is (idle, active, overloaded);
+
+  -- end code from book
+
+end package system_types;
+
+
+
+
+entity ch_09_03 is
+
+end entity ch_09_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_09_03 is
+
+  -- code from book
+
+  alias status_type is work.system_types.system_status;
+
+  -- end code from book
+
+begin
+
+
+  process_09_2_b : process is
+
+                             variable status : status_type := idle;
+
+  begin
+    wait for 10 ns;
+    status := active;
+    wait for 10 ns;
+    status := overloaded;
+
+    wait;
+  end process process_09_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_04.vhd
new file mode 100644
index 0000000..d4ef534
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_04.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_04.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package arithmetic_ops is
+
+  -- code from book
+
+  procedure increment ( bv : inout bit_vector;  by : in integer := 1 );
+
+  procedure increment ( int : inout integer;  by : in integer := 1 );
+
+  -- end code from book
+
+end package arithmetic_ops;
+
+package body arithmetic_ops is
+
+  procedure increment ( bv : inout bit_vector;  by : in integer := 1 ) is
+  begin
+  end procedure increment;
+
+  procedure increment ( int : inout integer;  by : in integer := 1 ) is
+  begin
+  end procedure increment;
+
+end package body arithmetic_ops;
+
+
+entity ch_09_04 is
+
+end entity ch_09_04;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of ch_09_04 is
+
+  -- code from book
+
+  -- MTI bug mt017
+  -- alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];
+
+  alias int_increment is work.arithmetic_ops.increment [ integer, integer ];
+
+  -- workaround to avoid MTI bug mt018
+  -- alias "*" is "and" [ bit, bit return bit ];
+
+  alias "*" is std.standard."and" [ bit, bit return bit ];
+
+  -- alias "+" is "or" [ bit, bit return bit ];
+
+  alias "+" is std.standard."or" [ bit, bit return bit ];
+
+  -- alias "-" is "not" [ bit return bit ];
+
+  alias "-" is std.standard."not" [ bit return bit ];
+
+  -- end workaround
+
+  alias high is std.standard.'1' [ return bit ];
+
+  -- end code from book
+
+  signal a, b, c, s : bit := '0';
+  signal test_vector : bit_vector(1 to 3);
+  signal test_high : bit := high;
+
+begin
+
+  -- code from book
+
+  -- workaround to avoid MTI bug mt018
+  -- s <= a * b + (-a) * c;
+
+  s <= (a and b) or ((not a) and c);
+
+  -- end workaround
+
+  -- end code from book
+
+  stimulus : all_possible_values ( bv => test_vector,
+				   delay_between_values => 10 ns );
+
+  (a, b, c) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_01.vhd
new file mode 100644
index 0000000..f87aefa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_01.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+package alu_types is
+
+  constant data_width : positive := 32;
+
+end package alu_types;
+
+
+package io_types is
+
+  constant data_width : positive := 32;
+
+end package io_types;
+
+
+entity controller_system is
+end entity controller_system;
+
+-- end not in book
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.alu_types.all, work.io_types.all;
+
+architecture structural of controller_system is
+
+  alias alu_data_width is work.alu_types.data_width;
+  alias io_data_width is work.io_types.data_width;
+
+  signal alu_in1, alu_in2,
+    alu_result : std_logic_vector(0 to alu_data_width - 1);
+  signal  io_data : std_logic_vector(0 to io_data_width - 1);
+  -- . . .
+
+  -- not in book
+  -- following should not analyze: data_width not directly visible
+  -- constant test : positive := data_width;
+  -- end not in book
+
+begin
+
+  -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_02.vhd
new file mode 100644
index 0000000..1bcc30c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_02.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package fg_09_02_a is
+
+  -- code from book (in text)
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  -- end code from book
+
+end package fg_09_02_a;
+
+
+
+package body fg_09_02_a is
+
+  -- code from book
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+    alias norm1 : bit_vector(1 to bv1'length) is bv1;
+    alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+    variable result : bit_vector(1 to bv1'length);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "arguments of different length" severity failure;
+    else
+      for index in norm1'reverse_range loop
+        result(index) := norm1(index) xor norm2(index) xor carry;
+        carry := ( norm1(index) and norm2(index) )
+                 or ( carry and ( norm1(index) or norm2(index) ) );
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+  -- end code from book
+
+end package body fg_09_02_a;
+
+
+
+
+entity fg_09_02_b is
+end entity fg_09_02_b;
+
+
+architecture test of fg_09_02_b is
+
+  use work.fg_09_02_a.all;
+
+begin
+
+  stimulus : process is
+                       use std.textio.all;
+                     variable L : line;
+  begin
+    write(L, X"0002" + X"0000");
+    writeline(output, L);
+    write(L, X"0002" + X"0005");
+    writeline(output, L);
+    write(L, X"0002" + X"FFFE");
+    writeline(output, L);
+    
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd
new file mode 100644
index 0000000..d2cc16e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 32;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+end package cpu_types;
+
+
+
+package bit_vector_unsigned_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+end package bit_vector_unsigned_arithmetic;
+
+
+package body bit_vector_unsigned_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+    alias norm1 : bit_vector(1 to bv1'length) is bv1;
+    alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+    variable result : bit_vector(1 to bv1'length);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "arguments of different length" severity failure;
+    else
+      for index in norm1'reverse_range loop
+        result(index) := norm1(index) xor norm2(index) xor carry;
+        carry := ( norm1(index) and norm2(index) )
+                 or ( carry and ( norm1(index) or norm2(index) ) );
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+end package  body bit_vector_unsigned_arithmetic;
+
+
+
+
+-- code from book
+
+package DMA_controller_types_and_utilities is
+
+  alias word is work.cpu_types.word;
+  alias address is work.cpu_types.address;
+  alias status_value is work.cpu_types.status_value;
+
+  alias "+" is work.bit_vector_unsigned_arithmetic."+"
+    [ bit_vector, bit_vector return bit_vector ];
+
+  -- . . .
+
+end package DMA_controller_types_and_utilities;
+
+-- end code from book
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_04.vhd
new file mode 100644
index 0000000..260eaf1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_04.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity DMA_controller is
+end entity DMA_controller;
+
+-- end not in book
+
+
+
+architecture behavioral of DMA_controller is
+
+  use work.DMA_controller_types_and_utilities.all;
+
+begin
+
+  behavior : process is
+
+                       variable address_reg0, address_reg1 : address;
+                     variable count_reg0, count_reg1 : word;
+                     -- . . .
+
+  begin
+    -- . . .
+    address_reg0 := address_reg0 + X"0000_0004";
+    -- . . .
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd
new file mode 100644
index 0000000..ff9d5c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_alu-b.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behavior of alu is
+begin
+
+  alu_op: process (s1, s2, func) is
+
+                                   constant Tpd : delay_length := 10 ns;
+
+                                 variable bv_s1 : bit_vector(s1'range) := To_bitvector(s1);
+                                 variable bv_s2 : bit_vector(s2'range) := To_bitvector(s2);
+                                 variable temp_result : bit_vector(result'range);
+                                 constant zero_result : bit_vector(result'range) := (others => '0');
+                                 variable temp_overflow : boolean;
+
+                                 type boolean_to_X01_table is array (boolean) of X01;
+                                 constant boolean_to_X01 : boolean_to_X01_table
+                                   := ( false => '0', true => '1' );
+
+  begin
+    case func is
+      when alu_add =>
+        bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_addu =>
+        bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_sub =>
+        bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_subu =>
+        bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when others =>
+        report "alu: illegal function code" severity error;
+        temp_result := X"0000_0000";
+    end case;
+    result <= To_X01(temp_result) after Tpd;
+    zero <= boolean_to_X01(temp_result = zero_result) after Tpd;
+    negative <= To_X01(temp_result(temp_result'left)) after Tpd;
+    overflow <= boolean_to_X01(temp_overflow) after Tpd;
+  end process alu_op;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu.vhd
new file mode 100644
index 0000000..a9fadd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_alu.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+               use work.alu_types.all;
+
+               entity alu is
+                 port ( s1, s2 : in std_ulogic_vector;
+                        result : out std_ulogic_vector;
+                        func : in alu_func;
+                        zero, negative, overflow : out std_ulogic );
+               end entity alu;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alut.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alut.vhd
new file mode 100644
index 0000000..359cdf5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alut.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_alut.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package alu_types is
+
+                 subtype alu_func is std_ulogic_vector(3 downto 0);
+
+                 constant alu_add : alu_func := "0000";
+                 constant alu_addu : alu_func := "0001";
+                 constant alu_sub : alu_func := "0010";
+                 constant alu_subu : alu_func := "0011";
+
+               end package alu_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd
new file mode 100644
index 0000000..0e81119
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd
@@ -0,0 +1,1034 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use std.textio.all, bv_utilities.bv_arithmetic.all;
+
+architecture bench of bv_test is
+  
+begin
+
+  process is
+
+            variable L : line;
+          variable byte : bit_vector(0 to 7);
+          variable word : bit_vector(1 to 32);
+          variable half_byte : bit_vector(1 to 4);
+          variable overflow, div_by_zero, result : boolean;
+
+  begin
+    wait for 1 ns;
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    -- test bit_vector to numeric conversions
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing bv_to_natural:"));
+    writeline(output, L);
+
+    write(L, string'("  bv_to_natural(X""02"") = "));
+    write(L, bv_to_natural(X"02"));
+    writeline(output, L);
+    assert bv_to_natural(X"02") = 2;
+
+    write(L, string'("  bv_to_natural(X""FE"") = "));
+    write(L, bv_to_natural(X"FE"));
+    writeline(output, L);
+    assert bv_to_natural(X"FE") = 254;
+
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing natural_to_bv:"));
+    writeline(output, L);
+
+    write(L, string'("  natural_to_bv(2) = "));
+    write(L, natural_to_bv(2, 8));
+    writeline(output, L);
+    assert natural_to_bv(2, 8) = X"02";
+
+    write(L, string'("  natural_to_bv(254) = "));
+    write(L, natural_to_bv(254, 8));
+    writeline(output, L);
+    assert natural_to_bv(254, 8) = X"FE";
+
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing bv_to_integer:"));
+    writeline(output, L);
+
+    write(L, string'("  bv_to_integer(X""02"") = "));
+    write(L, bv_to_integer(X"02"));
+    writeline(output, L);
+    assert bv_to_integer(X"02") = 2;
+
+    write(L, string'("  bv_to_integer(X""FE"") = "));
+    write(L, bv_to_integer(X"FE"));
+    writeline(output, L);
+    assert bv_to_integer(X"FE") = -2;
+
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing integer_to_bv:"));
+    writeline(output, L);
+
+    write(L, string'("  integer_to_bv(2) = "));
+    write(L, integer_to_bv(2, 8));
+    writeline(output, L);
+    assert integer_to_bv(2, 8) = X"02";
+
+    write(L, string'("  integer_to_bv(-2) = "));
+    write(L, integer_to_bv(-2, 8));
+    writeline(output, L);
+    assert integer_to_bv(-2, 8) = X"FE";
+
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    --  Arithmetic operations
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    ----------------------------------------------------------------
+    -- bv_add: Signed addition with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_add with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    bv_add(X"02", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"04" and not overflow;
+
+    write(L, string'("  2+(-3) = "));
+    bv_add(X"02", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FF" and not overflow;
+
+    write(L, string'("  64+64 = "));
+    bv_add(X"40", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    write(L, string'("  -64+(-64) = "));
+    bv_add(X"C0", X"C0", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    ----------------------------------------------------------------
+    -- "+": Signed addition without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""+"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    byte := X"02" + X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"04";
+
+    write(L, string'("  2+(-3) = "));
+    byte := X"02" + X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FF";
+
+    write(L, string'("  64+64 = "));
+    byte := X"40" + X"40";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -64+(-64) = "));
+    byte := X"C0" + X"C0";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    ----------------------------------------------------------------
+    -- bv_sub: Signed subtraction with overflow detection
+    ----------------------------------------------------------------
+    
+    writeline(output, L);
+    write(L, string'("Testing bv_sub with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2-2 = "));
+    bv_sub(X"02", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and not overflow;
+
+    write(L, string'("  2-(-3) = "));
+    bv_sub(X"02", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"05" and not overflow;
+
+    write(L, string'("  64-(-64) = "));
+    bv_sub(X"40", X"C0", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    write(L, string'("  -64-64 = "));
+    bv_sub(X"C0", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    ----------------------------------------------------------------
+    -- "-": Signed subtraction without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""-"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2-2 = "));
+    byte := X"02" - X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  2-(-3) = "));
+    byte := X"02" - X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"05";
+
+    write(L, string'("  64-(-64) = "));
+    byte := X"40" - X"C0";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -64-64 = "));
+    byte := X"C0" - X"40";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    ----------------------------------------------------------------
+    -- bv_addu:  Unsigned addition with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_addu with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    bv_addu(X"02", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"04" and not overflow;
+
+    write(L, string'("  64+64 = "));
+    bv_addu(X"40", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    write(L, string'("  128+128 = "));
+    bv_addu(X"80", X"80", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    ----------------------------------------------------------------
+    -- bv_addu: Unsigned addition without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_addu without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    byte := bv_addu(X"02", X"02");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"04";
+
+    write(L, string'("  64+64 = "));
+    byte := bv_addu(X"40", X"40");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  128+128 = "));
+    byte := bv_addu(X"80", X"80");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_subu: Unsigned subtraction with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_subu with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  3-2 = "));
+    bv_subu(X"03", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"01" and not overflow;
+
+    write(L, string'("  64-64 = "));
+    bv_subu(X"40", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and not overflow;
+
+    write(L, string'("  64-128 = "));
+    bv_subu(X"40", X"80", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"C0" and overflow;
+
+    ----------------------------------------------------------------
+    -- bv_subu: Unsigned subtraction without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_subu without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  3-2 = "));
+    byte := bv_subu(X"03", X"02");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"01";
+
+    write(L, string'("  64-64 = "));
+    byte := bv_subu(X"40", X"40");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  64-128 = "));
+    byte := bv_subu(X"40", X"80");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"C0";
+
+    ----------------------------------------------------------------
+    -- bv_neg: Signed negation with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_neg with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  -(3) = "));
+    bv_neg(X"03", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FD" and not overflow;
+
+    write(L, string'("  -(-3) = "));
+    bv_neg(X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"03" and not overflow;
+
+    write(L, string'("  -(127) = "));
+    bv_neg(X"7F", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"81" and not overflow;
+
+    write(L, string'("  -(-128) = "));
+    bv_neg(X"80", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    ----------------------------------------------------------------
+    -- "-": Signed negation without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""-"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  -(3) = "));
+    byte := - X"03";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FD";
+
+    write(L, string'("  -(-3) = "));
+    byte := - X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  -(127) = "));
+    byte := - X"7F";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"81";
+
+    write(L, string'("  -(-128) = "));
+    byte := - X"80";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    ----------------------------------------------------------------
+    -- bv_mult: Signed multiplication with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_mult with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*(-3) = "));
+    bv_mult(X"05", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"F1" and not overflow;
+
+    write(L, string'("  (-5)*(-3) = "));
+    bv_mult(X"FB", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"0F" and not overflow;
+
+    write(L, string'("  16*8 = "));
+    bv_mult(X"10", X"08", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    write(L, string'("  16*16 = "));
+    bv_mult(X"10", X"10", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    write(L, string'("  16*(-8) = "));
+    bv_mult(X"10", X"F8", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    write(L, string'("  16*(-16) = "));
+    bv_mult(X"10", X"F0", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    ----------------------------------------------------------------
+    -- "*":  Signed multiplication without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""*"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*(-3) = "));
+    byte := X"05" * X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"F1";
+
+    write(L, string'("  (-5)*(-3) = "));
+    byte := X"FB" * X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"0F";
+
+    write(L, string'("  16*8 = "));
+    byte := X"10" * X"08";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  16*16 = "));
+    byte := X"10" * X"10";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  16*(-8) = "));
+    byte := X"10" * X"F8";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  16*(-16) = "));
+    byte := X"10" * X"F0";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_multu:  Unsigned multiplication with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_multu with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*7 = "));
+    bv_multu(X"05", X"07", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"23" and not overflow;
+
+    write(L, string'("  16*8 = "));
+    bv_multu(X"10", X"08", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    write(L, string'("  16*16 = "));
+    bv_multu(X"10", X"10", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    ----------------------------------------------------------------
+    --  bv_multu: Unsigned multiplication without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_multu without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*7 = "));
+    byte := bv_multu(X"05", X"07");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"23";
+
+    write(L, string'("  16*8 = "));
+    byte := bv_multu(X"10", X"08");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  16*16 = "));
+    byte := bv_multu(X"10", X"10");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_div: Signed division with divide by zero and overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_div with flags:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    bv_div(X"07", X"02", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"03" and not div_by_zero and not overflow;
+
+    write(L, string'("  -7/2 = "));
+    bv_div(X"F9", X"02", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FD" and not div_by_zero and not overflow;
+
+    write(L, string'("  7/-2 = "));
+    bv_div(X"07", X"FE", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FD" and not div_by_zero and not overflow;
+
+    write(L, string'("  -7/-2 = "));
+    bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"03" and not div_by_zero and not overflow;
+
+    write(L, string'("  -128/1 = "));
+    bv_div(X"80", X"01", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not div_by_zero and not overflow;
+
+    write(L, string'("  -128/-1 = "));
+    bv_div(X"80", X"FF", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not div_by_zero and overflow;
+
+    write(L, string'("  -16/0 = "));
+    bv_div(X"F0", X"00", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and div_by_zero and not overflow;
+
+    ----------------------------------------------------------------
+    -- "/": Signed division without divide by zero and overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""/"" without flags:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    byte := X"07" / X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  -7/2 = "));
+    byte := X"F9" / X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FD";
+
+    write(L, string'("  7/-2 = "));
+    byte := X"07" / X"FE";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FD";
+
+    write(L, string'("  -7/-2 = "));
+    byte := X"F9" / X"FE";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  -128/1 = "));
+    byte := X"80" / X"01";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -128/-1 = "));
+    byte := X"80" / X"FF";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -16/0 = "));
+    byte := X"F0" / X"00";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_divu: Unsigned division with divide by zero detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_divu with flag:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    bv_divu(X"07", X"02", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"03" and not div_by_zero;
+
+    write(L, string'("  14/7 = "));
+    bv_divu(X"0E", X"07", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"02" and not div_by_zero;
+
+    write(L, string'("  16/1 = "));
+    bv_divu(X"10", X"01", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"10" and not div_by_zero;
+
+    write(L, string'("  16/0 = "));
+    bv_divu(X"10", X"00", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"10" and div_by_zero;
+
+    write(L, string'("  16/16 = "));
+    bv_divu(X"10", X"10", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"01" and not div_by_zero;
+
+    write(L, string'("  1/16 = "));
+    bv_divu(X"01", X"10", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"00" and not div_by_zero;
+
+    write(L, string'("  255/1 = "));
+    bv_divu(X"FF", X"01", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"FF" and not div_by_zero;
+
+    ----------------------------------------------------------------
+    -- bv_divu: Unsigned division without divide by zero detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_divu without flag:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    byte := bv_divu(X"07", X"02");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  14/7 = "));
+    byte := bv_divu(X"0E", X"07");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"02";
+
+    write(L, string'("  16/1 = "));
+    byte := bv_divu(X"10", X"01");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"10";
+
+    write(L, string'("  16/0 = "));
+    byte := bv_divu(X"10", X"00");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  16/16 = "));
+    byte := bv_divu(X"10", X"10");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"01";
+
+    write(L, string'("  1/16 = "));
+    byte := bv_divu(X"01", X"10");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  255/1 = "));
+    byte := bv_divu(X"FF", X"01");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FF";
+
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    --  Arithmetic comparison operators.
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    ----------------------------------------------------------------
+    -- bv_lt: Signed less than comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_lt:"));
+    writeline(output, L);
+
+    write(L, string'("  2 < 2 = "));
+    result := bv_lt(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    write(L, string'("  2 < 3 = "));
+    result := bv_lt(X"02", X"03");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -2 < 2 = "));
+    result := bv_lt(X"FE", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 < -3 = "));
+    result := bv_lt(X"02", X"FD");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    -- bv_le: Signed less than or equal comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_le:"));
+    writeline(output, L);
+
+    write(L, string'("  2 <= 2 = "));
+    result := bv_le(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 <= 3 = "));
+    result := bv_le(X"02", X"03");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -2 <= 2 = "));
+    result := bv_le(X"FE", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 <= -3 = "));
+    result := bv_le(X"02", X"FD");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    -- bv_gt: Signed greater than comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_gt:"));
+    writeline(output, L);
+
+    write(L, string'("  2 > 2 = "));
+    result := bv_gt(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    write(L, string'("  3 > 2 = "));
+    result := bv_gt(X"03", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 > -2 = "));
+    result := bv_gt(X"02", X"FE");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -3 > 2 = "));
+    result := bv_gt(X"FD", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    -- bv_ge: Signed greater than or equal comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_ge:"));
+    writeline(output, L);
+
+    write(L, string'("  2 >= 2 = "));
+    result := bv_ge(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  3 >= 2 = "));
+    result := bv_ge(X"03", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 >= -2 = "));
+    result := bv_ge(X"02", X"FE");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -3 >= 2 = "));
+    result := bv_ge(X"FD", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    --  Extension operators - convert a bit vector to a longer one
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    ----------------------------------------------------------------
+    -- bv_sext: Sign extension
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_sext:"));
+    writeline(output, L);
+
+    write(L, string'("  sext(X""02"", 32) = "));
+    word := bv_sext(X"02", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"00000002";
+
+    write(L, string'("  sext(X""FE"", 32) = "));
+    word := bv_sext(X"FE", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"FFFFFFFE";
+
+    write(L, string'("  sext(X""02"", 8) = "));
+    byte := bv_sext(X"02", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"02";
+
+    write(L, string'("  sext(X""FE"", 8) = "));
+    byte := bv_sext(X"FE", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FE";
+
+    write(L, string'("  sext(X""02"", 4) = "));
+    half_byte := bv_sext(X"02", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"2";
+
+    write(L, string'("  sext(X""FE"", 4) = "));
+    half_byte := bv_sext(X"FE", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"E";
+
+    ----------------------------------------------------------------
+    -- bv_zext" Zero extension
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_zext:"));
+    writeline(output, L);
+
+    write(L, string'("  zext(X""02"", 32) = "));
+    word := bv_zext(X"02", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"00000002";
+
+    write(L, string'("  zext(X""FE"", 32) = "));
+    word := bv_zext(X"FE", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"000000FE";
+
+    write(L, string'("  zext(X""02"", 8) = "));
+    byte := bv_zext(X"02", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"02";
+
+    write(L, string'("  zext(X""FE"", 8) = "));
+    byte := bv_zext(X"FE", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FE";
+
+    write(L, string'("  zext(X""02"", 4) = "));
+    half_byte := bv_zext(X"02", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"2";
+
+    write(L, string'("  zext(X""FE"", 4) = "));
+    half_byte := bv_zext(X"FE", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"E";
+
+
+    wait;
+  end process;
+
+end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat.vhd
new file mode 100644
index 0000000..14e2590
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_bvat.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity bv_test is
+  
+end entity bv_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkdiv.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkdiv.vhd
new file mode 100644
index 0000000..f0cc387
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkdiv.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_chkdiv.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity check_div is
+end entity check_div;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behav of check_div is
+
+begin
+
+  checker : process is
+
+                      variable bv_a, bv_b, bv_quotient, bv_remainder : bit_vector(3 downto 0);
+                    variable div_by_zero : boolean;
+
+  begin
+    for a in 0 to 15 loop
+      for b in 0 to 15 loop
+	bv_a := natural_to_bv(a, bv_a'length);
+        bv_b := natural_to_bv(b, bv_b'length);
+        bv_divu(bv_a, bv_b, bv_quotient, bv_remainder, div_by_zero);
+	if b = 0 then
+	  assert div_by_zero
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": div_by_zero not true";
+	else
+	  assert not div_by_zero
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": div_by_zero not false";
+	  assert bv_to_natural(bv_quotient) = a / b
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": quotient = " & integer'image(bv_to_natural(bv_quotient));
+	  assert bv_to_natural(bv_remainder) = a rem b
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": remainder = " & integer'image(bv_to_natural(bv_remainder));
+	end if;
+      end loop;
+    end loop;
+    wait;
+  end process checker;
+
+end architecture behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkmult.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkmult.vhd
new file mode 100644
index 0000000..588a0fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkmult.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_chkmult.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity check_mult is
+end entity check_mult;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behav of check_mult is
+
+begin
+
+  checker : process is
+
+                      variable bv_a, bv_b, bv_product : bit_vector(3 downto 0);
+                    variable overflow : boolean;
+
+  begin
+    for a in 0 to 15 loop
+      for b in 0 to 15 loop
+	bv_a := natural_to_bv(a, bv_a'length);
+        bv_b := natural_to_bv(b, bv_b'length);
+        bv_multu(bv_a, bv_b, bv_product, overflow);
+	if a * b > 15 then
+	  assert overflow
+	    report integer'image(a) & '*' & integer'image(b)
+            & ": overflow not true";
+	else
+	  assert not overflow
+	    report integer'image(a) & '*' & integer'image(b)
+            & ": overflow not false";
+	  assert bv_to_natural(bv_product) = a * b
+	    report integer'image(a) & '*' & integer'image(b)
+            & ": product = " & integer'image(bv_to_natural(bv_product));
+	end if;
+      end loop;
+    end loop;
+    wait;
+  end process checker;
+
+end architecture behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_01.vhd
new file mode 100644
index 0000000..cfa42c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_01.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_ch_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_11_01 is
+
+end entity ch_11_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_11_01 is
+
+  type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
+
+  -- code from book:
+
+  type small_int is range 1 to 4;
+  type small_array is array (small_int range <>) of -- . . . ;
+    -- not in book
+    MVL4_ulogic;
+  -- end not in book
+
+  -- end of code from book
+
+  type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
+    variable result : MVL4_ulogic := 'Z';
+  begin
+    for index in contribution'range loop
+      result := resolution_table(result, contribution(index));
+    end loop;
+    return result;
+  end function resolve_MVL4;
+
+  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+  signal s : MVL4_logic;
+
+begin
+
+  driver_1 : s <= 'Z';
+
+  driver_2 : s <= 'Z';
+
+  driver_3 : s <= 'Z';
+
+  driver_4 : s <= 'Z';
+
+  driver_5 : s <= 'Z';
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_02.vhd
new file mode 100644
index 0000000..9f4b2e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_02.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_ch_11_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_11_02 is
+
+  -- code from book
+
+  type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+  subtype std_logic is resolved std_ulogic;
+
+  type std_logic_vector is array ( natural range <>) of std_logic;
+
+  subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
+  subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
+  subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
+  subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')
+
+  -- end code from book
+
+end package ch_11_02;
+
+
+
+package body ch_11_02 is
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic is
+  begin
+  end function resolved;
+
+end package body ch_11_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_03.vhd
new file mode 100644
index 0000000..db6fda4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_03.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_ch_11_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity IO_section is
+                 port ( data_ack : inout std_logic;  -- . . . );
+                        -- not in book
+                        other_port : in std_ulogic := 'U' );
+                 -- end not in book
+               end entity IO_section;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd
new file mode 100644
index 0000000..f422f83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_11_01 is
+end entity fg_11_01;
+
+
+
+architecture test of fg_11_01 is
+
+  -- code from book (in text)
+
+  type tri_state_logic is ('0', '1', 'Z');
+
+  type tri_state_logic_array is array (integer range <>) of tri_state_logic;
+
+  -- end code from book
+
+
+  -- code from book
+
+  function resolve_tri_state_logic ( values : in tri_state_logic_array )
+    return tri_state_logic is
+    variable result : tri_state_logic := 'Z';
+  begin
+    for index in values'range loop
+      if values(index) /= 'Z' then
+        result := values(index);
+      end if;
+    end loop;
+    return result;
+  end function resolve_tri_state_logic;
+
+  -- end code from book
+
+
+  -- code from book (in text)
+
+  signal s1 : resolve_tri_state_logic tri_state_logic;
+
+  subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
+
+  signal s2, s3 : resolved_logic;
+
+  -- end code from book
+
+begin
+
+  source_1 : s1 <= 'Z',
+                   '0' after 10 ns,
+                   'Z' after 20 ns,
+                   '1' after 30 ns,
+                   'Z' after 40 ns,
+	           '1' after 200 ns,
+	           'Z' after 220 ns;
+
+  source_2 : s1 <= 'Z',
+                   '0' after 110 ns,
+                   'Z' after 120 ns,
+                   '1' after 130 ns,
+                   'Z' after 140 ns,
+	           '1' after 200 ns,
+	           '0' after 210 ns,
+	           'Z' after 220 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_02.vhd
new file mode 100644
index 0000000..79d85da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_02.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package MVL4 is
+
+  type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
+
+  type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic;
+
+  function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+    return MVL4_ulogic;
+
+  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+  -- code from book (in text)
+
+  type MVL4_logic_vector is array (natural range <>) of MVL4_logic;
+
+  -- end code from book
+
+end package MVL4;
+
+--------------------------------------------------
+
+package body MVL4 is
+
+  type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+    return MVL4_ulogic is
+    variable result : MVL4_ulogic := 'Z';
+  begin
+    for index in contribution'range loop
+      result := resolution_table(result, contribution(index));
+    end loop;
+    return result;
+  end function resolve_MVL4;
+
+end package body MVL4;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_03.vhd
new file mode 100644
index 0000000..34bd076
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_03.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+use work.MVL4.all;
+
+entity tri_state_buffer is
+  port ( a, enable : in MVL4_ulogic;  y : out MVL4_ulogic );
+end entity tri_state_buffer;
+
+--------------------------------------------------
+
+architecture behavioral of tri_state_buffer is
+begin
+
+  y <= 'Z' when enable = '0' else
+       a   when enable = '1' and (a = '0' or a = '1') else
+       'X';
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_04.vhd
new file mode 100644
index 0000000..c350711
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_04.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity misc_logic is
+end entity misc_logic;
+
+-- end not in book
+
+
+
+use work.MVL4.all;
+
+architecture gate_level of misc_logic is
+
+  signal src1, src1_enable : MVL4_ulogic;
+  signal src2, src2_enable : MVL4_ulogic;
+  signal selected_val : MVL4_logic;
+  -- . . .
+
+begin
+
+  src1_buffer : entity work.tri_state_buffer(behavioral)
+    port map ( a => src1, enable => src1_enable, y => selected_val );
+
+  src2_buffer : entity work.tri_state_buffer(behavioral)
+    port map ( a => src2, enable => src2_enable, y => selected_val );
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    src1_enable <= '0';  src2_enable <= '0';  wait for 10 ns;
+    src1 <= '0';         src2 <= '1';         wait for 10 ns;
+    src1_enable <= '1';                       wait for 10 ns;
+    src1 <= 'Z';                              wait for 10 ns;
+    src1 <= '1';                              wait for 10 ns;
+    src1_enable <= '0';                       wait for 10 ns;
+    src2_enable <= '1';  wait for 10 ns;
+    src2 <= 'Z';         wait for 10 ns;
+    src2 <= '0';         wait for 10 ns;
+    src2_enable <= '0';  wait for 10 ns;
+    src1_enable <= '1';  src2_enable <= '1';  wait for 10 ns;
+    src1 <= '0';                              wait for 10 ns;
+    src1 <= 'X';                              wait for 10 ns;
+    src1 <= '1';         src2 <= '1';         wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture gate_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_05.vhd
new file mode 100644
index 0000000..91c13bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_05.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package words is
+
+  type X01Z is ('X', '0', '1', 'Z');
+  type uword is array (0 to 31) of X01Z;
+
+  type uword_vector is array (natural range <>) of uword;
+
+  function resolve_word ( contribution : uword_vector ) return uword;
+
+  subtype word is resolve_word uword;
+
+  -- not in book
+  type ubyte is array (0 to 7) of X01Z;
+  -- end not in book
+
+end package words;
+
+--------------------------------------------------
+
+package body words is
+
+  type table is array (X01Z, X01Z) of X01Z;
+
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_word ( contribution : uword_vector ) return uword is
+    variable result : uword := (others => 'Z');
+  begin
+    for index in contribution'range loop
+      for element in uword'range loop
+        result(element) :=
+          resolution_table( result(element), contribution(index)(element) );
+      end loop;
+    end loop;
+    return result;
+  end function resolve_word;
+
+end package body words;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_06.vhd
new file mode 100644
index 0000000..ab8b380
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_06.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.words.all;
+
+entity cpu is
+  port ( address : out uword;  data : inout uword;  -- . . . );
+  -- not in book
+  other_port : in X01Z := 'Z' );
+  -- end not in book
+end entity cpu;
+
+
+-- not in book
+
+architecture behavioral of cpu is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+use work.words.all;
+
+entity memory is
+  port ( address : in uword;  data : inout uword; -- . . . );
+  -- not in book
+  other_port : in X01Z := 'Z' );
+  -- end not in book
+end entity memory;
+
+
+-- not in book
+
+architecture behavioral of memory is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+
+-- not in book
+
+use work.words.all;
+
+entity ROM is
+  port ( a : in uword;  d : out ubyte;  other_port : in X01Z := 'Z' );
+end entity ROM;
+
+
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+
+architecture top_level of computer_system is
+
+  use work.words.all;
+
+  signal address : uword;
+  signal data : word;
+  -- . . .
+
+begin
+
+  the_cpu : entity work.cpu(behavioral)
+    port map ( address, data, -- . . . );
+               -- not in book
+               open );
+  -- end not in book
+
+  the_memory : entity work.memory(behavioral)
+    port map ( address, data, -- . . . );
+               -- not in book
+               open );
+  -- end not in book
+
+  -- . . .
+
+  -- code from book (in text)
+
+--   boot_rom : entity work.ROM(behavioral)
+--     port map ( a => address, d => data(24 to 31), -- . . . );  -- illegal
+--     -- not in book
+--                other_port => open );
+--     -- end not in book
+
+  -- end code from book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_07.vhd
new file mode 100644
index 0000000..6740056
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_07.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_07.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.MVL4.all;
+
+entity ROM is
+  port ( a : in MVL4_ulogic_vector(15 downto 0);
+         d : inout MVL4_logic_vector(7 downto 0);
+         rd : in MVL4_ulogic );
+end entity ROM;
+
+-- not in book
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+use work.MVL4.all;
+
+entity SIMM is
+  port ( a : in MVL4_ulogic_vector(9 downto 0);
+         d : inout MVL4_logic_vector(31 downto 0);
+         ras, cas, we, cs : in MVL4_ulogic );
+end entity SIMM;
+
+-- not in book
+architecture behavioral of SIMM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+-- not in book
+
+use work.MVL4.all;
+
+entity memory_subsystem is
+end entity memory_subsystem;
+
+-- end not in book
+
+architecture detailed of memory_subsystem is
+
+  signal internal_data : MVL4_logic_vector(31 downto 0);
+  -- . . .
+
+  -- not in book
+  signal internal_addr : MVL4_ulogic_vector(31 downto 0);
+  signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
+  signal ROM_select : MVL4_ulogic;
+  -- end not in book
+
+begin
+
+  boot_ROM : entity work.ROM(behavioral)
+    port map ( a => internal_addr(15 downto 0),
+               d => internal_data(7 downto 0),
+               rd => ROM_select );
+
+  main_mem : entity work.SIMM(behavioral)
+    port map ( a => main_mem_addr, d => internal_data, -- . . . );
+               -- not in book
+               ras => '0', cas => '0', we => '0', cs => '0' );
+  -- end not in book
+
+  -- . . .
+
+end architecture detailed;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_08.vhd
new file mode 100644
index 0000000..9f417d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_08.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package fg_11_08 is
+
+  type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+  function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+end package fg_11_08;
+
+
+package body fg_11_08 is
+
+  -- code from book
+
+  type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
+  constant resolution_table : stdlogic_table :=
+    -- ---------------------------------------------
+    --  'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
+    -- ---------------------------------------------
+    ( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ),  --  'U'
+      ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),  --  'X'
+      ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ),  --  '0'
+      ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ),  --  '1'
+      ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ),  --  'Z'
+      ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ),  --  'W'
+      ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ),  --  'L'
+      ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ),  --  'H'
+      ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )   --  '-'
+      );
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic is
+    variable result : std_ulogic := 'Z';  -- weakest state default
+  begin
+    if s'length = 1 then
+      return s(s'low);
+    else
+      for i in s'range loop
+        result := resolution_table(result, s(i));
+      end loop;
+    end if;
+    return result;
+  end function resolved;
+
+  -- end code from book
+
+end package body fg_11_08;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.vhd
new file mode 100644
index 0000000..d06a9a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bus_module is
+                 port ( synch : inout std_ulogic;  -- . . . );
+                        -- not in book
+                        other_port : in std_ulogic := 'U' );
+                 -- end not in book
+               end entity bus_module;
+
+--------------------------------------------------
+
+-- not in book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity bus_based_system is
+               end entity bus_based_system;
+
+-- end not in book
+
+
+               architecture top_level of bus_based_system is
+
+                 signal synch_control : std_logic;
+                 -- . . .
+
+               begin
+
+                 synch_control_pull_up : synch_control <= 'H';
+
+                 bus_module_1 : entity work.bus_module(behavioral)
+                   port map ( synch => synch_control, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 bus_module_2 : entity work.bus_module(behavioral)
+                   port map ( synch => synch_control, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 -- . . .
+
+               end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_10.vhd
new file mode 100644
index 0000000..822cfdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_10.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of bus_module is
+begin
+
+  behavior : process is
+                       -- . . .
+                       -- not in book
+                       constant Tdelay_synch : delay_length := 10 ns;
+                     constant wait_delay : delay_length := 100 ns;
+                     -- end not in book
+  begin
+    synch <= '0'  after Tdelay_synch;
+    -- . . .
+    -- not in book
+    wait for wait_delay;
+    -- end not in book
+    -- ready to start operation
+    synch <= 'Z' after Tdelay_synch;
+    wait until synch = 'H';
+    -- . . .    -- proceed with operation
+    -- . . .
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd
new file mode 100644
index 0000000..e2330c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package fg_11_12 is
+
+                 procedure init_synchronize ( signal synch : out std_logic );
+
+                 procedure begin_synchronize ( signal synch : inout std_logic;
+                                               Tdelay : in delay_length := 0 fs );
+
+                 procedure end_synchronize ( signal synch : inout std_logic;
+                                             Tdelay : in delay_length := 0 fs );
+
+               end package fg_11_12;
+
+
+
+               package body fg_11_12 is
+
+                 -- code from book
+
+                 procedure init_synchronize ( signal synch : out std_logic ) is
+                 begin
+                   synch <= '0';
+                 end procedure init_synchronize;
+
+                 procedure begin_synchronize ( signal synch : inout std_logic;
+                                               Tdelay : in delay_length := 0 fs ) is
+                 begin
+                   synch <= 'Z' after Tdelay;
+                   wait until synch = 'H';
+                 end procedure begin_synchronize;
+
+                 procedure end_synchronize ( signal synch : inout std_logic;
+                                             Tdelay : in delay_length := 0 fs ) is
+                 begin
+                   synch <= '0' after Tdelay;
+                   wait until synch = '0';
+                 end procedure end_synchronize;
+
+                 -- end code from book
+
+               end package body fg_11_12;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_13.vhd
new file mode 100644
index 0000000..c3943b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_13.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_13.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_11_13 is
+               end entity fg_11_13;
+
+
+
+               architecture test of fg_11_13 is
+
+                 use work.fg_11_12.all;
+
+                 signal barrier : std_logic;
+
+               begin
+
+                 pullup : barrier <= 'H';
+
+                 -- code from book
+
+                 synchronized_module : process is
+                                                 -- . . .
+                 begin
+                   init_synchronize(barrier);
+                   -- . . .
+                   loop
+                     -- . . .
+                     begin_synchronize(barrier);
+                     -- . . .    -- perform operation, synchronized with other processes
+                     end_synchronize(barrier);
+                     -- . . .
+                   end loop;
+                 end process synchronized_module;
+
+                 -- end code from book
+
+                 another_synchronized_module : process is
+                 begin
+                   init_synchronize(barrier);
+                   loop
+                     wait for 10 ns;
+                     begin_synchronize(barrier);
+                     -- . . .    -- perform operation, synchronized with other processes
+                     end_synchronize(barrier);
+                   end loop;
+                 end process another_synchronized_module;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_01.vhd
new file mode 100644
index 0000000..32dbe5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_01.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_ch_12_01.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity and2 is
+  generic ( Tpd : time );
+  port ( a, b : in bit;  y : out bit );
+end entity and2;
+
+architecture simple of and2 is
+begin
+
+  and2_function :
+    y <= a and b after Tpd;
+
+end architecture simple;
+
+-- end code from book
+
+entity ch_12_01 is
+
+end entity ch_12_01;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of ch_12_01 is
+
+  signal a1, b1, sig1, sig2, sig_out : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  -- code from book
+
+  gate1 : entity work.and2(simple)
+    generic map ( Tpd => 2 ns )
+    port map ( a => sig1,  b => sig2,  y => sig_out );
+
+  gate2 : entity work.and2(simple)
+    generic map ( Tpd => 3 ns )
+    port map ( a => a1,  b => b1,  y => sig1 );
+
+  -- end code from book
+
+  stimulus : all_possible_values ( bv => test_vector,
+				   delay_between_values => 10 ns );
+
+  (sig2, a1, b1) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd
new file mode 100644
index 0000000..17a3a97
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_ch_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity reg is
+  port ( d : in bit_vector;  q : out bit_vector;  -- . . . );
+  -- not in book
+  other_port : in bit := '0' );
+  -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+  q <= d;
+end architecture test;
+
+
+
+entity ch_12_02 is
+
+end entity ch_12_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_12_02 is
+
+  -- code from book
+
+  signal small_data : bit_vector(0 to 7);
+  signal large_data : bit_vector(0 to 15);
+  -- . . .
+
+  -- end code from book
+
+
+begin
+
+  -- code from book
+
+  problem_reg : entity work.reg
+    port map ( d => small_data,  q => large_data, -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_03.vhd
new file mode 100644
index 0000000..e41f815
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_03.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_ch_12_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity reg is
+  generic ( width : positive );
+  port ( d : in bit_vector(0 to width - 1);
+         q : out bit_vector(0 to width - 1);
+         -- . . . );
+         -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+  q <= d;
+end architecture test;
+
+
+
+entity ch_12_03 is
+
+end entity ch_12_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_12_03 is
+
+  constant bus_size : positive := 16;
+
+  -- code from book
+
+  signal in_data, out_data : bit_vector(0 to bus_size - 1);
+  -- . . .
+
+  -- end code from book
+
+
+begin
+
+  -- code from book
+
+  ok_reg : entity work.reg
+    generic map ( width => bus_size )
+    port map ( d => in_data,  q => out_data, -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_01.vhd
new file mode 100644
index 0000000..11a1a65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_01.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_fg_12_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity control_unit is
+
+  generic ( Tpd_clk_out, Tpw_clk : delay_length;
+            debug : boolean := false );
+
+  port ( clk : in bit;
+         ready : in bit;
+         control1, control2 : out bit );
+
+end entity control_unit;
+
+-- end code from book
+
+
+
+architecture test of control_unit is
+begin
+end architecture test;
+
+
+
+
+entity fg_12_01 is
+end entity fg_12_01;
+
+
+
+architecture test of fg_12_01 is
+
+  signal clk, ready : bit;
+
+begin
+
+  dut1 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( 200 ps, 1500 ps, false )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+  dut2 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+  dut3 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( 200 ps, 1500 ps, debug => open )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd
new file mode 100644
index 0000000..a57b894
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity D_flipflop is
+  generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
+  port ( clk, d : in bit;  q : out bit );
+end entity D_flipflop;
+
+--------------------------------------------------
+
+architecture basic of D_flipflop is
+begin
+
+  behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
+
+  check_setup : process is
+  begin
+    wait until clk = '1';
+    assert d'last_event >= Tsu_d_clk
+      report "setup violation";
+  end process check_setup;
+
+  check_hold : process is
+  begin
+    wait until clk'delayed(Th_d_clk) = '1';
+    assert d'delayed'last_event >= Th_d_clk
+      report "hold violation";
+  end process check_hold;
+
+end architecture basic;
+
+-- end code from book
+
+
+
+entity fg_12_02 is
+end entity fg_12_02;
+
+
+
+architecture test of fg_12_02 is
+
+  signal system_clock, request, request_pending : bit := '0';
+
+begin
+
+  -- code from book (in text)
+
+  request_flipflop : entity work.D_flipflop(basic)
+    generic map ( Tpd_clk_q => 4 ns,
+                  Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
+    port map ( clk => system_clock,
+               d => request, q => request_pending );
+
+  -- end code from book
+
+  clock_gen : system_clock <= '1' after 10 ns,
+                              '0' after 20 ns when system_clock = '0';
+
+  stimulus :  request <= '1' after  25 ns, '0' after  35 ns,
+                         '1' after  67 ns, '0' after  71 ns,
+                         '1' after 108 ns, '0' after 110.5 ns;
+  
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_03.vhd
new file mode 100644
index 0000000..cdbb699
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_03.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_fg_12_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity reg is
+  generic ( width : positive );
+  port ( d :  in  bit_vector(0 to width - 1);
+         q :  out  bit_vector(0 to width - 1);
+         clk, reset : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+architecture behavioral of reg is
+begin
+
+  behavior : process (clk, reset) is
+                                    constant zero : bit_vector(0 to width - 1) := (others => '0');
+  begin
+    if reset = '1' then
+      q <= zero;
+    elsif clk'event and clk = '1' then
+      q <= d;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
+
+-- end code from book
+
+
+
+entity fg_12_03 is
+end entity fg_12_03;
+
+
+architecture test of fg_12_03 is
+
+  -- code from book
+
+  subtype state_vector is bit_vector(1 to 5);
+
+  -- end code from book
+
+  signal clk, reset : bit := '0';
+  signal word_in, word_out : bit_vector(0 to 31);
+  signal state_in, state_out : state_vector;
+
+begin
+
+  -- code from book
+
+  word_reg : entity work.reg(behavioral)
+    generic map ( width => 32 )
+    port map ( -- . . . );
+      -- not in book
+      d => word_in, q => word_out, clk => clk, reset => reset );
+  -- end not in book
+
+  state_reg : entity work.reg(behavioral)
+    generic map ( width => state_vector'length )
+    port map ( -- . . . );
+      -- not in book
+      d => state_in, q => state_out, clk => clk, reset => reset );
+
+  -- end code from book
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  reset_gen : reset <= '1' after 80 ns, '0' after 105 ns;
+
+  stimulus_word : word_in <= X"11111111" after 25 ns,
+                             X"22222222" after 65 ns,
+		             X"33333333" after 85 ns,
+		             X"44444444" after 125 ns;
+
+  stimulus_state : state_in <= "00001" after 25 ns,
+                               "00010" after 65 ns,
+		               "00011" after 85 ns,
+		               "00100" after 125 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_ch_13_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_ch_13_01.vhd
new file mode 100644
index 0000000..fae8a96
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_ch_13_01.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_ch_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_13_01 is
+end entity ch_13_01;
+
+
+architecture test of ch_13_01 is
+
+  -- code from book
+
+  component nand3 is
+                    port ( a, b, c : in bit := '1';  y : out bit );
+  end component nand3;
+
+  -- end code from book
+
+  signal s1, s2, s3 : bit;
+
+begin
+
+  -- code from book
+
+  gate1 : component nand3
+    port map ( a => s1, b => s2, c => open, y => s3 );
+
+  -- end code from book
+
+end architecture test;
+
+
+
+-- code from book
+
+entity nand2 is
+  port ( a, b : in bit := '1';  y : out bit );
+end entity nand2;
+
+-- end code from book
+
+
+configuration ch_13_01_test of ch_13_01 is
+
+  for test
+
+    -- code from book
+
+    for gate1 : nand3
+      use entity work.nand2(basic);
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration ch_13_01_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_01.vhd
new file mode 100644
index 0000000..eb0d1fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_01.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity edge_triggered_Dff is
+  generic ( Tprop, Tsetup, Thold : delay_length );
+  port ( clk : in bit;  clr : in bit; d : in bit;
+  q : out bit );
+end entity edge_triggered_Dff;
+
+
+architecture basic of edge_triggered_Dff is
+begin
+
+  state_change : process (clk, clr) is
+  begin
+    if clr = '1' then
+      q <= '0' after Tprop;
+    elsif clk'event and clk = '1' then
+      q <= d after Tprop;
+    end if;
+  end process state_change;
+
+end architecture basic;
+
+
+architecture hi_fanout of edge_triggered_Dff is
+begin
+
+  state_change : process (clk, clr) is
+  begin
+    if clr = '1' then
+      q <= '0' after Tprop;
+    elsif clk'event and clk = '1' then
+      q <= d after Tprop;
+    end if;
+  end process state_change;
+
+end architecture hi_fanout;
+
+
+-- code from book
+
+entity reg4 is
+  port ( clk, clr : in bit;  d : in bit_vector(0 to 3);
+  q : out bit_vector(0 to 3) );
+end entity reg4;
+
+--------------------------------------------------
+
+architecture struct of reg4 is
+
+  component flipflop is
+                       generic ( Tprop, Tsetup, Thold : delay_length );
+                     port ( clk : in bit;  clr : in bit;  d : in bit;
+                     q : out bit );
+  end component flipflop;
+
+begin
+
+  bit0 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(0), q => q(0) );
+
+  bit1 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(1), q => q(1) );
+
+  bit2 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(2), q => q(2) );
+
+  bit3 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(3), q => q(3) );
+
+end architecture struct;
+
+-- end code from book
+
+
+
+configuration fg_13_01 of reg4 is
+
+  for struct
+
+    -- code from book (in text)
+
+    for bit0, bit1 : flipflop
+      use entity work.edge_triggered_Dff(basic);
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration fg_13_01;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_02.vhd
new file mode 100644
index 0000000..a4ca0eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_02.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package serial_interface_defs is
+
+                 subtype reg_address_vector is std_logic_vector(1 downto 0);
+
+                 constant status_reg_address : reg_address_vector := B"00";
+                 constant control_reg_address : reg_address_vector := B"01";
+                 constant rx_data_register : reg_address_vector := B"10";
+                 constant tx_data_register : reg_address_vector := B"11";
+
+                 subtype data_vector is std_logic_vector(7 downto 0);
+
+                 -- . . .    -- other useful declarations
+
+                 component serial_interface is
+                                              port ( clock_phi1, clock_phi2 : in std_logic;
+                                                     serial_select : in std_logic;
+                                                     reg_address : in reg_address_vector;
+                                                     data : inout data_vector;
+                                                     interrupt_request : out std_logic;
+                                                     rx_serial_data : in std_logic;
+                                                     tx_serial_data : out std_logic );
+                 end component serial_interface;
+
+               end package serial_interface_defs;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_03.vhd
new file mode 100644
index 0000000..1ad9033
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_03.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.serial_interface_defs.all;
+
+               entity serial_interface is
+                 port ( clock_phi1, clock_phi2 : in std_logic;
+                        serial_select : in std_logic;
+                        reg_address : in reg_address_vector;
+                        data : inout data_vector;
+                        interrupt_request : out std_logic;
+                        rx_serial_data : in std_logic;
+                        tx_serial_data : out std_logic );
+               end entity serial_interface;
+
+
+-- not in book
+
+               architecture test of serial_interface is
+               begin
+               end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd
new file mode 100644
index 0000000..e702c81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.serial_interface_defs.all;
+
+entity microcontroller is
+end entity microcontroller;
+
+-- end not in book
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture structure of microcontroller is
+
+  use work.serial_interface_defs.serial_interface;
+
+  -- . . .    -- declarations of other components, signals, etc
+
+  -- not in book
+  signal buffered_phi1, buffered_phi2, serial_a_select : std_logic;
+  signal internal_addr : std_logic_vector(1 downto 0);
+  signal internal_data_bus : data_vector;
+  signal serial_a_int_req, rx_data_a, tx_data_a : std_logic;
+  -- end not in book
+
+begin
+
+  serial_a : component serial_interface
+    port map ( clock_phi1 => buffered_phi1,
+               clock_phi2 => buffered_phi2,
+               serial_select => serial_a_select,
+               reg_address => internal_addr(1 downto 0),
+               data => internal_data_bus,
+               interrupt_request => serial_a_int_req,
+               rx_serial_data => rx_data_a,
+               tx_serial_data => tx_data_a );
+
+  -- . . .    -- other component instances
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_05.vhd
new file mode 100644
index 0000000..f09e364
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_05.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_05.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library star_lib;
+--use star_lib.edge_triggered_Dff;
+use star_lib.all;
+
+configuration reg4_gate_level of reg4 is
+
+  for struct  -- architecture of reg4
+
+    for bit0 : flipflop
+      use entity star_lib.edge_triggered_Dff(hi_fanout);
+    end for;
+
+    for others : flipflop
+      use entity star_lib.edge_triggered_Dff(basic);
+    end for;
+
+  end for;  -- end of architecture struct
+
+end configuration reg4_gate_level;
+
+-- end code from book
+
+
+entity fg_13_05 is
+end entity fg_13_05;
+
+
+architecture test of fg_13_05 is
+
+  component reg4 is
+                   port ( clk, clr : in bit;  d : in bit_vector(0 to 3);
+                   q : out bit_vector(0 to 3) );
+  end component reg4;
+
+  signal clk, clr : bit;
+  signal d, q : bit_vector(0 to 3);
+
+begin
+
+  flag_reg : component reg4
+    port map ( clk => clk, clr => clr, d => d, q => q );
+
+end architecture test;
+
+
+configuration fg_13_05_test of fg_13_05 is
+
+  for test
+
+    -- code from book (in text)
+
+    for flag_reg : reg4
+      use configuration work.reg4_gate_level;
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration fg_13_05_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.vhd
new file mode 100644
index 0000000..db630d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.vhd
@@ -0,0 +1,135 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package counter_types is
+
+  -- code from book (in text)
+
+  subtype digit is bit_vector(3 downto 0);
+
+  -- end code from book
+
+end package counter_types;
+
+
+
+use work.counter_types.digit;
+
+entity add_1 is
+  port ( d : in digit;  y : out digit );
+end entity add_1;
+
+
+architecture boolean_eqn of add_1 is
+begin
+
+  y(0) <= not d(0) after 4 ns;
+
+  y(1) <= (not d(1) and d(0))
+          or (d(1) and not d(0)) after 4 ns;
+
+  y(2) <= (not d(2) and d(1) and d(0))
+	  or (d(2) and not (d(1) and d(0))) after 4 ns;
+
+  y(3) <= (not d(3) and d(2) and d(1) and d(0))
+	  or (d(3) and not (d(2) and d(1) and d(0))) after 4 ns;
+
+end architecture boolean_eqn;
+
+
+use work.counter_types.digit;
+
+entity buf4 is
+  port ( a : in digit;  y : out digit );
+end entity buf4;
+
+
+architecture basic of buf4 is
+begin
+
+  y(0) <= a(0) after 2 ns;
+  y(1) <= a(1) after 2 ns;
+  y(2) <= a(2) after 2 ns;
+  y(3) <= a(3) after 2 ns;
+
+end architecture basic;
+
+
+
+
+-- code from book
+
+use work.counter_types.digit;
+
+entity counter is
+  port ( clk, clr : in bit;
+         q0, q1 : out digit );
+end entity counter;
+
+--------------------------------------------------
+
+architecture registered of counter is
+
+  component digit_register is
+                             port ( clk, clr : in bit;
+                                    d : in digit;
+                                    q : out digit );
+  end component digit_register;
+
+  signal current_val0, current_val1, next_val0, next_val1 : digit;
+
+begin
+
+  val0_reg : component digit_register
+    port map ( clk => clk, clr => clr, d => next_val0,
+               q => current_val0 );
+
+  val1_reg : component digit_register
+    port map ( clk => clk, clr => clr, d => next_val1,
+               q => current_val1 );
+
+  -- other component instances
+  -- . . .
+
+  -- not in book
+
+  incr0 : entity work.add_1(boolean_eqn)
+    port map ( d => current_val0, y => next_val0 );
+
+  incr1 : entity work.add_1(boolean_eqn)
+    port map ( d => current_val1, y => next_val1 );
+
+  buf0 : entity work.buf4(basic)
+    port map ( a => current_val0, y => q0 );
+
+  buf1 : entity work.buf4(basic)
+    port map ( a => current_val1, y => q1 );
+
+  -- end not in book
+
+end architecture registered;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd
new file mode 100644
index 0000000..d8bb53a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration counter_down_to_gate_level of counter is
+
+  for registered
+
+    for all : digit_register
+      use configuration work.reg4_gate_level;
+    end for;
+
+    -- . . .    -- bindings for other component instances
+
+  end for;  -- end of architecture registered
+
+end configuration counter_down_to_gate_level;
+
+
+
+-- not in book
+
+entity fg_13_07 is
+end entity fg_13_07;
+
+
+use work.counter_types.all;
+
+architecture test of fg_13_07 is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : configuration work.counter_down_to_gate_level
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd
new file mode 100644
index 0000000..92068dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+library star_lib;
+--use star_lib.edge_triggered_dff;
+use star_lib.all;
+
+configuration full of counter is
+
+  for registered  -- architecture of counter
+
+    for all : digit_register
+      use entity work.reg4(struct);
+
+      for struct  -- architecture of reg4
+
+        for bit0 : flipflop
+          use entity edge_triggered_Dff(hi_fanout);
+        end for;
+
+        for others : flipflop
+          use entity edge_triggered_Dff(basic);
+        end for;
+
+      end for;  -- end of architecture struct
+
+    end for;
+
+    -- . . .    -- bindings for other component instances
+
+  end for;  -- end of architecture registered
+
+end configuration full;
+
+
+
+-- not in book
+
+entity fg_13_08 is
+end entity fg_13_08;
+
+
+use work.counter_types.all;
+
+architecture test of fg_13_08 is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : configuration work.full
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_09.vhd
new file mode 100644
index 0000000..10dc09b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_09.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity alarm_clock is
+end entity alarm_clock;
+
+-- end not in book
+
+
+architecture top_level of alarm_clock is
+
+  --use work.counter_types.digit;
+  use work.counter_types.all;
+
+  signal reset_to_midnight, seconds_clk : bit;
+  signal seconds_units, seconds_tens : digit;
+  -- . . .
+
+begin
+
+  seconds : configuration work.counter_down_to_gate_level
+    port map ( clk => seconds_clk, clr => reset_to_midnight,
+               q0 => seconds_units, q1 => seconds_tens );
+
+  -- . . .
+
+  -- not in book
+
+  clk_gen : seconds_clk <= not seconds_clk after 20 ns;
+
+  clr_gen : reset_to_midnight <= '1' after 95 ns,
+		                 '0' after 135 ns;
+
+  -- end not in book;
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_10.vhd
new file mode 100644
index 0000000..9c7314e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_10.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity reg is
+                 generic ( t_setup, t_hold, t_pd : delay_length;
+                           width : positive );
+                 port ( clock : in std_logic;
+                        data_in : in std_logic_vector(0 to width - 1);
+                        data_out : out std_logic_vector(0 to width - 1) );
+               end entity reg;
+
+
+
+-- not in book
+
+               architecture gate_level of reg is
+               begin
+               end architecture gate_level;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_11.vhd
new file mode 100644
index 0000000..bc4a155
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_11.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_11.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity controller is
+               end entity controller;
+
+-- end not in book
+
+
+               architecture structural of controller is
+
+                 component reg is
+                                 generic ( width : positive );
+                               port ( clock : in std_logic;
+                                      data_in : in std_logic_vector(0 to width - 1);
+                                      data_out : out std_logic_vector(0 to width - 1) );
+                 end component reg;
+
+                 -- . . .
+
+                 -- not in book
+                 subtype state_type is std_logic_vector(0 to 5);
+                 signal clock_phase1 : std_logic;
+                 signal next_state, current_state : state_type;
+                 -- end not in book
+
+               begin
+
+                 state_reg : component reg
+                   generic map ( width => state_type'length )
+                   port map ( clock => clock_phase1,
+                              data_in => next_state,
+                              data_out => current_state );
+
+                 -- . . .
+
+               end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_12.vhd
new file mode 100644
index 0000000..02ae148
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_12.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration controller_with_timing of controller is
+
+  for structural
+
+    for state_reg : reg
+      use entity work.reg(gate_level)
+        generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
+                      width => width );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration controller_with_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_13.vhd
new file mode 100644
index 0000000..0868c64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_13.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_13.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+
+library stimulus;  
+use stimulus.stimulus_generators.all;
+
+-- end not in book
+
+architecture structure of computer_system is
+
+  component decoder_2_to_4 is
+                             generic ( prop_delay : delay_length );
+                           port ( in0, in1 : in bit;
+                                  out0, out1, out2, out3 : out bit );
+  end component decoder_2_to_4;
+
+  -- . . .
+
+  -- not in book
+
+  signal addr : bit_vector(5 downto 4);
+  signal interface_a_select, interface_b_select,
+    interface_c_select, interface_d_select : bit;
+  -- end not in book
+
+begin
+
+  interface_decoder : component decoder_2_to_4
+    generic map ( prop_delay => 4 ns )
+    port map ( in0 => addr(4), in1 => addr(5),
+               out0 => interface_a_select, out1 => interface_b_select,
+               out2 => interface_c_select, out3 => interface_d_select );
+
+  -- . . .
+
+  -- not in book
+
+  all_possible_values(addr, 10 ns);
+
+  -- end not in book
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_14.vhd
new file mode 100644
index 0000000..b03f1d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_14.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_14.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity decoder_3_to_8 is
+  generic ( Tpd_01, Tpd_10 : delay_length );
+  port ( s0, s1, s2 : in bit;
+         enable : in bit;
+         y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
+end entity decoder_3_to_8;
+
+
+-- not in book
+
+architecture basic of decoder_3_to_8 is
+begin
+
+  process (enable, s2, s1, s0) is
+  begin
+    if enable = '0' then
+      (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
+    else
+      case bit_vector'(s2, s1, s0) is
+        when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
+        when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
+        when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
+        when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
+        when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
+        when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
+        when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
+        when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
+      end case;
+    end if;
+  end process;
+
+end architecture basic;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd
new file mode 100644
index 0000000..a8bed90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration computer_structure of computer_system is
+
+  for structure
+
+    for interface_decoder : decoder_2_to_4
+      use entity work.decoder_3_to_8(basic)
+        generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
+        port map ( s0 => in0, s1 => in1, s2 => '0',
+                   enable => '1',
+                   y0 => out0, y1 => out1, y2 => out2, y3 => out3,
+                   y4 => open, y5 => open, y6 => open, y7 => open );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration computer_structure;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.vhd
new file mode 100644
index 0000000..0617981
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_17.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+entity single_board_computer is
+end entity single_board_computer;
+-- end not in book
+
+
+architecture structural of single_board_computer is
+
+  -- . . .    -- type and signal declarations
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  signal sys_clk : bit;
+  signal cpu_a_d, latched_addr : word;
+
+  -- end not in book
+
+  component processor is
+                        port ( clk : in bit;  a_d : inout word; -- . . . );
+                        -- not in book
+                        other_port : in bit := '0' );
+                      -- end not in book
+  end component processor;
+
+  component memory is
+                     port ( addr : in bit_vector(25 downto 0); -- . . . );
+                            -- not in book
+                            other_port : in bit := '0' );
+                   -- end not in book
+  end component memory;
+
+  component serial_interface is
+                               port ( clk : in bit;  address : in bit_vector(3 downto 0); -- . . . );
+                               -- not in book
+                               other_port : in bit := '0' );
+                             -- end not in book
+  end component serial_interface;
+
+begin
+
+  cpu : component processor
+    port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  main_memory : component memory
+    port map ( addr => latched_addr(25 downto 0), -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  serial_interface_a : component serial_interface
+    port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd
new file mode 100644
index 0000000..e7ba617
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_18.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity XYZ3000_cpu is
+  port ( clock : in bit;  addr_data : inout bit_vector(31 downto 0);
+  other_port : in bit := '0' );
+end entity XYZ3000_cpu;
+
+architecture full_function of XYZ3000_cpu is
+begin
+end architecture full_function;
+
+
+entity memory_array is
+  port ( addr : in bit_vector(25 downto 0);  other_port : in bit := '0' );
+end entity memory_array;
+
+
+architecture behavioral of memory_array is
+begin
+end architecture behavioral;
+
+-- code from book
+
+library chips;
+
+configuration intermediate of single_board_computer is
+
+  for structural
+
+    for cpu : processor
+      use entity chips.XYZ3000_cpu(full_function)
+        port map ( clock => clk, addr_data => a_d, -- . . . );
+                   -- not in book
+                   other_port => open );
+      -- end not in book
+    end for;
+
+    for main_memory : memory
+      use entity work.memory_array(behavioral);
+    end for;
+
+    for all : serial_interface
+      use open;
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration intermediate;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd
new file mode 100644
index 0000000..bcd3ee4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_19.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book (in text)
+
+entity nand3 is
+  port ( a, b, c : in bit;  y : out bit );
+end entity nand3;
+
+-- end code from book
+
+architecture behavioral of nand3 is
+begin
+  y <= not (a and b and c);
+end architecture behavioral;
+
+
+entity logic_block is
+end entity logic_block;
+
+
+-- code from book
+
+library gate_lib;
+
+architecture ideal of logic_block is
+
+  component nand2 is
+                    port ( in1, in2 : in bit;  result : out bit );
+  end component nand2;
+
+  for all : nand2
+    use entity gate_lib.nand3(behavioral)
+    port map ( a => in1, b => in2, c => '1', y => result );
+
+  -- . . .    -- other declarations
+
+  -- not in book
+  signal s1, s2, s3 : bit := '0';
+
+begin
+
+  gate1 : component nand2
+    port map ( in1 => s1, in2 => s2, result => s3 );
+
+  -- . . .    -- other concurrent statements
+
+  -- not in book
+
+  s1 <= '1' after 20 ns;
+
+  s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+
+  -- end not in book
+
+end architecture ideal;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd
new file mode 100644
index 0000000..18e9e4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_20.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity control_section is
+               end entity control_section;
+
+-- end not in book
+
+
+               architecture structural of control_section is
+
+                 component reg is
+                                 generic ( width : positive );
+                               port ( clk : in std_logic;
+                                      d : in std_logic_vector(0 to width - 1);
+                                      q : out std_logic_vector(0 to width - 1) );
+                 end component reg;
+
+                 for flag_reg : reg
+                   use entity work.reg(gate_level)
+                   -- workaround for MTI bug mt023
+                   -- port map ( clock => clk, data_in => d, data_out => q );
+                   port map ( clock => clk, data_in => d, data_out => q, reset_n => '1' );
+                 -- end workaround
+
+                 -- . . .
+
+                 -- not in book
+                 signal clock_phase1, zero_result, neg_result, overflow_result,
+                   zero_flag, neg_flag, overflow_flag : std_logic;
+                 -- end not in book
+
+               begin
+
+                 flag_reg : component reg
+                   generic map ( width => 3 )
+                   port map ( clk => clock_phase1,
+                              d(0) => zero_result, d(1) => neg_result,
+                              d(2) => overflow_result,
+                              q(0) => zero_flag, q(1) => neg_flag,
+                              q(2) => overflow_flag );
+
+                 -- . . .
+
+                 -- not in book
+
+                 stimulus : process is
+                 begin
+                   clock_phase1 <= '0';
+                   zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+                 -- end not in book
+
+               end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd
new file mode 100644
index 0000000..0042431
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity reg is
+                 generic ( t_setup, t_hold, t_pd : delay_length;
+                           width : positive );
+                 port ( clock : in std_logic;
+                        reset_n : in std_logic;
+                        data_in : in std_logic_vector(0 to width - 1);
+                        data_out : out std_logic_vector(0 to width - 1) );
+               end entity reg;
+
+
+
+-- not in book
+
+               architecture gate_level of reg is
+
+               begin
+
+                 store : process (clock, reset_n) is
+                 begin
+                   if reset_n = '0' or reset_n = 'L' then
+                     data_out <= (others => '0') after t_pd;
+                   elsif rising_edge(clock) then
+                     data_out <= data_in after t_pd;
+                   end if;
+                 end process store;
+
+               end architecture gate_level;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_22.vhd
new file mode 100644
index 0000000..632a10a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_22.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_22.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration controller_with_timing of control_section is
+
+  for structural
+
+    for flag_reg : reg
+      generic map ( t_setup => 200 ps, t_hold => 150 ps,
+                    t_pd => 150 ps, width => width )
+        -- workaround for MTI bug mt023
+        -- port map ( reset_n => '1');
+        ;
+      -- end workaround
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration controller_with_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd
new file mode 100644
index 0000000..a35bddb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd
@@ -0,0 +1,121 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity nor_gate is
+                 generic ( width : positive;
+                           Tpd01, Tpd10 : delay_length );
+                 port ( input : in std_logic_vector(0 to width - 1);
+                        output : out std_logic );
+               end entity nor_gate;
+
+
+               architecture primitive of nor_gate is
+
+                 function max ( a, b : delay_length ) return delay_length is
+                 begin
+                   if a > b then
+                     return a;
+                   else
+                     return b;
+                   end if;
+                 end function max;
+
+               begin
+
+                 reducer : process (input) is
+                                             variable result : std_logic;
+                 begin
+                   result := '0';
+                   for index in input'range loop
+                     result := result or input(index);
+                   end loop;
+                   if not result = '1' then
+                     output <= not result after Tpd01;
+                   elsif not result = '0' then
+                     output <= not result after Tpd10;
+                   else
+                     output <= not result after max(Tpd01, Tpd10);
+                   end if;
+                 end process reducer;
+
+               end architecture primitive;
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+               library cell_lib;
+
+               entity interlock_control is
+               end entity interlock_control;
+
+
+-- code from book
+
+               architecture detailed_timing of interlock_control is
+
+                 component nor_gate is
+                                      generic ( input_width : positive );
+                                    port ( input : in std_logic_vector(0 to input_width - 1);
+                                           output : out std_logic );
+                 end component nor_gate;
+
+                 for ex_interlock_gate : nor_gate
+                   use entity cell_lib.nor_gate(primitive)
+                   generic map ( width => input_width,
+                                 Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates
+
+                 -- . . .
+
+                 -- not in book
+                 signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
+                 -- end not in book
+
+               begin
+
+                 ex_interlock_gate : component nor_gate
+                   generic map ( input_width => 2 )
+                   port map ( input(0) => reg_access_hazard,
+                              input(1) => load_hazard,
+                              output => stall_ex_n);
+
+                 -- . . .
+
+                 -- not in book
+
+                 reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
+
+                 load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
+                                '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
+                                '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
+                                '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
+
+                 -- end not in book
+
+               end architecture detailed_timing;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_24.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_24.vhd
new file mode 100644
index 0000000..cca5943
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_24.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_24.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration interlock_control_with_estimates of interlock_control is
+
+  for detailed_timing
+
+  end for;
+
+  -- . . .
+
+end configuration interlock_control_with_estimates;
+
+--------------------------------------------------
+
+configuration interlock_control_with_actual of interlock_control is
+
+  for detailed_timing
+
+    for ex_interlock_gate : nor_gate
+      generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration interlock_control_with_actual;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd
new file mode 100644
index 0000000..8e24ede
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity nand3 is
+  generic ( Tpd : delay_length );
+  port ( a, b, c : in bit;  y : out bit );
+end entity nand3;
+
+architecture basic of nand3 is
+begin
+  y <= not (a and b and c) after Tpd;
+end architecture basic;
+
+
+library project_lib;
+library stimulus;  
+use stimulus.stimulus_generators.all;
+
+entity misc_logic is
+end entity misc_logic;
+
+-- code from book
+
+architecture gate_level of misc_logic is
+
+  component nand3 is
+                    generic ( Tpd : delay_length );
+                  port ( a, b, c : in bit;  y : out bit );
+  end component nand3;
+
+  for all : nand3
+    use entity project_lib.nand3(basic);
+
+  -- . . .
+
+  -- not in book
+  signal sig1, sig2, sig3, out_sig : bit;
+  signal test_vector : bit_vector(1 to 3);
+  -- end not in book
+
+begin
+
+  gate1 : component nand3
+    generic map ( Tpd => 2 ns )
+    port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
+
+  -- . . .
+
+  -- not in book
+
+  all_possible_values(test_vector, 10 ns);
+
+  (sig1, sig2, sig3) <= test_vector;
+
+  -- end not in book
+
+end architecture gate_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_26.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_26.vhd
new file mode 100644
index 0000000..f7e3c10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_26.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_26.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration misc_logic_reconfigured of misc_logic is
+
+  for gate_level
+
+    for gate1 : nand3
+      generic map ( Tpd => 1.6 ns )
+        port map ( a => c, c => a, b => b, y => y );
+    end for;
+
+  end for;
+
+end configuration misc_logic_reconfigured;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd
new file mode 100644
index 0000000..e6704b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd
@@ -0,0 +1,144 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_ch_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity buf is
+                 port ( a : in std_logic;  y : out std_logic );
+               end buf;
+
+
+               architecture basic of buf is
+               begin
+                 y <= a;
+               end basic;
+
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fanout_tree is
+                 generic ( height : natural );
+                 port ( input : in std_logic;
+                        output : out std_logic_vector (0 to 2**height - 1) );
+               end fanout_tree;
+
+--------------------------------------------------
+
+               architecture recursive of fanout_tree is
+
+                 component buf
+                   port ( a : in std_logic;  y : out std_logic );
+                 end component;
+
+                 component fanout_tree
+                   generic ( height : natural );
+                   port ( input : in std_logic;
+                          output : out std_logic_vector (0 to 2**height - 1) );
+                 end component;
+
+                 signal buffered_input_0, buffered_input_1 : std_logic;
+
+               begin
+
+                 degenerate_tree : if height = 0 generate
+                   output(0) <= input;
+                 end generate degenerate_tree;
+
+                 compound_tree : if height > 0 generate
+
+                   buf_0 : buf
+                     port map ( a => input, y => buffered_input_0 );
+
+                   -- code from book
+
+                   block_0 : block
+                     for subtree_0 : fanout_tree
+                       use entity work.fanout_tree(recursive);
+                   begin
+                     subtree_0 : fanout_tree
+                       generic map ( height => height - 1 )
+                       port map (  input => buffered_input_0,
+                                   output => output(0 to 2**(height - 1) - 1) );
+                   end block block_0;
+
+                   -- end code from book
+
+                   buf_1 : buf
+                     port map ( a => input, y => buffered_input_1 );
+
+                   block_1 : block
+                     for subtree_1 : fanout_tree
+                       use entity work.fanout_tree(recursive);
+                   begin
+                     subtree_1 : fanout_tree
+                       generic map ( height => height - 1 )
+                       port map ( input => buffered_input_1,
+                                  output => output(2**(height - 1) to 2**height - 1) );
+                   end block block_1;
+
+                 end generate compound_tree;
+
+               end recursive;
+
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity ch_14_01 is
+               end ch_14_01;
+
+
+               architecture test of ch_14_01 is
+
+                 component fanout_tree
+                   generic ( height : natural );
+                   port ( input : in std_logic;
+                          output : out std_logic_vector (0 to 2**height - 1) );
+                 end component;
+
+                 for clock_buffer_tree : fanout_tree
+                   use entity work.fanout_tree(recursive);
+
+                 signal unbuffered_clock : std_logic;
+                 signal buffered_clock_array : std_logic_vector(0 to 7);
+
+               begin
+
+                 clock_buffer_tree : fanout_tree
+                   generic map ( height => 3 )
+                   port map ( input => unbuffered_clock,
+                              output => buffered_clock_array );
+
+                 clock_gen : process
+                 begin
+                   unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+               end test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd
new file mode 100644
index 0000000..74fa3e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd
@@ -0,0 +1,171 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity D_flipflop is
+                 port ( clk : in std_logic;  d : in std_logic;
+                 q : out std_logic );
+               end entity D_flipflop;
+
+
+               architecture synthesized of D_flipflop is
+               begin
+                 q <= d when not clk'stable and (To_X01(clk) = '1') and 
+                      (To_X01(clk'last_value) = '0');
+               end architecture synthesized;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity tristate_buffer is
+                 port ( a : in std_logic;
+                        en : in std_logic;
+                        y : out std_logic );
+               end entity tristate_buffer;
+
+
+               architecture synthesized of tristate_buffer is
+               begin
+                 y <= 'X' when is_X(en) else
+                      a  when To_X01(en) = '1' else
+                      'Z';
+               end architecture synthesized;
+
+
+
+-- code from book (in Figure 14-1)
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity register_tristate is
+                 generic ( width : positive );
+                 port ( clock : in std_logic;
+                        out_enable : in std_logic;
+                        data_in : in std_logic_vector(0 to width - 1);
+                        data_out : out std_logic_vector(0 to width - 1) );
+               end entity register_tristate;
+
+--------------------------------------------------
+
+               architecture cell_level of register_tristate is
+
+                 component D_flipflop is
+                                        port ( clk : in std_logic;  d : in std_logic;
+                                        q : out std_logic );
+                 end component D_flipflop;
+
+                 component tristate_buffer is
+                                             port ( a : in std_logic;
+                                                    en : in std_logic;
+                                                    y : out std_logic );
+                 end component tristate_buffer;
+
+               begin
+
+                 cell_array : for bit_index in 0 to width - 1 generate
+
+                   signal data_unbuffered : std_logic;
+
+                 begin
+
+                   cell_storage : component D_flipflop
+                     port map ( clk => clock, d => data_in(bit_index),
+                                q => data_unbuffered );
+
+                   cell_buffer : component tristate_buffer
+                     port map ( a => data_unbuffered, en => out_enable,
+                                y => data_out(bit_index) );
+
+                 end generate cell_array;
+
+               end architecture cell_level;
+
+-- end code from book (in Figure 14-1)
+
+
+-- code from book (in Figure 14-11)
+
+               library cell_lib;
+
+               configuration identical_cells of register_tristate is
+
+                 for cell_level
+
+                   for cell_array
+
+                   for cell_storage : D_flipflop
+                   use entity cell_lib.D_flipflop(synthesized);
+               end for;
+
+               for cell_buffer : tristate_buffer
+                 use entity cell_lib.tristate_buffer(synthesized);
+               end for;
+
+               end for;
+
+               end for;
+
+               end configuration identical_cells;
+
+-- code from book (in Figure 14-11)
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_01 is
+               end entity fg_14_01;
+
+
+               architecture test of fg_14_01 is
+
+                 signal clk, en : std_logic;
+                 signal d_in, d_out : std_logic_vector(0 to 3);
+
+               begin
+
+                 dut : configuration work.identical_cells
+                   generic map ( width => d_in'length )
+                   port map ( clock => clk, out_enable => en,
+                              data_in => d_in, data_out => d_out );
+
+                 stimulus : process is
+                 begin
+                   wait for 10 ns;
+                   d_in <= "0000";  en <= '0';  clk <= '0';  wait for 10 ns;
+                   clk <= '1', '0' after 5 ns;  wait for 10 ns;
+                   en <= '1', '0' after 5 ns;   wait for 10 ns;
+                   d_in <= "0101";              wait for 10 ns;
+                   clk <= '1', '0' after 5 ns;  wait for 10 ns;
+                   en <= 'H', '0' after 5 ns;   wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd
new file mode 100644
index 0000000..11fec16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity graphics_engine is
+end entity graphics_engine;
+
+-- end not in book
+
+
+architecture behavioral of graphics_engine is
+
+  type point is array (1 to 3) of real;
+  type transformation_matrix is array (1 to 3, 1 to 3) of real;
+
+  signal p, transformed_p : point;
+  signal a : transformation_matrix;
+  signal clock : bit;
+  -- . . .
+
+begin
+
+  transform_stage : for i in 1 to 3 generate
+  begin
+
+    cross_product_transform : process is
+                                        variable result1, result2, result3 : real := 0.0;
+    begin
+      wait until clock = '1';
+      transformed_p(i) <= result3;
+      result3 := result2;
+      result2 := result1;
+      result1 :=  a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
+    end process cross_product_transform;
+
+  end generate transform_stage;
+
+  -- . . .    -- other stages in the pipeline, etc
+
+  -- not in book
+
+  clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
+
+  stimulus : process is
+  begin
+    a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
+    p <= ( 10.0, 10.0, 10.0 );
+    wait until clock = '0';
+    p <= ( 20.0, 20.0, 20.0 );
+    wait until clock = '0';
+    p <= ( 30.0, 30.0, 30.0 );
+    wait until clock = '0';
+    p <= ( 40.0, 40.0, 40.0 );
+    wait until clock = '0';
+    p <= ( 50.0, 50.0, 50.0 );
+    wait until clock = '0';
+    p <= ( 60.0, 60.0, 60.0 );
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_04.vhd
new file mode 100644
index 0000000..d0d828c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_04.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity DRAM is
+                 port ( a :  in std_logic_vector(0 to 10);
+                        d :  inout std_logic_vector(0 to 3);
+                        cs, we, ras, cas : in std_logic );
+               end entity DRAM;
+
+
+               architecture empty of DRAM is
+               begin
+                 d <= (others => 'Z');
+               end architecture empty;
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity memory_board is
+               end entity memory_board;
+
+-- end not in book
+
+
+               architecture chip_level of memory_board is
+
+                 component DRAM is
+                                  port ( a :  in std_logic_vector(0 to 10);
+                                         d :  inout std_logic_vector(0 to 3);
+                                         cs, we, ras, cas : in std_logic );
+                 end component DRAM;
+
+                 signal buffered_address : std_logic_vector(0 to 10);
+                 signal DRAM_data : std_logic_vector(0 to 31);
+                 signal bank_select : std_logic_vector(0 to 3);
+                 signal buffered_we, buffered_ras, buffered_cas : std_logic;
+
+                 -- . . .    -- other declarations
+
+               begin
+
+                 bank_array : for bank_index in 0 to 3 generate
+                 begin
+
+                   nibble_array : for nibble_index in 0 to 7 generate
+
+                     constant data_lo : natural := nibble_index * 4;
+                     constant data_hi : natural := nibble_index * 4 + 3;
+
+                   begin
+
+                     a_DRAM : component DRAM
+                       port map ( a => buffered_address,
+                                  d => DRAM_data(data_lo to data_hi),
+                                  cs => bank_select(bank_index),
+                                  we => buffered_we,
+                                  ras => buffered_ras,
+                                  cas => buffered_cas );
+
+                   end generate nibble_array;
+
+                 end generate bank_array;
+
+                 -- . . .    -- other component instances, etc
+
+                 -- not in book
+
+                 buffered_address <= "01010101010";
+                 DRAM_data <= X"01234567";
+
+                 -- end not in book
+
+               end architecture chip_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd
new file mode 100644
index 0000000..e0784d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd
@@ -0,0 +1,152 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_05.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity master_slave_flipflop is
+                 port ( phi1, phi2 : in std_logic;
+                        d : in std_logic;
+                        q : out std_logic );
+               end entity master_slave_flipflop;
+
+
+               architecture behavioral of master_slave_flipflop is
+
+                 signal master_d : std_logic;
+
+               begin
+
+                 master_d <= d when phi1 = '1';
+
+                 q <= master_d when phi2 = '1';
+
+               end architecture behavioral;
+
+
+
+
+
+-- code from book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity shift_reg is
+                 port ( phi1, phi2 : in std_logic;
+                        serial_data_in : in std_logic;
+                        parallel_data : inout std_logic_vector );
+               end entity shift_reg;
+
+--------------------------------------------------
+
+               architecture cell_level of shift_reg is
+
+                 alias normalized_parallel_data :
+                   std_logic_vector(0 to parallel_data'length - 1)
+                   is parallel_data;
+
+                 component master_slave_flipflop is
+                                                   port ( phi1, phi2 : in std_logic;
+                                                          d : in std_logic;
+                                                          q : out std_logic );
+                 end component master_slave_flipflop;
+
+               begin
+
+                 reg_array : for index in normalized_parallel_data'range generate
+                 begin
+
+                   first_cell : if index = 0 generate
+                   begin
+                     cell : component master_slave_flipflop
+                       port map ( phi1, phi2,
+                                  d => serial_data_in,
+                                  q => normalized_parallel_data(index) );
+                   end generate first_cell;
+
+                   other_cell : if index /= 0 generate
+                   begin
+                     cell : component master_slave_flipflop
+                       port map ( phi1, phi2,
+                                  d => normalized_parallel_data(index - 1),
+                                  q => normalized_parallel_data(index) );
+                   end generate other_cell;
+
+                 end generate reg_array;
+
+               end architecture cell_level;
+
+-- end code from book
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_05 is
+               end entity fg_14_05;
+
+
+               architecture test of fg_14_05 is
+
+                 signal phi1, phi2, serial_data_in : std_logic := '0';
+                 signal parallel_data : std_logic_vector(3 downto 0);
+
+               begin
+
+                 dut : entity work.shift_reg(cell_level)
+                   port map ( phi1 => phi1, phi2 => phi2,
+                              serial_data_in => serial_data_in,
+                              parallel_data => parallel_data );
+
+                 clock_gen : process is
+                 begin
+                   phi1 <= '1', '0' after 4 ns;
+                   phi2 <= '1' after 5 ns, '0' after 9 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+                 stimulus : process is
+                 begin
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd
new file mode 100644
index 0000000..eb19069
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd
@@ -0,0 +1,175 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book (in text)
+
+entity computer_system is
+  generic ( instrumented : boolean := false );
+  port ( -- . . . );
+    -- not in book
+    other_port : in bit := '0' );
+  -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc
+
+  instrumentation : if instrumented generate
+
+    signal ifetch_freq, write_freq, read_freq : real := 0.0;
+
+  begin
+
+    access_monitor : process is
+                               variable access_count, ifetch_count,
+                             write_count, read_count : natural := 0;
+    begin
+      wait until mem_req = '1';
+      if ifetch = '1' then
+        ifetch_count := ifetch_count + 1;
+      elsif write = '1' then
+        write_count := write_count + 1;
+      else
+        read_count := read_count + 1;
+      end if;
+      access_count := access_count + 1;
+      ifetch_freq <= real(ifetch_count) / real(access_count);
+      write_freq <= real(write_count) / real(access_count);
+      read_freq <= real(read_count) / real(access_count);
+    end process access_monitor;
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
+
+
+
+entity fg_14_06 is
+end entity fg_14_06;
+
+
+architecture test of fg_14_06 is
+
+  component computer_system is
+                              port ( other_port : in bit := '0' );
+  end component computer_system;
+
+begin
+
+  system_under_test : component computer_system
+    port map ( other_port => open );
+
+end architecture test;
+
+
+
+configuration fg_14_06_test of fg_14_06 is
+
+  for test
+
+    -- code from book (in text)
+
+    for system_under_test : computer_system
+      use entity work.computer_system(block_level)
+        generic map ( instrumented => true )
+        -- . . .
+        -- not in book
+        ;
+      -- end not in book
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration fg_14_06_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_08.vhd
new file mode 100644
index 0000000..321ab2b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_08.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity buf is
+                 port ( a : in std_logic;  y : out std_logic );
+               end entity buf;
+
+
+               architecture basic of buf is
+               begin
+                 y <= a;
+               end architecture basic;
+
+
+
+
+-- code from book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fanout_tree is
+                 generic ( height : natural );
+                 port ( input : in std_logic;
+                        output : out std_logic_vector (0 to 2**height - 1) );
+               end entity fanout_tree;
+
+--------------------------------------------------
+
+               architecture recursive of fanout_tree is
+
+               begin
+
+                 degenerate_tree : if height = 0 generate
+                 begin
+                   output(0) <= input;
+                 end generate degenerate_tree;
+
+                 compound_tree : if height > 0 generate
+                   signal buffered_input_0, buffered_input_1 : std_logic;
+                 begin
+
+                   buf_0 : entity work.buf(basic)
+                     port map ( a => input, y => buffered_input_0 );
+
+                   subtree_0 : entity work.fanout_tree(recursive)
+                     generic map ( height => height - 1 )
+                     port map ( input => buffered_input_0,
+                                output => output(0 to 2**(height - 1) - 1) );
+
+                   buf_1 : entity work.buf(basic)
+                     port map ( a => input, y => buffered_input_1 );
+
+                   subtree_1 : entity work.fanout_tree(recursive)
+                     generic map ( height => height - 1 )
+                     port map ( input => buffered_input_1,
+                                output => output(2**(height - 1) to 2**height - 1) );
+
+                 end generate compound_tree;
+
+               end architecture recursive;
+
+-- end code from book
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_08 is
+               end entity fg_14_08;
+
+
+               architecture test of fg_14_08 is
+
+                 signal unbuffered_clock : std_logic;
+                 signal buffered_clock_array : std_logic_vector(0 to 7);
+
+               begin
+
+                 -- code from book (in text)
+
+                 clock_buffer_tree : entity work.fanout_tree(recursive)
+                   generic map ( height => 3 )
+                   port map ( input => unbuffered_clock,
+                              output => buffered_clock_array );
+
+                 -- end code from book
+
+                 clock_gen : process is
+                 begin
+                   unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_09.vhd
new file mode 100644
index 0000000..4063ca2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_09.vhd
@@ -0,0 +1,182 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package bus_monitor_pkg is
+
+  type stats_type is record
+                       ifetch_freq, write_freq, read_freq : real;
+                     end record stats_type;
+
+  component bus_monitor is
+                          generic ( verbose, dump_stats : boolean := false );
+                        port ( mem_req, ifetch, write : in bit;
+                               bus_stats : out stats_type );
+  end component bus_monitor;
+
+end package bus_monitor_pkg;
+
+
+use work.bus_monitor_pkg.all;
+
+entity bus_monitor is
+  generic ( verbose, dump_stats : boolean := false );
+  port ( mem_req, ifetch, write : in bit;
+         bus_stats : out stats_type );
+end entity bus_monitor;
+
+
+architecture general_purpose of bus_monitor is
+begin
+
+  access_monitor : process is
+
+                             variable access_count, ifetch_count,
+                           write_count, read_count : natural := 0;
+                           use std.textio;
+                           variable L : textio.line;
+
+  begin
+    wait until mem_req = '1';
+    if ifetch = '1' then
+      ifetch_count := ifetch_count + 1;
+      if verbose then
+        textio.write(L, string'("Ifetch"));
+        textio.writeline(textio.output, L);
+      end if;
+    elsif write = '1' then
+      write_count := write_count + 1;
+      if verbose then
+        textio.write(L, string'("Write"));
+        textio.writeline(textio.output, L);
+      end if;
+    else
+      read_count := read_count + 1;
+      if verbose then
+        textio.write(L, string'("Read"));
+        textio.writeline(textio.output, L);
+      end if;
+    end if;
+    access_count := access_count + 1;
+    bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
+    bus_stats.write_freq <= real(write_count) / real(access_count);
+    bus_stats.read_freq <= real(read_count) / real(access_count);
+    if dump_stats and access_count mod 5 = 0 then
+      textio.write(L, string'("Ifetch frequency = "));
+      textio.write(L, real(ifetch_count) / real(access_count));
+      textio.writeline(textio.output, L);
+      textio.write(L, string'("Write frequency = "));
+      textio.write(L, real(write_count) / real(access_count));
+      textio.writeline(textio.output, L);
+      textio.write(L, string'("Read frequency = "));
+      textio.write(L, real(read_count) / real(access_count));
+      textio.writeline(textio.output, L);
+    end if;
+  end process access_monitor;
+
+end architecture general_purpose;
+
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc.
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc.
+
+  instrumentation : if instrumented generate
+
+    use work.bus_monitor_pkg;
+    signal bus_stats : bus_monitor_pkg.stats_type;
+
+  begin
+
+    cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
+      port map ( mem_req, ifetch, write, bus_stats );
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_10.vhd
new file mode 100644
index 0000000..c611f1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_10.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration architectural of computer_system is
+
+  for block_level
+
+    -- . . .    -- component configurations for cpu and memory, etc
+
+    for instrumentation
+
+      for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
+                                             use entity work.bus_monitor(general_purpose)
+                                             generic map ( verbose => true, dump_stats => true );
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration architectural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_11.vhd
new file mode 100644
index 0000000..f86d520
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_11.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+library cell_lib;
+
+configuration identical_cells of register_tristate is
+
+  for cell_level
+
+    for cell_array
+
+      for cell_storage : D_flipflop
+        use entity cell_lib.D_flipflop(synthesized);
+      end for;
+
+      for cell_buffer : tristate_buffer
+        use entity cell_lib.tristate_buffer(synthesized);
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration identical_cells;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_12.vhd
new file mode 100644
index 0000000..3a523bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_12.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity DRAM_4M_by_4 is
+                 port ( a :  in std_logic_vector(0 to 10);
+                        d :  inout std_logic_vector(0 to 3);
+                        cs, we, ras, cas : in std_logic );
+               end entity DRAM_4M_by_4;
+
+
+               architecture chip_function of DRAM_4M_by_4 is
+               begin
+                 d <= (others => 'Z');
+               end architecture chip_function;
+
+
+-- code from book
+
+               library chip_lib;  use chip_lib.all;
+
+               configuration down_to_chips of memory_board is
+
+                 for chip_level
+
+                   for bank_array
+
+                   for nibble_array
+
+                   for a_DRAM : DRAM
+                   use entity DRAM_4M_by_4(chip_function);
+               end for;
+
+               end for;
+
+               end for;
+
+               -- . . .    -- configurations of other component instances
+
+               end for;
+
+               end configuration down_to_chips;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_13.vhd
new file mode 100644
index 0000000..bdfa833
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_13.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_13.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity ms_flipflop is
+                 port ( phi1, phi2 : in std_logic;
+                        d : in std_logic;
+                        q : out std_logic );
+               end entity ms_flipflop;
+
+
+               architecture normal_drive of ms_flipflop is
+                 signal master_d : std_logic;
+               begin
+                 master_d <= d when phi1 = '1';
+                 q <= master_d when phi2 = '1';
+               end architecture normal_drive;
+
+
+               architecture high_drive of ms_flipflop is
+                 signal master_d : std_logic;
+               begin
+                 master_d <= d when phi1 = '1';
+                 q <= master_d when phi2 = '1';
+               end architecture high_drive;
+
+
+
+-- code from book
+
+               library cell_lib;
+
+               configuration last_high_drive of shift_reg is
+
+                 for cell_level
+
+                   -- workaround for MTI bug mt026
+                   -- for reg_array ( 0 to parallel_data'length - 2 )
+                   for reg_array ( 0 to 2 )
+                   -- end workaround
+
+                   for first_cell
+                   for cell : master_slave_flipflop
+                   use entity cell_lib.ms_flipflop(normal_drive);
+               end for;
+               end for;
+
+               for other_cell
+                 for cell : master_slave_flipflop
+                 use entity cell_lib.ms_flipflop(normal_drive);
+               end for;
+               end for;
+
+               end for;
+
+               -- workaround for MTI bug mt026
+               -- for reg_array ( parallel_data'length - 1 )
+               for reg_array ( 3 )
+                 -- end workaround
+
+                 for other_cell
+                 for cell : master_slave_flipflop
+                 use entity cell_lib.ms_flipflop(high_drive);
+               end for;
+               end for;
+
+               end for;
+
+               end for;
+
+               end configuration last_high_drive;
+
+-- end code from book
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_13 is
+               end entity fg_14_13;
+
+
+               architecture test of fg_14_13 is
+
+                 signal phi1, phi2, serial_data_in : std_logic := '0';
+                 signal parallel_data : std_logic_vector(3 downto 0);
+
+               begin
+
+                 dut : configuration work.last_high_drive
+                   port map ( phi1 => phi1, phi2 => phi2,
+                              serial_data_in => serial_data_in,
+                              parallel_data => parallel_data );
+
+                 clock_gen : process is
+                 begin
+                   phi1 <= '1', '0' after 4 ns;
+                   phi2 <= '1' after 5 ns, '0' after 9 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+                 stimulus : process is
+                 begin
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd
new file mode 100644
index 0000000..a4e0a19
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_alu-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behavior of alu is
+
+begin
+
+  alu_op: process ( s1, s2, func ) is
+
+                                     variable bv_s1, bv_s2 : dlx_bv_word;
+                                   variable temp_result : dlx_bv_word;
+                                   variable temp_overflow : boolean;
+
+                                   type boolean_to_X01_table is array (boolean) of X01;
+                                   constant boolean_to_X01 : boolean_to_X01_table := ( '0', '1' );
+
+  begin
+    bv_s1 := To_bitvector(s1);
+    bv_s2 := To_bitvector(s2);
+    temp_overflow := false;
+    case func is
+      when alu_pass_s1 =>
+        temp_result := bv_s1;
+      when alu_pass_s2 =>
+        temp_result := bv_s2;
+      when alu_and =>
+        temp_result := bv_s1 and bv_s2;
+      when alu_or =>
+        temp_result := bv_s1 or bv_s2;
+      when alu_xor =>
+        temp_result := bv_s1 xor bv_s2;
+      when alu_sll =>
+        temp_result := bv_s1 sll bv_to_natural(bv_s2(27 to 31));
+      when alu_srl =>
+        temp_result := bv_s1 srl bv_to_natural(bv_s2(27 to 31));
+      when alu_sra =>
+        temp_result := bv_s1 sra bv_to_natural(bv_s2(27 to 31));
+      when alu_add =>
+        bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_addu =>
+        bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_sub =>
+        bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_subu =>
+        bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when others =>
+	report "illegal function code" severity error;
+	temp_result := X"0000_0000";
+    end case;
+    result <= To_X01(temp_result) after Tpd;
+    zero <= boolean_to_X01(temp_result = X"0000_0000") after Tpd;
+    negative <= To_X01(temp_result(0)) after Tpd;
+    overflow <= boolean_to_X01(temp_overflow) after Tpd;
+  end process alu_op;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu.vhd
new file mode 100644
index 0000000..f3cc532
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_alu.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all,
+  work.alu_types.all;
+
+entity alu is
+  generic ( Tpd : delay_length );
+  port ( s1 : in dlx_word;
+         s2 : in dlx_word;
+         result : out dlx_word;
+         func : in alu_func;
+         zero, negative, overflow : out std_logic );
+end entity alu;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alut.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alut.vhd
new file mode 100644
index 0000000..f776434
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alut.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_alut.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package alu_types is
+
+  subtype alu_func is std_logic_vector(3 downto 0);
+
+  constant alu_add :     alu_func := "0000";
+  constant alu_addu :    alu_func := "0001";
+  constant alu_sub :     alu_func := "0010";
+  constant alu_subu :    alu_func := "0011";
+  constant alu_and :     alu_func := "0100";
+  constant alu_or :      alu_func := "0101";
+  constant alu_xor :     alu_func := "0110";
+  constant alu_sll :     alu_func := "1000";
+  constant alu_srl :     alu_func := "1001";
+  constant alu_sra :     alu_func := "1010";
+  constant alu_pass_s1 : alu_func := "1100";
+  constant alu_pass_s2 : alu_func := "1101";
+
+end package alu_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd
new file mode 100644
index 0000000..306c48d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_cg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of clock_gen is
+
+  constant clock_period : delay_length := 2 * (Tpw + Tps);
+
+begin
+
+  reset_driver : 
+    reset <= '1', '0' after 2.5 * clock_period + Tps;
+
+  clock_driver : process is
+  begin
+    phi1 <= '0';
+    phi2 <= '0';
+    wait for clock_period / 2;
+    loop
+      phi1 <= '1', '0' after Tpw;
+      phi2 <= '1' after clock_period / 2,
+              '0' after clock_period / 2 + Tpw;
+      wait for clock_period;
+    end loop;
+  end process clock_driver;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg.vhd
new file mode 100644
index 0000000..d04b7c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_cg.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity clock_gen is
+
+                 generic ( Tpw : delay_length;
+                           Tps : delay_length );
+
+                 port ( phi1, phi2 : out std_logic;
+                        reset : out std_logic );
+
+               end entity clock_gen;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd
new file mode 100644
index 0000000..3bb331a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all,
+  work.alu_types.all,
+  work.reg_file_types.all;
+
+entity controller is
+  generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
+            debug : dlx_debug_control := none );
+  port ( phi1, phi2 : in std_logic;
+         reset : in std_logic;
+         halt : out std_logic;
+         width : out dlx_mem_width;
+         write_enable : out std_logic;
+         mem_enable : out std_logic;
+         ifetch : out std_logic;
+         ready : in std_logic;
+         alu_in_latch_en : out std_logic;
+         alu_function : out alu_func;
+         alu_zero, alu_negative, alu_overflow : in std_logic;
+         reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
+         reg_write : out std_logic;
+         c_latch_en : out std_logic;
+         a_latch_en, a_out_en : out std_logic;
+         b_latch_en, b_out_en : out std_logic;
+         temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
+         iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
+         pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
+         mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
+         mem_addr_mux_sel : out std_logic;
+         mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
+         mdr_mux_sel : out std_logic;
+         ir_latch_en : out std_logic;
+         ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
+         ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
+         ir_immed1_en, ir_immed2_en : out std_logic;
+         current_instruction : in dlx_word;
+         mem_addr : std_logic_vector(1 downto 0);
+         const1, const2 : out dlx_word );
+end entity controller;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ctrl-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ctrl-b.vhd
new file mode 100644
index 0000000..7f773c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ctrl-b.vhd
@@ -0,0 +1,913 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_ctrl-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+library work;
+use work.dlx_instr.all;
+
+architecture behavior of controller is
+
+begin -- behavior
+
+  sequencer : process is
+
+                        variable current_instruction_bv : dlx_bv_word;
+
+                      alias IR_opcode : dlx_opcode is current_instruction_bv(0 to 5);
+                      alias IR_sp_func : dlx_sp_func is current_instruction_bv(26 to 31);
+                      alias IR_fp_func : dlx_fp_func is current_instruction_bv(27 to 31);
+
+                      alias IR_rs1 : reg_file_addr is current_instruction(6 to 10);
+                      alias IR_rs2 : reg_file_addr is current_instruction(11 to 15);
+                      alias IR_Itype_rd : reg_file_addr is current_instruction(11 to 15);
+                      alias IR_Rtype_rd : reg_file_addr is current_instruction(16 to 20);
+
+                      variable result_of_set_is_1, branch_taken : boolean;
+
+                      variable disassembled_instr : string(1 to 40);
+                      variable disassembled_instr_len : positive;
+
+                      variable instr_count : natural := 0;
+
+                      procedure bus_instruction_fetch is
+                      begin
+                        -- use PC as address
+                        mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
+                        -- set up memory control signals
+                        width <= dlx_mem_width_word after Tpd_clk_ctrl;
+                        ifetch <= '1' after Tpd_clk_ctrl;
+                        write_enable <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '1' after Tpd_clk_ctrl;
+                        -- wait until phi2, then enable IR input
+                        wait until rising_edge(phi2);
+                        ir_latch_en <= '1' after Tpd_clk_ctrl;
+                        -- wait until memory is ready at end of phi2
+                        loop 
+                          wait until falling_edge(phi2);
+                          if To_bit(reset) = '1' then
+                            return;
+                          end if;
+                          exit when To_bit(ready) = '1';
+                        end loop;
+                        -- disable IR input and memory control signals
+                        ir_latch_en <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '0' after Tpd_clk_ctrl;
+                      end procedure bus_instruction_fetch;
+
+                      procedure bus_data_read ( read_width : in dlx_mem_width ) is
+                      begin
+                        -- use MAR as address
+                        mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
+                        -- set up memory control signals
+                        width <= read_width after Tpd_clk_ctrl;
+                        ifetch <= '0' after Tpd_clk_ctrl;
+                        write_enable <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '1' after Tpd_clk_ctrl;
+                        -- wait until phi2, then enable MDR input
+                        wait until rising_edge(phi2);
+                        mdr_mux_sel <= '1' after Tpd_clk_ctrl;
+                        mdr_latch_en <= '1' after Tpd_clk_ctrl;
+                        -- wait until memory is ready at end of phi2
+                        loop 
+                          wait until falling_edge(phi2);
+                          if To_bit(reset) = '1' then
+                            return;
+                          end if;
+                          exit when To_bit(ready) = '1';
+                        end loop;
+                        -- disable MDR input and memory control signals
+                        mdr_latch_en <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '0' after Tpd_clk_ctrl;
+                      end procedure bus_data_read;
+
+                      procedure bus_data_write ( write_width : in dlx_mem_width ) is
+                      begin
+                        -- use MAR as address
+                        mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
+                        -- enable MDR output
+                        mdr_out_en3 <= '1' after Tpd_clk_ctrl;
+                        -- set up memory control signals
+                        width <= write_width after Tpd_clk_ctrl;
+                        ifetch <= '0' after Tpd_clk_ctrl;
+                        write_enable <= '1' after Tpd_clk_ctrl;
+                        mem_enable <= '1' after Tpd_clk_ctrl;
+                        -- wait until memory is ready at end of phi2
+                        loop 
+                          wait until falling_edge(phi2);
+                          if To_bit(reset) = '1' then
+                            return;
+                          end if;
+                          exit when To_bit(ready) = '1';
+                        end loop;
+                        -- disable MDR output and memory control signals
+                        write_enable <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '0' after Tpd_clk_ctrl;
+                        mdr_out_en3 <= '0' after Tpd_clk_ctrl;
+                      end procedure bus_data_write;
+
+                      procedure do_set_result is
+                      begin
+                        wait until rising_edge(phi1);
+                        if result_of_set_is_1 then
+                          const2 <= X"0000_0001" after Tpd_clk_const;
+                        else
+                          const2 <= X"0000_0000" after Tpd_clk_const;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        const2 <= disabled_dlx_word after Tpd_clk_const;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_set_result;    
+
+                      procedure do_EX_set_unsigned ( immed : boolean ) is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                          ir_immed2_unsigned <= '1' after Tpd_clk_ctrl;
+                          ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '1' after Tpd_clk_ctrl;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_subu after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_en <= '0' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until falling_edge(phi2);
+                        if immed then
+                          case IR_opcode is
+                            when op_sequi => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when op_sneui =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when op_sltui =>
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1';
+                            when op_sgtui => 
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1' and To_bit(alu_zero) /= '1';
+                            when op_sleui => 
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1' or To_bit(alu_zero) = '1';
+                            when op_sgeui => 
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        else
+                          case IR_sp_func is
+                            when sp_func_sequ => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when sp_func_sneu =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when sp_func_sltu =>
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1';
+                            when sp_func_sgtu =>
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1' and To_bit(alu_zero) /= '1';
+                            when sp_func_sleu => 
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1' or To_bit(alu_zero) = '1';
+                            when sp_func_sgeu => 
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        end if;
+
+                        do_set_result;
+                      end procedure do_EX_set_unsigned;
+
+                      procedure do_EX_set_signed ( immed : boolean ) is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                          ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                          ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '1' after Tpd_clk_ctrl;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_sub after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_en <= '0' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until falling_edge(phi2);
+                        if immed then
+                          case IR_opcode is
+                            when op_seqi => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when op_snei =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when op_slti =>
+                              result_of_set_is_1 := To_bit(alu_negative) = '1';
+                            when op_sgti => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1' and To_bit(alu_zero) /= '1';
+                            when op_slei => 
+                              result_of_set_is_1 := To_bit(alu_negative) = '1' or To_bit(alu_zero) = '1';
+                            when op_sgei => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        else
+                          case IR_sp_func is
+                            when sp_func_seq => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when sp_func_sne =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when sp_func_slt =>
+                              result_of_set_is_1 := To_bit(alu_negative) = '1';
+                            when sp_func_sgt => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1' and To_bit(alu_zero) /= '1';
+                            when sp_func_sle => 
+                              result_of_set_is_1 := To_bit(alu_negative) = '1' or To_bit(alu_zero) = '1';
+                            when sp_func_sge => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        end if;
+
+                        do_set_result;
+                      end procedure do_EX_set_signed;
+
+                      procedure do_EX_arith_logic is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        b_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        case IR_sp_func is
+                          when sp_func_add =>
+                            alu_function <= alu_add after Tpd_clk_ctrl;
+                          when sp_func_addu =>
+                            alu_function <= alu_addu after Tpd_clk_ctrl;
+                          when sp_func_sub =>
+                            alu_function <= alu_sub after Tpd_clk_ctrl;
+                          when sp_func_subu =>
+                            alu_function <= alu_subu after Tpd_clk_ctrl;
+                          when sp_func_and =>
+                            alu_function <= alu_and after Tpd_clk_ctrl;
+                          when sp_func_or =>
+                            alu_function <= alu_or after Tpd_clk_ctrl;
+                          when sp_func_xor =>
+                            alu_function <= alu_xor after Tpd_clk_ctrl;
+                          when sp_func_sll =>
+                            alu_function <= alu_sll after Tpd_clk_ctrl;
+                          when sp_func_srl =>
+                            alu_function <= alu_srl after Tpd_clk_ctrl;
+                          when sp_func_sra =>
+                            alu_function <= alu_sra after Tpd_clk_ctrl;
+                          when others =>
+                            null;
+                        end case;                  --  IR_sp_func
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        b_out_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_arith_logic;
+
+                      procedure do_EX_arith_logic_immed is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                        if IR_opcode = op_addi or IR_opcode = op_subi then
+                          ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        else
+                          ir_immed2_unsigned <= '1' after Tpd_clk_ctrl;
+                        end if;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        case IR_opcode is
+                          when op_addi =>
+                            alu_function <= alu_add after Tpd_clk_ctrl;
+                          when op_subi =>
+                            alu_function <= alu_sub after Tpd_clk_ctrl;
+                          when op_addui =>
+                            alu_function <= alu_addu after Tpd_clk_ctrl;
+                          when op_subui =>
+                            alu_function <= alu_subu after Tpd_clk_ctrl;
+                          when op_andi =>
+                            alu_function <= alu_and after Tpd_clk_ctrl;
+                          when op_ori =>
+                            alu_function <= alu_or after Tpd_clk_ctrl;
+                          when op_xori =>
+                            alu_function <= alu_xor after Tpd_clk_ctrl;
+                          when op_slli =>
+                            alu_function <= alu_sll after Tpd_clk_ctrl;
+                          when op_srli =>
+                            alu_function <= alu_srl after Tpd_clk_ctrl;
+                          when op_srai =>
+                            alu_function <= alu_sra after Tpd_clk_ctrl;
+                          when others =>
+                            null;
+                        end case;                      --  IR_opcode
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_arith_logic_immed;
+
+                      procedure do_EX_link is
+                      begin
+                        wait until rising_edge(phi1);
+                        pc_out_en1 <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        pc_out_en1 <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_link;
+
+                      procedure do_EX_lhi is
+                      begin
+                        wait until rising_edge(phi1);
+                        ir_immed1_size_26 <= '0' after Tpd_clk_ctrl;
+                        ir_immed1_unsigned <= '1' after Tpd_clk_ctrl;
+                        ir_immed1_en <= '1' after Tpd_clk_ctrl;
+                        const2 <= X"0000_0010" after Tpd_clk_const;         -- shift by 16 bits
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_sll after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        ir_immed1_en <= '0' after Tpd_clk_ctrl;
+                        const2 <= disabled_dlx_word after Tpd_clk_const;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_lhi;    
+
+                      procedure do_EX_branch is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        if IR_opcode = op_beqz then
+                          branch_taken := To_bit(alu_zero) = '1';
+                        else
+                          branch_taken := To_bit(alu_zero) /= '1';
+                        end if;
+                      end procedure do_EX_branch;
+
+                      procedure do_EX_load_store is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_add after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        mar_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        mar_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_load_store;
+
+                      procedure do_MEM_jump is
+                      begin
+                        wait until rising_edge(phi1);
+                        pc_out_en1 <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_add after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        pc_out_en1 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        pc_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_jump;
+
+                      procedure do_MEM_jump_reg is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        pc_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_jump_reg;
+
+                      procedure do_MEM_branch is
+                      begin
+                        wait until rising_edge(phi1);
+                        pc_out_en1 <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_add after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        pc_out_en1 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        pc_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_branch;
+
+                      procedure do_MEM_load is
+                        subtype ls_2_addr_bits is bit_vector(1 downto 0);
+                      begin
+                        wait until rising_edge(phi1);
+                        if IR_opcode = op_lb or IR_opcode = op_lbu then
+                          bus_data_read(dlx_mem_width_byte);
+                        elsif IR_opcode = op_lh or IR_opcode = op_lhu then
+                          bus_data_read(dlx_mem_width_halfword);
+                        else
+                          bus_data_read(dlx_mem_width_word);
+                        end if;
+                        if To_bit(reset) = '1' then
+                          return;
+                        end if;
+
+                        if ( (IR_opcode = op_lb or IR_opcode = op_lbu) and To_bitvector(mem_addr) /= "00" )
+                          or ( (IR_opcode = op_lh or IR_opcode = op_lhu) and To_bit(mem_addr(1)) /= '0' ) then
+                          -- first step of extension: left-justify byte or halfword -> mdr
+                          wait until rising_edge(phi1);
+                          mdr_out_en1 <= '1' after Tpd_clk_ctrl;
+                          if IR_opcode = op_lb or IR_opcode = op_lbu then
+                            case ls_2_addr_bits'(To_bitvector(mem_addr)) is
+                              when "00" => 
+                                null;
+                              when "01" => 
+                                const2 <= X"0000_0008" after Tpd_clk_const;
+                              when "10" => 
+                                const2 <= X"0000_0010" after Tpd_clk_const;
+                              when "11" => 
+                                const2 <= X"0000_0018" after Tpd_clk_const;
+                            end case;
+                          else
+                            const2 <= X"0000_0010" after Tpd_clk_const;
+                          end if;
+                          alu_function <= alu_sll after Tpd_clk_ctrl;
+                          alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi1);
+                          mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+                          const2 <= disabled_dlx_word after Tpd_clk_const;
+                          alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                          wait until rising_edge(phi2);
+                          mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+                          mdr_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi2);
+                          mdr_latch_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until rising_edge(phi1);
+                        mdr_out_en1 <= '1' after Tpd_clk_ctrl;
+                        if IR_opcode = op_lb or IR_opcode = op_lbu then
+                          const2 <= X"0000_0018" after Tpd_clk_const;
+                        elsif IR_opcode = op_lh or IR_opcode = op_lhu then
+                          const2 <= X"0000_0010" after Tpd_clk_const;
+                        else
+                          const2 <= X"0000_0000" after Tpd_clk_const;
+                        end if;
+                        if IR_opcode = op_lbu or IR_opcode = op_lhu then
+                          alu_function <= alu_srl after Tpd_clk_ctrl;
+                        else
+                          alu_function <= alu_sra after Tpd_clk_ctrl;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+                        const2 <= disabled_dlx_word after Tpd_clk_const;
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_load;    
+
+                      procedure do_MEM_store is
+                        subtype ls_2_addr_bits is bit_vector(1 downto 0);
+                      begin
+                        wait until rising_edge(phi1);
+                        b_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        b_out_en <= '0' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+                        mdr_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        mdr_latch_en <= '0' after Tpd_clk_ctrl;
+
+                        if ( IR_opcode = op_sb and To_bitvector(mem_addr) /= "11" )
+                          or ( IR_opcode = op_sh and To_bit(mem_addr(1)) /= '1' ) then
+                          -- align byte or halfword -> mdr
+                          wait until rising_edge(phi1);
+                          mdr_out_en1 <= '1' after Tpd_clk_ctrl;
+                          if IR_opcode = op_sb then
+                            case ls_2_addr_bits'(To_bitvector(mem_addr)) is
+                              when "00" => 
+                                const2 <= X"0000_0018" after Tpd_clk_const;
+                              when "01" => 
+                                const2 <= X"0000_0010" after Tpd_clk_const;
+                              when "10" => 
+                                const2 <= X"0000_0008" after Tpd_clk_const;
+                              when "11" => 
+                                null;
+                            end case;
+                          else
+                            const2 <= X"0000_0010" after Tpd_clk_const;
+                          end if;
+                          alu_function <= alu_sll after Tpd_clk_ctrl;
+                          alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi1);
+                          mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+                          const2 <= disabled_dlx_word after Tpd_clk_const;
+                          alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                          wait until rising_edge(phi2);
+                          mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+                          mdr_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi2);
+                          mdr_latch_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until rising_edge(phi1);
+                        if IR_opcode = op_sb then
+                          bus_data_write(dlx_mem_width_byte);
+                        elsif IR_opcode = op_sh then
+                          bus_data_write(dlx_mem_width_halfword);
+                        else
+                          bus_data_write(dlx_mem_width_word);
+                        end if;
+                      end procedure do_MEM_store;
+
+                      procedure do_WB ( Rd : reg_file_addr ) is
+                      begin
+                        wait until rising_edge(phi1);
+                        reg_dest_addr <= Rd after Tpd_clk_ctrl;
+                        reg_write <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        reg_write <= '0' after Tpd_clk_ctrl;
+                      end procedure do_WB;
+
+                      procedure execute_op_special is
+                      begin
+                        case IR_sp_func is
+                          when sp_func_nop =>
+                            null;
+                          when sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu
+                            | sp_func_sll | sp_func_srl | sp_func_sra
+                            | sp_func_and | sp_func_or | sp_func_xor =>
+                            do_EX_arith_logic;
+                            do_WB(IR_Rtype_rd);
+                          when sp_func_sequ | sp_func_sneu | sp_func_sltu
+                            | sp_func_sgtu | sp_func_sleu | sp_func_sgeu => 
+                            do_EX_set_unsigned(immed => false);
+                            do_WB(IR_Rtype_rd);
+                          when sp_func_seq | sp_func_sne | sp_func_slt
+                            | sp_func_sgt | sp_func_sle | sp_func_sge => 
+                            do_EX_set_signed(immed => false);
+                            do_WB(IR_Rtype_rd);
+                          when sp_func_movi2s | sp_func_movs2i
+                            | sp_func_movf | sp_func_movd
+                            | sp_func_movfp2i | sp_func_movi2fp  => 
+                            report sp_func_names(bv_to_natural(IR_sp_func))
+                              & " instruction not implemented" severity warning;
+                          when others =>
+                            report "undefined special instruction function" severity error;
+                        end case;  
+                      end procedure execute_op_special;
+
+                      procedure execute_op_fparith is
+                      begin
+                        case IR_fp_func is
+                          when fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu
+                            | fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
+                            | fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
+                            | fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f
+                            | fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d
+                            | fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf
+                            | fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned
+                            | fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged => 
+                            report fp_func_names(bv_to_natural(IR_fp_func))
+                              & " instruction not implemented" severity warning;
+                          when others =>
+                            report "undefined floating point instruction function" severity error;
+                        end case;
+                      end procedure execute_op_fparith;
+
+  begin -- sequencer
+
+    ----------------------------------------------------------------
+    -- initialize all control signals
+    ----------------------------------------------------------------
+    if debug > none then
+      report "initializing";
+    end if;
+
+    halt <= '0' after Tpd_clk_ctrl;
+    width <= dlx_mem_width_word after Tpd_clk_ctrl;
+    write_enable <= '0' after Tpd_clk_ctrl;
+    mem_enable <= '0' after Tpd_clk_ctrl;
+    ifetch <= '0' after Tpd_clk_ctrl;
+    alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+    alu_function <= alu_add after Tpd_clk_ctrl;
+    reg_s1_addr <= B"00000" after Tpd_clk_ctrl;
+    reg_s2_addr <= B"00000" after Tpd_clk_ctrl;
+    reg_dest_addr <= B"00000" after Tpd_clk_ctrl;
+    reg_write <= '0' after Tpd_clk_ctrl;
+    c_latch_en <= '0' after Tpd_clk_ctrl;
+    a_latch_en <= '0' after Tpd_clk_ctrl;
+    a_out_en <= '0' after Tpd_clk_ctrl;
+    b_latch_en <= '0' after Tpd_clk_ctrl;
+    b_out_en <= '0' after Tpd_clk_ctrl;
+    temp_latch_en <= '0' after Tpd_clk_ctrl;
+    temp_out_en1 <= '0' after Tpd_clk_ctrl;
+    temp_out_en2 <= '0' after Tpd_clk_ctrl;
+    iar_latch_en <= '0' after Tpd_clk_ctrl;
+    iar_out_en1 <= '0' after Tpd_clk_ctrl;
+    iar_out_en2 <= '0' after Tpd_clk_ctrl;
+    pc_latch_en <= '0' after Tpd_clk_ctrl;
+    pc_out_en1 <= '0' after Tpd_clk_ctrl;
+    pc_out_en2 <= '0' after Tpd_clk_ctrl;
+    mar_latch_en <= '0' after Tpd_clk_ctrl;
+    mar_out_en1 <= '0' after Tpd_clk_ctrl;
+    mar_out_en2 <= '0' after Tpd_clk_ctrl;
+    mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
+    mdr_latch_en <= '0' after Tpd_clk_ctrl;
+    mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+    mdr_out_en2 <= '0' after Tpd_clk_ctrl;
+    mdr_out_en3 <= '0' after Tpd_clk_ctrl;
+    mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+    ir_latch_en <= '0' after Tpd_clk_ctrl;
+    ir_immed1_size_26 <= '0' after Tpd_clk_ctrl;
+    ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+    ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+    ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+    ir_immed1_en <= '0' after Tpd_clk_ctrl;
+    ir_immed2_en <= '0' after Tpd_clk_ctrl;
+    const1 <= disabled_dlx_word after Tpd_clk_const;
+    const2 <= disabled_dlx_word after Tpd_clk_const;
+
+    instr_count := 0;
+
+    wait on phi2 until falling_edge(phi2) and To_bit(reset) = '0';
+
+    ----------------------------------------------------------------
+    -- control loop
+    ----------------------------------------------------------------
+    loop
+      exit when To_bit(reset) = '1';
+
+      ----------------------------------------------------------------
+      -- fetch next instruction (IF)
+      ----------------------------------------------------------------
+      wait until rising_edge(phi1);
+
+      instr_count := instr_count + 1;
+      if debug = msg_every_100_instructions and instr_count mod 100 = 0 then
+        report "instruction count = " & natural'image(instr_count);
+      end if;
+
+      if debug >= msg_each_instruction then
+        report "fetching instruction";
+      end if;
+
+      bus_instruction_fetch;
+      exit when To_bit(reset) = '1';
+      current_instruction_bv := To_bitvector(current_instruction);
+
+      if debug >= trace_each_instruction then
+        disassemble(current_instruction_bv, disassembled_instr, disassembled_instr_len);
+        report disassembled_instr(1 to disassembled_instr_len);
+      end if;
+
+      ----------------------------------------------------------------
+      -- instruction decode, source register read and PC increment (ID)
+      ----------------------------------------------------------------
+      wait until rising_edge(phi1);
+
+      if debug = trace_each_step then
+        report "decode, source register read and PC increment";
+      end if;
+
+      reg_s1_addr <= IR_rs1 after Tpd_clk_ctrl;
+      reg_s2_addr <= IR_rs2 after Tpd_clk_ctrl;
+      a_latch_en <= '1' after Tpd_clk_ctrl;
+      b_latch_en <= '1' after Tpd_clk_ctrl;
+
+      pc_out_en1 <= '1' after Tpd_clk_ctrl;
+      const2 <= X"0000_0004" after Tpd_clk_const;
+      alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+      alu_function <= alu_addu after Tpd_clk_ctrl;
+
+      wait until falling_edge(phi1);
+      a_latch_en <= '0' after Tpd_clk_ctrl;
+      b_latch_en <= '0' after Tpd_clk_ctrl;
+      alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+      pc_out_en1 <= '0' after Tpd_clk_ctrl;
+      const2 <= disabled_dlx_word after Tpd_clk_const;
+
+      wait until rising_edge(phi2);
+      pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+      wait until falling_edge(phi2);
+      pc_latch_en <= '0' after Tpd_clk_ctrl;
+
+      ----------------------------------------------------------------
+      -- execute instruction, (EX, MEM, WB)
+      ----------------------------------------------------------------
+      if debug = trace_each_step then
+        report "execute";
+      end if;
+
+      case IR_opcode is
+        when op_special =>
+          execute_op_special;
+        when op_fparith => 
+          execute_op_fparith;
+        when op_j =>
+          do_MEM_jump;
+        when op_jal =>
+          do_EX_link;
+          do_MEM_jump;
+          do_WB(To_X01(natural_to_bv(link_reg, 5)));
+        when op_jr =>
+          do_MEM_jump_reg;
+        when op_jalr =>
+          do_EX_link;
+          do_MEM_jump_reg;
+          do_WB(To_X01(natural_to_bv(link_reg, 5)));
+        when op_beqz | op_bnez => 
+          do_EX_branch;
+          if branch_taken then
+            do_MEM_branch;
+          end if;
+        when op_addi | op_subi | op_addui | op_subui 
+          | op_slli | op_srli | op_srai
+          | op_andi | op_ori | op_xori =>
+          do_EX_arith_logic_immed;
+          do_WB(IR_Itype_rd);
+        when op_lhi =>
+          do_EX_lhi;
+          do_WB(IR_Itype_rd);
+        when op_sequi | op_sneui | op_sltui
+          | op_sgtui | op_sleui | op_sgeui => 
+          do_EX_set_unsigned(immed => true);
+          do_WB(IR_Itype_rd);
+        when op_seqi | op_snei | op_slti
+          | op_sgti | op_slei | op_sgei => 
+          do_EX_set_signed(immed => true);
+          do_WB(IR_Itype_rd);
+        when op_trap =>
+          report "TRAP instruction encountered, execution halted"
+            severity note;
+          wait until rising_edge(phi1);
+          halt <= '1' after Tpd_clk_ctrl;
+          wait until reset = '1';
+          exit;
+        when op_lb | op_lh | op_lw | op_lbu | op_lhu => 
+          do_EX_load_store;
+          do_MEM_load;
+          exit when reset = '1';
+          do_WB(IR_Itype_rd);
+        when op_sb | op_sh | op_sw =>
+          do_EX_load_store;
+          do_MEM_store;
+          exit when reset = '1';
+        when op_rfe | op_bfpt | op_bfpf | op_lf | op_ld | op_sf | op_sd =>
+          report opcode_names(bv_to_natural(IR_opcode))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined instruction" severity error;
+      end case;
+
+      -- overflow and divide-by-zero exception handing
+      -- (not implemented)
+
+      if debug = trace_each_step then
+        report "end of execution";
+      end if;
+
+    end loop;
+    -- loop is only exited when reset active:
+    -- process interpreter starts again from beginning
+  end process sequencer;
+
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd
new file mode 100644
index 0000000..c1bcb5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd
@@ -0,0 +1,476 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlx-b.vhd,v 1.4 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.4 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+library work;
+use work.dlx_instr.all;
+
+architecture behavior of dlx is
+begin
+
+  interpreter : process
+    is
+
+    type reg_array is array (reg_index) of dlx_bv_word;
+    variable reg : reg_array;
+    variable fp_reg : reg_array;
+
+    variable PC : dlx_bv_word;
+    constant PC_incr : dlx_bv_word := X"0000_0004";
+
+    variable IR : dlx_bv_word;
+    alias IR_opcode : dlx_opcode is IR(0 to 5);
+    alias IR_sp_func : dlx_sp_func is IR(26 to 31);
+    alias IR_fp_func : dlx_fp_func is IR(27 to 31);
+    alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
+    alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
+    alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
+    alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
+    alias IR_immed16 : dlx_immed16 is IR(16 to 31);
+    alias IR_immed26 : dlx_immed26 is IR(6 to 31);
+
+    variable disassembled_instr : string(1 to 40);
+    variable disassembled_instr_len : positive;
+
+    variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
+
+    variable mem_addr_reg : dlx_bv_address;
+    variable mem_data_reg : dlx_bv_word;
+
+    variable overflow : boolean;
+
+    -- lookup table for result of set instructions
+    type set_result_table is array (boolean) of dlx_bv_word;
+    constant set_if : set_result_table := ( false => X"0000_0000",
+                                            true => X"0000_0001" );
+    variable instr_count : natural;
+
+
+    -- local procedures for use within the interpreter
+
+
+    procedure bus_read ( address : in dlx_bv_address;
+                         data_width : in dlx_mem_width;
+                         instr_fetch : in std_logic;
+                         data : out dlx_bv_word ) is
+
+    begin
+      wait until rising_edge(phi1);
+      if To_bit(reset) = '1' then
+        return;
+      end if;
+      a <= To_X01(address) after Tpd_clk_out;
+      width <= data_width after Tpd_clk_out;
+      ifetch <= instr_fetch after Tpd_clk_out;
+      mem_enable <= '1' after Tpd_clk_out;
+      loop 
+        wait until falling_edge(phi2);
+        if To_bit(reset) = '1' then
+          return;
+        end if;
+        exit when To_bit(ready) = '1';
+      end loop;
+      assert not Is_X(d) report "Bus read data contains unknown bits";
+      data := To_bitvector(d);
+      mem_enable <= '0' after Tpd_clk_out;
+    end procedure bus_read;
+
+
+    procedure bus_write ( address : in dlx_bv_address;
+                          data_width : in dlx_mem_width;
+                          data : in dlx_bv_word ) is
+
+    begin
+      wait until rising_edge(phi1);
+      if To_bit(reset) = '1' then
+        return;
+      end if;
+      a <= To_X01(address) after Tpd_clk_out;
+      ifetch <= '0' after Tpd_clk_out;
+      width <= data_width after Tpd_clk_out;
+      d <= To_X01Z(data) after Tpd_clk_out;
+      write_enable <= '1' after Tpd_clk_out;
+      mem_enable <= '1' after Tpd_clk_out;
+      loop 
+        wait until falling_edge(phi2);
+        if To_bit(reset) = '1' then
+          return;
+        end if;
+        exit when To_bit(ready) = '1';
+      end loop;
+      d <= disabled_dlx_word after Tpd_clk_out;
+      write_enable <= '0' after Tpd_clk_out;
+      mem_enable <= '0' after Tpd_clk_out;
+    end procedure bus_write;
+
+
+    procedure execute_op_special is
+    begin
+      case IR_sp_func is
+        when sp_func_nop =>
+          null;
+        when sp_func_add => 
+          bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_addu => 
+          bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_sub => 
+          bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_subu => 
+          bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_sll => 
+          reg(Rtype_rd) := reg(rs1) sll bv_to_natural(reg(rs2)(27 to 31));
+        when sp_func_srl => 
+          reg(Rtype_rd) := reg(rs1) srl bv_to_natural(reg(rs2)(27 to 31));
+        when sp_func_sra => 
+          reg(Rtype_rd) := reg(rs1) sra bv_to_natural(reg(rs2)(27 to 31));
+        when sp_func_and => 
+          reg(Rtype_rd) := reg(rs1) and reg(rs2);
+        when sp_func_or => 
+          reg(Rtype_rd) := reg(rs1) or reg(rs2);
+        when sp_func_xor => 
+          reg(Rtype_rd) := reg(rs1) xor reg(rs2);
+        when sp_func_sequ =>
+          reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
+        when sp_func_sneu => 
+          reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
+        when sp_func_sltu => 
+          reg(Rtype_rd) := set_if( reg(rs1) < reg(rs2) );
+        when sp_func_sgtu => 
+          reg(Rtype_rd) := set_if( reg(rs1) > reg(rs2) );
+        when sp_func_sleu => 
+          reg(Rtype_rd) := set_if( reg(rs1) <= reg(rs2) );
+        when sp_func_sgeu => 
+          reg(Rtype_rd) := set_if( reg(rs1) >= reg(rs2) );
+        when sp_func_seq => 
+          reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
+        when sp_func_sne => 
+          reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
+        when sp_func_slt => 
+          reg(Rtype_rd) := set_if( bv_lt(reg(rs1), reg(rs2)) );
+        when sp_func_sgt => 
+          reg(Rtype_rd) := set_if( bv_gt(reg(rs1), reg(rs2)) );
+        when sp_func_sle => 
+          reg(Rtype_rd) := set_if( bv_le(reg(rs1), reg(rs2)) );
+        when sp_func_sge => 
+          reg(Rtype_rd) := set_if( bv_ge(reg(rs1), reg(rs2)) );
+        when sp_func_movi2s | sp_func_movs2i
+          | sp_func_movf | sp_func_movd
+          | sp_func_movfp2i | sp_func_movi2fp => 
+          report sp_func_names(bv_to_natural(IR_sp_func))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined special instruction function" severity error;
+      end case;
+    end procedure execute_op_special;
+
+
+    procedure execute_op_fparith is
+    begin
+      case IR_fp_func is
+        when fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu
+          | fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
+          | fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
+          | fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f
+          | fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d
+          | fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf
+          | fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned
+          | fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
+          report fp_func_names(bv_to_natural(IR_fp_func))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined floating point instruction function" severity error;
+      end case;
+    end procedure execute_op_fparith;
+
+
+    procedure execute_load ( data_width : dlx_mem_width; unsigned : boolean ) is
+
+      variable temp : dlx_bv_word;
+
+      -- type for least-significant two bits of address
+      subtype ls_2_addr_bits is bit_vector(1 downto 0);
+
+    begin
+      mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
+      bus_read(mem_addr_reg, data_width, '0', mem_data_reg);
+      if To_bit(reset) = '1' then
+        return;
+      end if;
+      case data_width is
+        when dlx_mem_width_byte =>
+          case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
+            when B"00" =>
+              temp(0 to 7) := mem_data_reg(0 to 7);
+            when B"01" =>
+              temp(0 to 7) := mem_data_reg(8 to 15);
+            when B"10" =>
+              temp(0 to 7) := mem_data_reg(16 to 23);
+            when B"11" =>
+              temp(0 to 7) := mem_data_reg(24 to 31);
+          end case;
+          if unsigned then
+            reg(Itype_rd) := bv_zext(temp(0 to 7), 32);
+          else
+            reg(Itype_rd) := bv_sext(temp(0 to 7), 32);
+          end if;
+        when dlx_mem_width_halfword =>
+          if mem_addr_reg(1) = '0' then
+            temp(0 to 15) := mem_data_reg(0 to 15);
+          else
+            temp(0 to 15) := mem_data_reg(16 to 31);
+          end if;
+          if unsigned then
+            reg(Itype_rd) := bv_zext(temp(0 to 15), 32);
+          else
+            reg(Itype_rd) := bv_sext(temp(0 to 15), 32);
+          end if;
+        when dlx_mem_width_word =>
+          reg(Itype_rd) := mem_data_reg;
+        when others =>
+          null;
+      end case;
+    end procedure execute_load;
+
+
+    procedure execute_store ( data_width : dlx_mem_width ) is
+
+      variable temp : dlx_bv_word;
+
+      -- type for least-significant two bits of address
+      subtype ls_2_addr_bits is bit_vector(1 downto 0);
+
+    begin
+      mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
+      mem_data_reg := X"0000_0000";
+      case data_width is
+        when dlx_mem_width_byte =>
+          case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
+            when B"00" =>
+              mem_data_reg(0 to 7) := reg(Itype_rd)(0 to 7);
+            when B"01" =>
+              mem_data_reg(8 to 15) := reg(Itype_rd)(0 to 7);
+            when B"10" =>
+              mem_data_reg(16 to 23) := reg(Itype_rd)(0 to 7);
+            when B"11" =>
+              mem_data_reg(24 to 31) := reg(Itype_rd)(0 to 7);
+          end case;
+        when dlx_mem_width_halfword =>
+          if mem_addr_reg(1) = '0' then
+            mem_data_reg(0 to 15) := reg(Itype_rd)(0 to 15);
+          else
+            mem_data_reg(16 to 31) := reg(Itype_rd)(0 to 15);
+          end if;
+        when dlx_mem_width_word =>
+          mem_data_reg := reg(Itype_rd);
+        when others =>
+          null;
+      end case;
+      bus_write(mem_addr_reg, data_width, mem_data_reg);
+    end procedure execute_store;
+
+
+  begin -- interpreter
+
+    -- reset the processor
+    d <= disabled_dlx_word;
+    halt <= '0';
+    write_enable <= '0';
+    mem_enable <= '0';
+    reg(0) := X"0000_0000";
+    PC := X"0000_0000";
+    instr_count := 0;
+    wait on phi2 until falling_edge(phi2) and To_bit(reset) = '0';
+
+    -- fetch-decode-execute loop
+    while To_bit(reset) /= '1' loop
+      -- fetch next instruction
+      instr_count := instr_count + 1;
+      if debug = msg_every_100_instructions and instr_count mod 100 = 0 then
+        report "instruction count = " & natural'image(instr_count);
+      end if;
+
+      if debug >= msg_each_instruction then
+        report "fetching instruction";
+      end if;
+
+      bus_read( address => PC, data_width => dlx_mem_width_word,
+                instr_fetch => '1', data => IR );
+      exit when To_bit(reset) = '1';
+
+      if debug >= trace_each_instruction then
+	disassemble(IR, disassembled_instr, disassembled_instr_len);
+        report disassembled_instr(1 to disassembled_instr_len);
+      end if;
+
+      wait until rising_edge(phi1);
+
+      -- increment the PC to point to the following instruction
+      if debug = trace_each_step then
+        report "incrementing PC";
+      end if;
+
+      PC := bv_addu(PC, PC_incr);
+
+      -- decode the instruction
+      if debug = trace_each_step then
+        report "decoding instruction";
+      end if;
+
+      rs1 := bv_to_natural(IR_rs1);
+      rs2 := bv_to_natural(IR_rs2);
+      Itype_rd := bv_to_natural(IR_Itype_rd);
+      Rtype_rd := bv_to_natural(IR_Rtype_rd);
+
+      -- execute the instruction
+      if debug = trace_each_step then
+        report "executing instruction";
+      end if;
+
+      overflow := false;
+
+      case IR_opcode is
+        when op_special =>
+          execute_op_special;
+        when op_fparith =>
+          execute_op_fparith;
+        when op_j  => 
+          PC := PC + bv_sext(IR_immed26, 32);
+        when op_jal => 
+          reg(link_reg) := PC;
+          PC := PC + bv_sext(IR_immed26, 32);
+        when op_jr => 
+          PC := reg(rs1);
+        when op_jalr => 
+          reg(link_reg) := PC;
+          PC := reg(rs1);
+        when op_beqz => 
+          if reg(rs1) = X"0000_0000" then
+            PC := PC + bv_sext(IR_immed16, 32);
+          end if;
+        when op_bnez => 
+          if reg(rs1) /= X"0000_0000" then
+            PC := PC + bv_sext(IR_immed16, 32);
+          end if;
+        when op_addi =>
+          bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_addui => 
+          bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_subi => 
+          bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_subui => 
+          bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_slli => 
+          reg(Itype_rd) := reg(rs1) sll bv_to_natural(IR_immed16(11 to 15));
+        when op_srli =>
+          reg(Itype_rd) := reg(rs1) srl bv_to_natural(IR_immed16(11 to 15));
+        when op_srai => 
+          reg(Itype_rd) := reg(rs1) sra bv_to_natural(IR_immed16(11 to 15));
+        when op_andi => 
+          reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
+        when op_ori => 
+          reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
+        when op_xori => 
+          reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
+        when op_lhi => 
+          reg(Itype_rd) := IR_immed16 & X"0000";
+        when op_sequi => 
+          reg(Itype_rd) := set_if( reg(rs1) = bv_zext(IR_immed16, 32) );
+        when op_sneui => 
+          reg(Itype_rd) := set_if( reg(rs1) /= bv_zext(IR_immed16, 32) );
+        when op_sltui => 
+          reg(Itype_rd) := set_if( reg(rs1) < bv_zext(IR_immed16, 32) );
+        when op_sgtui => 
+          reg(Itype_rd) := set_if( reg(rs1) > bv_zext(IR_immed16, 32) );
+        when op_sleui => 
+          reg(Itype_rd) := set_if( reg(rs1) <= bv_zext(IR_immed16, 32) );
+        when op_sgeui => 
+          reg(Itype_rd) := set_if( reg(rs1) >= bv_zext(IR_immed16, 32) );
+        when op_seqi => 
+          reg(Itype_rd) := set_if( reg(rs1) = bv_sext(IR_immed16, 32) );
+        when op_snei => 
+          reg(Itype_rd) := set_if( reg(rs1) /= bv_sext(IR_immed16, 32) );
+        when op_slti => 
+          reg(Itype_rd) := set_if( bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_sgti => 
+          reg(Itype_rd) := set_if( bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_slei => 
+          reg(Itype_rd) := set_if( bv_le(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_sgei => 
+          reg(Itype_rd) := set_if( bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_trap =>
+          report "TRAP instruction encountered, execution halted" severity note;
+          halt <= '1' after Tpd_clk_out;
+          wait until To_bit(reset) = '1';
+          exit;
+        when op_lb =>
+          execute_load(data_width => dlx_mem_width_byte, unsigned => false);
+          exit when To_bit(reset) = '1';
+        when op_lh => 
+          execute_load(data_width => dlx_mem_width_halfword, unsigned => false);
+          exit when To_bit(reset) = '1';
+        when op_lw => 
+          execute_load(data_width => dlx_mem_width_word, unsigned => false);
+          exit when To_bit(reset) = '1';
+        when op_lbu => 
+          execute_load(data_width => dlx_mem_width_byte, unsigned => true);
+          exit when To_bit(reset) = '1';
+        when op_lhu => 
+          execute_load(data_width => dlx_mem_width_halfword, unsigned => true);
+          exit when To_bit(reset) = '1';
+        when op_sb => 
+          execute_store ( data_width => dlx_mem_width_byte );
+          exit when To_bit(reset) = '1';
+        when op_sh => 
+          execute_store ( data_width => dlx_mem_width_halfword );
+          exit when To_bit(reset) = '1';
+        when op_sw => 
+          execute_store ( data_width => dlx_mem_width_word );
+          exit when To_bit(reset) = '1';
+        when op_rfe | op_bfpt | op_bfpf | op_lf | op_ld | op_sf | op_sd => 
+          report opcode_names(bv_to_natural(IR_opcode))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined instruction" severity error;
+      end case;
+
+      -- fix up R0 in case it was overwritten
+      reg(0) := X"0000_0000";
+
+      -- overflow and divide-by-zero exception handing
+      -- (not implemented)
+
+      if debug = trace_each_step then
+        report "end of execution";
+      end if;
+
+    end loop;
+    -- loop is only exited when reset active:
+    -- process interpreter starts again from beginning
+  end process interpreter;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd
new file mode 100644
index 0000000..27b6ae2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd
@@ -0,0 +1,281 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+use work.alu_types.all,
+  work.reg_file_types.all;
+
+architecture rtl of dlx is
+
+  component alu is
+                  port ( s1 : in dlx_word;
+                         s2 : in dlx_word;
+                         result : out dlx_word;
+                         func : in alu_func;
+                         zero, negative, overflow : out std_logic );
+  end component alu;
+
+  component reg_file is
+                       port ( a1 : in reg_file_addr;
+                              q1 : out dlx_word;
+                              a2 : in reg_file_addr;
+                              q2 : out dlx_word;
+                              a3 : in reg_file_addr;
+                              d3 : in dlx_word;
+                              write_en : in std_logic );
+  end component reg_file;
+
+  component latch is
+                    port ( d : in dlx_word;
+                           q : out dlx_word;
+                           latch_en : in std_logic );
+  end component latch;
+
+  component ir_extender is
+                          port ( d : in dlx_word;
+                                 q : out dlx_word;
+                                 immed_size_26 : in std_logic;
+                                 immed_unsigned : in std_logic;
+                                 immed_en : in std_logic );
+  end component ir_extender;
+
+  component reg_multiple_out is
+                               generic ( num_outputs : positive );
+                             port ( d : in dlx_word;
+                                    q : out dlx_word_array(1 to num_outputs);
+                                    latch_en : in std_logic;
+                                    out_en : in std_logic_vector(1 to num_outputs) );
+  end component reg_multiple_out;
+
+  component reg_multiple_plus_one_out is
+                                        generic ( num_outputs : positive );
+                                      port ( d : in dlx_word;
+                                             q0 : out dlx_word;
+                                             q : out dlx_word_array(1 to num_outputs);
+                                             latch_en : in std_logic;
+                                             out_en : in std_logic_vector(1 to num_outputs) );
+  end component reg_multiple_plus_one_out;
+
+  component reg_multiple_plus_one_out_reset is
+                                              generic ( num_outputs : positive );
+                                            port ( d : in dlx_word;
+                                                   q0 : out dlx_word;
+                                                   q : out dlx_word_array(1 to num_outputs);
+                                                   latch_en : in std_logic;
+                                                   out_en : in std_logic_vector(1 to num_outputs);
+                                                   reset : in std_logic );
+  end component reg_multiple_plus_one_out_reset;
+
+  component mux2 is
+                   port ( i0, i1 : in dlx_word;
+                          y : out dlx_word;
+                          sel : in std_logic);
+  end component mux2;
+
+  component controller is
+                         port ( phi1, phi2 : in std_logic;
+                                reset : in std_logic;
+                                halt : out std_logic;
+                                width : out dlx_mem_width;
+                                write_enable : out std_logic;
+                                mem_enable : out std_logic;
+                                ifetch : out std_logic;
+                                ready : in std_logic;
+                                alu_in_latch_en : out std_logic;
+                                alu_function : out alu_func;
+                                alu_zero, alu_negative, alu_overflow : in std_logic;
+                                reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
+                                reg_write : out std_logic;
+                                c_latch_en : out std_logic;
+                                a_latch_en, a_out_en : out std_logic;
+                                b_latch_en, b_out_en : out std_logic;
+                                temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
+                                iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
+                                pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
+                                mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
+                                mem_addr_mux_sel : out std_logic;
+                                mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
+                                mdr_mux_sel : out std_logic;
+                                ir_latch_en : out std_logic;
+                                ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
+                                ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
+                                ir_immed1_en, ir_immed2_en : out std_logic;
+                                current_instruction : in dlx_word;
+                                mem_addr : std_logic_vector(1 downto 0);
+                                const1, const2 : out dlx_word );
+  end component controller;
+
+
+  signal s1_bus, s2_bus : dlx_word;
+  signal dest_bus : dlx_word;
+  signal alu_in1, alu_in2 : dlx_word;
+  signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
+  signal mdr_in : dlx_word;
+  signal current_instruction : dlx_word;
+  signal pc_to_mem : dlx_address;
+  signal mar_to_mem : dlx_address;
+
+  signal alu_in_latch_en : std_logic;
+  signal alu_function : alu_func;
+  signal alu_zero, alu_negative, alu_overflow : std_logic;
+  signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr;
+  signal reg_write : std_logic;
+  signal a_out_en, a_latch_en : std_logic;
+  signal b_out_en, b_latch_en : std_logic;
+  signal c_latch_en : std_logic;
+  signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic;
+  signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic;
+  signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic;
+  signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic;
+  signal mem_addr_mux_sel : std_logic;
+  signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic;
+  signal mdr_mux_sel : std_logic;
+  signal ir_latch_en : std_logic;
+  signal ir_immed1_size_26, ir_immed2_size_26 : std_logic;
+  signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic;
+  signal ir_immed1_en, ir_immed2_en : std_logic;
+
+begin
+
+  alu_s1_reg : component latch
+    port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en );
+
+  alu_s2_reg : component latch
+    port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en );
+
+  the_alu : component alu
+    port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus,
+               func => alu_function,
+               zero => alu_zero, negative => alu_negative, overflow => alu_overflow );
+
+  the_reg_file : component reg_file
+    port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
+               a2 => reg_s2_addr, q2 => reg_file_out2,
+               a3 => reg_dest_addr, d3 => reg_file_in,
+               write_en => reg_write );
+
+  c_reg : component latch
+    port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en );
+
+  a_reg : component reg_multiple_out
+    generic map ( num_outputs => 1 )
+    port map ( d => reg_file_out1, q(1) => s1_bus,
+               latch_en => a_latch_en, out_en(1) => a_out_en );
+
+  b_reg : component reg_multiple_out
+    generic map ( num_outputs => 1 )
+    port map ( d => reg_file_out2, q(1) => s2_bus,
+               latch_en => b_latch_en, out_en(1) => b_out_en );
+
+  temp_reg : component reg_multiple_out
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
+               latch_en => temp_latch_en,
+               out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );
+
+  iar_reg : component reg_multiple_out
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
+               latch_en => iar_latch_en,
+               out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 );
+
+  pc_reg : component reg_multiple_plus_one_out_reset
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
+               latch_en => pc_latch_en,
+               out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
+	       reset => reset );
+
+  mar_reg : component reg_multiple_plus_one_out
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
+               latch_en => mar_latch_en,
+               out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );
+
+  mem_addr_mux : component mux2
+    port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
+               sel => mem_addr_mux_sel );
+
+  mdr_reg : component reg_multiple_out
+    generic map ( num_outputs => 3 )
+    port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
+               latch_en => mdr_latch_en,
+               out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
+	       out_en(3) => mdr_out_en3 );
+
+  mdr_mux : component mux2
+    port map ( i0 => dest_bus, i1 => d, y => mdr_in,
+               sel => mdr_mux_sel );
+
+  instr_reg : component latch
+    port map ( d => d, q => current_instruction,
+               latch_en => ir_latch_en );
+
+  ir_extender1 : component ir_extender
+    port map ( d => current_instruction, q => s1_bus,
+               immed_size_26 => ir_immed1_size_26,
+	       immed_unsigned => ir_immed1_unsigned,
+               immed_en => ir_immed1_en );
+
+  ir_extender2 : component ir_extender
+    port map ( d => current_instruction, q => s2_bus,
+               immed_size_26 => ir_immed2_size_26,
+	       immed_unsigned => ir_immed2_unsigned,
+               immed_en => ir_immed2_en );
+
+  the_controller : component controller
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt, 
+      	       width => width, write_enable => write_enable, mem_enable => mem_enable,
+	       ifetch => ifetch, ready => ready, 
+               alu_in_latch_en => alu_in_latch_en, alu_function => alu_function,
+	       alu_zero => alu_zero, alu_negative => alu_negative,
+	       alu_overflow => alu_overflow,
+               reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
+	       reg_dest_addr => reg_dest_addr, reg_write => reg_write, 
+               c_latch_en => c_latch_en,
+	       a_latch_en => a_latch_en, a_out_en => a_out_en,
+	       b_latch_en => b_latch_en, b_out_en =>  b_out_en, 
+               temp_latch_en => temp_latch_en,
+	       temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2, 
+               iar_latch_en => iar_latch_en,
+	       iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2, 
+               pc_latch_en => pc_latch_en,
+	       pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2, 
+               mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en,
+	       mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
+               mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en,
+	       mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2, 
+	       mdr_out_en3 => mdr_out_en3, 
+               ir_latch_en => ir_latch_en,
+	       ir_immed1_size_26 => ir_immed1_size_26,
+	       ir_immed2_size_26 => ir_immed2_size_26,
+	       ir_immed1_unsigned => ir_immed1_unsigned,
+	       ir_immed2_unsigned => ir_immed2_unsigned,
+	       ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,  
+               current_instruction => current_instruction,
+	       mem_addr => mar_to_mem(1 downto 0),
+	       const1 => s1_bus, const2 => s2_bus );
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx.vhd
new file mode 100644
index 0000000..a261921
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlx.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+               use work.dlx_types.all;
+
+               entity dlx is
+
+                 generic ( Tpd_clk_out : delay_length;
+                           debug : dlx_debug_control := none );
+
+                 port ( phi1, phi2 : in std_logic;
+                        reset : in std_logic;
+                        halt : out std_logic;
+                        a : out dlx_address;
+                        d : inout dlx_word;
+                        width : out dlx_mem_width;
+                        write_enable : out std_logic;
+                        ifetch : out std_logic;
+                        mem_enable : out std_logic;
+                        ready : in std_logic );
+
+               end entity dlx;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd
new file mode 100644
index 0000000..3194fad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd
@@ -0,0 +1,320 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxi-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+package body dlx_instr is
+
+  use bv_utilities.bv_arithmetic.all;
+
+  constant opcode_names : opcode_name_array
+    := ( "SPECIAL ",   "FPARITH ",   "J       ",   "JAL     ",
+         "BEQZ    ",   "BNEZ    ",   "BFPT    ",   "BFPF    ",
+         "ADDI    ",    "ADDUI   ",   "SUBI    ",   "SUBUI   ",
+         "ANDI    ",   "ORI     ",   "XORI    ",   "LHI     ",
+         "RFE     ",   "TRAP    ",   "JR      ",   "JALR    ",
+         "SLLI    ",   "UNDEF_15",   "SRLI    ",   "SRAI    ",
+         "SEQI    ",   "SNEI    ",   "SLTI    ",   "SGTI    ",
+         "SLEI    ",   "SGEI    ",   "UNDEF_1E",   "UNDEF_1F",
+         "LB      ",   "LH      ",   "UNDEF_22",   "LW      ",
+         "LBU     ",   "LHU     ",   "LF      ",   "LD      ",
+         "SB      ",   "SH      ",   "UNDEF_2A",   "SW      ",
+         "UNDEF_2C",   "UNDEF_2D",   "SF      ",   "SD      ",
+         "SEQUI   ",   "SNEUI   ",   "SLTUI   ",   "SGTUI   ",
+         "SLEUI   ",   "SGEUI   ",   "UNDEF_36",   "UNDEF_37",
+         "UNDEF_38",   "UNDEF_39",   "UNDEF_3A",   "UNDEF_3B",
+         "UNDEF_3C",   "UNDEF_3D",   "UNDEF_3E",   "UNDEF_3F" );
+
+  constant sp_func_names : sp_func_name_array
+    := ( "NOP     ",   "UNDEF_01",   "UNDEF_02",   "UNDEF_03",
+         "SLL     ",   "UNDEF_05",   "SRL     ",   "SRA     ",
+         "UNDEF_08",   "UNDEF_09",   "UNDEF_0A",   "UNDEF_0B",
+         "UNDEF_0C",   "UNDEF_0D",   "UNDEF_0E",   "UNDEF_0F",
+         "SEQU    ",   "SNEU    ",   "SLTU    ",   "SGTU    ",
+         "SLEU    ",   "SGEU    ",   "UNDEF_16",   "UNDEF_17",
+         "UNDEF_18",   "UNDEF_19",   "UNDEF_1A",   "UNDEF_1B",
+         "UNDEF_1C",   "UNDEF_1D",   "UNDEF_1E",   "UNDEF_1F",
+         "ADD     ",   "ADDU    ",   "SUB     ",   "SUBU    ",
+         "AND     ",   "OR      ",   "XOR     ",   "UNDEF_27",
+         "SEQ     ",   "SNE     ",   "SLT     ",   "SGT     ",
+         "SLE     ",   "SGE     ",   "UNDEF_2E",   "UNDEF_2F",
+         "MOVI2S  ",   "MOVS2I  ",   "MOVF    ",   "MOVD    ",
+         "MOVFP2I ",   "MOVI2FP ",   "UNDEF_36",   "UNDEF_37",
+         "UNDEF_38",   "UNDEF_39",   "UNDEF_3A",   "UNDEF_3B",
+         "UNDEF_3C",   "UNDEF_3D",   "UNDEF_3E",   "UNDEF_3F" );
+
+  constant fp_func_names : fp_func_name_array
+    := ( "ADDF    ",   "SUBF    ",   "MULTF   ",   "DIVF    ",
+         "ADDD    ",   "SUBD    ",   "MULTD   ",   "DIVD    ",
+         "CVTF2D  ",   "CVTF2I  ",   "CVTD2F  ",   "CVTD2I  ",
+         "CVTI2F  ",   "CVTI2D  ",   "MULT    ",   "DIV     ",
+         "EQF     ",   "NEF     ",   "LTF     ",   "GTF     ",
+         "LEF     ",   "GEF     ",   "MULTU   ",   "DIVU    ",
+         "EQD     ",   "NED     ",   "LTD     ",   "GTD     ",
+         "LED     ",   "GED     ",   "UNDEF_1E",   "UNDEF_1F" );
+
+
+  procedure disassemble ( instr : dlx_bv_word;
+			  disassembled_instr : out string;  len : out positive ) is
+
+    alias norm_disassembled_instr : string(1 to disassembled_instr'length)
+      is disassembled_instr;
+
+    alias instr_opcode : dlx_opcode is instr(0 to 5);
+    alias instr_sp_func : dlx_sp_func is instr(26 to 31);
+    alias instr_fp_func : dlx_fp_func is instr(27 to 31);
+    alias instr_rs1 : dlx_reg_addr is instr(6 to 10);
+    alias instr_rs2 : dlx_reg_addr is instr(11 to 15);
+    alias instr_Itype_rd : dlx_reg_addr is instr(11 to 15);
+    alias instr_Rtype_rd : dlx_reg_addr is instr(16 to 20);
+    alias instr_immed16 : dlx_immed16 is instr(16 to 31);
+    alias instr_immed26 : dlx_immed26 is instr(6 to 31);
+
+    variable instr_opcode_num : dlx_opcode_num;
+    variable instr_sp_func_num : dlx_sp_func_num;
+    variable instr_fp_func_num : dlx_fp_func_num;
+    variable rs1 : reg_index;
+    variable rs2 : reg_index;
+    variable Itype_rd : reg_index;
+    variable Rtype_rd : reg_index;
+    variable result : string(1 to 40)	-- long enough for longest instruction
+		:= (others => ' ');
+    variable index : positive range 1 to 41 := 1;  -- position for next char in result
+
+    procedure disassemble_reg ( reg : reg_index;  reg_prefix : character ) is
+    begin
+      result(index) := reg_prefix;
+      index := index + 1;
+      if reg < 10 then
+        result(index to index) := integer'image(reg);
+        index := index + 1;
+      else
+        result(index to index + 1) := integer'image(reg);
+        index := index + 2;
+      end if;
+    end procedure disassemble_reg;
+
+    procedure disassemble_special_reg ( reg : reg_index ) is
+    begin
+      case reg is
+        when 0 =>
+          result(index to index + 2) := "IAR";
+          index := index + 3;
+        when 1 =>
+          result(index to index + 2) := "FSR";
+          index := index + 3;
+        when others =>
+          disassemble_reg(reg, 'S');
+      end case;
+    end procedure disassemble_special_reg;
+
+    procedure disassemble_integer ( int : integer ) is
+      constant int_image_length : natural := integer'image(int)'length;
+    begin
+      result(index to index + int_image_length - 1) := integer'image(int);
+      index := index + int_image_length;
+    end procedure disassemble_integer;
+
+  begin
+    instr_opcode_num := bv_to_natural(instr_opcode);
+    instr_sp_func_num := bv_to_natural(instr_sp_func);
+    instr_fp_func_num := bv_to_natural(instr_fp_func);
+    rs1 := bv_to_natural(instr_rs1);
+    rs2 := bv_to_natural(instr_rs2);
+    Itype_rd := bv_to_natural(instr_Itype_rd);
+    Rtype_rd := bv_to_natural(instr_Rtype_rd);
+    if (instr_opcode /= op_special) and (instr_opcode /= op_fparith) then
+      result(index to index + instr_name'length - 1) := opcode_names(instr_opcode_num);
+      index := index + instr_name'length + 1;  -- include space after opcode name
+    end if;
+    case instr_opcode is
+      when op_special =>
+	result(index to index + instr_name'length - 1) := sp_func_names(instr_sp_func_num);
+        index := index + instr_name'length + 1;  -- include space after function name
+        case instr_sp_func is
+          when sp_func_nop =>
+            null;
+          when sp_func_sll | sp_func_srl | sp_func_sra
+            | sp_func_sequ | sp_func_sneu | sp_func_sltu
+            | sp_func_sgtu | sp_func_sleu | sp_func_sgeu
+            | sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu
+            | sp_func_and | sp_func_or | sp_func_xor
+            | sp_func_seq | sp_func_sne | sp_func_slt
+            | sp_func_sgt | sp_func_sle | sp_func_sge =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs2, 'R');
+          when sp_func_movi2s =>
+	    disassemble_special_reg(Rtype_rd);
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+          when sp_func_movs2i =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_special_reg(rs1);
+          when sp_func_movf | sp_func_movd =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when sp_func_movfp2i =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when sp_func_movi2fp =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+          when others =>
+            null;
+        end case;
+      when op_fparith =>
+	result(index to index + instr_name'length - 1) := fp_func_names(instr_fp_func_num);
+        index := index + instr_name'length + 1;  -- include space after function name
+        case instr_fp_func is
+          when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
+            | fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
+            | fp_func_mult | fp_func_div | fp_func_multu | fp_func_divu =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs2, 'F');
+          when fp_func_cvtf2d | fp_func_cvtd2f =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when fp_func_cvtf2i | fp_func_cvtd2i =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when fp_func_cvti2f | fp_func_cvti2d =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+          when fp_func_eqf | fp_func_nef | fp_func_ltf
+            | fp_func_gtf | fp_func_lef | fp_func_gef
+            | fp_func_eqd | fp_func_ned | fp_func_ltd
+            | fp_func_gtd | fp_func_led | fp_func_ged =>
+	    disassemble_reg(rs1, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs2, 'F');
+          when others =>
+            null;
+        end case;
+      when op_j  | op_jal =>
+        disassemble_integer(bv_to_integer(instr_immed26));
+      when op_beqz | op_bnez =>
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_integer(instr_immed16));
+      when op_bfpt | op_bfpf =>
+	disassemble_integer(bv_to_integer(instr_immed16));
+      when op_slli | op_srli | op_srai =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_natural(instr_immed16(11 to 15)));
+      when op_addi | op_subi
+        | op_seqi | op_snei | op_slti | op_sgti | op_slei | op_sgei =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_integer(instr_immed16));
+      when op_addui | op_subui | op_andi | op_ori | op_xori
+        | op_sequi | op_sneui | op_sltui | op_sgtui | op_sleui | op_sgeui =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_natural(instr_immed16));
+      when op_lhi =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_natural(instr_immed16));
+      when op_rfe =>
+        null;
+      when op_trap =>
+	disassemble_integer(bv_to_natural(instr_immed26));
+      when op_jr | op_jalr =>
+	disassemble_reg(rs1, 'R');
+      when op_lb | op_lh | op_lw | op_lbu | op_lhu | op_lf | op_ld =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_integer(instr_immed16));
+        result(index) := '(';
+                           index := index + 1;
+                           disassemble_reg(rs1, 'R');
+                           result(index) := ')';
+	index := index + 1;
+      when op_sb | op_sh | op_sw | op_sf | op_sd =>
+	disassemble_integer(bv_to_integer(instr_immed16));
+        result(index) := '(';
+                           index := index + 1;
+                           disassemble_reg(rs1, 'R');
+                           result(index) := ')';
+	index := index + 1;
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(Itype_rd, 'R');
+      when others =>
+        null;  -- remaining opcodes have no operands to disassemble
+    end case;
+    if index > norm_disassembled_instr'length then
+      index := norm_disassembled_instr'length;  -- limit to out parameter length
+    else
+      index := index - 1;  -- index points to last result character
+    end if;
+    norm_disassembled_instr(1 to index) := result(1 to index);
+    len := index;
+  end procedure disassemble;
+
+end package body dlx_instr;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd
new file mode 100644
index 0000000..f4436fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd
@@ -0,0 +1,228 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxi.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.dlx_types.all;
+
+package dlx_instr is
+
+  subtype dlx_opcode is bit_vector(0 to 5);
+  subtype dlx_sp_func is bit_vector(0 to 5);
+  subtype dlx_fp_func is bit_vector(0 to 4);
+  subtype dlx_reg_addr is bit_vector(0 to 4);
+  subtype dlx_immed16 is bit_vector(0 to 15);
+  subtype dlx_immed26 is bit_vector(0 to 25);
+
+  constant op_special   : dlx_opcode := B"000000";
+  constant op_fparith   : dlx_opcode := B"000001";
+  constant op_j         : dlx_opcode := B"000010";
+  constant op_jal       : dlx_opcode := B"000011";
+  constant op_beqz      : dlx_opcode := B"000100";
+  constant op_bnez      : dlx_opcode := B"000101";
+  constant op_bfpt      : dlx_opcode := B"000110";
+  constant op_bfpf      : dlx_opcode := B"000111";
+  constant op_addi      : dlx_opcode := B"001000";
+  constant op_addui     : dlx_opcode := B"001001";
+  constant op_subi	: dlx_opcode := B"001010";
+  constant op_subui	: dlx_opcode := B"001011";
+  constant op_andi	: dlx_opcode := B"001100";
+  constant op_ori	: dlx_opcode := B"001101";
+  constant op_xori	: dlx_opcode := B"001110";
+  constant op_lhi	: dlx_opcode := B"001111";
+
+  constant op_rfe	: dlx_opcode := B"010000";
+  constant op_trap	: dlx_opcode := B"010001";
+  constant op_jr	: dlx_opcode := B"010010";
+  constant op_jalr	: dlx_opcode := B"010011";
+  constant op_slli	: dlx_opcode := B"010100";
+  constant op_undef_15	: dlx_opcode := B"010101";
+  constant op_srli	: dlx_opcode := B"010110";
+  constant op_srai	: dlx_opcode := B"010111";
+  constant op_seqi	: dlx_opcode := B"011000";
+  constant op_snei	: dlx_opcode := B"011001";
+  constant op_slti	: dlx_opcode := B"011010";
+  constant op_sgti	: dlx_opcode := B"011011";
+  constant op_slei	: dlx_opcode := B"011100";
+  constant op_sgei	: dlx_opcode := B"011101";
+  constant op_undef_1E	: dlx_opcode := B"011110";
+  constant op_undef_1F	: dlx_opcode := B"011111";
+
+  constant op_lb	: dlx_opcode := B"100000";
+  constant op_lh	: dlx_opcode := B"100001";
+  constant op_undef_22	: dlx_opcode := B"100010";
+  constant op_lw	: dlx_opcode := B"100011";
+  constant op_lbu	: dlx_opcode := B"100100";
+  constant op_lhu	: dlx_opcode := B"100101";
+  constant op_lf	: dlx_opcode := B"100110";
+  constant op_ld	: dlx_opcode := B"100111";
+  constant op_sb	: dlx_opcode := B"101000";
+  constant op_sh	: dlx_opcode := B"101001";
+  constant op_undef_2A	: dlx_opcode := B"101010";
+  constant op_sw	: dlx_opcode := B"101011";
+  constant op_undef_2C	: dlx_opcode := B"101100";
+  constant op_undef_2D	: dlx_opcode := B"101101";
+  constant op_sf	: dlx_opcode := B"101110";
+  constant op_sd	: dlx_opcode := B"101111";
+
+  constant op_sequi	: dlx_opcode := B"110000";
+  constant op_sneui	: dlx_opcode := B"110001";
+  constant op_sltui	: dlx_opcode := B"110010";
+  constant op_sgtui	: dlx_opcode := B"110011";
+  constant op_sleui	: dlx_opcode := B"110100";
+  constant op_sgeui	: dlx_opcode := B"110101";
+  constant op_undef_36	: dlx_opcode := B"110110";
+  constant op_undef_37	: dlx_opcode := B"110111";
+  constant op_undef_38	: dlx_opcode := B"111000";
+  constant op_undef_39	: dlx_opcode := B"111001";
+  constant op_undef_3A	: dlx_opcode := B"111010";
+  constant op_undef_3B	: dlx_opcode := B"111011";
+  constant op_undef_3C	: dlx_opcode := B"111100";
+  constant op_undef_3D	: dlx_opcode := B"111101";
+  constant op_undef_3E	: dlx_opcode := B"111110";
+  constant op_undef_3F  : dlx_opcode := B"111111";
+
+  constant sp_func_nop       : dlx_sp_func := B"000000";
+  constant sp_func_undef_01  : dlx_sp_func := B"000001";
+  constant sp_func_undef_02  : dlx_sp_func := B"000010";
+  constant sp_func_undef_03  : dlx_sp_func := B"000011";
+  constant sp_func_sll       : dlx_sp_func := B"000100";
+  constant sp_func_undef_05  : dlx_sp_func := B"000101";
+  constant sp_func_srl	     : dlx_sp_func := B"000110";
+  constant sp_func_sra	     : dlx_sp_func := B"000111";
+  constant sp_func_undef_08  : dlx_sp_func := B"001000";
+  constant sp_func_undef_09  : dlx_sp_func := B"001001";
+  constant sp_func_undef_0A  : dlx_sp_func := B"001010";
+  constant sp_func_undef_0B  : dlx_sp_func := B"001011";
+  constant sp_func_undef_0C  : dlx_sp_func := B"001100";
+  constant sp_func_undef_0D  : dlx_sp_func := B"001101";
+  constant sp_func_undef_0E  : dlx_sp_func := B"001110";
+  constant sp_func_undef_0F  : dlx_sp_func := B"001111";
+  
+  constant sp_func_sequ	     : dlx_sp_func := B"010000";
+  constant sp_func_sneu	     : dlx_sp_func := B"010001";
+  constant sp_func_sltu	     : dlx_sp_func := B"010010";
+  constant sp_func_sgtu	     : dlx_sp_func := B"010011";
+  constant sp_func_sleu	     : dlx_sp_func := B"010100";
+  constant sp_func_sgeu	     : dlx_sp_func := B"010101";
+  constant sp_func_undef_16  : dlx_sp_func := B"010110";
+  constant sp_func_undef_17  : dlx_sp_func := B"010111";
+  constant sp_func_undef_18  : dlx_sp_func := B"011000";
+  constant sp_func_undef_19  : dlx_sp_func := B"011001";
+  constant sp_func_undef_1A  : dlx_sp_func := B"011010";
+  constant sp_func_undef_1B  : dlx_sp_func := B"011011";
+  constant sp_func_undef_1C  : dlx_sp_func := B"011100";
+  constant sp_func_undef_1D  : dlx_sp_func := B"011101";
+  constant sp_func_undef_1E  : dlx_sp_func := B"011110";
+  constant sp_func_undef_1F  : dlx_sp_func := B"011111";
+  
+  constant sp_func_add	     : dlx_sp_func := B"100000";
+  constant sp_func_addu	     : dlx_sp_func := B"100001";
+  constant sp_func_sub	     : dlx_sp_func := B"100010";
+  constant sp_func_subu	     : dlx_sp_func := B"100011";
+  constant sp_func_and	     : dlx_sp_func := B"100100";
+  constant sp_func_or	     : dlx_sp_func := B"100101";
+  constant sp_func_xor	     : dlx_sp_func := B"100110";
+  constant sp_func_undef_27  : dlx_sp_func := B"100111";
+  constant sp_func_seq	     : dlx_sp_func := B"101000";
+  constant sp_func_sne	     : dlx_sp_func := B"101001";
+  constant sp_func_slt	     : dlx_sp_func := B"101010";
+  constant sp_func_sgt	     : dlx_sp_func := B"101011";
+  constant sp_func_sle	     : dlx_sp_func := B"101100";
+  constant sp_func_sge	     : dlx_sp_func := B"101101";
+  constant sp_func_undef_2E  : dlx_sp_func := B"101110";
+  constant sp_func_undef_2F  : dlx_sp_func := B"101111";
+  
+  constant sp_func_movi2s    : dlx_sp_func := B"110000";
+  constant sp_func_movs2i    : dlx_sp_func := B"110001";
+  constant sp_func_movf	     : dlx_sp_func := B"110010";
+  constant sp_func_movd	     : dlx_sp_func := B"110011";
+  constant sp_func_movfp2i   : dlx_sp_func := B"110100";
+  constant sp_func_movi2fp   : dlx_sp_func := B"110101";
+  constant sp_func_undef_36  : dlx_sp_func := B"110110";
+  constant sp_func_undef_37  : dlx_sp_func := B"110111";
+  constant sp_func_undef_38  : dlx_sp_func := B"111000";
+  constant sp_func_undef_39  : dlx_sp_func := B"111001";
+  constant sp_func_undef_3A  : dlx_sp_func := B"111010";
+  constant sp_func_undef_3B  : dlx_sp_func := B"111011";
+  constant sp_func_undef_3C  : dlx_sp_func := B"111100";
+  constant sp_func_undef_3D  : dlx_sp_func := B"111101";
+  constant sp_func_undef_3E  : dlx_sp_func := B"111110";
+  constant sp_func_undef_3F  : dlx_sp_func := B"111111";
+  
+  constant fp_func_addf      : dlx_fp_func := B"00000";
+  constant fp_func_subf      : dlx_fp_func := B"00001";
+  constant fp_func_multf     : dlx_fp_func := B"00010";
+  constant fp_func_divf	     : dlx_fp_func := B"00011";
+  constant fp_func_addd	     : dlx_fp_func := B"00100";
+  constant fp_func_subd	     : dlx_fp_func := B"00101";
+  constant fp_func_multd     : dlx_fp_func := B"00110";
+  constant fp_func_divd	     : dlx_fp_func := B"00111";
+  constant fp_func_cvtf2d    : dlx_fp_func := B"01000";
+  constant fp_func_cvtf2i    : dlx_fp_func := B"01001";
+  constant fp_func_cvtd2f    : dlx_fp_func := B"01010";
+  constant fp_func_cvtd2i    : dlx_fp_func := B"01011";
+  constant fp_func_cvti2f    : dlx_fp_func := B"01100";
+  constant fp_func_cvti2d    : dlx_fp_func := B"01101";
+  constant fp_func_mult	     : dlx_fp_func := B"01110";
+  constant fp_func_div	     : dlx_fp_func := B"01111";
+  
+  constant fp_func_eqf	     : dlx_fp_func := B"10000";
+  constant fp_func_nef	     : dlx_fp_func := B"10001";
+  constant fp_func_ltf	     : dlx_fp_func := B"10010";
+  constant fp_func_gtf	     : dlx_fp_func := B"10011";
+  constant fp_func_lef	     : dlx_fp_func := B"10100";
+  constant fp_func_gef	     : dlx_fp_func := B"10101";
+  constant fp_func_multu     : dlx_fp_func := B"10110";
+  constant fp_func_divu	     : dlx_fp_func := B"10111";
+  constant fp_func_eqd	     : dlx_fp_func := B"11000";
+  constant fp_func_ned	     : dlx_fp_func := B"11001";
+  constant fp_func_ltd	     : dlx_fp_func := B"11010";
+  constant fp_func_gtd	     : dlx_fp_func := B"11011";
+  constant fp_func_led	     : dlx_fp_func := B"11100";
+  constant fp_func_ged	     : dlx_fp_func := B"11101";
+  constant fp_func_undef_1E  : dlx_fp_func := B"11110";
+  constant fp_func_undef_1F  : dlx_fp_func := B"11111";
+
+  subtype dlx_opcode_num is natural range 0 to 63;
+  subtype dlx_sp_func_num is natural range 0 to 63;
+  subtype dlx_fp_func_num is natural range 0 to 31;
+
+  subtype instr_name is string(1 to 8);
+  type opcode_name_array is array (dlx_opcode_num) of instr_name;
+  type sp_func_name_array is array (dlx_sp_func_num) of instr_name;
+  type fp_func_name_array is array (dlx_fp_func_num) of instr_name;
+
+  constant opcode_names : opcode_name_array;
+  constant sp_func_names : sp_func_name_array;
+  constant fp_func_names : fp_func_name_array;
+
+  subtype reg_index is natural range 0 to 31;
+
+  constant link_reg : reg_index := 31;
+
+  procedure disassemble ( instr : dlx_bv_word;
+			  disassembled_instr : out string;  len : out positive );
+
+end package dlx_instr;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxr.vhd
new file mode 100644
index 0000000..a00dc21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxr.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_rtl of dlx is
+
+  for rtl
+
+    for alu_s1_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for alu_s2_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for the_alu : alu
+      use entity work.alu(behavior)
+        generic map ( Tpd => 4 ns );
+    end for;
+
+    for the_reg_file : reg_file
+      use entity work.reg_file(behavior)
+        generic map ( Tac => 4 ns );
+    end for;
+
+    for c_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for a_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for b_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for temp_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for iar_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for pc_reg :reg_multiple_plus_one_out_reset
+      use entity work.reg_multiple_plus_one_out_reset(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for mar_reg : reg_multiple_plus_one_out
+      use entity work.reg_multiple_plus_one_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for mem_addr_mux : mux2
+      use entity work.mux2(behavior)
+        generic map ( Tpd => 1 ns );
+    end for;
+
+    for mdr_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for mdr_mux : mux2
+      use entity work.mux2(behavior)
+        generic map ( Tpd => 1 ns );
+    end for;
+
+    for instr_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for ir_extender1 : ir_extender
+      use entity work.ir_extender(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for ir_extender2 : ir_extender
+      use entity work.ir_extender(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for the_controller : controller
+      use entity work.controller(behavior)
+        generic map ( Tpd_clk_ctrl => 2 ns, Tpd_clk_const => 4 ns,
+                      debug => debug );
+    end for;
+
+  end for;  -- rtl of dlx
+
+end configuration dlx_rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxstsv.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxstsv.vhd
new file mode 100644
index 0000000..0a211df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxstsv.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxstsv.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_test_verifier of dlx_test is
+
+  for verifier
+
+    for cg : clock_gen
+      use entity work.clock_gen(behavior)
+        generic map ( Tpw => 8 ns, Tps => 2 ns );
+    end for;
+
+    for mem : memory
+      use entity work.memory(preloaded)
+        generic map ( mem_size => 65536,
+                      Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
+    end for;
+
+    for proc_behav : dlx
+      use entity work.dlx(behavior)
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+    for proc_rtl : dlx
+      use configuration work.dlx_rtl
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+  end for;  -- verifier of dlx_test
+
+end configuration dlx_test_verifier;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxt.vhd
new file mode 100644
index 0000000..190ea0c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxt.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxt.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package dlx_types is
+
+  -- little-endian addresses
+  subtype dlx_address is std_logic_vector(31 downto 0);
+  subtype dlx_bv_address is bit_vector(31 downto 0);
+
+  -- big-endian data words
+  subtype dlx_word is std_logic_vector(0 to 31);
+  subtype dlx_bv_word is bit_vector(0 to 31);
+
+  type dlx_word_array is array (natural range <>) of dlx_word;
+
+  -- tristate bus driving value
+  constant disabled_dlx_word : dlx_word := ( others => 'Z' );
+
+  -- type for specifying data width on the data bus
+  subtype dlx_mem_width is std_logic_vector(1 downto 0);
+
+  constant dlx_mem_width_byte : dlx_mem_width := "01";
+  constant dlx_mem_width_halfword : dlx_mem_width := "10";
+  constant dlx_mem_width_word : dlx_mem_width := "00";
+
+  -- type for controlling trace information generated by model
+  type dlx_debug_control is
+    ( none,
+      msg_every_100_instructions, msg_each_instruction,
+      trace_each_instruction, trace_each_step );
+
+end package dlx_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-b.vhd
new file mode 100644
index 0000000..65e91af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-b.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtst-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench of dlx_test is
+
+  use work.dlx_types.all;
+
+  component clock_gen is
+                        port ( phi1, phi2 : out std_logic;
+                               reset : out std_logic );
+  end component clock_gen;
+
+  component memory is
+                     port ( phi1, phi2 : in std_logic;
+                            a : in dlx_address;
+                            d : inout dlx_word;
+                            width : in dlx_mem_width;
+                            write_enable : in std_logic;
+                            burst : in std_logic := '0';
+                            mem_enable : in std_logic;
+                            ready : out std_logic );
+  end component memory;
+
+  component dlx is
+                  port ( phi1, phi2 : in std_logic;
+                         reset : in std_logic;
+                         halt : out std_logic;
+                         a : out dlx_address;
+                         d : inout dlx_word;
+                         width : out dlx_mem_width;
+                         write_enable : out std_logic;
+                         ifetch : out std_logic;
+                         mem_enable : out std_logic;
+                         ready : in std_logic );
+  end component dlx;
+
+  signal phi1, phi2, reset : std_logic;
+  signal a : dlx_address;
+  signal d : dlx_word;
+  signal halt : std_logic;
+  signal width : dlx_mem_width;
+  signal write_enable, mem_enable, ifetch, ready : std_logic;
+
+begin
+
+  cg : component clock_gen
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset );
+
+  mem : component memory
+    port map ( phi1 => phi1, phi2 => phi2,
+               a => a, d => d,
+               width => width, write_enable => write_enable, burst => open,
+               mem_enable => mem_enable, ready => ready );
+
+  proc : component dlx
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
+               a => a, d => d,
+               width => width, write_enable => write_enable, ifetch => ifetch,
+               mem_enable => mem_enable, ready => ready );
+
+end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd
new file mode 100644
index 0000000..b031296
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd
@@ -0,0 +1,156 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture verifier of dlx_test is
+
+  use work.dlx_types.all;
+
+  component clock_gen is
+                        port ( phi1, phi2 : out std_logic;
+                               reset : out std_logic );
+  end component clock_gen;
+
+  component memory is
+                     port ( phi1, phi2 : in std_logic;
+                            a : in dlx_address;
+                            d : inout dlx_word;
+                            width : in dlx_mem_width;
+                            write_enable : in std_logic;
+                            burst : in std_logic := '0';
+                            mem_enable : in std_logic;
+                            ready : out std_logic );
+  end component memory;
+
+  component dlx is
+                  port ( phi1, phi2 : in std_logic;
+                         reset : in std_logic;
+                         halt : out std_logic;
+                         a : out dlx_address;
+                         d : inout dlx_word;
+                         width : out dlx_mem_width;
+                         write_enable : out std_logic;
+                         ifetch : out std_logic;
+                         mem_enable : out std_logic;
+                         ready : in std_logic );
+  end component dlx;
+
+  signal phi1, phi2, reset : std_logic;
+
+  signal a_behav : dlx_address;
+  signal d_behav : dlx_word;
+  signal halt_behav : std_logic;
+  signal width_behav : dlx_mem_width;
+  signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
+
+  signal a_rtl : dlx_address;
+  signal d_rtl : dlx_word;
+  signal halt_rtl : std_logic;
+  signal width_rtl : dlx_mem_width;
+  signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
+
+  signal ready_mem : std_logic;
+
+begin
+
+  cg : component clock_gen
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset );
+
+  mem : component memory
+    port map ( phi1 => phi1, phi2 => phi2,
+               a => a_behav, d => d_behav,
+               width => width_behav, write_enable => write_enable_behav,
+               burst => open,
+               mem_enable => mem_enable_behav, ready => ready_mem );
+
+  proc_behav : component dlx
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
+               a => a_behav, d => d_behav,
+               width => width_behav, write_enable => write_enable_behav,
+               ifetch => ifetch_behav,
+               mem_enable => mem_enable_behav, ready => ready_mem );
+
+  proc_rtl : component dlx
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
+               a => a_rtl, d => d_rtl,
+               width => width_rtl, write_enable => write_enable_rtl,
+               ifetch => ifetch_rtl,
+               mem_enable => mem_enable_rtl, ready => ready_mem );
+
+  verification_section : block is
+  begin
+
+    fwd_data_from_mem_to_rtl : 
+      d_rtl <= d_behav when mem_enable_rtl = '1'
+               and write_enable_rtl = '0' else
+               disabled_dlx_word;
+
+    monitor : process
+
+      variable write_command_behav : boolean;
+      variable write_command_rtl : boolean;
+
+    begin
+      monitor_loop : loop
+        -- wait for a command, valid on leading edge of phi2
+        wait until rising_edge(phi2)
+          and mem_enable_behav = '1' and mem_enable_rtl = '1';
+        --
+        -- capture the command information
+        write_command_behav := write_enable_behav = '1';
+        write_command_rtl := write_enable_rtl = '1';
+        assert a_behav = a_rtl
+          report "addresses differ";
+        assert write_enable_behav = write_enable_rtl
+          report "write enable states differ";
+        assert ifetch_behav = ifetch_rtl
+          report "instruction fetch states differ";
+        assert width_behav = width_rtl
+          report "widths differ";
+        if write_command_behav and write_command_rtl then
+          assert d_behav = d_rtl
+            report "write data differs";
+        end if;
+        --
+        -- wait for the response from memory
+        ready_loop : loop 
+          wait until falling_edge(phi2);
+          exit monitor_loop when reset = '1';
+          exit ready_loop when ready_mem = '1';
+        end loop ready_loop;
+      end loop monitor_loop;
+      --
+      -- get here when reset is asserted
+      wait until reset = '0';
+      --
+      -- process monitor now starts again from beginning
+    end process monitor;
+
+  end block verification_section;
+
+end architecture verifier;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst.vhd
new file mode 100644
index 0000000..bc7087c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtst.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity dlx_test is
+
+end entity dlx_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstb.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstb.vhd
new file mode 100644
index 0000000..e5bb8b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstb.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtstb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_test_behavior of dlx_test is
+
+  for bench
+
+    for cg : clock_gen
+      use entity work.clock_gen(behavior)
+        generic map ( Tpw => 8 ns, Tps => 2 ns );
+    end for;
+
+    for mem : memory
+      use entity work.memory(preloaded)
+        generic map ( mem_size => 65536,
+                      Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
+    end for;
+
+    for proc : dlx
+      use entity work.dlx(behavior)
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+  end for;
+
+end configuration dlx_test_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstr.vhd
new file mode 100644
index 0000000..2a590db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstr.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtstr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_test_rtl of dlx_test is
+
+  for bench
+
+    for cg : clock_gen
+      use entity work.clock_gen(behavior)
+        generic map ( Tpw => 8 ns, Tps => 2 ns );
+    end for;
+
+    for mem : memory
+      use entity work.memory(preloaded)
+        generic map ( mem_size => 65536,
+                      Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
+    end for;
+
+    for proc : dlx
+      use configuration work.dlx_rtl
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+  end for;  -- bench of dlx_test
+
+end configuration dlx_test_rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire-b.vhd
new file mode 100644
index 0000000..39813af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire-b.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_ire-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+use work.dlx_instr.all;
+
+architecture behavior of ir_extender is
+
+  subtype upper_6_bits is std_logic_vector(0 to 5);
+  subtype upper_16_bits is std_logic_vector(0 to 15);
+
+begin
+
+  extender : process ( d, immed_en, immed_size_26, immed_unsigned ) is
+  begin
+    if To_bit(immed_en) = '1' then
+      if To_bit(immed_size_26) = '1' then  -- 26-bit immediate
+      	if To_bit(immed_unsigned) = '1' then
+	  q <= upper_6_bits'(others => '0') & d(6 to 31) after Tpd;
+	else
+	  q <= upper_6_bits'(others => d(6)) & d(6 to 31) after Tpd;
+	end if;
+      else -- 16-bit immediate
+      	if To_bit(immed_unsigned) = '1' then
+	  q <= upper_16_bits'(others => '0') & d(16 to 31) after Tpd;
+	else
+	  q <= upper_16_bits'(others => d(16)) & d(16 to 31) after Tpd;
+	end if;
+      end if;
+    else
+      q <= disabled_dlx_word after Tpd;
+    end if;
+  end process extender;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd
new file mode 100644
index 0000000..21d1a19
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_ire.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.dlx_types.all;
+
+               entity ir_extender is
+                 generic ( Tpd : delay_length );
+                 port ( d : in dlx_word;
+                        q : out dlx_word;
+                        immed_size_26 : in std_logic;
+                        immed_unsigned : in std_logic;
+                        immed_en : in std_logic );
+               end entity ir_extender;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch-b.vhd
new file mode 100644
index 0000000..cbd72a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch-b.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_latch-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of latch is
+
+begin 
+
+  q <= d after Tpd when To_bit(latch_en) = '1';
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd
new file mode 100644
index 0000000..d8c287b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_latch.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity latch is
+  generic ( Tpd : delay_length );
+  port ( d : in dlx_word;
+         q : out dlx_word;
+         latch_en : in std_logic );
+end entity latch;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd
new file mode 100644
index 0000000..60a8767
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd
@@ -0,0 +1,193 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mem-fl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use bv_utilities.bv_arithmetic.all,
+  std.textio.all;
+
+architecture file_loaded of memory is
+begin
+
+  mem_behavior : process is
+
+                           constant high_address : natural := mem_size - 1;
+
+                         type memory_array is
+                           array (natural range 0 to high_address / 4) of dlx_bv_word;
+
+                         variable mem : memory_array;
+
+                         variable byte_address, word_address : natural;
+                         variable write_access : boolean;
+
+                         procedure load is
+
+                           file binary_file : text open read_mode is load_file_name;
+                           variable L : line;
+                           variable ch : character;
+                           variable line_number : natural := 0;
+                           variable addr : natural;
+                           variable word : dlx_bv_word;
+
+                           procedure read_hex_natural ( L : inout line;  n : out natural ) is
+                             variable result : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 result := result*16 + character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 result := result*16 + character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 result := result*16 + character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number) severity error;
+                               end if;
+                             end loop;
+                             n := result;
+                           end read_hex_natural;
+
+                           procedure read_hex_word ( L : inout line;  word : out dlx_bv_word ) is
+                             variable digit : natural;
+                             variable r : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 digit := character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 digit := character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 digit := character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number)
+                                   severity error;
+                               end if;
+                               word(r to r+3) := natural_to_bv(digit, 4);
+                               r := r + 4;
+                             end loop;
+                           end read_hex_word;
+
+                         begin
+                           while not endfile(binary_file) loop
+                             readline(binary_file, L);
+                             line_number := line_number + 1;
+                             read_hex_natural(L, addr);
+                             read(L, ch);  -- the space between addr and data
+                             read_hex_word(L, word);
+                             mem(addr / 4) := word;
+                           end loop;
+                         end load;
+
+                         procedure do_write is
+                           subtype ls_2_bits is bit_vector(1 downto 0);
+                         begin
+                           case width is
+                             when dlx_mem_width_word =>
+                               mem(word_address) := to_bitvector(d);
+                             when dlx_mem_width_halfword =>
+                               if To_bit(a(1)) = '0' then  -- ms half word
+                                 mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
+                               else  -- ls half word
+                                 mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
+                               end if;
+                             when dlx_mem_width_byte =>
+                               case ls_2_bits'(To_bitvector(a(1 downto 0))) is
+                                 when b"00" =>
+                                   mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
+                                 when b"01" =>
+                                   mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
+                                 when b"10" =>
+                                   mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
+                                 when b"11" =>
+                                   mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
+                               end case;
+                             when others =>
+                               report "illegal width indicator in write" severity error;
+                           end case;
+                         end do_write;
+
+                         procedure do_read is
+                         begin
+                           d <= To_X01( mem(word_address) );
+                         end do_read;
+
+  begin
+    load;  -- read binary memory image into memory array
+    -- initialize outputs
+    d <= disabled_dlx_word;
+    ready <= '0';
+
+    -- process memory cycles
+    loop
+      -- wait for a command, valid on leading edge of phi2
+      wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
+
+      -- decode address and perform command if selected
+      byte_address := bv_to_natural(To_bitvector(a));
+      write_access := To_bit(write_enable) = '1';
+      if byte_address <= high_address then
+        word_address := byte_address / 4;
+        if write_access then -- write cycle
+          do_write;
+          wait for Tac_first;  -- write access time, 1st cycle
+        else -- read cycle
+          wait for Tac_first;  -- read access time, 1st cycle
+          do_read;
+        end if;
+        -- ready synchronous with phi2
+        wait until rising_edge(phi2);
+        ready <= '1' after Tpd_clk_out;
+        wait until falling_edge(phi2);
+        ready <= '0' after Tpd_clk_out;
+        --  do subsequent cycles in burst
+        while To_bit(burst) = '1' loop
+          word_address := (word_address + 1) mod (mem_size / 4);
+          wait until rising_edge(phi2);
+          if write_access then -- write cycle
+            do_write;
+            wait for Tac_burst;  -- write access time, burst cycle
+          else -- read cycle
+            wait for Tac_burst;  -- read access time, burst cycle
+            do_read;
+          end if;
+          -- ready synchronous with phi2
+          wait until rising_edge(phi2);
+          ready <= '1' after Tpd_clk_out;
+          wait until falling_edge(phi2);
+          ready <= '0' after Tpd_clk_out;
+        end loop;
+        if not write_access then  -- was read
+          d <= disabled_dlx_word after Tpd_clk_out;
+        end if;
+      end if;
+    end loop;
+  end process mem_behavior;
+
+end architecture file_loaded;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd
new file mode 100644
index 0000000..5322a8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd
@@ -0,0 +1,140 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mem-pl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use bv_utilities.bv_arithmetic.all;
+
+architecture preloaded of memory is
+
+begin 
+
+  mem_behavior : process is
+
+                           constant high_address : natural := mem_size - 1;
+
+                         type memory_array is
+                           array (natural range 0 to high_address / 4) of dlx_bv_word;
+
+                         variable mem : memory_array
+                           := ( X"20020000",	 --           addi  r2, r0, 0
+                                X"ac020018",  -- loop:     sw    counter(r0), r2
+                                X"20420001",  --           addi  r2, r2, 1
+                                X"6441000a",  --           snei  r1, r2, 10
+                                X"1420fff0",  --           bnez  r1, loop
+                                X"44000000",  --           trap  0
+                                X"00000000",  -- counter:  .word 0
+                                others => X"00000000" );
+
+                         variable byte_address, word_address : natural;
+                         variable write_access : boolean;
+
+
+                         procedure do_write is
+                           subtype ls_2_bits is bit_vector(1 downto 0);
+                         begin
+                           case width is
+                             when dlx_mem_width_word =>
+                               mem(word_address) := to_bitvector(d);
+                             when dlx_mem_width_halfword =>
+                               if To_bit(a(1)) = '0' then  -- ms half word
+                                 mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
+                               else  -- ls half word
+                                 mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
+                               end if;
+                             when dlx_mem_width_byte =>
+                               case ls_2_bits'(To_bitvector(a(1 downto 0))) is
+                                 when b"00" =>
+                                   mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
+                                 when b"01" =>
+                                   mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
+                                 when b"10" =>
+                                   mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
+                                 when b"11" =>
+                                   mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
+                               end case;
+                             when others =>
+                               report "illegal width indicator in write" severity error;
+                           end case;
+                         end do_write;
+
+                         procedure do_read is
+                         begin
+                           d <= To_X01( mem(word_address) );
+                         end do_read;
+
+  begin
+    -- initialize outputs
+    d <= disabled_dlx_word;
+    ready <= '0';
+
+    -- process memory cycles
+    loop
+      -- wait for a command, valid on leading edge of phi2
+      wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
+
+      -- decode address and perform command if selected
+      byte_address := bv_to_natural(To_bitvector(a));
+      write_access := To_bit(write_enable) = '1';
+      if byte_address <= high_address then
+        word_address := byte_address / 4;
+        if write_access then -- write cycle
+          do_write;
+          wait for Tac_first;  -- write access time, 1st cycle
+        else -- read cycle
+          wait for Tac_first;  -- read access time, 1st cycle
+          do_read;
+        end if;
+        -- ready synchronous with phi2
+        wait until rising_edge(phi2);
+        ready <= '1' after Tpd_clk_out;
+        wait until falling_edge(phi2);
+        ready <= '0' after Tpd_clk_out;
+        --  do subsequent cycles in burst
+        while To_bit(burst) = '1' loop
+	  word_address := (word_address + 1) mod (mem_size / 4);
+          wait until rising_edge(phi2);
+          if write_access then -- write cycle
+            do_write;
+            wait for Tac_burst;  -- write access time, burst cycle
+          else -- read cycle
+            wait for Tac_burst;  -- read access time, burst cycle
+            do_read;
+          end if;
+          -- ready synchronous with phi2
+          wait until rising_edge(phi2);
+          ready <= '1' after Tpd_clk_out;
+          wait until falling_edge(phi2);
+          ready <= '0' after Tpd_clk_out;
+        end loop;
+        if not write_access then  -- was read
+          d <= disabled_dlx_word after Tpd_clk_out;
+        end if;
+      end if;
+    end loop;
+  end process mem_behavior;
+
+end architecture preloaded;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem.vhd
new file mode 100644
index 0000000..d69c778
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mem.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee. std_logic_1164.all;
+
+               use work.dlx_types.all;
+
+               entity memory is
+
+                 generic ( mem_size : positive;
+                           Tac_first : delay_length;
+                           Tac_burst : delay_length;
+                           Tpd_clk_out : delay_length;
+                           load_file_name : string := "dlx.out" );
+
+                 port ( phi1, phi2 : in std_logic;
+                        a : in dlx_address;
+                        d : inout dlx_word;
+                        width : in dlx_mem_width;
+                        write_enable : in std_logic;
+                        burst : in std_logic := '0';
+                        mem_enable : in std_logic;
+                        ready : out std_logic );
+
+               end entity memory;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2-b.vhd
new file mode 100644
index 0000000..39d13b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2-b.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mux2-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of mux2 is
+
+begin
+
+  with To_bit(sel) select
+    y <=  i0 after Tpd when '0',
+    i1 after Tpd when '1';
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2.vhd
new file mode 100644
index 0000000..f690795
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mux2.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.dlx_types.all;
+
+               entity mux2 is
+                 generic ( Tpd : delay_length );
+                 port ( i0, i1 : in dlx_word;
+                        y : out dlx_word;
+                        sel : in std_logic );
+               end mux2;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm-b.vhd
new file mode 100644
index 0000000..551b9eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm-b.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regm-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of reg_multiple_out is
+
+begin
+
+  reg: process ( d, latch_en, out_en ) is
+
+                                         variable latched_value : dlx_word;
+
+  begin
+    if To_bit(latch_en) = '1' then
+      latched_value := To_X01(d);
+    end if;
+    for index in out_en'range loop
+      if To_bit(out_en(index)) = '1' then
+	q(index) <= latched_value after Tpd;
+      else
+	q(index) <= disabled_dlx_word after Tpd;
+      end if;
+    end loop;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm.vhd
new file mode 100644
index 0000000..790fe50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regm.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity reg_multiple_out is
+  generic ( num_outputs : positive;
+            Tpd : delay_length );
+  port ( d : in dlx_word;
+         q : out dlx_word_array(1 to num_outputs);
+         latch_en : in std_logic;
+         out_en : in std_logic_vector(1 to num_outputs) );
+end entity reg_multiple_out;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp-b.vhd
new file mode 100644
index 0000000..9dfc31d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp-b.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmp-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of reg_multiple_plus_one_out is
+
+begin
+
+  reg: process ( d, latch_en, out_en ) is
+
+                                         variable latched_value : dlx_word;
+
+  begin
+    if To_bit(latch_en) = '1' then
+      latched_value := To_X01(d);
+    end if;
+    q0 <= latched_value after Tpd;
+    for index in out_en'range loop
+      if To_bit(out_en(index)) = '1' then
+	q(index) <= latched_value after Tpd;
+      else
+	q(index) <= disabled_dlx_word after Tpd;
+      end if;
+    end loop;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp.vhd
new file mode 100644
index 0000000..d1ccb05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmp.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity reg_multiple_plus_one_out is
+  generic ( num_outputs : positive;
+            Tpd : delay_length );
+  port ( d : in dlx_word;
+         q0 : out dlx_word;
+         q : out dlx_word_array(1 to num_outputs);
+         latch_en : in std_logic;
+         out_en : in std_logic_vector(1 to num_outputs) );
+end entity reg_multiple_plus_one_out;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr-b.vhd
new file mode 100644
index 0000000..6400914
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr-b.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmpr-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of reg_multiple_plus_one_out_reset is
+
+begin
+
+  reg: process ( d, latch_en, out_en, reset )
+    is
+
+      variable latched_value : dlx_word;
+
+  begin
+    if To_bit(reset) = '1' then
+      latched_value := X"0000_0000";
+    elsif To_bit(latch_en) = '1' then
+      latched_value := To_X01(d);
+    end if;
+    q0 <= latched_value after Tpd;
+    for index in out_en'range loop
+      if To_bit(out_en(index)) = '1' then
+	q(index) <= latched_value after Tpd;
+      else
+	q(index) <= disabled_dlx_word after Tpd;
+      end if;
+    end loop;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr.vhd
new file mode 100644
index 0000000..1b21ca7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmpr.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity reg_multiple_plus_one_out_reset is
+  generic ( num_outputs : positive;
+            Tpd : delay_length );
+  port ( d : in dlx_word;
+         q0 : out dlx_word;
+         q : out dlx_word_array(1 to num_outputs);
+         latch_en : in std_logic;
+         out_en : in std_logic_vector(1 to num_outputs);
+         reset : in std_logic );
+end entity reg_multiple_plus_one_out_reset;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf-b.vhd
new file mode 100644
index 0000000..c80b6b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf-b.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_rf-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+architecture behavior of reg_file is
+
+begin
+
+  reg: process ( a1, a2, a3, d3, write_en ) is
+
+                                              use work.dlx_instr.reg_index,
+                                              bv_utilities.bv_arithmetic.bv_to_natural;
+
+                                            constant all_zeros : dlx_word := X"0000_0000";
+
+                                            type register_array is array (reg_index range 1 to 31) of dlx_word;
+
+                                            variable register_file : register_array;
+                                            variable reg_index1, reg_index2, reg_index3 : reg_index;
+
+  begin
+    -- do write first if enabled
+    --
+    if To_bit(write_en) = '1' then
+      reg_index3 := bv_to_natural(To_bitvector(a3));
+      if reg_index3 /= 0 then
+        register_file(reg_index3) := To_X01(d3);
+      end if;
+    end if;
+    --
+    -- read port 1
+    --
+    reg_index1 := bv_to_natural(To_bitvector(a1));
+    if reg_index1 /= 0 then
+      q1 <= register_file(reg_index1) after Tac;
+    else
+      q1 <= all_zeros after Tac;
+    end if;
+    --
+    -- read port 2
+    --
+    reg_index2 := bv_to_natural(To_bitvector(a2));
+    if reg_index2 /= 0 then
+      q2 <= register_file(reg_index2) after Tac;
+    else
+      q2 <= all_zeros after Tac;
+    end if;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd
new file mode 100644
index 0000000..fa29d4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_rf.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.dlx_types.all,
+                 work.reg_file_types.all;
+
+               entity reg_file is
+                 generic ( Tac : delay_length );
+                 port ( a1 : in reg_file_addr;
+                        q1 : out dlx_word;
+                        a2 : in reg_file_addr;
+                        q2 : out dlx_word;
+                        a3 : in reg_file_addr;
+                        d3 : in dlx_word;
+                        write_en : in std_logic );
+               end entity reg_file;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rft.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rft.vhd
new file mode 100644
index 0000000..ba29d11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rft.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_rft.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--use work.dlx_instr.dlx_reg_addr;
+use work.dlx_instr.all;
+
+package reg_file_types is
+
+  subtype reg_file_addr is std_logic_vector(dlx_reg_addr'range);
+
+end package reg_file_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_01.vhd
new file mode 100644
index 0000000..e07996e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_01.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_01 is
+
+end entity ch_16_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_01 is
+
+  function pulled_up ( drivers : bit_vector ) return bit is
+  begin
+    for index in drivers'range loop
+      if drivers(index) = '0' then
+        return '0';
+      end if;
+    end loop;
+    return '1';
+  end function pulled_up;
+
+  type state_type is (init_state, state1, state2, state3);
+  type state_vector is array (integer range <>) of state_type;
+
+  function resolve_state ( drivers : state_vector ) return state_type is
+  begin
+    return drivers(drivers'left);
+  end function resolve_state;
+
+
+  -- code from book:
+
+  signal interrupt_request : pulled_up bit bus;
+
+  signal stored_state : resolve_state state_type register := init_state;
+
+  -- end of code from book
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_02.vhd
new file mode 100644
index 0000000..d080b4f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_02.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_02 is
+
+end entity ch_16_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_02 is
+
+  -- code from book:
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word;
+
+  signal s : resolve_words word bus;
+
+  -- end of code from book
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  constant T_delay : delay_length := 2 ns;
+
+begin
+
+
+  process is
+  begin
+
+    -- code from book (should fail)
+
+    s(0 to 15) <= X"003F" after T_delay;
+    s(16 to 31) <= null after T_delay;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_03.vhd
new file mode 100644
index 0000000..5896cd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_03.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_03 is
+
+end entity ch_16_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_03 is
+
+  function pulled_up ( drivers : bit_vector ) return bit is
+  begin
+    for index in drivers'range loop
+      if drivers(index) = '0' then
+        return '0';
+      end if;
+    end loop;
+    return '1';
+  end function pulled_up;
+
+  signal s : pulled_up bit bus;
+
+begin
+
+
+  process is
+  begin
+
+    s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
+         null after 19 ns, '0' after 25 ns;
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= reject 3 ns inertial null after 10 ns;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd
new file mode 100644
index 0000000..6bff359
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_04 is
+
+end entity ch_16_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_04 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  -- code from book:
+
+  signal memory_data_bus : resolved_word bus;
+  disconnect memory_data_bus : resolved_word after 3 ns;
+
+  -- end of code from book
+
+  signal mem_sel, mem_write : boolean;
+  signal cache_data_bus : word;
+
+begin
+
+
+  -- code from book:
+
+  mem_write_buffer : block (mem_sel and mem_write) is
+  begin
+    memory_data_bus <=
+      guarded reject 2 ns inertial cache_data_bus after 4 ns;
+  end block mem_write_buffer;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    cache_data_bus <= X"DDDDDDDD";
+    wait for 10 ns;
+    mem_sel <= true;  mem_write <= true;
+    wait for 10 ns;
+    cache_data_bus <= X"AAAAAAAA";
+    wait for 10 ns;
+    mem_sel <= false;  mem_write <= false;
+    wait for 10 ns;
+    cache_data_bus <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd
new file mode 100644
index 0000000..4303bd9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_05 is
+
+end entity ch_16_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_05 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  -- code from book:
+
+  signal source_bus_1, source_bus_2 : resolved_word bus;
+  signal address_bus : resolved_word bus;
+
+  disconnect all : resolved_word after 2 ns;
+
+  -- end of code from book
+
+  signal s : word;
+  signal g : boolean;
+
+begin
+
+
+  b : block (g) is
+  begin
+    source_bus_1 <= guarded s after 4 ns;
+    source_bus_2 <= guarded s after 4 ns;
+    address_bus <= guarded s after 4 ns;
+  end block b;
+
+  stimulus : process is
+  begin
+    s <= X"DDDDDDDD";
+    wait for 10 ns;
+    g <= true;
+    wait for 10 ns;
+    s <= X"AAAAAAAA";
+    wait for 10 ns;
+    g <= false;
+    wait for 10 ns;
+    s <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd
new file mode 100644
index 0000000..29d4158
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_06 is
+
+end entity ch_16_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_06 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  signal source_bus_1, source_bus_2 : resolved_word bus;
+  signal address_bus : resolved_word bus;
+
+  -- code from book:
+
+  disconnect address_bus : resolved_word after 3 ns;
+
+  disconnect others : resolved_word after 2 ns;
+
+  -- end of code from book
+
+  signal s : word;
+  signal g : boolean;
+
+begin
+
+
+  b : block (g) is
+  begin
+    source_bus_1 <= guarded s after 4 ns;
+    source_bus_2 <= guarded s after 4 ns;
+    address_bus <= guarded s after 4 ns;
+  end block b;
+
+  stimulus : process is
+  begin
+    s <= X"DDDDDDDD";
+    wait for 10 ns;
+    g <= true;
+    wait for 10 ns;
+    s <= X"AAAAAAAA";
+    wait for 10 ns;
+    g <= false;
+    wait for 10 ns;
+    s <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_01.vhd
new file mode 100644
index 0000000..f5a3631
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_01.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture top_level of computer_system is
+
+  function resolve_bits ( bits : bit_vector ) return bit is
+    variable result : bit := '0';
+  begin
+    for index in bits'range loop
+      result := result or bits(index);
+      exit when result = '1';
+    end loop;
+    return result;
+  end function resolve_bits;
+
+  signal write_en : resolve_bits bit bus;
+  -- . . .
+
+  -- not in book
+  constant Tpd : delay_length := 2 ns;
+  signal clock, hold_req : bit := '0';
+  -- end not in book
+
+begin
+
+  CPU : process is
+                  -- . . .
+  begin
+    write_en <= '0' after Tpd;
+    -- . . .
+    loop
+      wait until clock = '1';
+      if hold_req = '1' then
+        write_en <= null after Tpd;
+        wait on clock until clock = '1' and hold_req = '0';
+        write_en <= '0' after Tpd;
+      end if;
+      -- . . .
+    end loop;
+  end process CPU;
+
+  -- . . .
+
+  -- not in book
+
+  clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0';
+
+  stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns;
+
+  process is
+  begin
+    write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns;
+    wait;
+  end process;
+
+  -- end not in book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_02.vhd
new file mode 100644
index 0000000..ca84bc1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_02.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity processor is
+end entity processor;
+
+
+
+-- code from book
+
+architecture rtl of processor is
+
+  subtype word is bit_vector(0 to 31);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_unique ( drivers : word_vector ) return word is
+  begin
+    return drivers(drivers'left);
+  end function resolve_unique;
+
+  signal source1, source2 : resolve_unique word register;
+  -- . . .
+
+  -- not in book
+
+  type alu_op_type is (pass1, pass2, add, subtract);
+
+  procedure perform_alu_op ( signal alu_opcode : in alu_op_type;
+			     signal source1, source2 : in word;
+			     signal destination : out word;
+			     constant ignored : in integer := 0 ) is
+  begin
+    null;
+  end procedure perform_alu_op;
+
+  signal phase1, source1_reg_out_en,other_signal : bit;
+  signal alu_opcode : alu_op_type;
+  signal destination : word;
+
+  -- end not in book
+
+begin
+
+  source1_reg : process (phase1, source1_reg_out_en, -- . . .) is
+                         -- not in book
+                         other_signal) is
+                                         -- end not in book
+                                         variable stored_value : word;
+  begin
+    -- . . .
+    if source1_reg_out_en = '1' and phase1 = '1' then
+      source1 <= stored_value;
+      -- not in book
+      stored_value := not stored_value;
+      -- end not in book
+    else
+      source1 <= null;
+    end if;
+  end process source1_reg;
+
+  alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
+                         -- not in book
+                         open );
+  -- end not in book
+
+  -- . . .
+
+  -- not in book
+
+  process is
+  begin
+    wait for 10 ns;
+    source1_reg_out_en <= '1';
+    phase1 <= '1', '0' after 10 ns;
+    wait for 20 ns;
+    source1_reg_out_en <= '1';
+    phase1 <= '1', '0' after 10 ns;
+    wait;
+  end process;
+
+  -- end not in book
+
+end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_04.vhd
new file mode 100644
index 0000000..52deb9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_04.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package fg_16_04 is
+
+  -- code from book (in text)
+
+  subtype byte is bit_vector(0 to 7);
+  type byte_array is array (integer range <>) of byte;
+  function resolve ( bytes : byte_array ) return byte;
+  subtype resolved_byte is resolve byte;
+
+  -- end code from book
+
+end package fg_16_04;
+
+
+package body fg_16_04 is
+
+  -- code from book
+
+  function resolve ( bytes : byte_array ) return byte is
+    variable result : byte := b"0000_0000";
+  begin
+    for index in bytes'range loop
+      result := result or bytes(index);
+    end loop;
+    return result;
+  end function resolve;
+
+  -- end code from book
+
+end package body fg_16_04;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_05.vhd
new file mode 100644
index 0000000..d857953
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_05.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.fg_16_04.all;
+
+-- code from book (in text)
+
+entity tri_state_reg is
+  port ( d : in resolved_byte;
+         q : out resolved_byte bus;
+         clock, out_enable : in bit );
+end entity tri_state_reg;
+
+-- end code from book
+
+
+
+-- code from book
+
+architecture behavioral of tri_state_reg is
+begin
+
+  reg_behavior : process (d, clock, out_enable) is
+                                                  variable stored_byte : byte;
+  begin
+    if clock'event and clock = '1' then
+      stored_byte := d;
+    end if;
+    if out_enable = '1' then
+      q <= stored_byte;
+    else
+      q <= null;
+    end if;
+  end process reg_behavior;
+
+end architecture behavioral;
+
+-- end code from book
+
+
+
+use work.fg_16_04.all;
+
+entity fg_16_05 is
+end entity fg_16_05;
+
+
+architecture test of fg_16_05 is
+
+  signal d1, d2, q : resolved_byte := X"00";
+  signal clk1, clk2, oe1, oe2 : bit := '0';
+
+begin
+
+  dut1 : entity work.tri_state_reg(behavioral)
+    port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
+
+  dut2 : entity work.tri_state_reg(behavioral)
+    port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
+
+  stimulus : process is
+  begin
+    d1 <= X"11";  clk1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    d2 <= X"21";  clk2 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe2 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe1 <= '1', '0' after 5 ns;
+    oe2 <= '1', '0' after 5 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd
new file mode 100644
index 0000000..ba7a774
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd
@@ -0,0 +1,105 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity data_logger is
+end entity data_logger;
+
+
+-- code from book
+
+architecture high_level of data_logger is
+
+  subtype byte is bit_vector(7 downto 0);
+
+  type byte_array is array (integer range <>) of byte;
+
+  function resolver ( bytes : byte_array ) return byte is
+  begin
+    if bytes'length > 0 then
+      return bytes( bytes'left );
+    else
+      return X"00";
+    end if;
+  end function resolver;
+
+  subtype resolved_byte is resolver byte;
+
+  procedure reg ( signal clock, out_enable : in bit;
+                  signal d : in byte;
+                  -- workaround for MTI bugs mt027/mt028
+                  -- signal q : out resolved_byte ) is
+                  signal q : out resolved_byte bus ) is
+    -- end workaround
+    variable stored_byte : byte;
+  begin
+    loop
+      if clock = '1' then
+        stored_byte := d;
+      end if;
+      if out_enable = '1' then
+        q <= stored_byte;
+      else
+        q <= null;
+      end if;
+      wait on clock, out_enable, d;
+    end loop;
+  end procedure reg;
+
+  signal data_bus : resolved_byte bus;
+  -- . . .
+
+  -- not in book
+  signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
+  signal port_a, port_b : byte := X"00";
+  -- end not in book
+
+begin
+
+  a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
+
+  b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    port_a <= X"11";  a_reg_clk <= '1', '0' after 5 ns;  wait for 10 ns;
+    a_reg_read <= '1', '0' after 5 ns;  wait for 10 ns;
+    port_b <= X"21";  b_reg_clk <= '1', '0' after 5 ns;  wait for 10 ns;
+    b_reg_read <= '1', '0' after 5 ns;  wait for 10 ns;
+    a_reg_read <= '1', '0' after 5 ns;
+    b_reg_read <= '1', '0' after 5 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture high_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd
new file mode 100644
index 0000000..f7388b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_16_07 is
+               end entity fg_16_07;
+
+
+               architecture test of fg_16_07 is
+
+                 constant reg0 : std_logic_vector(7 downto 0) := "00000000";
+                 constant reg1 : std_logic_vector(7 downto 0) := "11111111";
+                 signal dbus : std_logic_vector(7 downto 0);
+                 signal reg_sel, read, reg_addr : X01 := '0';
+
+               begin
+
+                 -- code from book
+
+                 reg_read_selector : block (reg_sel = '1' and read = '1') is
+                 begin
+                   dbus <= reg0 when guard and reg_addr = '0' else
+                           reg1 when guard and reg_addr = '1' else
+                           "ZZZZZZZZ";
+                 end block reg_read_selector;
+
+                 -- end code from book
+
+                 stimulus : process is
+                 begin
+                   reg_sel <= '1';  wait for 10 ns;
+                   read <= '1', '0' after 5 ns;  wait for 10 ns;
+                   reg_sel <= '0';  wait for 10 ns;
+                   read <= '1', '0' after 5 ns;  wait for 10 ns;
+                   reg_addr <= '1';  wait for 10 ns;
+                   reg_sel <= '1';  wait for 10 ns;
+                   read <= '1', '0' after 5 ns;  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_08.vhd
new file mode 100644
index 0000000..fed1762
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_08.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity processor_node is
+end entity processor_node;
+
+
+-- code from book
+
+architecture dataflow of processor_node is
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_unique ( drivers : word_vector ) return word is
+  begin
+    if drivers'length > 0 then
+      return drivers(drivers'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_unique;
+
+  -- end not in book
+
+  signal address_bus : resolve_unique word bus;
+  -- . . .
+
+  -- not in book
+  signal cache_miss, dirty, replace_section,
+    snoop_hit, flag_update : bit := '0';
+  constant tag_section0 : bit_vector(11 downto 0) := X"000";
+  constant tag_section1 : bit_vector(11 downto 0) := X"001";
+  constant set_index : bit_vector(15 downto 0) := X"6666";
+  constant snoop_address : word := X"88888888";
+  -- end not in book
+
+begin
+
+  cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
+  begin
+    address_bus <= guarded
+                   tag_section0 & set_index & B"0000" when replace_section = '0' else
+                   tag_section1 & set_index & B"0000";
+  end block cache_to_address_buffer;
+
+  snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
+  begin
+    address_bus <= guarded snoop_address(31 downto 4) & B"0000";
+  end block snoop_to_address_buffer;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    dirty <= '0';  cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    dirty <= '1';  cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    replace_section <= '1';
+    cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns;  wait for 10 ns;
+    flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns;  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture dataflow;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_09.vhd
new file mode 100644
index 0000000..907e8ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_09.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity latch is
+  generic ( width : positive );
+  port ( enable : in bit;
+         d : in bit_vector(0 to width - 1);
+         q : out bit_vector(0 to width - 1) );
+end entity latch;
+
+--------------------------------------------------
+
+architecture behavioral of latch is
+begin
+
+  transfer_control : block ( enable = '1' ) is
+  begin
+    q <= guarded d;
+  end block transfer_control;
+
+end architecture behavioral;
+
+
+-- not in book
+
+entity fg_16_09 is
+end entity fg_16_09;
+
+
+architecture test of fg_16_09 is
+
+  signal enable : bit := '0';
+  signal d, q : bit_vector(0 to 7);
+
+begin
+
+  dut : entity work.latch(behavioral)
+    generic map ( width => 8 )
+    port map ( enable => enable, d => d, q => q );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    d <= X"11";  wait for 10 ns;
+    enable <= '1';  wait for 10 ns;
+    d <= X"AA";  wait for 10 ns;
+    enable <= '0';  wait for 10 ns;
+    d <= X"00";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd
new file mode 100644
index 0000000..25866f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity computer_system is
+end entity computer_system;
+
+
+-- code from book
+
+architecture abstract of computer_system is
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_word ( drivers : word_vector ) return word is
+  begin
+    if drivers'length > 0 then
+      return drivers(drivers'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_word;
+
+  -- end not in book
+
+  -- . . .
+
+  signal address_bus : resolve_word word bus;
+  signal hold_req : bit;
+  -- . . .
+
+  -- not in book
+  signal clk : bit := '0';
+  -- end not in book
+
+begin
+
+  cpu : block is
+
+                signal guard : boolean := false;
+              signal cpu_internal_address : word;
+              -- . . .
+
+  begin
+
+    cpu_address_driver:
+      address_bus <= guarded cpu_internal_address;
+
+    -- . . .    -- other bus drivers
+
+    controller : process is
+                           -- . . .
+    begin
+      -- . . .
+      -- . . .    -- determine when to disable cpu bus drivers
+      guard <= false;
+      wait on clk until hold_req = '0' and clk = '1';
+      guard <= true;  -- re-enable cpu bus drivers
+      -- . . .
+      -- not in book
+      wait until clk = '1';
+      -- end not in book
+    end process controller;
+
+    -- . . .    -- cpu datapath processes
+
+    -- not in book
+    cpu_internal_address <= X"11111111";
+    -- end not in book
+
+  end block cpu;
+
+  -- . . .    -- blocks for DMA and other modules
+
+  -- not in book
+  clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+  -- end not in book
+
+end architecture abstract;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd
new file mode 100644
index 0000000..ba0d4a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity counter is
+
+  generic ( tipd_reset,                   -- input prop delay on reset
+            tipd_clk,                     -- input prop delay on clk
+            topd_q : delay_length;        -- output prop delay on q
+            tsetup_reset,                 -- setup: reset before clk
+            thold_reset : delay_length ); -- hold time: reset after clk
+
+  port ( reset,                           -- synchronous reset input
+         clk : in bit;                    -- edge triggered clock input
+         q : out bit_vector );            -- counter output
+
+end entity counter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_13.vhd
new file mode 100644
index 0000000..df8cbb0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_13.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture detailed_timing of counter is
+
+  signal reset_ipd,                   -- data input port delayed
+    clk_ipd : bit;               -- clock input port delayed
+  signal q_zd : bit_vector(q'range);  -- q output with zero delay
+
+begin
+
+  input_port_delay : block is
+  begin
+    reset_ipd <= reset after tipd_reset;
+    clk_ipd <= clk after tipd_clk;
+  end block input_port_delay;
+
+  functionality : block is
+
+                          function increment ( bv : bit_vector ) return bit_vector is
+    variable result : bit_vector(bv'range) := bv;
+    variable carry : bit := '1';
+  begin
+    for index in result'reverse_range loop
+      result(index) := bv(index) xor carry;
+      carry :=  bv(index) and carry;
+      exit when carry = '0';
+    end loop;
+    return result;
+  end function increment;
+
+  signal next_count : bit_vector(q'range);
+
+  begin
+    next_count <= increment(q_zd) when reset_ipd = '0' else
+                  (others => '0');
+    q_zd <= next_count when clk_ipd = '1' and clk_ipd'event;
+  end block functionality;
+
+  output_port_delay : block is
+  begin
+    q <= q_zd after topd_q;
+  end block output_port_delay;
+
+  timing_checks : block is
+  begin
+    -- check setup time: reset before clk
+    -- . . .
+    -- check hold time: reset after clk
+    -- . . .
+  end block timing_checks;
+
+end architecture detailed_timing;
+
+
+-- not in book
+
+entity fg_16_13 is
+end entity fg_16_13;
+
+
+architecture test of fg_16_13 is
+
+  signal reset, clk : bit := '0';
+  signal q : bit_vector(3 downto 0);
+
+begin
+
+  dut : entity work.counter(detailed_timing)
+    generic map ( tipd_reset => 2 ns,
+                  tipd_clk => 3 ns,
+                  topd_q => 4 ns,
+                  tsetup_reset => 3 ns,
+                  thold_reset => 1 ns )
+    port map ( reset => reset, clk => clk, q => q );
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  reset <= '1' after 62 ns, '0' after 106 ns;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd
new file mode 100644
index 0000000..9b9c543
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity example_entity is
+end entity example_entity;
+
+-- end not in book
+
+
+architecture contrived of example_entity is
+
+  constant sig_width : positive := 16;
+  signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
+  signal sel : bit;
+  -- . . .
+
+begin
+
+  mux : block is
+                generic ( width : positive );
+              generic map ( width => sig_width );
+              port ( d0, d1 : in bit_vector(0 to width - 1);
+                     y : out bit_vector(0 to width - 1);
+                     sel : in bit);
+              port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
+
+              constant zero : bit_vector(0 to width - 1) := ( others => '0' );
+              signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
+
+  begin
+    gated_d0 <= d0 when sel = '0' else zero;
+    gated_d1 <= d1 when sel = '1' else zero;
+    y <= gated_d0 or gated_d1;
+  end block mux;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    s1 <= X"1111";  s2 <= X"2222";  sel <= '0';  wait for 10 ns;
+    s1 <= X"0101";  wait for 10 ns;
+    s2 <= X"0202";  wait for 10 ns;
+    sel <= '1';  wait for 10 ns;
+    s1 <= X"0001";  wait for 10 ns;
+    s2 <= X"0002";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture contrived;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd
new file mode 100644
index 0000000..d92ac85
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity circuit is
+  generic ( inpad_delay, outpad_delay : delay_length );
+  port ( in1, in2, in3 : in bit;  out1, out2 : out bit );
+end entity circuit;
+
+--------------------------------------------------
+
+architecture with_pad_delays of circuit is
+
+  component subcircuit is
+                         port ( a, b : in bit;  y1, y2 : out bit );
+  end component subcircuit;
+
+  signal delayed_in1, delayed_in2, delayed_in3 : bit;
+  signal undelayed_out1, undelayed_out2 : bit;
+
+begin
+
+  input_delays : block is
+  begin
+    delayed_in1 <= in1 after inpad_delay;
+    delayed_in2 <= in2 after inpad_delay;
+    delayed_in3 <= in3 after inpad_delay;
+  end block input_delays;
+
+  functionality : block is
+                          signal intermediate : bit;
+  begin
+    cell1 : component subcircuit
+      port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
+    cell2 : component subcircuit
+      port map ( intermediate, delayed_in3, undelayed_out2, open );
+  end block functionality;
+
+  output_delays : block is
+  begin
+    out1 <= undelayed_out1 after outpad_delay;
+    out2 <= undelayed_out2 after outpad_delay;
+  end block output_delays;
+
+end architecture with_pad_delays;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_16.vhd
new file mode 100644
index 0000000..5efc7f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_16.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_16.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity real_subcircuit is
+  port ( a, b : in bit;  y1, y2 : out bit );
+end entity real_subcircuit;
+
+
+architecture basic of real_subcircuit is
+begin
+  y1 <= a and b after 10 ns;
+  y2 <= a nand b after 10 ns;
+end architecture basic;
+
+-- code from book
+
+configuration full of circuit is
+
+  for with_pad_delays  -- configure the architecture
+
+    for functionality    -- configure the block
+
+      for all : subcircuit
+        use entity work.real_subcircuit(basic);
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration full;
+
+-- end code from book
+
+entity fg_16_16 is
+end entity fg_16_16;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of fg_16_16 is
+
+  signal in1, in2, in3, out1, out2 : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  dut : configuration work.full
+    generic map ( inpad_delay => 2 ns, outpad_delay => 3 ns )
+    port map ( in1 => in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2 );
+
+  stimulus : all_possible_values ( test_vector, 50 ns );
+
+  (in1, in2, in3) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_01.vhd
new file mode 100644
index 0000000..77c95a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_01.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_01 is
+
+end entity ch_17_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_01 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type natural_ptr is access natural;
+
+          variable count : natural_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    count := new natural;
+
+    count.all := 10;
+
+    if count.all = 0 then
+      -- . . .
+      -- not in book
+      report "count.all = 0";
+      -- end not in book
+    end if;
+
+    -- end of code from book
+
+    if count.all /= 0 then
+      report "count.all /= 0";
+    end if;
+
+    -- code from book:
+
+    count := new natural'(10);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_02.vhd
new file mode 100644
index 0000000..cdf4ae7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_02.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_02 is
+
+end entity ch_17_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_02 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type stimulus_record is record
+                                      stimulus_time : time;
+                                      stimulus_value : bit_vector(0 to 3);
+                                    end record stimulus_record;
+
+          type stimulus_ptr is access stimulus_record;
+
+          variable bus_stimulus : stimulus_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    bus_stimulus := new stimulus_record'( 20 ns, B"0011" );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_03.vhd
new file mode 100644
index 0000000..7ef3705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_03.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_03 is
+
+end entity ch_17_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_03 is
+begin
+
+
+  process is
+
+            type natural_ptr is access natural;
+
+          -- code from book:
+
+          variable count1, count2 : natural_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    count1 := new natural'(5);
+    count2 := new natural'(10);
+
+    count2 := count1;
+
+    count1.all := 20;
+
+    -- end of code from book
+
+    assert
+      -- code from book:
+      count1 = count2
+      -- end of code from book
+      ;
+
+    -- code from book:
+
+    count1 := new natural'(30);
+    count2 := new natural'(30);
+
+    -- end of code from book
+
+    assert count1 = count2;
+
+    assert
+      -- code from book:
+      count1.all = count2.all
+      -- end of code from book
+      ;
+
+    -- code from book:
+
+    if count1 /= null then
+      count1.all := count1.all + 1;
+    end if;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_04.vhd
new file mode 100644
index 0000000..043cc7b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_04.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_04 is
+
+end entity ch_17_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_04 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type stimulus_record is record
+                                      stimulus_time : time;
+                                      stimulus_value : bit_vector(0 to 3);
+                                    end record stimulus_record;
+
+          type stimulus_ptr is access stimulus_record;
+
+          variable bus_stimulus : stimulus_ptr;
+
+          -- end of code from book
+
+  begin
+
+    bus_stimulus := new stimulus_record;
+
+    bus_stimulus.all := stimulus_record'(20 ns, B"0011");
+
+    report time'image(bus_stimulus.all.stimulus_time);
+
+    report time'image(bus_stimulus.stimulus_time);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_05.vhd
new file mode 100644
index 0000000..b567349
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_05.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_05 is
+
+end entity ch_17_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_05 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type coordinate is array (1 to 3) of real;
+          type coordinate_ptr is access coordinate;
+
+          variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
+
+          type time_array is array (positive range <>) of time;
+          variable activation_times : time_array(1 to 100);
+
+          -- end of code from book
+
+  begin
+
+    report real'image( origin(1) );
+    report real'image( origin(2) );
+    report real'image( origin(3) );
+    report real'image( origin.all(1) );
+
+    wait;
+  end process;
+
+
+  process is
+
+            type time_array is array (positive range <>) of time;
+
+          -- code from book:
+
+          type time_array_ptr is access time_array;
+
+          variable activation_times : time_array_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    activation_times := new time_array'(10 us, 15 us, 40 us);
+
+    activation_times := new time_array'( activation_times.all
+                                         & time_array'(70 us, 100 us) );
+
+    activation_times := new time_array(1 to 10);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_06.vhd
new file mode 100644
index 0000000..5ef2bac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_06.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_06 is
+
+end entity ch_17_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_06 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type value_cell is record
+                                 value : bit_vector(0 to 3);
+                                 next_cell : value_ptr;
+                               end record value_cell;
+
+          type value_ptr is access value_cell;
+
+          -- end of code from book
+
+  begin
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd
new file mode 100644
index 0000000..e2d8426
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_07 is
+
+end entity ch_17_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_07 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list : value_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    if value_list /= null then
+      -- . . .       -- do something with the list
+      -- not in book
+      report "value_list /= null";
+      -- end not in book
+    end if;
+
+    value_list := new value_cell'( B"1000", value_list );
+
+    value_list := new value_cell'( B"0010", value_list );
+
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_08.vhd
new file mode 100644
index 0000000..b47fc7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_08.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_08 is
+
+end entity ch_17_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_08 is
+
+  type T is (t1, t2, t3);
+
+  -- code from book:
+
+  type T_ptr is access T;
+
+  procedure deallocate ( P : inout T_ptr );
+
+  -- end of code from book
+
+  procedure deallocate ( P : inout T_ptr ) is
+  begin
+    null;
+  end procedure deallocate;
+
+  -- end of code from book
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_09.vhd
new file mode 100644
index 0000000..5797333
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_09.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_09 is
+
+end entity ch_17_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_09 is
+
+begin
+
+  process is
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list, cell_to_be_deleted : value_ptr;
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- code from book:
+
+    cell_to_be_deleted := value_list;
+    value_list := value_list.next_cell;
+    deallocate(cell_to_be_deleted);
+
+    while value_list /= null loop
+      cell_to_be_deleted := value_list;
+      value_list := value_list.next_cell;
+      deallocate(cell_to_be_deleted);
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd
new file mode 100644
index 0000000..0ba75ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_17_05 is
+
+end entity fg_17_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of fg_17_05 is
+
+  signal s : bit_vector(0 to 3);
+
+begin
+
+  process is
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list, current_cell : value_ptr;
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- code from book:
+
+    current_cell := value_list;
+    while current_cell /= null loop
+      s <= current_cell.value;
+      wait for 10 ns;
+      current_cell := current_cell.next_cell;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_07.vhd
new file mode 100644
index 0000000..695419f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_07.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_17_07 is
+
+end entity fg_17_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of fg_17_07 is
+
+  signal s : bit_vector(0 to 3);
+
+begin
+
+  process is
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list, current_cell : value_ptr;
+          variable search_value : bit_vector(0 to 3);
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    search_value := B"0010";
+
+    -- code from book:
+
+    current_cell := value_list;
+    while current_cell /= null
+      and current_cell.value /= search_value loop
+      current_cell := current_cell.next_cell;
+    end loop;
+    assert current_cell /= null
+      report "search for value failed";
+
+    -- end of code from book
+
+    search_value := B"1111";
+
+    current_cell := value_list;
+    while current_cell /= null
+      and current_cell.value /= search_value loop
+      current_cell := current_cell.next_cell;
+    end loop;
+    assert current_cell /= null
+      report "search for value failed";
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_08.vhd
new file mode 100644
index 0000000..a934c82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_08.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package bounded_buffer_adt is
+
+  subtype byte is bit_vector(0 to 7);
+
+  type bounded_buffer_object;  -- private
+
+  type bounded_buffer is access bounded_buffer_object;
+
+  function new_bounded_buffer ( size : in positive ) return bounded_buffer;
+  -- creates a bounded buffer object with 'size' bytes of storage
+
+  procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+                         is_empty : out boolean );
+  -- tests whether the bounded buffer is empty (i.e., no data to read)
+
+  procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+                        is_full : out boolean );
+  -- tests whether the bounded buffer is full (i.e., no data can be written)
+
+  procedure write ( the_bounded_buffer : inout bounded_buffer;  data : in byte );
+  -- if the bounded buffer is not full, writes the data
+  -- if it is full, assertion violation with severity failure
+
+  procedure read ( the_bounded_buffer : inout bounded_buffer;  data : out byte );
+  -- if the bounded buffer is not empty, read the first byte of data
+  -- if it is empty, assertion violation with severity failure
+
+  --------------------------------------------------
+
+  -- the following types are private to the ADT
+
+  type store_array is array (natural range <>) of byte;
+
+  type store_ptr is access store_array;
+
+  type bounded_buffer_object is record
+                                  byte_count : natural;
+                                  head_index, tail_index : natural;
+                                  store : store_ptr;
+                                end record bounded_buffer_object;
+
+end package bounded_buffer_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_09.vhd
new file mode 100644
index 0000000..d9e3a4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_09.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_17_09 is
+end entity fg_17_09;
+
+
+
+architecture test of fg_17_09 is
+begin
+
+  -- code from book
+
+  receiver : process is
+
+                       use work.bounded_buffer_adt.all;
+
+                     variable receive_buffer : bounded_buffer := new_bounded_buffer(2048);
+                     variable buffer_overrun, buffer_underrun : boolean;
+                     -- . . .
+
+                     -- not in book
+                     variable received_byte, check_byte : byte;
+                     -- end not in book
+
+  begin
+    -- . . .
+
+    test_full(receive_buffer, buffer_overrun);
+    if not buffer_overrun then
+      write(receive_buffer, received_byte);
+    end if;
+    -- . . .
+
+    test_empty(receive_buffer, buffer_underrun);
+    if not buffer_underrun then
+      read(receive_buffer, check_byte);
+    end if;
+    -- . . .
+
+  end process receiver;
+
+  -- end code from book
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd
new file mode 100644
index 0000000..cac8c5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd
@@ -0,0 +1,164 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package body bounded_buffer_adt is
+
+  function new_bounded_buffer ( size : in positive ) return bounded_buffer is
+  begin
+    return new bounded_buffer_object'(
+      byte_count => 0, head_index => 0, tail_index => 0,
+      store => new store_array(0 to size - 1) );
+  end function new_bounded_buffer;
+
+  procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+                         is_empty : out boolean ) is
+  begin
+    is_empty := the_bounded_buffer.byte_count = 0;
+  end procedure test_empty;
+
+  procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+                        is_full : out boolean ) is
+  begin
+    is_full := the_bounded_buffer.byte_count = the_bounded_buffer.store'length;
+  end procedure test_full;
+
+  procedure write ( the_bounded_buffer : inout bounded_buffer;  data : in byte ) is
+    variable buffer_full : boolean;
+  begin
+    test_full(the_bounded_buffer, buffer_full);
+    if buffer_full then
+      report "write to full bounded buffer" severity failure;
+    else
+      the_bounded_buffer.store(the_bounded_buffer.tail_index) := data;
+      the_bounded_buffer.tail_index := (the_bounded_buffer.tail_index + 1)
+                                       mod the_bounded_buffer.store'length;
+      the_bounded_buffer.byte_count := the_bounded_buffer.byte_count + 1;
+    end if;
+  end procedure write;
+
+  procedure read ( the_bounded_buffer : inout bounded_buffer;  data : out byte ) is
+    variable buffer_empty : boolean;
+  begin
+    test_empty(the_bounded_buffer, buffer_empty);
+    if buffer_empty then
+      report "read from empty bounded buffer" severity failure;
+    else
+      data := the_bounded_buffer.store(the_bounded_buffer.head_index);
+      the_bounded_buffer.head_index := (the_bounded_buffer.head_index + 1)
+                                       mod the_bounded_buffer.store'length;
+      the_bounded_buffer.byte_count := the_bounded_buffer.byte_count - 1;
+    end if;
+  end procedure read;
+
+end package body bounded_buffer_adt;
+
+
+
+-- not in book
+
+entity fg_17_11 is
+end entity fg_17_11;
+
+
+architecture test of fg_17_11 is
+begin
+
+  process is
+
+            use work.bounded_buffer_adt.all;
+
+          variable buf : bounded_buffer := new_bounded_buffer(4);
+          variable empty, full : boolean;
+          variable d : byte;
+
+  begin
+    test_empty(buf, empty);
+    assert empty;
+    test_full(buf, full);
+    assert not full;
+
+    write(buf, X"01");
+    write(buf, X"02");
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert not full;
+
+    write(buf, X"03");
+    write(buf, X"04");
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert full;
+
+    write(buf, X"05");
+
+    read(buf, d);
+    read(buf, d);
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert not full;
+
+    read(buf, d);
+    read(buf, d);
+
+    test_empty(buf, empty);
+    assert empty;
+    test_full(buf, full);
+    assert not full;
+
+    read(buf, d);
+
+    write(buf, X"06");
+    write(buf, X"07");
+    write(buf, X"08");
+    read(buf, d);
+    read(buf, d);
+    write(buf, X"09");
+    read(buf, d);
+    write(buf, X"0A");
+    read(buf, d);
+    write(buf, X"0B");
+    read(buf, d);
+    write(buf, X"0C");
+    read(buf, d);
+    write(buf, X"0D");
+    read(buf, d);
+    write(buf, X"0E");
+    read(buf, d);
+    write(buf, X"0F");
+    read(buf, d);
+
+    wait;
+  end process;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_13.vhd
new file mode 100644
index 0000000..a40f080
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_13.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package stimulus_types is
+
+                 constant stimulus_vector_length : positive := 10;
+
+                 type stimulus_element is record
+                                            application_time : delay_length;
+                                            pattern : std_logic_vector(0 to stimulus_vector_length - 1);
+                                          end record stimulus_element;
+
+                 function stimulus_key ( stimulus : stimulus_element ) return delay_length;
+
+               end package stimulus_types;
+
+--------------------------------------------------
+
+               package body stimulus_types is
+
+                 function stimulus_key ( stimulus : stimulus_element ) return delay_length is
+                 begin
+                   return stimulus.application_time;
+                 end function stimulus_key;
+
+               end package body stimulus_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_01.vhd
new file mode 100644
index 0000000..8d37eb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_01.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_01 is
+
+end entity ch_18_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_01 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type integer_file is file of integer;
+
+          file lookup_table_file : integer_file is "lookup-values";
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            -- code from book:
+
+            type file_open_kind is (read_mode, write_mode, append_mode);
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+
+          -- code from book:
+
+          type file_type is file of element_type;
+
+          procedure read ( file f : file_type;  value : out element_type );
+
+          function endfile ( file f : file_type ) return boolean;
+
+          -- end of code from book
+
+          procedure read ( file f : file_type;  value : out element_type ) is
+          begin
+          end;
+
+          function endfile ( file f : file_type ) return boolean is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_02.vhd
new file mode 100644
index 0000000..727c908
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_02.vhd
@@ -0,0 +1,133 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_02_a is
+end entity ch_18_02_a;
+
+
+architecture writer of ch_18_02_a is
+begin
+
+  process is
+            type bit_vector_file is file of bit_vector;
+          file vectors : bit_vector_file open write_mode is "vectors.dat";
+  begin
+    write(vectors, bit_vector'(""));
+    write(vectors, bit_vector'("1"));
+    write(vectors, bit_vector'("10"));
+    write(vectors, bit_vector'("011"));
+    write(vectors, bit_vector'("0100"));
+    write(vectors, bit_vector'("00101"));
+    write(vectors, bit_vector'("000110"));
+    write(vectors, bit_vector'("0000111"));
+    write(vectors, bit_vector'("00001000"));
+    write(vectors, bit_vector'("111111111111111111111111111111111111111111111111111111111111111111111111"));
+    wait;
+  end process;
+
+end architecture writer;
+
+
+----------------------------------------------------------------
+
+
+
+entity ch_18_02 is
+
+end entity ch_18_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_02 is
+begin
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+          type file_type is file of element_type;
+
+          -- code from book:
+
+          type bit_vector_file is file of bit_vector;
+
+          procedure read ( file f : file_type;
+                           value : out element_type;  length : out natural );
+
+          -- end of code from book
+
+          procedure read ( file f : file_type;
+                           value : out element_type;  length : out natural ) is
+          begin
+          end;
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            type bit_vector_file is file of bit_vector;
+
+          -- code from book:
+
+          file vectors : bit_vector_file open read_mode is "vectors.dat";
+          variable next_vector : bit_vector(63 downto 0);
+          variable actual_len : natural;
+
+          -- end of code from book
+
+          variable lost : boolean;
+
+  begin
+    while not endfile(vectors) loop
+
+      -- code from book:
+
+      read(vectors, next_vector, actual_len);
+
+      -- end of code from book
+
+      lost :=
+        -- code from book:
+
+        actual_len > next_vector'length
+
+        -- end of code from book
+        ;
+
+    end loop;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_03.vhd
new file mode 100644
index 0000000..ead25f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_03.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_03 is
+
+end entity ch_18_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_03 is
+begin
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+
+          type file_type is file of element_type;
+
+          -- code from book:
+
+          procedure write ( file f : file_type;  value : in element_type );
+
+          -- end of code from book
+
+          procedure write ( file f : file_type;  value : in element_type ) is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_04.vhd
new file mode 100644
index 0000000..655ab0d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_04.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_04 is
+
+end entity ch_18_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_04 is
+begin
+
+
+  process is
+
+            type data_file_type is file of character;
+          variable ch : character;
+
+          -- code from book:
+
+          procedure write_to_file is
+            file data_file : data_file_type open write_mode is "datafile";
+          begin
+            -- . . .
+            -- not in book
+            write(data_file, ch);
+            -- end not in book
+          end procedure write_to_file;
+
+          -- end of code from book
+
+  begin
+    ch := 'A';
+    write_to_file;
+    ch := 'B';
+    write_to_file;
+    ch := 'C';
+    write_to_file;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_05.vhd
new file mode 100644
index 0000000..65a345f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_05.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_05 is
+
+end entity ch_18_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_05 is
+
+  type log_file is file of string;
+
+  -- code from book:
+
+  file log_info : log_file open write_mode is "logfile";
+
+  -- end of code from book
+
+begin
+
+
+  process is
+  begin
+    write(log_info, string'("AAAA"));
+    wait for 1 ns;
+    write(log_info, string'("BBBB"));
+    wait;
+  end process;
+
+
+  process is
+  begin
+    write(log_info, string'("CCCC"));
+    wait for 1 ns;
+    write(log_info, string'("DDDD"));
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_06.vhd
new file mode 100644
index 0000000..7d324a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_06.vhd
@@ -0,0 +1,149 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_06 is
+
+end entity ch_18_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_06 is
+
+  type integer_file is file of integer;
+
+begin
+
+
+  process is
+
+            -- code from book:
+
+            file lookup_table_file, result_file : integer_file;
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+
+          -- code from book:
+
+          type file_type is file of element_type;
+
+          procedure file_open ( file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode );
+
+          -- end of code from book
+
+          procedure file_open ( file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode ) is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            -- code from book:
+
+            file lookup_table_file : integer_file open read_mode is "lookup-values";
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            -- code from book:
+
+            file lookup_table_file : integer_file;
+          -- . . .
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    file_open ( lookup_table_file,
+                external_name => "lookup-values", open_kind => read_mode );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+          type file_type is file of element_type;
+
+          -- code from book:
+
+          type file_open_status is (open_ok, status_error, name_error, mode_error);
+
+          procedure file_open ( status : out file_open_status;
+                                file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode );
+
+          procedure file_close ( file f : file_type );
+
+          -- end of code from book
+
+          procedure file_open ( status : out file_open_status;
+                                file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode ) is
+          begin
+          end;
+
+          procedure file_close ( file f : file_type ) is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_07.vhd
new file mode 100644
index 0000000..5b41bc6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_07.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_07_a is
+end ch_18_07_a;
+
+
+architecture writer of ch_18_07_a is
+begin
+
+  process
+    type transform_file is file of real;
+--    file initial_transforms : transform_file is out "transforms.ini";
+    file initial_transforms : transform_file open WRITE_MODE is "transforms.ini";
+  begin
+    for i in 1 to 12 loop
+      write(initial_transforms, real(i));
+    end loop;
+    wait;
+  end process;
+
+end writer;
+
+
+
+
+entity ch_18_07 is
+end ch_18_07;
+
+
+architecture test of ch_18_07 is
+begin
+
+  process
+
+    type transform_array is array (1 to 3, 1 to 3) of real;
+    variable transform1, transform2 : transform_array;
+
+    type transform_file is file of real;
+--    file initial_transforms : transform_file is in "transforms.ini";
+    file initial_transforms: transform_file open READ_MODE is "transforms.ini";
+
+    -- code from book
+
+    procedure read_transform
+      ( variable f : in transform_file;
+        variable transform : out transform_array ) is -- . . .
+
+      -- end code from book
+
+    begin
+      for i in transform'range(1) loop
+        for j in transform'range(2) loop
+          if endfile(f) then
+            assert false
+              report "unexpected end of file in read_transform - "
+              & "some array elements not read"
+              severity error;
+            return;
+          end if;
+          read ( f, transform(i, j) );
+        end loop;
+      end loop;
+    end read_transform;
+
+  begin
+
+    read_transform ( initial_transforms, transform1 );
+    read_transform ( initial_transforms, transform2 );
+
+    wait;
+  end process;
+
+end test;
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_08.vhd
new file mode 100644
index 0000000..9410949
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_08.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_08 is
+
+end entity ch_18_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_08 is
+begin
+
+
+  process is
+
+            use std.textio.all;
+          file f : text open read_mode is "ch_18_08.dat";
+          variable L : line;
+          variable ch : character;
+          variable s : string(1 to 5);
+          variable i : integer;
+          variable r : real;
+
+  begin
+
+    readline(f, L);
+    read(L, ch);
+    report character'image(ch);
+    read(L, ch);
+    report character'image(ch);
+
+    readline(f, L);
+    read(L, s);
+    report '"' & s & '"';
+    read(L, s);
+    report '"' & s & '"';
+
+    readline(f, L);
+
+    -- code from book:
+
+    if L'length < s'length then
+      read(L, s(1 to L'length));
+    else
+      read(L, s);
+    end if;
+
+    -- end of code from book
+
+    report '"' & s & '"';
+
+    readline(f, L);
+    read(L, i);
+    report integer'image(i);
+    read(L, r);
+    report real'image(r);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_09.vhd
new file mode 100644
index 0000000..b93e134
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_09.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_09 is
+
+end entity ch_18_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_09 is
+begin
+
+
+  process is
+
+            use std.textio.all;
+          variable L : line;
+
+  begin
+
+    write(L, 42, justified => left, field => 5);
+    writeline(output, L);
+    write(L, 42, justified => right, field => 5);
+    writeline(output, L);
+    write(L, 123, field => 2);
+    writeline(output, L);
+
+    -- code from book:
+
+    write ( L, string'( "fred" ) );
+    write ( L, ' ' );
+    write ( L, bit_vector'( X"3A" ) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    write(L, 3.14159, digits => 2);
+    writeline(output, L);
+    write(L, 123.4567, digits => 0);
+    writeline(output, L);
+
+    write(L, 40 ns, unit => ps);
+    writeline(output, L);
+    write(L, 23 us, unit => ms);
+    writeline(output, L);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_10.vhd
new file mode 100644
index 0000000..93a2cb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_10.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_10 is
+
+end entity ch_18_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_10 is
+begin
+
+
+  process is
+
+            use std.textio.all;
+          variable L : line;
+
+          -- code from book:
+
+          type speed_category is (stopped, slow, fast, maniacal);
+          variable speed : speed_category;
+
+          -- end of code from book
+
+  begin
+
+    speed := stopped;
+
+    -- code from book:
+
+    write ( L, speed_category'image(speed) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    speed := slow;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := fast;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := maniacal;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+
+    -- code from book:
+
+    readline( input, L );
+    speed := speed_category'value(L.all);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_01.vhd
new file mode 100644
index 0000000..0b7bf14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_01.vhd
@@ -0,0 +1,139 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_18_01_a is
+               end entity fg_18_01_a;
+
+
+               architecture writer of fg_18_01_a is
+               begin
+
+                 process is
+
+                           subtype word is std_logic_vector(0 to 7);
+                         type load_file_type is file of word;
+                         file load_file : load_file_type open write_mode is "fg_18_01.dat";
+
+                 begin
+                   write(load_file, word'(X"00"));
+                   write(load_file, word'(X"01"));
+                   write(load_file, word'(X"02"));
+                   write(load_file, word'(X"03"));
+                   write(load_file, word'(X"04"));
+                   write(load_file, word'(X"05"));
+                   write(load_file, word'(X"06"));
+                   write(load_file, word'(X"07"));
+                   write(load_file, word'(X"08"));
+                   write(load_file, word'(X"09"));
+                   write(load_file, word'(X"0A"));
+                   write(load_file, word'(X"0B"));
+                   write(load_file, word'(X"0C"));
+                   write(load_file, word'(X"0D"));
+                   write(load_file, word'(X"0E"));
+                   write(load_file, word'(X"0F"));
+
+                   wait;
+                 end process;
+
+               end architecture writer;
+
+-- end not in book
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity ROM is
+                 generic ( load_file_name : string );
+                 port ( sel : in std_logic;
+                        address : in std_logic_vector;
+                        data : inout std_logic_vector );
+               end entity ROM;
+
+--------------------------------------------------
+
+               architecture behavioral of ROM is
+
+               begin
+
+                 behavior : process is
+
+                                      subtype word is std_logic_vector(0 to data'length - 1);
+                                    type storage_array is
+                                      array (natural range 0 to 2**address'length - 1) of word;
+                                    variable storage : storage_array;
+                                    variable index : natural;
+                                    -- . . .    -- other declarations
+
+                                    type load_file_type is file of word;
+                                    file load_file : load_file_type open read_mode is load_file_name;
+
+                 begin
+
+                   -- load ROM contents from load_file
+                   index := 0;
+                   while not endfile(load_file) loop
+                     read(load_file, storage(index));
+                     index := index + 1;
+                   end loop;
+
+                   -- respond to ROM accesses
+                   loop
+                     -- . . .
+                   end loop;
+
+                 end process behavior;
+
+               end architecture behavioral;
+
+
+
+-- not in book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_18_01 is
+               end entity fg_18_01;
+
+
+               architecture test of fg_18_01 is
+
+                 signal sel : std_logic;
+                 signal address : std_logic_vector(3 downto 0);
+                 signal data : std_logic_vector(0 to 7);
+
+               begin
+
+                 dut : entity work.ROM(behavioral)
+                   generic map ( load_file_name => "fg_18_01.dat" )
+                   port map ( sel, address, data );
+
+               end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd
new file mode 100644
index 0000000..f00f099
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_02_a is
+end entity fg_18_02_a;
+
+
+architecture writer of fg_18_02_a is
+begin
+
+  process is
+            type packet_file is file of bit_vector;
+          file stimulus_file : packet_file open write_mode is "test packets";
+  begin
+    write(stimulus_file, X"6C");
+    write(stimulus_file, X"05");
+    write(stimulus_file, X"3");
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity fg_18_02 is
+end entity fg_18_02;
+
+
+architecture test of fg_18_02 is
+
+  signal stimulus_network, stimulus_clock : bit;
+
+begin
+
+  clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
+
+  -- code from book
+
+  stimulate_network : process is
+
+                                type packet_file is file of bit_vector;
+                              file stimulus_file : packet_file open read_mode is "test packets";
+
+                              -- variable packet : bit_vector(1 to 2048);
+                              -- not in book (for testing only)
+                              variable packet : bit_vector(1 to 8);
+                              -- end not in book
+                              variable packet_length : natural;
+
+  begin
+
+    while not endfile(stimulus_file) loop
+
+      read(stimulus_file, packet, packet_length);
+      if packet_length > packet'length then
+        report "stimulus packet too long - ignored" severity warning;
+      else
+        for bit_index in 1 to packet_length loop
+          wait until stimulus_clock = '1';
+          stimulus_network <= not stimulus_network;
+          wait until stimulus_clock = '0';
+          stimulus_network <= stimulus_network xor packet(bit_index);
+        end loop;
+      end if;
+
+    end loop;
+
+    wait;  -- end of stimulation: wait forever
+
+  end process stimulate_network;
+
+  -- code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd
new file mode 100644
index 0000000..b496231
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_03.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+package CPU_types is
+
+  subtype word is bit_vector(0 to 31);
+  subtype byte is bit_vector(0 to 7);
+
+  alias convert_to_natural is
+    bv_utilities.bv_arithmetic.bv_to_natural [ bit_vector return natural ];
+
+  constant halt_opcode : byte := "00000000";
+
+  type code_array is array (natural range <>) of word;
+  constant code : code_array := ( X"01000000", X"01000000", X"02000000",
+				  X"01000000", X"01000000", X"02000000",
+				  X"00000000" );
+
+end package CPU_types;
+
+use work.CPU_types.all;
+
+entity CPU is
+end entity CPU;
+
+-- code from book
+
+architecture instrumented of CPU is
+
+  type count_file is file of natural;
+  file instruction_counts : count_file open write_mode is "instructions";
+
+begin
+
+  interpreter : process is
+
+                          variable IR : word;
+                        alias opcode : byte is IR(0 to 7);
+                        variable opcode_number : natural;
+                        type counter_array is array (0 to 2**opcode'length - 1) of natural;
+                        variable counters : counter_array := (others => 0);
+                        -- . . .
+
+                        -- not in book
+                        variable code_index : natural := 0;
+                        -- end not in book
+
+  begin
+
+    -- . . .    -- initialize the instruction set interpreter
+
+    instruction_loop : loop
+
+      -- . . .    -- fetch the next instruction into IR
+
+      -- not in book
+      IR := code(code_index);
+      code_index := code_index + 1;
+      -- end not in book
+
+      -- decode the instruction
+      opcode_number := convert_to_natural(opcode);
+      counters(opcode_number) := counters(opcode_number) + 1;
+      -- . . .
+
+      -- execute the decoded instruction
+      case opcode is
+        -- . . .
+        when halt_opcode => exit instruction_loop;
+                            -- . . .
+                            -- not in book
+        when others => null;
+                       -- end not in book
+      end case;
+
+    end loop instruction_loop;
+
+    for index in counters'range loop
+      write(instruction_counts, counters(index));
+    end loop;
+    wait;  -- program finished, wait forever
+
+  end process interpreter;
+
+end architecture instrumented;
+
+-- code from book
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd
new file mode 100644
index 0000000..bfe6f09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd
@@ -0,0 +1,155 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity cache is
+  generic ( cache_size, block_size, associativity : positive;
+            benchmark_name : string(1 to 10) );
+  port ( halt : in bit );
+end entity cache;
+
+
+
+architecture instrumented of cache is
+
+begin
+
+  -- code from book
+
+  cache_monitor : process is
+
+                            type measurement_record is
+                          record
+                            cache_size, block_size, associativity : positive;
+                            benchmark_name : string(1 to 10);
+                            miss_rate : real;
+                            ave_access_time : delay_length;
+                          end record;
+                          type measurement_file is file of measurement_record;
+                          file measurements : measurement_file
+                            open append_mode is "cache-measurements";
+                          -- . . .
+
+                          -- not in book
+                          constant miss_count : natural := 100;
+                          constant total_accesses : natural := 1000;
+                          constant total_delay : delay_length := 2400 ns;
+                          -- end not in book
+
+  begin
+    -- . . .
+    loop
+      -- . . .
+      -- not in book
+      wait on halt;
+      -- end not in book
+      exit when halt = '1';
+      -- . . .
+    end loop;
+
+    write ( measurements,
+            measurement_record'(
+              -- write values of generics for this run
+              cache_size, block_size, associativity, benchmark_name,
+              -- calculate performance metrics
+              miss_rate => real(miss_count) / real(total_accesses),
+              ave_access_time => total_delay / total_accesses ) );
+    wait;
+
+  end process cache_monitor;
+
+  -- end code from book
+
+end architecture instrumented;
+
+
+
+entity fg_18_04 is
+end entity fg_18_04;
+
+
+
+architecture test of fg_18_04 is
+
+  signal halt : bit := '0';
+
+begin
+
+  dut : entity work.cache(instrumented)
+    generic map ( cache_size => 128*1024, block_size => 16,
+                  associativity => 2, benchmark_name => "dhrystone " )
+    port map ( halt => halt );
+
+  halt <= '1' after 10 ns;
+
+end architecture test;
+
+
+
+entity fg_18_04_a is
+end entity fg_18_04_a;
+
+
+architecture reader of fg_18_04_a is
+begin
+
+  process is
+
+            type measurement_record is
+          record
+            cache_size, block_size, associativity : positive;
+            benchmark_name : string(1 to 10);
+            miss_rate : real;
+            ave_access_time : delay_length;
+          end record;
+          type measurement_file is file of measurement_record;
+          file measurements : measurement_file open read_mode is "cache-measurements";
+          variable measurement : measurement_record;
+
+          use std.textio.all;
+          variable L : line;
+
+  begin
+    while not endfile(measurements) loop
+      read(measurements, measurement);
+      write(L, measurement.cache_size);
+      write(L, ' ');
+      write(L, measurement.block_size);
+      write(L, ' ');
+      write(L, measurement.associativity);
+      write(L, ' ');
+      write(L, measurement.benchmark_name);
+      write(L, ' ');
+      write(L, measurement.miss_rate);
+      write(L, ' ');
+      write(L, measurement.ave_access_time);
+      writeline(output, L);
+
+    end loop;
+
+    wait;
+  end process;
+
+end architecture reader;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd
new file mode 100644
index 0000000..e20b30f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_05_a is
+end entity fg_18_05_a;
+
+
+architecture writer of fg_18_05_a is
+begin
+
+  process is
+
+            type integer_file is file of integer;
+          file data_file : integer_file open write_mode is "coeff-data";
+
+  begin
+    write(data_file, 0);
+    write(data_file, 1);
+    write(data_file, 2);
+    write(data_file, 3);
+    write(data_file, 4);
+    write(data_file, 5);
+    write(data_file, 6);
+    write(data_file, 7);
+    write(data_file, 8);
+    write(data_file, 9);
+    write(data_file, 10);
+    write(data_file, 11);
+    write(data_file, 12);
+    write(data_file, 13);
+    write(data_file, 14);
+    write(data_file, 15);
+    write(data_file, 16);
+    write(data_file, 17);
+    write(data_file, 18);
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity fg_18_05 is
+end entity fg_18_05;
+
+
+architecture test of fg_18_05 is
+begin
+
+  process is
+
+            -- code from book (in text)
+
+            type integer_vector is array (integer range <>) of integer;
+
+          -- end code from book
+
+          -- code from book (Figure 18-5)
+
+          impure function read_array ( file_name : string;  array_length : natural )
+            return integer_vector is
+            type integer_file is file of integer;
+            file data_file : integer_file open read_mode is file_name;
+            variable result : integer_vector(1 to array_length) := (others => 0);
+            variable index : integer := 1;
+          begin
+            while not endfile(data_file) and index <= array_length loop
+              read(data_file, result(index));
+              index := index + 1;
+            end loop;
+            return result;
+          end function read_array;
+
+          -- end code from book
+
+          -- code from book (in text)
+
+          constant coeffs : integer_vector := read_array("coeff-data", 16);
+
+          -- end code from book
+
+  begin
+    wait;
+  end process;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_06.vhd
new file mode 100644
index 0000000..9f4e500
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_06.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_18_06 is
+               end entity fg_18_06;
+
+
+               architecture test of fg_18_06 is
+
+
+
+               begin
+
+                 -- code from book
+
+                 stimulus_generator : process is
+
+                                                type directory_file is file of string;
+                                              file directory : directory_file open read_mode is "stimulus-directory";
+                                              variable file_name : string(1 to 50);
+                                              variable file_name_length : natural;
+                                              variable open_status : file_open_status;
+
+                                              subtype stimulus_vector is std_logic_vector(0 to 9);
+                                              type stimulus_file is file of stimulus_vector;
+                                              file stimuli : stimulus_file;
+                                              variable current_stimulus : stimulus_vector;
+                                              -- . . .
+
+                 begin
+                   file_loop : while not endfile(directory) loop
+                     read( directory, file_name, file_name_length );
+                     if file_name_length > file_name'length then
+                       report "file name too long: " & file_name & "... - file skipped"
+                         severity warning;
+                       next file_loop;
+                     end if;
+                     file_open ( open_status, stimuli,
+                                 file_name(1 to file_name_length), read_mode );
+                     if open_status /= open_ok then
+                       report file_open_status'image(open_status) & " while opening file "
+                         & file_name(1 to file_name_length) & " - file skipped"
+                         severity warning;
+                       next file_loop;
+                     end if;
+                     stimulus_loop : while not endfile(stimuli) loop
+                       read(stimuli, current_stimulus);
+                       -- . . .    -- apply the stimulus
+                     end loop stimulus_loop;
+                     file_close(stimuli);
+                   end loop file_loop;
+                   wait;
+                 end process stimulus_generator;
+
+                 -- end code from book
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_07.vhd
new file mode 100644
index 0000000..683c15a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_07.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_07_a is
+end entity fg_18_07_a;
+
+
+architecture writer of fg_18_07_a is
+begin
+
+  process is
+            type transform_file is file of real;
+          file initial_transforms : transform_file open write_mode is "transforms.ini";
+  begin
+    for i in 1 to 50 loop
+      write(initial_transforms, real(i));
+    end loop;
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+
+entity fg_18_07 is
+end entity fg_18_07;
+
+
+architecture test of fg_18_07 is
+begin
+
+  process is
+
+            -- code from book (in text)
+
+            type transform_array is array (1 to 3, 1 to 3) of real;
+          variable transform1, transform2 : transform_array;
+
+          type transform_file is file of real;
+          file initial_transforms : transform_file
+            open read_mode is "transforms.ini";
+
+          -- end code from book
+
+          -- code from book (Figure 18-7)
+
+          procedure read_transform ( file f : transform_file;
+                                     variable transform : out transform_array ) is
+          begin
+            for i in transform'range(1) loop
+              for j in transform'range(2) loop
+                if endfile(f) then
+                  report "unexpected end of file in read_transform - "
+                    & "some array elements not read"
+                    severity error;
+                  return;
+                end if;
+                read ( f, transform(i, j) );
+              end loop;
+            end loop;
+          end procedure read_transform;
+
+          -- end code from book
+
+  begin
+
+    -- code from book (in text)
+
+    read_transform ( initial_transforms, transform1 );
+    read_transform ( initial_transforms, transform2 );
+
+    -- end code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_08.vhd
new file mode 100644
index 0000000..104748a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_08.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package textio is
+
+  type line is access string;
+
+  type text is file of string;
+
+  type side is (right, left);
+
+  subtype width is natural;
+
+  file input : text open read_mode is "std_input";
+  file output : text open write_mode is "std_output";
+
+  procedure readline(file f: text; l: out line);
+
+  procedure read ( L : inout line;  value: out bit;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit );
+
+  procedure read ( L : inout line;  value: out bit_vector;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit_vector );
+
+  procedure read ( L : inout line;  value: out boolean;  good : out boolean );
+  procedure read ( L : inout line;  value: out boolean );
+
+  procedure read ( L : inout line;  value: out character;  good : out boolean );
+  procedure read ( L : inout line;  value: out character );
+
+  procedure read ( L : inout line;  value: out integer;  good : out boolean );
+  procedure read ( L : inout line;  value: out integer );
+
+  procedure read ( L : inout line;  value: out real;  good : out boolean );
+  procedure read ( L : inout line;  value: out real );
+
+  procedure read ( L : inout line;  value: out string;  good : out boolean );
+  procedure read ( L : inout line;  value: out string );
+
+  procedure read ( L : inout line;  value: out time;  good : out boolean );
+  procedure read ( L : inout line;  value: out time );
+
+  procedure writeline ( file f : text;  L : inout line );
+
+  procedure write ( L : inout line;  value : in bit;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in bit_vector;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in boolean;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in character;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in integer;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in real;
+  justified: in side := right;  field: in width := 0;
+  digits: in natural := 0 );
+
+  procedure write ( L : inout line;  value : in string;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in time;
+  justified: in side := right;  field: in width := 0;
+  unit: in time := ns );
+
+end package textio;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_09.vhd
new file mode 100644
index 0000000..c121b69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_09.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_09.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use bv_utilities.bv_arithmetic.all, std.textio.all;
+
+architecture file_loaded of memory is
+begin
+
+  mem_behavior : process is
+
+                           constant high_address : natural := mem_size - 1;
+
+                         type memory_array is
+                           array (natural range 0 to high_address / 4) of dlx_bv_word;
+
+                         variable mem : memory_array;
+
+                         -- . . .    -- other variables as in architecture preloaded
+
+                         procedure load is
+
+                           file binary_file : text open read_mode is load_file_name;
+                           variable L : line;
+                           variable ch : character;
+                           variable line_number : natural := 0;
+                           variable addr : natural;
+                           variable word : dlx_bv_word;
+
+                           procedure read_hex_natural(L : inout line; n : out natural) is
+                             variable result : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 result := result*16 + character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 result := result*16 + character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 result := result*16 + character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number) severity error;
+                               end if;
+                             end loop;
+                             n := result;
+                           end read_hex_natural;
+
+                           procedure read_hex_word(L : inout line; word : out dlx_bv_word) is
+                             variable digit : natural;
+                             variable r : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 digit := character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 digit := character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 digit := character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number)
+                                   severity error;
+                               end if;
+                               word(r to r+3) := natural_to_bv(digit, 4);
+                               r := r + 4;
+                             end loop;
+                           end read_hex_word;
+
+                         begin
+                           while not endfile(binary_file) loop
+                             readline(binary_file, L);
+                             line_number := line_number + 1;
+                             read_hex_natural(L, addr);
+                             read(L, ch);  -- the space between addr and data
+                             read_hex_word(L, word);
+                             mem(addr / 4) := word;
+                           end loop;
+                         end load;
+
+                         procedure do_write is -- . . . -- as in architecture preloaded
+
+                           procedure do_read is -- . . .  -- as in architecture preloaded
+
+                           begin
+                             load;  -- read binary memory image into memory array
+                             -- . . .       -- as in architecture preloaded
+                           end process mem_behavior;
+
+                         end architecture file_loaded;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd
new file mode 100644
index 0000000..587b5ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd
@@ -0,0 +1,150 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_10 is
+end entity fg_18_10;
+
+
+architecture test of fg_18_10 is
+
+  signal temperature, setting : integer;
+  signal enable, heater_fail : bit;
+
+begin
+
+-- code from book
+
+  stimulus_interpreter : process is
+
+                                   use std.textio.all;
+
+                                 file control : text open read_mode is "control";
+
+                                 variable command : line;
+                                 variable read_ok : boolean;
+                                 variable next_time : time;
+                                 variable whitespace : character;
+                                 variable signal_id : string(1 to 4);
+                                 variable temp_value, set_value : integer;
+                                 variable on_value, fail_value : bit;
+
+  begin
+
+    command_loop : while not endfile(control) loop
+
+      readline ( control, command );
+
+      -- read next stimulus time, and suspend until then
+      read ( command, next_time, read_ok );
+      if not read_ok then
+        report "error reading time from line: " & command.all
+          severity warning;
+        next command_loop;
+      end if;
+      wait for next_time - now;
+
+      -- skip whitespace
+      while command'length > 0
+        and ( command(command'left) = ' '    -- ordinary space
+              or command(command'left) = ' '  -- non-breaking space
+              or command(command'left) = HT ) loop
+        read ( command, whitespace );
+      end loop;
+
+      -- read signal identifier string
+      read ( command, signal_id, read_ok );
+      if not read_ok then
+        report "error reading signal id from line: " & command.all
+          severity warning;
+        next command_loop;
+      end if;
+      -- dispatch based on signal id
+      case signal_id is
+
+        when "temp" =>
+          read ( command, temp_value, read_ok );
+          if not read_ok then
+            report "error reading temperature value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          temperature <= temp_value;
+
+        when "set " =>
+          -- . . .    -- similar to "temp"
+
+          -- not in book
+          read ( command, set_value, read_ok );
+          if not read_ok then
+            report "error reading setting value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          setting <= set_value;
+          -- end not in book
+
+        when "on  " =>
+          read ( command, on_value, read_ok );
+          if not read_ok then
+            report "error reading on value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          enable <= on_value;
+
+        when "fail" =>
+          -- . . .    -- similar to "on  "
+
+          -- not in book
+          read ( command, fail_value, read_ok );
+          if not read_ok then
+            report "error reading fail value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          heater_fail <= fail_value;
+          -- end not in book
+
+        when others =>
+          report "invalid signal id in line: " & signal_id
+            severity warning;
+          next command_loop;
+
+      end case;
+
+    end loop command_loop;
+
+    wait;
+
+  end process stimulus_interpreter;
+
+-- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_11.vhd
new file mode 100644
index 0000000..8474b66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_11.vhd
@@ -0,0 +1,133 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_11 is
+end entity fg_18_11;
+
+
+
+architecture test of fg_18_11 is
+
+  subtype byte is bit_vector(7 downto 0);
+  type byte_array is array (natural range <>) of byte;
+
+  function resolve_bytes ( drivers : in byte_array ) return byte is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bytes;
+
+  function resolve_bits ( drivers : in bit_vector ) return bit is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bits;
+
+  -- code from book (in text)
+
+  signal address : bit_vector(15 downto 0);
+  signal data : resolve_bytes byte;
+  signal rd, wr, io : bit;    -- read, write, io/mem select
+  signal ready : resolve_bits bit;
+
+  -- end code from book
+
+begin
+
+-- code from book
+
+  bus_monitor : process is
+
+                          constant header : string(1 to 44)
+                        := FF & "      Time   R/W I/M  Address          Data";
+
+                        use std.textio.all;
+
+                        file log : text open write_mode is "buslog";
+                        variable trace_line : line;
+                        variable line_count : natural := 0;
+
+  begin
+
+    if line_count mod 60 = 0 then
+      write ( trace_line, header );
+      writeline ( log, trace_line );
+      writeline ( log, trace_line );    -- empty line
+    end if;
+    wait until (rd = '1' or wr = '1') and ready = '1';
+    write ( trace_line, now, justified => right, field => 10, unit => us );
+    write ( trace_line, string'("    ") );
+    if rd = '1' then
+      write ( trace_line, 'R' );
+    else
+      write ( trace_line, 'W' );
+    end if;
+    write ( trace_line, string'("   ") );
+    if io = '1' then
+      write ( trace_line, 'I' );
+    else
+      write ( trace_line, 'M' );
+    end if;
+    write ( trace_line, string'("   ") );
+    write ( trace_line, address );
+    write ( trace_line, ' ');
+    write ( trace_line, data );
+    writeline ( log, trace_line );
+    line_count := line_count + 1;
+
+  end process bus_monitor;
+
+-- end code from book
+
+  stimulus : process is
+  begin
+    wait for 0.4 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0000";
+    data <= B"10011110";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 0.9 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0001";
+    data <= B"00010010";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.0 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0014";
+    data <= B"11100111";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.7 us - now;
+    wr <= '1', '0' after 10 ns;
+    io <= '1', '0' after 10 ns;
+    address <= X"0007";
+    data <= X"00";
+    ready <= '1', '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds-qn.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds-qn.vhd
new file mode 100644
index 0000000..0ed8b0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds-qn.vhd
@@ -0,0 +1,162 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_ds-qn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+use qsim.qsim_types.all, random.random.all;
+
+architecture queue_net of disk_system is
+
+  constant disk_cache_miss_rate : real := 0.2;
+  constant num_disks : positive := 2;
+
+  constant disk_cache_fork_probabilities : probability_vector(1 to num_disks)
+    := ( others => disk_cache_miss_rate / real(num_disks) );
+
+  signal info_detail_control : info_detail_type := none;
+  signal new_job, cpu_queue_in, cpu_in, cpu_out,
+    quantum_expired, job_done, requesting_disk,
+    disk_cache_hit, request_done : arc_type;
+  signal disk_cache_miss, disk_done : arc_vector(1 to num_disks);
+  signal cpu_ready : boolean;
+
+begin
+
+  new_jobs : entity source
+    generic map ( name => "new_jobs",
+		  distribution => exponential,
+		  mean_inter_arrival_time => 2 sec,
+		  seed => sample_seeds(1),
+		  time_unit => ms,
+		  info_file_name => "new_jobs.dat" )
+    port map ( out_arc => new_job,
+	       info_detail => info_detail_control );
+
+  cpu_join : entity join
+    generic map ( name => "cpu_join",
+		  time_unit => ms,
+		  info_file_name => "cpu_join.dat" )
+    port map ( in_arc(1) => quantum_expired,
+	       in_arc(2) => new_job,
+	       in_arc(3) => request_done,
+	       out_arc => cpu_queue_in,
+	       info_detail => info_detail_control );
+
+  cpu_queue : entity queue
+    generic map ( name => "cpu_queue",
+		  time_unit => ms,
+		  info_file_name => "cpu_queue.dat" )
+    port map ( in_arc => cpu_queue_in,
+	       out_arc => cpu_in,
+	       out_ready => cpu_ready,
+	       info_detail => info_detail_control );
+
+  cpu : entity server
+    generic map ( name => "cpu",
+		  distribution => uniform,
+		  mean_service_time => 50 ms,
+		  seed => sample_seeds(2),
+		  time_unit => ms,
+		  info_file_name => "cpu.dat" )
+    port map ( in_arc => cpu_in,
+	       in_ready => cpu_ready,
+	       out_arc => cpu_out,
+	       info_detail => info_detail_control );
+
+  cpu_fork : entity fork
+    generic map ( name => "cpu_fork",
+		  probabilities => ( 1 => 0.5, 2 => 0.45 ),
+		  seed => sample_seeds(3),
+		  time_unit => ms,
+		  info_file_name => "cpu_fork.dat" )
+    port map ( in_arc => cpu_out,
+	       out_arc(1) => quantum_expired,
+	       out_arc(2) => requesting_disk,
+	       out_arc(3) => job_done,
+	       info_detail => info_detail_control );
+
+  job_sink : entity sink
+    generic map ( name => "job_sink",
+		  time_unit => ms,
+		  info_file_name => "job_sink.dat" )
+    port map ( in_arc => job_done,
+	       info_detail => info_detail_control );
+
+  disk_cache_fork : entity fork
+    generic map ( name => "disk_cache_fork",
+		  probabilities => disk_cache_fork_probabilities,
+		  seed => sample_seeds(4),
+		  time_unit => ms,
+		  info_file_name => "disk_cache_fork.dat" )
+    port map ( in_arc => requesting_disk,
+	       out_arc(1 to num_disks) => disk_cache_miss,
+	       out_arc(num_disks + 1) => disk_cache_hit,
+	       info_detail => info_detail_control );
+
+
+  disk_array : for disk_index in 1 to num_disks generate
+
+    constant disk_index_str : string := integer'image(disk_index);
+
+    signal disk_in : arc_type;
+    signal disk_ready : boolean;
+
+  begin
+
+    disk_queue : entity queue
+      generic map ( name => "disk_queue_" & disk_index_str,
+		    time_unit => ms,
+		    info_file_name => "disk_queue_" & disk_index_str & ".dat" )
+      port map ( in_arc => disk_cache_miss(disk_index),
+	         out_arc => disk_in,
+	         out_ready => disk_ready,
+	         info_detail => info_detail_control );
+
+    disk : entity server
+      generic map ( name => "disk_" & disk_index_str,
+		    distribution => exponential,
+		    mean_service_time => 15 ms,
+		    seed => sample_seeds(4 + disk_index),
+		    time_unit => ms,
+		    info_file_name => "disk_" & disk_index_str & ".dat" )
+      port map ( in_arc => disk_in,
+	         in_ready => disk_ready,
+	         out_arc => disk_done(disk_index),
+	         info_detail => info_detail_control );
+
+  end generate disk_array;
+
+
+  disk_cache_join : entity join
+    generic map ( name => "disk_cache_join",
+		  time_unit => ms,
+		  info_file_name => "disk_cache_join.dat" )
+    port map ( in_arc(1 to num_disks) => disk_done,
+	       in_arc(num_disks + 1) => disk_cache_hit,
+	       out_arc => request_done,
+	       info_detail => info_detail_control );
+
+end architecture queue_net;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds.vhd
new file mode 100644
index 0000000..862cabd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_ds.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity disk_system is
+
+end entity disk_system;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork-b.vhd
new file mode 100644
index 0000000..b273c42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork-b.vhd
@@ -0,0 +1,131 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_fork-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of fork is
+
+begin
+
+  forker : process
+
+    variable cumulative_probabilities : probability_vector(1 to probabilities'length);
+    variable destination : positive range out_arc'range;
+    variable probabilities_index : positive range probabilities'range;
+    variable number_of_tokens_forked : natural := 0;
+    type counter_array is array (positive range out_arc'range) of natural;
+    variable number_forked_to_destination : counter_array := (others => 0);
+
+    variable random_info : random_info_record;
+    variable random_number : real;
+
+    type transaction_vector is array (positive range <>) of boolean;
+    variable out_arc_transaction_driving_value : transaction_vector(out_arc'range)
+      := (others => false);
+
+    use std.textio.all;
+    file info_file : text;
+    variable L : line;
+
+    procedure write_summary is
+    begin
+      write(L, string'("Summary information for fork "));
+      write(L, name);
+      write(L, string'(" up to time "));
+      write(L, now, unit => time_unit);
+      writeline(info_file, L);
+      write(L, string'("  Number of tokens forked = "));
+      write(L, natural(number_of_tokens_forked));
+      writeline(info_file, L);
+      for destination in out_arc'range loop
+        write(L, string'("    Number to output("));
+        write(L, destination);
+        write(L, string'(") = "));
+        write(L, number_forked_to_destination(destination));
+        write(L, string'(" ("));
+        write(L, real(number_forked_to_destination(destination))
+              / real(number_of_tokens_forked),
+              digits => 4);
+        write(L, ')');
+        writeline(info_file, L);
+      end loop;
+      writeline(info_file, L);
+    end write_summary;
+
+    procedure write_trace is
+    begin
+      write(L, string'("Fork "));
+      write(L, name);
+      write(L, string'(": at "));
+      write(L, now, unit => time_unit);
+      write(L, string'(" forked to output "));
+      write(L, destination);
+      write(L, ' ');
+      write(L, in_arc.token, time_unit);
+      writeline(info_file, L);
+    end write_trace;
+
+  begin
+    assert probabilities'length = out_arc'length - 1
+      report "incorrent number of probabilities - should be "
+      & integer'image(out_arc'length - 1) severity failure;
+    cumulative_probabilities := probabilities;
+    for index in 2 to cumulative_probabilities'length loop
+      cumulative_probabilities(index) := cumulative_probabilities(index - 1)
+					 + cumulative_probabilities(index);
+    end loop;
+    init_uniform( random_info,
+                  lower_bound => 0.0, upper_bound => 1.0, seed => seed );
+    file_open(info_file, info_file_name, write_mode);
+
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+        generate_random(random_info, random_number);
+        destination := out_arc'left;
+        for index in 1 to cumulative_probabilities'length loop
+          exit when random_number < cumulative_probabilities(index);
+	  if out_arc'ascending then
+	    destination := destination + 1;
+	  else
+	    destination := destination - 1;
+	  end if;
+        end loop;
+        out_arc(destination) <= arc_type'( transaction => not out_arc_transaction_driving_value(destination),
+					   token => in_arc.token );
+	out_arc_transaction_driving_value(destination) := not out_arc_transaction_driving_value(destination);
+        number_of_tokens_forked := number_of_tokens_forked + 1;
+        number_forked_to_destination(destination)
+          := number_forked_to_destination(destination) + 1;
+        if info_detail = trace then
+          write_trace;
+        end if;
+      end if;
+    end loop;
+  end process forker;
+
+end behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork.vhd
new file mode 100644
index 0000000..c26a730
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_fork.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use qsim.qsim_types.all, random.random.all;
+
+entity fork is
+
+  generic ( name : string;
+            probabilities : probability_vector;
+            -- must be one element shorter than out_arc port
+            seed : seed_type;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+         out_arc : out arc_vector;
+         info_detail : in info_detail_type );       
+
+end fork;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join-b.vhd
new file mode 100644
index 0000000..cef314e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join-b.vhd
@@ -0,0 +1,139 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_join-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+architecture behavior of join is
+
+begin
+
+  joiner : process
+
+    use qsim.token_fifo_adt.all;
+
+    variable source : positive range in_arc'range;
+    variable token_fifo : fifo_type := new_fifo;
+    variable current_fifo_size : natural := 0;
+    variable head_token : token_type;
+    variable number_of_tokens_joined : natural := 0;
+    type counter_array is array (positive range in_arc'range) of natural;
+    variable number_joined_from_source : counter_array := (others => 0);
+
+    use std.textio.all;
+    file info_file : text;
+    variable L : line;
+
+--  Modeltech bug mt043 workaround
+    variable in_arc_last_value : arc_vector(in_arc'range) := in_arc;
+--
+
+    procedure write_summary is
+    begin
+      write(L, string'("Summary information for join "));
+      write(L, name);
+      write(L, string'(" up to time "));
+      write(L, now, unit => time_unit);
+      writeline(info_file, L);
+      write(L, string'("  Number of tokens joined = "));
+      write(L, natural(number_of_tokens_joined));
+      writeline(info_file, L);
+      for source in in_arc'range loop
+        write(L, string'("    Number from input("));
+        write(L, source);
+        write(L, string'(") = "));
+        write(L, natural(number_joined_from_source(source)));
+        write(L, string'(" ("));
+        write(L, real(number_joined_from_source(source))
+              / real(number_of_tokens_joined),
+              digits => 4);
+        write(L, ')');
+        writeline(info_file, L);
+      end loop;
+      writeline(info_file, L);
+    end write_summary;
+
+    procedure write_trace is
+    begin
+      write(L, string'("Join "));
+      write(L, name);
+      write(L, string'(": at "));
+      write(L, now, unit => time_unit);
+      write(L, string'(" joined from input "));
+      write(L, source);
+      write(L, ' ');
+      write(L, in_arc(source).token, time_unit);
+      writeline(info_file, L);
+    end write_trace;
+
+    procedure accept_new_tokens is
+    begin
+      for index in 1 to in_arc'length loop
+--  Modeltech bug mt043 workaround
+--      if in_arc(index).transaction /= in_arc'last_value(index).transaction then
+        if in_arc(index).transaction /= in_arc_last_value(index).transaction then
+--
+          source := index;
+          insert(token_fifo, in_arc(source).token);
+          current_fifo_size := current_fifo_size + 1;
+          number_of_tokens_joined := number_of_tokens_joined + 1;
+          number_joined_from_source(source) := number_joined_from_source(source) + 1;
+          if info_detail = trace then
+            write_trace;
+          end if;
+        end if;
+      end loop;
+--  Modeltech bug mt043 workaround
+      in_arc_last_value := in_arc;
+--
+    end procedure accept_new_tokens;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+	accept_new_tokens;
+        while current_fifo_size > 0 loop
+          remove(token_fifo, head_token);
+          current_fifo_size := current_fifo_size - 1;
+	  out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+			        token => head_token );
+          wait for 0 fs;  -- delta delay before next output token
+          if info_detail'active and info_detail = summary then
+            write_summary;
+          end if;
+          if in_arc'event then
+	    accept_new_tokens;
+	  end if;
+        end loop;
+      end if;
+    end loop;
+  end process joiner;
+
+end behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd
new file mode 100644
index 0000000..1b27724
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_join.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+use qsim.qsim_types.all;
+
+entity join is
+
+  generic ( name : string;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_vector;
+	 out_arc : out arc_type;
+	 info_detail : in info_detail_type );       
+
+end join;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt-b.vhd
new file mode 100644
index 0000000..199a899
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt-b.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_qsimt-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package body qsim_types is
+
+  use std.textio.all;
+
+  procedure write ( L : inout line;  t : in token_type;
+  creation_time_unit : in time := ns ) is
+  begin
+    write(L, string'("token "));
+    write(L, natural(t.id));
+    write(L, string'(" from "));
+    write(L, t.source_name(1 to t.source_name_length));
+    write(L, string'(" created at "));
+    write(L, t.creation_time, unit => creation_time_unit);
+  end write;
+
+end package body qsim_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt.vhd
new file mode 100644
index 0000000..c840b98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_qsimt.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--use std.textio.line;
+use std.textio.all;
+
+package qsim_types is
+
+  constant name_max_length : natural := 20;
+  type token_id_type is range 0 to integer'high;
+
+  type token_type is record
+                       source_name : string(1 to name_max_length);
+                       source_name_length : natural;
+                       id : token_id_type;
+                       creation_time : time;
+                     end record;
+
+  type token_vector is array (positive range <>) of token_type;
+
+  type arc_type is record
+                     transaction : boolean;  -- flips when an arc changes
+                     token : token_type;
+                   end record arc_type;
+
+  type arc_vector is array (positive range <>) of arc_type;
+
+  type info_detail_type is (none, summary, trace);
+
+  procedure write ( L : inout line;  t : in token_type;
+  creation_time_unit : in time := ns );
+
+end package qsim_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qt.vhd
new file mode 100644
index 0000000..090ac12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qt.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_qt.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+use qsim.qsim_types.all;
+
+package queue_types is
+
+  type waiting_token_type is record
+                               token : token_type;
+                               time_when_enqueued : time;
+                             end record waiting_token_type;
+
+end package queue_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue-b.vhd
new file mode 100644
index 0000000..4d5e363
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue-b.vhd
@@ -0,0 +1,146 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_queue-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of queue is
+
+begin
+
+  queue_manager : process is
+
+                            use qsim.queue_types.all, qsim.waiting_token_fifo_adt.all;
+
+                          variable waiting_token, head_token : waiting_token_type;
+                          variable waiting_token_fifo : fifo_type := new_fifo;
+                          variable out_token_in_transit : boolean := false;
+                          variable number_of_tokens_released : natural := 0;
+                          variable current_queue_size : natural := 0;
+                          variable maximum_queue_size : natural := 0;
+                          variable waiting_time : natural;  -- in time_unit
+                          variable sum_of_waiting_times : real := 0.0;  -- in time_unit
+                          variable sum_of_squares_of_waiting_times : real := 0.0;  --in time_unit**2
+
+                          use std.textio.all;
+                          file info_file : text;
+                          variable L : line;
+
+                          use math.math_real.sqrt;
+
+                          procedure write_summary is
+                            variable mean_waiting_time : real
+                              := sum_of_waiting_times / real(number_of_tokens_released);
+                            variable std_dev_of_waiting_times : real
+                              := sqrt ( ( sum_of_squares_of_waiting_times
+                                          - sum_of_waiting_times**2 / real(number_of_tokens_released) )
+                                        / real( number_of_tokens_released - 1 ) );
+                          begin
+                            write(L, string'("Summary information for queue "));
+                            write(L, name);
+                            write(L, string'(" up to time "));
+                            write(L, now, unit => time_unit);
+                            writeline(info_file, L);
+                            write(L, string'("  Number of tokens currently waiting = "));
+                            write(L, natural(current_queue_size));
+                            writeline(info_file, L);
+                            write(L, string'("  Number of tokens released = "));
+                            write(L, natural(number_of_tokens_released));
+                            writeline(info_file, L);
+                            write(L, string'("  Maximum queue size = "));
+                            write(L, natural(maximum_queue_size));
+                            writeline(info_file, L);
+                            write(L, string'("  Mean waiting time = "));
+                            write(L, mean_waiting_time * time_unit, unit => time_unit);
+                            writeline(info_file, L);
+                            write(L, string'("  Standard deviation of waiting times = "));
+                            write(L, std_dev_of_waiting_times * time_unit, unit => time_unit);
+                            writeline(info_file, L);
+                            writeline(info_file, L);
+                          end procedure write_summary;
+
+                          procedure write_trace_enqueue is
+                          begin
+                            write(L, string'("Queue "));
+                            write(L, name);
+                            write(L, string'(": at "));
+                            write(L, now, unit => time_unit);
+                            write(L, string'(" enqueued "));
+                            write(L, waiting_token.token, time_unit);
+                            writeline(info_file, L);
+                          end procedure write_trace_enqueue;
+
+                          procedure write_trace_dequeue is
+                          begin
+                            write(L, string'("Queue "));
+                            write(L, name);
+                            write(L, string'(": at "));
+                            write(L, now, unit => time_unit);
+                            write(L, string'(" dequeued "));
+                            write(L, head_token.token, time_unit);
+                            writeline(info_file, L);
+                          end procedure write_trace_dequeue;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+    loop
+      wait on info_detail'transaction, in_arc, out_ready;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+        waiting_token := waiting_token_type'( token => in_arc.token,
+                                              time_when_enqueued => now );
+        insert(waiting_token_fifo, waiting_token);
+        current_queue_size := current_queue_size + 1;
+        if current_queue_size > maximum_queue_size then
+          maximum_queue_size := current_queue_size;
+        end if;
+        if info_detail = trace then
+          write_trace_enqueue;
+        end if;
+      end if;
+      if out_ready and current_queue_size > 0 and not out_token_in_transit then
+	remove(waiting_token_fifo, head_token);
+	current_queue_size := current_queue_size - 1;
+	out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+			      token => head_token.token );
+	out_token_in_transit := true;
+	number_of_tokens_released := number_of_tokens_released + 1;
+	waiting_time := (now - head_token.time_when_enqueued) / time_unit;
+	sum_of_waiting_times := sum_of_waiting_times + real(waiting_time);
+        sum_of_squares_of_waiting_times := sum_of_squares_of_waiting_times
+                                           + real(waiting_time) ** 2;
+        if info_detail = trace then
+          write_trace_dequeue;
+        end if;
+      end if;
+      if out_token_in_transit and not out_ready then
+	out_token_in_transit := false;
+      end if;
+    end loop;
+  end process queue_manager;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue.vhd
new file mode 100644
index 0000000..abb1891
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_queue.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+use qsim.qsim_types.all;
+
+entity queue is
+
+  generic ( name : string;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+	 out_arc : out arc_type;
+	 out_ready : in boolean;
+         info_detail : in info_detail_type );
+
+end entity queue;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd
new file mode 100644
index 0000000..0c15b6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd
@@ -0,0 +1,155 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_random-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+package body random is
+
+  use math.math_real;
+
+  constant sample_seeds : seed_array(0 to 50)
+    := (  0 => (1, 1),
+          1 => (1919456777, 2006618587),
+          2 => (928906921, 476680813),
+          3 => (715788085, 762347824),
+          4 => (366002668, 1804336679),
+          5 => (1866585254, 247488051),
+          6 => (1342990589, 1539624735),
+          7 => (677313287, 1675609237),
+          8 => (644816519, 2026475269),
+          9 => (1654953611, 564421524),
+          10 => (1020104619, 712556314),
+          11 => (609798541, 1592526288),
+          12 => (1106087470, 1468242308),
+          13 => (1378844312, 646793513),
+          14 => (966261604, 481733031),
+          15 => (1407842093, 1316990206),
+          16 => (1705378215, 1930221363),
+          17 => (206887499, 1810320799),
+          18 => (1681633030, 2114795480),
+          19 => (71194926, 1642522201),
+          20 => (663275331, 1947299255),
+          21 => (224432387, 944962866),
+          22 => (1156075861, 1866435087),
+          23 => (1670357576, 1247152991),
+          24 => (846934138, 1673364736),
+          25 => (1972636955, 1404522710),
+          26 => (533484185, 592078395),
+          27 => (1989468008, 1409246301),
+          28 => (697086615, 1975145057),
+          29 => (111393259, 1673620688),
+          30 => (1352201163, 872947497),
+          31 => (1342844190, 877696585),
+          32 => (938770066, 1222894811),
+          33 => (1144599578, 661919919),
+          34 => (1750521407, 269946538),
+          35 => (457892500, 1256953520),
+          36 => (1678589945, 356027520),
+          37 => (1484458924, 2103068828),
+          38 => (1296978761, 2124096638),
+          39 => (1702642440, 1161000593),
+          40 => (1244690090, 2016422304),
+          41 => (1858682943, 1053836731),
+          42 => (1496964676, 701079294),
+          43 => (432696952, 602526767),
+          44 => (2097684438, 1264032473),
+          45 => (2115456834, 298917738),
+          46 => (432301768, 232430346),
+          47 => (1929812456, 758157910),
+          48 => (1655564027, 1062345086),
+          49 => (1116121051, 538424126),
+          50 => (844396720, 821616997) );
+
+
+  procedure init_fixed ( random_info : out random_info_record;
+                         mean : in real ) is
+  begin
+    random_info.distribution := fixed;
+    random_info.mean := mean;
+  end procedure init_fixed;
+
+
+  procedure init_uniform ( random_info : out random_info_record;
+                           lower_bound, upper_bound : in real;
+                           seed : in seed_type ) is
+  begin
+    assert lower_bound <= upper_bound
+                          report "init_uniform: lower_bound > upper_bound" severity failure;
+    random_info.distribution := uniform;
+    random_info.lower_bound := lower_bound;
+    random_info.upper_bound := upper_bound;
+    random_info.seed := seed;
+  end procedure init_uniform;
+
+
+  procedure init_exponential ( random_info : out random_info_record;
+                               mean : in real;
+                               seed : in seed_type ) is
+  begin
+    assert mean > 0.0
+      report "init_exponential: mean not positive" severity failure;
+    random_info.distribution := exponential;
+    random_info.mean := mean;
+    random_info.seed := seed;
+  end procedure init_exponential;
+
+
+  procedure generate_uniform ( random_info : inout random_info_record;
+                               random_number : out real ) is
+    variable tmp : real;
+  begin
+    math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
+    random_number := random_info.lower_bound
+                     + tmp * (random_info.upper_bound - random_info.lower_bound);
+  end procedure generate_uniform;
+
+
+  procedure generate_exponential ( random_info : inout random_info_record;
+                                   random_number : out real ) is
+    variable tmp : real;
+  begin
+    loop
+      math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
+      exit when tmp /= 0.0;
+    end loop;
+    random_number := - random_info.mean * math_real.log(tmp);
+  end procedure generate_exponential;
+
+
+  procedure generate_random ( random_info : inout random_info_record;
+                              random_number : out real ) is
+  begin
+    case random_info.distribution is
+      when fixed =>
+        random_number := random_info.mean;
+      when uniform =>
+        generate_uniform(random_info, random_number);
+      when exponential =>
+        generate_exponential(random_info, random_number);
+    end case;
+  end procedure generate_random;
+
+end package body random;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd
new file mode 100644
index 0000000..445b38d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_random.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package random is
+
+  type distribution_type is (fixed, uniform, exponential);
+
+  subtype probability is real range 0.0 to 1.0;
+
+  type probability_vector is array (positive range <>) of probability;
+
+  type seed_type is record
+                      seed1, seed2 : positive;
+                    end record seed_type;
+  type seed_array is array ( natural range <> ) of seed_type;
+  constant sample_seeds : seed_array(0 to 50);
+
+  type random_info_record is record
+                               seed : seed_type;
+                               distribution : distribution_type;
+                               mean : real;
+                               lower_bound, upper_bound : real;
+                             end record random_info_record;
+
+
+  procedure init_fixed ( random_info : out random_info_record;
+                         mean : in real );
+
+  procedure init_uniform ( random_info : out random_info_record;
+                           lower_bound, upper_bound : in real;
+                           seed : in seed_type );
+
+  procedure init_exponential ( random_info : out random_info_record;
+                               mean : in real;
+                               seed : in seed_type );
+
+  procedure generate_random ( random_info : inout random_info_record;
+                              random_number : out real );
+
+end package random;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd
new file mode 100644
index 0000000..8efbea0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of sink is
+
+begin
+
+  token_consumer : process is
+
+                             variable number_of_tokens_consumed : natural := 0;
+                           variable life_time : real;  -- in time_unit
+                           variable sum_of_life_times : real := 0.0;  -- in time_unit
+                           variable sum_of_squares_of_life_times : real := 0.0;  --in time_unit**2
+
+                           use std.textio.all;
+                           file info_file : text;
+                           variable L : line;
+
+                           use math.math_real.sqrt;
+
+                           procedure write_summary is
+                             variable mean_life_time : real
+                               := sum_of_life_times / real(number_of_tokens_consumed);
+                             variable std_dev_of_life_times : real
+                               := sqrt ( ( sum_of_squares_of_life_times
+                                           - sum_of_life_times**2 / real(number_of_tokens_consumed) )
+                                         / real( number_of_tokens_consumed - 1 ) );
+                           begin
+                             write(L, string'("Summary information for sink "));
+                             write(L, name);
+                             write(L, string'(" up to time "));
+                             write(L, now, unit => time_unit);
+                             writeline(info_file, L);
+                             write(L, string'("  Number of tokens consumed = "));
+                             write(L, natural(number_of_tokens_consumed));
+                             writeline(info_file, L);
+                             write(L, string'("  Mean life_time = "));
+                             write(L, mean_life_time * time_unit, unit => time_unit);
+                             writeline(info_file, L);
+                             write(L, string'("  Standard deviation of life_times = "));
+                             write(L, std_dev_of_life_times * time_unit, unit => time_unit);
+                             writeline(info_file, L);
+                             writeline(info_file, L);
+                           end procedure write_summary;
+
+                           procedure write_trace is
+                           begin
+                             write(L, string'("Sink "));
+                             write(L, name);
+                             write(L, string'(": at "));
+                             write(L, now, unit => time_unit);
+                             write(L, string'(" consumed "));
+                             write(L, in_arc.token, time_unit);
+                             writeline(info_file, L);
+                           end procedure write_trace;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+        number_of_tokens_consumed := number_of_tokens_consumed + 1;
+        life_time := real( (now - in_arc.token.creation_time) / time_unit );
+        sum_of_life_times := sum_of_life_times + life_time;
+        sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
+        if info_detail = trace then
+          write_trace;
+        end if;
+      end if;
+    end loop;
+  end process token_consumer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink.vhd
new file mode 100644
index 0000000..a38d21a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_sink.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+use qsim.qsim_types.all;
+
+entity sink is
+
+  generic ( name : string;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+	 info_detail : in info_detail_type );
+
+end sink;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source-b.vhd
new file mode 100644
index 0000000..0ae94a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source-b.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_source-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of source is
+
+begin
+
+  token_generator : process is
+
+                              variable source_name : string(1 to name_max_length) := (others => ' ');
+                            variable source_name_length : natural;
+                            variable next_token_id : token_id_type := 0;
+                            variable next_arrival_time : time;
+                            variable number_of_tokens_generated : natural := 0;
+                            variable inter_arrival_time : natural;  -- in time_unit
+                            variable sum_of_inter_arrival_times : real := 0.0;  -- in time_unit
+                            variable sum_of_squares_of_inter_arrival_times : real := 0.0;  --in time_unit**2
+
+                            variable random_info : random_info_record;
+                            variable random_number : real;
+
+                            use std.textio.all;
+                            file info_file : text;
+                            variable L : line;
+
+                            use math.math_real.sqrt;
+
+                            procedure write_summary is
+                              variable measured_mean_inter_arrival_time : real
+                                := sum_of_inter_arrival_times / real(number_of_tokens_generated);
+                              variable measured_std_dev_of_inter_arrival_times : real
+                                := sqrt ( ( sum_of_squares_of_inter_arrival_times
+                                            - sum_of_inter_arrival_times**2 / real(number_of_tokens_generated) )
+                                          / real( number_of_tokens_generated - 1 ) );
+                            begin
+                              write(L, string'("Summary information for source "));
+                              write(L, name);
+                              write(L, string'(" up to time "));
+                              write(L, now, unit => time_unit);
+                              writeline(info_file, L);
+                              write(L, string'("  Inter arrival distribution: "));
+                              write(L, distribution_type'image(distribution));
+                              write(L, string'(" with mean inter arrival time of "));
+                              write(L, mean_inter_arrival_time, unit => time_unit);
+                              writeline(info_file, L);
+                              write(L, string'("  Number of tokens generated = "));
+                              write(L, natural(next_token_id));
+                              writeline(info_file, L);
+                              write(L, string'("  Mean inter arrival time = "));
+                              write(L, measured_mean_inter_arrival_time * time_unit, unit => time_unit);
+                              writeline(info_file, L);
+                              write(L, string'("  Standard deviation of inter arrival times = "));
+                              write(L, measured_std_dev_of_inter_arrival_times * time_unit, unit => time_unit);
+                              writeline(info_file, L);
+                              writeline(info_file, L);
+                            end procedure write_summary;
+
+                            procedure write_trace is
+                            begin
+                              write(L, string'("Source "));
+                              write(L, name);
+                              write(L, string'(": at "));
+                              write(L, now, unit => time_unit);
+                              write(L, string'(" generated token "));
+                              write(L, natural(next_token_id));
+                              writeline(info_file, L);
+                            end procedure write_trace;
+
+  begin
+    if name'length > name_max_length then
+      source_name := name(1 to name_max_length);
+      source_name_length := name_max_length;
+    else
+      source_name(1 to name'length) := name;
+      source_name_length := name'length;
+    end if;
+    file_open(info_file, info_file_name, write_mode);
+
+    case distribution is
+      when fixed =>
+        init_fixed(random_info, real(mean_inter_arrival_time / time_unit));
+      when uniform =>
+        init_uniform( random_info,
+                      lower_bound => 0.0,
+                      upper_bound => 2.0 * real(mean_inter_arrival_time / time_unit),
+                      seed => seed );
+      when exponential =>
+        init_exponential( random_info,
+                          mean => real(mean_inter_arrival_time / time_unit),
+                          seed => seed );
+    end case;
+
+    loop
+      generate_random(random_info, random_number);
+      inter_arrival_time :=  natural(random_number);
+      next_arrival_time := inter_arrival_time * time_unit + now;
+      loop
+        wait on info_detail'transaction for next_arrival_time - now;
+        if info_detail'active and info_detail = summary then
+          write_summary;
+        end if;
+        exit when next_arrival_time = now;
+      end loop;
+      out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+		            token => token_type'( source_name => source_name,
+                                                  source_name_length => source_name_length,
+                                                  id => next_token_id,
+                                                  creation_time => now ) );
+      number_of_tokens_generated := number_of_tokens_generated + 1;
+      sum_of_inter_arrival_times := sum_of_inter_arrival_times
+                                    + real(inter_arrival_time);
+      sum_of_squares_of_inter_arrival_times := sum_of_squares_of_inter_arrival_times
+                                               + real(inter_arrival_time) ** 2;
+
+      if info_detail = trace then
+        write_trace;
+      end if;
+      next_token_id := next_token_id + 1;
+    end loop;
+  end process token_generator;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source.vhd
new file mode 100644
index 0000000..784b2e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_source.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use qsim.qsim_types.all, random.random.all;
+
+entity source is
+
+  generic ( name : string;
+            distribution : distribution_type;
+            mean_inter_arrival_time : delay_length;
+            seed : seed_type;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( out_arc : out arc_type;
+         info_detail : in info_detail_type );
+
+end entity source;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr-b.vhd
new file mode 100644
index 0000000..7cb191d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr-b.vhd
@@ -0,0 +1,159 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_srvr-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of server is
+
+begin
+
+  service : process is
+
+                      variable served_token : token_type;
+                    variable release_time : time;
+                    variable number_of_tokens_served : natural := 0;
+                    variable service_time : natural;  -- in time_unit
+                    variable sum_of_service_times : real := 0.0;  -- in time_unit
+                    variable sum_of_squares_of_service_times : real := 0.0;  --in time_unit**2
+
+                    variable random_info : random_info_record;
+                    variable random_number : real;
+
+                    use std.textio.all;
+                    file info_file : text;
+                    variable L : line;
+
+                    use math.math_real.sqrt;
+
+                    procedure write_summary is
+                      variable measured_mean_service_time : real
+                        := sum_of_service_times / real(number_of_tokens_served);
+                      variable measured_std_dev_of_service_times : real
+                        := sqrt ( ( sum_of_squares_of_service_times
+                                    - sum_of_service_times**2 / real(number_of_tokens_served) )
+                                  / real( number_of_tokens_served - 1 ) );
+                    begin
+                      write(L, string'("Summary information for server "));
+                      write(L, name);
+                      write(L, string'(" up to time "));
+                      write(L, now, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Service distribution: "));
+                      write(L, distribution_type'image(distribution));
+                      write(L, string'(" with mean service time of "));
+                      write(L, mean_service_time, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Number of tokens served = "));
+                      write(L, natural(number_of_tokens_served));
+                      writeline(info_file, L);
+                      write(L, string'("  Mean service time = "));
+                      write(L, measured_mean_service_time * time_unit, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Standard deviation of service times = "));
+                      write(L, measured_std_dev_of_service_times * time_unit, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Utilization = "));
+                      write(L, sum_of_service_times / real(now / time_unit), digits => 4);
+                      writeline(info_file, L);
+                      writeline(info_file, L);
+                    end procedure write_summary;
+
+                    procedure write_trace_service is
+                    begin
+                      write(L, string'("Server "));
+                      write(L, name);
+                      write(L, string'(": at "));
+                      write(L, now, unit => time_unit);
+                      write(L, string'(" served "));
+                      write(L, in_arc.token, time_unit);
+                      writeline(info_file, L);
+                    end procedure write_trace_service;
+
+                    procedure write_trace_release is
+                    begin
+                      write(L, string'("Server "));
+                      write(L, name);
+                      write(L, string'(": at "));
+                      write(L, now, unit => time_unit);
+                      write(L, string'(" released "));
+                      write(L, served_token, time_unit);
+                      writeline(info_file, L);
+                    end procedure write_trace_release;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+
+    case distribution is
+      when fixed =>
+        init_fixed(random_info, real(mean_service_time / time_unit));
+      when uniform =>
+        init_uniform( random_info,
+                      lower_bound => 0.0,
+                      upper_bound => 2.0 * real(mean_service_time / time_unit),
+                      seed => seed );
+      when exponential =>
+        init_exponential( random_info,
+                          mean => real(mean_service_time / time_unit),
+                          seed => seed );
+    end case;
+
+    in_ready <= true;
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+	in_ready <= false;
+        if info_detail = trace then
+          write_trace_service;
+        end if;
+        served_token := in_arc.token;
+        generate_random(random_info, random_number);
+        service_time :=  natural(random_number);
+        release_time := service_time * time_unit + now;
+        loop
+          wait on info_detail'transaction for release_time - now;
+          if info_detail'active and info_detail = summary then
+            write_summary;
+          end if;
+          exit when release_time = now;
+        end loop;
+	in_ready <= true;
+	out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+			      token => served_token );
+        number_of_tokens_served := number_of_tokens_served + 1;
+        sum_of_service_times := sum_of_service_times + real(service_time);
+        sum_of_squares_of_service_times := sum_of_squares_of_service_times
+                                           + real(service_time) ** 2;
+        if info_detail = trace then
+          write_trace_release;
+        end if;
+      end if;
+    end loop;
+  end process service;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr.vhd
new file mode 100644
index 0000000..f68fbcc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_srvr.vhd,v 1.5 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.5 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random
+
+  use qsim.qsim_types.all, random.random.all;
+
+entity server is
+
+  generic ( name : string;
+            distribution : distribution_type;
+            mean_service_time : time;
+            seed : seed_type;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+         in_ready : out boolean;
+         out_arc : out arc_type;
+         info_detail : in info_detail_type );
+
+end entity server;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd
new file mode 100644
index 0000000..a96811c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-frk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture fork of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  constant num_outputs : positive := 4;
+  constant probabilities : probability_vector(1 to num_outputs - 1)
+    := ( 0.2, 0.4, 0.1 );
+
+  signal source_arc : arc_type;
+  signal fork_arc : arc_vector(1 to num_outputs);
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => source_arc,
+	       info_detail => info_detail );
+
+  fork1 : entity qsim.fork(behavior)
+    generic map ( name => "fork1",
+                  probabilities => probabilities,
+                  seed => sample_seeds(2),
+                  time_unit => ns,
+                  info_file_name => "fork1.dat" )
+    port map ( in_arc => source_arc,
+	       out_arc => fork_arc,
+               info_detail => info_detail );
+
+
+  source_monitor : process is
+                             variable L : line;
+  begin
+    wait on source_arc;
+    write(L, string'("source_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, source_arc.token, ns);
+    writeline(output, L);
+  end process source_monitor;
+
+
+  sinks : for index in 1 to num_outputs generate
+
+    constant index_string : string := integer'image(index);
+
+  begin
+
+    sink : entity qsim.sink(behavior)
+      generic map ( name => "sink" & index_string,
+                    time_unit => ns,
+                    info_file_name => "sink" & index_string & ".dat" )
+      port map ( in_arc => fork_arc(index),
+		 info_detail => info_detail );
+
+    sink_monitor : process
+      variable L : line;
+    begin
+      wait on fork_arc(index);
+      write(L, string'("sink_monitor(" & index_string & "): at "));
+      write(L, now, unit => ns);
+      write(L, string'(", "));
+      write(L, fork_arc(index).token, ns);
+      writeline(output, L);
+    end process sink_monitor;
+
+  end generate sinks;
+
+
+end architecture fork;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jn.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jn.vhd
new file mode 100644
index 0000000..45ac083
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jn.vhd
@@ -0,0 +1,128 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-jn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture join of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  constant num_outputs : positive := 4;
+  constant probabilities : probability_vector(1 to num_outputs - 1)
+    := ( 0.2, 0.4, 0.1 );
+
+  signal source_arc, join_arc : arc_type;
+  signal fork_arc : arc_vector(1 to num_outputs);
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => source_arc,
+               info_detail => info_detail );
+
+  fork1 : entity qsim.fork(behavior)
+    generic map ( name => "fork1",
+                  probabilities => probabilities,
+                  seed => sample_seeds(2),
+                  time_unit => ns,
+                  info_file_name => "fork1.dat" )
+    port map ( in_arc => source_arc,
+               out_arc => fork_arc,
+               info_detail => info_detail );
+
+
+  join1 : entity qsim.join(behavior)
+    generic map ( name => "join1",
+                  time_unit => ns,
+                  info_file_name => "join1.dat" )
+    port map ( in_arc => fork_arc,
+               out_arc => join_arc,
+               info_detail => info_detail );
+
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => join_arc,
+               info_detail => info_detail );
+
+
+  source_monitor : process is
+                             variable L : line;
+  begin
+    wait on source_arc;
+    write(L, string'("source_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, source_arc.token, ns);
+    writeline(output, L);
+  end process source_monitor;
+
+
+  forks : for index in 1 to num_outputs generate
+
+    constant index_string : string := integer'image(index);
+
+  begin
+
+    fork_monitor : process
+      variable L : line;
+    begin
+      wait on fork_arc(index);
+      write(L, string'("fork_monitor(" & index_string & "): at "));
+      write(L, now, unit => ns);
+      write(L, string'(", "));
+      write(L, fork_arc(index).token, ns);
+      writeline(output, L);
+    end process fork_monitor;
+
+  end generate forks;
+
+
+  sink_monitor : process
+    variable L : line;
+  begin
+    wait on join_arc;
+    write(L, string'("sink_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, join_arc.token, ns);
+    writeline(output, L);
+  end process sink_monitor;
+
+
+end architecture join;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jnsth.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jnsth.vhd
new file mode 100644
index 0000000..f80fd52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jnsth.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-jnsth.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+use std.textio.all;
+
+architecture join_synth of test_bench is
+
+  use qsim.qsim_types.all;
+
+  constant num_outputs : positive := 4;
+
+  signal fork_arc : arc_vector(1 to num_outputs);
+  signal join_arc : arc_type;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  generator : process is
+  begin
+    fork_arc(1) <= (true,  ("generator           ", 9,  0, now));
+    fork_arc(2) <= (true,  ("generator           ", 9,  1, now));    wait for 0 ns;
+    fork_arc(3) <= (true,  ("generator           ", 9,  2, now));
+    fork_arc(4) <= (true,  ("generator           ", 9,  3, now));    wait for 10 ns;
+
+    fork_arc(1) <= (false, ("generator           ", 9,  4, now));
+    fork_arc(2) <= (false, ("generator           ", 9,  5, now));    wait for 0 ns;
+    fork_arc(3) <= (false, ("generator           ", 9,  6, now));
+    fork_arc(4) <= (false, ("generator           ", 9,  7, now));    wait for 0 ns;
+    fork_arc(1) <= (true,  ("generator           ", 9,  8, now));
+    fork_arc(2) <= (true,  ("generator           ", 9,  9, now));    wait for 0 ns;
+    fork_arc(3) <= (true,  ("generator           ", 9, 10, now));
+    fork_arc(4) <= (true,  ("generator           ", 9, 11, now));    wait for 0 ns;
+    fork_arc(1) <= (false, ("generator           ", 9, 12, now));
+    fork_arc(2) <= (false, ("generator           ", 9, 13, now));    wait for 0 ns;
+    fork_arc(3) <= (false, ("generator           ", 9, 14, now));
+    fork_arc(4) <= (false, ("generator           ", 9, 15, now));    wait for 10 ns;
+
+    wait;
+  end process generator;
+
+  join1 : entity qsim.join(behavior)
+    generic map ( name => "join1",
+                  time_unit => ns,
+                  info_file_name => "join1.dat" )
+    port map ( in_arc => fork_arc,
+               out_arc => join_arc,
+               info_detail => info_detail );
+
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => join_arc,
+               info_detail => info_detail );
+
+
+  forks : for index in 1 to num_outputs generate
+
+    constant index_string : string := integer'image(index);
+
+  begin
+
+    fork_monitor : process
+      variable L : line;
+    begin
+      wait on fork_arc(index);
+      write(L, string'("fork_monitor(" & index_string & "): at "));
+      write(L, now, unit => ns);
+      write(L, string'(", "));
+      write(L, fork_arc(index).token, ns);
+      writeline(output, L);
+    end process fork_monitor;
+
+  end generate forks;
+
+
+  sink_monitor : process
+    variable L : line;
+  begin
+    wait on join_arc;
+    write(L, string'("sink_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, join_arc.token, ns);
+    writeline(output, L);
+  end process sink_monitor;
+
+
+end architecture join_synth;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-qs.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-qs.vhd
new file mode 100644
index 0000000..923f692
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-qs.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-qs.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture queue_server of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  signal source_arc, queue_arc, server_arc : arc_type;
+  signal server_ready : boolean;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => source_arc,
+               info_detail => info_detail );
+
+  queue1 : entity qsim.queue(behavior)
+    generic map ( name => "queue1",
+                  time_unit => ns,
+                  info_file_name => "queue1.dat" )
+    port map ( in_arc => source_arc,
+               out_arc => queue_arc,  out_ready => server_ready,
+               info_detail => info_detail );
+
+  server1 : entity qsim.server(behavior)
+    generic map ( name => "server1",
+                  distribution => fixed,  mean_service_time => 120 ns,
+                  seed => sample_seeds(2),
+                  time_unit => ns,
+                  info_file_name => "server1.dat" )
+    port map ( in_arc => queue_arc,  in_ready => server_ready,
+               out_arc => server_arc,
+               info_detail => info_detail );
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => server_arc,
+               info_detail => info_detail );
+
+
+  source_monitor : process is
+                             variable L : line;
+  begin
+    wait on source_arc;
+    write(L, string'("source_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, source_arc.token, ns);
+    writeline(output, L);
+  end process source_monitor;
+
+  queue_monitor : process is
+                            variable L : line;
+  begin
+    wait on queue_arc;
+    write(L, string'("queue_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, queue_arc.token, ns);
+    writeline(output, L);
+  end process queue_monitor;
+
+  server_monitor : process is
+                             variable L : line;
+  begin
+    wait on server_arc;
+    write(L, string'("server_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, server_arc.token, ns);
+    writeline(output, L);
+  end process server_monitor;
+
+
+end architecture queue_server;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-snk.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-snk.vhd
new file mode 100644
index 0000000..45e86ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-snk.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-snk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture sink of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  signal a : arc_type;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => a,
+               info_detail => info_detail );
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => a,
+               info_detail => info_detail );
+
+  monitor : process is
+
+                      variable L : line;
+
+  begin
+    wait on a;
+    write(L, string'("monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(" received "));
+    write(L, a.token, ns);
+    writeline(output, L);
+  end process monitor;
+
+end architecture sink;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd
new file mode 100644
index 0000000..865ed89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-src.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+use qsim.qsim_types.all;
+use random.random.all;
+
+architecture source of test_bench is
+
+  signal a : arc_type;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(0),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => a,
+               info_detail => info_detail );
+
+  monitor : process is
+
+                      variable L : line;
+
+  begin
+    wait on a;
+    write(L, string'("monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(" received "));
+    write(L, a.token, ns);
+    writeline(output, L);
+  end process monitor;
+
+end architecture source;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb.vhd
new file mode 100644
index 0000000..7358b25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench is
+
+end entity test_bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo-b.vhd
new file mode 100644
index 0000000..5c00f14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo-b.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tkfifo-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package body token_fifo_adt is
+
+  function new_fifo return fifo_type is
+  begin
+    return new fifo_record'( null, null );
+  end function new_fifo;
+
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean ) is
+  begin
+    is_empty := fifo.head_entry = null;
+  end procedure test_empty;
+
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type ) is
+
+    variable new_entry : fifo_entry
+      := new fifo_entry_record'( next_entry => null,
+                                 element => element );
+  begin
+    if fifo.tail_entry /= null then
+      fifo.tail_entry.next_entry := new_entry;
+    else
+      fifo.head_entry := new_entry;
+    end if;
+    fifo.tail_entry := new_entry;
+  end procedure insert;
+
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type ) is
+    variable empty_fifo : boolean;
+    variable removed_entry : fifo_entry;
+  begin
+    test_empty(fifo, empty_fifo);
+    if empty_fifo then
+      report "remove from empty fifo" severity failure;
+    else
+      removed_entry := fifo.head_entry;
+      element := removed_entry.element;
+      fifo.head_entry := removed_entry.next_entry;
+      if fifo.head_entry = null then  -- fifo now empty
+        fifo.tail_entry := null;
+      end if;
+      deallocate(removed_entry);
+    end if;
+  end procedure remove;
+
+end package body token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo.vhd
new file mode 100644
index 0000000..06f2b00
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tkfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+package token_fifo_adt is
+
+  alias element_type is qsim.qsim_types.token_type;
+
+  type fifo_record;
+
+  type fifo_type is access fifo_record;
+
+  function new_fifo return fifo_type;
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean );
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type );
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type );
+
+  -- private types
+
+  type fifo_entry_record;
+
+  type fifo_entry is access fifo_entry_record;
+
+  type fifo_entry_record is record
+                              next_entry : fifo_entry;
+                              element : element_type;
+                            end record;
+
+  type fifo_record is record
+                        head_entry, tail_entry : fifo_entry;
+                      end record;
+
+end package token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo-b.vhd
new file mode 100644
index 0000000..93618fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo-b.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_wtfifo-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package body waiting_token_fifo_adt is
+
+  function new_fifo return fifo_type is
+  begin
+    return new fifo_record'( null, null );
+  end function new_fifo;
+
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean ) is
+  begin
+    is_empty := fifo.head_entry = null;
+  end procedure test_empty;
+
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type ) is
+
+    variable new_entry : fifo_entry
+      := new fifo_entry_record'( next_entry => null,
+                                 element => element );
+  begin
+    if fifo.tail_entry /= null then
+      fifo.tail_entry.next_entry := new_entry;
+    else
+      fifo.head_entry := new_entry;
+    end if;
+    fifo.tail_entry := new_entry;
+  end procedure insert;
+
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type ) is
+    variable empty_fifo : boolean;
+    variable removed_entry : fifo_entry;
+  begin
+    test_empty(fifo, empty_fifo);
+    if empty_fifo then
+      report "remove from empty fifo" severity failure;
+    else
+      removed_entry := fifo.head_entry;
+      element := removed_entry.element;
+      fifo.head_entry := removed_entry.next_entry;
+      if fifo.head_entry = null then  -- fifo now empty
+        fifo.tail_entry := null;
+      end if;
+      deallocate(removed_entry);
+    end if;
+  end procedure remove;
+
+end package body waiting_token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo.vhd
new file mode 100644
index 0000000..5da8d94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_wtfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+package waiting_token_fifo_adt is
+
+  alias element_type is qsim.queue_types.waiting_token_type;
+
+  type fifo_record;
+
+  type fifo_type is access fifo_record;
+
+  function new_fifo return fifo_type;
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean );
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type );
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type );
+
+  -- private types
+
+  type fifo_entry_record;
+
+  type fifo_entry is access fifo_entry_record;
+
+  type fifo_entry_record is record
+                              next_entry : fifo_entry;
+                              element : element_type;
+                            end record;
+
+  type fifo_record is record
+                        head_entry, tail_entry : fifo_entry;
+                      end record;
+
+end package waiting_token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_01.vhd
new file mode 100644
index 0000000..50ae344
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_01.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package utility_definitions is
+
+  constant word_size : natural := 16;
+
+end package utility_definitions;
+
+
+----------------------------------------------------------------
+
+
+library utilities;
+
+entity ch_20_01 is
+
+end entity ch_20_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_01 is
+begin
+
+
+  process is
+  begin
+
+    report
+
+      -- code from book:
+
+      utilities.utility_definitions.word_size'simple_name
+
+      -- end of code from book
+
+      ;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_02.vhd
new file mode 100644
index 0000000..fddabba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_02.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library project;
+
+entity ch_20_02 is
+end entity ch_20_02;
+
+
+architecture test of ch_20_02 is
+begin
+
+  process is
+
+            --use project.mem_pkg;
+            --use project.mem_pkg.all;
+            use work.mem_pkg;
+          use work.mem_pkg.all;
+          variable words : word_array(0 to 3);
+
+  begin
+    assert
+      -- code from book (in text)
+      mem_pkg'path_name = ":project:mem_pkg:"
+      -- end code from book
+      ;
+    report mem_pkg'path_name;
+
+    assert
+      -- code from book (in text)
+      word'path_name = ":project:mem_pkg:word"
+      -- end code from book
+      ;
+    report word'path_name;
+
+    assert
+      -- code from book (in text)
+      word_array'path_name = ":project:mem_pkg:word_array"
+      -- end code from book
+      ;
+
+    report word_array'path_name;
+
+    assert
+      -- code from book (in text)
+      load_array'path_name = ":project:mem_pkg:load_array"
+      -- end code from book
+      ;
+    report load_array'path_name;
+
+    load_array(words, "/dev/null");
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_03.vhd
new file mode 100644
index 0000000..3b1a3b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_03.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_03_a is
+
+  -- code from book:
+
+  attribute cell_name : string;
+  attribute pin_number : positive;
+  attribute max_wire_delay : delay_length;
+  attribute encoding : bit_vector;
+
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  attribute cell_position : coordinate;
+
+  -- end of code from book
+
+end package ch_20_03_a;
+
+
+
+
+entity ch_20_03 is
+
+end entity ch_20_03;
+
+
+----------------------------------------------------------------
+
+
+architecture std_cell of ch_20_03 is
+
+  use work.ch_20_03_a.all;
+
+  signal enable, clk : bit;
+
+  type state_type is (idle_state, other_state);
+
+  -- code from book:
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+  attribute pin_number of enable : signal is 14;
+  attribute max_wire_delay of clk : signal is 50 ps;
+  attribute encoding of idle_state : literal is b"0000";
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+  -- end of code from book
+
+begin
+
+  the_fpu : block is
+  begin
+  end block the_fpu;
+
+  process is
+            use std.textio.all;
+          variable L : line;
+  begin
+    write(L, std_cell'cell_name);
+    writeline(output, L);
+    write(L, enable'pin_number);
+    writeline(output, L);
+    write(L, clk'max_wire_delay);
+    writeline(output, L);
+    write(L, idle_state[return state_type]'encoding);
+    writeline(output, L);
+    write(L, length'image(the_fpu'cell_position.x));
+    write(L, ' ');
+    write(L, length'image(the_fpu'cell_position.y));
+    writeline(output, L);
+
+    wait;
+  end process;
+
+end architecture std_cell;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_04.vhd
new file mode 100644
index 0000000..b8934d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_04.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_04 is
+
+  attribute cell_name : string;
+
+end package ch_20_04;
+
+
+
+entity flipflop is
+
+end entity flipflop;
+
+
+
+use work.ch_20_04.all;
+
+-- code from book:
+
+architecture std_cell of flipflop is
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+
+  -- . . .       -- other declarations
+
+begin
+  -- . . .
+end architecture std_cell;
+
+-- end of code from book
+
+
+
+-- code from book:
+
+package model_utilities is
+
+  attribute optimize : string;
+  attribute optimize of model_utilities : package is "level_4";
+
+  -- . . .
+
+end package model_utilities;
+
+-- end of code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_05.vhd
new file mode 100644
index 0000000..7e46ff3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_05.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_05 is
+
+end entity ch_20_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_05 is
+
+  type stimulus_list is array (natural range <>) of integer;
+
+  -- code from book:
+
+  function "&" ( a, b : stimulus_list ) return stimulus_list;
+
+  attribute debug : string;
+  attribute debug of
+    "&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
+    "source_statement_step";
+
+
+    type mvl is ('X', '0', '1', 'Z');
+    type mvl_vector is array ( integer range <>) of mvl;
+    function resolve_mvl ( drivers : mvl_vector ) return mvl;
+
+    subtype resolved_mvl is resolve_mvl mvl;
+
+
+    type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
+    attribute builtin : builtin_types;
+    
+    attribute builtin of resolved_mvl : subtype is builtin_mvl;
+
+    -- end of code from book
+
+    function "&" ( a, b : stimulus_list ) return stimulus_list is
+    begin
+      return stimulus_list'(1 to 0 => 0);
+    end function "&";
+
+    function resolve_mvl ( drivers : mvl_vector ) return mvl is
+    begin
+      return drivers(drivers'left);
+    end function resolve_mvl;
+
+  begin
+  end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd
new file mode 100644
index 0000000..549f606
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_06 is
+
+end entity ch_20_06;
+
+
+----------------------------------------------------------------
+
+use std.textio.all;
+
+architecture test of ch_20_06 is
+
+  subtype encoding_type is bit_vector(1 downto 0);
+  attribute encoding : encoding_type;
+
+begin
+
+
+  process1 : process is
+
+                       -- code from book:
+
+                       type controller_state is (idle, active, fail_safe);
+                     type load_level is (idle, busy, overloaded);
+
+                     attribute encoding of idle [ return controller_state ] : literal is b"00";
+                                                                                         attribute encoding of active [ return controller_state ] : literal is b"01";
+                                                                                                                                                               attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
+
+                                                                                                                                                                                                                                        -- end of code from book
+
+                                                                                                                                                                                                                                        variable L : line;
+
+                                                                                                                                                               begin
+                                                                                                                                                                 write(L, string'("process1"));
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, idle [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, active [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, fail_safe [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 wait;
+                                                                                                                                                               end process process1;
+
+
+                                                                                                                                                               process2 : process is
+
+                                                                                                                                                                                    type controller_state is (idle, active, fail_safe);
+                                                                                                                                                                                  type load_level is (idle, busy, overloaded);
+
+                                                                                                                                                                                  attribute encoding of idle : literal is b"11";
+
+                                                                                                                                                                                  variable L : line;
+
+                                                                                                                                                               begin
+                                                                                                                                                                 write(L, string'("process2"));
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, idle [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, idle [ return load_level ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 wait;
+                                                                                                                                                               end process process2;
+
+
+                                                                                         end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_07.vhd
new file mode 100644
index 0000000..9253f90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_07.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_07 is
+
+end entity ch_20_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_07 is
+
+  component multiplier is
+  end component multiplier;
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  type orientation_type is (up, down, left, right);
+
+  attribute cell_allocation : string;
+  attribute cell_position : coordinate;
+  attribute cell_orientation : orientation_type;
+
+  -- code from book:
+
+  attribute cell_allocation of mult : label is "wallace_tree_multiplier";
+  attribute cell_position of mult : label is ( 1200 um, 4500 um );
+  attribute cell_orientation of mult : label is down;
+
+  -- end of code from book
+
+begin
+
+  mult : component multiplier;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_08.vhd
new file mode 100644
index 0000000..0598e3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_08.vhd
@@ -0,0 +1,127 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_08 is
+
+end entity ch_20_08;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture std_cell of ch_20_08 is
+
+  attribute cell_name : string;
+  attribute pin_number : positive;
+  attribute max_wire_delay : delay_length;
+  attribute encoding : bit_vector;
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  attribute cell_position : coordinate;
+
+  type built_in_type is (bv_incr, std_incr);
+  attribute built_in : built_in_type;
+
+  signal enable, clk : bit;
+
+  type state_type is (idle_state, other_state);
+
+  type speed_range is (high, other_speed);
+  type coolant_level is (high, other_level);
+
+  attribute representation : string;
+
+  function increment ( vector : in bit_vector ) return bit_vector is
+  begin
+  end;
+
+  function increment ( vector : in std_logic_vector ) return std_logic_vector is
+  begin
+  end;
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+  attribute pin_number of enable : signal is 14;
+  attribute max_wire_delay of clk : signal is 50 ps;
+  attribute encoding of idle_state : literal is b"0000";
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+  attribute built_in of
+    increment [ bit_vector return bit_vector ] : function is bv_incr;
+                                                             attribute built_in of
+                                                               increment [ std_logic_vector return std_logic_vector ] : function is std_incr;
+                                                                                                                                    attribute representation of high [ return speed_range ] : literal is "byte";
+                                                                                                                                                                                                         attribute representation of high [ return coolant_level ] : literal is "word";
+
+                                                                                                                                                                                                         begin
+
+                                                                                                                                                                                                           the_fpu : block is
+                                                                                                                                                                                                           begin
+                                                                                                                                                                                                           end block the_fpu;
+
+                                                                                                                                                                                                           process is
+                                                                                                                                                                                                                     variable v1 : string(1 to 11);
+                                                                                                                                                                                                                   variable v2 : positive;
+                                                                                                                                                                                                                   variable v3 : time;
+                                                                                                                                                                                                                   variable v4 : bit_vector(0 to 3);
+                                                                                                                                                                                                                   variable v5 : coordinate;
+                                                                                                                                                                                                                   variable v6, v7 : built_in_type;
+                                                                                                                                                                                                                   variable v8, v9 : string(1 to 4);
+                                                                                                                                                                                                           begin
+
+                                                                                                                                                                                                             -- code from book included...
+
+                                                                                                                                                                                                             v1 := std_cell'cell_name ;
+                                                                                                                                                                                                             v2 := enable'pin_number ;
+                                                                                                                                                                                                             v3 := clk'max_wire_delay ;
+                                                                                                                                                                                                             -- workaround MTI bugs mt037/mt038
+                                                                                                                                                                                                             -- v4 := idle_state'encoding ;
+                                                                                                                                                                                                             v4 := idle_state[return state_type]'encoding ;
+                                                                                                                                                                                                             -- end workaround
+                                                                                                                                                                                                             v5 := the_fpu'cell_position ;
+
+                                                                                                                                                                                                             v6 := increment [ bit_vector return bit_vector ] 'built_in ;
+                                                                                                                                                                                                             v7 := increment [ std_logic_vector return std_logic_vector ] 'built_in ;
+
+                                                                                                                                                                                                             v8 := high [ return speed_range ] 'representation ;
+                                                                                                                                                                                                             v9 := high [ return coolant_level ] 'representation ;
+
+                                                                                                                                                                                                             -- end code from book
+
+                                                                                                                                                                                                             wait;
+                                                                                                                                                                                                           end process;
+
+                                                                                                                                                                                                         end architecture std_cell;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_09.vhd
new file mode 100644
index 0000000..327effa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_09.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_09_a is
+
+  attribute attr : integer;
+
+end package ch_20_09_a;
+
+
+
+use work.ch_20_09_a.all;
+
+entity e is
+  port ( p : in bit );
+  attribute attr of p : signal is 1;
+end entity e;
+
+
+architecture arch of e is
+begin
+
+  assert false report integer'image(p'attr);
+
+end architecture arch;
+
+
+
+use work.ch_20_09_a.all;
+
+entity ch_20_09 is
+end entity ch_20_09;
+
+
+
+architecture test of ch_20_09 is
+
+  signal s : bit;
+
+  attribute attr of s : signal is 2;
+
+begin
+
+  -- code from book
+
+  c1 : entity work.e(arch)
+    port map ( p => s );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_10.vhd
new file mode 100644
index 0000000..1ed33d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_10.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_10 is
+
+  -- code from book
+
+  attribute foreign : string;
+
+  -- end code from book
+
+end package ch_20_10;
+
+
+
+entity and2 is
+end entity and2;
+
+
+-- code from book
+
+architecture accelerated of and2 is
+  attribute foreign of accelerated : architecture is
+    "accelerate/function:and_2in/nocheck";
+begin
+end architecture accelerated;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_11.vhd
new file mode 100644
index 0000000..202ab84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_11.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_11 is
+
+end entity ch_20_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_11 is
+
+  component comp is
+  end component comp;
+
+  signal clk_phase1, clk_phase2 : bit;
+
+  -- code from book:
+
+  group signal_pair is (signal, signal);
+
+  group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
+
+  attribute max_skew : time;
+
+  attribute max_skew of clock_pair : group is 200 ps;
+
+  group component_instances is ( label <> );
+
+  group U1 : component_instances ( nand1, nand2, nand3 );
+  group U2 : component_instances ( inv1, inv2 );
+
+  attribute IC_allocation : string;
+
+  attribute IC_allocation of U1 : group is "74LS00";
+  attribute IC_allocation of U2 : group is "74LS04";
+
+  -- end of code from book
+
+begin
+
+
+  nand1 : component comp;
+  nand2 : component comp;
+  nand3 : component comp;
+  inv1 : component comp;
+  inv2 : component comp;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd
new file mode 100644
index 0000000..574c5c3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity flipflop is
+  generic ( Tsetup : delay_length );
+  port ( clk, d : in bit;  q : out bit );
+end entity flipflop;
+
+
+-- code from book
+
+architecture behavior of flipflop is
+begin
+
+  timing_check : process (clk) is
+  begin
+    if clk = '1' then
+      assert d'last_event >= Tsetup
+        report "set up violation detected in " & timing_check'path_name
+        severity error;
+    end if;
+  end process timing_check;
+
+  -- . . .    -- functionality
+
+end architecture behavior;
+
+-- end code from book
+
+
+
+entity fg_20_05 is
+end entity fg_20_05;
+
+
+architecture test of fg_20_05 is
+
+  signal clk, d, q : bit;
+
+begin
+
+  dut : entity work.flipflop(behavior)
+    generic map ( Tsetup => 3 ns )
+    port map ( clk => clk, d => d, q => q );
+
+  clk <= '1' after 10 ns, '0' after 20 ns;
+
+  d <= '1' after 8 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_06.vhd
new file mode 100644
index 0000000..027ede5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_06.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_06.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package mem_pkg is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (natural range <>) of word;
+
+  procedure load_array ( words : out word_array;  file_name : string );
+
+end package mem_pkg;
+
+package body mem_pkg is
+
+  procedure load_array ( words : out word_array;  file_name : string ) is
+    -- words'path_name = ":project:mem_pkg:load_array:words"
+
+    use std.textio.all;
+    file load_file : text open read_mode is file_name;
+    -- load_file'path_name = ":project:mem_pkg:load_array:load_file"
+
+    procedure read_line is
+      -- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
+      variable current_line : line;
+      -- current_line'path_name =
+      --    ":project:mem_pkg:load_array:read_line:current_line"
+    begin
+      -- . . .
+      -- not in book
+      report current_line'path_name;
+      -- end not in book
+    end procedure read_line;
+
+  begin  -- load_array
+    -- . . .
+    -- not in book
+    report mem_pkg'path_name;
+    report words'path_name;
+    report load_file'path_name;
+    report read_line'path_name;
+    read_line;
+    -- end not in book
+  end procedure load_array;
+
+end package body mem_pkg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd
new file mode 100644
index 0000000..31d7803
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity top is
+end entity top;
+
+architecture top_arch of top is
+
+  signal top_sig : -- . . .;                  -- 1
+    --
+    bit;
+    --
+
+begin
+
+  stimulus : process
+    is
+      variable var : -- . . .;                  -- 2
+      --
+      bit;
+    --
+  begin
+    -- . . .
+    --
+    report "--1: " & top'path_name;
+    report "--1: " & top'instance_name;
+    report "--1: " & top_sig'path_name;
+    report "--1: " & top_sig'instance_name;
+    report "--2: " & stimulus'path_name;
+    report "--2: " & stimulus'instance_name;
+    report "--2: " & var'path_name;
+    report "--2: " & var'instance_name;
+    wait;
+    --
+  end process stimulus;
+
+  rep_gen : for index in 0 to 7 generate
+  begin
+
+    end_gen : if index = 7 generate
+      signal end_sig : -- . . .;              -- 3
+        --
+        bit;
+        --
+    begin
+      -- . . .
+      assert false report "--3: " & end_sig'path_name;
+      assert false report "--3: " & end_sig'instance_name;
+      --
+    end generate end_gen;
+
+    other_gen : if index /= 7 generate
+      signal other_sig : -- . . .;            -- 4
+        --
+        bit;
+        --
+    begin
+      other_comp : entity work.bottom(bottom_arch)
+        port map ( -- . . . );
+          --
+          port_name => open );
+      assert false report "--4: " & other_sig'path_name;
+      assert false report "--4: " & other_sig'instance_name;
+      --
+    end generate other_gen;
+
+  end generate rep_gen;
+
+end architecture top_arch;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_09.vhd
new file mode 100644
index 0000000..5ce10ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_09.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity bottom is
+  port ( -- . . . );
+    --
+    port_name : in bit := '0' );
+  --
+end entity bottom;
+
+--------------------------------------------------
+
+architecture bottom_arch of bottom is
+
+  signal bot_sig : -- . . .;          -- 5
+    --
+    bit;
+  --
+
+  procedure proc ( -- . . . ) is
+    --
+    param_name : in bit := '0' ) is
+    --
+    variable v : -- . . .;            -- 6
+      --
+      bit;
+    --
+  begin
+    -- . . .
+    --
+    report "--6: " & v'path_name;
+    report "--6: " & v'instance_name;
+    --
+  end procedure proc;
+
+begin
+
+  delays : block is
+                   constant d : integer := 1;      -- 7
+  begin
+    -- . . .
+    --
+    assert false report "--7: " & d'path_name;
+    assert false report "--7: " & d'instance_name;
+    --
+  end block delays;
+
+  func : block is
+  begin
+
+    process is
+              variable v : -- . . .;          -- 8
+            --
+            bit;
+            --
+    begin
+      -- . . .
+      --
+      report "--5: " & bot_sig'path_name;
+      report "--5: " & bot_sig'instance_name;
+      report "--8: " & v'path_name;
+      report "--8: " & v'instance_name;
+      proc(param_name => open);
+      wait;
+      --
+      --
+    end process;
+
+  end block func;
+
+end architecture bottom_arch;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_11.vhd
new file mode 100644
index 0000000..bc11774
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_11.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_20_11 is
+end entity fg_20_11;
+
+
+architecture test of fg_20_11 is
+begin
+
+-- code from book
+
+  process is
+
+            procedure add_with_overflow ( a, b : in integer;
+                                          sum : out integer;
+                                          overflow : out boolean ) is -- . . .
+
+    -- not in book
+  begin
+  end;
+  -- end not in book
+
+  procedure add_with_overflow ( a, b : in bit_vector;
+                                sum : out bit_vector;
+                                overflow : out boolean ) is -- . . .
+
+    -- not in book
+  begin
+  end;
+  -- end not in book
+
+  attribute built_in : string;
+
+  attribute built_in of
+    add_with_overflow [ integer, integer,
+                        integer, boolean ] : procedure is "int_add_overflow";
+
+  attribute built_in of
+    add_with_overflow [ bit_vector, bit_vector,
+                        bit_vector, boolean ] : procedure is "bit_vector_add_overflow";
+
+  begin
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process;
+
+-- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_12.vhd
new file mode 100644
index 0000000..cc0e5c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_12.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package physical_attributes is
+
+  -- code from book (in text)
+
+  attribute layout_ignore : boolean;
+  attribute pin_number : positive;
+
+  -- end code from book
+
+end package physical_attributes;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.physical_attributes.all;
+
+entity \74x138\ is
+  generic ( Tpd : time );
+  port ( en1, en2a_n, en2b_n : in std_logic;
+         s0, s1, s2 : in std_logic;
+         y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
+
+  attribute layout_ignore of Tpd : constant is true;
+
+  attribute pin_number of s0 : signal is 1;
+  attribute pin_number of s1 : signal is 2;
+  attribute pin_number of s2 : signal is 3;
+  attribute pin_number of en2a_n : signal is 4;
+  -- . . .
+
+end entity \74x138\;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_13.vhd
new file mode 100644
index 0000000..745f4eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_13.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_20_13 is
+end entity fg_20_13;
+
+
+architecture test of fg_20_13 is
+
+  attribute trace : string;
+
+  subtype byte is bit_vector(7 downto 0);
+  type byte_vector is array (natural range <>) of byte;
+
+  type ram_bus is record
+                    d : byte;
+                    cmd, status, clk : bit;
+                  end record ram_bus;
+
+  -- code from book
+
+  procedure mem_read ( address : in natural;
+                       result : out byte_vector;
+                       signal memory_bus : inout ram_bus ) is
+
+    attribute trace of address : constant is "integer/hex";
+    attribute trace of result : variable is "byte/multiple/hex";
+    attribute trace of memory_bus : signal is
+      "custom/command=rambus.cmd";
+    -- . . .
+
+  begin
+    -- . . .
+    -- not in book
+    report address'trace;
+    report result'trace;
+    report memory_bus'trace;
+    -- end not in book
+  end procedure mem_read;
+
+  -- end code from book
+
+  signal memory_bus : ram_bus;
+
+begin
+
+  process is
+            variable address : natural;
+          variable result : byte_vector(0 to 3);
+  begin
+    mem_read ( address, result, memory_bus );
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_14.vhd
new file mode 100644
index 0000000..62581b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_14.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package graphics_pkg is
+
+  attribute graphic_symbol : string;
+  attribute graphic_style : string;
+
+end package graphics_pkg;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+--library graphics;
+library work;
+
+package gate_components is
+
+  --use graphics.graphics_pkg.graphic_symbol,
+  -- graphics.graphics_pkg.graphic_style;
+  use work.graphics_pkg.all;
+
+  component and2 is
+                   generic ( prop_delay : delay_length );
+                 port ( a, b : in std_logic;  y : out std_logic );
+  end component and2;
+
+  attribute graphic_symbol of and2 : component is "and2";
+  attribute graphic_style of and2 : component is "color:default, weight:bold";
+
+  -- . . .
+
+end package gate_components;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_15.vhd
new file mode 100644
index 0000000..65d281e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_15.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package cell_attributes is
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  attribute cell_position : coordinate;
+
+end package cell_attributes;
+
+
+
+entity CPU is
+end entity CPU;
+
+
+-- code from book
+
+architecture cell_based of CPU is
+
+  component fpu is
+                  port ( -- . . . );
+                    -- not in book
+                    port_name : bit := '0' );
+                -- end not in book
+  end component;
+
+  use work.cell_attributes.all;
+
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+  -- . . .
+
+begin
+
+  the_fpu : component fpu
+    port map ( -- . . . );
+      -- not in book
+      port_name => open );
+  -- end not in book
+
+  -- . . .
+
+end architecture cell_based;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_16.vhd
new file mode 100644
index 0000000..c95c4e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_16.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_16.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_20_16 is
+end entity fg_20_16;
+
+
+architecture test of fg_20_16 is
+
+  signal clk : bit;
+
+  attribute synthesis_hint : string;
+
+begin
+
+  -- code from book
+
+  controller : process is
+
+                         attribute synthesis_hint of control_loop : label is
+                       "implementation:FSM(clk)";
+                       -- . . .
+
+  begin
+    -- . . .    -- initialization
+    control_loop : loop
+      wait until clk = '1';
+      -- . . .
+    end loop;
+  end process controller;
+
+  -- end code fom book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_17.vhd
new file mode 100644
index 0000000..7e3ce06
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_17.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_17.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package voltage_defs is
+
+  type voltage is range -2e9 to +2e9
+    units
+      nV;
+      uV = 1000 nV;
+      mV = 1000 uV;
+      V = 1000 mV;
+    end units voltage;
+
+  attribute resolution : real;
+
+  attribute resolution of nV : units is 1.0;
+                                     attribute resolution of uV : units is 0.01;
+                                                                        attribute resolution of mV : units is 0.01;
+                                                                                                           attribute resolution of V : units is 0.001;
+
+                                                                                                                                   end package voltage_defs;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_18.vhd
new file mode 100644
index 0000000..a19dac1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_18.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_18.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package timing_attributes is
+
+  attribute max_wire_delay : delay_length;
+
+end package timing_attributes;
+
+
+entity sequencer is
+end entity sequencer;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.timing_attributes.all;
+
+architecture structural of sequencer is
+
+  signal recovered_clk1, recovered_clk2 : std_logic;
+  signal test_enable : std_logic;
+  signal test_data : std_logic_vector(0 to 15);
+
+  attribute max_wire_delay of
+    recovered_clk1, recovered_clk2 : signal is 100 ps;
+
+  attribute max_wire_delay of others : signal is 200 ps;
+
+  -- . . .
+
+begin
+  -- . . .
+  -- not in book
+  assert false report time'image(recovered_clk1'max_wire_delay) severity note;
+  assert false report time'image(recovered_clk2'max_wire_delay) severity note;
+  assert false report time'image(test_enable'max_wire_delay) severity note;
+  assert false report time'image(test_data'max_wire_delay) severity note;
+  -- end not in book
+end architecture structural;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_19.vhd
new file mode 100644
index 0000000..3636dab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_19.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_19.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package display_interface is
+
+  -- . . .
+
+  -- not in book
+  type status_type is (t1, t2, t3);
+  -- end not in book
+
+  procedure create_window ( size_x, size_y : natural;
+                            status : out status_type );
+
+  attribute foreign of create_window : procedure is
+    "language Ada;  with window_operations;" &
+    "bind to window_operations.create_window;" &
+    "parameter size_x maps to size_x : in natural;" &
+    "parameter size_y maps to size_y : in natural;" &
+    "parameter status maps to status : out window_operations.status_type;" &
+    "others map to default";
+
+  -- . . .
+
+end package display_interface;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd
new file mode 100644
index 0000000..b3090e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_20.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package constraints is
+
+  -- code from book (in text)
+
+  group port_pair is ( signal, signal );
+
+  attribute max_prop_delay : time;
+
+  -- end code from book
+
+end package constraints;
+
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.constraints.port_pair, work.constraints.max_prop_delay;
+
+entity clock_buffer is
+  port ( clock_in : in std_logic;
+         clock_out1, clock_out2, clock_out3 : out std_logic );
+
+  group clock_to_out1 : port_pair ( clock_in, clock_out1 );
+  group clock_to_out2 : port_pair ( clock_in, clock_out2 );
+  group clock_to_out3 : port_pair ( clock_in, clock_out3 );
+
+  attribute max_prop_delay of clock_to_out1 : group is 2 ns;
+  attribute max_prop_delay of clock_to_out2 : group is 2 ns;
+  attribute max_prop_delay of clock_to_out3 : group is 2 ns;
+
+end entity clock_buffer;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd
new file mode 100644
index 0000000..d3d4efa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_ch_21_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_21_01 is
+
+end entity ch_21_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_21_01 is
+
+  type std_ulogic is (t1, t2, t3);
+  subtype std_logic is std_ulogic;
+
+  -- code from book:
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+  type std_logic_vector is array ( natural range <>) of std_logic;
+
+  -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_02.vhd
new file mode 100644
index 0000000..a34d961
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_02.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_ch_21_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_21_02 is
+
+end entity ch_21_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_21_02 is
+
+  signal s : bit;
+
+begin
+
+  -- code from book:
+
+  p : postponed process is
+                          -- . . .
+                begin
+                  -- . . .
+                  wait until s = '1';
+                  -- . . .       -- s may not be '1'!!
+                  -- not in book
+                  report bit'image(s);
+                  wait;
+                  -- end not in book
+                end postponed process p;
+
+                                      -- end of code from book
+
+                                      stimulus : process is
+                                      begin
+                                        wait for 10 ns;
+                                        s <= '1';
+                                        wait for 0 ns;
+                                        s <= '0';
+                                        wait;
+                                      end process stimulus;
+
+                              end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd
new file mode 100644
index 0000000..adc42b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_ch_21_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity controller is
+end entity controller;
+
+
+-- code from book
+
+architecture instrumented of controller is
+
+  shared variable operation_count : natural := 0;
+  -- . . .
+
+begin
+  -- . . .
+end architecture instrumented;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd
new file mode 100644
index 0000000..3e784fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity D_flipflop is
+  port ( clk, d : in bit;  q : buffer bit );
+end entity D_flipflop;
+
+
+architecture behavioral of D_flipflop is
+begin
+  q <= d when clk'event and clk = '1';
+end architecture behavioral;
+
+
+
+entity inverter is
+  port ( a : in bit;  y : out bit );
+end entity inverter;
+
+
+architecture behavioral of inverter is
+begin
+  y <= not a;
+end architecture behavioral;
+
+
+
+-- code from book
+
+entity count2 is
+  port ( clk : in bit;  q0, q1 : buffer bit );
+end entity count2;
+
+--------------------------------------------------
+
+architecture buffered_outputs of count2 is
+
+  component D_flipflop is
+                         port ( clk, d : in bit;  q : buffer bit );
+  end component D_flipflop;
+
+  component inverter is
+                       port ( a : in bit;  y : out bit );
+  end component inverter;
+
+  signal q0_n, q1_n : bit;
+
+begin
+
+  bit0 : component D_flipflop
+    port map ( clk => clk, d => q0_n, q => q0 );
+
+  inv0 : component inverter
+    port map ( a => q0, y => q0_n );
+
+  bit1 : component D_flipflop
+    port map ( clk => q0_n, d => q1_n, q => q1 );
+
+  inv1 : component inverter
+    port map ( a => q1, y => q1_n );
+
+end architecture buffered_outputs;
+
+-- end code from book
+
+
+
+entity fg_21_01 is
+end entity fg_21_01;
+
+
+architecture test of fg_21_01 is
+
+  signal clk, q0, q1 : bit;
+
+begin
+
+  dut : entity work.count2(buffered_outputs)
+    port map ( clk => clk, q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 10 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_02.vhd
new file mode 100644
index 0000000..cb9a1b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_02.vhd
@@ -0,0 +1,127 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_02.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package project_util is
+
+                 -- code from book (in text)
+
+                 function "<" ( bv1, bv2 : bit_vector ) return boolean;
+
+                 subtype word is std_logic_vector(31 downto 0);
+
+                 -- end code from book
+
+               end package project_util;
+
+
+               package body project_util is
+
+                 function "<" ( bv1, bv2 : bit_vector ) return boolean is
+                   variable tmp1 : bit_vector(bv1'range) := bv1;
+                   variable tmp2 : bit_vector(bv2'range) := bv2;
+                 begin
+                   assert bv1'length = bv2'length
+                     report "vectors are of different length in ""<"" comparison"
+                     severity failure;
+                   tmp1(tmp1'left) := not tmp1(tmp1'left);
+                   tmp2(tmp2'left) := not tmp2(tmp2'left);
+                   return std.standard."<" ( tmp1, tmp2 );
+                 end function "<";
+
+               end package body project_util;
+
+
+
+-- code from book
+
+               library ieee;  use ieee.std_logic_1164.all;
+               use work.project_util.all;
+
+               entity limit_checker is
+                 port ( input, lower_bound, upper_bound : in word;
+                        out_of_bounds : out std_logic );
+               end entity limit_checker;
+
+--------------------------------------------------
+
+               architecture behavioral of limit_checker is
+
+                 subtype bv_word is bit_vector(31 downto 0);
+
+                 function word_to_bitvector ( w : in word ) return bv_word is
+                 begin
+                   return To_bitvector ( w, xmap => '0' );
+                 end function word_to_bitvector;
+
+               begin
+
+                 algorithm : process (input, lower_bound, upper_bound) is
+                 begin
+                   if "<" ( bv1 => word_to_bitvector(input),
+                            bv2 => word_to_bitvector(lower_bound) )
+                     or "<" ( bv1 => word_to_bitvector(upper_bound),
+                              bv2 => word_to_bitvector(input) ) then
+                     out_of_bounds <= '1';
+                   else
+                     out_of_bounds <= '0';
+                   end if;
+                 end process algorithm;
+
+               end architecture behavioral;
+
+-- end code from book
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+               use work.project_util.all;
+
+               entity fg_21_02 is
+               end entity fg_21_02;
+
+
+               architecture test of fg_21_02 is
+
+                 signal input : word;
+                 signal out_of_bounds : std_logic;
+
+               begin
+
+                 dut : entity work.limit_checker(behavioral)
+                   port map ( input => input,
+                              lower_bound => X"FFFFFFF0", upper_bound => X"00000010",
+                              out_of_bounds => out_of_bounds );
+
+                 stimulus : input <= X"00000000",
+                                     X"00000008" after 10 ns,
+                                     X"00000010" after 20 ns,
+                                     X"00000018" after 30 ns,
+                                     X"FFFFFFF8" after 40 ns,
+                                     X"FFFFFFF0" after 50 ns,
+                                     X"FFFFFF00" after 60 ns;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_03.vhd
new file mode 100644
index 0000000..5f08601
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_03.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book (in text)
+
+entity random_source is
+  generic ( min, max : natural;
+            seed : natural;
+            interval : delay_length );
+  port ( number : out natural );
+end entity random_source;
+
+-- end code from book
+
+
+architecture fudged of random_source is
+begin
+
+  process is
+            variable next_number : natural := seed;
+  begin
+    if next_number > max then
+      next_number := min;
+    end if;
+    number <= next_number;
+    next_number := next_number + 1;
+    wait for interval;
+  end process;
+
+end architecture fudged;
+
+
+
+entity test_bench is
+end entity test_bench;
+
+
+-- code from book
+
+architecture random_test of test_bench is
+
+  subtype bv11 is bit_vector(10 downto 0);
+
+  function natural_to_bv11 ( n : natural ) return bv11 is
+    variable result : bv11 := (others => '0');
+    variable remaining_digits : natural := n;
+  begin
+    for index in result'reverse_range loop
+      result(index) := bit'val(remaining_digits mod 2);
+      remaining_digits := remaining_digits / 2;
+      exit when remaining_digits = 0;
+    end loop;
+    return result;
+  end function natural_to_bv11;
+
+  signal stimulus_vector : bv11;
+  -- . . .
+
+begin
+
+  stimulus_generator : entity work.random_source
+    generic map ( min => 0, max => 2**10 - 1, seed => 0,
+                  interval => 100 ns )
+    port map ( natural_to_bv11(number) => stimulus_vector );
+
+  -- . . .
+
+end architecture random_test;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.vhd
new file mode 100644
index 0000000..2647048
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_04.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity processor is
+               end entity processor;
+
+
+-- code from book
+
+               architecture rtl of processor is
+
+                 component latch is
+                                   generic ( width : positive );
+                                 port ( d : in std_ulogic_vector(0 to width - 1);
+                                        q : out std_ulogic_vector(0 to width - 1);
+                                        -- . . . );
+                                        -- not in book
+                                        other_port : in std_ulogic := '-' );
+                                 -- end not in book
+                 end component latch;
+
+                 component ROM is
+                                 port ( d_out : out std_ulogic_vector;  -- . . . );
+                                        -- not in book
+                                        other_port : in std_ulogic := '-' );
+                               -- end not in book
+                 end component ROM;
+
+                 subtype std_logic_word is std_logic_vector(0 to 31);
+
+                 signal source1, source2, destination : std_logic_word;
+                 -- . . .
+
+               begin
+
+                 temp_register : component latch
+                   generic map ( width => 32 )
+                   port map ( d => std_ulogic_vector(destination),
+                              std_logic_vector(q) => source1, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 constant_ROM : component ROM
+                   port map ( std_logic_word(d_out) => source2, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 -- . . .
+
+               end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd
new file mode 100644
index 0000000..12c6d98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity SR_flipflop is
+  port ( s_n, r_n : in bit;  q, q_n : inout bit );
+
+begin
+
+  postponed process (q, q_n) is
+            begin
+              assert now = 0 fs or q = not q_n
+                report "implementation error: q /= not q_n";
+            end postponed process;
+
+                          end entity SR_flipflop;
+
+--------------------------------------------------
+
+                                 architecture dataflow of SR_flipflop is
+                                 begin
+
+                                   gate_1 : q <= s_n nand q_n;
+                                   gate_2 : q_n <= r_n nand q;
+
+                                 end architecture dataflow;
+
+
+
+-- not in book
+
+                                 entity fg_21_05 is
+                                 end entity fg_21_05;
+
+
+                                 architecture test of fg_21_05 is
+
+                                   signal s_n, r_n, q, q_n : bit;
+
+                                 begin
+
+                                   dut : entity work.SR_flipflop
+                                     port map ( s_n, r_n, q, q_n );
+
+                                   s_n <= '1',
+                                          '0' after 10 ns, '1' after 15 ns,
+                                          '0' after 30 ns, '1' after 40 ns;
+
+                                   r_n <= '0', '1' after 5 ns,
+                                          '0' after 20 ns, '1' after 25 ns,
+                                          '0' after 30 ns, '1' after 35 ns;
+
+                                 end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_06.vhd
new file mode 100644
index 0000000..8095dc5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_06.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity multiprocessor is
+end entity multiprocessor;
+
+
+-- code from book
+
+architecture instrumented of multiprocessor is
+
+  -- not in book
+  constant num_processors : positive := 2;
+  -- end not in book
+
+  shared variable bus_ifetch_count,
+    bus_read_count,
+    bus_write_count : natural := 0;
+
+  signal bus_request, bus_grant : bit_vector(0 to num_processors - 1);
+  -- . . .    -- other signal declarations
+
+begin
+
+  processor_array :
+  for processor_id in 0 to num_processors - 1 generate
+
+    processor : process is
+                          -- . . .
+    begin
+      -- . . .    -- initialize
+      loop
+        bus_request(processor_id) <= '1';
+        wait until bus_grant(processor_id) = '1';
+        bus_ifetch_count := bus_ifetch_count + 1;
+        -- . . .    -- fetch instruction
+        bus_request(processor_id) <= '0';
+        -- . . .    -- decode and execute instruction
+        -- not in book
+        wait until bus_grant(processor_id) = '0';
+        -- end not in book
+      end loop;
+    end process processor;
+
+  end generate processor_array;
+
+  arbiter : process is
+  begin
+    -- . . .
+    -- not in book
+    loop
+      for i in bus_request'range loop
+        if bus_request(i) = '1' then
+          bus_grant(i) <= '1' after 5 ns;
+          wait until bus_request(i) = '0';
+          bus_grant(i) <= '0' after 5 ns;
+        end if;
+      end loop;
+      wait for 5 ns;
+    end loop;
+    -- end not in book
+  end process arbiter;
+
+  -- . . .    -- other processes for memory, etc
+
+end architecture instrumented;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp b/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp
new file mode 100644
index 0000000..ddac7ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp
@@ -0,0 +1,826 @@
+
+# Copyright (C) 2001 Clifton Labs, Inc
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+# Authors: Philip A. Wilsey	philip.wilsey@ieee.org
+# 	   Dale E. Martin	dmartin@cliftonlabs.com
+
+# $Author: paw $
+# $Revision: 1.6 $
+
+# ------------------------------------------------------------------------
+#
+# $Id: compliant.exp,v 1.6 2001-11-03 23:19:37 paw Exp $
+#
+# ------------------------------------------------------------------------
+
+setup_test_group "Ashenden:Compliant Cases" "1076-1993"
+
+# create general libraries used in the testsuite
+
+create_lib stimulus
+build_compliant_test util_pk_test.vhd LIBRARY=stimulus
+
+create_lib bv_utilities
+
+build_compliant_test bv_arithmetic.vhd LIBRARY=bv_utilities
+build_compliant_test bv_arithmetic_body.vhd LIBRARY=bv_utilities
+
+build_compliant_test bv_images.vhd LIBRARY=bv_utilities
+build_compliant_test bv_images_body.vhd LIBRARY=bv_utilities
+
+# ------------------------------------------------------------------------
+# models from chapter 1....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_01_fg_01_07.vhd
+build_compliant_test ch_01_fg_01_08.vhd
+build_compliant_test ch_01_fg_01_10.vhd
+build_compliant_test ch_01_fg_01_11.vhd
+
+build_compliant_test ch_01_fg_01_13.vhd
+
+build_compliant_test ch_01_tb_01_01.vhd
+
+build_compliant_test ch_01_tb_01_02.vhd
+
+build_compliant_test ch_01_tb_01_03.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 2....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_02_tb_02_01.vhd
+build_compliant_test ch_02_fg_02_01.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 3....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_03_ch_03_01.vhd
+build_compliant_test ch_03_ch_03_02.vhd
+build_compliant_test ch_03_ch_03_03.vhd
+build_compliant_test ch_03_ch_03_04.vhd
+build_compliant_test ch_03_ch_03_05.vhd
+build_compliant_test ch_03_ch_03_06.vhd
+build_compliant_test ch_03_ch_03_07.vhd
+build_compliant_test ch_03_ch_03_08.vhd
+build_compliant_test ch_03_ch_03_10.vhd
+build_compliant_test ch_03_ch_03_11.vhd
+build_compliant_test ch_03_ch_03_12.vhd
+build_compliant_test ch_03_ch_03_13.vhd
+build_compliant_test ch_03_ch_03_14.vhd
+build_compliant_test ch_03_ch_03_16.vhd
+build_compliant_test ch_03_ch_03_17.vhd
+build_compliant_test ch_03_ch_03_18.vhd
+build_compliant_test ch_03_ch_03_19.vhd
+build_compliant_test ch_03_ch_03_20.vhd
+
+build_compliant_test ch_03_fg_03_01.vhd
+build_compliant_test ch_03_tb_03_01.vhd
+
+build_compliant_test ch_03_tb_03_02.vhd
+build_compliant_test ch_03_fg_03_02.vhd
+build_compliant_test ch_03_tb_03_03.vhd
+
+build_compliant_test ch_03_fg_03_03.vhd
+build_compliant_test ch_03_tb_03_04.vhd
+
+build_compliant_test ch_03_fg_03_04.vhd
+build_compliant_test ch_03_tb_03_05.vhd
+
+build_compliant_test ch_03_fg_03_05.vhd
+build_compliant_test ch_03_tb_03_06.vhd
+
+build_compliant_test ch_03_fg_03_05.vhd
+build_compliant_test ch_03_fg_03_06.vhd
+build_compliant_test ch_03_tb_03_07.vhd
+
+build_compliant_test ch_03_fg_03_07.vhd
+build_compliant_test ch_03_tb_03_08.vhd
+
+build_compliant_test ch_03_fg_03_08.vhd
+build_compliant_test ch_03_tb_03_09.vhd
+
+build_compliant_test ch_03_fg_03_09.vhd
+build_compliant_test ch_03_tb_03_10.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 4....
+# ------------------------------------------------------------------------
+
+create_lib ch4_pkgs
+
+build_compliant_test ch_04_pk_04_01.vhd LIBRARY=ch4_pkgs
+build_compliant_test ch_04_pk_04_02.vhd LIBRARY=ch4_pkgs
+
+build_compliant_test ch_04_ch_04_01.vhd
+build_compliant_test ch_04_ch_04_02.vhd
+build_compliant_test ch_04_ch_04_04.vhd
+build_compliant_test ch_04_ch_04_05.vhd
+build_compliant_test ch_04_ch_04_06.vhd
+build_compliant_test ch_04_ch_04_07.vhd
+build_compliant_test ch_04_ch_04_08.vhd
+build_compliant_test ch_04_ch_04_10.vhd
+
+build_compliant_test ch_04_fg_04_01.vhd
+build_compliant_test ch_04_fg_04_03.vhd
+
+build_compliant_test ch_04_tb_04_04.vhd
+build_compliant_test ch_04_fg_04_06.vhd
+
+build_compliant_test ch_04_tb_04_01.vhd
+
+build_compliant_test ch_04_fg_04_04.vhd
+build_compliant_test ch_04_tb_04_02.vhd
+
+build_compliant_test ch_04_fg_04_05.vhd
+build_compliant_test ch_04_tb_04_03.vhd
+
+delete_lib ch4_pkgs
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 5....
+# ------------------------------------------------------------------------
+
+# consider removing this test....doesn't it duplicate util_pk_test.vhd??
+build_compliant_test ch_05_pk_test.vhd
+
+build_compliant_test ch_05_ch_05_03.vhd
+build_compliant_test ch_05_fg_05_02.vhd
+build_compliant_test ch_05_tb_05_01.vhd
+build_compliant_test ch_05_tb_05_02.vhd
+
+build_compliant_test ch_05_fg_05_05.vhd
+build_compliant_test ch_05_fg_05_25.vhd
+build_compliant_test ch_05_tb_05_03.vhd
+
+build_compliant_test ch_05_fg_05_06.vhd
+build_compliant_test ch_05_tb_05_04.vhd
+
+build_compliant_test ch_05_fg_05_16.vhd
+build_compliant_test ch_05_tb_05_05.vhd
+
+# this file should be placed in a library
+build_compliant_test ch_05_fg_05_22.vhd
+build_compliant_test ch_05_tb_05_06.vhd
+build_compliant_test ch_05_fg_05_22.vhd
+build_compliant_test ch_05_tb_05_07.vhd
+
+build_compliant_test ch_05_fg_05_24.vhd
+build_compliant_test ch_05_tb_05_08.vhd
+
+build_compliant_test ch_05_fg_05_05.vhd
+
+create_lib star_lib
+
+build_compliant_test ch_05_fg_05_05.vhd
+build_compliant_test ch_05_fg_05_25.vhd
+
+build_compliant_test ch_05_tb_05_09.vhd
+build_compliant_test ch_05_tb_05_10.vhd
+build_compliant_test ch_05_fg_05_27.vhd
+build_compliant_test ch_05_tb_05_11.vhd
+
+create_lib widget_cells
+
+build_compliant_test ch_05_tb_05_12.vhd LIBRARY=widget_cells
+
+create_lib wasp_lib
+
+build_compliant_test ch_05_tb_05_13.vhd
+build_compliant_test ch_05_ch_05_01.vhd
+build_compliant_test ch_05_ch_05_02.vhd 
+build_compliant_test ch_05_ch_05_05.vhd
+build_compliant_test ch_05_tb_05_12.vhd LIBRARY=wasp_lib
+
+build_compliant_test ch_05_ch_05_04.vhd
+build_compliant_test ch_05_ch_05_06.vhd
+build_compliant_test ch_05_ch_05_07.vhd
+build_compliant_test ch_05_ch_05_08.vhd
+build_compliant_test ch_05_ch_05_09.vhd
+build_compliant_test ch_05_ch_05_10.vhd
+build_compliant_test ch_05_ch_05_11.vhd
+build_compliant_test ch_05_ch_05_12.vhd
+build_compliant_test ch_05_ch_05_13.vhd
+build_compliant_test ch_05_ch_05_14.vhd
+build_compliant_test ch_05_ch_05_15.vhd
+build_compliant_test ch_05_ch_05_16.vhd
+build_compliant_test ch_05_ch_05_17.vhd
+build_compliant_test ch_05_ch_05_18.vhd
+build_compliant_test ch_05_ch_05_19.vhd
+build_compliant_test ch_05_ch_05_20.vhd
+build_compliant_test ch_05_ch_05_21.vhd
+build_compliant_test ch_05_ch_05_22.vhd
+build_compliant_test ch_05_ch_05_23.vhd
+build_compliant_test ch_05_ch_05_24.vhd
+build_compliant_test ch_05_ch_05_25.vhd
+build_compliant_test ch_05_ch_05_26.vhd
+build_compliant_test ch_05_ch_05_27.vhd
+build_compliant_test ch_05_fg_05_01.vhd
+build_compliant_test ch_05_fg_05_03.vhd
+build_compliant_test ch_05_fg_05_04.vhd
+build_compliant_test ch_05_fg_05_07.vhd
+build_compliant_test ch_05_fg_05_08.vhd
+build_compliant_test ch_05_fg_05_09.vhd
+build_compliant_test ch_05_fg_05_12.vhd
+build_compliant_test ch_05_fg_05_17.vhd
+build_compliant_test ch_05_fg_05_18.vhd
+build_compliant_test ch_05_fg_05_19.vhd
+build_compliant_test ch_05_fg_05_20.vhd
+build_compliant_test ch_05_fg_05_21.vhd
+build_compliant_test ch_05_fg_05_23.vhd
+build_compliant_test ch_05_fg_05_25.vhd
+build_compliant_test ch_05_fg_05_28.vhd
+build_compliant_test ch_05_tb_05_12.vhd
+build_compliant_test ch_05_fg_05_30.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 6....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_06_acca.vhd
+build_compliant_test ch_06_acca-b.vhd
+build_compliant_test ch_06_accr.vhd
+build_compliant_test ch_06_accr-b.vhd
+build_compliant_test ch_06_mac.vhd
+build_compliant_test ch_06_tovec.vhd
+build_compliant_test ch_06_tovec-b.vhd
+build_compliant_test ch_06_tofp.vhd
+build_compliant_test ch_06_tofp-b.vhd
+build_compliant_test ch_06_reg.vhd
+build_compliant_test ch_06_reg-b.vhd
+build_compliant_test ch_06_mac-b.vhd
+build_compliant_test ch_06_mult.vhd
+build_compliant_test ch_06_mult-b.vhd
+build_compliant_test ch_06_pas.vhd
+build_compliant_test ch_06_pas-b.vhd
+build_compliant_test ch_06_srff.vhd
+build_compliant_test ch_06_srff-b.vhd
+build_compliant_test ch_06_ovfl.vhd
+build_compliant_test ch_06_ovfl-b.vhd
+build_compliant_test ch_06_mac-r.vhd
+
+build_compliant_test ch_06_mact.vhd
+build_compliant_test ch_06_mact-bb.vhd
+build_compliant_test ch_06_mact-br.vhd
+build_compliant_test ch_06_mact-bv.vhd
+build_compliant_test ch_06_multt.vhd
+build_compliant_test ch_06_multt-b.vhd
+build_compliant_test ch_06_tofpt.vhd
+build_compliant_test ch_06_tofpt-b.vhd
+build_compliant_test ch_06_tovect.vhd
+build_compliant_test ch_06_tovect-b.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 7....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_07_ch_07_01.vhd
+build_compliant_test ch_07_ch_07_02.vhd
+
+build_compliant_test ch_07_ch_07_03.vhd
+
+build_compliant_test ch_07_ch_07_04.vhd
+build_compliant_test ch_07_ch_07_05.vhd
+build_compliant_test ch_07_ch_07_06.vhd
+build_compliant_test ch_07_fg_07_01.vhd
+build_compliant_test ch_07_fg_07_02.vhd
+build_compliant_test ch_07_fg_07_03.vhd
+build_compliant_test ch_07_fg_07_04.vhd
+build_compliant_test ch_07_fg_07_05.vhd
+build_compliant_test ch_07_fg_07_06.vhd
+build_compliant_test ch_07_fg_07_07.vhd
+build_compliant_test ch_07_fg_07_08.vhd
+build_compliant_test ch_07_fg_07_09.vhd
+build_compliant_test ch_07_fg_07_10.vhd
+build_compliant_test ch_07_fg_07_11.vhd
+build_compliant_test ch_07_fg_07_12.vhd
+build_compliant_test ch_07_fg_07_13.vhd
+build_compliant_test ch_07_fg_07_14.vhd
+build_compliant_test ch_07_fg_07_15.vhd
+build_compliant_test ch_07_fg_07_16.vhd
+build_compliant_test ch_07_fg_07_17.vhd
+build_compliant_test ch_07_fg_07_18.vhd
+build_compliant_test ch_07_fg_07_19.vhd
+
+build_compliant_test ch_07_fg_07_20.vhd
+build_compliant_test ch_07_fg_07_22.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 8....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_08_ch_08_01.vhd
+build_compliant_test ch_08_fg_08_06.vhd
+build_compliant_test ch_08_ch_08_02.vhd
+build_compliant_test ch_08_ch_08_03.vhd
+build_compliant_test ch_08_ch_08_04.vhd
+build_compliant_test ch_08_ch_08_05.vhd
+build_compliant_test ch_08_fg_08_01.vhd
+build_compliant_test ch_08_fg_08_02.vhd
+build_compliant_test ch_08_fg_08_03.vhd
+build_compliant_test ch_08_fg_08_05.vhd
+build_compliant_test ch_08_fg_08_04.vhd
+build_compliant_test ch_08_fg_08_06.vhd
+build_compliant_test ch_08_fg_08_07.vhd
+build_compliant_test ch_08_fg_08_08.vhd LIBRARY=bv_utilities
+build_compliant_test ch_08_fg_08_09.vhd
+build_compliant_test ch_08_fg_08_10.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 9....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_09_ch_09_01.vhd
+build_compliant_test ch_09_ch_09_02.vhd
+build_compliant_test ch_09_ch_09_03.vhd
+build_compliant_test ch_09_ch_09_04.vhd
+build_compliant_test ch_09_fg_09_01.vhd
+build_compliant_test ch_09_fg_09_02.vhd
+build_compliant_test ch_09_fg_09_03.vhd
+build_compliant_test ch_09_fg_09_04.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 10....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_10_alut.vhd
+build_compliant_test ch_10_alu.vhd
+build_compliant_test ch_10_alu-b.vhd
+build_compliant_test ch_10_bvat.vhd
+build_compliant_test ch_10_bvat-b.vhd
+build_compliant_test ch_10_chkdiv.vhd
+build_compliant_test ch_10_chkmult.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 11....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_11_ch_11_01.vhd
+build_compliant_test ch_11_ch_11_02.vhd
+build_compliant_test ch_11_ch_11_03.vhd
+build_compliant_test ch_11_fg_11_01.vhd
+build_compliant_test ch_11_fg_11_02.vhd
+build_compliant_test ch_11_fg_11_03.vhd
+build_compliant_test ch_11_fg_11_04.vhd
+build_compliant_test ch_11_fg_11_05.vhd
+build_compliant_test ch_11_fg_11_06.vhd
+build_compliant_test ch_11_fg_11_07.vhd
+build_compliant_test ch_11_fg_11_08.vhd
+build_compliant_test ch_11_fg_11_09.vhd
+build_compliant_test ch_11_fg_11_10.vhd
+build_compliant_test ch_11_fg_11_12.vhd
+build_compliant_test ch_11_fg_11_13.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 12....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_12_ch_12_01.vhd
+build_compliant_test ch_12_ch_12_02.vhd
+build_compliant_test ch_12_ch_12_03.vhd
+build_compliant_test ch_12_fg_12_01.vhd
+build_compliant_test ch_12_fg_12_02.vhd
+build_compliant_test ch_12_fg_12_03.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 13....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_13_ch_13_01.vhd
+build_compliant_test ch_13_fg_13_01.vhd LIBRARY=star_lib
+build_compliant_test ch_13_fg_13_02.vhd
+build_compliant_test ch_13_fg_13_03.vhd
+build_compliant_test ch_13_fg_13_04.vhd
+build_compliant_test ch_13_fg_13_05.vhd
+build_compliant_test ch_13_fg_13_06.vhd
+build_compliant_test ch_13_fg_13_07.vhd
+build_compliant_test ch_13_fg_13_08.vhd
+build_compliant_test ch_13_fg_13_09.vhd
+build_compliant_test ch_13_fg_13_10.vhd
+build_compliant_test ch_13_fg_13_11.vhd
+build_compliant_test ch_13_fg_13_12.vhd
+build_compliant_test ch_13_fg_13_13.vhd
+build_compliant_test ch_13_fg_13_14.vhd
+build_compliant_test ch_13_fg_13_15.vhd
+build_compliant_test ch_13_fg_13_17.vhd
+
+create_lib chips
+
+build_compliant_test ch_13_fg_13_17.vhd LIBRARY=chips
+build_compliant_test ch_13_fg_13_18.vhd LIBRARY=chips
+build_compliant_test ch_13_fg_13_18.vhd
+
+create_lib gate_lib
+
+build_compliant_test ch_13_fg_13_19.vhd LIBRARY=gate_lib
+build_compliant_test ch_13_fg_13_19.vhd
+build_compliant_test ch_13_fg_13_20.vhd
+build_compliant_test ch_13_fg_13_21.vhd
+build_compliant_test ch_13_fg_13_22.vhd
+
+create_lib cell_lib
+
+build_compliant_test ch_13_fg_13_23.vhd LIBRARY=cell_lib
+build_compliant_test ch_13_fg_13_23.vhd
+build_compliant_test ch_13_fg_13_24.vhd
+
+create_lib project_lib
+
+build_compliant_test ch_05_pk_test.vhd LIBRARY=project_lib
+build_compliant_test ch_13_fg_13_25.vhd LIBRARY=project_lib
+build_compliant_test ch_13_fg_13_25.vhd
+build_compliant_test ch_13_fg_13_26.vhd
+
+build_compliant_test ch_14_ch_14_01.vhd
+build_compliant_test ch_14_fg_14_01.vhd LIBRARY=cell_lib
+build_compliant_test ch_14_fg_14_01.vhd
+build_compliant_test ch_14_fg_14_02.vhd
+build_compliant_test ch_14_fg_14_04.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 14....
+# ------------------------------------------------------------------------
+
+create_lib chip_lib
+
+build_compliant_test ch_14_fg_14_04.vhd LIBRARY=chip_lib
+build_compliant_test ch_14_fg_14_05.vhd
+build_compliant_test ch_14_fg_14_05.vhd LIBRARY=cell_lib
+build_compliant_test ch_14_fg_14_06.vhd
+build_compliant_test ch_14_fg_14_08.vhd
+build_compliant_test ch_14_fg_14_09.vhd
+build_compliant_test ch_14_fg_14_10.vhd
+build_compliant_test ch_14_fg_14_11.vhd
+build_compliant_test ch_14_fg_14_12.vhd
+build_compliant_test ch_14_fg_14_13.vhd LIBRARY=cell_lib
+build_compliant_test ch_14_fg_14_13.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 15....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_15_dlxt.vhd
+build_compliant_test ch_15_alut.vhd
+
+build_compliant_test ch_15_dlxi.vhd
+build_compliant_test ch_15_dlxi-b.vhd
+
+build_compliant_test ch_15_rft.vhd
+
+build_compliant_test ch_15_latch.vhd
+build_compliant_test ch_15_latch-b.vhd
+
+build_compliant_test ch_15_alu.vhd
+build_compliant_test ch_15_alu-b.vhd
+
+build_compliant_test ch_15_cg.vhd
+build_compliant_test ch_15_cg-b.vhd
+
+build_compliant_test ch_15_rf.vhd
+build_compliant_test ch_15_rf-b.vhd
+
+build_compliant_test ch_15_crtl.vhd
+build_compliant_test ch_15_ctrl-b.vhd
+
+build_compliant_test ch_15_regm.vhd
+build_compliant_test ch_15_regm-b.vhd
+
+build_compliant_test ch_15_regmpr.vhd
+build_compliant_test ch_15_regmpr-b.vhd
+
+build_compliant_test ch_15_dlx.vhd
+build_compliant_test ch_15_dlx-b.vhd
+build_compliant_test ch_15_dlx-r.vhd
+
+build_compliant_test ch_15_dlxr.vhd
+build_compliant_test ch_15_mem.vhd
+build_compliant_test ch_15_mem-pl.vhd
+
+build_compliant_test ch_15_ire.vhd
+build_compliant_test ch_15_ire-b.vhd
+
+build_compliant_test ch_15_mem-fl.vhd
+
+build_compliant_test ch_15_mux2.vhd
+build_compliant_test ch_15_mux2-b.vhd
+
+build_compliant_test ch_15_regmp.vhd
+build_compliant_test ch_15_regmp-b.vhd
+
+build_compliant_test ch_15_dlxtst.vhd
+build_compliant_test ch_15_dlxtst-b.vhd
+build_compliant_test ch_15_dlxtst-v.vhd
+
+build_compliant_test ch_15_dlxtstb.vhd
+
+build_compliant_test ch_15_dlxtstr.vhd
+build_compliant_test ch_15_dlxstsv.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 16....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_16_ch_16_01.vhd
+build_compliant_test ch_16_ch_16_02.vhd
+build_compliant_test ch_16_ch_16_03.vhd
+build_compliant_test ch_16_ch_16_04.vhd
+build_compliant_test ch_16_ch_16_05.vhd
+build_compliant_test ch_16_ch_16_06.vhd
+build_compliant_test ch_16_fg_16_01.vhd
+build_compliant_test ch_16_fg_16_02.vhd
+build_compliant_test ch_16_fg_16_04.vhd
+build_compliant_test ch_16_fg_16_05.vhd
+build_compliant_test ch_16_fg_16_06.vhd
+build_compliant_test ch_16_fg_16_07.vhd
+build_compliant_test ch_16_fg_16_08.vhd
+build_compliant_test ch_16_fg_16_09.vhd
+build_compliant_test ch_16_fg_16_10.vhd
+build_compliant_test ch_16_fg_16_12.vhd
+build_compliant_test ch_16_fg_16_13.vhd
+build_compliant_test ch_16_fg_16_14.vhd
+build_compliant_test ch_16_fg_16_15.vhd
+build_compliant_test ch_16_fg_16_16.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 17....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_17_ch_17_01.vhd
+build_compliant_test ch_17_ch_17_02.vhd
+build_compliant_test ch_17_ch_17_03.vhd
+build_compliant_test ch_17_ch_17_04.vhd
+build_compliant_test ch_17_ch_17_05.vhd
+build_compliant_test ch_17_ch_17_06.vhd
+build_compliant_test ch_17_ch_17_07.vhd
+build_compliant_test ch_17_ch_17_08.vhd
+build_compliant_test ch_17_ch_17_09.vhd
+build_compliant_test ch_17_fg_17_05.vhd
+build_compliant_test ch_17_fg_17_07.vhd
+build_compliant_test ch_17_fg_17_08.vhd
+build_compliant_test ch_17_fg_17_09.vhd
+build_compliant_test ch_17_fg_17_11.vhd
+build_compliant_test ch_17_fg_17_13.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 18....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_18_ch_18_01.vhd
+build_compliant_test ch_18_ch_18_02.vhd
+build_compliant_test ch_18_ch_18_03.vhd
+build_compliant_test ch_18_ch_18_04.vhd
+build_compliant_test ch_18_ch_18_05.vhd
+build_compliant_test ch_18_ch_18_06.vhd
+build_compliant_test ch_18_ch_18_07.vhd
+build_compliant_test ch_18_ch_18_08.vhd
+build_compliant_test ch_18_ch_18_09.vhd
+build_compliant_test ch_18_ch_18_10.vhd
+build_compliant_test ch_18_fg_18_01.vhd
+build_compliant_test ch_18_fg_18_02.vhd
+build_compliant_test ch_18_fg_18_03.vhd
+build_compliant_test ch_18_fg_18_04.vhd
+build_compliant_test ch_18_fg_18_05.vhd
+build_compliant_test ch_18_fg_18_06.vhd
+build_compliant_test ch_18_fg_18_07.vhd
+build_compliant_test ch_18_fg_18_08.vhd
+build_compliant_test ch_18_fg_18_09.vhd
+build_compliant_test ch_18_fg_18_10.vhd
+build_compliant_test ch_18_fg_18_11.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 19....
+# ------------------------------------------------------------------------
+
+create_lib math
+
+build_compliant_test math_real.vhd LIBRARY=math
+
+create_lib qsim
+
+build_compliant_test ch_19_qsimt.vhd LIBRARY=qsim
+build_compliant_test ch_19_qsimt-b.vhd LIBRARY=qsim
+
+build_compliant_test ch_19_qt.vhd LIBRARY=qsim
+
+build_compliant_test ch_19_wtfifo.vhd LIBRARY=qsim
+build_compliant_test ch_19_wtfifo-b.vhd LIBRARY=qsim
+
+build_compliant_test ch_19_tkfifo.vhd LIBRARY=qsim
+build_compliant_test ch_19_tkfifo-b.vhd LIBRARY=qsim
+
+create_lib random
+
+build_compliant_test ch_19_random.vhd LIBRARY=random
+build_compliant_test ch_19_random-b.vhd LIBRARY=random
+
+build_compliant_test ch_19_source.vhd
+build_compliant_test ch_19_source-b.vhd
+
+build_compliant_test ch_19_sink.vhd
+build_compliant_test ch_19_sink-b.vhd
+
+build_compliant_test ch_19_queue.vhd
+build_compliant_test ch_19_queue-b.vhd
+
+build_compliant_test ch_19_srvr.vhd
+build_compliant_test ch_19_srvr-b.vhd
+
+build_compliant_test ch_19_fork.vhd
+build_compliant_test ch_19_fork-b.vhd
+
+build_compliant_test ch_19_join.vhd
+build_compliant_test ch_19_join-b.vhd
+
+build_compliant_test ch_19_ds.vhd
+build_compliant_test ch_19_ds-qn.vhd
+
+build_compliant_test ch_19_tb.vhd
+build_compliant_test ch_19_tb-src.vhd
+
+# we may have to re-add ch_19_tb.vhd to work each time.....
+
+build_compliant_test ch_19_tb-snk.vhd
+build_compliant_test ch_19_tb-frk.vhd
+build_compliant_test ch_19_tb-jn.vhd
+build_compliant_test ch_19_tb-qs.vhd
+build_compliant_test ch_19_tb-jnsth.vhd
+
+delete_lib math
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 20....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_20_ch_20_01.vhd
+build_compliant_test ch_20_ch_20_02.vhd
+build_compliant_test ch_20_ch_20_03.vhd
+build_compliant_test ch_20_ch_20_04.vhd
+build_compliant_test ch_20_ch_20_05.vhd
+build_compliant_test ch_20_ch_20_06.vhd
+build_compliant_test ch_20_ch_20_08.vhd
+build_compliant_test ch_20_ch_20_09.vhd
+build_compliant_test ch_20_ch_20_07.vhd
+build_compliant_test ch_20_ch_20_10.vhd
+build_compliant_test ch_20_ch_20_11.vhd
+build_compliant_test ch_20_fg_20_05.vhd
+build_compliant_test ch_20_fg_20_06.vhd
+build_compliant_test ch_20_fg_20_09.vhd
+build_compliant_test ch_20_fg_20_07.vhd
+build_compliant_test ch_20_fg_20_11.vhd
+build_compliant_test ch_20_fg_20_12.vhd
+build_compliant_test ch_20_fg_20_13.vhd
+build_compliant_test ch_20_fg_20_14.vhd
+build_compliant_test ch_20_fg_20_15.vhd
+build_compliant_test ch_20_fg_20_16.vhd
+build_compliant_test ch_20_fg_20_17.vhd
+build_compliant_test ch_20_fg_20_18.vhd
+build_compliant_test ch_20_fg_20_19.vhd
+build_compliant_test ch_20_fg_20_20.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 21....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_21_ch_21_01.vhd
+build_compliant_test ch_21_ch_21_02.vhd
+build_compliant_test ch_21_ch_21_03.vhd
+build_compliant_test ch_21_fg_21_01.vhd
+build_compliant_test ch_21_fg_21_02.vhd
+build_compliant_test ch_21_fg_21_03.vhd
+build_compliant_test ch_21_fg_21_04.vhd
+build_compliant_test ch_21_fg_21_05.vhd
+build_compliant_test ch_21_fg_21_06.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from appendix a....
+# ------------------------------------------------------------------------
+
+build_compliant_test ap_a_ap_a_01.vhd
+build_compliant_test ap_a_ap_a_02.vhd
+build_compliant_test ap_a_ap_a_03.vhd
+build_compliant_test ap_a_ap_a_04.vhd
+build_compliant_test ap_a_ap_a_05.vhd
+build_compliant_test ap_a_ap_a_06.vhd
+build_compliant_test ap_a_ap_a_07.vhd
+build_compliant_test ap_a_ap_a_08.vhd
+build_compliant_test ap_a_ap_a_09.vhd
+build_compliant_test ap_a_ap_a_10.vhd
+build_compliant_test ap_a_fg_a_01.vhd
+build_compliant_test ap_a_fg_a_02.vhd
+build_compliant_test ap_a_fg_a_03.vhd
+build_compliant_test ap_a_fg_a_04.vhd
+build_compliant_test ap_a_fg_a_05.vhd
+build_compliant_test ap_a_fg_a_06.vhd
+build_compliant_test ap_a_fg_a_07.vhd
+build_compliant_test ap_a_fg_a_08.vhd
+build_compliant_test ap_a_fg_a_09.vhd
+build_compliant_test ap_a_fg_a_10.vhd
+build_compliant_test ap_a_fg_a_11.vhd
+
+delete_lib work
+
+delete_lib star_lib
+delete_lib widget_cells
+delete_lib wasp_lib
+delete_lib chips
+delete_lib gate_lib
+delete_lib cell_lib
+delete_lib project_lib
+delete_lib chip_lib
+delete_lib qsim
+
+delete_lib bv_utilities
+delete_lib stimulus
+
+end_test_group
+
+# $Log: compliant.exp,v $
+# Revision 1.6  2001-11-03 23:19:37  paw
+# Updating the test script so that each chapter builds into the work library
+# and work is not deleted until processing all the files for that chapter.
+# This means that none of the tests are setup for simulation (the most they
+# can test is the build), but they are now setup to satisfy the library
+# dependencies.  With these changes the analyzer passes just over 80% of the
+# tests correctly.  I will have to run through these tests chapter by chapter
+# to ensure everything is setup properly.  The original vests distributed
+# from UC was/is very inadequate.  This will take quite some time to fix.  In
+# the mean time, the files are at least useful for testing everything up to
+# TESTLEVEL=build.
+#
+# Revision 1.5  2001/10/25 01:24:24  paw
+# More changes/corrections to library creation/reference.  The parser now
+# reports over 80% on ashenden.  Many changes remain to correct errors in
+# this set of tests.
+#
+# Revision 1.3  2001/10/24 23:31:00  paw
+# More revisions/reorganization to have test harness satisfy dependencies
+# between tests.
+#
+# Revision 1.2  2001/10/24 22:18:13  paw
+# Setup a stricter library structure for the chapter 19 tests.  This is a
+# safety commit.
+#
+# Revision 1.1  2001/10/19 23:28:54  paw
+# Adding dejagnu scripts to run ashenden's test cases.
+#
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd
new file mode 100644
index 0000000..8df2479
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd
@@ -0,0 +1,212 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: math_real.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------- 
+--
+-- This source file may be used and distributed without restriction.
+-- No declarations or definitions shall be included in this package. 
+--
+--   ****************************************************************
+--   *                                                              *
+--   *                      W A R N I N G		 	    *
+--   *								    *
+--   *   This DRAFT version IS NOT endorsed or approved by IEEE     *
+--   *								    *
+--   ****************************************************************
+--
+-- Title:    PACKAGE MATH_REAL
+--
+-- Library:  This package shall be compiled into a library 
+--           symbolically named IEEE.
+--
+-- Purpose:  VHDL declarations for mathematical package MATH_REAL
+--	     which contains common real constants, common real
+--	     functions, and real trascendental functions.
+--
+-- Author:   Based on work by IEEE VHDL Math Package Study Group 
+--
+-- Notes:
+-- 	The package body shall be considered the formal definition of 
+-- 	the semantics of this package. Tool developers may choose to implement 
+-- 	the package body in the most efficient manner available to them.
+--
+-- History:
+--	Version 0.4		JAT	4/15/93
+-------------------------------------------------------------
+Library IEEE;
+
+Package MATH_REAL is
+--synopsys synthesis_off
+
+  constant  MATH_E :         real := 2.71828_18284_59045_23536;  
+                                        -- value of e
+  constant  MATH_1_E:        real := 0.36787_94411_71442_32160;
+                                        -- value of 1/e
+  constant  MATH_PI :        real := 3.14159_26535_89793_23846;  
+                                        -- value of pi
+  constant  MATH_1_PI :      real := 0.31830_98861_83790_67154;  
+                                        -- value of 1/pi
+  constant  MATH_LOG_OF_2:   real := 0.69314_71805_59945_30942;
+                                        -- natural log of 2
+  constant  MATH_LOG_OF_10:  real := 2.30258_50929_94045_68402;
+                                        -- natural log of10
+  constant  MATH_LOG2_OF_E:  real := 1.44269_50408_88963_4074;
+                                        -- log base 2 of e
+  constant  MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
+                                        -- log base 10 of e
+  constant  MATH_SQRT2:      real := 1.41421_35623_73095_04880; 
+                                        -- sqrt of 2
+  constant  MATH_SQRT1_2:    real := 0.70710_67811_86547_52440; 
+                                        -- sqrt of 1/2
+  constant  MATH_SQRT_PI:    real := 1.77245_38509_05516_02730; 
+                                        -- sqrt of pi
+  constant  MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
+  -- conversion factor from degree to radian
+  constant  MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
+  -- conversion factor from radian to degree
+
+  --
+  -- attribute for functions whose implementation is foreign (C native)
+  --
+  -- attribute FOREIGN: string;  -- predefined attribute in VHDL-1992
+  --
+
+  function SIGN (X: real ) return real;
+  -- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
+
+  function CEIL (X : real ) return real;
+  -- returns smallest integer value (as real) not less than X
+
+  function FLOOR (X : real ) return real;
+  -- returns largest integer value (as real) not greater than X
+
+  function ROUND (X : real ) return real;
+  -- returns FLOOR(X + 0.5) if X > 0.0;
+  -- return CEIL(X - 0.5) if X < 0.0
+  
+  function FMAX (X, Y : real ) return real;
+  -- returns the algebraically larger of X and Y
+
+  function FMIN (X, Y : real ) return real;
+  -- returns the algebraically smaller of X and Y
+
+  function SRAND (seed: in integer ) return integer;
+  -- attribute FOREIGN of SRAND: function is "C_NATIVE"; 
+  -- for VHDL-1992 standard
+  --
+  -- sets value of seed for sequence of pseudo-random numbers.
+  -- returns the value of the seed.
+  -- It uses the native C function srand().
+
+  function RAND return integer;		
+  -- attribute FOREIGN of RAND: function is "C_NATIVE"; 
+  -- for VHDL-1992 standard
+  --
+  -- returns an integer pseudo-random number with uniform distribution.
+  -- It uses the native C function rand(). 
+  -- Seed for the sequence is initialized with the
+  -- SRAND() function and value of the seed is changed every
+  -- time SRAND() is called,  but it is not visible.
+  -- The range of generated values is platform dependent.
+
+  function GET_RAND_MAX return integer;		
+  -- attribute FOREIGN of GET_RAND_MAX: function is "C_NATIVE"; 
+  -- for VHDL-1992 standard
+  --
+  -- returns the upper bound of the range of the
+  -- pseudo-random numbers generated by  RAND().
+  -- The support for this function is platform dependent.
+  -- It may not be available in some platforms.
+  -- Note: the value of (RAND() / GET_RAND_MAX()) is a
+  --       pseudo-random number distributed between 0 & 1.
+
+  function SQRT (X : real ) return real;
+  -- returns square root of X;  X >= 0.0
+
+  function CBRT (X : real ) return real;
+  -- returns cube root of X
+
+  function "**" (X : integer; Y : real) return real;
+  -- returns Y power of X ==>  X**Y;
+  -- error if X = 0 and Y <= 0.0
+  -- error if X < 0 and Y does not have an integral value
+
+  function "**" (X : real; Y : real) return real;
+  -- returns Y power of X ==>  X**Y;
+  -- error if X = 0.0 and Y <= 0.0
+  -- error if X < 0.0 and Y does not have an integral value
+
+  function EXP  (X : real ) return real;
+  -- returns e**X; where e = MATH_E
+
+  function LOG (X : real ) return real;
+  -- returns natural logarithm of X; X > 0
+
+  function LOG (BASE: positive; X : real) return real;
+  -- returns logarithm base BASE of X; X > 0
+
+  function  SIN (X : real ) return real;
+  -- returns sin X; X in radians
+
+  function  COS ( X : real ) return real;
+  -- returns cos X; X in radians
+
+  function  TAN (X : real ) return real;
+  -- returns tan X; X in radians
+  -- X /= ((2k+1) * PI/2), where k is an integer
+
+  function  ASIN (X : real ) return real; 
+  -- returns  -PI/2 < asin X < PI/2; | X | <= 1.0
+
+  function  ACOS (X : real ) return real;
+  -- returns  0 < acos X < PI; | X | <= 1.0
+
+  function  ATAN (X : real) return real;
+  -- returns  -PI/2 < atan X < PI/2
+
+  function  ATAN2 (X : real; Y : real) return real;
+  -- returns  atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
+
+  function SINH (X : real) return real;
+  -- hyperbolic sine; returns (e**X - e**(-X))/2
+
+  function  COSH (X : real) return real;
+  -- hyperbolic cosine; returns (e**X + e**(-X))/2
+
+  function  TANH (X : real) return real;
+  -- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
+  
+  function ASINH (X : real) return real;
+  -- returns ln( X + sqrt( X**2 + 1))
+
+  function ACOSH (X : real) return real;
+  -- returns ln( X + sqrt( X**2 - 1));   X >= 1.0
+
+  function ATANH (X : real) return real;
+  -- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1.0
+
+--synopsys synthesis_on
+end  MATH_REAL;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/util_pk_test.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/util_pk_test.vhd
new file mode 100644
index 0000000..5998e6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/util_pk_test.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: util_pk_test.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+package stimulus_generators is
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length );
+
+  procedure all_possible_values ( signal bv : out std_ulogic_vector;
+				  delay_between_values : in delay_length );
+
+  procedure all_possible_values ( signal bv : out std_logic_vector;
+				  delay_between_values : in delay_length );
+
+end package stimulus_generators;
+
+package body stimulus_generators is
+
+  type digit_table is array ( natural range 0 to 1 ) of bit;
+  constant digit : digit_table := ( '0', '1' );
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : natural := nat;
+    variable result : bit_vector(0 to length - 1);
+
+  begin
+    for index in result'reverse_range loop
+      result(index) := digit( temp rem 2 );
+      temp := temp / 2;
+    end loop;
+    return result;
+  end function natural_to_bv;
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= natural_to_bv(0, bv'length);
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= natural_to_bv(value, bv'length);
+    end loop;
+  end procedure all_possible_values;
+
+  procedure all_possible_values ( signal bv : out std_ulogic_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
+    end loop;
+  end procedure all_possible_values;
+
+  procedure all_possible_values ( signal bv : out std_logic_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
+    end loop;
+  end procedure all_possible_values;
+
+end package body stimulus_generators;