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| author | Sumanto Kar | 2024-11-21 23:46:28 +0530 |
|---|---|---|
| committer | GitHub | 2024-11-21 23:46:28 +0530 |
| commit | 1992c0efc2805f0683360514b23cdc5517361e00 (patch) | |
| tree | 23a8b023d2f06b910ade250b20828710db0d2582 /library/SubcircuitLibrary | |
| parent | c7f8a75e51d3c79aaa994b25849bcb358543f12c (diff) | |
| parent | 25f132133deed0e2f134ceeb001fb816c747249c (diff) | |
| download | eSim-1992c0efc2805f0683360514b23cdc5517361e00.tar.gz eSim-1992c0efc2805f0683360514b23cdc5517361e00.tar.bz2 eSim-1992c0efc2805f0683360514b23cdc5517361e00.zip | |
Subcircuit Files of ICs(Contributor: Shweta Khune)
Diffstat (limited to 'library/SubcircuitLibrary')
189 files changed, 28968 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib new file mode 100644 index 00000000..57dd9d9b --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib @@ -0,0 +1,138 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir new file mode 100644 index 00000000..00f7b56f --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir @@ -0,0 +1,35 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\CD4078B_IC\CD4078B_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/18/24 16:43:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad9_ Net-_U11-Pad1_ d_inverter +U4 Net-_U2-Pad10_ Net-_U11-Pad2_ d_inverter +U5 Net-_U2-Pad11_ Net-_U12-Pad1_ d_inverter +U6 Net-_U2-Pad12_ Net-_U12-Pad2_ d_inverter +U7 Net-_U2-Pad13_ Net-_U13-Pad1_ d_inverter +U8 Net-_U2-Pad14_ Net-_U13-Pad2_ d_inverter +U9 Net-_U2-Pad15_ Net-_U14-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U21 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U21-Pad3_ d_nor +U22 Net-_U21-Pad3_ Net-_U22-Pad2_ d_inverter +U24 Net-_U22-Pad2_ Net-_U24-Pad2_ d_inverter +U23 Net-_U21-Pad3_ Net-_U23-Pad2_ d_inverter +U25 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad9_ dac_bridge_2 +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U10-Pad1_ adc_bridge_8 +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand +U15 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U15-Pad3_ d_nand +U16 Net-_U12-Pad3_ Net-_U12-Pad3_ Net-_U16-Pad3_ d_nand +U19 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U19-Pad3_ d_nand +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand +U14 Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_nand +U17 Net-_U13-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nand +U18 Net-_U14-Pad3_ Net-_U14-Pad3_ Net-_U18-Pad3_ d_nand +U20 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U20-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out new file mode 100644 index 00000000..30c56474 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out @@ -0,0 +1,108 @@ +* d:\fossee\esim\library\subcircuitlibrary\cd4078b_ic\cd4078b_ic.cir + +* u3 net-_u2-pad9_ net-_u11-pad1_ d_inverter +* u4 net-_u2-pad10_ net-_u11-pad2_ d_inverter +* u5 net-_u2-pad11_ net-_u12-pad1_ d_inverter +* u6 net-_u2-pad12_ net-_u12-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u13-pad1_ d_inverter +* u8 net-_u2-pad14_ net-_u13-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u21 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u21-pad3_ net-_u22-pad2_ d_inverter +* u24 net-_u22-pad2_ net-_u24-pad2_ d_inverter +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad10_ net-_u1-pad9_ dac_bridge_2 +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad3_ net-_u19-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u14-pad3_ net-_u18-pad3_ d_nand +* u20 net-_u17-pad3_ net-_u18-pad3_ net-_u20-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port +a1 net-_u2-pad9_ net-_u11-pad1_ u3 +a2 net-_u2-pad10_ net-_u11-pad2_ u4 +a3 net-_u2-pad11_ net-_u12-pad1_ u5 +a4 net-_u2-pad12_ net-_u12-pad2_ u6 +a5 net-_u2-pad13_ net-_u13-pad1_ u7 +a6 net-_u2-pad14_ net-_u13-pad2_ u8 +a7 net-_u2-pad15_ net-_u14-pad1_ u9 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u21-pad3_ u21 +a10 net-_u21-pad3_ net-_u22-pad2_ u22 +a11 net-_u22-pad2_ net-_u24-pad2_ u24 +a12 net-_u21-pad3_ net-_u23-pad2_ u23 +a13 [net-_u24-pad2_ net-_u23-pad2_ ] [net-_u1-pad10_ net-_u1-pad9_ ] u25 +a14 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a18 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16 +a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u19-pad3_ u19 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a22 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a23 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u18-pad3_ u18 +a24 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0.01e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch new file mode 100644 index 00000000..9436e506 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch @@ -0,0 +1,700 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4078B_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 23622 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 66716575 +P 7850 6350 +F 0 "U3" H 7850 6250 60 0000 C CNN +F 1 "d_inverter" H 7850 6500 60 0000 C CNN +F 2 "" H 7900 6300 60 0000 C CNN +F 3 "" H 7900 6300 60 0000 C CNN + 1 7850 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 66716576 +P 7850 6850 +F 0 "U4" H 7850 6750 60 0000 C CNN +F 1 "d_inverter" H 7850 7000 60 0000 C CNN +F 2 "" H 7900 6800 60 0000 C CNN +F 3 "" H 7900 6800 60 0000 C CNN + 1 7850 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 66716577 +P 7850 7350 +F 0 "U5" H 7850 7250 60 0000 C CNN +F 1 "d_inverter" H 7850 7500 60 0000 C CNN +F 2 "" H 7900 7300 60 0000 C CNN +F 3 "" H 7900 7300 60 0000 C CNN + 1 7850 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 66716578 +P 7850 7950 +F 0 "U6" H 7850 7850 60 0000 C CNN +F 1 "d_inverter" H 7850 8100 60 0000 C CNN +F 2 "" H 7900 7900 60 0000 C CNN +F 3 "" H 7900 7900 60 0000 C CNN + 1 7850 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 66716579 +P 7850 8750 +F 0 "U7" H 7850 8650 60 0000 C CNN +F 1 "d_inverter" H 7850 8900 60 0000 C CNN +F 2 "" H 7900 8700 60 0000 C CNN +F 3 "" H 7900 8700 60 0000 C CNN + 1 7850 8750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6671657A +P 7850 9250 +F 0 "U8" H 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CNN +F 2 "" H 11550 7000 60 0000 C CNN +F 3 "" H 11550 7000 60 0000 C CNN + 1 11550 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 667165A0 +P 11550 7500 +F 0 "U16" H 11550 7500 60 0000 C CNN +F 1 "d_nand" H 11600 7600 60 0000 C CNN +F 2 "" H 11550 7500 60 0000 C CNN +F 3 "" H 11550 7500 60 0000 C CNN + 1 11550 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U19 +U 1 1 667165A1 +P 12750 7200 +F 0 "U19" H 12750 7200 60 0000 C CNN +F 1 "d_nand" H 12800 7300 60 0000 C CNN +F 2 "" H 12750 7200 60 0000 C CNN +F 3 "" H 12750 7200 60 0000 C CNN + 1 12750 7200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11100 6900 11000 6900 +Wire Wire Line + 11000 6900 11000 7000 +Wire Wire Line + 11000 7000 11100 7000 +Wire Wire Line + 11100 7400 11000 7400 +Wire Wire Line + 11000 7400 11000 7500 +Wire Wire Line + 11000 7500 11100 7500 +Wire Wire Line + 10700 6950 11000 6950 +Connection ~ 11000 6950 +Wire Wire Line + 10700 7450 11000 7450 +Connection ~ 11000 7450 +Wire Wire Line + 12000 6950 12150 6950 +Wire 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667165A4 +P 11550 9300 +F 0 "U17" H 11550 9300 60 0000 C CNN +F 1 "d_nand" H 11600 9400 60 0000 C CNN +F 2 "" H 11550 9300 60 0000 C CNN +F 3 "" H 11550 9300 60 0000 C CNN + 1 11550 9300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 667165A5 +P 11550 9800 +F 0 "U18" H 11550 9800 60 0000 C CNN +F 1 "d_nand" H 11600 9900 60 0000 C CNN +F 2 "" H 11550 9800 60 0000 C CNN +F 3 "" H 11550 9800 60 0000 C CNN + 1 11550 9800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11100 9200 11000 9200 +Wire Wire Line + 11000 9200 11000 9300 +Wire Wire Line + 11000 9300 11100 9300 +Wire Wire Line + 11100 9700 11000 9700 +Wire Wire Line + 11000 9700 11000 9800 +Wire Wire Line + 11000 9800 11100 9800 +Wire Wire Line + 10700 9250 11000 9250 +Connection ~ 11000 9250 +Wire Wire Line + 10700 9750 11000 9750 +Connection ~ 11000 9750 +Wire Wire Line + 9800 9200 9150 9200 +Wire Wire Line + 9150 9200 9150 9250 +Wire Wire Line + 9300 9350 9300 9300 +Wire Wire Line + 9300 9300 9800 9300 +Wire Wire Line + 9350 9450 9350 9700 +Wire Wire Line + 9350 9700 9800 9700 +Wire Wire Line + 9300 9550 9300 9800 +Wire Wire Line + 9300 9800 9800 9800 +$Comp +L d_nand U20 +U 1 1 667165A6 +P 12950 9500 +F 0 "U20" H 12950 9500 60 0000 C CNN +F 1 "d_nand" H 13000 9600 60 0000 C CNN +F 2 "" H 12950 9500 60 0000 C CNN +F 3 "" H 12950 9500 60 0000 C CNN + 1 12950 9500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12000 9250 12350 9250 +Wire Wire Line + 12350 9250 12350 9400 +Wire Wire Line + 12350 9400 12500 9400 +Wire Wire Line + 12000 9750 12350 9750 +Wire Wire Line + 12350 9750 12350 9500 +Wire Wire Line + 12350 9500 12500 9500 +Wire Wire Line + 13700 8200 13700 9450 +Wire Wire Line + 13700 9450 13400 9450 +Wire Wire Line + 13900 8100 13700 8100 +Wire Wire Line + 13700 8100 13700 7150 +Wire Wire Line + 13700 7150 13200 7150 +$Comp +L PORT U1 +U 1 1 6671678E +P 4050 7700 +F 0 "U1" H 4100 7800 30 0000 C CNN +F 1 "PORT" H 4050 7700 30 0000 C CNN +F 2 "" H 4050 7700 60 0000 C CNN +F 3 "" H 4050 7700 60 0000 C CNN + 1 4050 7700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 66716827 +P 4050 7900 +F 0 "U1" H 4100 8000 30 0000 C CNN +F 1 "PORT" H 4050 7900 30 0000 C CNN +F 2 "" H 4050 7900 60 0000 C CNN +F 3 "" H 4050 7900 60 0000 C CNN + 2 4050 7900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 667168B8 +P 4050 8100 +F 0 "U1" H 4100 8200 30 0000 C CNN +F 1 "PORT" H 4050 8100 30 0000 C CNN +F 2 "" H 4050 8100 60 0000 C CNN +F 3 "" H 4050 8100 60 0000 C CNN + 3 4050 8100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6671693B +P 4050 8300 +F 0 "U1" H 4100 8400 30 0000 C CNN +F 1 "PORT" H 4050 8300 30 0000 C CNN +F 2 "" H 4050 8300 60 0000 C CNN +F 3 "" H 4050 8300 60 0000 C CNN + 4 4050 8300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 667169A8 +P 4050 8500 +F 0 "U1" H 4100 8600 30 0000 C CNN +F 1 "PORT" H 4050 8500 30 0000 C CNN +F 2 "" H 4050 8500 60 0000 C CNN +F 3 "" H 4050 8500 60 0000 C CNN + 5 4050 8500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 66716A2D +P 4050 8700 +F 0 "U1" H 4100 8800 30 0000 C CNN +F 1 "PORT" H 4050 8700 30 0000 C CNN +F 2 "" H 4050 8700 60 0000 C CNN +F 3 "" H 4050 8700 60 0000 C CNN + 6 4050 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 66716AB0 +P 4050 8900 +F 0 "U1" H 4100 9000 30 0000 C CNN +F 1 "PORT" H 4050 8900 30 0000 C CNN +F 2 "" H 4050 8900 60 0000 C CNN +F 3 "" H 4050 8900 60 0000 C CNN + 7 4050 8900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 66716B2F +P 4050 9100 +F 0 "U1" H 4100 9200 30 0000 C CNN +F 1 "PORT" H 4050 9100 30 0000 C CNN +F 2 "" H 4050 9100 60 0000 C CNN +F 3 "" H 4050 9100 60 0000 C CNN + 8 4050 9100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 7700 4800 7700 +Wire Wire Line + 4800 7700 4800 8000 +Wire Wire Line + 4800 8000 4900 8000 +Wire Wire Line + 4300 7900 4750 7900 +Wire Wire Line + 4750 7900 4750 8100 +Wire Wire Line + 4750 8100 4900 8100 +Wire Wire Line + 4300 8100 4650 8100 +Wire Wire Line + 4650 8100 4650 8200 +Wire Wire Line + 4650 8200 4900 8200 +Wire Wire Line + 4300 8300 4900 8300 +Wire Wire Line + 4300 8500 4750 8500 +Wire Wire Line + 4750 8500 4750 8400 +Wire Wire Line + 4750 8400 4900 8400 +Wire Wire Line + 4300 8700 4800 8700 +Wire Wire Line + 4800 8700 4800 8500 +Wire Wire Line + 4800 8500 4900 8500 +Wire Wire Line + 4300 8900 4850 8900 +Wire Wire Line + 4850 8900 4850 8600 +Wire Wire Line + 4850 8600 4900 8600 +Wire Wire Line + 4300 9100 4900 9100 +Wire Wire Line + 4900 9100 4900 8700 +$Comp +L PORT U1 +U 9 1 667175F2 +P 18450 8450 +F 0 "U1" H 18500 8550 30 0000 C CNN +F 1 "PORT" H 18450 8450 30 0000 C CNN +F 2 "" H 18450 8450 60 0000 C CNN +F 3 "" H 18450 8450 60 0000 C CNN + 9 18450 8450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6671766D +P 18450 8300 +F 0 "U1" H 18500 8400 30 0000 C CNN +F 1 "PORT" H 18450 8300 30 0000 C CNN +F 2 "" H 18450 8300 60 0000 C CNN +F 3 "" H 18450 8300 60 0000 C CNN + 10 18450 8300 + -1 0 0 1 +$EndComp +Wire Wire Line + 18200 8300 17900 8300 +Wire Wire Line + 18200 8450 17900 8450 +Wire Wire Line + 17900 8450 17900 8400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub new file mode 100644 index 00000000..7800040c --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub @@ -0,0 +1,102 @@ +* Subcircuit CD4078B_IC +.subckt CD4078B_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ +* d:\fossee\esim\library\subcircuitlibrary\cd4078b_ic\cd4078b_ic.cir +* u3 net-_u2-pad9_ net-_u11-pad1_ d_inverter +* u4 net-_u2-pad10_ net-_u11-pad2_ d_inverter +* u5 net-_u2-pad11_ net-_u12-pad1_ d_inverter +* u6 net-_u2-pad12_ net-_u12-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u13-pad1_ d_inverter +* u8 net-_u2-pad14_ net-_u13-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u21 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u21-pad3_ net-_u22-pad2_ d_inverter +* u24 net-_u22-pad2_ net-_u24-pad2_ d_inverter +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad10_ net-_u1-pad9_ dac_bridge_2 +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad3_ net-_u19-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u14-pad3_ net-_u18-pad3_ d_nand +* u20 net-_u17-pad3_ net-_u18-pad3_ net-_u20-pad3_ d_nand +a1 net-_u2-pad9_ net-_u11-pad1_ u3 +a2 net-_u2-pad10_ net-_u11-pad2_ u4 +a3 net-_u2-pad11_ net-_u12-pad1_ u5 +a4 net-_u2-pad12_ net-_u12-pad2_ u6 +a5 net-_u2-pad13_ net-_u13-pad1_ u7 +a6 net-_u2-pad14_ net-_u13-pad2_ u8 +a7 net-_u2-pad15_ net-_u14-pad1_ u9 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u21-pad3_ u21 +a10 net-_u21-pad3_ net-_u22-pad2_ u22 +a11 net-_u22-pad2_ net-_u24-pad2_ u24 +a12 net-_u21-pad3_ net-_u23-pad2_ u23 +a13 [net-_u24-pad2_ net-_u23-pad2_ ] [net-_u1-pad10_ net-_u1-pad9_ ] u25 +a14 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a18 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16 +a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u19-pad3_ u19 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a22 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a23 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u18-pad3_ u18 +a24 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4078B_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml new file mode 100644 index 00000000..821bf547 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u10><u21 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u22><u24 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u24><u23 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u23><u25 name="type">dac_bridge<field37 name="Enter value for out_low (default=0.0)" /><field38 name="Enter value for out_high (default=5.0)" /><field39 name="Enter value for out_undef (default=0.5)" /><field40 name="Enter value for input load (default=1.0e-12)" /><field41 name="Enter the Rise Time (default=1.0e-9)" /><field42 name="Enter the Fall Time (default=1.0e-9)" /></u25><u2 name="type">adc_bridge<field43 name="Enter value for in_low (default=1.0)" /><field44 name="Enter value for in_high (default=2.0)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /><field46 name="Enter Fall Delay (default=1.0e-9)" /></u2><u11 name="type">d_nand<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_nand<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_nand<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u16><u19 name="type">d_nand<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u19><u13 name="type">d_nand<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_nand<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u14><u17 name="type">d_nand<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nand<field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_nand<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u20></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4078B_sub/analysis b/library/SubcircuitLibrary/CD4078B_sub/analysis new file mode 100644 index 00000000..db9906e6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib new file mode 100644 index 00000000..cca13acf --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir new file mode 100644 index 00000000..dc30556f --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir @@ -0,0 +1,57 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\CD4556BMS_IC\CD4556BMS_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/24 15:55:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad4_ Net-_U10-Pad1_ d_inverter +U4 Net-_U2-Pad5_ Net-_U4-Pad2_ d_inverter +U5 Net-_U2-Pad6_ Net-_U16-Pad2_ d_inverter +U6 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U7 Net-_U4-Pad2_ Net-_U10-Pad2_ d_inverter +U8 Net-_U10-Pad1_ Net-_U4-Pad2_ Net-_U12-Pad1_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad1_ Net-_U12-Pad3_ d_nand +U16 Net-_U12-Pad3_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nand +U9 Net-_U11-Pad1_ Net-_U4-Pad2_ Net-_U13-Pad1_ d_nand +U13 Net-_U13-Pad1_ Net-_U13-Pad1_ Net-_U13-Pad3_ d_nand +U17 Net-_U13-Pad3_ Net-_U16-Pad2_ Net-_U17-Pad3_ d_nand +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U14 Net-_U10-Pad3_ Net-_U10-Pad3_ Net-_U14-Pad3_ d_nand +U18 Net-_U14-Pad3_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_nand +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nand +U15 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U15-Pad3_ d_nand +U19 Net-_U15-Pad3_ Net-_U16-Pad2_ Net-_U19-Pad3_ d_nand +U20 Net-_U16-Pad3_ Net-_U20-Pad2_ d_inverter +U21 Net-_U17-Pad3_ Net-_U21-Pad2_ d_inverter +U22 Net-_U18-Pad3_ Net-_U22-Pad2_ d_inverter +U23 Net-_U19-Pad3_ Net-_U23-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ adc_bridge_3 +U24 Net-_U20-Pad2_ Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ dac_bridge_4 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U26 Net-_U25-Pad4_ Net-_U26-Pad2_ d_inverter +U27 Net-_U25-Pad5_ Net-_U27-Pad2_ d_inverter +U28 Net-_U25-Pad6_ Net-_U28-Pad2_ d_inverter +U29 Net-_U26-Pad2_ Net-_U29-Pad2_ d_inverter +U30 Net-_U27-Pad2_ Net-_U30-Pad2_ d_inverter +U31 Net-_U26-Pad2_ Net-_U27-Pad2_ Net-_U31-Pad3_ d_nand +U35 Net-_U31-Pad3_ Net-_U31-Pad3_ Net-_U35-Pad3_ d_nand +U39 Net-_U35-Pad3_ Net-_U28-Pad2_ Net-_U39-Pad3_ d_nand +U32 Net-_U29-Pad2_ Net-_U27-Pad2_ Net-_U32-Pad3_ d_nand +U36 Net-_U32-Pad3_ Net-_U32-Pad3_ Net-_U36-Pad3_ d_nand +U40 Net-_U36-Pad3_ Net-_U28-Pad2_ Net-_U40-Pad3_ d_nand +U33 Net-_U26-Pad2_ Net-_U30-Pad2_ Net-_U33-Pad3_ d_nand +U37 Net-_U33-Pad3_ Net-_U33-Pad3_ Net-_U37-Pad3_ d_nand +U41 Net-_U37-Pad3_ Net-_U28-Pad2_ Net-_U41-Pad3_ d_nand +U34 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U34-Pad3_ d_nand +U38 Net-_U34-Pad3_ Net-_U34-Pad3_ Net-_U38-Pad3_ d_nand +U42 Net-_U38-Pad3_ Net-_U28-Pad2_ Net-_U42-Pad3_ d_nand +U43 Net-_U39-Pad3_ Net-_U43-Pad2_ d_inverter +U44 Net-_U40-Pad3_ Net-_U44-Pad2_ d_inverter +U45 Net-_U41-Pad3_ Net-_U45-Pad2_ d_inverter +U46 Net-_U42-Pad3_ Net-_U46-Pad2_ d_inverter +U25 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U25-Pad4_ Net-_U25-Pad5_ Net-_U25-Pad6_ adc_bridge_3 +U47 Net-_U43-Pad2_ Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_U46-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad8_ dac_bridge_4 + +.end diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out new file mode 100644 index 00000000..d1117c7b --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out @@ -0,0 +1,196 @@ +* d:\fossee\esim\library\subcircuitlibrary\cd4556bms_ic\cd4556bms_ic.cir + +* u3 net-_u2-pad4_ net-_u10-pad1_ d_inverter +* u4 net-_u2-pad5_ net-_u4-pad2_ d_inverter +* u5 net-_u2-pad6_ net-_u16-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u4-pad2_ net-_u10-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad1_ net-_u12-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u9 net-_u11-pad1_ net-_u4-pad2_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad1_ net-_u13-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u14 net-_u10-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u16-pad3_ net-_u20-pad2_ d_inverter +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u24 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ dac_bridge_4 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u26 net-_u25-pad4_ net-_u26-pad2_ d_inverter +* u27 net-_u25-pad5_ net-_u27-pad2_ d_inverter +* u28 net-_u25-pad6_ net-_u28-pad2_ d_inverter +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u26-pad2_ net-_u27-pad2_ net-_u31-pad3_ d_nand +* u35 net-_u31-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_nand +* u39 net-_u35-pad3_ net-_u28-pad2_ net-_u39-pad3_ d_nand +* u32 net-_u29-pad2_ net-_u27-pad2_ net-_u32-pad3_ d_nand +* u36 net-_u32-pad3_ net-_u32-pad3_ net-_u36-pad3_ d_nand +* u40 net-_u36-pad3_ net-_u28-pad2_ net-_u40-pad3_ d_nand +* u33 net-_u26-pad2_ net-_u30-pad2_ net-_u33-pad3_ d_nand +* u37 net-_u33-pad3_ net-_u33-pad3_ net-_u37-pad3_ d_nand +* u41 net-_u37-pad3_ net-_u28-pad2_ net-_u41-pad3_ d_nand +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_nand +* u38 net-_u34-pad3_ net-_u34-pad3_ net-_u38-pad3_ d_nand +* u42 net-_u38-pad3_ net-_u28-pad2_ net-_u42-pad3_ d_nand +* u43 net-_u39-pad3_ net-_u43-pad2_ d_inverter +* u44 net-_u40-pad3_ net-_u44-pad2_ d_inverter +* u45 net-_u41-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u42-pad3_ net-_u46-pad2_ d_inverter +* u25 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ adc_bridge_3 +* u47 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ dac_bridge_4 +a1 net-_u2-pad4_ net-_u10-pad1_ u3 +a2 net-_u2-pad5_ net-_u4-pad2_ u4 +a3 net-_u2-pad6_ net-_u16-pad2_ u5 +a4 net-_u10-pad1_ net-_u11-pad1_ u6 +a5 net-_u4-pad2_ net-_u10-pad2_ u7 +a6 [net-_u10-pad1_ net-_u4-pad2_ ] net-_u12-pad1_ u8 +a7 [net-_u12-pad1_ net-_u12-pad1_ ] net-_u12-pad3_ u12 +a8 [net-_u12-pad3_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u11-pad1_ net-_u4-pad2_ ] net-_u13-pad1_ u9 +a10 [net-_u13-pad1_ net-_u13-pad1_ ] net-_u13-pad3_ u13 +a11 [net-_u13-pad3_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a15 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a18 net-_u16-pad3_ net-_u20-pad2_ u20 +a19 net-_u17-pad3_ net-_u21-pad2_ u21 +a20 net-_u18-pad3_ net-_u22-pad2_ u22 +a21 net-_u19-pad3_ net-_u23-pad2_ u23 +a22 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a23 [net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] u24 +a24 net-_u25-pad4_ net-_u26-pad2_ u26 +a25 net-_u25-pad5_ net-_u27-pad2_ u27 +a26 net-_u25-pad6_ net-_u28-pad2_ u28 +a27 net-_u26-pad2_ net-_u29-pad2_ u29 +a28 net-_u27-pad2_ net-_u30-pad2_ u30 +a29 [net-_u26-pad2_ net-_u27-pad2_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a31 [net-_u35-pad3_ net-_u28-pad2_ ] net-_u39-pad3_ u39 +a32 [net-_u29-pad2_ net-_u27-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u32-pad3_ ] net-_u36-pad3_ u36 +a34 [net-_u36-pad3_ net-_u28-pad2_ ] net-_u40-pad3_ u40 +a35 [net-_u26-pad2_ net-_u30-pad2_ ] net-_u33-pad3_ u33 +a36 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u37-pad3_ u37 +a37 [net-_u37-pad3_ net-_u28-pad2_ ] net-_u41-pad3_ u41 +a38 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a39 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u38-pad3_ u38 +a40 [net-_u38-pad3_ net-_u28-pad2_ ] net-_u42-pad3_ u42 +a41 net-_u39-pad3_ net-_u43-pad2_ u43 +a42 net-_u40-pad3_ net-_u44-pad2_ u44 +a43 net-_u41-pad3_ net-_u45-pad2_ u45 +a44 net-_u42-pad3_ net-_u46-pad2_ u46 +a45 [net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ ] [net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ ] u25 +a46 [net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ ] [net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ ] u47 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0.01e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch new file mode 100644 index 00000000..7cdf8bf2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch @@ -0,0 +1,1129 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches 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5250 +Wire Wire Line + 19350 5250 19450 5250 +Wire Wire Line + 19150 5200 19350 5200 +Connection ~ 19350 5200 +$Comp +L d_nand U34 +U 1 1 6672C7CE +P 18700 5950 +F 0 "U34" H 18700 5950 60 0000 C CNN +F 1 "d_nand" H 18750 6050 60 0000 C CNN +F 2 "" H 18700 5950 60 0000 C CNN +F 3 "" H 18700 5950 60 0000 C CNN + 1 18700 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U38 +U 1 1 6672C7D4 +P 19900 5950 +F 0 "U38" H 19900 5950 60 0000 C CNN +F 1 "d_nand" H 19950 6050 60 0000 C CNN +F 2 "" H 19900 5950 60 0000 C CNN +F 3 "" H 19900 5950 60 0000 C CNN + 1 19900 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U42 +U 1 1 6672C7DA +P 21100 6050 +F 0 "U42" H 21100 6050 60 0000 C CNN +F 1 "d_nand" H 21150 6150 60 0000 C CNN +F 2 "" H 21100 6050 60 0000 C CNN +F 3 "" H 21100 6050 60 0000 C CNN + 1 21100 6050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 5950 20600 5950 +Wire Wire Line + 20600 5950 20600 5900 +Wire Wire Line + 20600 5900 20350 5900 +Wire Wire Line + 19450 5850 19350 5850 +Wire Wire Line + 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Line + 16650 4250 16650 4550 +Connection ~ 16650 4550 +Wire Wire Line + 18250 4450 17750 4450 +Connection ~ 17750 4450 +Wire Wire Line + 18250 5150 18050 5150 +Wire Wire Line + 18050 5150 18050 3850 +Connection ~ 18050 3850 +Wire Wire Line + 18250 3950 17850 3950 +Wire Wire Line + 17850 3950 17850 4250 +Connection ~ 17850 4250 +Wire Wire Line + 18250 5250 17900 5250 +Connection ~ 17900 5250 +$Comp +L d_inverter U43 +U 1 1 6672C80C +P 22150 4000 +F 0 "U43" H 22150 3900 60 0000 C CNN +F 1 "d_inverter" H 22150 4150 60 0000 C CNN +F 2 "" H 22200 3950 60 0000 C CNN +F 3 "" H 22200 3950 60 0000 C CNN + 1 22150 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U44 +U 1 1 6672C812 +P 22150 4600 +F 0 "U44" H 22150 4500 60 0000 C CNN +F 1 "d_inverter" H 22150 4750 60 0000 C CNN +F 2 "" H 22200 4550 60 0000 C CNN +F 3 "" H 22200 4550 60 0000 C CNN + 1 22150 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U45 +U 1 1 6672C818 +P 22150 5300 +F 0 "U45" H 22150 5200 60 0000 C CNN +F 1 "d_inverter" H 22150 5450 60 0000 C CNN +F 2 "" H 22200 5250 60 0000 C CNN +F 3 "" H 22200 5250 60 0000 C CNN + 1 22150 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U46 +U 1 1 6672C81E +P 22150 6000 +F 0 "U46" H 22150 5900 60 0000 C CNN +F 1 "d_inverter" H 22150 6150 60 0000 C CNN +F 2 "" H 22200 5950 60 0000 C CNN +F 3 "" H 22200 5950 60 0000 C CNN + 1 22150 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 21550 4000 21850 4000 +Wire Wire Line + 21550 4600 21850 4600 +Wire Wire Line + 21550 5300 21850 5300 +Wire Wire Line + 21550 6000 21850 6000 +$Comp +L adc_bridge_3 U25 +U 1 1 6672C828 +P 14400 4850 +F 0 "U25" H 14400 4850 60 0000 C CNN +F 1 "adc_bridge_3" H 14400 5000 60 0000 C CNN +F 2 "" H 14400 4850 60 0000 C CNN +F 3 "" H 14400 4850 60 0000 C CNN + 1 14400 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14950 4800 15200 4800 +Wire Wire Line + 15200 4800 15200 3900 +Wire Wire Line + 15200 3900 15850 3900 +Wire Wire Line + 14950 4900 15500 4900 +Wire Wire Line + 15500 4900 15500 4550 +Wire Wire Line + 15500 4550 15850 4550 +Wire Wire Line + 14950 5000 15500 5000 +Wire Wire Line + 15500 5000 15500 6350 +Wire Wire Line + 15500 6350 15850 6350 +$Comp +L dac_bridge_4 U47 +U 1 1 6672C837 +P 23750 4950 +F 0 "U47" H 23750 4950 60 0000 C CNN +F 1 "dac_bridge_4" H 23750 5250 60 0000 C CNN +F 2 "" H 23750 4950 60 0000 C CNN +F 3 "" H 23750 4950 60 0000 C CNN + 1 23750 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 22450 4000 23000 4000 +Wire Wire Line + 23000 4000 23000 4750 +Wire Wire Line + 23000 4750 23200 4750 +Wire Wire Line + 22450 4600 22900 4600 +Wire Wire Line + 22900 4600 22900 4850 +Wire Wire Line + 22900 4850 23200 4850 +Wire Wire Line + 22450 5300 22900 5300 +Wire Wire Line + 22900 5300 22900 4950 +Wire Wire Line + 22900 4950 23200 4950 +Wire Wire Line + 22450 6000 23050 6000 +Wire Wire Line + 23050 6000 23050 5050 +Wire Wire Line + 23050 5050 23200 5050 +Wire Wire Line + 18000 3700 16600 3700 +$Comp +L PORT U1 +U 12 1 6672E56A +P 13400 4900 +F 0 "U1" H 13450 5000 30 0000 C CNN +F 1 "PORT" H 13400 4900 30 0000 C CNN +F 2 "" H 13400 4900 60 0000 C CNN +F 3 "" H 13400 4900 60 0000 C CNN + 12 13400 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24550 5050 24300 5050 +$Comp +L PORT U1 +U 14 1 6672E730 +P 13450 5100 +F 0 "U1" H 13500 5200 30 0000 C CNN +F 1 "PORT" H 13450 5100 30 0000 C CNN +F 2 "" H 13450 5100 60 0000 C CNN +F 3 "" H 13450 5100 60 0000 C CNN + 14 13450 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24650 4900 24400 4900 +Wire Wire Line + 24400 4900 24400 4950 +Wire Wire Line + 24400 4950 24300 4950 +$Comp +L PORT U1 +U 13 1 6672E8E7 +P 13450 4650 +F 0 "U1" H 13500 4750 30 0000 C CNN +F 1 "PORT" H 13450 4650 30 0000 C CNN +F 2 "" H 13450 4650 60 0000 C CNN +F 3 "" H 13450 4650 60 0000 C CNN + 13 13450 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24600 4750 24600 4850 +Wire Wire Line + 24600 4850 24300 4850 +$Comp +L PORT U1 +U 11 1 6672EACB +P 24800 4550 +F 0 "U1" H 24850 4650 30 0000 C CNN +F 1 "PORT" H 24800 4550 30 0000 C CNN +F 2 "" H 24800 4550 60 0000 C CNN +F 3 "" H 24800 4550 60 0000 C CNN + 11 24800 4550 + -1 0 0 1 +$EndComp +Wire Wire Line + 24550 4550 24400 4550 +Wire Wire Line + 24400 4550 24400 4750 +Wire Wire Line + 24400 4750 24300 4750 +$Comp +L PORT U1 +U 10 1 6672F27B +P 24850 4750 +F 0 "U1" H 24900 4850 30 0000 C CNN +F 1 "PORT" H 24850 4750 30 0000 C CNN +F 2 "" H 24850 4750 60 0000 C CNN +F 3 "" H 24850 4750 60 0000 C CNN + 10 24850 4750 + -1 0 0 1 +$EndComp +Wire Wire Line + 13650 4900 13800 4900 +$Comp +L PORT U1 +U 9 1 6672FB88 +P 24900 4900 +F 0 "U1" H 24950 5000 30 0000 C CNN +F 1 "PORT" H 24900 4900 30 0000 C CNN +F 2 "" H 24900 4900 60 0000 C CNN +F 3 "" H 24900 4900 60 0000 C CNN + 9 24900 4900 + -1 0 0 1 +$EndComp +Wire Wire Line + 13700 4650 13700 4800 +Wire Wire Line + 13700 4800 13800 4800 +$Comp +L PORT U1 +U 8 1 6672FD62 +P 24800 5050 +F 0 "U1" H 24850 5150 30 0000 C CNN +F 1 "PORT" H 24800 5050 30 0000 C CNN +F 2 "" H 24800 5050 60 0000 C CNN +F 3 "" H 24800 5050 60 0000 C CNN + 8 24800 5050 + -1 0 0 1 +$EndComp +Wire Wire Line + 13700 5100 13700 5000 +Wire Wire Line + 13700 5000 13800 5000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub new file mode 100644 index 00000000..fdabce6f --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub @@ -0,0 +1,190 @@ +* Subcircuit CD4556BMS_IC +.subckt CD4556BMS_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\cd4556bms_ic\cd4556bms_ic.cir +* u3 net-_u2-pad4_ net-_u10-pad1_ d_inverter +* u4 net-_u2-pad5_ net-_u4-pad2_ d_inverter +* u5 net-_u2-pad6_ net-_u16-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u4-pad2_ net-_u10-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad1_ net-_u12-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u9 net-_u11-pad1_ net-_u4-pad2_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad1_ net-_u13-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u14 net-_u10-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u16-pad3_ net-_u20-pad2_ d_inverter +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u24 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ dac_bridge_4 +* u26 net-_u25-pad4_ net-_u26-pad2_ d_inverter +* u27 net-_u25-pad5_ net-_u27-pad2_ d_inverter +* u28 net-_u25-pad6_ net-_u28-pad2_ d_inverter +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u26-pad2_ net-_u27-pad2_ net-_u31-pad3_ d_nand +* u35 net-_u31-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_nand +* u39 net-_u35-pad3_ net-_u28-pad2_ net-_u39-pad3_ d_nand +* u32 net-_u29-pad2_ net-_u27-pad2_ net-_u32-pad3_ d_nand +* u36 net-_u32-pad3_ net-_u32-pad3_ net-_u36-pad3_ d_nand +* u40 net-_u36-pad3_ net-_u28-pad2_ net-_u40-pad3_ d_nand +* u33 net-_u26-pad2_ net-_u30-pad2_ net-_u33-pad3_ d_nand +* u37 net-_u33-pad3_ net-_u33-pad3_ net-_u37-pad3_ d_nand +* u41 net-_u37-pad3_ net-_u28-pad2_ net-_u41-pad3_ d_nand +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_nand +* u38 net-_u34-pad3_ net-_u34-pad3_ net-_u38-pad3_ d_nand +* u42 net-_u38-pad3_ net-_u28-pad2_ net-_u42-pad3_ d_nand +* u43 net-_u39-pad3_ net-_u43-pad2_ d_inverter +* u44 net-_u40-pad3_ net-_u44-pad2_ d_inverter +* u45 net-_u41-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u42-pad3_ net-_u46-pad2_ d_inverter +* u25 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ adc_bridge_3 +* u47 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ dac_bridge_4 +a1 net-_u2-pad4_ net-_u10-pad1_ u3 +a2 net-_u2-pad5_ net-_u4-pad2_ u4 +a3 net-_u2-pad6_ net-_u16-pad2_ u5 +a4 net-_u10-pad1_ net-_u11-pad1_ u6 +a5 net-_u4-pad2_ net-_u10-pad2_ u7 +a6 [net-_u10-pad1_ net-_u4-pad2_ ] net-_u12-pad1_ u8 +a7 [net-_u12-pad1_ net-_u12-pad1_ ] net-_u12-pad3_ u12 +a8 [net-_u12-pad3_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u11-pad1_ net-_u4-pad2_ ] net-_u13-pad1_ u9 +a10 [net-_u13-pad1_ net-_u13-pad1_ ] net-_u13-pad3_ u13 +a11 [net-_u13-pad3_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a15 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a18 net-_u16-pad3_ net-_u20-pad2_ u20 +a19 net-_u17-pad3_ net-_u21-pad2_ u21 +a20 net-_u18-pad3_ net-_u22-pad2_ u22 +a21 net-_u19-pad3_ net-_u23-pad2_ u23 +a22 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a23 [net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] u24 +a24 net-_u25-pad4_ net-_u26-pad2_ u26 +a25 net-_u25-pad5_ net-_u27-pad2_ u27 +a26 net-_u25-pad6_ net-_u28-pad2_ u28 +a27 net-_u26-pad2_ net-_u29-pad2_ u29 +a28 net-_u27-pad2_ net-_u30-pad2_ u30 +a29 [net-_u26-pad2_ net-_u27-pad2_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a31 [net-_u35-pad3_ net-_u28-pad2_ ] net-_u39-pad3_ u39 +a32 [net-_u29-pad2_ net-_u27-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u32-pad3_ ] net-_u36-pad3_ u36 +a34 [net-_u36-pad3_ net-_u28-pad2_ ] net-_u40-pad3_ u40 +a35 [net-_u26-pad2_ net-_u30-pad2_ ] net-_u33-pad3_ u33 +a36 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u37-pad3_ u37 +a37 [net-_u37-pad3_ net-_u28-pad2_ ] net-_u41-pad3_ u41 +a38 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a39 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u38-pad3_ u38 +a40 [net-_u38-pad3_ net-_u28-pad2_ ] net-_u42-pad3_ u42 +a41 net-_u39-pad3_ net-_u43-pad2_ u43 +a42 net-_u40-pad3_ net-_u44-pad2_ u44 +a43 net-_u41-pad3_ net-_u45-pad2_ u45 +a44 net-_u42-pad3_ net-_u46-pad2_ u46 +a45 [net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ ] [net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ ] u25 +a46 [net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ ] [net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ ] u47 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4556BMS_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml new file mode 100644 index 00000000..5d199ade --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u12 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u12><u16 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u16><u9 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u9><u13 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u13><u17 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u17><u10 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u18><u11 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u11><u15 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15><u19 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u23><u2 name="type">adc_bridge<field64 name="Enter value for in_low (default=1.0)" /><field65 name="Enter value for in_high (default=2.0)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /><field67 name="Enter Fall Delay (default=1.0e-9)" /></u2><u24 name="type">dac_bridge<field68 name="Enter value for out_low (default=0.0)" /><field69 name="Enter value for out_high (default=5.0)" /><field70 name="Enter value for out_undef (default=0.5)" /><field71 name="Enter value for input load (default=1.0e-12)" /><field72 name="Enter the Rise Time (default=1.0e-9)" /><field73 name="Enter the Fall Time (default=1.0e-9)" /></u24><u26 name="type">d_inverter<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_inverter<field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_inverter<field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u31><u35 name="type">d_nand<field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /></u35><u39 name="type">d_nand<field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /></u39><u32 name="type">d_nand<field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /></u32><u36 name="type">d_nand<field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /></u36><u40 name="type">d_nand<field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /><field106 name="Enter Input Load (default=1.0e-12)" /></u40><u33 name="type">d_nand<field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /><field109 name="Enter Input Load (default=1.0e-12)" /></u33><u37 name="type">d_nand<field110 name="Enter Rise Delay (default=1.0e-9)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /><field112 name="Enter Input Load (default=1.0e-12)" /></u37><u41 name="type">d_nand<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u41><u34 name="type">d_nand<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u34><u38 name="type">d_nand<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u38><u42 name="type">d_nand<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u42><u43 name="type">d_inverter<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_inverter<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u44><u45 name="type">d_inverter<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_inverter<field134 name="Enter Rise Delay (default=1.0e-9)" /><field135 name="Enter Fall Delay (default=1.0e-9)" /><field136 name="Enter Input Load (default=1.0e-12)" /></u46><u25 name="type">adc_bridge<field137 name="Enter value for in_low (default=1.0)" /><field138 name="Enter value for in_high (default=2.0)" /><field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /></u25><u47 name="type">dac_bridge<field141 name="Enter value for out_low (default=0.0)" /><field142 name="Enter value for out_high (default=5.0)" /><field143 name="Enter value for out_undef (default=0.5)" /><field144 name="Enter value for input load (default=1.0e-12)" /><field145 name="Enter the Rise Time (default=1.0e-9)" /><field146 name="Enter the Fall Time (default=1.0e-9)" /></u47></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/analysis b/library/SubcircuitLibrary/CD4556BMS_sub/analysis new file mode 100644 index 00000000..db9906e6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LF147_sub/D.lib b/library/SubcircuitLibrary/LF147_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC-cache.lib b/library/SubcircuitLibrary/LF147_sub/LF147_IC-cache.lib new file mode 100644 index 00000000..6e89a43f --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC-cache.lib @@ -0,0 +1,186 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PJF +# +DEF eSim_PJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_PJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_p +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 -45 0 -5 15 -5 -15 -45 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir new file mode 100644 index 00000000..4b2bbf21 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir @@ -0,0 +1,67 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LF147_IC\LF147_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/12/24 14:21:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +I1 Net-_I1-Pad1_ Net-_I1-Pad2_ 80u +I3 Net-_I1-Pad1_ Net-_D3-Pad1_ 400u +J1 Net-_I1-Pad2_ Net-_J1-Pad2_ Net-_D1-Pad1_ jfet_p +J3 Net-_I1-Pad2_ Net-_J3-Pad2_ Net-_C1-Pad2_ jfet_p +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R1 Net-_D1-Pad2_ Net-_Q11-Pad3_ 5k +Q1 Net-_C1-Pad2_ Net-_D1-Pad1_ Net-_Q1-Pad3_ eSim_NPN +R3 Net-_Q1-Pad3_ Net-_Q11-Pad3_ 2k +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D3-Pad2_ Net-_C1-Pad1_ eSim_Diode +Q3 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q5 Net-_I1-Pad1_ Net-_D3-Pad1_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q11-Pad3_ Net-_C1-Pad1_ Net-_Q5-Pad3_ eSim_PNP +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +I5 Net-_I1-Pad1_ Net-_I5-Pad2_ 80u +I7 Net-_I1-Pad1_ Net-_D9-Pad1_ 400u +J5 Net-_I5-Pad2_ Net-_J5-Pad2_ Net-_D7-Pad1_ jfet_p +J7 Net-_I5-Pad2_ Net-_J7-Pad2_ Net-_C3-Pad2_ jfet_p +D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode +R5 Net-_D7-Pad2_ Net-_Q11-Pad3_ 5k +Q9 Net-_C3-Pad2_ Net-_D7-Pad1_ Net-_Q9-Pad3_ eSim_NPN +R7 Net-_Q9-Pad3_ Net-_Q11-Pad3_ 2k +D9 Net-_D9-Pad1_ Net-_D10-Pad1_ eSim_Diode +D10 Net-_D10-Pad1_ Net-_C3-Pad1_ eSim_Diode +Q11 Net-_C3-Pad1_ Net-_C3-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_I1-Pad1_ Net-_D9-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q14 Net-_Q11-Pad3_ Net-_C3-Pad1_ Net-_Q13-Pad3_ eSim_PNP +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10p +I2 Net-_I1-Pad1_ Net-_I2-Pad2_ 80u +I4 Net-_I1-Pad1_ Net-_D5-Pad1_ 400u +J2 Net-_I2-Pad2_ Net-_J2-Pad2_ Net-_D2-Pad1_ jfet_p +J4 Net-_I2-Pad2_ Net-_J4-Pad2_ Net-_C2-Pad2_ jfet_p +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R2 Net-_D2-Pad2_ Net-_Q11-Pad3_ 5k +Q2 Net-_C2-Pad2_ Net-_D2-Pad1_ Net-_Q2-Pad3_ eSim_NPN +R4 Net-_Q2-Pad3_ Net-_Q11-Pad3_ 2k +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +D6 Net-_D5-Pad2_ Net-_C2-Pad1_ eSim_Diode +Q4 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q7 Net-_I1-Pad1_ Net-_D5-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q11-Pad3_ Net-_C2-Pad1_ Net-_Q7-Pad3_ eSim_PNP +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10p +I6 Net-_I1-Pad1_ Net-_I6-Pad2_ 80u +I8 Net-_I1-Pad1_ Net-_D11-Pad1_ 400u +J6 Net-_I6-Pad2_ Net-_J6-Pad2_ Net-_D8-Pad1_ jfet_p +J8 Net-_I6-Pad2_ Net-_J8-Pad2_ Net-_C4-Pad2_ jfet_p +D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode +R6 Net-_D8-Pad2_ Net-_Q11-Pad3_ 5k +Q10 Net-_C4-Pad2_ Net-_D8-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R8 Net-_Q10-Pad3_ Net-_Q11-Pad3_ 2k +D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode +D12 Net-_D11-Pad2_ Net-_C4-Pad1_ eSim_Diode +Q12 Net-_C4-Pad1_ Net-_C4-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q15 Net-_I1-Pad1_ Net-_D11-Pad1_ Net-_Q15-Pad3_ eSim_NPN +Q16 Net-_Q11-Pad3_ Net-_C4-Pad1_ Net-_Q15-Pad3_ eSim_PNP +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 10p +U1 Net-_Q5-Pad3_ Net-_J1-Pad2_ Net-_J3-Pad2_ Net-_I1-Pad1_ Net-_J4-Pad2_ Net-_J2-Pad2_ Net-_Q7-Pad3_ Net-_Q15-Pad3_ Net-_J6-Pad2_ Net-_J8-Pad2_ Net-_Q11-Pad3_ Net-_J7-Pad2_ Net-_J5-Pad2_ Net-_Q13-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir.out b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir.out new file mode 100644 index 00000000..44d64043 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir.out @@ -0,0 +1,72 @@ +* d:\fossee\esim\library\subcircuitlibrary\lf147_ic\lf147_ic.cir + +.include PNP.lib +.include D.lib +.include NPN.lib +.include PJF.lib +i1 net-_i1-pad1_ net-_i1-pad2_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 400u +j1 net-_i1-pad2_ net-_j1-pad2_ net-_d1-pad1_ J2N3820 +j3 net-_i1-pad2_ net-_j3-pad2_ net-_c1-pad2_ J2N3820 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r1 net-_d1-pad2_ net-_q11-pad3_ 5k +q1 net-_c1-pad2_ net-_d1-pad1_ net-_q1-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q11-pad3_ 2k +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d3-pad2_ net-_c1-pad1_ 1N4148 +q3 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q5 net-_i1-pad1_ net-_d3-pad1_ net-_q5-pad3_ Q2N2222 +q6 net-_q11-pad3_ net-_c1-pad1_ net-_q5-pad3_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +i5 net-_i1-pad1_ net-_i5-pad2_ 80u +i7 net-_i1-pad1_ net-_d9-pad1_ 400u +j5 net-_i5-pad2_ net-_j5-pad2_ net-_d7-pad1_ J2N3820 +j7 net-_i5-pad2_ net-_j7-pad2_ net-_c3-pad2_ J2N3820 +d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148 +r5 net-_d7-pad2_ net-_q11-pad3_ 5k +q9 net-_c3-pad2_ net-_d7-pad1_ net-_q9-pad3_ Q2N2222 +r7 net-_q9-pad3_ net-_q11-pad3_ 2k +d9 net-_d9-pad1_ net-_d10-pad1_ 1N4148 +d10 net-_d10-pad1_ net-_c3-pad1_ 1N4148 +q11 net-_c3-pad1_ net-_c3-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_i1-pad1_ net-_d9-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q11-pad3_ net-_c3-pad1_ net-_q13-pad3_ Q2N2907A +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +i4 net-_i1-pad1_ net-_d5-pad1_ 400u +j2 net-_i2-pad2_ net-_j2-pad2_ net-_d2-pad1_ J2N3820 +j4 net-_i2-pad2_ net-_j4-pad2_ net-_c2-pad2_ J2N3820 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r2 net-_d2-pad2_ net-_q11-pad3_ 5k +q2 net-_c2-pad2_ net-_d2-pad1_ net-_q2-pad3_ Q2N2222 +r4 net-_q2-pad3_ net-_q11-pad3_ 2k +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d5-pad2_ net-_c2-pad1_ 1N4148 +q4 net-_c2-pad1_ net-_c2-pad2_ net-_q11-pad3_ Q2N2222 +q7 net-_i1-pad1_ net-_d5-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q11-pad3_ net-_c2-pad1_ net-_q7-pad3_ Q2N2907A +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +i6 net-_i1-pad1_ net-_i6-pad2_ 80u +i8 net-_i1-pad1_ net-_d11-pad1_ 400u +j6 net-_i6-pad2_ net-_j6-pad2_ net-_d8-pad1_ J2N3820 +j8 net-_i6-pad2_ net-_j8-pad2_ net-_c4-pad2_ J2N3820 +d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148 +r6 net-_d8-pad2_ net-_q11-pad3_ 5k +q10 net-_c4-pad2_ net-_d8-pad1_ net-_q10-pad3_ Q2N2222 +r8 net-_q10-pad3_ net-_q11-pad3_ 2k +d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148 +d12 net-_d11-pad2_ net-_c4-pad1_ 1N4148 +q12 net-_c4-pad1_ net-_c4-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_i1-pad1_ net-_d11-pad1_ net-_q15-pad3_ Q2N2222 +q16 net-_q11-pad3_ net-_c4-pad1_ net-_q15-pad3_ Q2N2907A +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +* u1 net-_q5-pad3_ net-_j1-pad2_ net-_j3-pad2_ net-_i1-pad1_ net-_j4-pad2_ net-_j2-pad2_ net-_q7-pad3_ net-_q15-pad3_ net-_j6-pad2_ net-_j8-pad2_ net-_q11-pad3_ net-_j7-pad2_ net-_j5-pad2_ net-_q13-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.pro b/library/SubcircuitLibrary/LF147_sub/LF147_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.sch b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sch new file mode 100644 index 00000000..243f479c --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sch @@ -0,0 +1,1186 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LF147_simplified_circuit-cache +EELAYER 25 0 +EELAYER END +$Descr User 31496 23622 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dc I1 +U 1 1 6690E555 +P 4850 4800 +F 0 "I1" H 4650 4900 60 0000 C CNN +F 1 "80u" H 4650 4750 60 0000 C CNN +F 2 "R1" H 4550 4800 60 0000 C CNN +F 3 "" H 4850 4800 60 0000 C CNN + 1 4850 4800 + 1 0 0 -1 +$EndComp +$Comp +L dc I3 +U 1 1 6690E556 +P 7350 4700 +F 0 "I3" H 7150 4800 60 0000 C CNN +F 1 "400u" H 7150 4650 60 0000 C CNN +F 2 "R1" H 7050 4700 60 0000 C CNN +F 3 "" H 7350 4700 60 0000 C CNN + 1 7350 4700 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J1 +U 1 1 6690E557 +P 4400 5800 +F 0 "J1" H 4300 5850 50 0000 R CNN +F 1 "jfet_p" H 4350 5950 50 0000 R CNN +F 2 "" H 4600 5900 29 0000 C CNN +F 3 "" H 4400 5800 60 0000 C CNN + 1 4400 5800 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J3 +U 1 1 6690E558 +P 5450 5800 +F 0 "J3" H 5350 5850 50 0000 R CNN +F 1 "jfet_p" H 5400 5950 50 0000 R CNN +F 2 "" H 5650 5900 29 0000 C CNN +F 3 "" H 5450 5800 60 0000 C CNN + 1 5450 5800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6690E559 +P 4500 7050 +F 0 "D1" H 4500 7150 50 0000 C CNN +F 1 "eSim_Diode" H 4500 6950 50 0000 C CNN +F 2 "" H 4500 7050 60 0000 C CNN +F 3 "" H 4500 7050 60 0000 C CNN + 1 4500 7050 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 6690E55A +P 4450 7500 +F 0 "R1" H 4500 7630 50 0000 C CNN +F 1 "5k" H 4500 7450 50 0000 C CNN +F 2 "" H 4500 7480 30 0000 C CNN +F 3 "" V 4500 7550 30 0000 C CNN + 1 4450 7500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6690E55B +P 5250 6800 +F 0 "Q1" H 5150 6850 50 0000 R CNN +F 1 "eSim_NPN" H 5200 6950 50 0000 R CNN +F 2 "" H 5450 6900 29 0000 C CNN +F 3 "" H 5250 6800 60 0000 C CNN + 1 5250 6800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 6690E55C +P 5300 7500 +F 0 "R3" H 5350 7630 50 0000 C CNN +F 1 "2k" H 5350 7450 50 0000 C CNN +F 2 "" H 5350 7480 30 0000 C CNN +F 3 "" V 5350 7550 30 0000 C CNN + 1 5300 7500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6690E55D +P 7350 5600 +F 0 "D3" H 7350 5700 50 0000 C CNN +F 1 "eSim_Diode" H 7350 5500 50 0000 C CNN +F 2 "" H 7350 5600 60 0000 C CNN +F 3 "" H 7350 5600 60 0000 C CNN + 1 7350 5600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6690E55E +P 7350 6000 +F 0 "D4" H 7350 6100 50 0000 C CNN +F 1 "eSim_Diode" H 7350 5900 50 0000 C CNN +F 2 "" H 7350 6000 60 0000 C CNN +F 3 "" H 7350 6000 60 0000 C CNN + 1 7350 6000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6690E55F +P 7250 7150 +F 0 "Q3" H 7150 7200 50 0000 R CNN +F 1 "eSim_NPN" H 7200 7300 50 0000 R CNN +F 2 "" H 7450 7250 29 0000 C CNN +F 3 "" H 7250 7150 60 0000 C CNN + 1 7250 7150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6690E560 +P 8550 5250 +F 0 "Q5" H 8450 5300 50 0000 R CNN +F 1 "eSim_NPN" H 8500 5400 50 0000 R CNN +F 2 "" H 8750 5350 29 0000 C CNN +F 3 "" H 8550 5250 60 0000 C CNN + 1 8550 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6690E561 +P 8550 6350 +F 0 "Q6" H 8450 6400 50 0000 R CNN +F 1 "eSim_PNP" H 8500 6500 50 0000 R CNN +F 2 "" H 8750 6450 29 0000 C CNN +F 3 "" H 8550 6350 60 0000 C CNN + 1 8550 6350 + 1 0 0 1 +$EndComp +$Comp +L capacitor C1 +U 1 1 6690E562 +P 6900 6800 +F 0 "C1" H 6925 6900 50 0000 L CNN +F 1 "10p" H 6925 6700 50 0000 L CNN +F 2 "" H 6938 6650 30 0000 C CNN +F 3 "" H 6900 6800 60 0000 C CNN + 1 6900 6800 + 0 1 1 0 +$EndComp +Wire Wire Line + 4500 5600 4500 5500 +Wire Wire Line + 4500 5500 5350 5500 +Wire Wire Line + 5350 5500 5350 5600 +Wire Wire Line + 4850 5250 4850 5500 +Connection ~ 4850 5500 +Wire Wire Line + 4500 6000 4500 6900 +Wire Wire Line + 4500 7200 4500 7400 +Wire Wire Line + 5350 6000 5350 6600 +Wire Wire Line + 5350 7000 5350 7400 +Wire Wire Line + 4500 8250 4500 7700 +Wire Wire Line + 2900 8250 8650 8250 +Wire Wire Line + 5350 8250 5350 7700 +Wire Wire Line + 5050 6800 4500 6800 +Connection ~ 4500 6800 +Wire Wire Line + 7350 5750 7350 5850 +Wire Wire Line + 7350 5150 7350 5450 +Wire Wire Line + 7350 8250 7350 7350 +Connection ~ 5350 8250 +Wire Wire Line + 7350 6150 7350 6950 +Wire Wire Line + 8650 4100 8650 5050 +Wire Wire Line + 3450 4100 8650 4100 +Wire Wire Line + 4850 4100 4850 4350 +Wire Wire Line + 7350 4250 7350 4100 +Connection ~ 7350 4100 +Wire Wire Line + 8650 5450 8650 6150 +Wire Wire Line + 8650 8250 8650 6550 +Connection ~ 7350 8250 +Connection ~ 6350 7150 +Connection ~ 4850 4100 +Connection ~ 4500 8250 +Wire Wire Line + 8650 5800 9800 5800 +Connection ~ 8650 5800 +Wire Wire Line + 8350 5250 7350 5250 +Connection ~ 7350 5250 +Wire Wire Line + 5650 5800 5950 5800 +Wire Wire Line + 8350 6350 7600 6350 +Wire Wire Line + 7600 6350 7600 6800 +Wire Wire Line + 7600 6800 7050 6800 +Connection ~ 7350 6800 +Wire Wire Line + 6750 6800 6350 6800 +Wire Wire Line + 6350 6800 6350 7150 +Wire Wire Line + 5700 7150 7050 7150 +Wire Wire Line + 5700 7150 5700 6300 +Wire Wire Line + 5700 6300 5350 6300 +Connection ~ 5350 6300 +Wire Wire Line + 3950 5800 4200 5800 +$Comp +L dc I5 +U 1 1 6690ED18 +P 19500 4700 +F 0 "I5" H 19300 4800 60 0000 C CNN +F 1 "80u" H 19300 4650 60 0000 C CNN +F 2 "R1" H 19200 4700 60 0000 C CNN +F 3 "" H 19500 4700 60 0000 C CNN + 1 19500 4700 + 1 0 0 -1 +$EndComp +$Comp +L dc I7 +U 1 1 6690ED1E +P 22000 4600 +F 0 "I7" H 21800 4700 60 0000 C CNN +F 1 "400u" H 21800 4550 60 0000 C CNN +F 2 "R1" H 21700 4600 60 0000 C CNN +F 3 "" H 22000 4600 60 0000 C CNN + 1 22000 4600 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J5 +U 1 1 6690ED24 +P 19050 5700 +F 0 "J5" H 18950 5750 50 0000 R CNN +F 1 "jfet_p" H 19000 5850 50 0000 R CNN +F 2 "" H 19250 5800 29 0000 C CNN +F 3 "" H 19050 5700 60 0000 C CNN + 1 19050 5700 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J7 +U 1 1 6690ED2A +P 20100 5700 +F 0 "J7" H 20000 5750 50 0000 R CNN +F 1 "jfet_p" H 20050 5850 50 0000 R CNN +F 2 "" H 20300 5800 29 0000 C CNN +F 3 "" H 20100 5700 60 0000 C CNN + 1 20100 5700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 6690ED30 +P 19150 6950 +F 0 "D7" H 19150 7050 50 0000 C CNN +F 1 "eSim_Diode" H 19150 6850 50 0000 C CNN +F 2 "" H 19150 6950 60 0000 C CNN +F 3 "" H 19150 6950 60 0000 C CNN + 1 19150 6950 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 6690ED36 +P 19100 7400 +F 0 "R5" H 19150 7530 50 0000 C CNN +F 1 "5k" H 19150 7350 50 0000 C CNN +F 2 "" H 19150 7380 30 0000 C CNN +F 3 "" V 19150 7450 30 0000 C CNN + 1 19100 7400 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6690ED3C +P 19900 6700 +F 0 "Q9" H 19800 6750 50 0000 R CNN +F 1 "eSim_NPN" H 19850 6850 50 0000 R CNN +F 2 "" H 20100 6800 29 0000 C CNN +F 3 "" H 19900 6700 60 0000 C CNN + 1 19900 6700 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 6690ED42 +P 19950 7400 +F 0 "R7" H 20000 7530 50 0000 C CNN +F 1 "2k" H 20000 7350 50 0000 C CNN +F 2 "" H 20000 7380 30 0000 C CNN +F 3 "" V 20000 7450 30 0000 C CNN + 1 19950 7400 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D9 +U 1 1 6690ED48 +P 22000 5500 +F 0 "D9" H 22000 5600 50 0000 C CNN +F 1 "eSim_Diode" H 22000 5400 50 0000 C CNN +F 2 "" H 22000 5500 60 0000 C CNN +F 3 "" H 22000 5500 60 0000 C CNN + 1 22000 5500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D10 +U 1 1 6690ED4E +P 22000 5900 +F 0 "D10" H 22000 6000 50 0000 C CNN +F 1 "eSim_Diode" H 22000 5800 50 0000 C CNN +F 2 "" H 22000 5900 60 0000 C CNN +F 3 "" H 22000 5900 60 0000 C CNN + 1 22000 5900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 6690ED54 +P 21900 7050 +F 0 "Q11" H 21800 7100 50 0000 R CNN +F 1 "eSim_NPN" H 21850 7200 50 0000 R CNN +F 2 "" H 22100 7150 29 0000 C CNN +F 3 "" H 21900 7050 60 0000 C CNN + 1 21900 7050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 6690ED5A +P 23200 5150 +F 0 "Q13" H 23100 5200 50 0000 R CNN +F 1 "eSim_NPN" H 23150 5300 50 0000 R CNN +F 2 "" H 23400 5250 29 0000 C CNN +F 3 "" H 23200 5150 60 0000 C CNN + 1 23200 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 6690ED60 +P 23200 6250 +F 0 "Q14" H 23100 6300 50 0000 R CNN +F 1 "eSim_PNP" H 23150 6400 50 0000 R CNN +F 2 "" H 23400 6350 29 0000 C CNN +F 3 "" H 23200 6250 60 0000 C CNN + 1 23200 6250 + 1 0 0 1 +$EndComp +$Comp +L capacitor C3 +U 1 1 6690ED66 +P 21550 6700 +F 0 "C3" H 21575 6800 50 0000 L CNN +F 1 "10p" H 21575 6600 50 0000 L CNN +F 2 "" H 21588 6550 30 0000 C CNN +F 3 "" H 21550 6700 60 0000 C CNN + 1 21550 6700 + 0 1 1 0 +$EndComp +Wire Wire Line + 19150 5500 19150 5400 +Wire Wire Line + 19150 5400 20000 5400 +Wire Wire Line + 20000 5400 20000 5500 +Wire Wire Line + 19500 5150 19500 5400 +Connection ~ 19500 5400 +Wire Wire Line + 19150 5900 19150 6800 +Wire Wire Line + 19150 7100 19150 7300 +Wire Wire Line + 20000 5900 20000 6500 +Wire Wire Line + 20000 6900 20000 7300 +Wire Wire Line + 19150 8150 19150 7600 +Wire Wire Line + 18450 8150 23300 8150 +Wire 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0000 R CNN +F 1 "jfet_p" H 5800 15800 50 0000 R CNN +F 2 "" H 6050 15750 29 0000 C CNN +F 3 "" H 5850 15650 60 0000 C CNN + 1 5850 15650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6690F50F +P 4900 16900 +F 0 "D2" H 4900 17000 50 0000 C CNN +F 1 "eSim_Diode" H 4900 16800 50 0000 C CNN +F 2 "" H 4900 16900 60 0000 C CNN +F 3 "" H 4900 16900 60 0000 C CNN + 1 4900 16900 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 6690F515 +P 4850 17350 +F 0 "R2" H 4900 17480 50 0000 C CNN +F 1 "5k" H 4900 17300 50 0000 C CNN +F 2 "" H 4900 17330 30 0000 C CNN +F 3 "" V 4900 17400 30 0000 C CNN + 1 4850 17350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 6690F51B +P 5650 16650 +F 0 "Q2" H 5550 16700 50 0000 R CNN +F 1 "eSim_NPN" H 5600 16800 50 0000 R CNN +F 2 "" H 5850 16750 29 0000 C CNN +F 3 "" H 5650 16650 60 0000 C CNN + 1 5650 16650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 6690F521 +P 5700 17350 +F 0 "R4" H 5750 17480 50 0000 C CNN +F 1 "2k" H 5750 17300 50 0000 C CNN +F 2 "" H 5750 17330 30 0000 C CNN +F 3 "" V 5750 17400 30 0000 C CNN + 1 5700 17350 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 6690F527 +P 7750 15450 +F 0 "D5" H 7750 15550 50 0000 C CNN +F 1 "eSim_Diode" H 7750 15350 50 0000 C CNN +F 2 "" H 7750 15450 60 0000 C CNN +F 3 "" H 7750 15450 60 0000 C CNN + 1 7750 15450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 6690F52D +P 7750 15850 +F 0 "D6" H 7750 15950 50 0000 C CNN +F 1 "eSim_Diode" H 7750 15750 50 0000 C CNN +F 2 "" H 7750 15850 60 0000 C CNN +F 3 "" H 7750 15850 60 0000 C CNN + 1 7750 15850 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6690F533 +P 7650 17000 +F 0 "Q4" H 7550 17050 50 0000 R CNN +F 1 "eSim_NPN" H 7600 17150 50 0000 R CNN +F 2 "" H 7850 17100 29 0000 C CNN +F 3 "" H 7650 17000 60 0000 C CNN + 1 7650 17000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6690F539 +P 8950 15100 +F 0 "Q7" H 8850 15150 50 0000 R CNN +F 1 "eSim_NPN" H 8900 15250 50 0000 R CNN +F 2 "" H 9150 15200 29 0000 C CNN +F 3 "" H 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+F 1 "2k" H 20350 16750 50 0000 C CNN +F 2 "" H 20350 16780 30 0000 C CNN +F 3 "" V 20350 16850 30 0000 C CNN + 1 20300 16800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D11 +U 1 1 6690FD62 +P 22350 14900 +F 0 "D11" H 22350 15000 50 0000 C CNN +F 1 "eSim_Diode" H 22350 14800 50 0000 C CNN +F 2 "" H 22350 14900 60 0000 C CNN +F 3 "" H 22350 14900 60 0000 C CNN + 1 22350 14900 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D12 +U 1 1 6690FD68 +P 22350 15300 +F 0 "D12" H 22350 15400 50 0000 C CNN +F 1 "eSim_Diode" H 22350 15200 50 0000 C CNN +F 2 "" H 22350 15300 60 0000 C CNN +F 3 "" H 22350 15300 60 0000 C CNN + 1 22350 15300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 6690FD6E +P 22250 16450 +F 0 "Q12" H 22150 16500 50 0000 R CNN +F 1 "eSim_NPN" H 22200 16600 50 0000 R CNN +F 2 "" H 22450 16550 29 0000 C CNN +F 3 "" H 22250 16450 60 0000 C CNN + 1 22250 16450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 6690FD74 +P 23550 14550 +F 0 "Q15" H 23450 14600 50 0000 R CNN +F 1 "eSim_NPN" H 23500 14700 50 0000 R CNN +F 2 "" H 23750 14650 29 0000 C CNN +F 3 "" H 23550 14550 60 0000 C CNN + 1 23550 14550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q16 +U 1 1 6690FD7A +P 23550 15650 +F 0 "Q16" H 23450 15700 50 0000 R CNN +F 1 "eSim_PNP" H 23500 15800 50 0000 R CNN +F 2 "" H 23750 15750 29 0000 C CNN +F 3 "" H 23550 15650 60 0000 C CNN + 1 23550 15650 + 1 0 0 1 +$EndComp +$Comp +L capacitor C4 +U 1 1 6690FD80 +P 21900 16100 +F 0 "C4" H 21925 16200 50 0000 L CNN +F 1 "10p" H 21925 16000 50 0000 L CNN +F 2 "" H 21938 15950 30 0000 C CNN +F 3 "" H 21900 16100 60 0000 C CNN + 1 21900 16100 + 0 1 1 0 +$EndComp +Wire Wire Line + 19500 14900 19500 14800 +Wire Wire Line + 19500 14800 20350 14800 +Wire Wire Line + 20350 14800 20350 14900 +Wire Wire Line + 19850 14550 19850 14800 +Connection ~ 19850 14800 +Wire Wire Line + 19500 15300 19500 16200 +Wire Wire Line + 19500 16500 19500 16700 +Wire Wire Line + 20350 15300 20350 15900 +Wire Wire Line + 20350 16300 20350 16700 +Wire Wire Line + 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C CNN + 1 10050 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6691397B +P 18350 5700 +F 0 "U1" H 18400 5800 30 0000 C CNN +F 1 "PORT" H 18350 5700 30 0000 C CNN +F 2 "" H 18350 5700 60 0000 C CNN +F 3 "" H 18350 5700 60 0000 C CNN + 13 18350 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 669150B9 +P 20850 5700 +F 0 "U1" H 20900 5800 30 0000 C CNN +F 1 "PORT" H 20850 5700 30 0000 C CNN +F 2 "" H 20850 5700 60 0000 C CNN +F 3 "" H 20850 5700 60 0000 C CNN + 12 20850 5700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6691577B +P 24700 5700 +F 0 "U1" H 24750 5800 30 0000 C CNN +F 1 "PORT" H 24700 5700 30 0000 C CNN +F 2 "" H 24700 5700 60 0000 C CNN +F 3 "" H 24700 5700 60 0000 C CNN + 14 24700 5700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 669161F1 +P 10450 15650 +F 0 "U1" H 10500 15750 30 0000 C CNN +F 1 "PORT" H 10450 15650 30 0000 C CNN +F 2 "" H 10450 15650 60 0000 C CNN +F 3 "" H 10450 15650 60 0000 C CNN + 7 10450 15650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 66917212 +P 4100 15650 +F 0 "U1" H 4150 15750 30 0000 C CNN +F 1 "PORT" H 4100 15650 30 0000 C CNN +F 2 "" H 4100 15650 60 0000 C CNN +F 3 "" H 4100 15650 60 0000 C CNN + 6 4100 15650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6691775E +P 6600 15650 +F 0 "U1" H 6650 15750 30 0000 C CNN +F 1 "PORT" H 6600 15650 30 0000 C CNN +F 2 "" H 6600 15650 60 0000 C CNN +F 3 "" H 6600 15650 60 0000 C CNN + 5 6600 15650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 66918407 +P 25050 15100 +F 0 "U1" H 25100 15200 30 0000 C CNN +F 1 "PORT" H 25050 15100 30 0000 C CNN +F 2 "" H 25050 15100 60 0000 C CNN +F 3 "" H 25050 15100 60 0000 C CNN + 8 25050 15100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 669199DD +P 18700 15100 +F 0 "U1" H 18750 15200 30 0000 C CNN +F 1 "PORT" H 18700 15100 30 0000 C CNN +F 2 "" H 18700 15100 60 0000 C CNN +F 3 "" H 18700 15100 60 0000 C CNN + 9 18700 15100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6691A785 +P 21200 15100 +F 0 "U1" H 21250 15200 30 0000 C CNN +F 1 "PORT" H 21200 15100 30 0000 C CNN +F 2 "" H 21200 15100 60 0000 C CNN +F 3 "" H 21200 15100 60 0000 C CNN + 10 21200 15100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6691B2C4 +P 2650 8250 +F 0 "U1" H 2700 8350 30 0000 C CNN +F 1 "PORT" H 2650 8250 30 0000 C CNN +F 2 "" H 2650 8250 60 0000 C CNN +F 3 "" H 2650 8250 60 0000 C CNN + 11 2650 8250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18450 8150 18450 8650 +Wire Wire Line + 18450 8650 4200 8650 +Wire Wire Line + 4200 8650 4200 8250 +Connection ~ 4200 8250 +Wire Wire Line + 11150 17550 11150 9350 +Wire Wire Line + 11150 9350 3900 9350 +Wire Wire Line + 3900 9350 3900 8250 +Connection ~ 3900 8250 +Wire Wire Line + 1900 18100 1900 8900 +Wire Wire Line + 1900 8900 3550 8900 +Wire Wire Line + 3550 8900 3550 8250 +Connection ~ 3550 8250 +Wire Wire Line + 1500 13950 1500 5400 +Wire Wire Line + 1500 5400 4250 5400 +Wire Wire Line + 4250 5400 4250 4100 +Connection ~ 4250 4100 +$Comp +L PORT U1 +U 4 1 669208AB +P 3200 4100 +F 0 "U1" H 3250 4200 30 0000 C CNN +F 1 "PORT" H 3200 4100 30 0000 C CNN +F 2 "" H 3200 4100 60 0000 C CNN +F 3 "" H 3200 4100 60 0000 C CNN + 4 3200 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14100 13400 14100 3200 +Wire Wire Line + 14100 3200 4100 3200 +Wire Wire Line + 4100 3200 4100 4100 +Connection ~ 4100 4100 +Wire Wire Line + 4150 4000 4150 4100 +Connection ~ 4150 4100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.sub b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sub new file mode 100644 index 00000000..e4cccc57 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sub @@ -0,0 +1,66 @@ +* Subcircuit LF147_IC +.subckt LF147_IC net-_q5-pad3_ net-_j1-pad2_ net-_j3-pad2_ net-_i1-pad1_ net-_j4-pad2_ net-_j2-pad2_ net-_q7-pad3_ net-_q15-pad3_ net-_j6-pad2_ net-_j8-pad2_ net-_q11-pad3_ net-_j7-pad2_ net-_j5-pad2_ net-_q13-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\lf147_ic\lf147_ic.cir +.include PNP.lib +.include D.lib +.include NPN.lib +.include PJF.lib +i1 net-_i1-pad1_ net-_i1-pad2_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 400u +j1 net-_i1-pad2_ net-_j1-pad2_ net-_d1-pad1_ J2N3820 +j3 net-_i1-pad2_ net-_j3-pad2_ net-_c1-pad2_ J2N3820 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r1 net-_d1-pad2_ net-_q11-pad3_ 5k +q1 net-_c1-pad2_ net-_d1-pad1_ net-_q1-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q11-pad3_ 2k +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d3-pad2_ net-_c1-pad1_ 1N4148 +q3 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q5 net-_i1-pad1_ net-_d3-pad1_ net-_q5-pad3_ Q2N2222 +q6 net-_q11-pad3_ net-_c1-pad1_ net-_q5-pad3_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +i5 net-_i1-pad1_ net-_i5-pad2_ 80u +i7 net-_i1-pad1_ net-_d9-pad1_ 400u +j5 net-_i5-pad2_ net-_j5-pad2_ net-_d7-pad1_ J2N3820 +j7 net-_i5-pad2_ net-_j7-pad2_ net-_c3-pad2_ J2N3820 +d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148 +r5 net-_d7-pad2_ net-_q11-pad3_ 5k +q9 net-_c3-pad2_ net-_d7-pad1_ net-_q9-pad3_ Q2N2222 +r7 net-_q9-pad3_ net-_q11-pad3_ 2k +d9 net-_d9-pad1_ net-_d10-pad1_ 1N4148 +d10 net-_d10-pad1_ net-_c3-pad1_ 1N4148 +q11 net-_c3-pad1_ net-_c3-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_i1-pad1_ net-_d9-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q11-pad3_ net-_c3-pad1_ net-_q13-pad3_ Q2N2907A +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +i4 net-_i1-pad1_ net-_d5-pad1_ 400u +j2 net-_i2-pad2_ net-_j2-pad2_ net-_d2-pad1_ J2N3820 +j4 net-_i2-pad2_ net-_j4-pad2_ net-_c2-pad2_ J2N3820 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r2 net-_d2-pad2_ net-_q11-pad3_ 5k +q2 net-_c2-pad2_ net-_d2-pad1_ net-_q2-pad3_ Q2N2222 +r4 net-_q2-pad3_ net-_q11-pad3_ 2k +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d5-pad2_ net-_c2-pad1_ 1N4148 +q4 net-_c2-pad1_ net-_c2-pad2_ net-_q11-pad3_ Q2N2222 +q7 net-_i1-pad1_ net-_d5-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q11-pad3_ net-_c2-pad1_ net-_q7-pad3_ Q2N2907A +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +i6 net-_i1-pad1_ net-_i6-pad2_ 80u +i8 net-_i1-pad1_ net-_d11-pad1_ 400u +j6 net-_i6-pad2_ net-_j6-pad2_ net-_d8-pad1_ J2N3820 +j8 net-_i6-pad2_ net-_j8-pad2_ net-_c4-pad2_ J2N3820 +d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148 +r6 net-_d8-pad2_ net-_q11-pad3_ 5k +q10 net-_c4-pad2_ net-_d8-pad1_ net-_q10-pad3_ Q2N2222 +r8 net-_q10-pad3_ net-_q11-pad3_ 2k +d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148 +d12 net-_d11-pad2_ net-_c4-pad1_ 1N4148 +q12 net-_c4-pad1_ net-_c4-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_i1-pad1_ net-_d11-pad1_ net-_q15-pad3_ Q2N2222 +q16 net-_q11-pad3_ net-_c4-pad1_ net-_q15-pad3_ Q2N2907A +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +* Control Statements + +.ends LF147_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC_Previous_Values.xml b/library/SubcircuitLibrary/LF147_sub/LF147_IC_Previous_Values.xml new file mode 100644 index 00000000..7232ccc1 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i1 name="Source type">80u</i1><i3 name="Source type">400u</i3><i5 name="Source type">80u</i5><i7 name="Source type">400u</i7><i2 name="Source type">80u</i2><i4 name="Source type">400u</i4><i6 name="Source type">80u</i6><i8 name="Source type">400u</i8></source><model /><devicemodel><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j1><j3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j3><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><j5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j5><j7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j7><d7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><d9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d10><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q14><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j2><j4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j4><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><d5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><j6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j6><j8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j8><d8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d11><d12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d12><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q16></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LF147_sub/NPN.lib b/library/SubcircuitLibrary/LF147_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LF147_sub/PJF.lib b/library/SubcircuitLibrary/LF147_sub/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/library/SubcircuitLibrary/LF147_sub/PNP.lib b/library/SubcircuitLibrary/LF147_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LF147_sub/analysis b/library/SubcircuitLibrary/LF147_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC-cache.lib b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC-cache.lib new file mode 100644 index 00000000..809d9541 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC-cache.lib @@ -0,0 +1,160 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir new file mode 100644 index 00000000..7de39320 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir @@ -0,0 +1,49 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LM140L_IC\LM140L_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/01/24 22:06:45 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_J1-Pad1_ Net-_Q2-Pad3_ 418 +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +U1 Net-_J1-Pad2_ Net-_J1-Pad3_ zener +Q1 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad3_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ eSim_PNP +U2 Net-_J1-Pad2_ Net-_Q1-Pad3_ zener +Q3 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q7 Net-_Q11-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad3_ Net-_Q4-Pad3_ eSim_NPN +R2 Net-_Q4-Pad3_ Net-_Q8-Pad2_ 576 +R3 Net-_Q8-Pad2_ Net-_R3-Pad2_ 3.41k +R4 Net-_R3-Pad2_ Net-_Q10-Pad2_ 3.89k +Q5 Net-_Q10-Pad2_ Net-_Q10-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q5-Pad3_ Net-_Q5-Pad3_ Net-_J1-Pad2_ eSim_NPN +U3 Net-_R10-Pad1_ Net-_J1-Pad1_ zener +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 5k +U4 Net-_Q13-Pad2_ Net-_R10-Pad2_ zener +Q15 Net-_J1-Pad1_ Net-_Q11-Pad3_ Net-_Q12-Pad1_ eSim_NPN +Q9 Net-_Q11-Pad3_ Net-_Q8-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_Q8-Pad2_ Net-_Q4-Pad3_ eSim_PNP +R5 Net-_Q8-Pad1_ Net-_J1-Pad2_ 7.8k +Q16 Net-_J1-Pad1_ Net-_Q12-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q10-Pad1_ eSim_NPN +R6 Net-_Q12-Pad2_ Net-_R3-Pad2_ 13k +Q11 Net-_J1-Pad2_ Net-_C1-Pad1_ Net-_Q11-Pad3_ eSim_PNP +R8 Net-_Q11-Pad3_ Net-_C1-Pad1_ 5.76k +Q14 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q10-Pad3_ Net-_J1-Pad2_ 2.84k +R9 Net-_Q13-Pad3_ Net-_R13-Pad2_ 100 +R14 Net-_Q16-Pad3_ Net-_R13-Pad2_ 1.9 +R13 Net-_Q12-Pad1_ Net-_R13-Pad2_ 2.5k +R11 Net-_Q16-Pad3_ Net-_Q13-Pad2_ 100 +R15 Net-_R13-Pad2_ Net-_R12-Pad1_ 1.5k +R12 Net-_R12-Pad1_ Net-_C1-Pad2_ 15k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5u +R16 Net-_R12-Pad1_ Net-_J1-Pad2_ 2.23k +Q13 Net-_Q11-Pad3_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +U5 Net-_J1-Pad1_ Net-_R13-Pad2_ Net-_J1-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir.out b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir.out new file mode 100644 index 00000000..68cd633e --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir.out @@ -0,0 +1,65 @@ +* d:\fossee\esim\library\subcircuitlibrary\lm140l_ic\lm140l_ic.cir + +.include NJF.lib +.include NPN.lib +.include PNP.lib +r1 net-_j1-pad1_ net-_q2-pad3_ 418 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +* u1 net-_j1-pad2_ net-_j1-pad3_ zener +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ Q2N2907A +* u2 net-_j1-pad2_ net-_q1-pad3_ zener +q3 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q7 net-_q11-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q4 net-_q1-pad1_ net-_q1-pad3_ net-_q4-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_q8-pad2_ 576 +r3 net-_q8-pad2_ net-_r3-pad2_ 3.41k +r4 net-_r3-pad2_ net-_q10-pad2_ 3.89k +q5 net-_q10-pad2_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q5-pad3_ net-_j1-pad2_ Q2N2222 +* u3 net-_r10-pad1_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 5k +* u4 net-_q13-pad2_ net-_r10-pad2_ zener +q15 net-_j1-pad1_ net-_q11-pad3_ net-_q12-pad1_ Q2N2222 +q9 net-_q11-pad3_ net-_q8-pad1_ net-_j1-pad2_ Q2N2222 +q8 net-_q8-pad1_ net-_q8-pad2_ net-_q4-pad3_ Q2N2907A +r5 net-_q8-pad1_ net-_j1-pad2_ 7.8k +q16 net-_j1-pad1_ net-_q12-pad1_ net-_q16-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q10-pad1_ Q2N2222 +r6 net-_q12-pad2_ net-_r3-pad2_ 13k +q11 net-_j1-pad2_ net-_c1-pad1_ net-_q11-pad3_ Q2N2907A +r8 net-_q11-pad3_ net-_c1-pad1_ 5.76k +q14 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q10-pad3_ net-_j1-pad2_ 2.84k +r9 net-_q13-pad3_ net-_r13-pad2_ 100 +r14 net-_q16-pad3_ net-_r13-pad2_ 1.9 +r13 net-_q12-pad1_ net-_r13-pad2_ 2.5k +r11 net-_q16-pad3_ net-_q13-pad2_ 100 +r15 net-_r13-pad2_ net-_r12-pad1_ 1.5k +r12 net-_r12-pad1_ net-_c1-pad2_ 15k +c1 net-_c1-pad1_ net-_c1-pad2_ 5u +r16 net-_r12-pad1_ net-_j1-pad2_ 2.23k +q13 net-_q11-pad3_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +* u5 net-_j1-pad1_ net-_r13-pad2_ net-_j1-pad2_ port +a1 net-_j1-pad2_ net-_j1-pad3_ u1 +a2 net-_j1-pad2_ net-_q1-pad3_ u2 +a3 net-_r10-pad1_ net-_j1-pad1_ u3 +a4 net-_q13-pad2_ net-_r10-pad2_ u4 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.pro b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sch b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sch new file mode 100644 index 00000000..fee2452b --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sch @@ -0,0 +1,732 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM140L_IC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 666EB6C4 +P 2300 1550 +F 0 "R1" H 2350 1680 50 0000 C CNN +F 1 "418" H 2350 1500 50 0000 C CNN +F 2 "" H 2350 1530 30 0000 C CNN +F 3 "" V 2350 1600 30 0000 C CNN + 1 2300 1550 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J1 +U 1 1 666EB6C5 +P 1650 1800 +F 0 "J1" H 1550 1850 50 0000 R CNN +F 1 "jfet_n" H 1600 1950 50 0000 R CNN +F 2 "" H 1850 1900 29 0000 C CNN +F 3 "" H 1650 1800 60 0000 C CNN + 1 1650 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 1600 1750 1300 +Wire Wire Line + 1750 1300 7600 1300 +Wire Wire Line + 2350 1300 2350 1450 +$Comp +L zener U1 +U 1 1 666EB6C6 +P 1750 3600 +F 0 "U1" H 1700 3500 60 0000 C CNN +F 1 "zener" H 1750 3700 60 0000 C CNN +F 2 "" H 1800 3600 60 0000 C CNN +F 3 "" H 1800 3600 60 0000 C CNN + 1 1750 3600 + 0 1 -1 0 +$EndComp +Wire Wire Line + 1750 2000 1750 3300 +$Comp +L eSim_NPN Q1 +U 1 1 666EB6C7 +P 2000 2550 +F 0 "Q1" H 1900 2600 50 0000 R CNN +F 1 "eSim_NPN" H 1950 2700 50 0000 R CNN +F 2 "" H 2200 2650 29 0000 C CNN +F 3 "" H 2000 2550 60 0000 C CNN + 1 2000 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 666EB6C8 +P 2450 2000 +F 0 "Q2" H 2350 2050 50 0000 R CNN +F 1 "eSim_PNP" H 2400 2150 50 0000 R CNN +F 2 "" H 2650 2100 29 0000 C CNN +F 3 "" H 2450 2000 60 0000 C CNN + 1 2450 2000 + -1 0 0 1 +$EndComp +Wire Wire Line + 2350 1800 2350 1750 +$Comp +L zener U2 +U 1 1 666EB6C9 +P 2350 3600 +F 0 "U2" H 2300 3500 60 0000 C CNN +F 1 "zener" H 2350 3700 60 0000 C CNN +F 2 "" H 2400 3600 60 0000 C CNN +F 3 "" H 2400 3600 60 0000 C CNN + 1 2350 3600 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2350 2200 2350 3300 +$Comp +L eSim_PNP Q3 +U 1 1 666EB6CA +P 3050 2000 +F 0 "Q3" H 2950 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3000 2150 50 0000 R CNN +F 2 "" H 3250 2100 29 0000 C CNN +F 3 "" H 3050 2000 60 0000 C CNN + 1 3050 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 666EB6CB +P 3500 2000 +F 0 "Q7" H 3400 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3450 2150 50 0000 R CNN +F 2 "" H 3700 2100 29 0000 C CNN +F 3 "" H 3500 2000 60 0000 C CNN + 1 3500 2000 + 1 0 0 1 +$EndComp +Wire Wire Line + 2650 2000 3300 2000 +Wire Wire Line + 3150 1800 3600 1800 +Wire Wire Line + 3400 1300 3400 1800 +Connection ~ 2350 1300 +Connection ~ 3400 1800 +Connection ~ 2850 2000 +$Comp +L eSim_NPN Q4 +U 1 1 666EB6CC +P 3050 2700 +F 0 "Q4" H 2950 2750 50 0000 R CNN +F 1 "eSim_NPN" H 3000 2850 50 0000 R CNN +F 2 "" H 3250 2800 29 0000 C CNN +F 3 "" H 3050 2700 60 0000 C CNN + 1 3050 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 2200 3150 2500 +Wire Wire Line + 2750 2000 2750 2350 +Wire Wire Line + 2750 2350 3150 2350 +Connection ~ 3150 2350 +Connection ~ 2750 2000 +Wire Wire Line + 2200 2700 2850 2700 +Wire Wire Line + 2200 2700 2200 2750 +Wire Wire Line + 2200 2750 2100 2750 +Connection ~ 2350 2700 +Wire Wire Line + 2100 2350 2600 2350 +Wire Wire Line + 2600 2350 2600 2450 +Wire Wire Line + 2600 2450 3150 2450 +Connection ~ 3150 2450 +Wire Wire Line + 1800 2550 1750 2550 +Connection ~ 1750 2550 +$Comp +L resistor R2 +U 1 1 666EB6CD +P 3100 3150 +F 0 "R2" H 3150 3280 50 0000 C CNN +F 1 "576" H 3150 3100 50 0000 C CNN +F 2 "" H 3150 3130 30 0000 C CNN +F 3 "" V 3150 3200 30 0000 C CNN + 1 3100 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 666EB6CE +P 3100 3600 +F 0 "R3" H 3150 3730 50 0000 C CNN +F 1 "3.41k" H 3150 3550 50 0000 C CNN +F 2 "" H 3150 3580 30 0000 C CNN +F 3 "" V 3150 3650 30 0000 C CNN + 1 3100 3600 + 0 1 1 0 +$EndComp +Wire Wire Line + 3150 2900 3150 3050 +Wire Wire Line + 3150 3350 3150 3500 +$Comp +L resistor R4 +U 1 1 666EB6CF +P 3100 4300 +F 0 "R4" H 3150 4430 50 0000 C CNN +F 1 "3.89k" H 3150 4250 50 0000 C CNN +F 2 "" H 3150 4280 30 0000 C CNN +F 3 "" V 3150 4350 30 0000 C CNN + 1 3100 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 3150 3800 3150 4200 +$Comp +L eSim_NPN Q5 +U 1 1 666EB6D0 +P 3050 5000 +F 0 "Q5" H 2950 5050 50 0000 R CNN +F 1 "eSim_NPN" H 3000 5150 50 0000 R CNN +F 2 "" H 3250 5100 29 0000 C CNN +F 3 "" H 3050 5000 60 0000 C CNN + 1 3050 5000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 666EB6D1 +P 3050 5600 +F 0 "Q6" H 2950 5650 50 0000 R CNN +F 1 "eSim_NPN" H 3000 5750 50 0000 R CNN +F 2 "" H 3250 5700 29 0000 C CNN +F 3 "" H 3050 5600 60 0000 C CNN + 1 3050 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 4500 3150 4800 +Wire Wire Line + 3150 5200 3150 5400 +Wire Wire Line + 2750 5000 4500 5000 +Wire Wire Line + 2750 5000 2750 4700 +Wire Wire Line + 2750 4700 3150 4700 +Connection ~ 3150 4700 +Wire Wire Line + 2850 5600 2850 5350 +Wire Wire Line + 2850 5350 3150 5350 +Connection ~ 3150 5350 +Wire Wire Line + 1750 3800 1750 6000 +Wire Wire Line + 1250 6000 7250 6000 +Wire Wire Line + 3150 6000 3150 5800 +Wire Wire Line + 2350 3800 2350 6000 +Connection ~ 2350 6000 +Wire Wire Line + 1450 1800 1250 1800 +Wire Wire Line + 1250 1800 1250 6000 +Connection ~ 1750 6000 +$Comp +L zener U3 +U 1 1 666EB6D2 +P 5650 1650 +F 0 "U3" H 5600 1550 60 0000 C CNN +F 1 "zener" H 5650 1750 60 0000 C CNN +F 2 "" H 5700 1650 60 0000 C CNN +F 3 "" H 5700 1650 60 0000 C CNN + 1 5650 1650 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5650 1300 5650 1350 +Connection ~ 3400 1300 +$Comp +L resistor R10 +U 1 1 666EB6D3 +P 5600 2000 +F 0 "R10" H 5650 2130 50 0000 C CNN +F 1 "5k" H 5650 1950 50 0000 C CNN +F 2 "" H 5650 1980 30 0000 C CNN +F 3 "" V 5650 2050 30 0000 C CNN + 1 5600 2000 + 0 1 1 0 +$EndComp +$Comp +L zener U4 +U 1 1 666EB6D4 +P 5650 2700 +F 0 "U4" H 5600 2600 60 0000 C CNN +F 1 "zener" H 5650 2800 60 0000 C CNN +F 2 "" H 5700 2700 60 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 0 1 -1 0 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 666EB6D5 +P 6250 2350 +F 0 "Q15" H 6150 2400 50 0000 R CNN +F 1 "eSim_NPN" H 6200 2500 50 0000 R CNN +F 2 "" H 6450 2450 29 0000 C CNN +F 3 "" H 6250 2350 60 0000 C CNN + 1 6250 2350 + 1 0 0 -1 +$EndComp +Connection ~ 5650 1300 +Wire Wire Line + 5650 1900 5650 1850 +Wire Wire Line + 6350 1300 6350 2150 +Wire Wire Line + 3600 2350 6050 2350 +Wire Wire Line + 3600 2350 3600 2200 +$Comp +L eSim_NPN Q9 +U 1 1 666EB6D6 +P 4150 4650 +F 0 "Q9" H 4050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 4100 4800 50 0000 R CNN +F 2 "" H 4350 4750 29 0000 C CNN +F 3 "" H 4150 4650 60 0000 C CNN + 1 4150 4650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 666EB6D7 +P 3650 3400 +F 0 "Q8" H 3550 3450 50 0000 R CNN +F 1 "eSim_PNP" H 3600 3550 50 0000 R CNN +F 2 "" H 3850 3500 29 0000 C CNN +F 3 "" H 3650 3400 60 0000 C CNN + 1 3650 3400 + 1 0 0 1 +$EndComp +Wire Wire Line + 3750 3200 3750 3000 +Wire Wire Line + 3750 3000 3150 3000 +Connection ~ 3150 3000 +Wire Wire Line + 3450 3400 3150 3400 +Connection ~ 3150 3400 +$Comp +L resistor R5 +U 1 1 666EB6D8 +P 3700 5000 +F 0 "R5" H 3750 5130 50 0000 C CNN +F 1 "7.8k" H 3750 4950 50 0000 C CNN +F 2 "" H 3750 4980 30 0000 C CNN +F 3 "" V 3750 5050 30 0000 C CNN + 1 3700 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 3750 3600 3750 4900 +Wire Wire Line + 3750 6000 3750 5200 +Connection ~ 3150 6000 +Wire Wire Line + 3950 4650 3750 4650 +Connection ~ 3750 4650 +Wire Wire Line + 4250 4450 4250 2350 +Connection ~ 4250 2350 +Wire Wire Line + 4250 6000 4250 4850 +Connection ~ 3750 6000 +Wire Wire Line + 5650 2400 5650 2200 +$Comp +L eSim_NPN Q16 +U 1 1 666EB6D9 +P 7150 2700 +F 0 "Q16" H 7050 2750 50 0000 R CNN +F 1 "eSim_NPN" H 7100 2850 50 0000 R CNN +F 2 "" H 7350 2800 29 0000 C CNN +F 3 "" H 7150 2700 60 0000 C CNN + 1 7150 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7250 1300 7250 2500 +Connection ~ 6350 1300 +Wire Wire Line + 6350 2550 6350 2700 +Wire Wire Line + 6350 2700 6950 2700 +$Comp +L eSim_NPN Q12 +U 1 1 666EB6DA +P 4750 4000 +F 0 "Q12" H 4650 4050 50 0000 R CNN +F 1 "eSim_NPN" H 4700 4150 50 0000 R CNN +F 2 "" H 4950 4100 29 0000 C CNN +F 3 "" H 4750 4000 60 0000 C CNN + 1 4750 4000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 666EB6DB +P 4050 3950 +F 0 "R6" H 4100 4080 50 0000 C CNN +F 1 "13k" H 4100 3900 50 0000 C CNN +F 2 "" H 4100 3930 30 0000 C CNN +F 3 "" V 4100 4000 30 0000 C CNN + 1 4050 3950 + -1 0 0 1 +$EndComp +Wire Wire Line + 4550 4000 4150 4000 +Wire Wire Line + 3850 4000 3150 4000 +Connection ~ 3150 4000 +Wire Wire Line + 4850 3800 4850 3100 +Wire Wire Line + 4850 3100 6450 3100 +Wire Wire Line + 6450 3100 6450 2700 +Connection ~ 6450 2700 +$Comp +L eSim_PNP Q11 +U 1 1 666EB6DC +P 4750 2800 +F 0 "Q11" H 4650 2850 50 0000 R CNN +F 1 "eSim_PNP" H 4700 2950 50 0000 R CNN +F 2 "" H 4950 2900 29 0000 C CNN +F 3 "" H 4750 2800 60 0000 C CNN + 1 4750 2800 + -1 0 0 1 +$EndComp +Connection ~ 4250 6000 +$Comp +L resistor R8 +U 1 1 666EB6DD +P 5000 2500 +F 0 "R8" H 5050 2630 50 0000 C CNN +F 1 "5.76k" H 5050 2450 50 0000 C CNN +F 2 "" H 5050 2480 30 0000 C CNN +F 3 "" V 5050 2550 30 0000 C CNN + 1 5000 2500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4950 6000 4950 3000 +$Comp +L eSim_NPN Q14 +U 1 1 666EB6DE +P 5450 4000 +F 0 "Q14" H 5350 4050 50 0000 R CNN +F 1 "eSim_NPN" H 5400 4150 50 0000 R CNN +F 2 "" H 5650 4100 29 0000 C CNN +F 3 "" H 5450 4000 60 0000 C CNN + 1 5450 4000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4850 4200 5350 4200 +$Comp +L eSim_NPN Q10 +U 1 1 666EB6DF +P 4700 5000 +F 0 "Q10" H 4600 5050 50 0000 R CNN +F 1 "eSim_NPN" H 4650 5150 50 0000 R CNN +F 2 "" H 4900 5100 29 0000 C CNN +F 3 "" H 4700 5000 60 0000 C CNN + 1 4700 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 4800 4900 4800 +Wire Wire Line + 4900 4800 4900 4200 +Connection ~ 4900 4200 +Connection ~ 2850 5000 +$Comp +L resistor R7 +U 1 1 666EB6E0 +P 4750 5500 +F 0 "R7" H 4800 5630 50 0000 C CNN +F 1 "2.84k" H 4800 5450 50 0000 C CNN +F 2 "" H 4800 5480 30 0000 C CNN +F 3 "" V 4800 5550 30 0000 C CNN + 1 4750 5500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4800 5400 4800 5200 +Wire Wire Line + 4800 5700 4800 6000 +Connection ~ 4800 6000 +$Comp +L resistor R9 +U 1 1 666EB6E1 +P 5200 3350 +F 0 "R9" H 5250 3480 50 0000 C CNN +F 1 "100" H 5250 3300 50 0000 C CNN +F 2 "" H 5250 3330 30 0000 C CNN +F 3 "" V 5250 3400 30 0000 C CNN + 1 5200 3350 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 666EB6E2 +P 7200 3200 +F 0 "R14" H 7250 3330 50 0000 C CNN +F 1 "1.9" H 7250 3150 50 0000 C CNN +F 2 "" H 7250 3180 30 0000 C CNN +F 3 "" V 7250 3250 30 0000 C CNN + 1 7200 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 666EB6E3 +P 6700 3200 +F 0 "R13" H 6750 3330 50 0000 C CNN +F 1 "2.5k" H 6750 3150 50 0000 C CNN +F 2 "" H 6750 3180 30 0000 C CNN +F 3 "" V 6750 3250 30 0000 C CNN + 1 6700 3200 + 0 1 1 0 +$EndComp +Wire Wire Line + 6750 3100 6750 2700 +Connection ~ 6750 2700 +Wire Wire Line + 7250 2900 7250 3100 +$Comp +L resistor R11 +U 1 1 666EB6E4 +P 6150 2950 +F 0 "R11" H 6200 3080 50 0000 C CNN +F 1 "100" H 6200 2900 50 0000 C CNN +F 2 "" H 6200 2930 30 0000 C CNN +F 3 "" V 6200 3000 30 0000 C CNN + 1 6150 2950 + -1 0 0 1 +$EndComp +Wire Wire Line + 5550 3000 5950 3000 +Wire Wire Line + 6250 3000 7250 3000 +Connection ~ 7250 3000 +Wire Wire Line + 5250 3650 7950 3650 +Wire Wire Line + 7250 3400 7250 3900 +Wire Wire Line + 6750 3400 6750 3650 +Connection ~ 6750 3650 +$Comp +L resistor R15 +U 1 1 666EB6E5 +P 7200 4000 +F 0 "R15" H 7250 4130 50 0000 C CNN +F 1 "1.5k" H 7250 3950 50 0000 C CNN +F 2 "" H 7250 3980 30 0000 C CNN +F 3 "" V 7250 4050 30 0000 C CNN + 1 7200 4000 + 0 1 1 0 +$EndComp +Connection ~ 7250 3650 +Wire Wire Line + 6900 4000 6900 4450 +Wire Wire Line + 6900 4450 7250 4450 +Wire Wire Line + 7250 4200 7250 5100 +$Comp +L resistor R12 +U 1 1 666EB6E6 +P 6450 3950 +F 0 "R12" H 6500 4080 50 0000 C CNN +F 1 "15k" H 6500 3900 50 0000 C CNN +F 2 "" H 6500 3930 30 0000 C CNN +F 3 "" V 6500 4000 30 0000 C CNN + 1 6450 3950 + -1 0 0 1 +$EndComp +Wire Wire Line + 6550 4000 6900 4000 +Wire Wire Line + 5650 4000 6250 4000 +$Comp +L capacitor_polarised C1 +U 1 1 666EB6E7 +P 5850 3750 +F 0 "C1" H 5875 3850 50 0000 L CNN +F 1 "5u" H 5875 3650 50 0000 L CNN +F 2 "" H 5850 3750 50 0001 C CNN +F 3 "" H 5850 3750 50 0001 C CNN + 1 5850 3750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6000 3750 6100 3750 +Wire Wire Line + 6100 3750 6100 4000 +Connection ~ 6100 4000 +Wire Wire Line + 5700 3750 5350 3750 +Connection ~ 5350 3750 +$Comp +L resistor R16 +U 1 1 666EB6E8 +P 7200 5200 +F 0 "R16" H 7250 5330 50 0000 C CNN +F 1 "2.23k" H 7250 5150 50 0000 C CNN +F 2 "" H 7250 5180 30 0000 C CNN +F 3 "" V 7250 5250 30 0000 C CNN + 1 7200 5200 + 0 1 1 0 +$EndComp +Connection ~ 7250 4450 +Wire Wire Line + 7250 5400 7250 6250 +Connection ~ 4950 6000 +Wire Wire Line + 5350 3700 5350 3800 +Wire Wire Line + 5050 3700 5350 3700 +Wire Wire Line + 5050 2700 5050 3700 +Wire Wire Line + 5050 2400 5050 2350 +Connection ~ 5050 2350 +Wire Wire Line + 4950 2800 5050 2800 +Connection ~ 5050 2800 +Wire Wire Line + 4650 2600 4650 2350 +Connection ~ 4650 2350 +Wire Wire Line + 4950 3000 4650 3000 +$Comp +L eSim_NPN Q13 +U 1 1 666EB6E9 +P 5350 3000 +F 0 "Q13" H 5250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 5300 3150 50 0000 R CNN +F 2 "" H 5550 3100 29 0000 C CNN +F 3 "" H 5350 3000 60 0000 C CNN + 1 5350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5250 2800 5250 2350 +Connection ~ 5250 2350 +Wire Wire Line + 5650 2900 5650 3000 +Connection ~ 5650 3000 +Wire Wire Line + 5250 3250 5250 3200 +Wire Wire Line + 5250 3550 5250 3650 +Connection ~ 7250 1300 +Connection ~ 7250 6000 +Wire Wire Line + 7950 3650 7950 3550 +$Comp +L PORT U5 +U 1 1 666EBC17 +P 7850 1300 +F 0 "U5" H 7900 1400 30 0000 C CNN +F 1 "PORT" H 7850 1300 30 0000 C CNN +F 2 "" H 7850 1300 60 0000 C CNN +F 3 "" H 7850 1300 60 0000 C CNN + 1 7850 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 2 1 666EC091 +P 8200 3550 +F 0 "U5" H 8250 3650 30 0000 C CNN +F 1 "PORT" H 8200 3550 30 0000 C CNN +F 2 "" H 8200 3550 60 0000 C CNN +F 3 "" H 8200 3550 60 0000 C CNN + 2 8200 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 3 1 666EC2BD +P 7250 6500 +F 0 "U5" H 7300 6600 30 0000 C CNN +F 1 "PORT" H 7250 6500 30 0000 C CNN +F 2 "" H 7250 6500 60 0000 C CNN +F 3 "" H 7250 6500 60 0000 C CNN + 3 7250 6500 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sub b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sub new file mode 100644 index 00000000..c8bd59c9 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sub @@ -0,0 +1,59 @@ +* Subcircuit LM140L_IC +.subckt LM140L_IC net-_j1-pad1_ net-_r13-pad2_ net-_j1-pad2_ +* d:\fossee\esim\library\subcircuitlibrary\lm140l_ic\lm140l_ic.cir +.include NJF.lib +.include NPN.lib +.include PNP.lib +r1 net-_j1-pad1_ net-_q2-pad3_ 418 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +* u1 net-_j1-pad2_ net-_j1-pad3_ zener +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ Q2N2907A +* u2 net-_j1-pad2_ net-_q1-pad3_ zener +q3 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q7 net-_q11-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q4 net-_q1-pad1_ net-_q1-pad3_ net-_q4-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_q8-pad2_ 576 +r3 net-_q8-pad2_ net-_r3-pad2_ 3.41k +r4 net-_r3-pad2_ net-_q10-pad2_ 3.89k +q5 net-_q10-pad2_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q5-pad3_ net-_j1-pad2_ Q2N2222 +* u3 net-_r10-pad1_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 5k +* u4 net-_q13-pad2_ net-_r10-pad2_ zener +q15 net-_j1-pad1_ net-_q11-pad3_ net-_q12-pad1_ Q2N2222 +q9 net-_q11-pad3_ net-_q8-pad1_ net-_j1-pad2_ Q2N2222 +q8 net-_q8-pad1_ net-_q8-pad2_ net-_q4-pad3_ Q2N2907A +r5 net-_q8-pad1_ net-_j1-pad2_ 7.8k +q16 net-_j1-pad1_ net-_q12-pad1_ net-_q16-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q10-pad1_ Q2N2222 +r6 net-_q12-pad2_ net-_r3-pad2_ 13k +q11 net-_j1-pad2_ net-_c1-pad1_ net-_q11-pad3_ Q2N2907A +r8 net-_q11-pad3_ net-_c1-pad1_ 5.76k +q14 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q10-pad3_ net-_j1-pad2_ 2.84k +r9 net-_q13-pad3_ net-_r13-pad2_ 100 +r14 net-_q16-pad3_ net-_r13-pad2_ 1.9 +r13 net-_q12-pad1_ net-_r13-pad2_ 2.5k +r11 net-_q16-pad3_ net-_q13-pad2_ 100 +r15 net-_r13-pad2_ net-_r12-pad1_ 1.5k +r12 net-_r12-pad1_ net-_c1-pad2_ 15k +c1 net-_c1-pad1_ net-_c1-pad2_ 5u +r16 net-_r12-pad1_ net-_j1-pad2_ 2.23k +q13 net-_q11-pad3_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +a1 net-_j1-pad2_ net-_j1-pad3_ u1 +a2 net-_j1-pad2_ net-_q1-pad3_ u2 +a3 net-_r10-pad1_ net-_j1-pad1_ u3 +a4 net-_q13-pad2_ net-_r10-pad2_ u4 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM140L_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC_Previous_Values.xml b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC_Previous_Values.xml new file mode 100644 index 00000000..c58cd7ba --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)" /><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u3><u4 name="type">zener<field16 name="Enter Breakdown Voltage (default=5.6)" /><field17 name="Enter Breakdown Current (default=2.0e-2)" /><field18 name="Enter Saturation Current (default=1.0e-12)" /><field19 name="Enter Forward Emission Coefficient (default=1.0)" /><field20 name="Enter Switch for Limiting (default=FALSE)" /></u4></model><devicemodel><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM140L_sub/NJF.lib b/library/SubcircuitLibrary/LM140L_sub/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM140L_sub/NPN.lib b/library/SubcircuitLibrary/LM140L_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM140L_sub/PNP.lib b/library/SubcircuitLibrary/LM140L_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM140L_sub/analysis b/library/SubcircuitLibrary/LM140L_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM143_sub/D.lib b/library/SubcircuitLibrary/LM143_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC-cache.lib b/library/SubcircuitLibrary/LM143_sub/LM143_IC-cache.lib new file mode 100644 index 00000000..5e755436 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC-cache.lib @@ -0,0 +1,183 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir new file mode 100644 index 00000000..a903cdea --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir @@ -0,0 +1,42 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LM143_IC\LM143_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 18:26:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +I2 Net-_I2-Pad1_ Net-_I2-Pad2_ 80u +I3 Net-_I2-Pad1_ Net-_I3-Pad2_ 80u +I4 Net-_I2-Pad1_ Net-_I4-Pad2_ 80u +Q1 Net-_I2-Pad2_ Net-_Q1-Pad2_ Net-_I1-Pad1_ eSim_NPN +Q2 Net-_I1-Pad2_ Net-_I1-Pad1_ Net-_I2-Pad2_ eSim_PNP +Q6 Net-_I1-Pad2_ Net-_I5-Pad1_ Net-_I4-Pad2_ eSim_PNP +Q8 Net-_I4-Pad2_ Net-_Q8-Pad2_ Net-_I5-Pad1_ eSim_NPN +R2 Net-_Q3-Pad3_ Net-_I3-Pad2_ 5.6k +R3 Net-_I3-Pad2_ Net-_Q7-Pad3_ 5.6k +Q3 Net-_Q3-Pad1_ Net-_I1-Pad1_ Net-_Q3-Pad3_ eSim_PNP +Q7 Net-_C1-Pad2_ Net-_I5-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q4 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_I1-Pad2_ eSim_NPN +Q5 Net-_C1-Pad2_ Net-_Q3-Pad1_ Net-_I1-Pad2_ eSim_NPN +I1 Net-_I1-Pad1_ Net-_I1-Pad2_ 20u +I5 Net-_I5-Pad1_ Net-_I1-Pad2_ 20u +I6 Net-_I2-Pad1_ Net-_D1-Pad1_ 400u +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D2-Pad2_ Net-_C1-Pad1_ eSim_Diode +Q11 Net-_C1-Pad1_ Net-_Q11-Pad2_ Net-_Q10-Pad1_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 27p +Q9 Net-_I2-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_I1-Pad2_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_I1-Pad2_ 39k +v1 Net-_Q11-Pad2_ Net-_I1-Pad2_ 2 +Q15 Net-_I2-Pad1_ Net-_I7-Pad2_ Net-_Q13-Pad1_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_D1-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q14 Net-_I1-Pad2_ Net-_Q12-Pad3_ Net-_Q13-Pad3_ eSim_PNP +Q12 Net-_I1-Pad2_ Net-_C1-Pad1_ Net-_Q12-Pad3_ eSim_PNP +I7 Net-_I2-Pad1_ Net-_I7-Pad2_ 400u +v2 Net-_I7-Pad2_ Net-_Q13-Pad3_ 3.5 +U1 Net-_Q1-Pad2_ Net-_Q8-Pad2_ Net-_I1-Pad2_ Net-_Q13-Pad3_ Net-_I2-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir.out b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir.out new file mode 100644 index 00000000..4cac6cfc --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir.out @@ -0,0 +1,46 @@ +* d:\fossee\esim\library\subcircuitlibrary\lm143_ic\lm143_ic.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +i2 net-_i2-pad1_ net-_i2-pad2_ 80u +i3 net-_i2-pad1_ net-_i3-pad2_ 80u +i4 net-_i2-pad1_ net-_i4-pad2_ 80u +q1 net-_i2-pad2_ net-_q1-pad2_ net-_i1-pad1_ Q2N2222 +q2 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2907A +q6 net-_i1-pad2_ net-_i5-pad1_ net-_i4-pad2_ Q2N2907A +q8 net-_i4-pad2_ net-_q8-pad2_ net-_i5-pad1_ Q2N2222 +r2 net-_q3-pad3_ net-_i3-pad2_ 5.6k +r3 net-_i3-pad2_ net-_q7-pad3_ 5.6k +q3 net-_q3-pad1_ net-_i1-pad1_ net-_q3-pad3_ Q2N2907A +q7 net-_c1-pad2_ net-_i5-pad1_ net-_q7-pad3_ Q2N2907A +q4 net-_q3-pad1_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +q5 net-_c1-pad2_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +i1 net-_i1-pad1_ net-_i1-pad2_ 20u +i5 net-_i5-pad1_ net-_i1-pad2_ 20u +i6 net-_i2-pad1_ net-_d1-pad1_ 400u +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_c1-pad1_ 1N4148 +q11 net-_c1-pad1_ net-_q11-pad2_ net-_q10-pad1_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 27p +q9 net-_i2-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_i1-pad2_ Q2N2222 +r5 net-_q10-pad2_ net-_i1-pad2_ 39k +v1 net-_q11-pad2_ net-_i1-pad2_ 2 +q15 net-_i2-pad1_ net-_i7-pad2_ net-_q13-pad1_ Q2N2222 +q13 net-_q13-pad1_ net-_d1-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_i1-pad2_ net-_q12-pad3_ net-_q13-pad3_ Q2N2907A +q12 net-_i1-pad2_ net-_c1-pad1_ net-_q12-pad3_ Q2N2907A +i7 net-_i2-pad1_ net-_i7-pad2_ 400u +v2 net-_i7-pad2_ net-_q13-pad3_ 3.5 +* u1 net-_q1-pad2_ net-_q8-pad2_ net-_i1-pad2_ net-_q13-pad3_ net-_i2-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.pro b/library/SubcircuitLibrary/LM143_sub/LM143_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.sch b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sch new file mode 100644 index 00000000..a86aa174 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sch @@ -0,0 +1,664 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM143_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 23622 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dc I2 +U 1 1 668A62E5 +P 8200 5700 +F 0 "I2" H 8000 5800 60 0000 C CNN +F 1 "80u" H 8000 5650 60 0000 C CNN +F 2 "R1" H 7900 5700 60 0000 C CNN +F 3 "" H 8200 5700 60 0000 C CNN + 1 8200 5700 + -1 0 0 -1 +$EndComp +$Comp +L dc I3 +U 1 1 668A62E6 +P 9000 5750 +F 0 "I3" H 8800 5850 60 0000 C CNN +F 1 "80u" H 8800 5700 60 0000 C CNN +F 2 "R1" H 8700 5750 60 0000 C CNN +F 3 "" H 9000 5750 60 0000 C CNN + 1 9000 5750 + -1 0 0 -1 +$EndComp +$Comp +L dc I4 +U 1 1 668A62E7 +P 9800 5700 +F 0 "I4" H 9600 5800 60 0000 C CNN +F 1 "80u" H 9600 5650 60 0000 C CNN +F 2 "R1" H 9500 5700 60 0000 C CNN +F 3 "" H 9800 5700 60 0000 C CNN + 1 9800 5700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 668A62E8 +P 7400 6600 +F 0 "Q1" H 7300 6650 50 0000 R CNN +F 1 "eSim_NPN" H 7350 6750 50 0000 R CNN +F 2 "" H 7600 6700 29 0000 C CNN +F 3 "" H 7400 6600 60 0000 C CNN + 1 7400 6600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 668A62E9 +P 8100 6850 +F 0 "Q2" H 8000 6900 50 0000 R CNN +F 1 "eSim_PNP" H 8050 7000 50 0000 R CNN +F 2 "" H 8300 6950 29 0000 C CNN +F 3 "" H 8100 6850 60 0000 C CNN + 1 8100 6850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 668A62EA +P 9900 6850 +F 0 "Q6" H 9800 6900 50 0000 R CNN +F 1 "eSim_PNP" H 9850 7000 50 0000 R CNN +F 2 "" H 10100 6950 29 0000 C CNN +F 3 "" H 9900 6850 60 0000 C CNN + 1 9900 6850 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 668A62EB +P 10900 6550 +F 0 "Q8" H 10800 6600 50 0000 R CNN +F 1 "eSim_NPN" H 10850 6700 50 0000 R CNN +F 2 "" H 11100 6650 29 0000 C CNN +F 3 "" H 10900 6550 60 0000 C CNN + 1 10900 6550 + -1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 668A62EC +P 8600 7500 +F 0 "R2" H 8650 7630 50 0000 C CNN +F 1 "5.6k" H 8650 7450 50 0000 C CNN +F 2 "" H 8650 7480 30 0000 C CNN +F 3 "" V 8650 7550 30 0000 C CNN + 1 8600 7500 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 668A62ED +P 9250 7500 +F 0 "R3" H 9300 7630 50 0000 C CNN +F 1 "5.6k" H 9300 7450 50 0000 C CNN +F 2 "" H 9300 7480 30 0000 C CNN +F 3 "" V 9300 7550 30 0000 C CNN + 1 9250 7500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 668A62EE +P 8200 7650 +F 0 "Q3" H 8100 7700 50 0000 R CNN +F 1 "eSim_PNP" H 8150 7800 50 0000 R CNN +F 2 "" H 8400 7750 29 0000 C CNN +F 3 "" H 8200 7650 60 0000 C CNN + 1 8200 7650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 668A62EF +P 9900 7650 +F 0 "Q7" H 9800 7700 50 0000 R CNN +F 1 "eSim_PNP" H 9850 7800 50 0000 R CNN +F 2 "" H 10100 7750 29 0000 C CNN +F 3 "" H 9900 7650 60 0000 C CNN + 1 9900 7650 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 668A62F0 +P 8400 8750 +F 0 "Q4" H 8300 8800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 8900 50 0000 R CNN +F 2 "" H 8600 8850 29 0000 C CNN +F 3 "" H 8400 8750 60 0000 C CNN + 1 8400 8750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 668A62F1 +P 9700 8750 +F 0 "Q5" H 9600 8800 50 0000 R CNN +F 1 "eSim_NPN" H 9650 8900 50 0000 R CNN +F 2 "" H 9900 8850 29 0000 C CNN +F 3 "" H 9700 8750 60 0000 C CNN + 1 9700 8750 + 1 0 0 -1 +$EndComp +$Comp +L dc I1 +U 1 1 668A62F2 +P 7650 8350 +F 0 "I1" H 7450 8450 60 0000 C CNN +F 1 "20u" H 7450 8300 60 0000 C CNN +F 2 "R1" H 7350 8350 60 0000 C CNN +F 3 "" H 7650 8350 60 0000 C CNN + 1 7650 8350 + -1 0 0 -1 +$EndComp +$Comp +L dc I5 +U 1 1 668A62F3 +P 10400 8500 +F 0 "I5" H 10200 8600 60 0000 C CNN +F 1 "20u" H 10200 8450 60 0000 C CNN +F 2 "R1" H 10100 8500 60 0000 C CNN +F 3 "" H 10400 8500 60 0000 C CNN + 1 10400 8500 + -1 0 0 -1 +$EndComp +$Comp +L dc I6 +U 1 1 668A62F4 +P 12600 5800 +F 0 "I6" H 12400 5900 60 0000 C CNN +F 1 "400u" H 12400 5750 60 0000 C CNN +F 2 "R1" H 12300 5800 60 0000 C CNN +F 3 "" H 12600 5800 60 0000 C CNN + 1 12600 5800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 668A62F5 +P 12600 6800 +F 0 "D1" H 12600 6900 50 0000 C CNN +F 1 "eSim_Diode" H 12600 6700 50 0000 C CNN +F 2 "" H 12600 6800 60 0000 C CNN +F 3 "" H 12600 6800 60 0000 C CNN + 1 12600 6800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 668A62F6 +P 12600 7300 +F 0 "D2" H 12600 7400 50 0000 C CNN +F 1 "eSim_Diode" H 12600 7200 50 0000 C CNN +F 2 "" H 12600 7300 60 0000 C CNN +F 3 "" H 12600 7300 60 0000 C CNN + 1 12600 7300 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 668A62F7 +P 12600 7800 +F 0 "D3" H 12600 7900 50 0000 C CNN +F 1 "eSim_Diode" H 12600 7700 50 0000 C CNN +F 2 "" H 12600 7800 60 0000 C CNN +F 3 "" H 12600 7800 60 0000 C CNN + 1 12600 7800 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 668A62F8 +P 12700 8550 +F 0 "Q11" H 12600 8600 50 0000 R CNN +F 1 "eSim_NPN" H 12650 8700 50 0000 R CNN +F 2 "" H 12900 8650 29 0000 C CNN +F 3 "" H 12700 8550 60 0000 C CNN + 1 12700 8550 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 668A62F9 +P 12050 8250 +F 0 "C1" H 12075 8350 50 0000 L CNN +F 1 "27p" H 12075 8150 50 0000 L CNN +F 2 "" H 12088 8100 30 0000 C CNN +F 3 "" H 12050 8250 60 0000 C CNN + 1 12050 8250 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 668A62FA +P 11600 9000 +F 0 "Q9" H 11500 9050 50 0000 R CNN +F 1 "eSim_NPN" H 11550 9150 50 0000 R CNN +F 2 "" H 11800 9100 29 0000 C CNN +F 3 "" H 11600 9000 60 0000 C CNN + 1 11600 9000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 668A62FB +P 12500 9000 +F 0 "Q10" H 12400 9050 50 0000 R CNN +F 1 "eSim_NPN" H 12450 9150 50 0000 R CNN +F 2 "" H 12700 9100 29 0000 C CNN +F 3 "" H 12500 9000 60 0000 C CNN + 1 12500 9000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 668A62FC +P 11950 9500 +F 0 "R5" H 12000 9630 50 0000 C CNN +F 1 "39k" H 12000 9450 50 0000 C CNN +F 2 "" H 12000 9480 30 0000 C CNN +F 3 "" V 12000 9550 30 0000 C CNN + 1 11950 9500 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 668A62FD +P 13150 9150 +F 0 "v1" H 12950 9250 60 0000 C CNN +F 1 "2" H 12950 9100 60 0000 C CNN +F 2 "R1" H 12850 9150 60 0000 C CNN +F 3 "" H 13150 9150 60 0000 C CNN + 1 13150 9150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 668A62FE +P 14100 5550 +F 0 "Q15" H 14000 5600 50 0000 R CNN +F 1 "eSim_NPN" H 14050 5700 50 0000 R CNN +F 2 "" H 14300 5650 29 0000 C CNN +F 3 "" H 14100 5550 60 0000 C CNN + 1 14100 5550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 668A62FF +P 13900 6200 +F 0 "Q13" H 13800 6250 50 0000 R CNN +F 1 "eSim_NPN" H 13850 6350 50 0000 R CNN +F 2 "" H 14100 6300 29 0000 C CNN +F 3 "" H 13900 6200 60 0000 C CNN + 1 13900 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 668A6300 +P 13900 6700 +F 0 "Q14" H 13800 6750 50 0000 R CNN +F 1 "eSim_PNP" H 13850 6850 50 0000 R CNN +F 2 "" H 14100 6800 29 0000 C CNN +F 3 "" H 13900 6700 60 0000 C CNN + 1 13900 6700 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 668A6301 +P 13450 6950 +F 0 "Q12" H 13350 7000 50 0000 R CNN +F 1 "eSim_PNP" H 13400 7100 50 0000 R CNN +F 2 "" H 13650 7050 29 0000 C CNN +F 3 "" H 13450 6950 60 0000 C CNN + 1 13450 6950 + 1 0 0 1 +$EndComp +$Comp +L dc I7 +U 1 1 668A6302 +P 14750 5700 +F 0 "I7" H 14550 5800 60 0000 C CNN +F 1 "400u" H 14550 5650 60 0000 C CNN +F 2 "R1" H 14450 5700 60 0000 C CNN +F 3 "" H 14750 5700 60 0000 C CNN + 1 14750 5700 + -1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 668A6303 +P 14750 6950 +F 0 "v2" H 14550 7050 60 0000 C CNN +F 1 "3.5" H 14550 6900 60 0000 C CNN +F 2 "R1" H 14450 6950 60 0000 C CNN +F 3 "" H 14750 6950 60 0000 C CNN + 1 14750 6950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 6150 8200 6650 +Wire Wire Line + 7500 6800 7500 6850 +Wire Wire Line + 7500 6850 7900 6850 +Wire Wire Line + 7500 6400 7500 6350 +Wire Wire Line + 7500 6350 8200 6350 +Connection ~ 8200 6350 +Wire Wire Line + 9800 6150 9800 6650 +Connection ~ 9800 6250 +Wire Wire Line + 10800 6850 10800 6750 +Wire Wire Line + 10100 6850 10800 6850 +Wire Wire Line + 10800 6350 9850 6350 +Wire Wire Line + 9850 6350 9850 6250 +Wire Wire Line + 9850 6250 9800 6250 +Wire Wire Line + 8200 5250 14750 5250 +Wire Wire Line + 9000 5300 9000 5250 +Connection ~ 9000 5250 +Wire Wire Line + 8800 7450 9150 7450 +Wire Wire Line + 8300 7450 8500 7450 +Wire Wire Line + 9800 7450 9450 7450 +Wire Wire Line + 8000 7650 7650 7650 +Connection ~ 7650 6850 +Wire Wire Line + 8300 7850 8300 8550 +Wire Wire Line + 8600 8750 9500 8750 +Wire Wire Line + 9800 8550 9800 7850 +Wire Wire Line + 7650 6850 7650 7900 +Connection ~ 7650 7650 +Wire Wire Line + 7650 8800 7650 9950 +Wire Wire Line + 9800 9950 9800 8950 +Wire Wire Line + 8300 8950 8300 9950 +Wire Wire Line + 8300 8400 8900 8400 +Wire Wire Line + 8900 8400 8900 8750 +Connection ~ 8900 8750 +Connection ~ 8300 8400 +Wire Wire Line + 9000 6200 9000 7450 +Connection ~ 9000 7450 +Wire Wire Line + 10400 6850 10400 8050 +Connection ~ 10400 6850 +Wire Wire Line + 10100 7650 10400 7650 +Connection ~ 10400 7650 +Wire Wire Line + 10400 9950 10400 8950 +Wire Wire Line + 12600 5250 12600 5350 +Connection ~ 9800 5250 +Wire Wire Line + 12600 6250 12600 6650 +Wire Wire Line + 12600 7150 12600 6950 +Wire Wire Line + 12600 7650 12600 7450 +Wire Wire Line + 12600 7950 12600 8350 +Wire Wire Line + 12200 8250 12600 8250 +Connection ~ 12600 8250 +Wire Wire Line + 11900 8250 11150 8250 +Wire Wire Line + 11150 8250 11150 9000 +Wire Wire Line + 9950 9000 11400 9000 +Wire Wire Line + 12600 8800 12600 8750 +Wire Wire Line + 12300 9300 12300 9000 +Wire Wire Line + 11700 9300 12300 9300 +Wire Wire Line + 11700 9300 11700 9200 +Wire Wire Line + 12000 9400 12000 9300 +Connection ~ 12000 9300 +Wire Wire Line + 13150 8700 13150 8550 +Wire Wire Line + 13150 8550 12900 8550 +Wire Wire Line + 7650 9950 14000 9950 +Wire Wire Line + 13150 9950 13150 9600 +Wire Wire Line + 12000 9700 12000 9950 +Connection ~ 12000 9950 +Connection ~ 10400 9950 +Connection ~ 9800 9950 +Connection ~ 8300 9950 +Wire Wire Line + 14000 5250 14000 5350 +Connection ~ 12600 5250 +Wire Wire Line + 14000 6000 14000 5750 +Wire Wire Line + 13700 6200 12800 6200 +Wire Wire Line + 12800 6200 12800 6400 +Wire Wire Line + 12800 6400 12600 6400 +Connection ~ 12600 6400 +Wire Wire Line + 14000 6400 14000 6500 +Wire Wire Line + 13550 6750 13550 6700 +Wire Wire Line + 13550 6700 13700 6700 +Wire Wire Line + 13250 6950 12900 6950 +Wire Wire Line + 12900 6950 12900 8100 +Wire Wire Line + 12900 8100 12600 8100 +Connection ~ 12600 8100 +Wire Wire Line + 14000 9950 14000 6900 +Connection ~ 13150 9950 +Wire Wire Line + 13550 7150 13550 7200 +Wire Wire Line + 13550 7200 14000 7200 +Connection ~ 14000 7200 +Connection ~ 14000 5250 +Wire Wire Line + 14300 5550 14300 6300 +Wire Wire Line + 14300 6300 14750 6300 +Wire Wire Line + 14750 6150 14750 6500 +Connection ~ 14750 6300 +Wire Wire Line + 14000 6450 14350 6450 +Wire Wire Line + 14350 6450 14350 7450 +Connection ~ 14000 6450 +Wire Wire Line + 11600 4850 11600 5250 +Connection ~ 11600 5250 +Wire Wire Line + 11200 9950 11200 10600 +Connection ~ 11200 9950 +Wire Wire Line + 8200 7050 8200 7250 +Wire Wire Line + 8200 7250 7950 7250 +Wire Wire Line + 7950 7250 7950 10450 +Wire Wire Line + 7950 10450 11200 10450 +Connection ~ 11200 10450 +Wire Wire Line + 9800 7050 10050 7050 +Wire Wire Line + 10050 7050 10050 10350 +Wire Wire Line + 10050 10350 11200 10350 +Connection ~ 11200 10350 +Wire Wire Line + 11700 8800 11700 7900 +Wire Wire Line + 11700 7900 11850 7900 +Wire Wire Line + 12600 9200 12600 9950 +Connection ~ 12600 9950 +Wire Wire Line + 14750 7700 15150 7700 +Wire Wire Line + 9950 9000 9950 8400 +Wire Wire Line + 9950 8400 9800 8400 +Connection ~ 9800 8400 +Connection ~ 11150 9000 +Wire Wire Line + 14350 7450 14750 7450 +Connection ~ 14750 7450 +Wire Wire Line + 11850 7900 11850 5250 +Connection ~ 11850 5250 +Connection ~ 14750 7700 +Wire Wire Line + 14750 7700 14750 7400 +Wire Wire Line + 6450 6600 7200 6600 +$Comp +L PORT U1 +U 1 1 668A67B8 +P 6200 6600 +F 0 "U1" H 6250 6700 30 0000 C CNN +F 1 "PORT" H 6200 6600 30 0000 C CNN +F 2 "" H 6200 6600 60 0000 C CNN +F 3 "" H 6200 6600 60 0000 C CNN + 1 6200 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 668A6ADF +P 11550 6550 +F 0 "U1" H 11600 6650 30 0000 C CNN +F 1 "PORT" H 11550 6550 30 0000 C CNN +F 2 "" H 11550 6550 60 0000 C CNN +F 3 "" H 11550 6550 60 0000 C CNN + 2 11550 6550 + -1 0 0 1 +$EndComp +Wire Wire Line + 11100 6550 11300 6550 +$Comp +L PORT U1 +U 3 1 668A7018 +P 11200 10850 +F 0 "U1" H 11250 10950 30 0000 C CNN +F 1 "PORT" H 11200 10850 30 0000 C CNN +F 2 "" H 11200 10850 60 0000 C CNN +F 3 "" H 11200 10850 60 0000 C CNN + 3 11200 10850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 668A744A +P 11850 4850 +F 0 "U1" H 11900 4950 30 0000 C CNN +F 1 "PORT" H 11850 4850 30 0000 C CNN +F 2 "" H 11850 4850 60 0000 C CNN +F 3 "" H 11850 4850 60 0000 C CNN + 5 11850 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 668A7705 +P 15400 7700 +F 0 "U1" H 15450 7800 30 0000 C CNN +F 1 "PORT" H 15400 7700 30 0000 C CNN +F 2 "" H 15400 7700 60 0000 C CNN +F 3 "" H 15400 7700 60 0000 C CNN + 4 15400 7700 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.sub b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sub new file mode 100644 index 00000000..41b29af7 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sub @@ -0,0 +1,40 @@ +* Subcircuit LM143_IC +.subckt LM143_IC net-_q1-pad2_ net-_q8-pad2_ net-_i1-pad2_ net-_q13-pad3_ net-_i2-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\lm143_ic\lm143_ic.cir +.include NPN.lib +.include PNP.lib +.include D.lib +i2 net-_i2-pad1_ net-_i2-pad2_ 80u +i3 net-_i2-pad1_ net-_i3-pad2_ 80u +i4 net-_i2-pad1_ net-_i4-pad2_ 80u +q1 net-_i2-pad2_ net-_q1-pad2_ net-_i1-pad1_ Q2N2222 +q2 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2907A +q6 net-_i1-pad2_ net-_i5-pad1_ net-_i4-pad2_ Q2N2907A +q8 net-_i4-pad2_ net-_q8-pad2_ net-_i5-pad1_ Q2N2222 +r2 net-_q3-pad3_ net-_i3-pad2_ 5.6k +r3 net-_i3-pad2_ net-_q7-pad3_ 5.6k +q3 net-_q3-pad1_ net-_i1-pad1_ net-_q3-pad3_ Q2N2907A +q7 net-_c1-pad2_ net-_i5-pad1_ net-_q7-pad3_ Q2N2907A +q4 net-_q3-pad1_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +q5 net-_c1-pad2_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +i1 net-_i1-pad1_ net-_i1-pad2_ 20u +i5 net-_i5-pad1_ net-_i1-pad2_ 20u +i6 net-_i2-pad1_ net-_d1-pad1_ 400u +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_c1-pad1_ 1N4148 +q11 net-_c1-pad1_ net-_q11-pad2_ net-_q10-pad1_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 27p +q9 net-_i2-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_i1-pad2_ Q2N2222 +r5 net-_q10-pad2_ net-_i1-pad2_ 39k +v1 net-_q11-pad2_ net-_i1-pad2_ 2 +q15 net-_i2-pad1_ net-_i7-pad2_ net-_q13-pad1_ Q2N2222 +q13 net-_q13-pad1_ net-_d1-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_i1-pad2_ net-_q12-pad3_ net-_q13-pad3_ Q2N2907A +q12 net-_i1-pad2_ net-_c1-pad1_ net-_q12-pad3_ Q2N2907A +i7 net-_i2-pad1_ net-_i7-pad2_ 400u +v2 net-_i7-pad2_ net-_q13-pad3_ 3.5 +* Control Statements + +.ends LM143_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC_Previous_Values.xml b/library/SubcircuitLibrary/LM143_sub/LM143_IC_Previous_Values.xml new file mode 100644 index 00000000..241d7b93 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i2 name="Source type">80u</i2><i3 name="Source type">80u</i3><i4 name="Source type">80u</i4><i1 name="Source type">20u</i1><i5 name="Source type">20u</i5><i6 name="Source type">400u</i6><v1 name="Source type">2</v1><i7 name="Source type">400u</i7><v2 name="Source type">3.5</v2></source><model /><devicemodel><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q14><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM143_sub/NPN.lib b/library/SubcircuitLibrary/LM143_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM143_sub/PNP.lib b/library/SubcircuitLibrary/LM143_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM143_sub/analysis b/library/SubcircuitLibrary/LM143_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC-cache.lib b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC-cache.lib new file mode 100644 index 00000000..27408fec --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC-cache.lib @@ -0,0 +1,138 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir new file mode 100644 index 00000000..4b52a3c4 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir @@ -0,0 +1,56 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LM78M05_IC\LM78M05_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/02/24 21:24:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 80k +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +U1 Net-_Q16-Pad3_ Net-_Q1-Pad2_ zener +R2 Net-_Q1-Pad3_ Net-_Q13-Pad2_ 7k +R3 Net-_Q13-Pad2_ Net-_Q3-Pad2_ 4.97k +R4 Net-_Q3-Pad2_ Net-_Q16-Pad3_ 830 +Q4 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q8 Net-_Q12-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q5 Net-_Q2-Pad1_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q13-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q5-Pad3_ Net-_Q13-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R5 Net-_Q2-Pad3_ Net-_Q6-Pad3_ 500 +Q7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ Net-_C1-Pad2_ eSim_NPN +R6 Net-_C1-Pad2_ Net-_Q16-Pad3_ 1.2k +R7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ 1.9k +R8 Net-_Q7-Pad2_ Net-_C1-Pad1_ 26 +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 0.4p +Q9 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q16-Pad3_ eSim_NPN +U2 Net-_R12-Pad1_ Net-_Q1-Pad1_ zener +R12 Net-_R12-Pad1_ Net-_R12-Pad2_ 5k +U3 Net-_Q12-Pad2_ Net-_R12-Pad2_ zener +Q18 Net-_Q1-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad1_ eSim_NPN +Q19 Net-_Q1-Pad1_ Net-_Q13-Pad1_ Net-_Q19-Pad3_ eSim_NPN +R18 Net-_Q13-Pad1_ Net-_Q12-Pad2_ 1.14k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R16 Net-_Q19-Pad3_ Net-_Q12-Pad2_ 100 +R17 Net-_R17-Pad1_ Net-_Q12-Pad3_ 100 +R19 Net-_R17-Pad1_ Net-_Q19-Pad3_ 0.5 +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_Q10-Pad1_ eSim_NPN +R20 Net-_Q13-Pad2_ Net-_R17-Pad1_ 1.6k +R14 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 850 +R10 Net-_C2-Pad2_ Net-_Q10-Pad1_ 16.5k +Q10 Net-_Q10-Pad1_ Net-_C1-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R9 Net-_Q16-Pad3_ Net-_Q10-Pad3_ 12.1k +R15 Net-_C2-Pad1_ Net-_Q17-Pad3_ 4k +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 20p +Q14 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q14-Pad3_ eSim_NPN +Q3 Net-_Q12-Pad1_ Net-_Q3-Pad2_ Net-_Q16-Pad3_ eSim_NPN +Q11 Net-_C2-Pad2_ Net-_Q10-Pad3_ Net-_Q11-Pad3_ eSim_NPN +R11 Net-_Q16-Pad3_ Net-_Q11-Pad3_ 1k +Q15 Net-_Q14-Pad3_ Net-_Q14-Pad3_ Net-_Q15-Pad3_ eSim_NPN +R13 Net-_Q16-Pad3_ Net-_Q15-Pad3_ 4k +Q16 Net-_C2-Pad1_ Net-_Q14-Pad3_ Net-_Q16-Pad3_ eSim_NPN +R21 Net-_Q16-Pad3_ Net-_Q13-Pad2_ 4k +Q17 Net-_Q16-Pad3_ Net-_C2-Pad1_ Net-_Q17-Pad3_ eSim_PNP +U4 Net-_Q1-Pad1_ Net-_R17-Pad1_ Net-_Q16-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir.out b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir.out new file mode 100644 index 00000000..1cc0d232 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir.out @@ -0,0 +1,68 @@ +* d:\fossee\esim\library\subcircuitlibrary\lm78m05_ic\lm78m05_ic.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 80k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +* u1 net-_q16-pad3_ net-_q1-pad2_ zener +r2 net-_q1-pad3_ net-_q13-pad2_ 7k +r3 net-_q13-pad2_ net-_q3-pad2_ 4.97k +r4 net-_q3-pad2_ net-_q16-pad3_ 830 +q4 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q8 net-_q12-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q5 net-_q2-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q13-pad2_ net-_q2-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q13-pad2_ net-_q6-pad3_ Q2N2222 +r5 net-_q2-pad3_ net-_q6-pad3_ 500 +q7 net-_q6-pad3_ net-_q7-pad2_ net-_c1-pad2_ Q2N2222 +r6 net-_c1-pad2_ net-_q16-pad3_ 1.2k +r7 net-_q6-pad3_ net-_q7-pad2_ 1.9k +r8 net-_q7-pad2_ net-_c1-pad1_ 26 +c1 net-_c1-pad1_ net-_c1-pad2_ 0.4p +q9 net-_c1-pad1_ net-_c1-pad2_ net-_q16-pad3_ Q2N2222 +* u2 net-_r12-pad1_ net-_q1-pad1_ zener +r12 net-_r12-pad1_ net-_r12-pad2_ 5k +* u3 net-_q12-pad2_ net-_r12-pad2_ zener +q18 net-_q1-pad1_ net-_q12-pad1_ net-_q13-pad1_ Q2N2222 +q19 net-_q1-pad1_ net-_q13-pad1_ net-_q19-pad3_ Q2N2222 +r18 net-_q13-pad1_ net-_q12-pad2_ 1.14k +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r16 net-_q19-pad3_ net-_q12-pad2_ 100 +r17 net-_r17-pad1_ net-_q12-pad3_ 100 +r19 net-_r17-pad1_ net-_q19-pad3_ 0.5 +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222 +r20 net-_q13-pad2_ net-_r17-pad1_ 1.6k +r14 net-_q17-pad3_ net-_q12-pad1_ 850 +r10 net-_c2-pad2_ net-_q10-pad1_ 16.5k +q10 net-_q10-pad1_ net-_c1-pad1_ net-_q10-pad3_ Q2N2222 +r9 net-_q16-pad3_ net-_q10-pad3_ 12.1k +r15 net-_c2-pad1_ net-_q17-pad3_ 4k +c2 net-_c2-pad1_ net-_c2-pad2_ 20p +q14 net-_c2-pad1_ net-_c2-pad2_ net-_q14-pad3_ Q2N2222 +q3 net-_q12-pad1_ net-_q3-pad2_ net-_q16-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r11 net-_q16-pad3_ net-_q11-pad3_ 1k +q15 net-_q14-pad3_ net-_q14-pad3_ net-_q15-pad3_ Q2N2222 +r13 net-_q16-pad3_ net-_q15-pad3_ 4k +q16 net-_c2-pad1_ net-_q14-pad3_ net-_q16-pad3_ Q2N2222 +r21 net-_q16-pad3_ net-_q13-pad2_ 4k +q17 net-_q16-pad3_ net-_c2-pad1_ net-_q17-pad3_ Q2N2907A +* u4 net-_q1-pad1_ net-_r17-pad1_ net-_q16-pad3_ port +a1 net-_q16-pad3_ net-_q1-pad2_ u1 +a2 net-_r12-pad1_ net-_q1-pad1_ u2 +a3 net-_q12-pad2_ net-_r12-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0.01e-03 0.1e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.pro b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sch b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sch new file mode 100644 index 00000000..3693b791 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sch @@ -0,0 +1,828 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM78M05-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 66842368 +P 2150 1500 +F 0 "R1" H 2200 1630 50 0000 C CNN +F 1 "80k" H 2200 1450 50 0000 C CNN +F 2 "" H 2200 1480 30 0000 C CNN +F 3 "" V 2200 1550 30 0000 C CNN + 1 2150 1500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 66842369 +P 2600 1900 +F 0 "Q1" H 2500 1950 50 0000 R CNN +F 1 "eSim_NPN" H 2550 2050 50 0000 R CNN +F 2 "" H 2800 2000 29 0000 C CNN +F 3 "" H 2600 1900 60 0000 C CNN + 1 2600 1900 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 6684236A +P 2200 3350 +F 0 "U1" H 2150 3250 60 0000 C CNN +F 1 "zener" H 2200 3450 60 0000 C CNN +F 2 "" H 2250 3350 60 0000 C CNN +F 3 "" H 2250 3350 60 0000 C CNN + 1 2200 3350 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2200 1700 2200 3050 +$Comp +L resistor R2 +U 1 1 6684236B +P 2650 2800 +F 0 "R2" H 2700 2930 50 0000 C CNN +F 1 "7k" H 2700 2750 50 0000 C CNN +F 2 "" H 2700 2780 30 0000 C CNN +F 3 "" V 2700 2850 30 0000 C CNN + 1 2650 2800 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 6684236C +P 2650 3550 +F 0 "R3" H 2700 3680 50 0000 C CNN +F 1 "4.97k" H 2700 3500 50 0000 C CNN +F 2 "" H 2700 3530 30 0000 C CNN +F 3 "" V 2700 3600 30 0000 C CNN + 1 2650 3550 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6684236D +P 2650 6200 +F 0 "R4" H 2700 6330 50 0000 C CNN +F 1 "830" H 2700 6150 50 0000 C CNN +F 2 "" H 2700 6180 30 0000 C CNN +F 3 "" V 2700 6250 30 0000 C CNN + 1 2650 6200 + 0 1 1 0 +$EndComp +Wire Wire Line + 2200 3550 2200 6700 +Wire Wire Line + 2700 3750 2700 6100 +Wire Wire Line + 2700 2100 2700 2700 +Wire Wire Line + 2400 1900 2200 1900 +Connection ~ 2200 1900 +Wire Wire Line + 2700 1700 2700 1300 +Wire Wire Line + 2200 1300 7600 1300 +Wire Wire Line + 2200 1300 2200 1400 +$Comp +L eSim_PNP Q4 +U 1 1 6684236E +P 3350 1650 +F 0 "Q4" H 3250 1700 50 0000 R CNN +F 1 "eSim_PNP" H 3300 1800 50 0000 R CNN +F 2 "" H 3550 1750 29 0000 C CNN +F 3 "" H 3350 1650 60 0000 C CNN + 1 3350 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6684236F +P 3800 1650 +F 0 "Q8" H 3700 1700 50 0000 R CNN +F 1 "eSim_PNP" H 3750 1800 50 0000 R CNN +F 2 "" H 4000 1750 29 0000 C CNN +F 3 "" H 3800 1650 60 0000 C CNN + 1 3800 1650 + 1 0 0 1 +$EndComp +Wire Wire Line + 3600 1650 3150 1650 +Wire Wire Line + 3450 1850 3450 2350 +Wire Wire Line + 3900 1850 3900 1950 +Wire Wire Line + 3450 1450 3900 1450 +Wire Wire Line + 3700 1300 3700 1450 +Connection ~ 2700 1300 +Connection ~ 3700 1450 +$Comp +L eSim_NPN Q5 +U 1 1 66842370 +P 3350 2550 +F 0 "Q5" H 3250 2600 50 0000 R CNN +F 1 "eSim_NPN" H 3300 2700 50 0000 R CNN +F 2 "" H 3550 2650 29 0000 C CNN +F 3 "" H 3350 2550 60 0000 C CNN + 1 3350 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 2550 2700 2550 +Connection ~ 2700 2550 +Wire Wire Line + 3150 1650 3150 1950 +Wire Wire Line + 3150 1950 3450 1950 +Connection ~ 3450 1950 +Wire Wire Line + 2700 3000 2700 3450 +$Comp +L eSim_NPN Q2 +U 1 1 66842371 +P 2950 3250 +F 0 "Q2" H 2850 3300 50 0000 R CNN +F 1 "eSim_NPN" H 2900 3400 50 0000 R CNN +F 2 "" H 3150 3350 29 0000 C CNN +F 3 "" H 2950 3250 60 0000 C CNN + 1 2950 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 66842372 +P 3550 3250 +F 0 "Q6" H 3450 3300 50 0000 R CNN +F 1 "eSim_NPN" H 3500 3400 50 0000 R CNN +F 2 "" H 3750 3350 29 0000 C CNN +F 3 "" H 3550 3250 60 0000 C CNN + 1 3550 3250 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3450 2750 3450 3050 +Wire Wire Line + 3050 3050 3050 2300 +Wire Wire Line + 3050 2300 3450 2300 +Connection ~ 3450 2300 +$Comp +L resistor R5 +U 1 1 66842373 +P 3000 3700 +F 0 "R5" H 3050 3830 50 0000 C CNN +F 1 "500" H 3050 3650 50 0000 C CNN +F 2 "" H 3050 3680 30 0000 C CNN +F 3 "" V 3050 3750 30 0000 C CNN + 1 3000 3700 + 0 1 1 0 +$EndComp +Wire Wire Line + 3050 3600 3050 3450 +$Comp +L eSim_NPN Q7 +U 1 1 66842374 +P 3550 4150 +F 0 "Q7" H 3450 4200 50 0000 R CNN +F 1 "eSim_NPN" H 3500 4300 50 0000 R CNN +F 2 "" H 3750 4250 29 0000 C CNN +F 3 "" H 3550 4150 60 0000 C CNN + 1 3550 4150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3450 3450 3450 3950 +$Comp +L resistor R6 +U 1 1 66842375 +P 3400 6100 +F 0 "R6" H 3450 6230 50 0000 C CNN +F 1 "1.2k" H 3450 6050 50 0000 C CNN +F 2 "" H 3450 6080 30 0000 C CNN +F 3 "" V 3450 6150 30 0000 C CNN + 1 3400 6100 + 0 1 1 0 +$EndComp +Wire Wire Line + 3450 4350 3450 6000 +$Comp +L resistor R7 +U 1 1 66842376 +P 4000 3850 +F 0 "R7" H 4050 3980 50 0000 C CNN +F 1 "1.9k" H 4050 3800 50 0000 C CNN +F 2 "" H 4050 3830 30 0000 C CNN +F 3 "" V 4050 3900 30 0000 C CNN + 1 4000 3850 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 66842377 +P 4000 4350 +F 0 "R8" H 4050 4480 50 0000 C CNN +F 1 "26" H 4050 4300 50 0000 C CNN +F 2 "" H 4050 4330 30 0000 C CNN +F 3 "" V 4050 4400 30 0000 C CNN + 1 4000 4350 + 0 1 1 0 +$EndComp +Wire Wire Line + 4050 4050 4050 4250 +Wire Wire Line + 3750 4150 4050 4150 +Connection ~ 4050 4150 +Wire Wire Line + 3050 3900 3750 3900 +Wire Wire Line + 3750 3900 3750 3700 +Wire Wire Line + 3750 3700 4050 3700 +Wire Wire Line + 4050 3700 4050 3750 +Connection ~ 3450 3900 +$Comp +L capacitor C1 +U 1 1 66842378 +P 3750 4700 +F 0 "C1" H 3775 4800 50 0000 L CNN +F 1 "0.4p" H 3775 4600 50 0000 L CNN +F 2 "" H 3788 4550 30 0000 C CNN +F 3 "" H 3750 4700 60 0000 C CNN + 1 3750 4700 + 0 1 1 0 +$EndComp +Wire Wire Line + 3600 4700 3450 4700 +Connection ~ 3450 4700 +Wire Wire Line + 4050 4550 4050 5400 +Wire Wire Line + 3900 4700 4200 4700 +$Comp +L eSim_NPN Q9 +U 1 1 66842379 +P 3950 5600 +F 0 "Q9" H 3850 5650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 5750 50 0000 R CNN +F 2 "" H 4150 5700 29 0000 C CNN +F 3 "" H 3950 5600 60 0000 C CNN + 1 3950 5600 + 1 0 0 -1 +$EndComp +Connection ~ 4050 4700 +$Comp +L zener U2 +U 1 1 6684237A +P 5400 1700 +F 0 "U2" H 5350 1600 60 0000 C CNN +F 1 "zener" H 5400 1800 60 0000 C CNN +F 2 "" H 5450 1700 60 0000 C CNN +F 3 "" H 5450 1700 60 0000 C CNN + 1 5400 1700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5400 1300 5400 1400 +Connection ~ 3700 1300 +$Comp +L resistor R12 +U 1 1 6684237B +P 5350 2300 +F 0 "R12" H 5400 2430 50 0000 C CNN +F 1 "5k" H 5400 2250 50 0000 C CNN +F 2 "" H 5400 2280 30 0000 C CNN +F 3 "" V 5400 2350 30 0000 C CNN + 1 5350 2300 + 0 1 1 0 +$EndComp +$Comp +L zener U3 +U 1 1 6684237C +P 5400 2900 +F 0 "U3" H 5350 2800 60 0000 C CNN +F 1 "zener" H 5400 3000 60 0000 C CNN +F 2 "" H 5450 2900 60 0000 C CNN +F 3 "" H 5450 2900 60 0000 C CNN + 1 5400 2900 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5400 1900 5400 2200 +Wire Wire Line + 5400 2500 5400 2600 +$Comp +L eSim_NPN Q18 +U 1 1 6684237D +P 6000 1950 +F 0 "Q18" H 5900 2000 50 0000 R CNN +F 1 "eSim_NPN" H 5950 2100 50 0000 R CNN +F 2 "" H 6200 2050 29 0000 C CNN +F 3 "" H 6000 1950 60 0000 C CNN + 1 6000 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 1300 6100 1750 +Connection ~ 5400 1300 +Wire Wire Line + 3900 1950 5800 1950 +$Comp +L eSim_NPN Q19 +U 1 1 6684237E +P 6800 2200 +F 0 "Q19" H 6700 2250 50 0000 R CNN +F 1 "eSim_NPN" H 6750 2350 50 0000 R CNN +F 2 "" H 7000 2300 29 0000 C CNN +F 3 "" H 6800 2200 60 0000 C CNN + 1 6800 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 1300 6900 2000 +Connection ~ 6100 1300 +Wire Wire Line + 6100 2200 6600 2200 +Wire Wire Line + 6100 2200 6100 2150 +$Comp +L resistor R18 +U 1 1 6684237F +P 6200 2400 +F 0 "R18" H 6250 2530 50 0000 C CNN +F 1 "1.14k" H 6250 2350 50 0000 C CNN +F 2 "" H 6250 2380 30 0000 C CNN +F 3 "" V 6250 2450 30 0000 C CNN + 1 6200 2400 + 0 1 1 0 +$EndComp +Wire Wire Line + 6250 3150 6250 2600 +Wire Wire Line + 5400 3100 5400 3350 +Wire Wire Line + 6250 2300 6250 2200 +Connection ~ 6250 2200 +$Comp +L eSim_NPN Q12 +U 1 1 66842380 +P 4950 3350 +F 0 "Q12" H 4850 3400 50 0000 R CNN +F 1 "eSim_NPN" H 4900 3500 50 0000 R CNN +F 2 "" H 5150 3450 29 0000 C CNN +F 3 "" H 4950 3350 60 0000 C CNN + 1 4950 3350 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4850 1950 4850 3150 +Connection ~ 4850 1950 +Wire Wire Line + 5400 3150 6250 3150 +$Comp +L resistor R16 +U 1 1 66842381 +P 5850 3300 +F 0 "R16" H 5900 3430 50 0000 C CNN +F 1 "100" H 5900 3250 50 0000 C CNN +F 2 "" H 5900 3280 30 0000 C CNN +F 3 "" V 5900 3350 30 0000 C CNN + 1 5850 3300 + -1 0 0 1 +$EndComp +Wire Wire Line + 5150 3350 5650 3350 +Connection ~ 5400 3350 +Connection ~ 5400 3150 +Wire Wire Line + 5950 3350 6900 3350 +Wire Wire Line + 6900 2400 6900 3400 +$Comp +L resistor R17 +U 1 1 66842382 +P 5850 3750 +F 0 "R17" H 5900 3880 50 0000 C CNN +F 1 "100" H 5900 3700 50 0000 C CNN +F 2 "" H 5900 3730 30 0000 C CNN +F 3 "" V 5900 3800 30 0000 C CNN + 1 5850 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 4850 3550 4850 3800 +$Comp +L resistor R19 +U 1 1 66842383 +P 6950 3600 +F 0 "R19" H 7000 3730 50 0000 C CNN +F 1 "0.5" H 7000 3550 50 0000 C CNN +F 2 "" H 7000 3580 30 0000 C CNN +F 3 "" V 7000 3650 30 0000 C CNN + 1 6950 3600 + 0 -1 -1 0 +$EndComp +Connection ~ 6900 3350 +$Comp +L eSim_NPN Q13 +U 1 1 66842384 +P 4950 4250 +F 0 "Q13" H 4850 4300 50 0000 R CNN +F 1 "eSim_NPN" H 4900 4400 50 0000 R CNN +F 2 "" H 5150 4350 29 0000 C CNN +F 3 "" H 4950 4250 60 0000 C CNN + 1 4950 4250 + -1 0 0 -1 +$EndComp +Connection ~ 6450 2200 +Wire Wire Line + 4850 4050 4850 4000 +Wire Wire Line + 4850 4000 6450 4000 +Wire Wire Line + 6450 4000 6450 2200 +Wire Wire Line + 2700 3250 4600 3250 +Wire Wire Line + 4600 3250 4600 4250 +Wire Wire Line + 4600 4250 6900 4250 +Connection ~ 2700 3250 +$Comp +L resistor R20 +U 1 1 66842385 +P 6950 4100 +F 0 "R20" H 7000 4230 50 0000 C CNN +F 1 "1.6k" H 7000 4050 50 0000 C CNN +F 2 "" H 7000 4080 30 0000 C CNN +F 3 "" V 7000 4150 30 0000 C CNN + 1 6950 4100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6900 4200 6900 5600 +Wire Wire Line + 6900 3700 6900 3900 +Wire Wire Line + 4850 3800 5650 3800 +Wire Wire Line + 5950 3800 7500 3800 +Connection ~ 6900 3800 +Connection ~ 5150 4250 +Connection ~ 3750 3250 +Connection ~ 2750 3250 +$Comp +L resistor R14 +U 1 1 66842386 +P 5550 4600 +F 0 "R14" H 5600 4730 50 0000 C CNN +F 1 "850" H 5600 4550 50 0000 C CNN +F 2 "" H 5600 4580 30 0000 C CNN +F 3 "" V 5600 4650 30 0000 C CNN + 1 5550 4600 + 0 -1 -1 0 +$EndComp +Connection ~ 5500 1950 +Wire Wire Line + 5500 4400 5500 1950 +$Comp +L resistor R10 +U 1 1 66842387 +P 4900 4900 +F 0 "R10" H 4950 5030 50 0000 C CNN +F 1 "16.5k" H 4950 4850 50 0000 C CNN +F 2 "" H 4950 4880 30 0000 C CNN +F 3 "" V 4950 4950 30 0000 C CNN + 1 4900 4900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4850 4450 4850 4700 +$Comp +L eSim_NPN Q10 +U 1 1 66842388 +P 4400 4700 +F 0 "Q10" H 4300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 4350 4850 50 0000 R CNN +F 2 "" H 4600 4800 29 0000 C CNN +F 3 "" H 4400 4700 60 0000 C CNN + 1 4400 4700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 4500 4850 4500 +Connection ~ 4850 4500 +$Comp +L resistor R9 +U 1 1 66842389 +P 4550 6300 +F 0 "R9" H 4600 6430 50 0000 C CNN +F 1 "12.1k" H 4600 6250 50 0000 C CNN +F 2 "" H 4600 6280 30 0000 C CNN +F 3 "" V 4600 6350 30 0000 C CNN + 1 4550 6300 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4900 4500 6100 +$Comp +L resistor R15 +U 1 1 6684238A +P 5550 5100 +F 0 "R15" H 5600 5230 50 0000 C CNN +F 1 "4k" H 5600 5050 50 0000 C CNN +F 2 "" H 5600 5080 30 0000 C CNN +F 3 "" V 5600 5150 30 0000 C CNN + 1 5550 5100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5500 4700 5500 4900 +$Comp +L capacitor C2 +U 1 1 6684238B +P 5050 5300 +F 0 "C2" H 5075 5400 50 0000 L CNN +F 1 "20p" H 5075 5200 50 0000 L CNN +F 2 "" H 5088 5150 30 0000 C CNN +F 3 "" H 5050 5300 60 0000 C CNN + 1 5050 5300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5500 5200 5500 5750 +Wire Wire Line + 4850 5000 4850 5850 +Wire Wire Line + 4850 5300 4900 5300 +$Comp +L eSim_NPN Q14 +U 1 1 6684238C +P 5200 5700 +F 0 "Q14" H 5100 5750 50 0000 R CNN +F 1 "eSim_NPN" H 5150 5850 50 0000 R CNN +F 2 "" H 5400 5800 29 0000 C CNN +F 3 "" H 5200 5700 60 0000 C CNN + 1 5200 5700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 5500 5300 5300 +Connection ~ 5300 5300 +Wire Wire Line + 4850 5700 5000 5700 +Connection ~ 4850 5300 +Wire Wire Line + 2200 6700 4850 6700 +Wire Wire Line + 2700 6700 2700 6400 +Connection ~ 2700 6700 +$Comp +L eSim_NPN Q3 +U 1 1 6684238D +P 3000 5900 +F 0 "Q3" H 2900 5950 50 0000 R CNN +F 1 "eSim_NPN" H 2950 6050 50 0000 R CNN +F 2 "" H 3200 6000 29 0000 C CNN +F 3 "" H 3000 5900 60 0000 C CNN + 1 3000 5900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 5900 2700 5900 +Connection ~ 2700 5900 +Wire Wire Line + 3100 5700 3100 3100 +Wire Wire Line + 3100 3100 4850 3100 +Connection ~ 4850 3100 +Wire Wire Line + 3100 6100 3100 6700 +Connection ~ 3100 6700 +Connection ~ 3450 6700 +Wire Wire Line + 4500 6700 4500 6400 +Connection ~ 4050 6700 +Wire Wire Line + 3450 6300 3450 6700 +$Comp +L eSim_NPN Q11 +U 1 1 6684238E +P 4750 6050 +F 0 "Q11" H 4650 6100 50 0000 R CNN +F 1 "eSim_NPN" H 4700 6200 50 0000 R CNN +F 2 "" H 4950 6150 29 0000 C CNN +F 3 "" H 4750 6050 60 0000 C CNN + 1 4750 6050 + 1 0 0 -1 +$EndComp +Connection ~ 4850 5700 +Wire Wire Line + 4550 6050 4500 6050 +Connection ~ 4500 6050 +$Comp +L resistor R11 +U 1 1 6684238F +P 4900 6550 +F 0 "R11" H 4950 6680 50 0000 C CNN +F 1 "1k" H 4950 6500 50 0000 C CNN +F 2 "" H 4950 6530 30 0000 C CNN +F 3 "" V 4950 6600 30 0000 C CNN + 1 4900 6550 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4850 6650 4850 6900 +Connection ~ 4500 6700 +Wire Wire Line + 4850 6350 4850 6250 +$Comp +L eSim_NPN Q15 +U 1 1 66842390 +P 5400 6300 +F 0 "Q15" H 5300 6350 50 0000 R CNN +F 1 "eSim_NPN" H 5350 6450 50 0000 R CNN +F 2 "" H 5600 6400 29 0000 C CNN +F 3 "" H 5400 6300 60 0000 C CNN + 1 5400 6300 + -1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 66842391 +P 5350 6800 +F 0 "R13" H 5400 6930 50 0000 C CNN +F 1 "4k" H 5400 6750 50 0000 C CNN +F 2 "" H 5400 6780 30 0000 C CNN +F 3 "" V 5400 6850 30 0000 C CNN + 1 5350 6800 + 0 -1 -1 0 +$EndComp +Connection ~ 4850 6700 +Wire Wire Line + 5300 6600 5300 6500 +Wire Wire Line + 5300 5900 5300 6100 +$Comp +L eSim_NPN Q16 +U 1 1 66842392 +P 5650 5950 +F 0 "Q16" H 5550 6000 50 0000 R CNN +F 1 "eSim_NPN" H 5600 6100 50 0000 R CNN +F 2 "" H 5850 6050 29 0000 C CNN +F 3 "" H 5650 5950 60 0000 C CNN + 1 5650 5950 + 1 0 0 -1 +$EndComp +Connection ~ 5500 5300 +Wire Wire Line + 5600 6050 5600 6300 +Wire Wire Line + 5600 6050 5300 6050 +Connection ~ 5300 6050 +Connection ~ 5300 6900 +$Comp +L resistor R21 +U 1 1 66842393 +P 6950 5800 +F 0 "R21" H 7000 5930 50 0000 C CNN +F 1 "4k" H 7000 5750 50 0000 C CNN +F 2 "" H 7000 5780 30 0000 C CNN +F 3 "" V 7000 5850 30 0000 C CNN + 1 6950 5800 + 0 -1 -1 0 +$EndComp +Connection ~ 6900 4250 +Wire Wire Line + 3750 5600 3450 5600 +Connection ~ 3450 5600 +Wire Wire Line + 4050 5800 4050 6700 +Wire Wire Line + 5500 5750 5750 5750 +Wire Wire Line + 5450 5950 5300 5950 +Connection ~ 5300 5950 +Wire Wire Line + 5750 6900 5750 6150 +Connection ~ 5750 6900 +$Comp +L eSim_PNP Q17 +U 1 1 66842394 +P 5800 5300 +F 0 "Q17" H 5700 5350 50 0000 R CNN +F 1 "eSim_PNP" H 5750 5450 50 0000 R CNN +F 2 "" H 6000 5400 29 0000 C CNN +F 3 "" H 5800 5300 60 0000 C CNN + 1 5800 5300 + 1 0 0 1 +$EndComp +Wire Wire Line + 5200 5300 5600 5300 +Wire Wire Line + 5900 5100 5900 4800 +Wire Wire Line + 5900 4800 5500 4800 +Connection ~ 5500 4800 +Wire Wire Line + 5900 6900 5900 5500 +Connection ~ 5900 6900 +Connection ~ 6900 1300 +Wire Wire Line + 6950 6900 6950 7050 +Wire Wire Line + 6900 5900 6900 7000 +Wire Wire Line + 6900 7000 6950 7000 +Connection ~ 6950 7000 +Wire Wire Line + 4850 6900 6950 6900 +$Comp +L PORT U4 +U 1 1 66842F0A +P 7850 1300 +F 0 "U4" H 7900 1400 30 0000 C CNN +F 1 "PORT" H 7850 1300 30 0000 C CNN +F 2 "" H 7850 1300 60 0000 C CNN +F 3 "" H 7850 1300 60 0000 C CNN + 1 7850 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 2 1 668432FF +P 7750 3800 +F 0 "U4" H 7800 3900 30 0000 C CNN +F 1 "PORT" H 7750 3800 30 0000 C CNN +F 2 "" H 7750 3800 60 0000 C CNN +F 3 "" H 7750 3800 60 0000 C CNN + 2 7750 3800 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 3 1 66843537 +P 6950 7300 +F 0 "U4" H 7000 7400 30 0000 C CNN +F 1 "PORT" H 6950 7300 30 0000 C CNN +F 2 "" H 6950 7300 60 0000 C CNN +F 3 "" H 6950 7300 60 0000 C CNN + 3 6950 7300 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sub b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sub new file mode 100644 index 00000000..17df98f3 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sub @@ -0,0 +1,62 @@ +* Subcircuit LM78M05_IC +.subckt LM78M05_IC net-_q1-pad1_ net-_r17-pad1_ net-_q16-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\lm78m05_ic\lm78m05_ic.cir +.include PNP.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 80k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +* u1 net-_q16-pad3_ net-_q1-pad2_ zener +r2 net-_q1-pad3_ net-_q13-pad2_ 7k +r3 net-_q13-pad2_ net-_q3-pad2_ 4.97k +r4 net-_q3-pad2_ net-_q16-pad3_ 830 +q4 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q8 net-_q12-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q5 net-_q2-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q13-pad2_ net-_q2-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q13-pad2_ net-_q6-pad3_ Q2N2222 +r5 net-_q2-pad3_ net-_q6-pad3_ 500 +q7 net-_q6-pad3_ net-_q7-pad2_ net-_c1-pad2_ Q2N2222 +r6 net-_c1-pad2_ net-_q16-pad3_ 1.2k +r7 net-_q6-pad3_ net-_q7-pad2_ 1.9k +r8 net-_q7-pad2_ net-_c1-pad1_ 26 +c1 net-_c1-pad1_ net-_c1-pad2_ 0.4p +q9 net-_c1-pad1_ net-_c1-pad2_ net-_q16-pad3_ Q2N2222 +* u2 net-_r12-pad1_ net-_q1-pad1_ zener +r12 net-_r12-pad1_ net-_r12-pad2_ 5k +* u3 net-_q12-pad2_ net-_r12-pad2_ zener +q18 net-_q1-pad1_ net-_q12-pad1_ net-_q13-pad1_ Q2N2222 +q19 net-_q1-pad1_ net-_q13-pad1_ net-_q19-pad3_ Q2N2222 +r18 net-_q13-pad1_ net-_q12-pad2_ 1.14k +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r16 net-_q19-pad3_ net-_q12-pad2_ 100 +r17 net-_r17-pad1_ net-_q12-pad3_ 100 +r19 net-_r17-pad1_ net-_q19-pad3_ 0.5 +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222 +r20 net-_q13-pad2_ net-_r17-pad1_ 1.6k +r14 net-_q17-pad3_ net-_q12-pad1_ 850 +r10 net-_c2-pad2_ net-_q10-pad1_ 16.5k +q10 net-_q10-pad1_ net-_c1-pad1_ net-_q10-pad3_ Q2N2222 +r9 net-_q16-pad3_ net-_q10-pad3_ 12.1k +r15 net-_c2-pad1_ net-_q17-pad3_ 4k +c2 net-_c2-pad1_ net-_c2-pad2_ 20p +q14 net-_c2-pad1_ net-_c2-pad2_ net-_q14-pad3_ Q2N2222 +q3 net-_q12-pad1_ net-_q3-pad2_ net-_q16-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r11 net-_q16-pad3_ net-_q11-pad3_ 1k +q15 net-_q14-pad3_ net-_q14-pad3_ net-_q15-pad3_ Q2N2222 +r13 net-_q16-pad3_ net-_q15-pad3_ 4k +q16 net-_c2-pad1_ net-_q14-pad3_ net-_q16-pad3_ Q2N2222 +r21 net-_q16-pad3_ net-_q13-pad2_ 4k +q17 net-_q16-pad3_ net-_c2-pad1_ net-_q17-pad3_ Q2N2907A +a1 net-_q16-pad3_ net-_q1-pad2_ u1 +a2 net-_r12-pad1_ net-_q1-pad1_ u2 +a3 net-_q12-pad2_ net-_r12-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM78M05_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC_Previous_Values.xml b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC_Previous_Values.xml new file mode 100644 index 00000000..1be6e874 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)" /><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u3></model><devicemodel><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">0.1</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM78M05_sub/NPN.lib b/library/SubcircuitLibrary/LM78M05_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM78M05_sub/PNP.lib b/library/SubcircuitLibrary/LM78M05_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM78M05_sub/analysis b/library/SubcircuitLibrary/LM78M05_sub/analysis new file mode 100644 index 00000000..e69f4e9b --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 0.1e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC-cache.lib b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC-cache.lib new file mode 100644 index 00000000..7eda2392 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir new file mode 100644 index 00000000..170c7d7f --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir @@ -0,0 +1,179 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\MC3403_IC\MC3403_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 18:49:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q19 Net-_Q19-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q22 Net-_Q22-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q42 Net-_Q1-Pad2_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q43 Net-_C1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q47 Net-_J1-Pad1_ Net-_C1-Pad1_ Net-_Q47-Pad3_ eSim_NPN +Q49 Net-_J1-Pad1_ Net-_Q47-Pad3_ Net-_Q49-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_Q12-Pad3_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q2 Net-_J1-Pad2_ Net-_Q12-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q7 Net-_Q12-Pad2_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q18 Net-_C1-Pad2_ Net-_Q18-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q21 Net-_Q18-Pad2_ Net-_Q18-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q3 Net-_J1-Pad2_ Net-_Q3-Pad2_ Net-_Q12-Pad2_ eSim_PNP +Q8 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q16 Net-_C1-Pad2_ Net-_Q12-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q25 Net-_J1-Pad2_ Net-_Q25-Pad2_ Net-_Q18-Pad2_ eSim_PNP +Q29 Net-_J1-Pad2_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q30 Net-_Q19-Pad1_ Net-_Q10-Pad1_ Net-_Q30-Pad3_ eSim_NPN +Q32 Net-_Q30-Pad3_ Net-_Q22-Pad1_ Net-_Q32-Pad3_ eSim_NPN +R3 Net-_Q32-Pad3_ Net-_J1-Pad2_ 12k +Q35 Net-_J1-Pad2_ Net-_Q22-Pad1_ Net-_Q19-Pad1_ eSim_PNP +Q37 Net-_Q22-Pad1_ Net-_Q22-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q39 Net-_Q1-Pad2_ Net-_Q39-Pad2_ Net-_Q39-Pad3_ eSim_NPN +R5 Net-_Q39-Pad3_ Net-_J1-Pad2_ 0.7k +Q41 Net-_C1-Pad1_ Net-_Q30-Pad3_ Net-_J1-Pad2_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 8p +Q50 Net-_Q49-Pad3_ Net-_Q50-Pad2_ Net-_Q50-Pad3_ eSim_NPN +Q51 Net-_Q50-Pad3_ Net-_Q22-Pad1_ Net-_J1-Pad2_ eSim_NPN +R9 Net-_Q49-Pad3_ Net-_Q50-Pad2_ 31k +R10 Net-_Q50-Pad2_ Net-_Q50-Pad3_ 37k +Q57 Net-_J1-Pad1_ Net-_Q47-Pad3_ Net-_Q57-Pad3_ eSim_NPN +R13 Net-_Q57-Pad3_ Net-_Q58-Pad3_ 25 +Q58 Net-_J1-Pad2_ Net-_Q55-Pad3_ Net-_Q58-Pad3_ eSim_PNP +Q55 Net-_J1-Pad2_ Net-_Q50-Pad3_ Net-_Q55-Pad3_ eSim_PNP +Q61 Net-_C1-Pad1_ Net-_Q57-Pad3_ Net-_Q58-Pad3_ eSim_NPN +Q63 Net-_J1-Pad3_ Net-_J1-Pad3_ Net-_Q39-Pad2_ eSim_NPN +Q67 Net-_J1-Pad1_ Net-_J1-Pad3_ Net-_Q64-Pad2_ eSim_NPN +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +Q64 Net-_Q39-Pad2_ Net-_Q64-Pad2_ Net-_J1-Pad2_ eSim_NPN +R15 Net-_Q64-Pad2_ Net-_J1-Pad2_ 8.2k +Q89 Net-_Q103-Pad3_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q93 Net-_Q101-Pad2_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q111 Net-_Q107-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q113 Net-_C3-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q115 Net-_J1-Pad1_ Net-_C3-Pad1_ Net-_Q115-Pad3_ eSim_NPN +Q117 Net-_J1-Pad1_ Net-_Q115-Pad3_ Net-_Q117-Pad3_ eSim_NPN +Q81 Net-_Q81-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q75 Net-_Q75-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q69 Net-_Q69-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q71 Net-_J1-Pad2_ Net-_Q71-Pad2_ Net-_Q69-Pad1_ eSim_PNP +Q77 Net-_Q73-Pad3_ Net-_Q73-Pad3_ Net-_Q75-Pad1_ eSim_PNP +Q83 Net-_Q71-Pad2_ Net-_Q73-Pad3_ Net-_Q75-Pad1_ eSim_PNP +Q87 Net-_C3-Pad2_ Net-_Q87-Pad2_ Net-_Q75-Pad1_ eSim_PNP +Q91 Net-_Q87-Pad2_ Net-_Q87-Pad2_ Net-_Q75-Pad1_ eSim_PNP +Q73 Net-_J1-Pad2_ Net-_Q73-Pad2_ Net-_Q73-Pad3_ eSim_PNP +Q79 Net-_Q71-Pad2_ Net-_Q71-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q85 Net-_C3-Pad2_ Net-_Q71-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q95 Net-_J1-Pad2_ Net-_Q95-Pad2_ Net-_Q87-Pad2_ eSim_PNP +Q97 Net-_J1-Pad2_ Net-_C3-Pad2_ Net-_Q81-Pad1_ eSim_PNP +Q99 Net-_Q103-Pad3_ Net-_Q81-Pad1_ Net-_Q101-Pad1_ eSim_NPN +Q101 Net-_Q101-Pad1_ Net-_Q101-Pad2_ Net-_Q101-Pad3_ eSim_NPN +R19 Net-_Q101-Pad3_ Net-_J1-Pad2_ 12k +Q103 Net-_J1-Pad2_ Net-_Q101-Pad2_ Net-_Q103-Pad3_ eSim_PNP +Q105 Net-_Q101-Pad2_ Net-_Q101-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q107 Net-_Q107-Pad1_ Net-_Q107-Pad2_ Net-_Q107-Pad3_ eSim_NPN +R21 Net-_Q107-Pad3_ Net-_J1-Pad2_ 0.7k +Q109 Net-_C3-Pad1_ Net-_Q101-Pad1_ Net-_J1-Pad2_ eSim_NPN +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 8p +Q118 Net-_Q117-Pad3_ Net-_Q118-Pad2_ Net-_Q118-Pad3_ eSim_NPN +Q119 Net-_Q118-Pad3_ Net-_Q101-Pad2_ Net-_J1-Pad2_ eSim_NPN +R25 Net-_Q117-Pad3_ Net-_Q118-Pad2_ 31k +R26 Net-_Q118-Pad2_ Net-_Q118-Pad3_ 37k +Q125 Net-_J1-Pad1_ Net-_Q115-Pad3_ Net-_Q125-Pad3_ eSim_NPN +R29 Net-_Q125-Pad3_ Net-_Q126-Pad3_ 25 +Q126 Net-_J1-Pad2_ Net-_Q123-Pad3_ Net-_Q126-Pad3_ eSim_PNP +Q123 Net-_J1-Pad2_ Net-_Q118-Pad3_ Net-_Q123-Pad3_ eSim_PNP +Q129 Net-_C3-Pad1_ Net-_Q125-Pad3_ Net-_Q126-Pad3_ eSim_NPN +Q131 Net-_J3-Pad3_ Net-_J3-Pad3_ Net-_Q107-Pad2_ eSim_NPN +Q135 Net-_J1-Pad1_ Net-_J3-Pad3_ Net-_Q132-Pad2_ eSim_NPN +J3 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J3-Pad3_ jfet_n +Q132 Net-_Q107-Pad2_ Net-_Q132-Pad2_ Net-_J1-Pad2_ eSim_NPN +R31 Net-_Q132-Pad2_ Net-_J1-Pad2_ 8.2k +Q24 Net-_Q24-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q27 Net-_Q27-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q45 Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q46 Net-_C2-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q48 Net-_J1-Pad1_ Net-_C2-Pad1_ Net-_Q48-Pad3_ eSim_NPN +Q52 Net-_J1-Pad1_ Net-_Q48-Pad3_ Net-_Q52-Pad3_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q5 Net-_Q5-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q6 Net-_J1-Pad2_ Net-_Q14-Pad1_ Net-_Q5-Pad1_ eSim_PNP +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q11-Pad1_ eSim_PNP +Q17 Net-_Q14-Pad1_ Net-_Q13-Pad1_ Net-_Q11-Pad1_ eSim_PNP +Q23 Net-_C2-Pad2_ Net-_Q23-Pad2_ Net-_Q11-Pad1_ eSim_PNP +Q26 Net-_Q23-Pad2_ Net-_Q23-Pad2_ Net-_Q11-Pad1_ eSim_PNP +Q9 Net-_J1-Pad2_ Net-_Q9-Pad2_ Net-_Q13-Pad1_ eSim_PNP +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q20 Net-_C2-Pad2_ Net-_Q14-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q28 Net-_J1-Pad2_ Net-_Q28-Pad2_ Net-_Q23-Pad2_ eSim_PNP +Q31 Net-_J1-Pad2_ Net-_C2-Pad2_ Net-_Q15-Pad1_ eSim_PNP +Q33 Net-_Q24-Pad1_ Net-_Q15-Pad1_ Net-_Q33-Pad3_ eSim_NPN +Q34 Net-_Q33-Pad3_ Net-_Q27-Pad1_ Net-_Q34-Pad3_ eSim_NPN +R4 Net-_Q34-Pad3_ Net-_J1-Pad2_ 12k +Q36 Net-_J1-Pad2_ Net-_Q27-Pad1_ Net-_Q24-Pad1_ eSim_PNP +Q38 Net-_Q27-Pad1_ Net-_Q27-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q40 Net-_Q11-Pad2_ Net-_Q40-Pad2_ Net-_Q40-Pad3_ eSim_NPN +R6 Net-_Q40-Pad3_ Net-_J1-Pad2_ 0.7k +Q44 Net-_C2-Pad1_ Net-_Q33-Pad3_ Net-_J1-Pad2_ eSim_NPN +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 8p +Q53 Net-_Q52-Pad3_ Net-_Q53-Pad2_ Net-_Q53-Pad3_ eSim_NPN +Q54 Net-_Q53-Pad3_ Net-_Q27-Pad1_ Net-_J1-Pad2_ eSim_NPN +R11 Net-_Q52-Pad3_ Net-_Q53-Pad2_ 31k +R12 Net-_Q53-Pad2_ Net-_Q53-Pad3_ 37k +Q59 Net-_J1-Pad1_ Net-_Q48-Pad3_ Net-_Q59-Pad3_ eSim_NPN +R14 Net-_Q59-Pad3_ Net-_Q60-Pad3_ 25 +Q60 Net-_J1-Pad2_ Net-_Q56-Pad3_ Net-_Q60-Pad3_ eSim_PNP +Q56 Net-_J1-Pad2_ Net-_Q53-Pad3_ Net-_Q56-Pad3_ eSim_PNP +Q62 Net-_C2-Pad1_ Net-_Q59-Pad3_ Net-_Q60-Pad3_ eSim_NPN +Q65 Net-_J2-Pad3_ Net-_J2-Pad3_ Net-_Q40-Pad2_ eSim_NPN +Q68 Net-_J1-Pad1_ Net-_J2-Pad3_ Net-_Q66-Pad2_ eSim_NPN +J2 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J2-Pad3_ jfet_n +Q66 Net-_Q40-Pad2_ Net-_Q66-Pad2_ Net-_J1-Pad2_ eSim_NPN +R16 Net-_Q66-Pad2_ Net-_J1-Pad2_ 8.2k +Q90 Net-_Q100-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q94 Net-_Q102-Pad2_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q112 Net-_Q108-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q114 Net-_C4-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q116 Net-_J1-Pad1_ Net-_C4-Pad1_ Net-_Q116-Pad3_ eSim_NPN +Q120 Net-_J1-Pad1_ Net-_Q116-Pad3_ Net-_Q120-Pad3_ eSim_NPN +Q82 Net-_Q100-Pad2_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q76 Net-_Q76-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q70 Net-_Q70-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q72 Net-_J1-Pad2_ Net-_Q72-Pad2_ Net-_Q70-Pad1_ eSim_PNP +Q78 Net-_Q74-Pad3_ Net-_Q74-Pad3_ Net-_Q76-Pad1_ eSim_PNP +Q84 Net-_Q72-Pad2_ Net-_Q74-Pad3_ Net-_Q76-Pad1_ eSim_PNP +Q88 Net-_C4-Pad2_ Net-_Q88-Pad2_ Net-_Q76-Pad1_ eSim_PNP +Q92 Net-_Q88-Pad2_ Net-_Q88-Pad2_ Net-_Q76-Pad1_ eSim_PNP +Q74 Net-_J1-Pad2_ Net-_Q74-Pad2_ Net-_Q74-Pad3_ eSim_PNP +Q80 Net-_Q72-Pad2_ Net-_Q72-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q86 Net-_C4-Pad2_ Net-_Q72-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q96 Net-_J1-Pad2_ Net-_Q96-Pad2_ Net-_Q88-Pad2_ eSim_PNP +Q98 Net-_J1-Pad2_ Net-_C4-Pad2_ Net-_Q100-Pad2_ eSim_PNP +Q100 Net-_Q100-Pad1_ Net-_Q100-Pad2_ Net-_Q100-Pad3_ eSim_NPN +Q102 Net-_Q100-Pad3_ Net-_Q102-Pad2_ Net-_Q102-Pad3_ eSim_NPN +R20 Net-_Q102-Pad3_ Net-_J1-Pad2_ 12k +Q104 Net-_J1-Pad2_ Net-_Q102-Pad2_ Net-_Q100-Pad1_ eSim_PNP +Q106 Net-_Q102-Pad2_ Net-_Q102-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q108 Net-_Q108-Pad1_ Net-_Q108-Pad2_ Net-_Q108-Pad3_ eSim_NPN +R22 Net-_Q108-Pad3_ Net-_J1-Pad2_ 0.7k +Q110 Net-_C4-Pad1_ Net-_Q100-Pad3_ Net-_J1-Pad2_ eSim_NPN +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 8p +Q121 Net-_Q120-Pad3_ Net-_Q121-Pad2_ Net-_Q121-Pad3_ eSim_NPN +Q122 Net-_Q121-Pad3_ Net-_Q102-Pad2_ Net-_J1-Pad2_ eSim_NPN +R27 Net-_Q120-Pad3_ Net-_Q121-Pad2_ 31k +R28 Net-_Q121-Pad2_ Net-_Q121-Pad3_ 37k +Q127 Net-_J1-Pad1_ Net-_Q116-Pad3_ Net-_Q127-Pad3_ eSim_NPN +R30 Net-_Q127-Pad3_ Net-_Q128-Pad3_ 25 +Q128 Net-_J1-Pad2_ Net-_Q124-Pad3_ Net-_Q128-Pad3_ eSim_PNP +Q124 Net-_J1-Pad2_ Net-_Q121-Pad3_ Net-_Q124-Pad3_ eSim_PNP +Q130 Net-_C4-Pad1_ Net-_Q127-Pad3_ Net-_Q128-Pad3_ eSim_NPN +Q133 Net-_J4-Pad3_ Net-_J4-Pad3_ Net-_Q108-Pad2_ eSim_NPN +Q136 Net-_J1-Pad1_ Net-_J4-Pad3_ Net-_Q134-Pad2_ eSim_NPN +J4 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J4-Pad3_ jfet_n +Q134 Net-_Q108-Pad2_ Net-_Q134-Pad2_ Net-_J1-Pad2_ eSim_NPN +R32 Net-_Q134-Pad2_ Net-_J1-Pad2_ 8.2k +U1 Net-_Q58-Pad3_ Net-_Q3-Pad2_ Net-_Q25-Pad2_ Net-_J1-Pad1_ Net-_Q28-Pad2_ Net-_Q9-Pad2_ Net-_Q60-Pad3_ Net-_Q126-Pad3_ Net-_Q73-Pad2_ Net-_Q95-Pad2_ Net-_J1-Pad2_ Net-_Q96-Pad2_ Net-_Q74-Pad2_ Net-_Q128-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir.out b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir.out new file mode 100644 index 00000000..36e3635e --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir.out @@ -0,0 +1,183 @@ +* d:\fossee\esim\library\subcircuitlibrary\mc3403_ic\mc3403_ic.cir + +.include NPN.lib +.include PNP.lib +.include NJF.lib +q19 net-_q19-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q22 net-_q22-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q42 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q43 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q47 net-_j1-pad1_ net-_c1-pad1_ net-_q47-pad3_ Q2N2222 +q49 net-_j1-pad1_ net-_q47-pad3_ net-_q49-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q12-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q12-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q12-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q18 net-_c1-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q21 net-_q18-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q12-pad2_ Q2N2907A +q8 net-_q12-pad1_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q16 net-_c1-pad2_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q25 net-_j1-pad2_ net-_q25-pad2_ net-_q18-pad2_ Q2N2907A +q29 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q30 net-_q19-pad1_ net-_q10-pad1_ net-_q30-pad3_ Q2N2222 +q32 net-_q30-pad3_ net-_q22-pad1_ net-_q32-pad3_ Q2N2222 +r3 net-_q32-pad3_ net-_j1-pad2_ 12k +q35 net-_j1-pad2_ net-_q22-pad1_ net-_q19-pad1_ Q2N2907A +q37 net-_q22-pad1_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +q39 net-_q1-pad2_ net-_q39-pad2_ net-_q39-pad3_ Q2N2222 +r5 net-_q39-pad3_ net-_j1-pad2_ 0.7k +q41 net-_c1-pad1_ net-_q30-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 8p +q50 net-_q49-pad3_ net-_q50-pad2_ net-_q50-pad3_ Q2N2222 +q51 net-_q50-pad3_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +r9 net-_q49-pad3_ net-_q50-pad2_ 31k +r10 net-_q50-pad2_ net-_q50-pad3_ 37k +q57 net-_j1-pad1_ net-_q47-pad3_ net-_q57-pad3_ Q2N2222 +r13 net-_q57-pad3_ net-_q58-pad3_ 25 +q58 net-_j1-pad2_ net-_q55-pad3_ net-_q58-pad3_ Q2N2907A +q55 net-_j1-pad2_ net-_q50-pad3_ net-_q55-pad3_ Q2N2907A +q61 net-_c1-pad1_ net-_q57-pad3_ net-_q58-pad3_ Q2N2222 +q63 net-_j1-pad3_ net-_j1-pad3_ net-_q39-pad2_ Q2N2222 +q67 net-_j1-pad1_ net-_j1-pad3_ net-_q64-pad2_ Q2N2222 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q64 net-_q39-pad2_ net-_q64-pad2_ net-_j1-pad2_ Q2N2222 +r15 net-_q64-pad2_ net-_j1-pad2_ 8.2k +q89 net-_q103-pad3_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q93 net-_q101-pad2_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q111 net-_q107-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q113 net-_c3-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q115 net-_j1-pad1_ net-_c3-pad1_ net-_q115-pad3_ Q2N2222 +q117 net-_j1-pad1_ net-_q115-pad3_ net-_q117-pad3_ Q2N2222 +q81 net-_q81-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q75 net-_q75-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q69 net-_q69-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q71 net-_j1-pad2_ net-_q71-pad2_ net-_q69-pad1_ Q2N2907A +q77 net-_q73-pad3_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q83 net-_q71-pad2_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q87 net-_c3-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q91 net-_q87-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q73 net-_j1-pad2_ net-_q73-pad2_ net-_q73-pad3_ Q2N2907A +q79 net-_q71-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q85 net-_c3-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q95 net-_j1-pad2_ net-_q95-pad2_ net-_q87-pad2_ Q2N2907A +q97 net-_j1-pad2_ net-_c3-pad2_ net-_q81-pad1_ Q2N2907A +q99 net-_q103-pad3_ net-_q81-pad1_ net-_q101-pad1_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad2_ net-_q101-pad3_ Q2N2222 +r19 net-_q101-pad3_ net-_j1-pad2_ 12k +q103 net-_j1-pad2_ net-_q101-pad2_ net-_q103-pad3_ Q2N2907A +q105 net-_q101-pad2_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +q107 net-_q107-pad1_ net-_q107-pad2_ net-_q107-pad3_ Q2N2222 +r21 net-_q107-pad3_ net-_j1-pad2_ 0.7k +q109 net-_c3-pad1_ net-_q101-pad1_ net-_j1-pad2_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 8p +q118 net-_q117-pad3_ net-_q118-pad2_ net-_q118-pad3_ Q2N2222 +q119 net-_q118-pad3_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +r25 net-_q117-pad3_ net-_q118-pad2_ 31k +r26 net-_q118-pad2_ net-_q118-pad3_ 37k +q125 net-_j1-pad1_ net-_q115-pad3_ net-_q125-pad3_ Q2N2222 +r29 net-_q125-pad3_ net-_q126-pad3_ 25 +q126 net-_j1-pad2_ net-_q123-pad3_ net-_q126-pad3_ Q2N2907A +q123 net-_j1-pad2_ net-_q118-pad3_ net-_q123-pad3_ Q2N2907A +q129 net-_c3-pad1_ net-_q125-pad3_ net-_q126-pad3_ Q2N2222 +q131 net-_j3-pad3_ net-_j3-pad3_ net-_q107-pad2_ Q2N2222 +q135 net-_j1-pad1_ net-_j3-pad3_ net-_q132-pad2_ Q2N2222 +j3 net-_j1-pad1_ net-_j1-pad2_ net-_j3-pad3_ J2N3819 +q132 net-_q107-pad2_ net-_q132-pad2_ net-_j1-pad2_ Q2N2222 +r31 net-_q132-pad2_ net-_j1-pad2_ 8.2k +q24 net-_q24-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q27 net-_q27-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q45 net-_q11-pad2_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q46 net-_c2-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q48 net-_j1-pad1_ net-_c2-pad1_ net-_q48-pad3_ Q2N2222 +q52 net-_j1-pad1_ net-_q48-pad3_ net-_q52-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q5 net-_q5-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_j1-pad2_ net-_q14-pad1_ net-_q5-pad1_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q17 net-_q14-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q23 net-_c2-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q26 net-_q23-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q9 net-_j1-pad2_ net-_q9-pad2_ net-_q13-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q20 net-_c2-pad2_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_j1-pad2_ net-_q28-pad2_ net-_q23-pad2_ Q2N2907A +q31 net-_j1-pad2_ net-_c2-pad2_ net-_q15-pad1_ Q2N2907A +q33 net-_q24-pad1_ net-_q15-pad1_ net-_q33-pad3_ Q2N2222 +q34 net-_q33-pad3_ net-_q27-pad1_ net-_q34-pad3_ Q2N2222 +r4 net-_q34-pad3_ net-_j1-pad2_ 12k +q36 net-_j1-pad2_ net-_q27-pad1_ net-_q24-pad1_ Q2N2907A +q38 net-_q27-pad1_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +q40 net-_q11-pad2_ net-_q40-pad2_ net-_q40-pad3_ Q2N2222 +r6 net-_q40-pad3_ net-_j1-pad2_ 0.7k +q44 net-_c2-pad1_ net-_q33-pad3_ net-_j1-pad2_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 8p +q53 net-_q52-pad3_ net-_q53-pad2_ net-_q53-pad3_ Q2N2222 +q54 net-_q53-pad3_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +r11 net-_q52-pad3_ net-_q53-pad2_ 31k +r12 net-_q53-pad2_ net-_q53-pad3_ 37k +q59 net-_j1-pad1_ net-_q48-pad3_ net-_q59-pad3_ Q2N2222 +r14 net-_q59-pad3_ net-_q60-pad3_ 25 +q60 net-_j1-pad2_ net-_q56-pad3_ net-_q60-pad3_ Q2N2907A +q56 net-_j1-pad2_ net-_q53-pad3_ net-_q56-pad3_ Q2N2907A +q62 net-_c2-pad1_ net-_q59-pad3_ net-_q60-pad3_ Q2N2222 +q65 net-_j2-pad3_ net-_j2-pad3_ net-_q40-pad2_ Q2N2222 +q68 net-_j1-pad1_ net-_j2-pad3_ net-_q66-pad2_ Q2N2222 +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j2-pad3_ J2N3819 +q66 net-_q40-pad2_ net-_q66-pad2_ net-_j1-pad2_ Q2N2222 +r16 net-_q66-pad2_ net-_j1-pad2_ 8.2k +q90 net-_q100-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q94 net-_q102-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q112 net-_q108-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q114 net-_c4-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q116 net-_j1-pad1_ net-_c4-pad1_ net-_q116-pad3_ Q2N2222 +q120 net-_j1-pad1_ net-_q116-pad3_ net-_q120-pad3_ Q2N2222 +q82 net-_q100-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q76 net-_q76-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q70 net-_q70-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q72 net-_j1-pad2_ net-_q72-pad2_ net-_q70-pad1_ Q2N2907A +q78 net-_q74-pad3_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q84 net-_q72-pad2_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q88 net-_c4-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q92 net-_q88-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q74 net-_j1-pad2_ net-_q74-pad2_ net-_q74-pad3_ Q2N2907A +q80 net-_q72-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q86 net-_c4-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q96 net-_j1-pad2_ net-_q96-pad2_ net-_q88-pad2_ Q2N2907A +q98 net-_j1-pad2_ net-_c4-pad2_ net-_q100-pad2_ Q2N2907A +q100 net-_q100-pad1_ net-_q100-pad2_ net-_q100-pad3_ Q2N2222 +q102 net-_q100-pad3_ net-_q102-pad2_ net-_q102-pad3_ Q2N2222 +r20 net-_q102-pad3_ net-_j1-pad2_ 12k +q104 net-_j1-pad2_ net-_q102-pad2_ net-_q100-pad1_ Q2N2907A +q106 net-_q102-pad2_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +q108 net-_q108-pad1_ net-_q108-pad2_ net-_q108-pad3_ Q2N2222 +r22 net-_q108-pad3_ net-_j1-pad2_ 0.7k +q110 net-_c4-pad1_ net-_q100-pad3_ net-_j1-pad2_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 8p +q121 net-_q120-pad3_ net-_q121-pad2_ net-_q121-pad3_ Q2N2222 +q122 net-_q121-pad3_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +r27 net-_q120-pad3_ net-_q121-pad2_ 31k +r28 net-_q121-pad2_ net-_q121-pad3_ 37k +q127 net-_j1-pad1_ net-_q116-pad3_ net-_q127-pad3_ Q2N2222 +r30 net-_q127-pad3_ net-_q128-pad3_ 25 +q128 net-_j1-pad2_ net-_q124-pad3_ net-_q128-pad3_ Q2N2907A +q124 net-_j1-pad2_ net-_q121-pad3_ net-_q124-pad3_ Q2N2907A +q130 net-_c4-pad1_ net-_q127-pad3_ net-_q128-pad3_ Q2N2222 +q133 net-_j4-pad3_ net-_j4-pad3_ net-_q108-pad2_ Q2N2222 +q136 net-_j1-pad1_ net-_j4-pad3_ net-_q134-pad2_ Q2N2222 +j4 net-_j1-pad1_ net-_j1-pad2_ net-_j4-pad3_ J2N3819 +q134 net-_q108-pad2_ net-_q134-pad2_ net-_j1-pad2_ Q2N2222 +r32 net-_q134-pad2_ net-_j1-pad2_ 8.2k +* u1 net-_q58-pad3_ net-_q3-pad2_ net-_q25-pad2_ net-_j1-pad1_ net-_q28-pad2_ net-_q9-pad2_ net-_q60-pad3_ net-_q126-pad3_ net-_q73-pad2_ net-_q95-pad2_ net-_j1-pad2_ net-_q96-pad2_ net-_q74-pad2_ net-_q128-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.pro b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sch b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sch new file mode 100644 index 00000000..f2268e6b --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sch @@ -0,0 +1,3447 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC3403_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 47244 39370 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q19 +U 1 1 66882D3A +P 4750 5450 +F 0 "Q19" H 4650 5500 50 0000 R CNN +F 1 "eSim_PNP" H 4700 5600 50 0000 R CNN +F 2 "" H 4950 5550 29 0000 C CNN +F 3 "" H 4750 5450 60 0000 C CNN + 1 4750 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q22 +U 1 1 66882D3B +P 5200 5450 +F 0 "Q22" H 5100 5500 50 0000 R CNN +F 1 "eSim_PNP" H 5150 5600 50 0000 R CNN +F 2 "" H 5400 5550 29 0000 C CNN +F 3 "" H 5200 5450 60 0000 C CNN + 1 5200 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q42 +U 1 1 66882D3C +P 11850 5450 +F 0 "Q42" H 11750 5500 50 0000 R CNN +F 1 "eSim_PNP" H 11800 5600 50 0000 R CNN +F 2 "" H 12050 5550 29 0000 C CNN +F 3 "" H 11850 5450 60 0000 C CNN + 1 11850 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q43 +U 1 1 66882D3D +P 12250 5450 +F 0 "Q43" H 12150 5500 50 0000 R CNN +F 1 "eSim_PNP" H 12200 5600 50 0000 R CNN +F 2 "" H 12450 5550 29 0000 C CNN +F 3 "" H 12250 5450 60 0000 C CNN + 1 12250 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q47 +U 1 1 66882D3E +P 13600 6150 +F 0 "Q47" H 13500 6200 50 0000 R CNN +F 1 "eSim_NPN" H 13550 6300 50 0000 R CNN +F 2 "" H 13800 6250 29 0000 C CNN +F 3 "" H 13600 6150 60 0000 C CNN + 1 13600 6150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q49 +U 1 1 66882D3F +P 14150 6450 +F 0 "Q49" H 14050 6500 50 0000 R CNN +F 1 "eSim_NPN" H 14100 6600 50 0000 R CNN +F 2 "" H 14350 6550 29 0000 C CNN +F 3 "" H 14150 6450 60 0000 C CNN + 1 14150 6450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 66882D40 +P 3850 7000 +F 0 "Q10" H 3750 7050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 7150 50 0000 R CNN +F 2 "" H 4050 7100 29 0000 C CNN +F 3 "" H 3850 7000 60 0000 C CNN + 1 3850 7000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 66882D41 +P 3400 7000 +F 0 "Q4" H 3300 7050 50 0000 R CNN +F 1 "eSim_PNP" H 3350 7150 50 0000 R CNN +F 2 "" H 3600 7100 29 0000 C CNN +F 3 "" H 3400 7000 60 0000 C CNN + 1 3400 7000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 66882D42 +P 2900 7000 +F 0 "Q1" H 2800 7050 50 0000 R CNN +F 1 "eSim_PNP" H 2850 7150 50 0000 R CNN +F 2 "" H 3100 7100 29 0000 C CNN +F 3 "" H 2900 7000 60 0000 C CNN + 1 2900 7000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 66882D43 +P 3050 11750 +F 0 "Q2" H 2950 11800 50 0000 R CNN +F 1 "eSim_PNP" H 3000 11900 50 0000 R CNN +F 2 "" H 3250 11850 29 0000 C CNN +F 3 "" H 3050 11750 60 0000 C CNN + 1 3050 11750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 66882D44 +P 3650 9050 +F 0 "Q7" H 3550 9100 50 0000 R CNN +F 1 "eSim_PNP" H 3600 9200 50 0000 R CNN +F 2 "" H 3850 9150 29 0000 C CNN +F 3 "" H 3650 9050 60 0000 C CNN + 1 3650 9050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 66882D45 +P 4050 9050 +F 0 "Q12" H 3950 9100 50 0000 R CNN +F 1 "eSim_PNP" H 4000 9200 50 0000 R CNN +F 2 "" H 4250 9150 29 0000 C CNN +F 3 "" H 4050 9050 60 0000 C CNN + 1 4050 9050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q18 +U 1 1 66882D46 +P 4700 9050 +F 0 "Q18" H 4600 9100 50 0000 R CNN +F 1 "eSim_PNP" H 4650 9200 50 0000 R CNN +F 2 "" H 4900 9150 29 0000 C CNN +F 3 "" H 4700 9050 60 0000 C CNN + 1 4700 9050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q21 +U 1 1 66882D47 +P 5150 9050 +F 0 "Q21" H 5050 9100 50 0000 R CNN +F 1 "eSim_PNP" H 5100 9200 50 0000 R CNN +F 2 "" H 5350 9150 29 0000 C CNN +F 3 "" H 5150 9050 60 0000 C CNN + 1 5150 9050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 66882D48 +P 3250 10350 +F 0 "Q3" H 3150 10400 50 0000 R CNN +F 1 "eSim_PNP" H 3200 10500 50 0000 R CNN +F 2 "" H 3450 10450 29 0000 C CNN +F 3 "" H 3250 10350 60 0000 C CNN + 1 3250 10350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 66882D49 +P 3700 12100 +F 0 "Q8" H 3600 12150 50 0000 R CNN +F 1 "eSim_NPN" H 3650 12250 50 0000 R CNN +F 2 "" H 3900 12200 29 0000 C CNN +F 3 "" H 3700 12100 60 0000 C CNN + 1 3700 12100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 66882D4A +P 4400 12100 +F 0 "Q16" H 4300 12150 50 0000 R CNN +F 1 "eSim_NPN" H 4350 12250 50 0000 R CNN +F 2 "" H 4600 12200 29 0000 C CNN +F 3 "" H 4400 12100 60 0000 C CNN + 1 4400 12100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q25 +U 1 1 66882D4B +P 5600 10400 +F 0 "Q25" H 5500 10450 50 0000 R CNN +F 1 "eSim_PNP" H 5550 10550 50 0000 R CNN +F 2 "" H 5800 10500 29 0000 C CNN +F 3 "" H 5600 10400 60 0000 C CNN + 1 5600 10400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q29 +U 1 1 66882D4C +P 6550 11900 +F 0 "Q29" H 6450 11950 50 0000 R CNN +F 1 "eSim_PNP" H 6500 12050 50 0000 R CNN +F 2 "" H 6750 12000 29 0000 C CNN +F 3 "" H 6550 11900 60 0000 C CNN + 1 6550 11900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q30 +U 1 1 66882D4D +P 7050 10400 +F 0 "Q30" H 6950 10450 50 0000 R CNN +F 1 "eSim_NPN" H 7000 10550 50 0000 R CNN +F 2 "" H 7250 10500 29 0000 C CNN +F 3 "" H 7050 10400 60 0000 C CNN + 1 7050 10400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q32 +U 1 1 66882D4E +P 7250 11200 +F 0 "Q32" H 7150 11250 50 0000 R CNN +F 1 "eSim_NPN" H 7200 11350 50 0000 R CNN +F 2 "" H 7450 11300 29 0000 C CNN +F 3 "" H 7250 11200 60 0000 C CNN + 1 7250 11200 + -1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 66882D4F +P 7100 11850 +F 0 "R3" H 7150 11980 50 0000 C CNN +F 1 "12k" H 7150 11800 50 0000 C CNN +F 2 "" H 7150 11830 30 0000 C CNN +F 3 "" V 7150 11900 30 0000 C CNN + 1 7100 11850 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q35 +U 1 1 66882D50 +P 8150 10400 +F 0 "Q35" H 8050 10450 50 0000 R CNN +F 1 "eSim_PNP" H 8100 10550 50 0000 R CNN +F 2 "" H 8350 10500 29 0000 C CNN +F 3 "" H 8150 10400 60 0000 C CNN + 1 8150 10400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q37 +U 1 1 66882D51 +P 9250 11200 +F 0 "Q37" H 9150 11250 50 0000 R CNN +F 1 "eSim_NPN" H 9200 11350 50 0000 R CNN +F 2 "" H 9450 11300 29 0000 C CNN +F 3 "" H 9250 11200 60 0000 C CNN + 1 9250 11200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q39 +U 1 1 66882D52 +P 10350 7700 +F 0 "Q39" H 10250 7750 50 0000 R CNN +F 1 "eSim_NPN" H 10300 7850 50 0000 R CNN +F 2 "" H 10550 7800 29 0000 C CNN +F 3 "" H 10350 7700 60 0000 C CNN + 1 10350 7700 + -1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 66882D53 +P 10200 8200 +F 0 "R5" H 10250 8330 50 0000 C CNN +F 1 "0.7k" H 10250 8150 50 0000 C CNN +F 2 "" H 10250 8180 30 0000 C CNN +F 3 "" V 10250 8250 30 0000 C CNN + 1 10200 8200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q41 +U 1 1 66882D54 +P 11800 9500 +F 0 "Q41" H 11700 9550 50 0000 R CNN +F 1 "eSim_NPN" H 11750 9650 50 0000 R CNN +F 2 "" H 12000 9600 29 0000 C CNN +F 3 "" H 11800 9500 60 0000 C CNN + 1 11800 9500 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 66882D55 +P 6250 7900 +F 0 "C1" H 6275 8000 50 0000 L CNN +F 1 "8p" H 6275 7800 50 0000 L CNN +F 2 "" H 6288 7750 30 0000 C CNN +F 3 "" H 6250 7900 60 0000 C CNN + 1 6250 7900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q50 +U 1 1 66882D56 +P 14150 9100 +F 0 "Q50" H 14050 9150 50 0000 R CNN +F 1 "eSim_NPN" H 14100 9250 50 0000 R CNN +F 2 "" H 14350 9200 29 0000 C CNN +F 3 "" H 14150 9100 60 0000 C CNN + 1 14150 9100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q51 +U 1 1 66882D57 +P 14150 11400 +F 0 "Q51" H 14050 11450 50 0000 R CNN +F 1 "eSim_NPN" H 14100 11550 50 0000 R CNN +F 2 "" H 14350 11500 29 0000 C CNN +F 3 "" H 14150 11400 60 0000 C CNN + 1 14150 11400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 66882D58 +P 13450 7100 +F 0 "R9" H 13500 7230 50 0000 C CNN +F 1 "31k" H 13500 7050 50 0000 C CNN +F 2 "" H 13500 7080 30 0000 C CNN +F 3 "" V 13500 7150 30 0000 C CNN + 1 13450 7100 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 66882D59 +P 13450 9650 +F 0 "R10" H 13500 9780 50 0000 C CNN +F 1 "37k" H 13500 9600 50 0000 C CNN +F 2 "" H 13500 9630 30 0000 C CNN +F 3 "" V 13500 9700 30 0000 C CNN + 1 13450 9650 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q57 +U 1 1 66882D5A +P 15850 6450 +F 0 "Q57" H 15750 6500 50 0000 R CNN +F 1 "eSim_NPN" H 15800 6600 50 0000 R CNN +F 2 "" H 16050 6550 29 0000 C CNN +F 3 "" H 15850 6450 60 0000 C CNN + 1 15850 6450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 66882D5B +P 15900 8200 +F 0 "R13" H 15950 8330 50 0000 C CNN +F 1 "25" H 15950 8150 50 0000 C CNN +F 2 "" H 15950 8180 30 0000 C CNN +F 3 "" V 15950 8250 30 0000 C CNN + 1 15900 8200 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q58 +U 1 1 66882D5C +P 15850 9200 +F 0 "Q58" H 15750 9250 50 0000 R CNN +F 1 "eSim_PNP" H 15800 9350 50 0000 R CNN +F 2 "" H 16050 9300 29 0000 C CNN +F 3 "" H 15850 9200 60 0000 C CNN + 1 15850 9200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q55 +U 1 1 66882D5D +P 15300 10150 +F 0 "Q55" H 15200 10200 50 0000 R CNN +F 1 "eSim_PNP" H 15250 10300 50 0000 R CNN +F 2 "" H 15500 10250 29 0000 C CNN +F 3 "" H 15300 10150 60 0000 C CNN + 1 15300 10150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q61 +U 1 1 66882D5E +P 16650 7800 +F 0 "Q61" H 16550 7850 50 0000 R CNN +F 1 "eSim_NPN" H 16600 7950 50 0000 R CNN +F 2 "" H 16850 7900 29 0000 C CNN +F 3 "" H 16650 7800 60 0000 C CNN + 1 16650 7800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q63 +U 1 1 66882D60 +P 18300 6400 +F 0 "Q63" H 18200 6450 50 0000 R CNN +F 1 "eSim_NPN" H 18250 6550 50 0000 R CNN +F 2 "" H 18500 6500 29 0000 C CNN +F 3 "" H 18300 6400 60 0000 C CNN + 1 18300 6400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q67 +U 1 1 66882D61 +P 19400 6400 +F 0 "Q67" H 19300 6450 50 0000 R CNN +F 1 "eSim_NPN" H 19350 6550 50 0000 R CNN +F 2 "" H 19600 6500 29 0000 C CNN +F 3 "" H 19400 6400 60 0000 C CNN + 1 19400 6400 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J1 +U 1 1 66882D62 +P 18300 5400 +F 0 "J1" H 18200 5450 50 0000 R CNN +F 1 "jfet_n" H 18250 5550 50 0000 R CNN +F 2 "" H 18500 5500 29 0000 C CNN +F 3 "" H 18300 5400 60 0000 C CNN + 1 18300 5400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q64 +U 1 1 66882D63 +P 18300 10300 +F 0 "Q64" H 18200 10350 50 0000 R CNN +F 1 "eSim_NPN" H 18250 10450 50 0000 R CNN +F 2 "" H 18500 10400 29 0000 C CNN +F 3 "" H 18300 10300 60 0000 C CNN + 1 18300 10300 + -1 0 0 -1 +$EndComp +$Comp +L resistor R15 +U 1 1 66882D64 +P 19450 10900 +F 0 "R15" H 19500 11030 50 0000 C CNN +F 1 "8.2k" H 19500 10850 50 0000 C CNN +F 2 "" H 19500 10880 30 0000 C CNN +F 3 "" V 19500 10950 30 0000 C CNN + 1 19450 10900 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q89 +U 1 1 66883B02 +P 26900 5850 +F 0 "Q89" H 26800 5900 50 0000 R CNN +F 1 "eSim_PNP" H 26850 6000 50 0000 R CNN +F 2 "" H 27100 5950 29 0000 C CNN +F 3 "" H 26900 5850 60 0000 C CNN + 1 26900 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q93 +U 1 1 66883B08 +P 27350 5850 +F 0 "Q93" H 27250 5900 50 0000 R CNN +F 1 "eSim_PNP" H 27300 6000 50 0000 R CNN +F 2 "" H 27550 5950 29 0000 C CNN +F 3 "" H 27350 5850 60 0000 C CNN + 1 27350 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q111 +U 1 1 66883B0E +P 34000 5850 +F 0 "Q111" H 33900 5900 50 0000 R CNN +F 1 "eSim_PNP" H 33950 6000 50 0000 R CNN +F 2 "" H 34200 5950 29 0000 C CNN +F 3 "" H 34000 5850 60 0000 C CNN + 1 34000 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q113 +U 1 1 66883B14 +P 34400 5850 +F 0 "Q113" H 34300 5900 50 0000 R CNN +F 1 "eSim_PNP" H 34350 6000 50 0000 R CNN +F 2 "" H 34600 5950 29 0000 C CNN +F 3 "" H 34400 5850 60 0000 C CNN + 1 34400 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q115 +U 1 1 66883B1A +P 35750 6550 +F 0 "Q115" H 35650 6600 50 0000 R CNN +F 1 "eSim_NPN" H 35700 6700 50 0000 R CNN +F 2 "" H 35950 6650 29 0000 C CNN +F 3 "" H 35750 6550 60 0000 C CNN + 1 35750 6550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q117 +U 1 1 66883B20 +P 36300 6850 +F 0 "Q117" H 36200 6900 50 0000 R CNN +F 1 "eSim_NPN" H 36250 7000 50 0000 R CNN +F 2 "" H 36500 6950 29 0000 C CNN +F 3 "" H 36300 6850 60 0000 C CNN + 1 36300 6850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q81 +U 1 1 66883B26 +P 26000 7400 +F 0 "Q81" H 25900 7450 50 0000 R CNN +F 1 "eSim_PNP" H 25950 7550 50 0000 R CNN +F 2 "" H 26200 7500 29 0000 C CNN +F 3 "" H 26000 7400 60 0000 C CNN + 1 26000 7400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q75 +U 1 1 66883B2C +P 25550 7400 +F 0 "Q75" H 25450 7450 50 0000 R CNN +F 1 "eSim_PNP" H 25500 7550 50 0000 R CNN +F 2 "" H 25750 7500 29 0000 C CNN +F 3 "" H 25550 7400 60 0000 C CNN + 1 25550 7400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q69 +U 1 1 66883B32 +P 25050 7400 +F 0 "Q69" H 24950 7450 50 0000 R CNN +F 1 "eSim_PNP" H 25000 7550 50 0000 R CNN +F 2 "" H 25250 7500 29 0000 C CNN +F 3 "" H 25050 7400 60 0000 C CNN + 1 25050 7400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q71 +U 1 1 66883B38 +P 25200 12150 +F 0 "Q71" H 25100 12200 50 0000 R CNN +F 1 "eSim_PNP" H 25150 12300 50 0000 R CNN +F 2 "" H 25400 12250 29 0000 C CNN +F 3 "" H 25200 12150 60 0000 C CNN + 1 25200 12150 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q77 +U 1 1 66883B3E +P 25800 9450 +F 0 "Q77" H 25700 9500 50 0000 R CNN +F 1 "eSim_PNP" H 25750 9600 50 0000 R CNN +F 2 "" H 26000 9550 29 0000 C CNN +F 3 "" H 25800 9450 60 0000 C CNN + 1 25800 9450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q83 +U 1 1 66883B44 +P 26200 9450 +F 0 "Q83" H 26100 9500 50 0000 R CNN +F 1 "eSim_PNP" H 26150 9600 50 0000 R CNN +F 2 "" H 26400 9550 29 0000 C CNN +F 3 "" H 26200 9450 60 0000 C CNN + 1 26200 9450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q87 +U 1 1 66883B4A +P 26850 9450 +F 0 "Q87" H 26750 9500 50 0000 R CNN +F 1 "eSim_PNP" H 26800 9600 50 0000 R CNN +F 2 "" H 27050 9550 29 0000 C CNN +F 3 "" H 26850 9450 60 0000 C CNN + 1 26850 9450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q91 +U 1 1 66883B50 +P 27300 9450 +F 0 "Q91" H 27200 9500 50 0000 R CNN +F 1 "eSim_PNP" H 27250 9600 50 0000 R CNN +F 2 "" H 27500 9550 29 0000 C CNN +F 3 "" H 27300 9450 60 0000 C CNN + 1 27300 9450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q73 +U 1 1 66883B56 +P 25400 10750 +F 0 "Q73" H 25300 10800 50 0000 R CNN +F 1 "eSim_PNP" H 25350 10900 50 0000 R CNN +F 2 "" H 25600 10850 29 0000 C CNN +F 3 "" H 25400 10750 60 0000 C CNN + 1 25400 10750 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q79 +U 1 1 66883B5C +P 25850 12500 +F 0 "Q79" H 25750 12550 50 0000 R CNN +F 1 "eSim_NPN" H 25800 12650 50 0000 R CNN +F 2 "" H 26050 12600 29 0000 C CNN +F 3 "" H 25850 12500 60 0000 C CNN + 1 25850 12500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q85 +U 1 1 66883B62 +P 26550 12500 +F 0 "Q85" H 26450 12550 50 0000 R CNN +F 1 "eSim_NPN" H 26500 12650 50 0000 R CNN +F 2 "" H 26750 12600 29 0000 C CNN +F 3 "" H 26550 12500 60 0000 C CNN + 1 26550 12500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q95 +U 1 1 66883B68 +P 27750 10800 +F 0 "Q95" H 27650 10850 50 0000 R CNN +F 1 "eSim_PNP" H 27700 10950 50 0000 R CNN +F 2 "" H 27950 10900 29 0000 C CNN +F 3 "" H 27750 10800 60 0000 C CNN + 1 27750 10800 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q97 +U 1 1 66883B6E +P 28700 12300 +F 0 "Q97" H 28600 12350 50 0000 R CNN +F 1 "eSim_PNP" H 28650 12450 50 0000 R CNN +F 2 "" H 28900 12400 29 0000 C CNN +F 3 "" H 28700 12300 60 0000 C CNN + 1 28700 12300 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q99 +U 1 1 66883B74 +P 29200 10800 +F 0 "Q99" H 29100 10850 50 0000 R CNN +F 1 "eSim_NPN" H 29150 10950 50 0000 R CNN +F 2 "" H 29400 10900 29 0000 C CNN +F 3 "" H 29200 10800 60 0000 C CNN + 1 29200 10800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q101 +U 1 1 66883B7A +P 29400 11600 +F 0 "Q101" H 29300 11650 50 0000 R CNN +F 1 "eSim_NPN" H 29350 11750 50 0000 R CNN +F 2 "" H 29600 11700 29 0000 C CNN +F 3 "" H 29400 11600 60 0000 C CNN + 1 29400 11600 + -1 0 0 -1 +$EndComp +$Comp +L resistor R19 +U 1 1 66883B80 +P 29250 12250 +F 0 "R19" H 29300 12380 50 0000 C CNN +F 1 "12k" H 29300 12200 50 0000 C CNN +F 2 "" H 29300 12230 30 0000 C CNN +F 3 "" V 29300 12300 30 0000 C CNN + 1 29250 12250 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q103 +U 1 1 66883B86 +P 30300 10800 +F 0 "Q103" H 30200 10850 50 0000 R CNN +F 1 "eSim_PNP" H 30250 10950 50 0000 R CNN +F 2 "" H 30500 10900 29 0000 C CNN +F 3 "" H 30300 10800 60 0000 C CNN + 1 30300 10800 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q105 +U 1 1 66883B8C +P 31400 11600 +F 0 "Q105" H 31300 11650 50 0000 R CNN +F 1 "eSim_NPN" H 31350 11750 50 0000 R CNN +F 2 "" H 31600 11700 29 0000 C CNN +F 3 "" H 31400 11600 60 0000 C CNN + 1 31400 11600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q107 +U 1 1 66883B92 +P 32500 8100 +F 0 "Q107" H 32400 8150 50 0000 R CNN +F 1 "eSim_NPN" H 32450 8250 50 0000 R CNN +F 2 "" H 32700 8200 29 0000 C CNN +F 3 "" H 32500 8100 60 0000 C CNN + 1 32500 8100 + -1 0 0 -1 +$EndComp +$Comp +L resistor R21 +U 1 1 66883B98 +P 32350 8600 +F 0 "R21" H 32400 8730 50 0000 C CNN +F 1 "0.7k" H 32400 8550 50 0000 C CNN +F 2 "" H 32400 8580 30 0000 C CNN +F 3 "" V 32400 8650 30 0000 C CNN + 1 32350 8600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q109 +U 1 1 66883B9E +P 33950 9900 +F 0 "Q109" H 33850 9950 50 0000 R CNN +F 1 "eSim_NPN" H 33900 10050 50 0000 R CNN +F 2 "" H 34150 10000 29 0000 C CNN +F 3 "" H 33950 9900 60 0000 C CNN + 1 33950 9900 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C3 +U 1 1 66883BA4 +P 28400 8300 +F 0 "C3" H 28425 8400 50 0000 L CNN +F 1 "8p" H 28425 8200 50 0000 L CNN +F 2 "" H 28438 8150 30 0000 C CNN +F 3 "" H 28400 8300 60 0000 C CNN + 1 28400 8300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q118 +U 1 1 66883BAA +P 36300 9500 +F 0 "Q118" H 36200 9550 50 0000 R CNN +F 1 "eSim_NPN" H 36250 9650 50 0000 R CNN +F 2 "" H 36500 9600 29 0000 C CNN +F 3 "" H 36300 9500 60 0000 C CNN + 1 36300 9500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q119 +U 1 1 66883BB0 +P 36300 11800 +F 0 "Q119" H 36200 11850 50 0000 R CNN +F 1 "eSim_NPN" H 36250 11950 50 0000 R CNN +F 2 "" H 36500 11900 29 0000 C CNN +F 3 "" H 36300 11800 60 0000 C CNN + 1 36300 11800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R25 +U 1 1 66883BB6 +P 35600 7500 +F 0 "R25" H 35650 7630 50 0000 C CNN +F 1 "31k" H 35650 7450 50 0000 C CNN +F 2 "" H 35650 7480 30 0000 C CNN +F 3 "" V 35650 7550 30 0000 C CNN + 1 35600 7500 + 0 1 1 0 +$EndComp +$Comp +L resistor R26 +U 1 1 66883BBC +P 35600 10050 +F 0 "R26" H 35650 10180 50 0000 C CNN +F 1 "37k" H 35650 10000 50 0000 C CNN +F 2 "" H 35650 10030 30 0000 C CNN +F 3 "" V 35650 10100 30 0000 C CNN + 1 35600 10050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q125 +U 1 1 66883BC2 +P 38000 6850 +F 0 "Q125" H 37900 6900 50 0000 R CNN +F 1 "eSim_NPN" H 37950 7000 50 0000 R CNN +F 2 "" H 38200 6950 29 0000 C CNN +F 3 "" H 38000 6850 60 0000 C CNN + 1 38000 6850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R29 +U 1 1 66883BC8 +P 38050 8600 +F 0 "R29" H 38100 8730 50 0000 C CNN +F 1 "25" H 38100 8550 50 0000 C CNN +F 2 "" H 38100 8580 30 0000 C CNN +F 3 "" V 38100 8650 30 0000 C CNN + 1 38050 8600 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q126 +U 1 1 66883BCE +P 38000 9600 +F 0 "Q126" H 37900 9650 50 0000 R CNN +F 1 "eSim_PNP" H 37950 9750 50 0000 R CNN +F 2 "" H 38200 9700 29 0000 C CNN +F 3 "" H 38000 9600 60 0000 C CNN + 1 38000 9600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q123 +U 1 1 66883BD4 +P 37450 10550 +F 0 "Q123" H 37350 10600 50 0000 R CNN +F 1 "eSim_PNP" H 37400 10700 50 0000 R CNN +F 2 "" H 37650 10650 29 0000 C CNN +F 3 "" H 37450 10550 60 0000 C CNN + 1 37450 10550 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q129 +U 1 1 66883BDA +P 38800 8200 +F 0 "Q129" H 38700 8250 50 0000 R CNN +F 1 "eSim_NPN" H 38750 8350 50 0000 R CNN +F 2 "" H 39000 8300 29 0000 C CNN +F 3 "" H 38800 8200 60 0000 C CNN + 1 38800 8200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q131 +U 1 1 66883BE6 +P 40450 6800 +F 0 "Q131" H 40350 6850 50 0000 R CNN +F 1 "eSim_NPN" H 40400 6950 50 0000 R CNN +F 2 "" H 40650 6900 29 0000 C CNN +F 3 "" H 40450 6800 60 0000 C CNN + 1 40450 6800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q135 +U 1 1 66883BEC +P 41550 6800 +F 0 "Q135" H 41450 6850 50 0000 R CNN +F 1 "eSim_NPN" H 41500 6950 50 0000 R CNN +F 2 "" H 41750 6900 29 0000 C CNN +F 3 "" H 41550 6800 60 0000 C CNN + 1 41550 6800 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J3 +U 1 1 66883BF2 +P 40450 5800 +F 0 "J3" H 40350 5850 50 0000 R CNN +F 1 "jfet_n" H 40400 5950 50 0000 R CNN +F 2 "" H 40650 5900 29 0000 C CNN +F 3 "" H 40450 5800 60 0000 C CNN + 1 40450 5800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q132 +U 1 1 66883BF8 +P 40450 10700 +F 0 "Q132" H 40350 10750 50 0000 R CNN +F 1 "eSim_NPN" H 40400 10850 50 0000 R CNN +F 2 "" H 40650 10800 29 0000 C CNN +F 3 "" H 40450 10700 60 0000 C CNN + 1 40450 10700 + -1 0 0 -1 +$EndComp +$Comp +L resistor R31 +U 1 1 66883BFE +P 41600 11300 +F 0 "R31" H 41650 11430 50 0000 C CNN +F 1 "8.2k" H 41650 11250 50 0000 C CNN +F 2 "" H 41650 11280 30 0000 C CNN +F 3 "" V 41650 11350 30 0000 C CNN + 1 41600 11300 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q24 +U 1 1 66886F38 +P 5250 22400 +F 0 "Q24" H 5150 22450 50 0000 R CNN +F 1 "eSim_PNP" H 5200 22550 50 0000 R CNN +F 2 "" H 5450 22500 29 0000 C CNN +F 3 "" H 5250 22400 60 0000 C CNN + 1 5250 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q27 +U 1 1 66886F3E +P 5700 22400 +F 0 "Q27" H 5600 22450 50 0000 R CNN +F 1 "eSim_PNP" H 5650 22550 50 0000 R CNN +F 2 "" H 5900 22500 29 0000 C CNN +F 3 "" H 5700 22400 60 0000 C CNN + 1 5700 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q45 +U 1 1 66886F44 +P 12350 22400 +F 0 "Q45" H 12250 22450 50 0000 R CNN +F 1 "eSim_PNP" H 12300 22550 50 0000 R CNN +F 2 "" H 12550 22500 29 0000 C CNN +F 3 "" H 12350 22400 60 0000 C CNN + 1 12350 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q46 +U 1 1 66886F4A +P 12750 22400 +F 0 "Q46" H 12650 22450 50 0000 R CNN +F 1 "eSim_PNP" H 12700 22550 50 0000 R CNN +F 2 "" H 12950 22500 29 0000 C CNN +F 3 "" H 12750 22400 60 0000 C CNN + 1 12750 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q48 +U 1 1 66886F50 +P 14100 23100 +F 0 "Q48" H 14000 23150 50 0000 R CNN +F 1 "eSim_NPN" H 14050 23250 50 0000 R CNN +F 2 "" H 14300 23200 29 0000 C CNN +F 3 "" H 14100 23100 60 0000 C CNN + 1 14100 23100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q52 +U 1 1 66886F56 +P 14650 23400 +F 0 "Q52" H 14550 23450 50 0000 R CNN +F 1 "eSim_NPN" H 14600 23550 50 0000 R CNN +F 2 "" H 14850 23500 29 0000 C CNN +F 3 "" H 14650 23400 60 0000 C CNN + 1 14650 23400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 66886F5C +P 4350 23950 +F 0 "Q15" H 4250 24000 50 0000 R CNN +F 1 "eSim_PNP" H 4300 24100 50 0000 R CNN +F 2 "" H 4550 24050 29 0000 C CNN +F 3 "" H 4350 23950 60 0000 C CNN + 1 4350 23950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 66886F62 +P 3900 23950 +F 0 "Q11" H 3800 24000 50 0000 R CNN +F 1 "eSim_PNP" H 3850 24100 50 0000 R CNN +F 2 "" H 4100 24050 29 0000 C CNN +F 3 "" H 3900 23950 60 0000 C CNN + 1 3900 23950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 66886F68 +P 3400 23950 +F 0 "Q5" H 3300 24000 50 0000 R CNN +F 1 "eSim_PNP" H 3350 24100 50 0000 R CNN +F 2 "" H 3600 24050 29 0000 C CNN +F 3 "" H 3400 23950 60 0000 C CNN + 1 3400 23950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 66886F6E +P 3550 28700 +F 0 "Q6" H 3450 28750 50 0000 R CNN +F 1 "eSim_PNP" H 3500 28850 50 0000 R CNN +F 2 "" H 3750 28800 29 0000 C CNN +F 3 "" H 3550 28700 60 0000 C CNN + 1 3550 28700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q13 +U 1 1 66886F74 +P 4150 26000 +F 0 "Q13" H 4050 26050 50 0000 R CNN +F 1 "eSim_PNP" H 4100 26150 50 0000 R CNN +F 2 "" H 4350 26100 29 0000 C CNN +F 3 "" H 4150 26000 60 0000 C CNN + 1 4150 26000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 66886F7A +P 4550 26000 +F 0 "Q17" H 4450 26050 50 0000 R CNN +F 1 "eSim_PNP" H 4500 26150 50 0000 R CNN +F 2 "" H 4750 26100 29 0000 C CNN +F 3 "" H 4550 26000 60 0000 C CNN + 1 4550 26000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q23 +U 1 1 66886F80 +P 5200 26000 +F 0 "Q23" H 5100 26050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 26150 50 0000 R CNN +F 2 "" H 5400 26100 29 0000 C CNN +F 3 "" H 5200 26000 60 0000 C CNN + 1 5200 26000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q26 +U 1 1 66886F86 +P 5650 26000 +F 0 "Q26" H 5550 26050 50 0000 R CNN +F 1 "eSim_PNP" H 5600 26150 50 0000 R CNN +F 2 "" H 5850 26100 29 0000 C CNN +F 3 "" H 5650 26000 60 0000 C CNN + 1 5650 26000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 66886F8C +P 3750 27300 +F 0 "Q9" H 3650 27350 50 0000 R CNN +F 1 "eSim_PNP" H 3700 27450 50 0000 R CNN +F 2 "" H 3950 27400 29 0000 C CNN +F 3 "" H 3750 27300 60 0000 C CNN + 1 3750 27300 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 66886F92 +P 4200 29050 +F 0 "Q14" H 4100 29100 50 0000 R CNN +F 1 "eSim_NPN" H 4150 29200 50 0000 R CNN +F 2 "" H 4400 29150 29 0000 C CNN +F 3 "" H 4200 29050 60 0000 C CNN + 1 4200 29050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 66886F98 +P 4900 29050 +F 0 "Q20" H 4800 29100 50 0000 R CNN +F 1 "eSim_NPN" H 4850 29200 50 0000 R CNN +F 2 "" H 5100 29150 29 0000 C CNN +F 3 "" H 4900 29050 60 0000 C CNN + 1 4900 29050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q28 +U 1 1 66886F9E +P 6100 27350 +F 0 "Q28" H 6000 27400 50 0000 R CNN +F 1 "eSim_PNP" H 6050 27500 50 0000 R CNN +F 2 "" H 6300 27450 29 0000 C CNN +F 3 "" H 6100 27350 60 0000 C CNN + 1 6100 27350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q31 +U 1 1 66886FA4 +P 7050 28850 +F 0 "Q31" H 6950 28900 50 0000 R CNN +F 1 "eSim_PNP" H 7000 29000 50 0000 R CNN +F 2 "" H 7250 28950 29 0000 C CNN +F 3 "" H 7050 28850 60 0000 C CNN + 1 7050 28850 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q33 +U 1 1 66886FAA +P 7550 27350 +F 0 "Q33" H 7450 27400 50 0000 R CNN +F 1 "eSim_NPN" H 7500 27500 50 0000 R CNN +F 2 "" H 7750 27450 29 0000 C CNN +F 3 "" H 7550 27350 60 0000 C CNN + 1 7550 27350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q34 +U 1 1 66886FB0 +P 7750 28150 +F 0 "Q34" H 7650 28200 50 0000 R CNN +F 1 "eSim_NPN" H 7700 28300 50 0000 R CNN +F 2 "" H 7950 28250 29 0000 C CNN +F 3 "" H 7750 28150 60 0000 C CNN + 1 7750 28150 + -1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 66886FB6 +P 7600 28800 +F 0 "R4" H 7650 28930 50 0000 C CNN +F 1 "12k" H 7650 28750 50 0000 C CNN +F 2 "" H 7650 28780 30 0000 C CNN +F 3 "" V 7650 28850 30 0000 C CNN + 1 7600 28800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q36 +U 1 1 66886FBC +P 8650 27350 +F 0 "Q36" H 8550 27400 50 0000 R CNN +F 1 "eSim_PNP" H 8600 27500 50 0000 R CNN +F 2 "" H 8850 27450 29 0000 C CNN +F 3 "" H 8650 27350 60 0000 C CNN + 1 8650 27350 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q38 +U 1 1 66886FC2 +P 9750 28150 +F 0 "Q38" H 9650 28200 50 0000 R CNN +F 1 "eSim_NPN" H 9700 28300 50 0000 R CNN +F 2 "" H 9950 28250 29 0000 C CNN +F 3 "" H 9750 28150 60 0000 C CNN + 1 9750 28150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q40 +U 1 1 66886FC8 +P 10850 24650 +F 0 "Q40" H 10750 24700 50 0000 R CNN +F 1 "eSim_NPN" H 10800 24800 50 0000 R CNN +F 2 "" H 11050 24750 29 0000 C CNN +F 3 "" H 10850 24650 60 0000 C CNN + 1 10850 24650 + -1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 66886FCE +P 10700 25150 +F 0 "R6" H 10750 25280 50 0000 C CNN +F 1 "0.7k" H 10750 25100 50 0000 C CNN +F 2 "" H 10750 25130 30 0000 C CNN +F 3 "" V 10750 25200 30 0000 C CNN + 1 10700 25150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q44 +U 1 1 66886FD4 +P 12300 26450 +F 0 "Q44" H 12200 26500 50 0000 R CNN +F 1 "eSim_NPN" H 12250 26600 50 0000 R CNN +F 2 "" H 12500 26550 29 0000 C CNN +F 3 "" H 12300 26450 60 0000 C CNN + 1 12300 26450 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 66886FDA +P 6750 24850 +F 0 "C2" H 6775 24950 50 0000 L CNN +F 1 "8p" H 6775 24750 50 0000 L CNN +F 2 "" H 6788 24700 30 0000 C CNN +F 3 "" H 6750 24850 60 0000 C CNN + 1 6750 24850 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q53 +U 1 1 66886FE0 +P 14650 26050 +F 0 "Q53" H 14550 26100 50 0000 R CNN +F 1 "eSim_NPN" H 14600 26200 50 0000 R CNN +F 2 "" H 14850 26150 29 0000 C CNN +F 3 "" H 14650 26050 60 0000 C CNN + 1 14650 26050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q54 +U 1 1 66886FE6 +P 14650 28350 +F 0 "Q54" H 14550 28400 50 0000 R CNN +F 1 "eSim_NPN" H 14600 28500 50 0000 R CNN +F 2 "" H 14850 28450 29 0000 C CNN +F 3 "" H 14650 28350 60 0000 C CNN + 1 14650 28350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 66886FEC +P 13950 24050 +F 0 "R11" H 14000 24180 50 0000 C CNN +F 1 "31k" H 14000 24000 50 0000 C CNN +F 2 "" H 14000 24030 30 0000 C CNN +F 3 "" V 14000 24100 30 0000 C CNN + 1 13950 24050 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 66886FF2 +P 13950 26600 +F 0 "R12" H 14000 26730 50 0000 C CNN +F 1 "37k" H 14000 26550 50 0000 C CNN +F 2 "" H 14000 26580 30 0000 C CNN +F 3 "" V 14000 26650 30 0000 C CNN + 1 13950 26600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q59 +U 1 1 66886FF8 +P 16350 23400 +F 0 "Q59" H 16250 23450 50 0000 R CNN +F 1 "eSim_NPN" H 16300 23550 50 0000 R CNN +F 2 "" H 16550 23500 29 0000 C CNN +F 3 "" H 16350 23400 60 0000 C CNN + 1 16350 23400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R14 +U 1 1 66886FFE +P 16400 25150 +F 0 "R14" H 16450 25280 50 0000 C CNN +F 1 "25" H 16450 25100 50 0000 C CNN +F 2 "" H 16450 25130 30 0000 C CNN +F 3 "" V 16450 25200 30 0000 C CNN + 1 16400 25150 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q60 +U 1 1 66887004 +P 16350 26150 +F 0 "Q60" H 16250 26200 50 0000 R CNN +F 1 "eSim_PNP" H 16300 26300 50 0000 R CNN +F 2 "" H 16550 26250 29 0000 C CNN +F 3 "" H 16350 26150 60 0000 C CNN + 1 16350 26150 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q56 +U 1 1 6688700A +P 15800 27100 +F 0 "Q56" H 15700 27150 50 0000 R CNN +F 1 "eSim_PNP" H 15750 27250 50 0000 R CNN +F 2 "" H 16000 27200 29 0000 C CNN +F 3 "" H 15800 27100 60 0000 C CNN + 1 15800 27100 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q62 +U 1 1 66887010 +P 17150 24750 +F 0 "Q62" H 17050 24800 50 0000 R CNN +F 1 "eSim_NPN" H 17100 24900 50 0000 R CNN +F 2 "" H 17350 24850 29 0000 C CNN +F 3 "" H 17150 24750 60 0000 C CNN + 1 17150 24750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q65 +U 1 1 6688701C +P 18800 23350 +F 0 "Q65" H 18700 23400 50 0000 R CNN +F 1 "eSim_NPN" H 18750 23500 50 0000 R CNN +F 2 "" H 19000 23450 29 0000 C CNN +F 3 "" H 18800 23350 60 0000 C CNN + 1 18800 23350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q68 +U 1 1 66887022 +P 19900 23350 +F 0 "Q68" H 19800 23400 50 0000 R CNN +F 1 "eSim_NPN" H 19850 23500 50 0000 R CNN +F 2 "" H 20100 23450 29 0000 C CNN +F 3 "" H 19900 23350 60 0000 C CNN + 1 19900 23350 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J2 +U 1 1 66887028 +P 18800 22350 +F 0 "J2" H 18700 22400 50 0000 R CNN +F 1 "jfet_n" H 18750 22500 50 0000 R CNN +F 2 "" H 19000 22450 29 0000 C CNN +F 3 "" H 18800 22350 60 0000 C CNN + 1 18800 22350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q66 +U 1 1 6688702E +P 18800 27250 +F 0 "Q66" H 18700 27300 50 0000 R CNN +F 1 "eSim_NPN" H 18750 27400 50 0000 R CNN +F 2 "" H 19000 27350 29 0000 C CNN +F 3 "" H 18800 27250 60 0000 C CNN + 1 18800 27250 + -1 0 0 -1 +$EndComp +$Comp +L resistor R16 +U 1 1 66887034 +P 19950 27850 +F 0 "R16" H 20000 27980 50 0000 C CNN +F 1 "8.2k" H 20000 27800 50 0000 C CNN +F 2 "" H 20000 27830 30 0000 C CNN +F 3 "" V 20000 27900 30 0000 C CNN + 1 19950 27850 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q90 +U 1 1 66887932 +P 26900 23450 +F 0 "Q90" H 26800 23500 50 0000 R CNN +F 1 "eSim_PNP" H 26850 23600 50 0000 R CNN +F 2 "" H 27100 23550 29 0000 C CNN +F 3 "" H 26900 23450 60 0000 C CNN + 1 26900 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q94 +U 1 1 66887938 +P 27350 23450 +F 0 "Q94" H 27250 23500 50 0000 R CNN +F 1 "eSim_PNP" H 27300 23600 50 0000 R CNN +F 2 "" H 27550 23550 29 0000 C CNN +F 3 "" H 27350 23450 60 0000 C CNN + 1 27350 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q112 +U 1 1 6688793E +P 34000 23450 +F 0 "Q112" H 33900 23500 50 0000 R CNN +F 1 "eSim_PNP" H 33950 23600 50 0000 R CNN +F 2 "" H 34200 23550 29 0000 C CNN +F 3 "" H 34000 23450 60 0000 C CNN + 1 34000 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q114 +U 1 1 66887944 +P 34400 23450 +F 0 "Q114" H 34300 23500 50 0000 R CNN +F 1 "eSim_PNP" H 34350 23600 50 0000 R CNN +F 2 "" H 34600 23550 29 0000 C CNN +F 3 "" H 34400 23450 60 0000 C CNN + 1 34400 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q116 +U 1 1 6688794A +P 35750 24150 +F 0 "Q116" H 35650 24200 50 0000 R CNN +F 1 "eSim_NPN" H 35700 24300 50 0000 R CNN +F 2 "" H 35950 24250 29 0000 C CNN +F 3 "" H 35750 24150 60 0000 C CNN + 1 35750 24150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q120 +U 1 1 66887950 +P 36300 24450 +F 0 "Q120" H 36200 24500 50 0000 R CNN +F 1 "eSim_NPN" H 36250 24600 50 0000 R CNN +F 2 "" H 36500 24550 29 0000 C CNN +F 3 "" H 36300 24450 60 0000 C CNN + 1 36300 24450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q82 +U 1 1 66887956 +P 26000 25000 +F 0 "Q82" H 25900 25050 50 0000 R CNN +F 1 "eSim_PNP" H 25950 25150 50 0000 R CNN +F 2 "" H 26200 25100 29 0000 C CNN +F 3 "" H 26000 25000 60 0000 C CNN + 1 26000 25000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q76 +U 1 1 6688795C +P 25550 25000 +F 0 "Q76" H 25450 25050 50 0000 R CNN +F 1 "eSim_PNP" H 25500 25150 50 0000 R CNN +F 2 "" H 25750 25100 29 0000 C CNN +F 3 "" H 25550 25000 60 0000 C CNN + 1 25550 25000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q70 +U 1 1 66887962 +P 25050 25000 +F 0 "Q70" H 24950 25050 50 0000 R CNN +F 1 "eSim_PNP" H 25000 25150 50 0000 R CNN +F 2 "" H 25250 25100 29 0000 C CNN +F 3 "" H 25050 25000 60 0000 C CNN + 1 25050 25000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q72 +U 1 1 66887968 +P 25200 29750 +F 0 "Q72" H 25100 29800 50 0000 R CNN +F 1 "eSim_PNP" H 25150 29900 50 0000 R CNN +F 2 "" H 25400 29850 29 0000 C CNN +F 3 "" H 25200 29750 60 0000 C CNN + 1 25200 29750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q78 +U 1 1 6688796E +P 25800 27050 +F 0 "Q78" H 25700 27100 50 0000 R CNN +F 1 "eSim_PNP" H 25750 27200 50 0000 R CNN +F 2 "" H 26000 27150 29 0000 C CNN +F 3 "" H 25800 27050 60 0000 C CNN + 1 25800 27050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q84 +U 1 1 66887974 +P 26200 27050 +F 0 "Q84" H 26100 27100 50 0000 R CNN +F 1 "eSim_PNP" H 26150 27200 50 0000 R CNN +F 2 "" H 26400 27150 29 0000 C CNN +F 3 "" H 26200 27050 60 0000 C CNN + 1 26200 27050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q88 +U 1 1 6688797A +P 26850 27050 +F 0 "Q88" H 26750 27100 50 0000 R CNN +F 1 "eSim_PNP" H 26800 27200 50 0000 R CNN +F 2 "" H 27050 27150 29 0000 C CNN +F 3 "" H 26850 27050 60 0000 C CNN + 1 26850 27050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q92 +U 1 1 66887980 +P 27300 27050 +F 0 "Q92" H 27200 27100 50 0000 R CNN +F 1 "eSim_PNP" H 27250 27200 50 0000 R CNN +F 2 "" H 27500 27150 29 0000 C CNN +F 3 "" H 27300 27050 60 0000 C CNN + 1 27300 27050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q74 +U 1 1 66887986 +P 25400 28350 +F 0 "Q74" H 25300 28400 50 0000 R CNN +F 1 "eSim_PNP" H 25350 28500 50 0000 R CNN +F 2 "" H 25600 28450 29 0000 C CNN +F 3 "" H 25400 28350 60 0000 C CNN + 1 25400 28350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q80 +U 1 1 6688798C +P 25850 30100 +F 0 "Q80" H 25750 30150 50 0000 R CNN +F 1 "eSim_NPN" H 25800 30250 50 0000 R CNN +F 2 "" H 26050 30200 29 0000 C CNN +F 3 "" H 25850 30100 60 0000 C CNN + 1 25850 30100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q86 +U 1 1 66887992 +P 26550 30100 +F 0 "Q86" H 26450 30150 50 0000 R CNN +F 1 "eSim_NPN" H 26500 30250 50 0000 R CNN +F 2 "" H 26750 30200 29 0000 C CNN +F 3 "" H 26550 30100 60 0000 C CNN + 1 26550 30100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q96 +U 1 1 66887998 +P 27750 28400 +F 0 "Q96" H 27650 28450 50 0000 R CNN +F 1 "eSim_PNP" H 27700 28550 50 0000 R CNN +F 2 "" H 27950 28500 29 0000 C CNN +F 3 "" H 27750 28400 60 0000 C CNN + 1 27750 28400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q98 +U 1 1 6688799E +P 28700 29900 +F 0 "Q98" H 28600 29950 50 0000 R CNN +F 1 "eSim_PNP" H 28650 30050 50 0000 R CNN +F 2 "" H 28900 30000 29 0000 C CNN +F 3 "" H 28700 29900 60 0000 C CNN + 1 28700 29900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q100 +U 1 1 668879A4 +P 29200 28400 +F 0 "Q100" H 29100 28450 50 0000 R CNN +F 1 "eSim_NPN" H 29150 28550 50 0000 R CNN +F 2 "" H 29400 28500 29 0000 C CNN +F 3 "" H 29200 28400 60 0000 C CNN + 1 29200 28400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q102 +U 1 1 668879AA +P 29400 29200 +F 0 "Q102" H 29300 29250 50 0000 R CNN +F 1 "eSim_NPN" H 29350 29350 50 0000 R CNN +F 2 "" H 29600 29300 29 0000 C CNN +F 3 "" H 29400 29200 60 0000 C CNN + 1 29400 29200 + -1 0 0 -1 +$EndComp +$Comp +L resistor R20 +U 1 1 668879B0 +P 29250 29850 +F 0 "R20" H 29300 29980 50 0000 C CNN +F 1 "12k" H 29300 29800 50 0000 C CNN +F 2 "" H 29300 29830 30 0000 C CNN +F 3 "" V 29300 29900 30 0000 C CNN + 1 29250 29850 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q104 +U 1 1 668879B6 +P 30300 28400 +F 0 "Q104" H 30200 28450 50 0000 R CNN +F 1 "eSim_PNP" H 30250 28550 50 0000 R CNN +F 2 "" H 30500 28500 29 0000 C CNN +F 3 "" H 30300 28400 60 0000 C CNN + 1 30300 28400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q106 +U 1 1 668879BC +P 31400 29200 +F 0 "Q106" H 31300 29250 50 0000 R CNN +F 1 "eSim_NPN" H 31350 29350 50 0000 R CNN +F 2 "" H 31600 29300 29 0000 C CNN +F 3 "" H 31400 29200 60 0000 C CNN + 1 31400 29200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q108 +U 1 1 668879C2 +P 32500 25700 +F 0 "Q108" H 32400 25750 50 0000 R CNN +F 1 "eSim_NPN" H 32450 25850 50 0000 R CNN +F 2 "" H 32700 25800 29 0000 C CNN +F 3 "" H 32500 25700 60 0000 C CNN + 1 32500 25700 + -1 0 0 -1 +$EndComp +$Comp +L resistor R22 +U 1 1 668879C8 +P 32350 26200 +F 0 "R22" H 32400 26330 50 0000 C CNN +F 1 "0.7k" H 32400 26150 50 0000 C CNN +F 2 "" H 32400 26180 30 0000 C CNN +F 3 "" V 32400 26250 30 0000 C CNN + 1 32350 26200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q110 +U 1 1 668879CE +P 33950 27500 +F 0 "Q110" H 33850 27550 50 0000 R CNN +F 1 "eSim_NPN" H 33900 27650 50 0000 R CNN +F 2 "" H 34150 27600 29 0000 C CNN +F 3 "" H 33950 27500 60 0000 C CNN + 1 33950 27500 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 668879D4 +P 28400 25900 +F 0 "C4" H 28425 26000 50 0000 L CNN +F 1 "8p" H 28425 25800 50 0000 L CNN +F 2 "" H 28438 25750 30 0000 C CNN +F 3 "" H 28400 25900 60 0000 C CNN + 1 28400 25900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q121 +U 1 1 668879DA +P 36300 27100 +F 0 "Q121" H 36200 27150 50 0000 R CNN +F 1 "eSim_NPN" H 36250 27250 50 0000 R CNN +F 2 "" H 36500 27200 29 0000 C CNN +F 3 "" H 36300 27100 60 0000 C CNN + 1 36300 27100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q122 +U 1 1 668879E0 +P 36300 29400 +F 0 "Q122" H 36200 29450 50 0000 R CNN +F 1 "eSim_NPN" H 36250 29550 50 0000 R CNN +F 2 "" H 36500 29500 29 0000 C CNN +F 3 "" H 36300 29400 60 0000 C CNN + 1 36300 29400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R27 +U 1 1 668879E6 +P 35600 25100 +F 0 "R27" H 35650 25230 50 0000 C CNN +F 1 "31k" H 35650 25050 50 0000 C CNN +F 2 "" H 35650 25080 30 0000 C CNN +F 3 "" V 35650 25150 30 0000 C CNN + 1 35600 25100 + 0 1 1 0 +$EndComp +$Comp +L resistor R28 +U 1 1 668879EC +P 35600 27650 +F 0 "R28" H 35650 27780 50 0000 C CNN +F 1 "37k" H 35650 27600 50 0000 C CNN +F 2 "" H 35650 27630 30 0000 C CNN +F 3 "" V 35650 27700 30 0000 C CNN + 1 35600 27650 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q127 +U 1 1 668879F2 +P 38000 24450 +F 0 "Q127" H 37900 24500 50 0000 R CNN +F 1 "eSim_NPN" H 37950 24600 50 0000 R CNN +F 2 "" H 38200 24550 29 0000 C CNN +F 3 "" H 38000 24450 60 0000 C CNN + 1 38000 24450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R30 +U 1 1 668879F8 +P 38050 26200 +F 0 "R30" H 38100 26330 50 0000 C CNN +F 1 "25" H 38100 26150 50 0000 C CNN +F 2 "" H 38100 26180 30 0000 C CNN +F 3 "" V 38100 26250 30 0000 C CNN + 1 38050 26200 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q128 +U 1 1 668879FE +P 38000 27200 +F 0 "Q128" H 37900 27250 50 0000 R CNN +F 1 "eSim_PNP" H 37950 27350 50 0000 R CNN +F 2 "" H 38200 27300 29 0000 C CNN +F 3 "" H 38000 27200 60 0000 C CNN + 1 38000 27200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q124 +U 1 1 66887A04 +P 37450 28150 +F 0 "Q124" H 37350 28200 50 0000 R CNN +F 1 "eSim_PNP" H 37400 28300 50 0000 R CNN +F 2 "" H 37650 28250 29 0000 C CNN +F 3 "" H 37450 28150 60 0000 C CNN + 1 37450 28150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q130 +U 1 1 66887A0A +P 38800 25800 +F 0 "Q130" H 38700 25850 50 0000 R CNN +F 1 "eSim_NPN" H 38750 25950 50 0000 R CNN +F 2 "" H 39000 25900 29 0000 C CNN +F 3 "" H 38800 25800 60 0000 C CNN + 1 38800 25800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q133 +U 1 1 66887A16 +P 40450 24400 +F 0 "Q133" H 40350 24450 50 0000 R CNN +F 1 "eSim_NPN" H 40400 24550 50 0000 R CNN +F 2 "" H 40650 24500 29 0000 C CNN +F 3 "" H 40450 24400 60 0000 C CNN + 1 40450 24400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q136 +U 1 1 66887A1C +P 41550 24400 +F 0 "Q136" H 41450 24450 50 0000 R CNN +F 1 "eSim_NPN" H 41500 24550 50 0000 R CNN +F 2 "" H 41750 24500 29 0000 C CNN +F 3 "" H 41550 24400 60 0000 C CNN + 1 41550 24400 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J4 +U 1 1 66887A22 +P 40450 23400 +F 0 "J4" H 40350 23450 50 0000 R CNN +F 1 "jfet_n" H 40400 23550 50 0000 R CNN +F 2 "" H 40650 23500 29 0000 C CNN +F 3 "" H 40450 23400 60 0000 C CNN + 1 40450 23400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q134 +U 1 1 66887A28 +P 40450 28300 +F 0 "Q134" H 40350 28350 50 0000 R CNN +F 1 "eSim_NPN" H 40400 28450 50 0000 R CNN +F 2 "" H 40650 28400 29 0000 C CNN +F 3 "" H 40450 28300 60 0000 C CNN + 1 40450 28300 + -1 0 0 -1 +$EndComp +$Comp +L resistor R32 +U 1 1 66887A2E +P 41600 28900 +F 0 "R32" H 41650 29030 50 0000 C CNN +F 1 "8.2k" H 41650 28850 50 0000 C CNN +F 2 "" H 41650 28880 30 0000 C CNN +F 3 "" V 41650 28950 30 0000 C CNN + 1 41600 28900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 6688C2EA +P 21600 4700 +F 0 "U1" H 21650 4800 30 0000 C CNN +F 1 "PORT" H 21600 4700 30 0000 C CNN +F 2 "" H 21600 4700 60 0000 C CNN +F 3 "" H 21600 4700 60 0000 C CNN + 4 21600 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6689C72D +P 20800 12600 +F 0 "U1" H 20850 12700 30 0000 C CNN +F 1 "PORT" H 20800 12600 30 0000 C CNN +F 2 "" H 20800 12600 60 0000 C CNN +F 3 "" H 20800 12600 60 0000 C CNN + 11 20800 12600 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 668A97B5 +P 17150 3500 +F 0 "U1" H 17200 3600 30 0000 C CNN +F 1 "PORT" H 17150 3500 30 0000 C CNN +F 2 "" H 17150 3500 60 0000 C CNN +F 3 "" H 17150 3500 60 0000 C CNN + 1 17150 3500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 668AB399 +P 1750 10350 +F 0 "U1" H 1800 10450 30 0000 C CNN +F 1 "PORT" H 1750 10350 30 0000 C CNN +F 2 "" H 1750 10350 60 0000 C CNN +F 3 "" H 1750 10350 60 0000 C CNN + 2 1750 10350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 668ABE39 +P 6250 10400 +F 0 "U1" H 6300 10500 30 0000 C CNN +F 1 "PORT" H 6250 10400 30 0000 C CNN +F 2 "" H 6250 10400 60 0000 C CNN +F 3 "" H 6250 10400 60 0000 C CNN + 3 6250 10400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 668AD6A7 +P 39300 3900 +F 0 "U1" H 39350 4000 30 0000 C CNN +F 1 "PORT" H 39300 3900 30 0000 C CNN +F 2 "" H 39300 3900 60 0000 C CNN +F 3 "" H 39300 3900 60 0000 C CNN + 8 39300 3900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 668AEEA7 +P 23900 10750 +F 0 "U1" H 23950 10850 30 0000 C CNN +F 1 "PORT" H 23900 10750 30 0000 C CNN +F 2 "" H 23900 10750 60 0000 C CNN +F 3 "" H 23900 10750 60 0000 C CNN + 9 23900 10750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 668AFE62 +P 28400 10800 +F 0 "U1" H 28450 10900 30 0000 C CNN +F 1 "PORT" H 28400 10800 30 0000 C CNN +F 2 "" H 28400 10800 60 0000 C CNN +F 3 "" H 28400 10800 60 0000 C CNN + 10 28400 10800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 668B2361 +P 39300 21500 +F 0 "U1" H 39350 21600 30 0000 C CNN +F 1 "PORT" H 39300 21500 30 0000 C CNN +F 2 "" H 39300 21500 60 0000 C CNN +F 3 "" H 39300 21500 60 0000 C CNN + 14 39300 21500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 668B386B +P 23900 28350 +F 0 "U1" H 23950 28450 30 0000 C CNN +F 1 "PORT" H 23900 28350 30 0000 C CNN +F 2 "" H 23900 28350 60 0000 C CNN +F 3 "" H 23900 28350 60 0000 C CNN + 13 23900 28350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 668B402B +P 28350 28400 +F 0 "U1" H 28400 28500 30 0000 C CNN +F 1 "PORT" H 28350 28400 30 0000 C CNN +F 2 "" H 28350 28400 60 0000 C CNN +F 3 "" H 28350 28400 60 0000 C CNN + 12 28350 28400 + -1 0 0 1 +$EndComp +Wire Wire Line + 27950 28400 28100 28400 +Wire Wire Line + 39300 21750 39300 26650 +Wire Wire Line + 28150 10800 27950 10800 +Wire Wire Line + 5800 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8100 +Wire Wire Line + 13700 6450 15650 6450 +Wire Wire Line + 13700 6350 13700 6450 +Connection ~ 13700 4700 +Wire Wire Line + 14250 4700 14250 6250 +Connection ~ 12150 4700 +Wire Wire Line + 13700 4700 13700 5950 +Wire Wire Line + 12350 6150 13400 6150 +Wire Wire Line + 12350 5650 12350 6150 +Connection ~ 12150 5200 +Wire Wire Line + 12150 4700 12150 5200 +Wire Wire Line + 12350 5200 12350 5250 +Wire Wire Line + 11950 5200 12350 5200 +Wire Wire Line + 11950 5250 11950 5200 +Connection ~ 4550 5450 +Connection ~ 9150 10400 +Connection ~ 9450 11200 +Wire Wire Line + 9700 10400 9700 11200 +Wire Wire Line + 7450 11200 13850 11200 +Connection ~ 8050 12850 +Wire Wire Line + 9150 12850 9150 11400 +Wire Wire Line + 9150 10400 9150 11000 +Wire Wire Line + 8350 10400 9700 10400 +Connection ~ 7150 12850 +Wire Wire Line + 8050 12850 8050 10600 +Connection ~ 7300 10200 +Connection ~ 6650 12850 +Wire Wire Line + 7150 12850 7150 12050 +Wire Wire Line + 7150 11400 7150 11750 +Wire Wire Line + 7150 10600 7150 11000 +Wire Wire Line + 7150 10200 8050 10200 +Wire Wire Line + 7300 6850 7300 10200 +Wire Wire Line + 6650 10400 6850 10400 +Wire Wire Line + 4400 11900 6350 11900 +Connection ~ 5500 12850 +Wire Wire Line + 6650 12850 6650 12100 +Wire Wire Line + 4850 6850 4850 5650 +Wire Wire Line + 7300 6850 4850 6850 +Wire Wire Line + 6650 10400 6650 11700 +Connection ~ 4800 8700 +Wire Wire Line + 4800 8500 4800 8700 +Wire Wire Line + 3500 8500 4800 8500 +Wire Wire Line + 3500 7200 3500 8500 +Connection ~ 4500 12850 +Wire Wire Line + 5500 12850 5500 10600 +Connection ~ 5500 9600 +Wire Wire Line + 5050 9600 5500 9600 +Wire Wire Line + 5050 9250 5050 9600 +Connection ~ 5350 9050 +Wire Wire Line + 5500 9050 5500 10200 +Connection ~ 3600 11750 +Wire Wire Line + 3600 11900 3600 11750 +Connection ~ 4150 11750 +Wire Wire Line + 3250 11750 4150 11750 +Connection ~ 4150 12100 +Wire Wire Line + 4150 9250 4150 12100 +Connection ~ 3350 12850 +Wire Wire Line + 3350 10550 3350 12850 +Connection ~ 3600 12850 +Wire Wire Line + 3600 12850 3600 12300 +Wire Wire Line + 4500 12850 4500 12300 +Wire Wire Line + 2950 12850 20800 12850 +Wire Wire Line + 2950 11950 2950 12850 +Wire Wire Line + 3900 12100 4200 12100 +Connection ~ 3350 9600 +Wire Wire Line + 3750 9600 3350 9600 +Wire Wire Line + 3750 9250 3750 9600 +Connection ~ 3450 9050 +Wire Wire Line + 3350 9050 3350 10150 +Connection ~ 3950 8800 +Connection ~ 4850 8800 +Wire Wire Line + 4850 8700 4850 8800 +Wire Wire Line + 3950 8700 4850 8700 +Wire Wire Line + 3950 8800 3950 8700 +Wire Wire Line + 4150 8800 4150 8850 +Wire Wire Line + 3750 8800 4150 8800 +Wire Wire Line + 3750 8850 3750 8800 +Wire Wire Line + 5050 8800 5050 8850 +Wire Wire Line + 4600 8800 5050 8800 +Wire Wire Line + 4600 8850 4600 8800 +Wire Wire Line + 4900 9050 5500 9050 +Wire Wire Line + 3350 9050 3850 9050 +Wire Wire Line + 2950 7200 3000 7200 +Wire Wire Line + 2950 7200 2950 11550 +Connection ~ 3200 7000 +Wire Wire Line + 2700 5450 12050 5450 +Wire Wire Line + 2700 7000 2700 5450 +Connection ~ 5050 4700 +Connection ~ 3500 6650 +Wire Wire Line + 3500 4700 3500 6800 +Wire Wire Line + 3000 6650 3000 6800 +Wire Wire Line + 3000 6650 3950 6650 +Wire Wire Line + 3950 6650 3950 6800 +Wire Wire Line + 2700 7000 3650 7000 +Connection ~ 5050 5200 +Wire Wire Line + 5050 4700 5050 5200 +Wire Wire Line + 3500 4700 21350 4700 +Wire Wire Line + 5300 5200 5300 5250 +Wire Wire Line + 4850 5200 5300 5200 +Wire Wire Line + 4850 5250 4850 5200 +Connection ~ 5000 5450 +Wire Wire Line + 17650 20700 17650 25600 +$Comp +L PORT U1 +U 7 1 668BD5A0 +P 17650 20450 +F 0 "U1" H 17700 20550 30 0000 C CNN +F 1 "PORT" H 17650 20450 30 0000 C CNN +F 2 "" H 17650 20450 60 0000 C CNN +F 3 "" H 17650 20450 60 0000 C CNN + 7 17650 20450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 668BEA81 +P 2250 27300 +F 0 "U1" H 2300 27400 30 0000 C CNN +F 1 "PORT" H 2250 27300 30 0000 C CNN +F 2 "" H 2250 27300 60 0000 C CNN +F 3 "" H 2250 27300 60 0000 C CNN + 6 2250 27300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 668BF2D4 +P 6750 27350 +F 0 "U1" H 6800 27450 30 0000 C CNN +F 1 "PORT" H 6750 27350 30 0000 C CNN +F 2 "" H 6750 27350 60 0000 C CNN +F 3 "" H 6750 27350 60 0000 C CNN + 5 6750 27350 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 27350 6300 27350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sub b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sub new file mode 100644 index 00000000..8c261c2f --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sub @@ -0,0 +1,177 @@ +* Subcircuit MC3403_IC +.subckt MC3403_IC net-_q58-pad3_ net-_q3-pad2_ net-_q25-pad2_ net-_j1-pad1_ net-_q28-pad2_ net-_q9-pad2_ net-_q60-pad3_ net-_q126-pad3_ net-_q73-pad2_ net-_q95-pad2_ net-_j1-pad2_ net-_q96-pad2_ net-_q74-pad2_ net-_q128-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\mc3403_ic\mc3403_ic.cir +.include NPN.lib +.include PNP.lib +.include NJF.lib +q19 net-_q19-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q22 net-_q22-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q42 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q43 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q47 net-_j1-pad1_ net-_c1-pad1_ net-_q47-pad3_ Q2N2222 +q49 net-_j1-pad1_ net-_q47-pad3_ net-_q49-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q12-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q12-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q12-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q18 net-_c1-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q21 net-_q18-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q12-pad2_ Q2N2907A +q8 net-_q12-pad1_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q16 net-_c1-pad2_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q25 net-_j1-pad2_ net-_q25-pad2_ net-_q18-pad2_ Q2N2907A +q29 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q30 net-_q19-pad1_ net-_q10-pad1_ net-_q30-pad3_ Q2N2222 +q32 net-_q30-pad3_ net-_q22-pad1_ net-_q32-pad3_ Q2N2222 +r3 net-_q32-pad3_ net-_j1-pad2_ 12k +q35 net-_j1-pad2_ net-_q22-pad1_ net-_q19-pad1_ Q2N2907A +q37 net-_q22-pad1_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +q39 net-_q1-pad2_ net-_q39-pad2_ net-_q39-pad3_ Q2N2222 +r5 net-_q39-pad3_ net-_j1-pad2_ 0.7k +q41 net-_c1-pad1_ net-_q30-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 8p +q50 net-_q49-pad3_ net-_q50-pad2_ net-_q50-pad3_ Q2N2222 +q51 net-_q50-pad3_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +r9 net-_q49-pad3_ net-_q50-pad2_ 31k +r10 net-_q50-pad2_ net-_q50-pad3_ 37k +q57 net-_j1-pad1_ net-_q47-pad3_ net-_q57-pad3_ Q2N2222 +r13 net-_q57-pad3_ net-_q58-pad3_ 25 +q58 net-_j1-pad2_ net-_q55-pad3_ net-_q58-pad3_ Q2N2907A +q55 net-_j1-pad2_ net-_q50-pad3_ net-_q55-pad3_ Q2N2907A +q61 net-_c1-pad1_ net-_q57-pad3_ net-_q58-pad3_ Q2N2222 +q63 net-_j1-pad3_ net-_j1-pad3_ net-_q39-pad2_ Q2N2222 +q67 net-_j1-pad1_ net-_j1-pad3_ net-_q64-pad2_ Q2N2222 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q64 net-_q39-pad2_ net-_q64-pad2_ net-_j1-pad2_ Q2N2222 +r15 net-_q64-pad2_ net-_j1-pad2_ 8.2k +q89 net-_q103-pad3_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q93 net-_q101-pad2_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q111 net-_q107-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q113 net-_c3-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q115 net-_j1-pad1_ net-_c3-pad1_ net-_q115-pad3_ Q2N2222 +q117 net-_j1-pad1_ net-_q115-pad3_ net-_q117-pad3_ Q2N2222 +q81 net-_q81-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q75 net-_q75-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q69 net-_q69-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q71 net-_j1-pad2_ net-_q71-pad2_ net-_q69-pad1_ Q2N2907A +q77 net-_q73-pad3_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q83 net-_q71-pad2_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q87 net-_c3-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q91 net-_q87-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q73 net-_j1-pad2_ net-_q73-pad2_ net-_q73-pad3_ Q2N2907A +q79 net-_q71-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q85 net-_c3-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q95 net-_j1-pad2_ net-_q95-pad2_ net-_q87-pad2_ Q2N2907A +q97 net-_j1-pad2_ net-_c3-pad2_ net-_q81-pad1_ Q2N2907A +q99 net-_q103-pad3_ net-_q81-pad1_ net-_q101-pad1_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad2_ net-_q101-pad3_ Q2N2222 +r19 net-_q101-pad3_ net-_j1-pad2_ 12k +q103 net-_j1-pad2_ net-_q101-pad2_ net-_q103-pad3_ Q2N2907A +q105 net-_q101-pad2_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +q107 net-_q107-pad1_ net-_q107-pad2_ net-_q107-pad3_ Q2N2222 +r21 net-_q107-pad3_ net-_j1-pad2_ 0.7k +q109 net-_c3-pad1_ net-_q101-pad1_ net-_j1-pad2_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 8p +q118 net-_q117-pad3_ net-_q118-pad2_ net-_q118-pad3_ Q2N2222 +q119 net-_q118-pad3_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +r25 net-_q117-pad3_ net-_q118-pad2_ 31k +r26 net-_q118-pad2_ net-_q118-pad3_ 37k +q125 net-_j1-pad1_ net-_q115-pad3_ net-_q125-pad3_ Q2N2222 +r29 net-_q125-pad3_ net-_q126-pad3_ 25 +q126 net-_j1-pad2_ net-_q123-pad3_ net-_q126-pad3_ Q2N2907A +q123 net-_j1-pad2_ net-_q118-pad3_ net-_q123-pad3_ Q2N2907A +q129 net-_c3-pad1_ net-_q125-pad3_ net-_q126-pad3_ Q2N2222 +q131 net-_j3-pad3_ net-_j3-pad3_ net-_q107-pad2_ Q2N2222 +q135 net-_j1-pad1_ net-_j3-pad3_ net-_q132-pad2_ Q2N2222 +j3 net-_j1-pad1_ net-_j1-pad2_ net-_j3-pad3_ J2N3819 +q132 net-_q107-pad2_ net-_q132-pad2_ net-_j1-pad2_ Q2N2222 +r31 net-_q132-pad2_ net-_j1-pad2_ 8.2k +q24 net-_q24-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q27 net-_q27-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q45 net-_q11-pad2_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q46 net-_c2-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q48 net-_j1-pad1_ net-_c2-pad1_ net-_q48-pad3_ Q2N2222 +q52 net-_j1-pad1_ net-_q48-pad3_ net-_q52-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q5 net-_q5-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_j1-pad2_ net-_q14-pad1_ net-_q5-pad1_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q17 net-_q14-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q23 net-_c2-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q26 net-_q23-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q9 net-_j1-pad2_ net-_q9-pad2_ net-_q13-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q20 net-_c2-pad2_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_j1-pad2_ net-_q28-pad2_ net-_q23-pad2_ Q2N2907A +q31 net-_j1-pad2_ net-_c2-pad2_ net-_q15-pad1_ Q2N2907A +q33 net-_q24-pad1_ net-_q15-pad1_ net-_q33-pad3_ Q2N2222 +q34 net-_q33-pad3_ net-_q27-pad1_ net-_q34-pad3_ Q2N2222 +r4 net-_q34-pad3_ net-_j1-pad2_ 12k +q36 net-_j1-pad2_ net-_q27-pad1_ net-_q24-pad1_ Q2N2907A +q38 net-_q27-pad1_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +q40 net-_q11-pad2_ net-_q40-pad2_ net-_q40-pad3_ Q2N2222 +r6 net-_q40-pad3_ net-_j1-pad2_ 0.7k +q44 net-_c2-pad1_ net-_q33-pad3_ net-_j1-pad2_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 8p +q53 net-_q52-pad3_ net-_q53-pad2_ net-_q53-pad3_ Q2N2222 +q54 net-_q53-pad3_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +r11 net-_q52-pad3_ net-_q53-pad2_ 31k +r12 net-_q53-pad2_ net-_q53-pad3_ 37k +q59 net-_j1-pad1_ net-_q48-pad3_ net-_q59-pad3_ Q2N2222 +r14 net-_q59-pad3_ net-_q60-pad3_ 25 +q60 net-_j1-pad2_ net-_q56-pad3_ net-_q60-pad3_ Q2N2907A +q56 net-_j1-pad2_ net-_q53-pad3_ net-_q56-pad3_ Q2N2907A +q62 net-_c2-pad1_ net-_q59-pad3_ net-_q60-pad3_ Q2N2222 +q65 net-_j2-pad3_ net-_j2-pad3_ net-_q40-pad2_ Q2N2222 +q68 net-_j1-pad1_ net-_j2-pad3_ net-_q66-pad2_ Q2N2222 +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j2-pad3_ J2N3819 +q66 net-_q40-pad2_ net-_q66-pad2_ net-_j1-pad2_ Q2N2222 +r16 net-_q66-pad2_ net-_j1-pad2_ 8.2k +q90 net-_q100-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q94 net-_q102-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q112 net-_q108-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q114 net-_c4-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q116 net-_j1-pad1_ net-_c4-pad1_ net-_q116-pad3_ Q2N2222 +q120 net-_j1-pad1_ net-_q116-pad3_ net-_q120-pad3_ Q2N2222 +q82 net-_q100-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q76 net-_q76-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q70 net-_q70-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q72 net-_j1-pad2_ net-_q72-pad2_ net-_q70-pad1_ Q2N2907A +q78 net-_q74-pad3_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q84 net-_q72-pad2_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q88 net-_c4-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q92 net-_q88-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q74 net-_j1-pad2_ net-_q74-pad2_ net-_q74-pad3_ Q2N2907A +q80 net-_q72-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q86 net-_c4-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q96 net-_j1-pad2_ net-_q96-pad2_ net-_q88-pad2_ Q2N2907A +q98 net-_j1-pad2_ net-_c4-pad2_ net-_q100-pad2_ Q2N2907A +q100 net-_q100-pad1_ net-_q100-pad2_ net-_q100-pad3_ Q2N2222 +q102 net-_q100-pad3_ net-_q102-pad2_ net-_q102-pad3_ Q2N2222 +r20 net-_q102-pad3_ net-_j1-pad2_ 12k +q104 net-_j1-pad2_ net-_q102-pad2_ net-_q100-pad1_ Q2N2907A +q106 net-_q102-pad2_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +q108 net-_q108-pad1_ net-_q108-pad2_ net-_q108-pad3_ Q2N2222 +r22 net-_q108-pad3_ net-_j1-pad2_ 0.7k +q110 net-_c4-pad1_ net-_q100-pad3_ net-_j1-pad2_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 8p +q121 net-_q120-pad3_ net-_q121-pad2_ net-_q121-pad3_ Q2N2222 +q122 net-_q121-pad3_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +r27 net-_q120-pad3_ net-_q121-pad2_ 31k +r28 net-_q121-pad2_ net-_q121-pad3_ 37k +q127 net-_j1-pad1_ net-_q116-pad3_ net-_q127-pad3_ Q2N2222 +r30 net-_q127-pad3_ net-_q128-pad3_ 25 +q128 net-_j1-pad2_ net-_q124-pad3_ net-_q128-pad3_ Q2N2907A +q124 net-_j1-pad2_ net-_q121-pad3_ net-_q124-pad3_ Q2N2907A +q130 net-_c4-pad1_ net-_q127-pad3_ net-_q128-pad3_ Q2N2222 +q133 net-_j4-pad3_ net-_j4-pad3_ net-_q108-pad2_ Q2N2222 +q136 net-_j1-pad1_ net-_j4-pad3_ net-_q134-pad2_ Q2N2222 +j4 net-_j1-pad1_ net-_j1-pad2_ net-_j4-pad3_ J2N3819 +q134 net-_q108-pad2_ net-_q134-pad2_ net-_j1-pad2_ Q2N2222 +r32 net-_q134-pad2_ net-_j1-pad2_ 8.2k +* Control Statements + +.ends MC3403_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC_Previous_Values.xml b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC_Previous_Values.xml new file mode 100644 index 00000000..edbbc0a6 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q22><q42><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q42><q43><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q43><q47><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q47><q49><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q49><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q25><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q25><q29><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q29><q30><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q30><q32><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q32><q35><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q35><q37><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q37><q39><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q39><q41><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q41><q50><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q50><q51><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q51><q57><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q57><q58><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q58><q55><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q55><q61><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q61><q63><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q63><q67><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q67><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q64><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q64><q89><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q89><q93><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q93><q111><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q111><q113><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q113><q115><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q115><q117><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q117><q81><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q81><q75><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q75><q69><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q69><q71><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q71><q77><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q77><q83><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q83><q87><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q87><q91><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q91><q73><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q73><q79><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q79><q85><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q85><q95><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q95><q97><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q97><q99><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q99><q101><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q101><q103><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q103><q105><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q105><q107><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q107><q109><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q109><q118><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q118><q119><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q119><q125><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q125><q126><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q126><q123><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q123><q129><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q129><q131><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q131><q135><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q135><j3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j3><q132><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q132><q24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q24><q27><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q27><q45><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q45><q46><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q46><q48><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q48><q52><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q52><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><q26><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q26><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q28><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q28><q31><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q31><q33><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q33><q34><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q34><q36><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q36><q38><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q38><q40><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q40><q44><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q44><q53><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q53><q54><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q54><q59><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q59><q60><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q60><q56><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q56><q62><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q62><q65><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q65><q68><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q68><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j2><q66><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q66><q90><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q90><q94><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q94><q112><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q112><q114><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q114><q116><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q116><q120><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q120><q82><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q82><q76><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q76><q70><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q70><q72><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q72><q78><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q78><q84><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q84><q88><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q88><q92><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q92><q74><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q74><q80><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q80><q86><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q86><q96><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q96><q98><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q98><q100><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q100><q102><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q102><q104><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q104><q106><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q106><q108><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q108><q110><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q110><q121><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q121><q122><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q122><q127><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q127><q128><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q128><q124><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q124><q130><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q130><q133><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q133><q136><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q136><j4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j4><q134><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q134></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC3403_sub/NJF.lib b/library/SubcircuitLibrary/MC3403_sub/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/MC3403_sub/NPN.lib b/library/SubcircuitLibrary/MC3403_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC3403_sub/PNP.lib b/library/SubcircuitLibrary/MC3403_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/MC3403_sub/analysis b/library/SubcircuitLibrary/MC3403_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC78L05_sub/D.lib b/library/SubcircuitLibrary/MC78L05_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC-cache.lib b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC-cache.lib new file mode 100644 index 00000000..c353ac98 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC-cache.lib @@ -0,0 +1,164 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir new file mode 100644 index 00000000..768e3dcd --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir @@ -0,0 +1,38 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\MC78L05_IC\MC78L05_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/24 11:39:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 15k +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q1-Pad3_ Net-_Q3-Pad2_ 3.8k +R3 Net-_Q3-Pad2_ Net-_Q2-Pad2_ 1.2k +R4 Net-_Q2-Pad2_ Net-_D1-Pad2_ 420 +U1 Net-_D1-Pad2_ Net-_Q1-Pad2_ zener +Q4 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q7 Net-_Q10-Pad1_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad1_ Net-_Q6-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R5 Net-_Q3-Pad3_ Net-_D1-Pad1_ 0.18k +R6 Net-_Q3-Pad3_ Net-_C1-Pad2_ 20k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_C1-Pad2_ Net-_D1-Pad1_ Net-_Q5-Pad3_ eSim_NPN +R7 Net-_Q5-Pad3_ Net-_D1-Pad2_ 1.0k +R8 Net-_Q10-Pad1_ Net-_C1-Pad1_ 2.2k +Q8 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_D1-Pad2_ eSim_NPN +Q9 Net-_D1-Pad2_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q11 Net-_Q1-Pad1_ Net-_Q10-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q2 Net-_Q10-Pad1_ Net-_Q2-Pad2_ Net-_D1-Pad2_ eSim_NPN +R9 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 5.0k +Q12 Net-_Q1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad2_ eSim_NPN +R10 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 3.0 +R11 Net-_Q10-Pad3_ Net-_Q6-Pad2_ 2.0k +R12 Net-_Q6-Pad2_ Net-_D1-Pad2_ 2.85k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5p +U2 Net-_Q10-Pad3_ Net-_D1-Pad2_ Net-_Q1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir.out b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir.out new file mode 100644 index 00000000..8486c6ca --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir.out @@ -0,0 +1,45 @@ +* d:\fossee\esim\library\subcircuitlibrary\mc78l05_ic\mc78l05_ic.cir + +.include PNP.lib +.include D.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 15k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q3-pad2_ 3.8k +r3 net-_q3-pad2_ net-_q2-pad2_ 1.2k +r4 net-_q2-pad2_ net-_d1-pad2_ 420 +* u1 net-_d1-pad2_ net-_q1-pad2_ zener +q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q10-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q3-pad1_ net-_q6-pad2_ net-_q3-pad3_ Q2N2222 +r5 net-_q3-pad3_ net-_d1-pad1_ 0.18k +r6 net-_q3-pad3_ net-_c1-pad2_ 20k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_c1-pad2_ net-_d1-pad1_ net-_q5-pad3_ Q2N2222 +r7 net-_q5-pad3_ net-_d1-pad2_ 1.0k +r8 net-_q10-pad1_ net-_c1-pad1_ 2.2k +q8 net-_c1-pad1_ net-_c1-pad2_ net-_d1-pad2_ Q2N2222 +q9 net-_d1-pad2_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q11 net-_q1-pad1_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q2 net-_q10-pad1_ net-_q2-pad2_ net-_d1-pad2_ Q2N2222 +r9 net-_q11-pad3_ net-_q10-pad3_ 5.0k +q12 net-_q1-pad1_ net-_q11-pad3_ net-_q10-pad2_ Q2N2222 +r10 net-_q10-pad2_ net-_q10-pad3_ 3.0 +r11 net-_q10-pad3_ net-_q6-pad2_ 2.0k +r12 net-_q6-pad2_ net-_d1-pad2_ 2.85k +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +* u2 net-_q10-pad3_ net-_d1-pad2_ net-_q1-pad1_ port +a1 net-_d1-pad2_ net-_q1-pad2_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.pro b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sch b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sch new file mode 100644 index 00000000..b86442f0 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sch @@ -0,0 +1,549 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC78L05-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 6684EB64 +P 2750 1700 +F 0 "R1" H 2800 1830 50 0000 C CNN +F 1 "15k" H 2800 1650 50 0000 C CNN +F 2 "" H 2800 1680 30 0000 C CNN +F 3 "" V 2800 1750 30 0000 C CNN + 1 2750 1700 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6684EB65 +P 3200 2300 +F 0 "Q1" H 3100 2350 50 0000 R CNN +F 1 "eSim_NPN" H 3150 2450 50 0000 R CNN +F 2 "" H 3400 2400 29 0000 C CNN +F 3 "" H 3200 2300 60 0000 C CNN + 1 3200 2300 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 6684EB66 +P 3250 2700 +F 0 "R2" H 3300 2830 50 0000 C CNN +F 1 "3.8k" H 3300 2650 50 0000 C CNN +F 2 "" H 3300 2680 30 0000 C CNN +F 3 "" V 3300 2750 30 0000 C CNN + 1 3250 2700 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 6684EB67 +P 3250 3400 +F 0 "R3" H 3300 3530 50 0000 C CNN +F 1 "1.2k" H 3300 3350 50 0000 C CNN +F 2 "" H 3300 3380 30 0000 C CNN +F 3 "" V 3300 3450 30 0000 C CNN + 1 3250 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6684EB68 +P 3250 4600 +F 0 "R4" H 3300 4730 50 0000 C CNN +F 1 "420" H 3300 4550 50 0000 C CNN +F 2 "" H 3300 4580 30 0000 C CNN +F 3 "" V 3300 4650 30 0000 C CNN + 1 3250 4600 + 0 1 1 0 +$EndComp +Wire Wire Line + 3300 2500 3300 2600 +Wire Wire Line + 3300 2900 3300 3300 +Wire Wire Line + 3300 3600 3300 4500 +$Comp +L zener U1 +U 1 1 6684EB69 +P 2800 3900 +F 0 "U1" H 2750 3800 60 0000 C CNN +F 1 "zener" H 2800 4000 60 0000 C CNN +F 2 "" H 2850 3900 60 0000 C CNN +F 3 "" H 2850 3900 60 0000 C CNN + 1 2800 3900 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2800 1900 2800 3600 +Wire Wire Line + 2800 4100 2800 5100 +Wire Wire Line + 2800 5100 8350 5100 +Wire Wire Line + 3300 5100 3300 4800 +$Comp +L eSim_PNP Q4 +U 1 1 6684EB6A +P 4700 1900 +F 0 "Q4" H 4600 1950 50 0000 R CNN +F 1 "eSim_PNP" H 4650 2050 50 0000 R CNN +F 2 "" H 4900 2000 29 0000 C CNN +F 3 "" H 4700 1900 60 0000 C CNN + 1 4700 1900 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6684EB6B +P 5900 1900 +F 0 "Q7" H 5800 1950 50 0000 R CNN +F 1 "eSim_PNP" H 5850 2050 50 0000 R CNN +F 2 "" H 6100 2000 29 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5900 1900 + 1 0 0 1 +$EndComp +Wire Wire Line + 4900 1900 5700 1900 +$Comp +L eSim_NPN Q3 +U 1 1 6684EB6C +P 4200 3100 +F 0 "Q3" H 4100 3150 50 0000 R CNN +F 1 "eSim_NPN" H 4150 3250 50 0000 R CNN +F 2 "" H 4400 3200 29 0000 C CNN +F 3 "" H 4200 3100 60 0000 C CNN + 1 4200 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 3100 4000 3100 +Connection ~ 3300 3100 +$Comp +L eSim_NPN Q6 +U 1 1 6684EB6D +P 5300 3100 +F 0 "Q6" H 5200 3150 50 0000 R CNN +F 1 "eSim_NPN" H 5250 3250 50 0000 R CNN +F 2 "" H 5500 3200 29 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 1 5300 3100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4300 2900 5200 2900 +Wire Wire Line + 4600 2100 4600 2900 +Connection ~ 4600 2900 +Wire Wire Line + 5100 1900 5100 2400 +Wire Wire Line + 5100 2400 4600 2400 +Connection ~ 4600 2400 +Connection ~ 5100 1900 +$Comp +L resistor R5 +U 1 1 6684EB6E +P 4250 3500 +F 0 "R5" H 4300 3630 50 0000 C CNN +F 1 "0.18k" H 4300 3450 50 0000 C CNN +F 2 "" H 4300 3480 30 0000 C CNN +F 3 "" V 4300 3550 30 0000 C CNN + 1 4250 3500 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 6684EB6F +P 5150 3500 +F 0 "R6" H 5200 3630 50 0000 C CNN +F 1 "20k" H 5200 3450 50 0000 C CNN +F 2 "" H 5200 3480 30 0000 C CNN +F 3 "" V 5200 3550 30 0000 C CNN + 1 5150 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4300 3300 4300 3400 +Wire Wire Line + 5200 3300 5200 3400 +Wire Wire Line + 4300 3350 5200 3350 +Connection ~ 5200 3350 +Connection ~ 4300 3350 +$Comp +L eSim_Diode D1 +U 1 1 6684EB70 +P 4300 4650 +F 0 "D1" H 4300 4750 50 0000 C CNN +F 1 "eSim_Diode" H 4300 4550 50 0000 C CNN +F 2 "" H 4300 4650 60 0000 C CNN +F 3 "" H 4300 4650 60 0000 C CNN + 1 4300 4650 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6684EB71 +P 5100 4300 +F 0 "Q5" H 5000 4350 50 0000 R CNN +F 1 "eSim_NPN" H 5050 4450 50 0000 R CNN +F 2 "" H 5300 4400 29 0000 C CNN +F 3 "" H 5100 4300 60 0000 C CNN + 1 5100 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3700 4300 4500 +Wire Wire Line + 5200 3700 5200 4100 +Wire Wire Line + 4900 4300 4300 4300 +Connection ~ 4300 4300 +$Comp +L resistor R7 +U 1 1 6684EB72 +P 5150 4700 +F 0 "R7" H 5200 4830 50 0000 C CNN +F 1 "1.0k" H 5200 4650 50 0000 C CNN +F 2 "" H 5200 4680 30 0000 C CNN +F 3 "" V 5200 4750 30 0000 C CNN + 1 5150 4700 + 0 1 1 0 +$EndComp +Wire Wire Line + 5200 4600 5200 4500 +Wire Wire Line + 5200 5100 5200 4900 +Connection ~ 3300 5100 +Wire Wire Line + 4300 4800 4300 5100 +Connection ~ 4300 5100 +$Comp +L resistor R8 +U 1 1 6684EB73 +P 5950 3500 +F 0 "R8" H 6000 3630 50 0000 C CNN +F 1 "2.2k" H 6000 3450 50 0000 C CNN +F 2 "" H 6000 3480 30 0000 C CNN +F 3 "" V 6000 3550 30 0000 C CNN + 1 5950 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 6000 2100 6000 3400 +$Comp +L eSim_NPN Q8 +U 1 1 6684EB74 +P 5900 4100 +F 0 "Q8" H 5800 4150 50 0000 R CNN +F 1 "eSim_NPN" H 5850 4250 50 0000 R CNN +F 2 "" H 6100 4200 29 0000 C CNN +F 3 "" H 5900 4100 60 0000 C CNN + 1 5900 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5700 4100 +Wire Wire Line + 5250 4100 5250 4050 +Wire Wire Line + 5250 4050 5200 4050 +Connection ~ 5200 4050 +Wire Wire Line + 5500 3900 5500 4100 +Connection ~ 5500 4100 +Wire Wire Line + 6000 3700 6000 3900 +$Comp +L eSim_PNP Q9 +U 1 1 6684EB75 +P 6700 3800 +F 0 "Q9" H 6600 3850 50 0000 R CNN +F 1 "eSim_PNP" H 6650 3950 50 0000 R CNN +F 2 "" H 6900 3900 29 0000 C CNN +F 3 "" H 6700 3800 60 0000 C CNN + 1 6700 3800 + 1 0 0 1 +$EndComp +Wire Wire Line + 5800 3800 6500 3800 +Connection ~ 6000 3800 +Wire Wire Line + 5500 3600 5800 3600 +Wire Wire Line + 5800 3600 5800 3800 +Wire Wire Line + 6800 3600 6800 3200 +Wire Wire Line + 6800 3200 6000 3200 +Connection ~ 6000 3200 +Wire Wire Line + 6000 5100 6000 4300 +Connection ~ 5200 5100 +Connection ~ 6000 5100 +$Comp +L eSim_NPN Q11 +U 1 1 6684EB76 +P 7600 1900 +F 0 "Q11" H 7500 1950 50 0000 R CNN +F 1 "eSim_NPN" H 7550 2050 50 0000 R CNN +F 2 "" H 7800 2000 29 0000 C CNN +F 3 "" H 7600 1900 60 0000 C CNN + 1 7600 1900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6684EB77 +P 7200 2600 +F 0 "Q10" H 7100 2650 50 0000 R CNN +F 1 "eSim_NPN" H 7150 2750 50 0000 R CNN +F 2 "" H 7400 2700 29 0000 C CNN +F 3 "" H 7200 2600 60 0000 C CNN + 1 7200 2600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 6684EB78 +P 3700 4100 +F 0 "Q2" H 3600 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3650 4250 50 0000 R CNN +F 2 "" H 3900 4200 29 0000 C CNN +F 3 "" H 3700 4100 60 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 4100 3500 4100 +Connection ~ 3300 4100 +Wire Wire Line + 3800 3900 3800 2650 +Wire Wire Line + 3800 2650 6400 2650 +Connection ~ 6000 2650 +Wire Wire Line + 6400 1900 7400 1900 +Wire Wire Line + 6400 2650 6400 1900 +$Comp +L resistor R9 +U 1 1 6684EB79 +P 7650 2900 +F 0 "R9" H 7700 3030 50 0000 C CNN +F 1 "5.0k" H 7700 2850 50 0000 C CNN +F 2 "" H 7700 2880 30 0000 C CNN +F 3 "" V 7700 2950 30 0000 C CNN + 1 7650 2900 + 0 1 1 0 +$EndComp +Wire Wire Line + 7700 2100 7700 2800 +$Comp +L eSim_NPN Q12 +U 1 1 6684EB7A +P 8200 2300 +F 0 "Q12" H 8100 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8150 2450 50 0000 R CNN +F 2 "" H 8400 2400 29 0000 C CNN +F 3 "" H 8200 2300 60 0000 C CNN + 1 8200 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8000 2300 7700 2300 +Connection ~ 7700 2300 +$Comp +L resistor R10 +U 1 1 6684EB7B +P 8250 2800 +F 0 "R10" H 8300 2930 50 0000 C CNN +F 1 "3.0" H 8300 2750 50 0000 C CNN +F 2 "" H 8300 2780 30 0000 C CNN +F 3 "" V 8300 2850 30 0000 C CNN + 1 8250 2800 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 6684EB7C +P 8250 3400 +F 0 "R11" H 8300 3530 50 0000 C CNN +F 1 "2.0k" H 8300 3350 50 0000 C CNN +F 2 "" H 8300 3380 30 0000 C CNN +F 3 "" V 8300 3450 30 0000 C CNN + 1 8250 3400 + 0 1 1 0 +$EndComp +Wire Wire Line + 8300 2500 8300 2700 +Wire Wire Line + 8300 3000 8300 3300 +Wire Wire Line + 7400 2600 8300 2600 +Connection ~ 8300 2600 +Wire Wire Line + 7100 2800 7100 3200 +Wire Wire Line + 7100 3200 9000 3200 +Connection ~ 8300 3200 +Wire Wire Line + 7700 3100 7700 3200 +Connection ~ 7700 3200 +$Comp +L resistor R12 +U 1 1 6684EB7D +P 8250 4400 +F 0 "R12" H 8300 4530 50 0000 C CNN +F 1 "2.85k" H 8300 4350 50 0000 C CNN +F 2 "" H 8300 4380 30 0000 C CNN +F 3 "" V 8300 4450 30 0000 C CNN + 1 8250 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 8300 3600 8300 4300 +Wire Wire Line + 8300 5100 8300 4600 +Connection ~ 6800 5100 +Wire Wire Line + 8300 1300 8300 2100 +Wire Wire Line + 2800 1400 8300 1400 +Wire Wire Line + 2800 1400 2800 1600 +Wire Wire Line + 7700 1700 7700 1400 +Connection ~ 7700 1400 +Wire Wire Line + 6000 1700 6000 1400 +Connection ~ 6000 1400 +Wire Wire Line + 4600 1700 4600 1400 +Connection ~ 4600 1400 +Wire Wire Line + 3300 2100 3300 1400 +Connection ~ 3300 1400 +Wire Wire Line + 3000 2300 2800 2300 +Connection ~ 2800 2300 +Wire Wire Line + 5500 3100 7000 3100 +Wire Wire Line + 7000 3100 7000 3700 +Wire Wire Line + 7000 3700 8300 3700 +Connection ~ 8300 3700 +Wire Wire Line + 3800 4300 3800 5100 +Connection ~ 3800 5100 +Wire Wire Line + 7100 1900 7100 2400 +Connection ~ 7100 1900 +Wire Wire Line + 8300 1300 9100 1300 +Connection ~ 8300 1400 +$Comp +L capacitor_polarised C1 +U 1 1 6684EB83 +P 5500 3750 +F 0 "C1" H 5525 3850 50 0000 L CNN +F 1 "5p" H 5525 3650 50 0000 L CNN +F 2 "" H 5500 3750 50 0001 C CNN +F 3 "" H 5500 3750 50 0001 C CNN + 1 5500 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6800 4000 6800 5100 +Wire Wire Line + 8350 5100 8350 5250 +Connection ~ 8300 5100 +$Comp +L PORT U2 +U 1 1 6684ECD2 +P 9250 3200 +F 0 "U2" H 9300 3300 30 0000 C CNN +F 1 "PORT" H 9250 3200 30 0000 C CNN +F 2 "" H 9250 3200 60 0000 C CNN +F 3 "" H 9250 3200 60 0000 C CNN + 1 9250 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 6684F14A +P 8350 5500 +F 0 "U2" H 8400 5600 30 0000 C CNN +F 1 "PORT" H 8350 5500 30 0000 C CNN +F 2 "" H 8350 5500 60 0000 C CNN +F 3 "" H 8350 5500 60 0000 C CNN + 2 8350 5500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 3 1 6684F492 +P 9350 1300 +F 0 "U2" H 9400 1400 30 0000 C CNN +F 1 "PORT" H 9350 1300 30 0000 C CNN +F 2 "" H 9350 1300 60 0000 C CNN +F 3 "" H 9350 1300 60 0000 C CNN + 3 9350 1300 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sub b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sub new file mode 100644 index 00000000..4c0d6df5 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sub @@ -0,0 +1,39 @@ +* Subcircuit MC78L05_IC +.subckt MC78L05_IC net-_q10-pad3_ net-_d1-pad2_ net-_q1-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\mc78l05_ic\mc78l05_ic.cir +.include PNP.lib +.include D.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 15k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q3-pad2_ 3.8k +r3 net-_q3-pad2_ net-_q2-pad2_ 1.2k +r4 net-_q2-pad2_ net-_d1-pad2_ 420 +* u1 net-_d1-pad2_ net-_q1-pad2_ zener +q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q10-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q3-pad1_ net-_q6-pad2_ net-_q3-pad3_ Q2N2222 +r5 net-_q3-pad3_ net-_d1-pad1_ 0.18k +r6 net-_q3-pad3_ net-_c1-pad2_ 20k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_c1-pad2_ net-_d1-pad1_ net-_q5-pad3_ Q2N2222 +r7 net-_q5-pad3_ net-_d1-pad2_ 1.0k +r8 net-_q10-pad1_ net-_c1-pad1_ 2.2k +q8 net-_c1-pad1_ net-_c1-pad2_ net-_d1-pad2_ Q2N2222 +q9 net-_d1-pad2_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q11 net-_q1-pad1_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q2 net-_q10-pad1_ net-_q2-pad2_ net-_d1-pad2_ Q2N2222 +r9 net-_q11-pad3_ net-_q10-pad3_ 5.0k +q12 net-_q1-pad1_ net-_q11-pad3_ net-_q10-pad2_ Q2N2222 +r10 net-_q10-pad2_ net-_q10-pad3_ 3.0 +r11 net-_q10-pad3_ net-_q6-pad2_ 2.0k +r12 net-_q6-pad2_ net-_d1-pad2_ 2.85k +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +a1 net-_d1-pad2_ net-_q1-pad2_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends MC78L05_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC_Previous_Values.xml b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC_Previous_Values.xml new file mode 100644 index 00000000..4f54bdf7 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1></model><devicemodel><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC78L05_sub/NPN.lib b/library/SubcircuitLibrary/MC78L05_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC78L05_sub/PNP.lib b/library/SubcircuitLibrary/MC78L05_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/MC78L05_sub/analysis b/library/SubcircuitLibrary/MC78L05_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/RC4559N_sub/D.lib b/library/SubcircuitLibrary/RC4559N_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/RC4559N_sub/NJF.lib b/library/SubcircuitLibrary/RC4559N_sub/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/RC4559N_sub/NPN.lib b/library/SubcircuitLibrary/RC4559N_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/RC4559N_sub/PNP.lib b/library/SubcircuitLibrary/RC4559N_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC-cache.lib b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC-cache.lib new file mode 100644 index 00000000..3dddd3f6 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC-cache.lib @@ -0,0 +1,182 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir new file mode 100644 index 00000000..4209920b --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir @@ -0,0 +1,67 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\RC4559N_IC\RC4559N_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 18:31:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 Net-_J1-Pad3_ Net-_Q3-Pad3_ 8.7k +Q3 Net-_Q1-Pad3_ Net-_Q13-Pad1_ Net-_Q3-Pad3_ eSim_PNP +Q5 Net-_C2-Pad2_ Net-_Q5-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_C1-Pad1_ eSim_NPN +Q4 Net-_C2-Pad2_ Net-_Q1-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R2 Net-_C1-Pad1_ Net-_C1-Pad2_ 5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 15p +R4 Net-_Q4-Pad3_ Net-_C1-Pad2_ 5k +Q9 Net-_Q10-Pad1_ Net-_Q13-Pad1_ Net-_J1-Pad3_ eSim_PNP +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_J1-Pad3_ eSim_PNP +Q11 Net-_J1-Pad3_ Net-_Q10-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q7 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad2_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_C2-Pad1_ eSim_NPN +R7 Net-_Q10-Pad2_ Net-_C2-Pad1_ 50k +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 15p +D1 Net-_C2-Pad2_ Net-_C2-Pad1_ eSim_Diode +Q6 Net-_J1-Pad3_ Net-_C2-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R6 Net-_Q6-Pad3_ Net-_C1-Pad2_ 50k +R8 Net-_Q11-Pad3_ Net-_R10-Pad2_ 27 +R9 Net-_R10-Pad2_ Net-_Q12-Pad3_ 27 +Q12 Net-_C1-Pad2_ Net-_C2-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q8 Net-_C2-Pad1_ Net-_Q6-Pad3_ Net-_C1-Pad2_ eSim_NPN +Q14 Net-_Q13-Pad1_ Net-_J1-Pad1_ Net-_Q14-Pad3_ eSim_NPN +R11 Net-_Q14-Pad3_ Net-_C1-Pad2_ 5.8k +J1 Net-_J1-Pad1_ Net-_C1-Pad2_ Net-_J1-Pad3_ jfet_n +U2 Net-_C1-Pad2_ Net-_J1-Pad1_ zener +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 120 +R14 Net-_J1-Pad3_ Net-_Q17-Pad3_ 8.7k +Q17 Net-_Q15-Pad3_ Net-_Q17-Pad2_ Net-_Q17-Pad3_ eSim_PNP +Q19 Net-_C4-Pad2_ Net-_Q19-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q15 Net-_Q15-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q16 Net-_Q15-Pad1_ Net-_Q15-Pad1_ Net-_C3-Pad1_ eSim_NPN +Q18 Net-_C4-Pad2_ Net-_Q15-Pad1_ Net-_Q18-Pad3_ eSim_NPN +R13 Net-_C3-Pad1_ Net-_C1-Pad2_ 5k +C3 Net-_C3-Pad1_ Net-_C1-Pad2_ 15p +R15 Net-_Q18-Pad3_ Net-_C1-Pad2_ 5k +Q23 Net-_Q21-Pad1_ Net-_Q17-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q27 Net-_Q17-Pad2_ Net-_Q17-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q25 Net-_J1-Pad3_ Net-_Q21-Pad1_ Net-_Q25-Pad3_ eSim_NPN +Q21 Net-_Q21-Pad1_ Net-_Q21-Pad1_ Net-_Q21-Pad3_ eSim_NPN +Q24 Net-_Q21-Pad1_ Net-_Q21-Pad3_ Net-_C4-Pad1_ eSim_NPN +R18 Net-_Q21-Pad3_ Net-_C4-Pad1_ 50k +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 15p +D2 Net-_C4-Pad2_ Net-_C4-Pad1_ eSim_Diode +Q20 Net-_J1-Pad3_ Net-_C4-Pad2_ Net-_Q20-Pad3_ eSim_NPN +R16 Net-_Q20-Pad3_ Net-_C1-Pad2_ 50k +R19 Net-_Q25-Pad3_ Net-_R19-Pad2_ 27 +R20 Net-_R19-Pad2_ Net-_Q26-Pad3_ 27 +Q26 Net-_C1-Pad2_ Net-_C4-Pad1_ Net-_Q26-Pad3_ eSim_PNP +Q22 Net-_C4-Pad1_ Net-_Q20-Pad3_ Net-_C1-Pad2_ eSim_NPN +Q28 Net-_Q17-Pad2_ Net-_J2-Pad1_ Net-_Q28-Pad3_ eSim_NPN +R22 Net-_Q28-Pad3_ Net-_C1-Pad2_ 5.8k +J2 Net-_J2-Pad1_ Net-_C1-Pad2_ Net-_J1-Pad3_ jfet_n +U3 Net-_C1-Pad2_ Net-_J2-Pad1_ zener +R21 Net-_R21-Pad1_ Net-_R19-Pad2_ 120 +U1 Net-_R10-Pad1_ Net-_Q1-Pad2_ Net-_Q5-Pad2_ Net-_C1-Pad2_ Net-_Q19-Pad2_ Net-_Q15-Pad2_ Net-_R21-Pad1_ Net-_J1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir.out b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir.out new file mode 100644 index 00000000..417a2f72 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir.out @@ -0,0 +1,78 @@ +* d:\fossee\esim\library\subcircuitlibrary\rc4559n_ic\rc4559n_ic.cir + +.include NPN.lib +.include PNP.lib +.include NJF.lib +.include D.lib +r3 net-_j1-pad3_ net-_q3-pad3_ 8.7k +q3 net-_q1-pad3_ net-_q13-pad1_ net-_q3-pad3_ Q2N2907A +q5 net-_c2-pad2_ net-_q5-pad2_ net-_q1-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q2 net-_q1-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222 +q4 net-_c2-pad2_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 +r2 net-_c1-pad1_ net-_c1-pad2_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 15p +r4 net-_q4-pad3_ net-_c1-pad2_ 5k +q9 net-_q10-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q11 net-_j1-pad3_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q7 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_c2-pad1_ Q2N2222 +r7 net-_q10-pad2_ net-_c2-pad1_ 50k +c2 net-_c2-pad1_ net-_c2-pad2_ 15p +d1 net-_c2-pad2_ net-_c2-pad1_ 1N4148 +q6 net-_j1-pad3_ net-_c2-pad2_ net-_q6-pad3_ Q2N2222 +r6 net-_q6-pad3_ net-_c1-pad2_ 50k +r8 net-_q11-pad3_ net-_r10-pad2_ 27 +r9 net-_r10-pad2_ net-_q12-pad3_ 27 +q12 net-_c1-pad2_ net-_c2-pad1_ net-_q12-pad3_ Q2N2907A +q8 net-_c2-pad1_ net-_q6-pad3_ net-_c1-pad2_ Q2N2222 +q14 net-_q13-pad1_ net-_j1-pad1_ net-_q14-pad3_ Q2N2222 +r11 net-_q14-pad3_ net-_c1-pad2_ 5.8k +j1 net-_j1-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u2 net-_c1-pad2_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 120 +r14 net-_j1-pad3_ net-_q17-pad3_ 8.7k +q17 net-_q15-pad3_ net-_q17-pad2_ net-_q17-pad3_ Q2N2907A +q19 net-_c4-pad2_ net-_q19-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q15-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad1_ Q2N2222 +q18 net-_c4-pad2_ net-_q15-pad1_ net-_q18-pad3_ Q2N2222 +r13 net-_c3-pad1_ net-_c1-pad2_ 5k +c3 net-_c3-pad1_ net-_c1-pad2_ 15p +r15 net-_q18-pad3_ net-_c1-pad2_ 5k +q23 net-_q21-pad1_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q27 net-_q17-pad2_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q25 net-_j1-pad3_ net-_q21-pad1_ net-_q25-pad3_ Q2N2222 +q21 net-_q21-pad1_ net-_q21-pad1_ net-_q21-pad3_ Q2N2222 +q24 net-_q21-pad1_ net-_q21-pad3_ net-_c4-pad1_ Q2N2222 +r18 net-_q21-pad3_ net-_c4-pad1_ 50k +c4 net-_c4-pad1_ net-_c4-pad2_ 15p +d2 net-_c4-pad2_ net-_c4-pad1_ 1N4148 +q20 net-_j1-pad3_ net-_c4-pad2_ net-_q20-pad3_ Q2N2222 +r16 net-_q20-pad3_ net-_c1-pad2_ 50k +r19 net-_q25-pad3_ net-_r19-pad2_ 27 +r20 net-_r19-pad2_ net-_q26-pad3_ 27 +q26 net-_c1-pad2_ net-_c4-pad1_ net-_q26-pad3_ Q2N2907A +q22 net-_c4-pad1_ net-_q20-pad3_ net-_c1-pad2_ Q2N2222 +q28 net-_q17-pad2_ net-_j2-pad1_ net-_q28-pad3_ Q2N2222 +r22 net-_q28-pad3_ net-_c1-pad2_ 5.8k +j2 net-_j2-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u3 net-_c1-pad2_ net-_j2-pad1_ zener +r21 net-_r21-pad1_ net-_r19-pad2_ 120 +* u1 net-_r10-pad1_ net-_q1-pad2_ net-_q5-pad2_ net-_c1-pad2_ net-_q19-pad2_ net-_q15-pad2_ net-_r21-pad1_ net-_j1-pad3_ port +a1 net-_c1-pad2_ net-_j1-pad1_ u2 +a2 net-_c1-pad2_ net-_j2-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.pro b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sch b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sch new file mode 100644 index 00000000..9133b092 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sch @@ -0,0 +1,1107 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:RC4559N_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R3 +U 1 1 66744C0E +P 8000 6800 +F 0 "R3" H 8050 6930 50 0000 C CNN +F 1 "8.7k" H 8050 6750 50 0000 C CNN +F 2 "" H 8050 6780 30 0000 C CNN +F 3 "" V 8050 6850 30 0000 C CNN + 1 8000 6800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 66744C0F +P 8150 7350 +F 0 "Q3" H 8050 7400 50 0000 R CNN +F 1 "eSim_PNP" H 8100 7500 50 0000 R CNN +F 2 "" H 8350 7450 29 0000 C CNN +F 3 "" H 8150 7350 60 0000 C CNN + 1 8150 7350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 66744C10 +P 8850 7950 +F 0 "Q5" H 8750 8000 50 0000 R CNN +F 1 "eSim_PNP" H 8800 8100 50 0000 R CNN +F 2 "" H 9050 8050 29 0000 C CNN +F 3 "" H 8850 7950 60 0000 C CNN + 1 8850 7950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 66744C11 +P 7650 7950 +F 0 "Q1" H 7550 8000 50 0000 R CNN +F 1 "eSim_PNP" H 7600 8100 50 0000 R CNN +F 2 "" H 7850 8050 29 0000 C CNN +F 3 "" H 7650 7950 60 0000 C CNN + 1 7650 7950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 66744C12 +P 7850 9600 +F 0 "Q2" H 7750 9650 50 0000 R CNN +F 1 "eSim_NPN" H 7800 9750 50 0000 R CNN +F 2 "" H 8050 9700 29 0000 C CNN +F 3 "" H 7850 9600 60 0000 C CNN + 1 7850 9600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 66744C13 +P 8650 9600 +F 0 "Q4" H 8550 9650 50 0000 R CNN +F 1 "eSim_NPN" H 8600 9750 50 0000 R CNN +F 2 "" H 8850 9700 29 0000 C CNN +F 3 "" H 8650 9600 60 0000 C CNN + 1 8650 9600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 66744C14 +P 7700 10150 +F 0 "R2" H 7750 10280 50 0000 C CNN +F 1 "5k" H 7750 10100 50 0000 C CNN +F 2 "" H 7750 10130 30 0000 C CNN +F 3 "" V 7750 10200 30 0000 C CNN + 1 7700 10150 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 66744C15 +P 8250 10200 +F 0 "C1" H 8275 10300 50 0000 L CNN +F 1 "15p" H 8275 10100 50 0000 L CNN +F 2 "" H 8288 10050 30 0000 C CNN +F 3 "" H 8250 10200 60 0000 C CNN + 1 8250 10200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 66744C16 +P 8700 10100 +F 0 "R4" H 8750 10230 50 0000 C CNN +F 1 "5k" H 8750 10050 50 0000 C CNN +F 2 "" H 8750 10080 30 0000 C CNN +F 3 "" V 8750 10150 30 0000 C CNN + 1 8700 10100 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 66744C17 +P 10850 7350 +F 0 "Q9" H 10750 7400 50 0000 R CNN +F 1 "eSim_PNP" H 10800 7500 50 0000 R CNN +F 2 "" H 11050 7450 29 0000 C CNN +F 3 "" H 10850 7350 60 0000 C CNN + 1 10850 7350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q13 +U 1 1 66744C18 +P 12500 7350 +F 0 "Q13" H 12400 7400 50 0000 R CNN +F 1 "eSim_PNP" H 12450 7500 50 0000 R CNN +F 2 "" H 12700 7450 29 0000 C CNN +F 3 "" H 12500 7350 60 0000 C CNN + 1 12500 7350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 66744C19 +P 11700 7900 +F 0 "Q11" H 11600 7950 50 0000 R CNN +F 1 "eSim_NPN" H 11650 8050 50 0000 R CNN +F 2 "" H 11900 8000 29 0000 C CNN +F 3 "" H 11700 7900 60 0000 C CNN + 1 11700 7900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 66744C1A +P 10400 8200 +F 0 "Q7" H 10300 8250 50 0000 R CNN +F 1 "eSim_NPN" H 10350 8350 50 0000 R CNN +F 2 "" H 10600 8300 29 0000 C CNN +F 3 "" H 10400 8200 60 0000 C CNN + 1 10400 8200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 66744C1B +P 10950 8600 +F 0 "Q10" H 10850 8650 50 0000 R CNN +F 1 "eSim_NPN" H 10900 8750 50 0000 R CNN +F 2 "" H 11150 8700 29 0000 C CNN +F 3 "" H 10950 8600 60 0000 C CNN + 1 10950 8600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 66744C1C +P 10250 9000 +F 0 "R7" H 10300 9130 50 0000 C CNN +F 1 "50k" H 10300 8950 50 0000 C CNN +F 2 "" H 10300 8980 30 0000 C CNN +F 3 "" V 10300 9050 30 0000 C CNN + 1 10250 9000 + 0 1 1 0 +$EndComp +$Comp +L capacitor C2 +U 1 1 66744C1D +P 9100 9100 +F 0 "C2" H 9125 9200 50 0000 L CNN +F 1 "15p" H 9125 9000 50 0000 L CNN +F 2 "" H 9138 8950 30 0000 C CNN +F 3 "" H 9100 9100 60 0000 C CNN + 1 9100 9100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 66744C1E +P 9100 8850 +F 0 "D1" H 9100 8950 50 0000 C CNN +F 1 "eSim_Diode" H 9100 8750 50 0000 C CNN +F 2 "" H 9100 8850 60 0000 C CNN +F 3 "" H 9100 8850 60 0000 C CNN + 1 9100 8850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 66744C1F +P 9500 9350 +F 0 "Q6" H 9400 9400 50 0000 R CNN +F 1 "eSim_NPN" H 9450 9500 50 0000 R CNN +F 2 "" H 9700 9450 29 0000 C CNN +F 3 "" H 9500 9350 60 0000 C CNN + 1 9500 9350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 66744C20 +P 9550 10050 +F 0 "R6" H 9600 10180 50 0000 C CNN +F 1 "50k" H 9600 10000 50 0000 C CNN +F 2 "" H 9600 10030 30 0000 C CNN +F 3 "" V 9600 10100 30 0000 C CNN + 1 9550 10050 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 66744C21 +P 11750 8400 +F 0 "R8" H 11800 8530 50 0000 C CNN +F 1 "27" H 11800 8350 50 0000 C CNN +F 2 "" H 11800 8380 30 0000 C CNN +F 3 "" V 11800 8450 30 0000 C CNN + 1 11750 8400 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 66744C22 +P 11750 8900 +F 0 "R9" H 11800 9030 50 0000 C CNN +F 1 "27" H 11800 8850 50 0000 C CNN +F 2 "" H 11800 8880 30 0000 C CNN +F 3 "" V 11800 8950 30 0000 C CNN + 1 11750 8900 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 66744C23 +P 11700 9400 +F 0 "Q12" H 11600 9450 50 0000 R CNN +F 1 "eSim_PNP" H 11650 9550 50 0000 R CNN +F 2 "" H 11900 9500 29 0000 C CNN +F 3 "" H 11700 9400 60 0000 C CNN + 1 11700 9400 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 66744C24 +P 10800 9800 +F 0 "Q8" H 10700 9850 50 0000 R CNN +F 1 "eSim_NPN" H 10750 9950 50 0000 R CNN +F 2 "" H 11000 9900 29 0000 C CNN +F 3 "" H 10800 9800 60 0000 C CNN + 1 10800 9800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 66744C25 +P 12700 8850 +F 0 "Q14" H 12600 8900 50 0000 R CNN +F 1 "eSim_NPN" H 12650 9000 50 0000 R CNN +F 2 "" H 12900 8950 29 0000 C CNN +F 3 "" H 12700 8850 60 0000 C CNN + 1 12700 8850 + -1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 66744C26 +P 12550 9550 +F 0 "R11" H 12600 9680 50 0000 C CNN +F 1 "5.8k" H 12600 9500 50 0000 C CNN +F 2 "" H 12600 9530 30 0000 C CNN +F 3 "" V 12600 9600 30 0000 C CNN + 1 12550 9550 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J1 +U 1 1 66744C27 +P 13400 8200 +F 0 "J1" H 13300 8250 50 0000 R CNN +F 1 "jfet_n" H 13350 8350 50 0000 R CNN +F 2 "" H 13600 8300 29 0000 C CNN +F 3 "" H 13400 8200 60 0000 C CNN + 1 13400 8200 + -1 0 0 1 +$EndComp +$Comp +L zener U2 +U 1 1 66744C28 +P 13300 9250 +F 0 "U2" H 13250 9150 60 0000 C CNN +F 1 "zener" H 13300 9350 60 0000 C CNN +F 2 "" H 13350 9250 60 0000 C CNN +F 3 "" H 13350 9250 60 0000 C CNN + 1 13300 9250 + 0 1 -1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 66744C29 +P 12200 8650 +F 0 "R10" H 12250 8780 50 0000 C CNN +F 1 "120" H 12250 8600 50 0000 C CNN +F 2 "" H 12250 8630 30 0000 C CNN +F 3 "" V 12250 8700 30 0000 C CNN + 1 12200 8650 + -1 0 0 1 +$EndComp +$Comp +L resistor R14 +U 1 1 66744C2A +P 16200 7000 +F 0 "R14" H 16250 7130 50 0000 C CNN +F 1 "8.7k" H 16250 6950 50 0000 C CNN +F 2 "" H 16250 6980 30 0000 C CNN +F 3 "" V 16250 7050 30 0000 C CNN + 1 16200 7000 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 66744C2B +P 16350 7550 +F 0 "Q17" H 16250 7600 50 0000 R CNN +F 1 "eSim_PNP" H 16300 7700 50 0000 R CNN +F 2 "" H 16550 7650 29 0000 C CNN +F 3 "" H 16350 7550 60 0000 C CNN + 1 16350 7550 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 66744C2C +P 17050 8150 +F 0 "Q19" H 16950 8200 50 0000 R CNN +F 1 "eSim_PNP" H 17000 8300 50 0000 R CNN +F 2 "" H 17250 8250 29 0000 C CNN +F 3 "" H 17050 8150 60 0000 C CNN + 1 17050 8150 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 66744C2D +P 15850 8150 +F 0 "Q15" H 15750 8200 50 0000 R CNN +F 1 "eSim_PNP" H 15800 8300 50 0000 R CNN +F 2 "" H 16050 8250 29 0000 C CNN +F 3 "" H 15850 8150 60 0000 C CNN + 1 15850 8150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 66744C2E +P 16050 9800 +F 0 "Q16" H 15950 9850 50 0000 R CNN +F 1 "eSim_NPN" H 16000 9950 50 0000 R CNN +F 2 "" H 16250 9900 29 0000 C CNN +F 3 "" H 16050 9800 60 0000 C CNN + 1 16050 9800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 66744C2F +P 16850 9800 +F 0 "Q18" H 16750 9850 50 0000 R CNN +F 1 "eSim_NPN" H 16800 9950 50 0000 R CNN +F 2 "" H 17050 9900 29 0000 C CNN +F 3 "" H 16850 9800 60 0000 C CNN + 1 16850 9800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 66744C30 +P 15900 10350 +F 0 "R13" H 15950 10480 50 0000 C CNN +F 1 "5k" H 15950 10300 50 0000 C CNN +F 2 "" H 15950 10330 30 0000 C CNN +F 3 "" V 15950 10400 30 0000 C CNN + 1 15900 10350 + 0 1 1 0 +$EndComp +$Comp +L capacitor C3 +U 1 1 66744C31 +P 16450 10400 +F 0 "C3" H 16475 10500 50 0000 L CNN +F 1 "15p" H 16475 10300 50 0000 L CNN +F 2 "" H 16488 10250 30 0000 C CNN +F 3 "" H 16450 10400 60 0000 C CNN + 1 16450 10400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R15 +U 1 1 66744C32 +P 16900 10300 +F 0 "R15" H 16950 10430 50 0000 C CNN +F 1 "5k" H 16950 10250 50 0000 C CNN +F 2 "" H 16950 10280 30 0000 C CNN +F 3 "" V 16950 10350 30 0000 C CNN + 1 16900 10300 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q23 +U 1 1 66744C33 +P 19050 7550 +F 0 "Q23" H 18950 7600 50 0000 R CNN +F 1 "eSim_PNP" H 19000 7700 50 0000 R CNN +F 2 "" H 19250 7650 29 0000 C CNN +F 3 "" H 19050 7550 60 0000 C CNN + 1 19050 7550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q27 +U 1 1 66744C34 +P 20700 7550 +F 0 "Q27" H 20600 7600 50 0000 R CNN +F 1 "eSim_PNP" H 20650 7700 50 0000 R CNN +F 2 "" H 20900 7650 29 0000 C CNN +F 3 "" H 20700 7550 60 0000 C CNN + 1 20700 7550 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q25 +U 1 1 66744C35 +P 19900 8100 +F 0 "Q25" H 19800 8150 50 0000 R CNN +F 1 "eSim_NPN" H 19850 8250 50 0000 R CNN +F 2 "" H 20100 8200 29 0000 C CNN +F 3 "" H 19900 8100 60 0000 C CNN + 1 19900 8100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 66744C36 +P 18600 8400 +F 0 "Q21" H 18500 8450 50 0000 R CNN +F 1 "eSim_NPN" H 18550 8550 50 0000 R CNN +F 2 "" H 18800 8500 29 0000 C CNN +F 3 "" H 18600 8400 60 0000 C CNN + 1 18600 8400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q24 +U 1 1 66744C37 +P 19150 8800 +F 0 "Q24" H 19050 8850 50 0000 R CNN +F 1 "eSim_NPN" H 19100 8950 50 0000 R CNN +F 2 "" H 19350 8900 29 0000 C CNN +F 3 "" H 19150 8800 60 0000 C CNN + 1 19150 8800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R18 +U 1 1 66744C38 +P 18450 9200 +F 0 "R18" H 18500 9330 50 0000 C CNN +F 1 "50k" H 18500 9150 50 0000 C CNN +F 2 "" H 18500 9180 30 0000 C CNN +F 3 "" V 18500 9250 30 0000 C CNN + 1 18450 9200 + 0 1 1 0 +$EndComp +$Comp +L capacitor C4 +U 1 1 66744C39 +P 17300 9300 +F 0 "C4" H 17325 9400 50 0000 L CNN +F 1 "15p" H 17325 9200 50 0000 L CNN +F 2 "" H 17338 9150 30 0000 C CNN +F 3 "" H 17300 9300 60 0000 C CNN + 1 17300 9300 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 66744C3A +P 17300 9050 +F 0 "D2" H 17300 9150 50 0000 C CNN +F 1 "eSim_Diode" H 17300 8950 50 0000 C CNN +F 2 "" H 17300 9050 60 0000 C CNN +F 3 "" H 17300 9050 60 0000 C CNN + 1 17300 9050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 66744C3B +P 17700 9550 +F 0 "Q20" H 17600 9600 50 0000 R CNN +F 1 "eSim_NPN" H 17650 9700 50 0000 R CNN +F 2 "" H 17900 9650 29 0000 C CNN +F 3 "" H 17700 9550 60 0000 C CNN + 1 17700 9550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R16 +U 1 1 66744C3C +P 17750 10250 +F 0 "R16" H 17800 10380 50 0000 C CNN +F 1 "50k" H 17800 10200 50 0000 C CNN +F 2 "" H 17800 10230 30 0000 C CNN +F 3 "" V 17800 10300 30 0000 C CNN + 1 17750 10250 + 0 1 1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 66744C3D +P 19950 8600 +F 0 "R19" H 20000 8730 50 0000 C CNN +F 1 "27" H 20000 8550 50 0000 C CNN +F 2 "" H 20000 8580 30 0000 C CNN +F 3 "" V 20000 8650 30 0000 C CNN + 1 19950 8600 + 0 1 1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 66744C3E +P 19950 9100 +F 0 "R20" H 20000 9230 50 0000 C CNN +F 1 "27" H 20000 9050 50 0000 C CNN +F 2 "" H 20000 9080 30 0000 C CNN +F 3 "" V 20000 9150 30 0000 C CNN + 1 19950 9100 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q26 +U 1 1 66744C3F +P 19900 9600 +F 0 "Q26" H 19800 9650 50 0000 R CNN +F 1 "eSim_PNP" H 19850 9750 50 0000 R CNN +F 2 "" H 20100 9700 29 0000 C CNN +F 3 "" H 19900 9600 60 0000 C CNN + 1 19900 9600 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q22 +U 1 1 66744C40 +P 19000 10000 +F 0 "Q22" H 18900 10050 50 0000 R CNN +F 1 "eSim_NPN" H 18950 10150 50 0000 R CNN +F 2 "" H 19200 10100 29 0000 C CNN +F 3 "" H 19000 10000 60 0000 C CNN + 1 19000 10000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q28 +U 1 1 66744C41 +P 20900 9050 +F 0 "Q28" H 20800 9100 50 0000 R CNN +F 1 "eSim_NPN" H 20850 9200 50 0000 R CNN +F 2 "" H 21100 9150 29 0000 C CNN +F 3 "" H 20900 9050 60 0000 C CNN + 1 20900 9050 + -1 0 0 -1 +$EndComp +$Comp +L resistor R22 +U 1 1 66744C42 +P 20750 9750 +F 0 "R22" H 20800 9880 50 0000 C CNN +F 1 "5.8k" H 20800 9700 50 0000 C CNN +F 2 "" H 20800 9730 30 0000 C CNN +F 3 "" V 20800 9800 30 0000 C CNN + 1 20750 9750 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J2 +U 1 1 66744C43 +P 21600 8400 +F 0 "J2" H 21500 8450 50 0000 R CNN +F 1 "jfet_n" H 21550 8550 50 0000 R CNN +F 2 "" H 21800 8500 29 0000 C CNN +F 3 "" H 21600 8400 60 0000 C CNN + 1 21600 8400 + -1 0 0 1 +$EndComp +$Comp +L zener U3 +U 1 1 66744C44 +P 21500 9450 +F 0 "U3" H 21450 9350 60 0000 C CNN +F 1 "zener" H 21500 9550 60 0000 C CNN +F 2 "" H 21550 9450 60 0000 C CNN +F 3 "" H 21550 9450 60 0000 C CNN + 1 21500 9450 + 0 1 -1 0 +$EndComp +$Comp +L resistor R21 +U 1 1 66744C45 +P 20400 8850 +F 0 "R21" H 20450 8980 50 0000 C CNN +F 1 "120" H 20450 8800 50 0000 C CNN +F 2 "" H 20450 8830 30 0000 C CNN +F 3 "" V 20450 8900 30 0000 C CNN + 1 20400 8850 + -1 0 0 1 +$EndComp +Wire Wire Line + 8050 7150 8050 7000 +Wire Wire Line + 7750 7700 8750 7700 +Wire Wire Line + 7750 7700 7750 7750 +Wire Wire Line + 8050 7550 8050 7700 +Connection ~ 8050 7700 +Wire Wire Line + 8050 9600 8450 9600 +Wire Wire Line + 7750 8150 7750 9400 +Wire Wire Line + 8150 9600 8150 9300 +Wire Wire Line + 8150 9300 7750 9300 +Connection ~ 7750 9300 +Connection ~ 8150 9600 +Wire Wire Line + 7750 10050 7750 9800 +Wire Wire Line + 8250 10050 8250 9950 +Wire Wire Line + 8250 9950 7750 9950 +Connection ~ 7750 9950 +Wire Wire Line + 7750 10350 7750 10450 +Wire Wire Line + 7700 10450 13750 10450 +Wire Wire Line + 8250 10450 8250 10350 +Wire Wire Line + 8750 9800 8750 10000 +Wire Wire Line + 8750 10450 8750 10300 +Connection ~ 8250 10450 +Wire Wire Line + 8750 7700 8750 7750 +Wire Wire Line + 8750 8150 8750 9400 +Wire Wire Line + 6450 6700 13300 6700 +Wire Wire Line + 8350 7350 12300 7350 +Wire Wire Line + 10300 7900 11500 7900 +Wire Wire Line + 10300 7900 10300 8000 +Wire Wire Line + 10950 7550 10950 7900 +Connection ~ 10950 7900 +Connection ~ 11050 7900 +Wire Wire Line + 10300 8400 10300 8900 +Wire Wire Line + 10300 8600 10750 8600 +Wire Wire Line + 11050 8400 11050 7900 +Wire Wire Line + 10600 8200 11050 8200 +Connection ~ 11050 8200 +Connection ~ 10300 8600 +Wire Wire Line + 9300 9350 8750 9350 +Connection ~ 8750 9350 +Wire Wire Line + 8950 9100 8750 9100 +Connection ~ 8750 9100 +Wire Wire Line + 9600 9150 9600 6700 +Connection ~ 9600 6700 +Wire Wire Line + 8950 8850 8850 8850 +Wire Wire Line + 8850 8850 8850 9100 +Connection ~ 8850 9100 +Wire Wire Line + 9600 10450 9600 10250 +Connection ~ 8750 10450 +Connection ~ 10650 7350 +Wire Wire Line + 10950 7150 10950 6700 +Connection ~ 10950 6700 +Wire Wire Line + 11800 6700 11800 7700 +Wire Wire Line + 11500 9400 9850 9400 +Wire Wire Line + 9850 9400 9850 9100 +Wire Wire Line + 9850 9100 9250 9100 +Wire Wire Line + 9250 8850 9400 8850 +Wire Wire Line + 9400 8850 9400 9100 +Connection ~ 9400 9100 +Wire Wire Line + 10300 9200 10300 9400 +Connection ~ 10300 9400 +Wire Wire Line + 11050 8800 11050 9400 +Connection ~ 11050 9400 +Wire Wire Line + 9600 9950 9600 9550 +Wire Wire Line + 10600 9800 9600 9800 +Connection ~ 9600 9800 +Wire Wire Line + 10900 10450 10900 10000 +Connection ~ 9600 10450 +Wire Wire Line + 11800 10450 11800 9600 +Connection ~ 10900 10450 +Wire Wire Line + 11800 8100 11800 8300 +Wire Wire Line + 11800 8600 11800 8800 +Wire Wire Line + 11800 9200 11800 9100 +Wire Wire Line + 12600 6700 12600 7150 +Connection ~ 11800 6700 +Wire Wire Line + 12600 8650 12600 7550 +Wire Wire Line + 12600 9450 12600 9050 +Wire Wire Line + 12600 10450 12600 9750 +Connection ~ 11800 10450 +Wire Wire Line + 13300 8400 13300 8950 +Wire Wire Line + 12900 8850 13300 8850 +Connection ~ 13300 8850 +Wire Wire Line + 13300 10450 13300 9450 +Connection ~ 12600 10450 +Wire Wire Line + 13300 6700 13300 8000 +Connection ~ 12600 6700 +Wire Wire Line + 13600 8200 13750 8200 +Wire Wire Line + 13750 8200 13750 10450 +Connection ~ 13300 10450 +Wire Wire Line + 12200 7350 12200 7700 +Wire Wire Line + 12200 7700 12600 7700 +Connection ~ 12600 7700 +Connection ~ 12200 7350 +Wire Wire Line + 12000 8700 11800 8700 +Connection ~ 11800 8700 +Wire Wire Line + 12300 8700 14100 8700 +Wire Wire Line + 10900 9600 10900 9400 +Connection ~ 10900 9400 +Connection ~ 8050 6700 +Connection ~ 7750 10450 +Wire Wire Line + 9250 7950 9050 7950 +Wire Wire Line + 16250 7350 16250 7200 +Wire Wire Line + 15950 7900 16950 7900 +Wire Wire Line + 15950 7900 15950 7950 +Wire Wire Line + 16250 7750 16250 7900 +Connection ~ 16250 7900 +Wire Wire Line + 16250 9800 16650 9800 +Wire Wire Line + 15950 8350 15950 9600 +Wire Wire Line + 16350 9800 16350 9500 +Wire Wire Line + 16350 9500 15950 9500 +Connection ~ 15950 9500 +Connection ~ 16350 9800 +Wire Wire Line + 15950 10250 15950 10000 +Wire Wire Line + 16450 10250 16450 10150 +Wire Wire Line + 16450 10150 15950 10150 +Connection ~ 15950 10150 +Wire Wire Line + 15950 10550 15950 10650 +Wire Wire Line + 16450 10650 16450 10550 +Wire Wire Line + 16950 10000 16950 10200 +Wire Wire Line + 16950 10650 16950 10500 +Connection ~ 16450 10650 +Wire Wire Line + 16950 7900 16950 7950 +Wire Wire Line + 16950 8350 16950 9600 +Wire Wire Line + 16550 7550 20500 7550 +Wire Wire Line + 18500 8100 19700 8100 +Wire Wire Line + 18500 8100 18500 8200 +Wire Wire Line + 19150 7750 19150 8100 +Connection ~ 19150 8100 +Connection ~ 19250 8100 +Wire Wire Line + 18500 8600 18500 9100 +Wire Wire Line + 18500 8800 18950 8800 +Wire Wire Line + 19250 8600 19250 8100 +Wire Wire Line + 18800 8400 19250 8400 +Connection ~ 19250 8400 +Connection ~ 18500 8800 +Wire Wire Line + 17500 9550 16950 9550 +Connection ~ 16950 9550 +Wire Wire Line + 17150 9300 16950 9300 +Connection ~ 16950 9300 +Wire Wire Line + 17800 9350 17800 6900 +Connection ~ 17800 6900 +Wire Wire Line + 17150 9050 17050 9050 +Wire Wire Line + 17050 9050 17050 9300 +Connection ~ 17050 9300 +Wire Wire Line + 17800 10650 17800 10450 +Connection ~ 16950 10650 +Connection ~ 18850 7550 +Wire Wire Line + 19150 7350 19150 6900 +Connection ~ 19150 6900 +Wire Wire Line + 20000 6900 20000 7900 +Wire Wire Line + 19700 9600 18050 9600 +Wire Wire Line + 18050 9600 18050 9300 +Wire Wire Line + 18050 9300 17450 9300 +Wire Wire Line + 17450 9050 17600 9050 +Wire Wire Line + 17600 9050 17600 9300 +Connection ~ 17600 9300 +Wire Wire Line + 18500 9400 18500 9600 +Connection ~ 18500 9600 +Wire Wire Line + 19250 9000 19250 9600 +Connection ~ 19250 9600 +Wire Wire Line + 17800 10150 17800 9750 +Wire Wire Line + 18800 10000 17800 10000 +Connection ~ 17800 10000 +Wire Wire Line + 19100 10650 19100 10200 +Connection ~ 17800 10650 +Wire Wire Line + 20000 10650 20000 9800 +Connection ~ 19100 10650 +Wire Wire Line + 20000 8300 20000 8500 +Wire Wire Line + 20000 8800 20000 9000 +Wire Wire Line + 20000 9400 20000 9300 +Wire Wire Line + 20800 6900 20800 7350 +Connection ~ 20000 6900 +Wire Wire Line + 20800 8850 20800 7750 +Wire Wire Line + 20800 9650 20800 9250 +Wire Wire Line + 20800 10650 20800 9950 +Connection ~ 20000 10650 +Wire Wire Line + 21500 8600 21500 9150 +Wire Wire Line + 21100 9050 21500 9050 +Connection ~ 21500 9050 +Wire Wire Line + 21500 10650 21500 9650 +Connection ~ 20800 10650 +Wire Wire Line + 21500 6900 21500 8200 +Connection ~ 20800 6900 +Wire Wire Line + 21800 8400 21950 8400 +Wire Wire Line + 21950 8400 21950 10650 +Connection ~ 21500 10650 +Wire Wire Line + 20400 7550 20400 7900 +Wire Wire Line + 20400 7900 20800 7900 +Connection ~ 20800 7900 +Connection ~ 20400 7550 +Wire Wire Line + 20200 8900 20000 8900 +Connection ~ 20000 8900 +Wire Wire Line + 20500 8900 22300 8900 +Wire Wire Line + 19100 9800 19100 9600 +Connection ~ 19100 9600 +Connection ~ 16250 6900 +Connection ~ 15950 10650 +Wire Wire Line + 17450 8150 17250 8150 +Wire Wire Line + 15200 6900 21500 6900 +Wire Wire Line + 15200 5300 15200 6900 +Wire Wire Line + 6200 5300 15200 5300 +Wire Wire Line + 21950 10650 7700 10650 +Wire Wire Line + 6450 6700 6450 7000 +Wire Wire Line + 6200 5300 6200 6750 +Wire Wire Line + 6200 6750 6450 6750 +Connection ~ 6450 6750 +Connection ~ 7700 10650 +Wire Wire Line + 6800 7950 7450 7950 +Wire Wire Line + 15000 8150 15650 8150 +Wire Wire Line + 7700 10450 7700 10750 +$Comp +L PORT U1 +U 1 1 66746E63 +P 14350 8700 +F 0 "U1" H 14400 8800 30 0000 C CNN +F 1 "PORT" H 14350 8700 30 0000 C CNN +F 2 "" H 14350 8700 60 0000 C CNN +F 3 "" H 14350 8700 60 0000 C CNN + 1 14350 8700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 66747237 +P 6550 7950 +F 0 "U1" H 6600 8050 30 0000 C CNN +F 1 "PORT" H 6550 7950 30 0000 C CNN +F 2 "" H 6550 7950 60 0000 C CNN +F 3 "" H 6550 7950 60 0000 C CNN + 2 6550 7950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 667472F4 +P 7700 11000 +F 0 "U1" H 7750 11100 30 0000 C CNN +F 1 "PORT" H 7700 11000 30 0000 C CNN +F 2 "" H 7700 11000 60 0000 C CNN +F 3 "" H 7700 11000 60 0000 C CNN + 4 7700 11000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 66747403 +P 9500 7950 +F 0 "U1" H 9550 8050 30 0000 C CNN +F 1 "PORT" H 9500 7950 30 0000 C CNN +F 2 "" H 9500 7950 60 0000 C CNN +F 3 "" H 9500 7950 60 0000 C CNN + 3 9500 7950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 66747B3E +P 17700 8150 +F 0 "U1" H 17750 8250 30 0000 C CNN +F 1 "PORT" H 17700 8150 30 0000 C CNN +F 2 "" H 17700 8150 60 0000 C CNN +F 3 "" H 17700 8150 60 0000 C CNN + 5 17700 8150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 66747BED +P 14750 8150 +F 0 "U1" H 14800 8250 30 0000 C CNN +F 1 "PORT" H 14750 8150 30 0000 C CNN +F 2 "" H 14750 8150 60 0000 C CNN +F 3 "" H 14750 8150 60 0000 C CNN + 6 14750 8150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 66748118 +P 6450 7250 +F 0 "U1" H 6500 7350 30 0000 C CNN +F 1 "PORT" H 6450 7250 30 0000 C CNN +F 2 "" H 6450 7250 60 0000 C CNN +F 3 "" H 6450 7250 60 0000 C CNN + 8 6450 7250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 6674854A +P 22550 8900 +F 0 "U1" H 22600 9000 30 0000 C CNN +F 1 "PORT" H 22550 8900 30 0000 C CNN +F 2 "" H 22550 8900 60 0000 C CNN +F 3 "" H 22550 8900 60 0000 C CNN + 7 22550 8900 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sub b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sub new file mode 100644 index 00000000..46e87586 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sub @@ -0,0 +1,72 @@ +* Subcircuit RC4559N_IC +.subckt RC4559N_IC net-_r10-pad1_ net-_q1-pad2_ net-_q5-pad2_ net-_c1-pad2_ net-_q19-pad2_ net-_q15-pad2_ net-_r21-pad1_ net-_j1-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\rc4559n_ic\rc4559n_ic.cir +.include NPN.lib +.include PNP.lib +.include NJF.lib +.include D.lib +r3 net-_j1-pad3_ net-_q3-pad3_ 8.7k +q3 net-_q1-pad3_ net-_q13-pad1_ net-_q3-pad3_ Q2N2907A +q5 net-_c2-pad2_ net-_q5-pad2_ net-_q1-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q2 net-_q1-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222 +q4 net-_c2-pad2_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 +r2 net-_c1-pad1_ net-_c1-pad2_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 15p +r4 net-_q4-pad3_ net-_c1-pad2_ 5k +q9 net-_q10-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q11 net-_j1-pad3_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q7 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_c2-pad1_ Q2N2222 +r7 net-_q10-pad2_ net-_c2-pad1_ 50k +c2 net-_c2-pad1_ net-_c2-pad2_ 15p +d1 net-_c2-pad2_ net-_c2-pad1_ 1N4148 +q6 net-_j1-pad3_ net-_c2-pad2_ net-_q6-pad3_ Q2N2222 +r6 net-_q6-pad3_ net-_c1-pad2_ 50k +r8 net-_q11-pad3_ net-_r10-pad2_ 27 +r9 net-_r10-pad2_ net-_q12-pad3_ 27 +q12 net-_c1-pad2_ net-_c2-pad1_ net-_q12-pad3_ Q2N2907A +q8 net-_c2-pad1_ net-_q6-pad3_ net-_c1-pad2_ Q2N2222 +q14 net-_q13-pad1_ net-_j1-pad1_ net-_q14-pad3_ Q2N2222 +r11 net-_q14-pad3_ net-_c1-pad2_ 5.8k +j1 net-_j1-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u2 net-_c1-pad2_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 120 +r14 net-_j1-pad3_ net-_q17-pad3_ 8.7k +q17 net-_q15-pad3_ net-_q17-pad2_ net-_q17-pad3_ Q2N2907A +q19 net-_c4-pad2_ net-_q19-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q15-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad1_ Q2N2222 +q18 net-_c4-pad2_ net-_q15-pad1_ net-_q18-pad3_ Q2N2222 +r13 net-_c3-pad1_ net-_c1-pad2_ 5k +c3 net-_c3-pad1_ net-_c1-pad2_ 15p +r15 net-_q18-pad3_ net-_c1-pad2_ 5k +q23 net-_q21-pad1_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q27 net-_q17-pad2_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q25 net-_j1-pad3_ net-_q21-pad1_ net-_q25-pad3_ Q2N2222 +q21 net-_q21-pad1_ net-_q21-pad1_ net-_q21-pad3_ Q2N2222 +q24 net-_q21-pad1_ net-_q21-pad3_ net-_c4-pad1_ Q2N2222 +r18 net-_q21-pad3_ net-_c4-pad1_ 50k +c4 net-_c4-pad1_ net-_c4-pad2_ 15p +d2 net-_c4-pad2_ net-_c4-pad1_ 1N4148 +q20 net-_j1-pad3_ net-_c4-pad2_ net-_q20-pad3_ Q2N2222 +r16 net-_q20-pad3_ net-_c1-pad2_ 50k +r19 net-_q25-pad3_ net-_r19-pad2_ 27 +r20 net-_r19-pad2_ net-_q26-pad3_ 27 +q26 net-_c1-pad2_ net-_c4-pad1_ net-_q26-pad3_ Q2N2907A +q22 net-_c4-pad1_ net-_q20-pad3_ net-_c1-pad2_ Q2N2222 +q28 net-_q17-pad2_ net-_j2-pad1_ net-_q28-pad3_ Q2N2222 +r22 net-_q28-pad3_ net-_c1-pad2_ 5.8k +j2 net-_j2-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u3 net-_c1-pad2_ net-_j2-pad1_ zener +r21 net-_r21-pad1_ net-_r19-pad2_ 120 +a1 net-_c1-pad2_ net-_j1-pad1_ u2 +a2 net-_c1-pad2_ net-_j2-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends RC4559N_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC_Previous_Values.xml b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC_Previous_Values.xml new file mode 100644 index 00000000..e1685a88 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u3></model><devicemodel><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><q27><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q27><q25><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><q24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q26><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q26><q22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q28><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q28><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/RC4559N_sub/analysis b/library/SubcircuitLibrary/RC4559N_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.cir b/library/SubcircuitLibrary/SN54147_sub/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out b/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.pro b/library/SubcircuitLibrary/SN54147_sub/3_and.pro new file mode 100644 index 00000000..da3e199e --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.sch b/library/SubcircuitLibrary/SN54147_sub/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.sub b/library/SubcircuitLibrary/SN54147_sub/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.cir b/library/SubcircuitLibrary/SN54147_sub/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out b/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.pro b/library/SubcircuitLibrary/SN54147_sub/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.sch b/library/SubcircuitLibrary/SN54147_sub/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.sub b/library/SubcircuitLibrary/SN54147_sub/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib new file mode 100644 index 00000000..45b9ccde --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib @@ -0,0 +1,189 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir new file mode 100644 index 00000000..772cd6bf --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir @@ -0,0 +1,64 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN54147_IC\SN54147_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/24 18:32:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U28 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U28-Pad3_ d_and +U29 Net-_U15-Pad2_ Net-_U17-Pad3_ Net-_U29-Pad3_ d_and +U35 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_and +U30 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U30-Pad3_ d_and +U36 Net-_U30-Pad3_ Net-_U17-Pad3_ Net-_U36-Pad3_ d_and +U31 Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U31-Pad3_ d_and +U18 Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U18-Pad3_ d_and +U19 Net-_U14-Pad2_ Net-_U17-Pad3_ Net-_U19-Pad3_ d_and +U33 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U33-Pad3_ d_and +U20 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U14-Pad2_ Net-_U17-Pad3_ Net-_U21-Pad3_ d_and +U34 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U34-Pad3_ d_and +U22 Net-_U15-Pad1_ Net-_U17-Pad3_ Net-_U22-Pad3_ d_and +U23 Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U23-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U7 Net-_U2-Pad11_ Net-_U13-Pad1_ d_inverter +U16 Net-_U10-Pad2_ Net-_U16-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U24 Net-_U13-Pad1_ Net-_U17-Pad3_ Net-_U24-Pad3_ d_and +U25 Net-_U14-Pad1_ Net-_U17-Pad3_ Net-_U25-Pad3_ d_and +U26 Net-_U15-Pad1_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_and +U27 Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U8 Net-_U2-Pad12_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U9 Net-_U2-Pad13_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U6 Net-_U2-Pad14_ Net-_U23-Pad1_ d_inverter +U4 Net-_U2-Pad15_ Net-_U17-Pad1_ d_inverter +U5 Net-_U2-Pad16_ Net-_U17-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nor +X1 Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U17-Pad3_ Net-_U42-Pad1_ 5_and +U32 Net-_U17-Pad2_ Net-_U17-Pad2_ Net-_U32-Pad3_ d_and +U37 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U37-Pad3_ d_nor +U3 Net-_U1-Pad10_ Net-_U11-Pad1_ adc_bridge_1 +U2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad9_ Net-_U10-Pad1_ Net-_U12-Pad1_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8 +U53 Net-_U52-Pad3_ Net-_U51-Pad3_ Net-_U46-Pad3_ Net-_U37-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad13_ dac_bridge_4 +U42 Net-_U42-Pad1_ Net-_U35-Pad3_ Net-_U42-Pad3_ d_nor +U49 Net-_U42-Pad3_ Net-_U36-Pad3_ Net-_U49-Pad3_ d_nor +U43 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U43-Pad3_ d_nor +U52 Net-_U49-Pad3_ Net-_U50-Pad3_ Net-_U52-Pad3_ d_nor +U40 Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_nor +U47 Net-_U40-Pad3_ Net-_U40-Pad3_ Net-_U47-Pad3_ d_nor +U41 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U41-Pad3_ d_nor +U48 Net-_U41-Pad3_ Net-_U41-Pad3_ Net-_U48-Pad3_ d_nor +U51 Net-_U47-Pad3_ Net-_U48-Pad3_ Net-_U51-Pad3_ d_nor +U38 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U38-Pad3_ d_nor +U39 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U39-Pad3_ d_nor +U44 Net-_U38-Pad3_ Net-_U38-Pad3_ Net-_U44-Pad3_ d_nor +U45 Net-_U39-Pad3_ Net-_U39-Pad3_ Net-_U45-Pad3_ d_nor +U46 Net-_U44-Pad3_ Net-_U45-Pad3_ Net-_U46-Pad3_ d_nor +U50 Net-_U43-Pad3_ Net-_U43-Pad3_ Net-_U50-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out new file mode 100644 index 00000000..eedd9eba --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out @@ -0,0 +1,222 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn54147_ic\sn54147_ic.cir + +.include 5_and.sub +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u28 net-_u12-pad2_ net-_u13-pad2_ net-_u28-pad3_ d_and +* u29 net-_u15-pad2_ net-_u17-pad3_ net-_u29-pad3_ d_and +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and +* u30 net-_u14-pad1_ net-_u15-pad2_ net-_u30-pad3_ d_and +* u36 net-_u30-pad3_ net-_u17-pad3_ net-_u36-pad3_ d_and +* u31 net-_u23-pad1_ net-_u17-pad3_ net-_u31-pad3_ d_and +* u18 net-_u10-pad2_ net-_u13-pad2_ net-_u18-pad3_ d_and +* u19 net-_u14-pad2_ net-_u17-pad3_ net-_u19-pad3_ d_and +* u33 net-_u18-pad3_ net-_u19-pad3_ net-_u33-pad3_ d_and +* u20 net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad3_ d_and +* u21 net-_u14-pad2_ net-_u17-pad3_ net-_u21-pad3_ d_and +* u34 net-_u20-pad3_ net-_u21-pad3_ net-_u34-pad3_ d_and +* u22 net-_u15-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and +* u23 net-_u23-pad1_ net-_u17-pad3_ net-_u23-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u7 net-_u2-pad11_ net-_u13-pad1_ d_inverter +* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u24 net-_u13-pad1_ net-_u17-pad3_ net-_u24-pad3_ d_and +* u25 net-_u14-pad1_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u26 net-_u15-pad1_ net-_u17-pad3_ net-_u26-pad3_ d_and +* u27 net-_u23-pad1_ net-_u17-pad3_ net-_u27-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u8 net-_u2-pad12_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u9 net-_u2-pad13_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad14_ net-_u23-pad1_ d_inverter +* u4 net-_u2-pad15_ net-_u17-pad1_ d_inverter +* u5 net-_u2-pad16_ net-_u17-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nor +x1 net-_u11-pad2_ net-_u16-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad3_ net-_u42-pad1_ 5_and +* u32 net-_u17-pad2_ net-_u17-pad2_ net-_u32-pad3_ d_and +* u37 net-_u17-pad1_ net-_u17-pad2_ net-_u37-pad3_ d_nor +* u3 net-_u1-pad10_ net-_u11-pad1_ adc_bridge_1 +* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +* u53 net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ dac_bridge_4 +* u42 net-_u42-pad1_ net-_u35-pad3_ net-_u42-pad3_ d_nor +* u49 net-_u42-pad3_ net-_u36-pad3_ net-_u49-pad3_ d_nor +* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_nor +* u52 net-_u49-pad3_ net-_u50-pad3_ net-_u52-pad3_ d_nor +* u40 net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u47 net-_u40-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor +* u41 net-_u22-pad3_ net-_u23-pad3_ net-_u41-pad3_ d_nor +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nor +* u51 net-_u47-pad3_ net-_u48-pad3_ net-_u51-pad3_ d_nor +* u38 net-_u24-pad3_ net-_u25-pad3_ net-_u38-pad3_ d_nor +* u39 net-_u26-pad3_ net-_u27-pad3_ net-_u39-pad3_ d_nor +* u44 net-_u38-pad3_ net-_u38-pad3_ net-_u44-pad3_ d_nor +* u45 net-_u39-pad3_ net-_u39-pad3_ net-_u45-pad3_ d_nor +* u46 net-_u44-pad3_ net-_u45-pad3_ net-_u46-pad3_ d_nor +* u50 net-_u43-pad3_ net-_u43-pad3_ net-_u50-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port +a1 net-_u11-pad1_ net-_u11-pad2_ u11 +a2 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u28-pad3_ u28 +a3 [net-_u15-pad2_ net-_u17-pad3_ ] net-_u29-pad3_ u29 +a4 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a5 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u30-pad3_ u30 +a6 [net-_u30-pad3_ net-_u17-pad3_ ] net-_u36-pad3_ u36 +a7 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u18-pad3_ u18 +a9 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a10 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u33-pad3_ u33 +a11 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad3_ u20 +a12 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u21-pad3_ u21 +a13 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u34-pad3_ u34 +a14 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22 +a15 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u23-pad3_ u23 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u2-pad11_ net-_u13-pad1_ u7 +a18 net-_u10-pad2_ net-_u16-pad2_ u16 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 [net-_u13-pad1_ net-_u17-pad3_ ] net-_u24-pad3_ u24 +a21 [net-_u14-pad1_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a22 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a23 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u27-pad3_ u27 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u2-pad12_ net-_u14-pad1_ u8 +a26 net-_u14-pad1_ net-_u14-pad2_ u14 +a27 net-_u2-pad13_ net-_u15-pad1_ u9 +a28 net-_u15-pad1_ net-_u15-pad2_ u15 +a29 net-_u2-pad14_ net-_u23-pad1_ u6 +a30 net-_u2-pad15_ net-_u17-pad1_ u4 +a31 net-_u2-pad16_ net-_u17-pad2_ u5 +a32 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a33 [net-_u17-pad2_ net-_u17-pad2_ ] net-_u32-pad3_ u32 +a34 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u37-pad3_ u37 +a35 [net-_u1-pad10_ ] [net-_u11-pad1_ ] u3 +a36 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ ] [net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a37 [net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ ] [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ ] u53 +a38 [net-_u42-pad1_ net-_u35-pad3_ ] net-_u42-pad3_ u42 +a39 [net-_u42-pad3_ net-_u36-pad3_ ] net-_u49-pad3_ u49 +a40 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43 +a41 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u52-pad3_ u52 +a42 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a43 [net-_u40-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u41-pad3_ u41 +a45 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a46 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u51-pad3_ u51 +a47 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u38-pad3_ u38 +a48 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u39-pad3_ u39 +a49 [net-_u38-pad3_ net-_u38-pad3_ ] net-_u44-pad3_ u44 +a50 [net-_u39-pad3_ net-_u39-pad3_ ] net-_u45-pad3_ u45 +a51 [net-_u44-pad3_ net-_u45-pad3_ ] net-_u46-pad3_ u46 +a52 [net-_u43-pad3_ net-_u43-pad3_ ] net-_u50-pad3_ u50 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u53 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u42 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u52 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch new file mode 100644 index 00000000..d1d0e0ff --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch @@ -0,0 +1,1363 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN54147-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 23622 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U11 +U 1 1 6676CB67 +P 9650 4750 +F 0 "U11" H 9650 4650 60 0000 C CNN +F 1 "d_inverter" H 9650 4900 60 0000 C CNN +F 2 "" H 9700 4700 60 0000 C CNN +F 3 "" H 9700 4700 60 0000 C CNN + 1 9650 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 6676CB68 +P 14600 5900 +F 0 "U28" H 14600 5900 60 0000 C CNN +F 1 "d_and" H 14650 6000 60 0000 C CNN +F 2 "" H 14600 5900 60 0000 C CNN +F 3 "" H 14600 5900 60 0000 C CNN + 1 14600 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_and 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PORT U1 +U 8 1 6676CBA4 +P 21250 9800 +F 0 "U1" H 21300 9900 30 0000 C CNN +F 1 "PORT" H 21250 9800 30 0000 C CNN +F 2 "" H 21250 9800 60 0000 C CNN +F 3 "" H 21250 9800 60 0000 C CNN + 8 21250 9800 + -1 0 0 1 +$EndComp +Wire Wire Line + 21000 9800 20900 9800 +Wire Wire Line + 20900 9800 20900 10000 +Wire Wire Line + 20900 10000 20700 10000 +$Comp +L PORT U1 +U 9 1 6676CBA5 +P 5700 10600 +F 0 "U1" H 5750 10700 30 0000 C CNN +F 1 "PORT" H 5700 10600 30 0000 C CNN +F 2 "" H 5700 10600 60 0000 C CNN +F 3 "" H 5700 10600 60 0000 C CNN + 9 5700 10600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 10250 6400 10250 +Wire Wire Line + 6400 10250 6400 10600 +Wire Wire Line + 6400 10600 5950 10600 +$Comp +L PORT U1 +U 10 1 6676CBA6 +P 7350 4750 +F 0 "U1" H 7400 4850 30 0000 C CNN +F 1 "PORT" H 7350 4750 30 0000 C CNN +F 2 "" H 7350 4750 60 0000 C CNN +F 3 "" H 7350 4750 60 0000 C CNN + 10 7350 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 4750 7900 4750 +$Comp +L PORT U1 +U 11 1 6676CBA7 +P 5700 9350 +F 0 "U1" H 5750 9450 30 0000 C CNN +F 1 "PORT" H 5700 9350 30 0000 C CNN +F 2 "" H 5700 9350 60 0000 C CNN +F 3 "" H 5700 9350 60 0000 C CNN + 11 5700 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6676CBA8 +P 5700 9550 +F 0 "U1" H 5750 9650 30 0000 C CNN +F 1 "PORT" H 5700 9550 30 0000 C CNN +F 2 "" H 5700 9550 60 0000 C CNN +F 3 "" H 5700 9550 60 0000 C CNN + 12 5700 9550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 9350 6350 9350 +Wire Wire Line + 6350 9350 6350 9550 +Wire Wire Line + 6350 9550 6500 9550 +Wire Wire Line + 5950 9550 6300 9550 +Wire Wire Line + 6300 9550 6300 9650 +Wire Wire Line + 6300 9650 6500 9650 +$Comp +L PORT U1 +U 13 1 6676CBA9 +P 21250 10450 +F 0 "U1" H 21300 10550 30 0000 C CNN +F 1 "PORT" H 21250 10450 30 0000 C CNN +F 2 "" H 21250 10450 60 0000 C CNN +F 3 "" H 21250 10450 60 0000 C CNN + 13 21250 10450 + -1 0 0 1 +$EndComp +Wire Wire Line + 20700 10300 20900 10300 +Wire Wire Line + 20900 10300 20900 10450 +Wire Wire Line + 20900 10450 21000 10450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub new file mode 100644 index 00000000..f16660b7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub @@ -0,0 +1,216 @@ +* Subcircuit SN54147_IC +.subckt SN54147_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ +* d:\fossee\esim\library\subcircuitlibrary\sn54147_ic\sn54147_ic.cir +.include 5_and.sub +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u28 net-_u12-pad2_ net-_u13-pad2_ net-_u28-pad3_ d_and +* u29 net-_u15-pad2_ net-_u17-pad3_ net-_u29-pad3_ d_and +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and +* u30 net-_u14-pad1_ net-_u15-pad2_ net-_u30-pad3_ d_and +* u36 net-_u30-pad3_ net-_u17-pad3_ net-_u36-pad3_ d_and +* u31 net-_u23-pad1_ net-_u17-pad3_ net-_u31-pad3_ d_and +* u18 net-_u10-pad2_ net-_u13-pad2_ net-_u18-pad3_ d_and +* u19 net-_u14-pad2_ net-_u17-pad3_ net-_u19-pad3_ d_and +* u33 net-_u18-pad3_ net-_u19-pad3_ net-_u33-pad3_ d_and +* u20 net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad3_ d_and +* u21 net-_u14-pad2_ net-_u17-pad3_ net-_u21-pad3_ d_and +* u34 net-_u20-pad3_ net-_u21-pad3_ net-_u34-pad3_ d_and +* u22 net-_u15-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and +* u23 net-_u23-pad1_ net-_u17-pad3_ net-_u23-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u7 net-_u2-pad11_ net-_u13-pad1_ d_inverter +* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u24 net-_u13-pad1_ net-_u17-pad3_ net-_u24-pad3_ d_and +* u25 net-_u14-pad1_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u26 net-_u15-pad1_ net-_u17-pad3_ net-_u26-pad3_ d_and +* u27 net-_u23-pad1_ net-_u17-pad3_ net-_u27-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u8 net-_u2-pad12_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u9 net-_u2-pad13_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad14_ net-_u23-pad1_ d_inverter +* u4 net-_u2-pad15_ net-_u17-pad1_ d_inverter +* u5 net-_u2-pad16_ net-_u17-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nor +x1 net-_u11-pad2_ net-_u16-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad3_ net-_u42-pad1_ 5_and +* u32 net-_u17-pad2_ net-_u17-pad2_ net-_u32-pad3_ d_and +* u37 net-_u17-pad1_ net-_u17-pad2_ net-_u37-pad3_ d_nor +* u3 net-_u1-pad10_ net-_u11-pad1_ adc_bridge_1 +* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +* u53 net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ dac_bridge_4 +* u42 net-_u42-pad1_ net-_u35-pad3_ net-_u42-pad3_ d_nor +* u49 net-_u42-pad3_ net-_u36-pad3_ net-_u49-pad3_ d_nor +* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_nor +* u52 net-_u49-pad3_ net-_u50-pad3_ net-_u52-pad3_ d_nor +* u40 net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u47 net-_u40-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor +* u41 net-_u22-pad3_ net-_u23-pad3_ net-_u41-pad3_ d_nor +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nor +* u51 net-_u47-pad3_ net-_u48-pad3_ net-_u51-pad3_ d_nor +* u38 net-_u24-pad3_ net-_u25-pad3_ net-_u38-pad3_ d_nor +* u39 net-_u26-pad3_ net-_u27-pad3_ net-_u39-pad3_ d_nor +* u44 net-_u38-pad3_ net-_u38-pad3_ net-_u44-pad3_ d_nor +* u45 net-_u39-pad3_ net-_u39-pad3_ net-_u45-pad3_ d_nor +* u46 net-_u44-pad3_ net-_u45-pad3_ net-_u46-pad3_ d_nor +* u50 net-_u43-pad3_ net-_u43-pad3_ net-_u50-pad3_ d_nor +a1 net-_u11-pad1_ net-_u11-pad2_ u11 +a2 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u28-pad3_ u28 +a3 [net-_u15-pad2_ net-_u17-pad3_ ] net-_u29-pad3_ u29 +a4 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a5 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u30-pad3_ u30 +a6 [net-_u30-pad3_ net-_u17-pad3_ ] net-_u36-pad3_ u36 +a7 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u18-pad3_ u18 +a9 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a10 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u33-pad3_ u33 +a11 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad3_ u20 +a12 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u21-pad3_ u21 +a13 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u34-pad3_ u34 +a14 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22 +a15 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u23-pad3_ u23 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u2-pad11_ net-_u13-pad1_ u7 +a18 net-_u10-pad2_ net-_u16-pad2_ u16 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 [net-_u13-pad1_ net-_u17-pad3_ ] net-_u24-pad3_ u24 +a21 [net-_u14-pad1_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a22 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a23 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u27-pad3_ u27 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u2-pad12_ net-_u14-pad1_ u8 +a26 net-_u14-pad1_ net-_u14-pad2_ u14 +a27 net-_u2-pad13_ net-_u15-pad1_ u9 +a28 net-_u15-pad1_ net-_u15-pad2_ u15 +a29 net-_u2-pad14_ net-_u23-pad1_ u6 +a30 net-_u2-pad15_ net-_u17-pad1_ u4 +a31 net-_u2-pad16_ net-_u17-pad2_ u5 +a32 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a33 [net-_u17-pad2_ net-_u17-pad2_ ] net-_u32-pad3_ u32 +a34 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u37-pad3_ u37 +a35 [net-_u1-pad10_ ] [net-_u11-pad1_ ] u3 +a36 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ ] [net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a37 [net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ ] [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ ] u53 +a38 [net-_u42-pad1_ net-_u35-pad3_ ] net-_u42-pad3_ u42 +a39 [net-_u42-pad3_ net-_u36-pad3_ ] net-_u49-pad3_ u49 +a40 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43 +a41 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u52-pad3_ u52 +a42 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a43 [net-_u40-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u41-pad3_ u41 +a45 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a46 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u51-pad3_ u51 +a47 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u38-pad3_ u38 +a48 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u39-pad3_ u39 +a49 [net-_u38-pad3_ net-_u38-pad3_ ] net-_u44-pad3_ u44 +a50 [net-_u39-pad3_ net-_u39-pad3_ ] net-_u45-pad3_ u45 +a51 [net-_u44-pad3_ net-_u45-pad3_ ] net-_u46-pad3_ u46 +a52 [net-_u43-pad3_ net-_u43-pad3_ ] net-_u50-pad3_ u50 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u53 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u42 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u52 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54147_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml new file mode 100644 index 00000000..ecb2c383 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u11 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u11><u28 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u29><u35 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u35><u30 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u30><u36 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u36><u31 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u18 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u19><u33 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u33><u20 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u21><u34 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u34><u22 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u23><u10 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u10><u7 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u16 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u16><u13 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u13><u24 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u27><u12 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u12><u8 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u8><u14 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u14><u9 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u9><u15 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u15><u6 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u6><u4 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u5><u17 name="type">d_nor<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u17><u32 name="type">d_and<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u32><u37 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u37><u3 name="type">adc_bridge<field103 name="Enter value for in_low (default=1.0)" /><field104 name="Enter value for in_high (default=2.0)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /><field106 name="Enter Fall Delay (default=1.0e-9)" /></u3><u2 name="type">adc_bridge<field107 name="Enter value for in_low (default=1.0)" /><field108 name="Enter value for in_high (default=2.0)" /><field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /></u2><u53 name="type">dac_bridge<field111 name="Enter value for out_low (default=0.0)" /><field112 name="Enter value for out_high (default=5.0)" /><field113 name="Enter value for out_undef (default=0.5)" /><field114 name="Enter value for input load (default=1.0e-12)" /><field115 name="Enter the Rise Time (default=1.0e-9)" /><field116 name="Enter the Fall Time (default=1.0e-9)" /></u53><u42 name="type">d_nor<field117 name="Enter Rise Delay (default=1.0e-9)" /><field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /></u42><u49 name="type">d_nor<field120 name="Enter Rise Delay (default=1.0e-9)" /><field121 name="Enter Fall Delay (default=1.0e-9)" /><field122 name="Enter Input Load (default=1.0e-12)" /></u49><u43 name="type">d_nor<field123 name="Enter Rise Delay (default=1.0e-9)" /><field124 name="Enter Fall Delay (default=1.0e-9)" /><field125 name="Enter Input Load (default=1.0e-12)" /></u43><u52 name="type">d_nor<field126 name="Enter Rise Delay (default=1.0e-9)" /><field127 name="Enter Fall Delay (default=1.0e-9)" /><field128 name="Enter Input Load (default=1.0e-12)" /></u52><u40 name="type">d_nor<field129 name="Enter Rise Delay (default=1.0e-9)" /><field130 name="Enter Fall Delay (default=1.0e-9)" /><field131 name="Enter Input Load (default=1.0e-12)" /></u40><u47 name="type">d_nor<field132 name="Enter Rise Delay (default=1.0e-9)" /><field133 name="Enter Fall Delay (default=1.0e-9)" /><field134 name="Enter Input Load (default=1.0e-12)" /></u47><u41 name="type">d_nor<field135 name="Enter Rise Delay (default=1.0e-9)" /><field136 name="Enter Fall Delay (default=1.0e-9)" /><field137 name="Enter Input Load (default=1.0e-12)" /></u41><u48 name="type">d_nor<field138 name="Enter Rise Delay (default=1.0e-9)" /><field139 name="Enter Fall Delay (default=1.0e-9)" /><field140 name="Enter Input Load (default=1.0e-12)" /></u48><u51 name="type">d_nor<field141 name="Enter Rise Delay (default=1.0e-9)" /><field142 name="Enter Fall Delay (default=1.0e-9)" /><field143 name="Enter Input Load (default=1.0e-12)" /></u51><u38 name="type">d_nor<field144 name="Enter Rise Delay (default=1.0e-9)" /><field145 name="Enter Fall Delay (default=1.0e-9)" /><field146 name="Enter Input Load (default=1.0e-12)" /></u38><u39 name="type">d_nor<field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /><field149 name="Enter Input Load (default=1.0e-12)" /></u39><u44 name="type">d_nor<field150 name="Enter Rise Delay (default=1.0e-9)" /><field151 name="Enter Fall Delay (default=1.0e-9)" /><field152 name="Enter Input Load (default=1.0e-12)" /></u44><u45 name="type">d_nor<field153 name="Enter Rise Delay (default=1.0e-9)" /><field154 name="Enter Fall Delay (default=1.0e-9)" /><field155 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_nor<field156 name="Enter Rise Delay (default=1.0e-9)" /><field157 name="Enter Fall Delay (default=1.0e-9)" /><field158 name="Enter Input Load (default=1.0e-12)" /></u46><u50 name="type">d_nor<field159 name="Enter Rise Delay (default=1.0e-9)" /><field160 name="Enter Fall Delay (default=1.0e-9)" /><field161 name="Enter Input Load (default=1.0e-12)" /></u50></model><devicemodel /><subcircuit><x1><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/analysis b/library/SubcircuitLibrary/SN54147_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC-cache.lib b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC-cache.lib new file mode 100644 index 00000000..aa224b4d --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir new file mode 100644 index 00000000..1d25f385 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir @@ -0,0 +1,72 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN5442A_IC\SN5442A_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/30/24 18:49:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand +U12 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand +U31 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U31-Pad3_ d_nand +U32 Net-_U12-Pad3_ Net-_U12-Pad3_ Net-_U32-Pad3_ d_nand +U51 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U51-Pad3_ d_nand +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_nand +U14 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U14-Pad3_ d_nand +U33 Net-_U13-Pad3_ Net-_U13-Pad3_ Net-_U33-Pad3_ d_nand +U34 Net-_U14-Pad3_ Net-_U14-Pad3_ Net-_U34-Pad3_ d_nand +U52 Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U52-Pad3_ d_nand +U15 Net-_U11-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nand +U16 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_nand +U35 Net-_U15-Pad3_ Net-_U15-Pad3_ Net-_U35-Pad3_ d_nand +U36 Net-_U16-Pad3_ Net-_U16-Pad3_ Net-_U36-Pad3_ d_nand +U53 Net-_U35-Pad3_ Net-_U36-Pad3_ Net-_U53-Pad3_ d_nand +U17 Net-_U13-Pad1_ Net-_U15-Pad2_ Net-_U17-Pad3_ d_nand +U18 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U18-Pad3_ d_nand +U37 Net-_U17-Pad3_ Net-_U17-Pad3_ Net-_U37-Pad3_ d_nand +U38 Net-_U18-Pad3_ Net-_U18-Pad3_ Net-_U38-Pad3_ d_nand +U54 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U54-Pad3_ d_nand +U19 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U19-Pad3_ d_nand +U20 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_nand +U39 Net-_U19-Pad3_ Net-_U19-Pad3_ Net-_U39-Pad3_ d_nand +U40 Net-_U20-Pad3_ Net-_U20-Pad3_ Net-_U40-Pad3_ d_nand +U55 Net-_U39-Pad3_ Net-_U40-Pad3_ Net-_U55-Pad3_ d_nand +U21 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U21-Pad3_ d_nand +U22 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U22-Pad3_ d_nand +U41 Net-_U21-Pad3_ Net-_U21-Pad3_ Net-_U41-Pad3_ d_nand +U42 Net-_U22-Pad3_ Net-_U22-Pad3_ Net-_U42-Pad3_ d_nand +U56 Net-_U41-Pad3_ Net-_U42-Pad3_ Net-_U56-Pad3_ d_nand +U23 Net-_U11-Pad1_ Net-_U15-Pad2_ Net-_U23-Pad3_ d_nand +U24 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U24-Pad3_ d_nand +U43 Net-_U23-Pad3_ Net-_U23-Pad3_ Net-_U43-Pad3_ d_nand +U44 Net-_U24-Pad3_ Net-_U24-Pad3_ Net-_U44-Pad3_ d_nand +U57 Net-_U43-Pad3_ Net-_U44-Pad3_ Net-_U57-Pad3_ d_nand +U25 Net-_U13-Pad1_ Net-_U15-Pad2_ Net-_U25-Pad3_ d_nand +U26 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U26-Pad3_ d_nand +U45 Net-_U25-Pad3_ Net-_U25-Pad3_ Net-_U45-Pad3_ d_nand +U46 Net-_U26-Pad3_ Net-_U26-Pad3_ Net-_U46-Pad3_ d_nand +U58 Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U58-Pad3_ d_nand +U27 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U27-Pad3_ d_nand +U28 Net-_U10-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_nand +U47 Net-_U27-Pad3_ Net-_U27-Pad3_ Net-_U47-Pad3_ d_nand +U48 Net-_U28-Pad3_ Net-_U28-Pad3_ Net-_U48-Pad3_ d_nand +U59 Net-_U47-Pad3_ Net-_U48-Pad3_ Net-_U59-Pad3_ d_nand +U29 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U29-Pad3_ d_nand +U30 Net-_U10-Pad1_ Net-_U28-Pad2_ Net-_U30-Pad3_ d_nand +U49 Net-_U29-Pad3_ Net-_U29-Pad3_ Net-_U49-Pad3_ d_nand +U50 Net-_U30-Pad3_ Net-_U30-Pad3_ Net-_U50-Pad3_ d_nand +U60 Net-_U49-Pad3_ Net-_U50-Pad3_ Net-_U60-Pad3_ d_nand +U4 Net-_U2-Pad5_ Net-_U11-Pad1_ d_inverter +U9 Net-_U11-Pad1_ Net-_U13-Pad1_ d_inverter +U3 Net-_U2-Pad6_ Net-_U11-Pad2_ d_inverter +U7 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter +U6 Net-_U2-Pad7_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U5 Net-_U2-Pad8_ Net-_U12-Pad2_ d_inverter +U8 Net-_U12-Pad2_ Net-_U28-Pad2_ d_inverter +U62 Net-_U51-Pad3_ Net-_U52-Pad3_ Net-_U53-Pad3_ Net-_U54-Pad3_ Net-_U55-Pad3_ Net-_U56-Pad3_ Net-_U57-Pad3_ Net-_U58-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ dac_bridge_8 +U61 Net-_U59-Pad3_ Net-_U60-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad10_ dac_bridge_2 +U2 Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ adc_bridge_4 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir.out b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir.out new file mode 100644 index 00000000..014d39a6 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir.out @@ -0,0 +1,256 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn5442a_ic\sn5442a_ic.cir + +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u31 net-_u11-pad3_ net-_u11-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u12-pad3_ net-_u12-pad3_ net-_u32-pad3_ d_nand +* u51 net-_u31-pad3_ net-_u32-pad3_ net-_u51-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u10-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_nand +* u33 net-_u13-pad3_ net-_u13-pad3_ net-_u33-pad3_ d_nand +* u34 net-_u14-pad3_ net-_u14-pad3_ net-_u34-pad3_ d_nand +* u52 net-_u33-pad3_ net-_u34-pad3_ net-_u52-pad3_ d_nand +* u15 net-_u11-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u16 net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_nand +* u35 net-_u15-pad3_ net-_u15-pad3_ net-_u35-pad3_ d_nand +* u36 net-_u16-pad3_ net-_u16-pad3_ net-_u36-pad3_ d_nand +* u53 net-_u35-pad3_ net-_u36-pad3_ net-_u53-pad3_ d_nand +* u17 net-_u13-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_nand +* u18 net-_u10-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_nand +* u37 net-_u17-pad3_ net-_u17-pad3_ net-_u37-pad3_ d_nand +* u38 net-_u18-pad3_ net-_u18-pad3_ net-_u38-pad3_ d_nand +* u54 net-_u37-pad3_ net-_u38-pad3_ net-_u54-pad3_ d_nand +* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u10-pad2_ net-_u12-pad2_ net-_u20-pad3_ d_nand +* u39 net-_u19-pad3_ net-_u19-pad3_ net-_u39-pad3_ d_nand +* u40 net-_u20-pad3_ net-_u20-pad3_ net-_u40-pad3_ d_nand +* u55 net-_u39-pad3_ net-_u40-pad3_ net-_u55-pad3_ d_nand +* u21 net-_u13-pad1_ net-_u11-pad2_ net-_u21-pad3_ d_nand +* u22 net-_u10-pad2_ net-_u12-pad2_ net-_u22-pad3_ d_nand +* u41 net-_u21-pad3_ net-_u21-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u22-pad3_ net-_u22-pad3_ net-_u42-pad3_ d_nand +* u56 net-_u41-pad3_ net-_u42-pad3_ net-_u56-pad3_ d_nand +* u23 net-_u11-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_nand +* u24 net-_u10-pad2_ net-_u12-pad2_ net-_u24-pad3_ d_nand +* u43 net-_u23-pad3_ net-_u23-pad3_ net-_u43-pad3_ d_nand +* u44 net-_u24-pad3_ net-_u24-pad3_ net-_u44-pad3_ d_nand +* u57 net-_u43-pad3_ net-_u44-pad3_ net-_u57-pad3_ d_nand +* u25 net-_u13-pad1_ net-_u15-pad2_ net-_u25-pad3_ d_nand +* u26 net-_u10-pad2_ net-_u12-pad2_ net-_u26-pad3_ d_nand +* u45 net-_u25-pad3_ net-_u25-pad3_ net-_u45-pad3_ d_nand +* u46 net-_u26-pad3_ net-_u26-pad3_ net-_u46-pad3_ d_nand +* u58 net-_u45-pad3_ net-_u46-pad3_ net-_u58-pad3_ d_nand +* u27 net-_u11-pad1_ net-_u11-pad2_ net-_u27-pad3_ d_nand +* u28 net-_u10-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nand +* u47 net-_u27-pad3_ net-_u27-pad3_ net-_u47-pad3_ d_nand +* u48 net-_u28-pad3_ net-_u28-pad3_ net-_u48-pad3_ d_nand +* u59 net-_u47-pad3_ net-_u48-pad3_ net-_u59-pad3_ d_nand +* u29 net-_u13-pad1_ net-_u11-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u10-pad1_ net-_u28-pad2_ net-_u30-pad3_ d_nand +* u49 net-_u29-pad3_ net-_u29-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u30-pad3_ net-_u30-pad3_ net-_u50-pad3_ d_nand +* u60 net-_u49-pad3_ net-_u50-pad3_ net-_u60-pad3_ d_nand +* u4 net-_u2-pad5_ net-_u11-pad1_ d_inverter +* u9 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u2-pad6_ net-_u11-pad2_ d_inverter +* u7 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad7_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u2-pad8_ net-_u12-pad2_ d_inverter +* u8 net-_u12-pad2_ net-_u28-pad2_ d_inverter +* u62 net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ dac_bridge_8 +* u61 net-_u59-pad3_ net-_u60-pad3_ net-_u1-pad9_ net-_u1-pad10_ dac_bridge_2 +* u2 net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ adc_bridge_4 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a2 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a3 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u31-pad3_ u31 +a4 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u32-pad3_ u32 +a5 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u51-pad3_ u51 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u33-pad3_ u33 +a9 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u34-pad3_ u34 +a10 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u52-pad3_ u52 +a11 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a12 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a13 [net-_u15-pad3_ net-_u15-pad3_ ] net-_u35-pad3_ u35 +a14 [net-_u16-pad3_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a15 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u53-pad3_ u53 +a16 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17 +a17 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u17-pad3_ net-_u17-pad3_ ] net-_u37-pad3_ u37 +a19 [net-_u18-pad3_ net-_u18-pad3_ ] net-_u38-pad3_ u38 +a20 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u54-pad3_ u54 +a21 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a22 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a23 [net-_u19-pad3_ net-_u19-pad3_ ] net-_u39-pad3_ u39 +a24 [net-_u20-pad3_ net-_u20-pad3_ ] net-_u40-pad3_ u40 +a25 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u55-pad3_ u55 +a26 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u21-pad3_ u21 +a27 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u22-pad3_ u22 +a28 [net-_u21-pad3_ net-_u21-pad3_ ] net-_u41-pad3_ u41 +a29 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u42-pad3_ u42 +a30 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u56-pad3_ u56 +a31 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23 +a32 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u24-pad3_ u24 +a33 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u43-pad3_ u43 +a34 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u44-pad3_ u44 +a35 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u57-pad3_ u57 +a36 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u25-pad3_ u25 +a37 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u26-pad3_ u26 +a38 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u45-pad3_ u45 +a39 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u46-pad3_ u46 +a40 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u58-pad3_ u58 +a41 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u27-pad3_ u27 +a42 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a43 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u48-pad3_ u48 +a45 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u59-pad3_ u59 +a46 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u29-pad3_ u29 +a47 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u30-pad3_ u30 +a48 [net-_u29-pad3_ net-_u29-pad3_ ] net-_u49-pad3_ u49 +a49 [net-_u30-pad3_ net-_u30-pad3_ ] net-_u50-pad3_ u50 +a50 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u60-pad3_ u60 +a51 net-_u2-pad5_ net-_u11-pad1_ u4 +a52 net-_u11-pad1_ net-_u13-pad1_ u9 +a53 net-_u2-pad6_ net-_u11-pad2_ u3 +a54 net-_u11-pad2_ net-_u15-pad2_ u7 +a55 net-_u2-pad7_ net-_u10-pad1_ u6 +a56 net-_u10-pad1_ net-_u10-pad2_ u10 +a57 net-_u2-pad8_ net-_u12-pad2_ u5 +a58 net-_u12-pad2_ net-_u28-pad2_ u8 +a59 [net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ ] [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u62 +a60 [net-_u59-pad3_ net-_u60-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ ] u61 +a61 [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ ] [net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] u2 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u44 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u58 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u59 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u62 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u61 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.pro b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sch b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sch new file mode 100644 index 00000000..d1cc4d39 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sch @@ -0,0 +1,1506 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN5442A-cache +EELAYER 25 0 +EELAYER END +$Descr User 23622 27559 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U11 +U 1 1 66815193 +P 13050 4450 +F 0 "U11" H 13050 4450 60 0000 C CNN +F 1 "d_nand" H 13100 4550 60 0000 C CNN +F 2 "" H 13050 4450 60 0000 C CNN +F 3 "" H 13050 4450 60 0000 C CNN + 1 13050 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U12 +U 1 1 66815194 +P 13050 5000 +F 0 "U12" H 13050 5000 60 0000 C CNN +F 1 "d_nand" H 13100 5100 60 0000 C CNN +F 2 "" H 13050 5000 60 0000 C CNN +F 3 "" H 13050 5000 60 0000 C CNN + 1 13050 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U31 +U 1 1 66815195 +P 14200 4450 +F 0 "U31" H 14200 4450 60 0000 C CNN +F 1 "d_nand" H 14250 4550 60 0000 C CNN +F 2 "" H 14200 4450 60 0000 C CNN +F 3 "" H 14200 4450 60 0000 C CNN + 1 14200 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U32 +U 1 1 66815196 +P 14200 5000 +F 0 "U32" H 14200 5000 60 0000 C CNN +F 1 "d_nand" H 14250 5100 60 0000 C CNN +F 2 "" H 14200 5000 60 0000 C CNN +F 3 "" H 14200 5000 60 0000 C CNN + 1 14200 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U51 +U 1 1 66815197 +P 15250 4650 +F 0 "U51" H 15250 4650 60 0000 C CNN +F 1 "d_nand" H 15300 4750 60 0000 C CNN +F 2 "" H 15250 4650 60 0000 C CNN +F 3 "" H 15250 4650 60 0000 C CNN + 1 15250 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U13 +U 1 1 66815198 +P 13050 6050 +F 0 "U13" H 13050 6050 60 0000 C CNN +F 1 "d_nand" H 13100 6150 60 0000 C CNN +F 2 "" H 13050 6050 60 0000 C CNN +F 3 "" H 13050 6050 60 0000 C CNN + 1 13050 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U14 +U 1 1 66815199 +P 13050 6600 +F 0 "U14" H 13050 6600 60 0000 C CNN +F 1 "d_nand" H 13100 6700 60 0000 C CNN +F 2 "" H 13050 6600 60 0000 C CNN +F 3 "" H 13050 6600 60 0000 C CNN + 1 13050 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U33 +U 1 1 6681519A +P 14200 6050 +F 0 "U33" H 14200 6050 60 0000 C CNN +F 1 "d_nand" H 14250 6150 60 0000 C CNN +F 2 "" H 14200 6050 60 0000 C CNN +F 3 "" H 14200 6050 60 0000 C CNN + 1 14200 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U34 +U 1 1 6681519B +P 14200 6600 +F 0 "U34" H 14200 6600 60 0000 C CNN +F 1 "d_nand" H 14250 6700 60 0000 C CNN +F 2 "" H 14200 6600 60 0000 C CNN +F 3 "" H 14200 6600 60 0000 C CNN + 1 14200 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U52 +U 1 1 6681519C +P 15250 6250 +F 0 "U52" H 15250 6250 60 0000 C CNN +F 1 "d_nand" H 15300 6350 60 0000 C CNN +F 2 "" H 15250 6250 60 0000 C CNN +F 3 "" H 15250 6250 60 0000 C CNN + 1 15250 6250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U15 +U 1 1 6681519D +P 13050 7750 +F 0 "U15" H 13050 7750 60 0000 C CNN +F 1 "d_nand" H 13100 7850 60 0000 C CNN +F 2 "" H 13050 7750 60 0000 C CNN +F 3 "" H 13050 7750 60 0000 C CNN + 1 13050 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 6681519E +P 13050 8300 +F 0 "U16" H 13050 8300 60 0000 C CNN +F 1 "d_nand" H 13100 8400 60 0000 C CNN +F 2 "" H 13050 8300 60 0000 C CNN +F 3 "" H 13050 8300 60 0000 C CNN + 1 13050 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U35 +U 1 1 6681519F +P 14200 7750 +F 0 "U35" H 14200 7750 60 0000 C CNN +F 1 "d_nand" H 14250 7850 60 0000 C CNN +F 2 "" H 14200 7750 60 0000 C CNN +F 3 "" H 14200 7750 60 0000 C CNN + 1 14200 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U36 +U 1 1 668151A0 +P 14200 8300 +F 0 "U36" H 14200 8300 60 0000 C CNN +F 1 "d_nand" H 14250 8400 60 0000 C CNN +F 2 "" H 14200 8300 60 0000 C CNN +F 3 "" H 14200 8300 60 0000 C CNN + 1 14200 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U53 +U 1 1 668151A1 +P 15250 7950 +F 0 "U53" H 15250 7950 60 0000 C CNN +F 1 "d_nand" H 15300 8050 60 0000 C CNN +F 2 "" H 15250 7950 60 0000 C CNN +F 3 "" H 15250 7950 60 0000 C CNN + 1 15250 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U17 +U 1 1 668151A2 +P 13050 9250 +F 0 "U17" H 13050 9250 60 0000 C CNN +F 1 "d_nand" H 13100 9350 60 0000 C CNN +F 2 "" H 13050 9250 60 0000 C CNN +F 3 "" H 13050 9250 60 0000 C CNN + 1 13050 9250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 668151A3 +P 13050 9800 +F 0 "U18" H 13050 9800 60 0000 C CNN +F 1 "d_nand" H 13100 9900 60 0000 C CNN +F 2 "" H 13050 9800 60 0000 C CNN +F 3 "" H 13050 9800 60 0000 C CNN + 1 13050 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U37 +U 1 1 668151A4 +P 14200 9250 +F 0 "U37" H 14200 9250 60 0000 C CNN +F 1 "d_nand" H 14250 9350 60 0000 C CNN +F 2 "" H 14200 9250 60 0000 C CNN +F 3 "" H 14200 9250 60 0000 C CNN + 1 14200 9250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U38 +U 1 1 668151A5 +P 14200 9800 +F 0 "U38" H 14200 9800 60 0000 C CNN +F 1 "d_nand" H 14250 9900 60 0000 C CNN +F 2 "" H 14200 9800 60 0000 C CNN +F 3 "" H 14200 9800 60 0000 C CNN + 1 14200 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U54 +U 1 1 668151A6 +P 15250 9450 +F 0 "U54" H 15250 9450 60 0000 C CNN +F 1 "d_nand" H 15300 9550 60 0000 C CNN +F 2 "" H 15250 9450 60 0000 C CNN +F 3 "" H 15250 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Wire Line + 15700 7900 16500 7900 +Wire Wire Line + 16500 7900 16500 9550 +Wire Wire Line + 16500 9550 17150 9550 +Wire Wire Line + 17150 9650 16350 9650 +Wire Wire Line + 16350 9650 16350 9400 +Wire Wire Line + 16350 9400 15700 9400 +Wire Wire Line + 17150 9750 16300 9750 +Wire Wire Line + 16300 9750 16300 11000 +Wire Wire Line + 16300 11000 15700 11000 +Wire Wire Line + 15700 12300 16650 12300 +Wire Wire Line + 16650 12300 16650 9850 +Wire Wire Line + 16650 9850 17150 9850 +Wire Wire Line + 17150 9950 16800 9950 +Wire Wire Line + 16800 9950 16800 13550 +Wire Wire Line + 16800 13550 15700 13550 +Wire Wire Line + 17150 10050 17000 10050 +Wire Wire Line + 17000 10050 17000 15000 +Wire Wire Line + 17000 15000 15700 15000 +Wire Wire Line + 15700 16400 16400 16400 +Wire Wire Line + 16400 16400 16400 17100 +Wire Wire Line + 16400 17100 16800 17100 +Wire Wire Line + 16800 17200 16350 17200 +Wire Wire Line + 16350 17200 16350 17950 +Wire Wire Line + 16350 17950 15700 17950 +Wire Wire Line + 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+ 2 19300 9250 + -1 0 0 1 +$EndComp +Wire Wire Line + 19050 9250 18850 9250 +Wire Wire Line + 18850 9250 18850 9450 +Wire Wire Line + 18850 9450 18300 9450 +$Comp +L PORT U1 +U 3 1 66816C29 +P 19400 9450 +F 0 "U1" H 19450 9550 30 0000 C CNN +F 1 "PORT" H 19400 9450 30 0000 C CNN +F 2 "" H 19400 9450 60 0000 C CNN +F 3 "" H 19400 9450 60 0000 C CNN + 3 19400 9450 + -1 0 0 1 +$EndComp +Wire Wire Line + 19150 9450 18950 9450 +Wire Wire Line + 18950 9450 18950 9550 +Wire Wire Line + 18950 9550 18300 9550 +$Comp +L PORT U1 +U 4 1 66816E91 +P 19450 9650 +F 0 "U1" H 19500 9750 30 0000 C CNN +F 1 "PORT" H 19450 9650 30 0000 C CNN +F 2 "" H 19450 9650 60 0000 C CNN +F 3 "" H 19450 9650 60 0000 C CNN + 4 19450 9650 + -1 0 0 1 +$EndComp +Wire Wire Line + 19200 9650 18300 9650 +$Comp +L PORT U1 +U 5 1 66817110 +P 19500 9850 +F 0 "U1" H 19550 9950 30 0000 C CNN +F 1 "PORT" H 19500 9850 30 0000 C CNN +F 2 "" H 19500 9850 60 0000 C CNN +F 3 "" H 19500 9850 60 0000 C CNN + 5 19500 9850 + -1 0 0 1 +$EndComp +Wire Wire Line + 19250 9850 19100 9850 +Wire Wire Line + 19100 9850 19100 9750 +Wire Wire Line + 19100 9750 18300 9750 +$Comp +L PORT U1 +U 6 1 66817388 +P 19600 10050 +F 0 "U1" H 19650 10150 30 0000 C CNN +F 1 "PORT" H 19600 10050 30 0000 C CNN +F 2 "" H 19600 10050 60 0000 C CNN +F 3 "" H 19600 10050 60 0000 C CNN + 6 19600 10050 + -1 0 0 1 +$EndComp +Wire Wire Line + 19350 10050 18950 10050 +Wire Wire Line + 18950 10050 18950 9850 +Wire Wire Line + 18950 9850 18300 9850 +$Comp +L PORT U1 +U 7 1 66817606 +P 19650 10250 +F 0 "U1" H 19700 10350 30 0000 C CNN +F 1 "PORT" H 19650 10250 30 0000 C CNN +F 2 "" H 19650 10250 60 0000 C CNN +F 3 "" H 19650 10250 60 0000 C CNN + 7 19650 10250 + -1 0 0 1 +$EndComp +Wire Wire Line + 19400 10250 18800 10250 +Wire Wire Line + 18800 10250 18800 9950 +Wire Wire Line + 18800 9950 18300 9950 +$Comp +L PORT U1 +U 8 1 66817F42 +P 19650 10500 +F 0 "U1" H 19700 10600 30 0000 C CNN +F 1 "PORT" H 19650 10500 30 0000 C CNN +F 2 "" H 19650 10500 60 0000 C CNN +F 3 "" H 19650 10500 60 0000 C CNN + 8 19650 10500 + -1 0 0 1 +$EndComp +Wire Wire Line + 19400 10500 18600 10500 +Wire Wire Line + 18600 10500 18600 10050 +Wire Wire Line + 18600 10050 18300 10050 +$Comp +L PORT U1 +U 9 1 668190C9 +P 18400 16950 +F 0 "U1" H 18450 17050 30 0000 C CNN +F 1 "PORT" H 18400 16950 30 0000 C CNN +F 2 "" H 18400 16950 60 0000 C CNN +F 3 "" H 18400 16950 60 0000 C CNN + 9 18400 16950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6681932C +P 18400 17300 +F 0 "U1" H 18450 17400 30 0000 C CNN +F 1 "PORT" H 18400 17300 30 0000 C CNN +F 2 "" H 18400 17300 60 0000 C CNN +F 3 "" H 18400 17300 60 0000 C CNN + 10 18400 17300 + -1 0 0 1 +$EndComp +Wire Wire Line + 18150 16950 18000 16950 +Wire Wire Line + 18000 16950 18000 17100 +Wire Wire Line + 18000 17100 17800 17100 +Wire Wire Line + 17800 17200 18000 17200 +Wire Wire Line + 18000 17200 18000 17300 +Wire Wire Line + 18000 17300 18150 17300 +$Comp +L PORT U1 +U 11 1 6681AADD +P 5900 10550 +F 0 "U1" H 5950 10650 30 0000 C CNN +F 1 "PORT" H 5900 10550 30 0000 C CNN +F 2 "" H 5900 10550 60 0000 C CNN +F 3 "" H 5900 10550 60 0000 C CNN + 11 5900 10550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6681AC90 +P 5900 10350 +F 0 "U1" H 5950 10450 30 0000 C CNN +F 1 "PORT" H 5900 10350 30 0000 C CNN +F 2 "" H 5900 10350 60 0000 C CNN +F 3 "" H 5900 10350 60 0000 C CNN + 12 5900 10350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6681AD61 +P 5900 10150 +F 0 "U1" H 5950 10250 30 0000 C CNN +F 1 "PORT" H 5900 10150 30 0000 C CNN +F 2 "" H 5900 10150 60 0000 C CNN +F 3 "" H 5900 10150 60 0000 C CNN + 13 5900 10150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6681AE2E +P 5900 9950 +F 0 "U1" H 5950 10050 30 0000 C CNN +F 1 "PORT" H 5900 9950 30 0000 C CNN +F 2 "" H 5900 9950 60 0000 C CNN +F 3 "" H 5900 9950 60 0000 C CNN + 14 5900 9950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 9950 6350 9950 +Wire Wire Line + 6350 9950 6350 10000 +Wire Wire Line + 6350 10000 6450 10000 +Wire Wire Line + 6150 10150 6350 10150 +Wire Wire Line + 6350 10150 6350 10100 +Wire Wire Line + 6350 10100 6450 10100 +Wire Wire Line + 6450 10200 6350 10200 +Wire Wire Line + 6350 10200 6350 10350 +Wire Wire Line + 6350 10350 6150 10350 +Wire Wire Line + 6150 10550 6400 10550 +Wire Wire Line + 6400 10550 6400 10300 +Wire Wire Line + 6400 10300 6450 10300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sub b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sub new file mode 100644 index 00000000..98a5525d --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sub @@ -0,0 +1,250 @@ +* Subcircuit SN5442A_IC +.subckt SN5442A_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\sn5442a_ic\sn5442a_ic.cir +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u31 net-_u11-pad3_ net-_u11-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u12-pad3_ net-_u12-pad3_ net-_u32-pad3_ d_nand +* u51 net-_u31-pad3_ net-_u32-pad3_ net-_u51-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u10-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_nand +* u33 net-_u13-pad3_ net-_u13-pad3_ net-_u33-pad3_ d_nand +* u34 net-_u14-pad3_ net-_u14-pad3_ net-_u34-pad3_ d_nand +* u52 net-_u33-pad3_ net-_u34-pad3_ net-_u52-pad3_ d_nand +* u15 net-_u11-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u16 net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_nand +* u35 net-_u15-pad3_ net-_u15-pad3_ net-_u35-pad3_ d_nand +* u36 net-_u16-pad3_ net-_u16-pad3_ net-_u36-pad3_ d_nand +* u53 net-_u35-pad3_ net-_u36-pad3_ net-_u53-pad3_ d_nand +* u17 net-_u13-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_nand +* u18 net-_u10-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_nand +* u37 net-_u17-pad3_ net-_u17-pad3_ net-_u37-pad3_ d_nand +* u38 net-_u18-pad3_ net-_u18-pad3_ net-_u38-pad3_ d_nand +* u54 net-_u37-pad3_ net-_u38-pad3_ net-_u54-pad3_ d_nand +* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u10-pad2_ net-_u12-pad2_ net-_u20-pad3_ d_nand +* u39 net-_u19-pad3_ net-_u19-pad3_ net-_u39-pad3_ d_nand +* u40 net-_u20-pad3_ net-_u20-pad3_ net-_u40-pad3_ d_nand +* u55 net-_u39-pad3_ net-_u40-pad3_ net-_u55-pad3_ d_nand +* u21 net-_u13-pad1_ net-_u11-pad2_ net-_u21-pad3_ d_nand +* u22 net-_u10-pad2_ net-_u12-pad2_ net-_u22-pad3_ d_nand +* u41 net-_u21-pad3_ net-_u21-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u22-pad3_ net-_u22-pad3_ net-_u42-pad3_ d_nand +* u56 net-_u41-pad3_ net-_u42-pad3_ net-_u56-pad3_ d_nand +* u23 net-_u11-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_nand +* u24 net-_u10-pad2_ net-_u12-pad2_ net-_u24-pad3_ d_nand +* u43 net-_u23-pad3_ net-_u23-pad3_ net-_u43-pad3_ d_nand +* u44 net-_u24-pad3_ net-_u24-pad3_ net-_u44-pad3_ d_nand +* u57 net-_u43-pad3_ net-_u44-pad3_ net-_u57-pad3_ d_nand +* u25 net-_u13-pad1_ net-_u15-pad2_ net-_u25-pad3_ d_nand +* u26 net-_u10-pad2_ net-_u12-pad2_ net-_u26-pad3_ d_nand +* u45 net-_u25-pad3_ net-_u25-pad3_ net-_u45-pad3_ d_nand +* u46 net-_u26-pad3_ net-_u26-pad3_ net-_u46-pad3_ d_nand +* u58 net-_u45-pad3_ net-_u46-pad3_ net-_u58-pad3_ d_nand +* u27 net-_u11-pad1_ net-_u11-pad2_ net-_u27-pad3_ d_nand +* u28 net-_u10-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nand +* u47 net-_u27-pad3_ net-_u27-pad3_ net-_u47-pad3_ d_nand +* u48 net-_u28-pad3_ net-_u28-pad3_ net-_u48-pad3_ d_nand +* u59 net-_u47-pad3_ net-_u48-pad3_ net-_u59-pad3_ d_nand +* u29 net-_u13-pad1_ net-_u11-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u10-pad1_ net-_u28-pad2_ net-_u30-pad3_ d_nand +* u49 net-_u29-pad3_ net-_u29-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u30-pad3_ net-_u30-pad3_ net-_u50-pad3_ d_nand +* u60 net-_u49-pad3_ net-_u50-pad3_ net-_u60-pad3_ d_nand +* u4 net-_u2-pad5_ net-_u11-pad1_ d_inverter +* u9 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u2-pad6_ net-_u11-pad2_ d_inverter +* u7 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad7_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u2-pad8_ net-_u12-pad2_ d_inverter +* u8 net-_u12-pad2_ net-_u28-pad2_ d_inverter +* u62 net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ dac_bridge_8 +* u61 net-_u59-pad3_ net-_u60-pad3_ net-_u1-pad9_ net-_u1-pad10_ dac_bridge_2 +* u2 net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ adc_bridge_4 +a1 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a2 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a3 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u31-pad3_ u31 +a4 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u32-pad3_ u32 +a5 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u51-pad3_ u51 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u33-pad3_ u33 +a9 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u34-pad3_ u34 +a10 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u52-pad3_ u52 +a11 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a12 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a13 [net-_u15-pad3_ net-_u15-pad3_ ] net-_u35-pad3_ u35 +a14 [net-_u16-pad3_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a15 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u53-pad3_ u53 +a16 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17 +a17 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u17-pad3_ net-_u17-pad3_ ] net-_u37-pad3_ u37 +a19 [net-_u18-pad3_ net-_u18-pad3_ ] net-_u38-pad3_ u38 +a20 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u54-pad3_ u54 +a21 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a22 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a23 [net-_u19-pad3_ net-_u19-pad3_ ] net-_u39-pad3_ u39 +a24 [net-_u20-pad3_ net-_u20-pad3_ ] net-_u40-pad3_ u40 +a25 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u55-pad3_ u55 +a26 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u21-pad3_ u21 +a27 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u22-pad3_ u22 +a28 [net-_u21-pad3_ net-_u21-pad3_ ] net-_u41-pad3_ u41 +a29 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u42-pad3_ u42 +a30 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u56-pad3_ u56 +a31 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23 +a32 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u24-pad3_ u24 +a33 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u43-pad3_ u43 +a34 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u44-pad3_ u44 +a35 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u57-pad3_ u57 +a36 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u25-pad3_ u25 +a37 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u26-pad3_ u26 +a38 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u45-pad3_ u45 +a39 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u46-pad3_ u46 +a40 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u58-pad3_ u58 +a41 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u27-pad3_ u27 +a42 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a43 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u48-pad3_ u48 +a45 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u59-pad3_ u59 +a46 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u29-pad3_ u29 +a47 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u30-pad3_ u30 +a48 [net-_u29-pad3_ net-_u29-pad3_ ] net-_u49-pad3_ u49 +a49 [net-_u30-pad3_ net-_u30-pad3_ ] net-_u50-pad3_ u50 +a50 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u60-pad3_ u60 +a51 net-_u2-pad5_ net-_u11-pad1_ u4 +a52 net-_u11-pad1_ net-_u13-pad1_ u9 +a53 net-_u2-pad6_ net-_u11-pad2_ u3 +a54 net-_u11-pad2_ net-_u15-pad2_ u7 +a55 net-_u2-pad7_ net-_u10-pad1_ u6 +a56 net-_u10-pad1_ net-_u10-pad2_ u10 +a57 net-_u2-pad8_ net-_u12-pad2_ u5 +a58 net-_u12-pad2_ net-_u28-pad2_ u8 +a59 [net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ ] [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u62 +a60 [net-_u59-pad3_ net-_u60-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ ] u61 +a61 [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ ] [net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] u2 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u44 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u58 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u59 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u62 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u61 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN5442A_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC_Previous_Values.xml new file mode 100644 index 00000000..8c4697fb --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u11 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u12><u31 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u32><u51 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u51><u13 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u14><u33 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u34><u52 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u52><u15 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u16><u35 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u35><u36 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u36><u53 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u53><u17 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u37 name="type">d_nand<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u37><u38 name="type">d_nand<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u38><u54 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u54><u19 name="type">d_nand<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_nand<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u20><u39 name="type">d_nand<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u39><u40 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u40><u55 name="type">d_nand<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u55><u21 name="type">d_nand<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_nand<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u22><u41 name="type">d_nand<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u41><u42 name="type">d_nand<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u42><u56 name="type">d_nand<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u56><u23 name="type">d_nand<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u24><u43 name="type">d_nand<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_nand<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u44><u57 name="type">d_nand<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u57><u25 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u26><u45 name="type">d_nand<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_nand<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u46><u58 name="type">d_nand<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u58><u27 name="type">d_nand<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_nand<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u28><u47 name="type">d_nand<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u47><u48 name="type">d_nand<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u48><u59 name="type">d_nand<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u59><u29 name="type">d_nand<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u30><u49 name="type">d_nand<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u49><u50 name="type">d_nand<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u50><u60 name="type">d_nand<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u60><u4 name="type">d_inverter<field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_inverter<field154 name="Enter Rise Delay (default=1.0e-9)" /><field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /></u9><u3 name="type">d_inverter<field157 name="Enter Rise Delay (default=1.0e-9)" /><field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /></u3><u7 name="type">d_inverter<field160 name="Enter Rise Delay (default=1.0e-9)" /><field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_inverter<field163 name="Enter Rise Delay (default=1.0e-9)" /><field164 name="Enter Fall Delay (default=1.0e-9)" /><field165 name="Enter Input Load (default=1.0e-12)" /></u6><u10 name="type">d_inverter<field166 name="Enter Rise Delay (default=1.0e-9)" /><field167 name="Enter Fall Delay (default=1.0e-9)" /><field168 name="Enter Input Load (default=1.0e-12)" /></u10><u5 name="type">d_inverter<field169 name="Enter Rise Delay (default=1.0e-9)" /><field170 name="Enter Fall Delay (default=1.0e-9)" /><field171 name="Enter Input Load (default=1.0e-12)" /></u5><u8 name="type">d_inverter<field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /><field174 name="Enter Input Load (default=1.0e-12)" /></u8><u62 name="type">dac_bridge<field175 name="Enter value for out_low (default=0.0)" /><field176 name="Enter value for out_high (default=5.0)" /><field177 name="Enter value for out_undef (default=0.5)" /><field178 name="Enter value for input load (default=1.0e-12)" /><field179 name="Enter the Rise Time (default=1.0e-9)" /><field180 name="Enter the Fall Time (default=1.0e-9)" /></u62><u61 name="type">dac_bridge<field181 name="Enter value for out_low (default=0.0)" /><field182 name="Enter value for out_high (default=5.0)" /><field183 name="Enter value for out_undef (default=0.5)" /><field184 name="Enter value for input load (default=1.0e-12)" /><field185 name="Enter the Rise Time (default=1.0e-9)" /><field186 name="Enter the Fall Time (default=1.0e-9)" /></u61><u2 name="type">adc_bridge<field187 name="Enter value for in_low (default=1.0)" /><field188 name="Enter value for in_high (default=2.0)" /><field189 name="Enter Rise Delay (default=1.0e-9)" /><field190 name="Enter Fall Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN5442A_sub/analysis b/library/SubcircuitLibrary/SN5442A_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib b/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib new file mode 100644 index 00000000..9e35c4fc --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib @@ -0,0 +1,232 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_5 +# +DEF dac_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir new file mode 100644 index 00000000..4ecebc03 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir @@ -0,0 +1,69 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS148_IC\SN74LS148_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/24 23:24:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U23 Net-_U11-Pad2_ Net-_U2-Pad9_ Net-_U23-Pad3_ d_nand +U24 Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U24-Pad3_ d_nand +U25 Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U25-Pad3_ d_nand +U26 Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U26-Pad3_ d_nand +U29 Net-_U23-Pad3_ Net-_U23-Pad3_ Net-_U29-Pad3_ d_nand +U30 Net-_U24-Pad3_ Net-_U24-Pad3_ Net-_U30-Pad3_ d_nand +U31 Net-_U25-Pad3_ Net-_U25-Pad3_ Net-_U31-Pad3_ d_nand +U32 Net-_U26-Pad3_ Net-_U26-Pad3_ Net-_U32-Pad3_ d_nand +U41 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U41-Pad3_ d_nand +U42 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U42-Pad3_ d_nand +U48 Net-_U41-Pad3_ Net-_U41-Pad3_ Net-_U48-Pad3_ d_nand +U49 Net-_U42-Pad3_ Net-_U42-Pad3_ Net-_U49-Pad3_ d_nand +U50 Net-_U48-Pad3_ Net-_U49-Pad3_ Net-_U50-Pad3_ d_nand +U53 Net-_U51-Pad3_ Net-_U10-Pad2_ Net-_U52-Pad1_ d_nand +U5 Net-_U2-Pad9_ Net-_U5-Pad2_ d_inverter +X5 Net-_U5-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad1_ 5_and +X2 Net-_U4-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad2_ 4_and +X1 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U36-Pad1_ 3_and +U16 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U16-Pad3_ d_and +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U35-Pad3_ d_nor +U36 Net-_U36-Pad1_ Net-_U16-Pad3_ Net-_U36-Pad3_ d_nor +U43 Net-_U35-Pad3_ Net-_U35-Pad3_ Net-_U43-Pad3_ d_nor +U44 Net-_U36-Pad3_ Net-_U36-Pad3_ Net-_U44-Pad3_ d_nor +U47 Net-_U43-Pad3_ Net-_U44-Pad3_ Net-_U47-Pad3_ d_nor +X3 Net-_U12-Pad1_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U27-Pad1_ 4_and +X4 Net-_U4-Pad2_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U27-Pad2_ 4_and +U17 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_and +U18 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_nor +U28 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U28-Pad3_ d_nor +U37 Net-_U27-Pad3_ Net-_U27-Pad3_ Net-_U37-Pad3_ d_nor +U38 Net-_U28-Pad3_ Net-_U28-Pad3_ Net-_U38-Pad3_ d_nor +U45 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U45-Pad3_ d_nor +U19 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U19-Pad3_ d_and +U20 Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_and +U22 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and +U33 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U33-Pad3_ d_nor +U34 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U34-Pad3_ d_nor +U39 Net-_U33-Pad3_ Net-_U33-Pad3_ Net-_U39-Pad3_ d_nor +U40 Net-_U34-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_nor +U46 Net-_U39-Pad3_ Net-_U40-Pad3_ Net-_U46-Pad3_ d_nor +U3 Net-_U2-Pad10_ Net-_U12-Pad1_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U4 Net-_U2-Pad11_ Net-_U4-Pad2_ d_inverter +U6 Net-_U2-Pad12_ Net-_U13-Pad1_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U7 Net-_U2-Pad13_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U8 Net-_U2-Pad14_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U9 Net-_U2-Pad15_ Net-_U16-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U2 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U10-Pad1_ adc_bridge_8 +U11 Net-_U1-Pad9_ Net-_U11-Pad2_ adc_bridge_1 +U54 Net-_U52-Pad1_ Net-_U10-Pad2_ Net-_U52-Pad2_ d_nand +U52 Net-_U52-Pad1_ Net-_U52-Pad2_ Net-_U47-Pad3_ Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ dac_bridge_5 +U51 Net-_U50-Pad3_ Net-_U50-Pad3_ Net-_U51-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out new file mode 100644 index 00000000..05b10ddb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out @@ -0,0 +1,232 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls148_ic\sn74ls148_ic.cir + +.include 4_and.sub +.include 5_and.sub +.include 3_and.sub +* u23 net-_u11-pad2_ net-_u2-pad9_ net-_u23-pad3_ d_nand +* u24 net-_u2-pad10_ net-_u2-pad11_ net-_u24-pad3_ d_nand +* u25 net-_u2-pad12_ net-_u2-pad13_ net-_u25-pad3_ d_nand +* u26 net-_u2-pad14_ net-_u2-pad15_ net-_u26-pad3_ d_nand +* u29 net-_u23-pad3_ net-_u23-pad3_ net-_u29-pad3_ d_nand +* u30 net-_u24-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nand +* u31 net-_u25-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u26-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_nand +* u41 net-_u29-pad3_ net-_u30-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u31-pad3_ net-_u32-pad3_ net-_u42-pad3_ d_nand +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nand +* u49 net-_u42-pad3_ net-_u42-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u48-pad3_ net-_u49-pad3_ net-_u50-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad1_ d_nand +* u5 net-_u2-pad9_ net-_u5-pad2_ d_inverter +x5 net-_u5-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad1_ 5_and +x2 net-_u4-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad2_ 4_and +x1 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ net-_u36-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u10-pad2_ net-_u16-pad3_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u36 net-_u36-pad1_ net-_u16-pad3_ net-_u36-pad3_ d_nor +* u43 net-_u35-pad3_ net-_u35-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u36-pad3_ net-_u36-pad3_ net-_u44-pad3_ d_nor +* u47 net-_u43-pad3_ net-_u44-pad3_ net-_u47-pad3_ d_nor +x3 net-_u12-pad1_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad1_ 4_and +x4 net-_u4-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad2_ 4_and +* u17 net-_u15-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u18 net-_u16-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u28 net-_u17-pad3_ net-_u18-pad3_ net-_u28-pad3_ d_nor +* u37 net-_u27-pad3_ net-_u27-pad3_ net-_u37-pad3_ d_nor +* u38 net-_u28-pad3_ net-_u28-pad3_ net-_u38-pad3_ d_nor +* u45 net-_u37-pad3_ net-_u38-pad3_ net-_u45-pad3_ d_nor +* u19 net-_u13-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and +* u20 net-_u14-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u15-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u16-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u33 net-_u19-pad3_ net-_u20-pad3_ net-_u33-pad3_ d_nor +* u34 net-_u21-pad3_ net-_u22-pad3_ net-_u34-pad3_ d_nor +* u39 net-_u33-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_nor +* u40 net-_u34-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u46 net-_u39-pad3_ net-_u40-pad3_ net-_u46-pad3_ d_nor +* u3 net-_u2-pad10_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u2-pad11_ net-_u4-pad2_ d_inverter +* u6 net-_u2-pad12_ net-_u13-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u8 net-_u2-pad14_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u1-pad9_ net-_u11-pad2_ adc_bridge_1 +* u54 net-_u52-pad1_ net-_u10-pad2_ net-_u52-pad2_ d_nand +* u52 net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ dac_bridge_5 +* u51 net-_u50-pad3_ net-_u50-pad3_ net-_u51-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u11-pad2_ net-_u2-pad9_ ] net-_u23-pad3_ u23 +a2 [net-_u2-pad10_ net-_u2-pad11_ ] net-_u24-pad3_ u24 +a3 [net-_u2-pad12_ net-_u2-pad13_ ] net-_u25-pad3_ u25 +a4 [net-_u2-pad14_ net-_u2-pad15_ ] net-_u26-pad3_ u26 +a5 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u29-pad3_ u29 +a6 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a7 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32 +a9 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u41-pad3_ u41 +a10 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u42-pad3_ u42 +a11 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a12 [net-_u42-pad3_ net-_u42-pad3_ ] net-_u49-pad3_ u49 +a13 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u50-pad3_ u50 +a14 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad1_ u53 +a15 net-_u2-pad9_ net-_u5-pad2_ u5 +a16 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u36-pad1_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a19 [net-_u35-pad3_ net-_u35-pad3_ ] net-_u43-pad3_ u43 +a20 [net-_u36-pad3_ net-_u36-pad3_ ] net-_u44-pad3_ u44 +a21 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a22 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a23 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a24 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u28-pad3_ u28 +a26 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u37-pad3_ u37 +a27 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u38-pad3_ u38 +a28 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u45-pad3_ u45 +a29 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a30 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a31 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a32 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a33 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u33-pad3_ u33 +a34 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u34-pad3_ u34 +a35 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a36 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a37 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u46-pad3_ u46 +a38 net-_u2-pad10_ net-_u12-pad1_ u3 +a39 net-_u12-pad1_ net-_u12-pad2_ u12 +a40 net-_u2-pad11_ net-_u4-pad2_ u4 +a41 net-_u2-pad12_ net-_u13-pad1_ u6 +a42 net-_u13-pad1_ net-_u13-pad2_ u13 +a43 net-_u2-pad13_ net-_u14-pad1_ u7 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u2-pad14_ net-_u15-pad1_ u8 +a46 net-_u15-pad1_ net-_u15-pad2_ u15 +a47 net-_u2-pad15_ net-_u16-pad1_ u9 +a48 net-_u10-pad1_ net-_u10-pad2_ u10 +a49 [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a50 [net-_u1-pad9_ ] [net-_u11-pad2_ ] u11 +a51 [net-_u52-pad1_ net-_u10-pad2_ ] net-_u52-pad2_ u54 +a52 [net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ ] [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ ] u52 +a53 [net-_u50-pad3_ net-_u50-pad3_ ] net-_u51-pad3_ u51 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u52 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch new file mode 100644 index 00000000..f749910f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch @@ -0,0 +1,1472 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS148_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 31496 27559 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U23 +U 1 1 66771E78 +P 19050 6700 +F 0 "U23" H 19050 6700 60 0000 C CNN +F 1 "d_nand" H 19100 6800 60 0000 C CNN +F 2 "" H 19050 6700 60 0000 C CNN +F 3 "" H 19050 6700 60 0000 C CNN + 1 19050 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U24 +U 1 1 66771E79 +P 19050 7200 +F 0 "U24" H 19050 7200 60 0000 C CNN +F 1 "d_nand" H 19100 7300 60 0000 C CNN +F 2 "" H 19050 7200 60 0000 C CNN +F 3 "" H 19050 7200 60 0000 C CNN + 1 19050 7200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U25 +U 1 1 66771E7A +P 19050 7700 +F 0 "U25" H 19050 7700 60 0000 C CNN +F 1 "d_nand" H 19100 7800 60 0000 C CNN +F 2 "" H 19050 7700 60 0000 C CNN +F 3 "" H 19050 7700 60 0000 C CNN + 1 19050 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U26 +U 1 1 66771E7B +P 19050 8200 +F 0 "U26" H 19050 8200 60 0000 C CNN +F 1 "d_nand" H 19100 8300 60 0000 C CNN +F 2 "" H 19050 8200 60 0000 C CNN +F 3 "" H 19050 8200 60 0000 C CNN + 1 19050 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U29 +U 1 1 66771E7C +P 20250 6700 +F 0 "U29" H 20250 6700 60 0000 C CNN +F 1 "d_nand" H 20300 6800 60 0000 C CNN +F 2 "" H 20250 6700 60 0000 C CNN +F 3 "" H 20250 6700 60 0000 C CNN + 1 20250 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U30 +U 1 1 66771E7D +P 20250 7200 +F 0 "U30" H 20250 7200 60 0000 C CNN +F 1 "d_nand" H 20300 7300 60 0000 C CNN +F 2 "" H 20250 7200 60 0000 C CNN +F 3 "" H 20250 7200 60 0000 C CNN + 1 20250 7200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U31 +U 1 1 66771E7E +P 20250 7700 +F 0 "U31" H 20250 7700 60 0000 C CNN +F 1 "d_nand" H 20300 7800 60 0000 C CNN +F 2 "" H 20250 7700 60 0000 C CNN +F 3 "" H 20250 7700 60 0000 C CNN + 1 20250 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U32 +U 1 1 66771E7F +P 20250 8200 +F 0 "U32" H 20250 8200 60 0000 C CNN +F 1 "d_nand" H 20300 8300 60 0000 C CNN +F 2 "" H 20250 8200 60 0000 C CNN +F 3 "" H 20250 8200 60 0000 C CNN + 1 20250 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U41 +U 1 1 66771E80 +P 21350 6900 +F 0 "U41" H 21350 6900 60 0000 C CNN +F 1 "d_nand" H 21400 7000 60 0000 C CNN +F 2 "" H 21350 6900 60 0000 C CNN +F 3 "" H 21350 6900 60 0000 C CNN + 1 21350 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U42 +U 1 1 66771E81 +P 21350 7900 +F 0 "U42" H 21350 7900 60 0000 C CNN +F 1 "d_nand" H 21400 8000 60 0000 C CNN +F 2 "" H 21350 7900 60 0000 C CNN +F 3 "" H 21350 7900 60 0000 C CNN + 1 21350 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U48 +U 1 1 66771E82 +P 22450 6900 +F 0 "U48" H 22450 6900 60 0000 C CNN +F 1 "d_nand" H 22500 7000 60 0000 C CNN +F 2 "" H 22450 6900 60 0000 C CNN +F 3 "" H 22450 6900 60 0000 C CNN + 1 22450 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U49 +U 1 1 66771E83 +P 22450 7900 +F 0 "U49" H 22450 7900 60 0000 C CNN +F 1 "d_nand" H 22500 8000 60 0000 C CNN +F 2 "" H 22450 7900 60 0000 C CNN +F 3 "" H 22450 7900 60 0000 C CNN + 1 22450 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U50 +U 1 1 66771E84 +P 23450 7350 +F 0 "U50" H 23450 7350 60 0000 C CNN +F 1 "d_nand" H 23500 7450 60 0000 C CNN +F 2 "" H 23450 7350 60 0000 C CNN +F 3 "" H 23450 7350 60 0000 C CNN + 1 23450 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U53 +U 1 1 66771E85 +P 25450 7600 +F 0 "U53" H 25450 7600 60 0000 C CNN +F 1 "d_nand" H 25500 7700 60 0000 C CNN +F 2 "" H 25450 7600 60 0000 C CNN +F 3 "" H 25450 7600 60 0000 C CNN + 1 25450 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 66771E86 +P 13900 9250 +F 0 "U5" H 13900 9150 60 0000 C CNN +F 1 "d_inverter" H 13900 9400 60 0000 C CNN +F 2 "" H 13950 9200 60 0000 C CNN +F 3 "" H 13950 9200 60 0000 C CNN + 1 13900 9250 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 66771E87 +P 19000 9650 +F 0 "X5" H 19050 9550 60 0000 C CNN +F 1 "5_and" H 19100 9800 60 0000 C CNN +F 2 "" H 19000 9650 60 0000 C CNN +F 3 "" H 19000 9650 60 0000 C CNN + 1 19000 9650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 66771E88 +P 18950 10400 +F 0 "X2" H 19000 10350 60 0000 C CNN +F 1 "4_and" H 19050 10500 60 0000 C CNN +F 2 "" H 18950 10400 60 0000 C CNN +F 3 "" H 18950 10400 60 0000 C CNN + 1 18950 10400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 66771E89 +P 18900 11100 +F 0 "X1" H 19000 11050 60 0000 C CNN +F 1 "3_and" H 19050 11250 60 0000 C CNN +F 2 "" H 18900 11100 60 0000 C CNN +F 3 "" H 18900 11100 60 0000 C CNN + 1 18900 11100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 66771E8A +P 19000 11550 +F 0 "U16" H 19000 11550 60 0000 C CNN +F 1 "d_and" H 19050 11650 60 0000 C CNN +F 2 "" H 19000 11550 60 0000 C CNN +F 3 "" H 19000 11550 60 0000 C CNN + 1 19000 11550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U35 +U 1 1 66771E8B +P 20300 9850 +F 0 "U35" H 20300 9850 60 0000 C CNN +F 1 "d_nor" H 20350 9950 60 0000 C CNN +F 2 "" H 20300 9850 60 0000 C CNN +F 3 "" H 20300 9850 60 0000 C CNN + 1 20300 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U36 +U 1 1 66771E8C +P 20300 10850 +F 0 "U36" H 20300 10850 60 0000 C CNN +F 1 "d_nor" H 20350 10950 60 0000 C CNN +F 2 "" H 20300 10850 60 0000 C CNN +F 3 "" H 20300 10850 60 0000 C CNN + 1 20300 10850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U43 +U 1 1 66771E8D +P 21350 9850 +F 0 "U43" H 21350 9850 60 0000 C CNN +F 1 "d_nor" H 21400 9950 60 0000 C CNN +F 2 "" H 21350 9850 60 0000 C CNN +F 3 "" H 21350 9850 60 0000 C CNN + 1 21350 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U44 +U 1 1 66771E8E +P 21350 10850 +F 0 "U44" H 21350 10850 60 0000 C CNN +F 1 "d_nor" H 21400 10950 60 0000 C CNN +F 2 "" H 21350 10850 60 0000 C CNN +F 3 "" H 21350 10850 60 0000 C CNN + 1 21350 10850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U47 +U 1 1 66771E8F +P 22350 10350 +F 0 "U47" H 22350 10350 60 0000 C CNN +F 1 "d_nor" H 22400 10450 60 0000 C CNN +F 2 "" H 22350 10350 60 0000 C CNN +F 3 "" H 22350 10350 60 0000 C CNN + 1 22350 10350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 66771E90 +P 18950 12500 +F 0 "X3" H 19000 12450 60 0000 C CNN +F 1 "4_and" H 19050 12600 60 0000 C CNN +F 2 "" H 18950 12500 60 0000 C CNN +F 3 "" H 18950 12500 60 0000 C CNN + 1 18950 12500 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 66771E91 +P 18950 13200 +F 0 "X4" H 19000 13150 60 0000 C CNN +F 1 "4_and" H 19050 13300 60 0000 C CNN +F 2 "" H 18950 13200 60 0000 C CNN +F 3 "" H 18950 13200 60 0000 C CNN + 1 18950 13200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 66771E92 +P 19000 13750 +F 0 "U17" H 19000 13750 60 0000 C CNN +F 1 "d_and" H 19050 13850 60 0000 C CNN +F 2 "" H 19000 13750 60 0000 C CNN +F 3 "" H 19000 13750 60 0000 C CNN + 1 19000 13750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 66771E93 +P 19000 14150 +F 0 "U18" H 19000 14150 60 0000 C CNN +F 1 "d_and" H 19050 14250 60 0000 C CNN +F 2 "" H 19000 14150 60 0000 C CNN +F 3 "" H 19000 14150 60 0000 C CNN + 1 19000 14150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U27 +U 1 1 66771E94 +P 20200 12850 +F 0 "U27" H 20200 12850 60 0000 C CNN +F 1 "d_nor" H 20250 12950 60 0000 C CNN +F 2 "" H 20200 12850 60 0000 C CNN +F 3 "" H 20200 12850 60 0000 C CNN + 1 20200 12850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U28 +U 1 1 66771E95 +P 20200 13850 +F 0 "U28" H 20200 13850 60 0000 C CNN +F 1 "d_nor" H 20250 13950 60 0000 C CNN +F 2 "" H 20200 13850 60 0000 C CNN +F 3 "" H 20200 13850 60 0000 C CNN + 1 20200 13850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U37 +U 1 1 66771E96 +P 21250 12850 +F 0 "U37" H 21250 12850 60 0000 C CNN +F 1 "d_nor" H 21300 12950 60 0000 C CNN +F 2 "" H 21250 12850 60 0000 C CNN +F 3 "" H 21250 12850 60 0000 C CNN + 1 21250 12850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U38 +U 1 1 66771E97 +P 21250 13850 +F 0 "U38" H 21250 13850 60 0000 C CNN +F 1 "d_nor" H 21300 13950 60 0000 C CNN +F 2 "" H 21250 13850 60 0000 C CNN +F 3 "" H 21250 13850 60 0000 C CNN + 1 21250 13850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U45 +U 1 1 66771E98 +P 22250 13350 +F 0 "U45" H 22250 13350 60 0000 C CNN +F 1 "d_nor" H 22300 13450 60 0000 C CNN +F 2 "" H 22250 13350 60 0000 C CNN +F 3 "" H 22250 13350 60 0000 C CNN + 1 22250 13350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 66771E99 +P 19000 14850 +F 0 "U19" H 19000 14850 60 0000 C CNN +F 1 "d_and" H 19050 14950 60 0000 C CNN +F 2 "" H 19000 14850 60 0000 C CNN +F 3 "" H 19000 14850 60 0000 C CNN + 1 19000 14850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 66771E9A +P 19000 15250 +F 0 "U20" H 19000 15250 60 0000 C CNN +F 1 "d_and" H 19050 15350 60 0000 C CNN +F 2 "" H 19000 15250 60 0000 C CNN +F 3 "" H 19000 15250 60 0000 C CNN + 1 19000 15250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 66771E9B +P 19000 15650 +F 0 "U21" H 19000 15650 60 0000 C CNN +F 1 "d_and" H 19050 15750 60 0000 C CNN +F 2 "" H 19000 15650 60 0000 C CNN +F 3 "" H 19000 15650 60 0000 C CNN + 1 19000 15650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 66771E9C +P 19000 16050 +F 0 "U22" H 19000 16050 60 0000 C CNN +F 1 "d_and" H 19050 16150 60 0000 C CNN +F 2 "" H 19000 16050 60 0000 C CNN +F 3 "" H 19000 16050 60 0000 C CNN + 1 19000 16050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U33 +U 1 1 66771E9D +P 20250 15000 +F 0 "U33" H 20250 15000 60 0000 C CNN +F 1 "d_nor" H 20300 15100 60 0000 C CNN +F 2 "" H 20250 15000 60 0000 C CNN +F 3 "" H 20250 15000 60 0000 C CNN + 1 20250 15000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U34 +U 1 1 66771E9E +P 20250 16000 +F 0 "U34" H 20250 16000 60 0000 C CNN +F 1 "d_nor" H 20300 16100 60 0000 C CNN +F 2 "" H 20250 16000 60 0000 C CNN +F 3 "" H 20250 16000 60 0000 C CNN + 1 20250 16000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U39 +U 1 1 66771E9F +P 21300 15000 +F 0 "U39" H 21300 15000 60 0000 C CNN +F 1 "d_nor" H 21350 15100 60 0000 C CNN +F 2 "" H 21300 15000 60 0000 C CNN +F 3 "" H 21300 15000 60 0000 C CNN + 1 21300 15000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U40 +U 1 1 66771EA0 +P 21300 16000 +F 0 "U40" H 21300 16000 60 0000 C CNN +F 1 "d_nor" H 21350 16100 60 0000 C CNN +F 2 "" H 21300 16000 60 0000 C CNN +F 3 "" H 21300 16000 60 0000 C CNN + 1 21300 16000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U46 +U 1 1 66771EA1 +P 22300 15500 +F 0 "U46" H 22300 15500 60 0000 C CNN +F 1 "d_nor" H 22350 15600 60 0000 C CNN +F 2 "" H 22300 15500 60 0000 C CNN +F 3 "" H 22300 15500 60 0000 C CNN + 1 22300 15500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 66771EA2 +P 13850 10050 +F 0 "U3" H 13850 9950 60 0000 C CNN +F 1 "d_inverter" H 13850 10200 60 0000 C CNN +F 2 "" H 13900 10000 60 0000 C CNN +F 3 "" H 13900 10000 60 0000 C CNN + 1 13850 10050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 66771EA3 +P 14850 10050 +F 0 "U12" H 14850 9950 60 0000 C CNN +F 1 "d_inverter" H 14850 10200 60 0000 C CNN +F 2 "" H 14900 10000 60 0000 C CNN +F 3 "" H 14900 10000 60 0000 C CNN + 1 14850 10050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 66771EA4 +P 13850 11050 +F 0 "U4" H 13850 10950 60 0000 C CNN +F 1 "d_inverter" H 13850 11200 60 0000 C CNN +F 2 "" H 13900 11000 60 0000 C CNN +F 3 "" H 13900 11000 60 0000 C CNN + 1 13850 11050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 66771EA5 +P 13950 11750 +F 0 "U6" H 13950 11650 60 0000 C CNN +F 1 "d_inverter" H 13950 11900 60 0000 C CNN +F 2 "" H 14000 11700 60 0000 C CNN +F 3 "" H 14000 11700 60 0000 C CNN + 1 13950 11750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 66771EA6 +P 14950 11750 +F 0 "U13" H 14950 11650 60 0000 C CNN +F 1 "d_inverter" H 14950 11900 60 0000 C CNN +F 2 "" H 15000 11700 60 0000 C CNN +F 3 "" H 15000 11700 60 0000 C CNN + 1 14950 11750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 66771EA7 +P 13950 12650 +F 0 "U7" H 13950 12550 60 0000 C CNN +F 1 "d_inverter" H 13950 12800 60 0000 C CNN +F 2 "" H 14000 12600 60 0000 C CNN +F 3 "" H 14000 12600 60 0000 C CNN + 1 13950 12650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 66771EA8 +P 14950 12650 +F 0 "U14" H 14950 12550 60 0000 C CNN +F 1 "d_inverter" H 14950 12800 60 0000 C CNN +F 2 "" H 15000 12600 60 0000 C CNN +F 3 "" H 15000 12600 60 0000 C CNN + 1 14950 12650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 66771EA9 +P 13950 13650 +F 0 "U8" H 13950 13550 60 0000 C CNN +F 1 "d_inverter" H 13950 13800 60 0000 C CNN +F 2 "" H 14000 13600 60 0000 C CNN +F 3 "" H 14000 13600 60 0000 C CNN + 1 13950 13650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 66771EAA +P 14950 13650 +F 0 "U15" H 14950 13550 60 0000 C CNN +F 1 "d_inverter" H 14950 13800 60 0000 C CNN +F 2 "" H 15000 13600 60 0000 C CNN +F 3 "" H 15000 13600 60 0000 C CNN + 1 14950 13650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 66771EAB +P 14050 15050 +F 0 "U9" H 14050 14950 60 0000 C CNN +F 1 "d_inverter" H 14050 15200 60 0000 C CNN +F 2 "" H 14100 15000 60 0000 C CNN +F 3 "" H 14100 15000 60 0000 C CNN + 1 14050 15050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 66771EAC +P 14050 16050 +F 0 "U10" H 14050 15950 60 0000 C CNN +F 1 "d_inverter" H 14050 16200 60 0000 C CNN +F 2 "" H 14100 16000 60 0000 C CNN +F 3 "" H 14100 16000 60 0000 C CNN + 1 14050 16050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U2 +U 1 1 66771EAD +P 8000 10500 +F 0 "U2" H 8000 10500 60 0000 C CNN +F 1 "adc_bridge_8" H 8000 10650 60 0000 C CNN +F 2 "" H 8000 10500 60 0000 C CNN +F 3 "" H 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6850 10200 6850 10450 +Wire Wire Line + 6850 10450 7400 10450 +$Comp +L PORT U1 +U 2 1 66773392 +P 6250 10950 +F 0 "U1" H 6300 11050 30 0000 C CNN +F 1 "PORT" H 6250 10950 30 0000 C CNN +F 2 "" H 6250 10950 60 0000 C CNN +F 3 "" H 6250 10950 60 0000 C CNN + 2 6250 10950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 10400 6800 10400 +Wire Wire Line + 6800 10400 6800 10550 +Wire Wire Line + 6800 10550 7400 10550 +$Comp +L PORT U1 +U 3 1 667735C4 +P 6250 11150 +F 0 "U1" H 6300 11250 30 0000 C CNN +F 1 "PORT" H 6250 11150 30 0000 C CNN +F 2 "" H 6250 11150 60 0000 C CNN +F 3 "" H 6250 11150 60 0000 C CNN + 3 6250 11150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 10650 7400 10650 +$Comp +L PORT U1 +U 4 1 66773832 +P 6250 11350 +F 0 "U1" H 6300 11450 30 0000 C CNN +F 1 "PORT" H 6250 11350 30 0000 C CNN +F 2 "" H 6250 11350 60 0000 C CNN +F 3 "" H 6250 11350 60 0000 C CNN + 4 6250 11350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 10800 6850 10750 +Wire Wire Line + 6850 10750 7400 10750 +$Comp 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1 667774D7 +P 6600 10200 +F 0 "U1" H 6650 10300 30 0000 C CNN +F 1 "PORT" H 6600 10200 30 0000 C CNN +F 2 "" H 6600 10200 60 0000 C CNN +F 3 "" H 6600 10200 60 0000 C CNN + 10 6600 10200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6677758C +P 6500 10400 +F 0 "U1" H 6550 10500 30 0000 C CNN +F 1 "PORT" H 6500 10400 30 0000 C CNN +F 2 "" H 6500 10400 60 0000 C CNN +F 3 "" H 6500 10400 60 0000 C CNN + 11 6500 10400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6677763D +P 6450 10650 +F 0 "U1" H 6500 10750 30 0000 C CNN +F 1 "PORT" H 6450 10650 30 0000 C CNN +F 2 "" H 6450 10650 60 0000 C CNN +F 3 "" H 6450 10650 60 0000 C CNN + 12 6450 10650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6677815E +P 26350 11900 +F 0 "U1" H 26400 12000 30 0000 C CNN +F 1 "PORT" H 26350 11900 30 0000 C CNN +F 2 "" H 26350 11900 60 0000 C CNN +F 3 "" H 26350 11900 60 0000 C CNN + 13 26350 11900 + -1 0 0 1 +$EndComp +Wire Wire Line + 25850 11950 26100 11950 +Wire Wire Line + 26100 11950 26100 11900 +$Comp +L PORT U1 +U 14 1 667783B7 +P 26350 11650 +F 0 "U1" H 26400 11750 30 0000 C CNN +F 1 "PORT" H 26350 11650 30 0000 C CNN +F 2 "" H 26350 11650 60 0000 C CNN +F 3 "" H 26350 11650 60 0000 C CNN + 14 26350 11650 + -1 0 0 1 +$EndComp +Wire Wire Line + 26100 11650 25950 11650 +Wire Wire Line + 25950 11650 25950 11850 +Wire Wire Line + 25950 11850 25850 11850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub new file mode 100644 index 00000000..777e7e3f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub @@ -0,0 +1,226 @@ +* Subcircuit SN74LS148_IC +.subckt SN74LS148_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls148_ic\sn74ls148_ic.cir +.include 4_and.sub +.include 5_and.sub +.include 3_and.sub +* u23 net-_u11-pad2_ net-_u2-pad9_ net-_u23-pad3_ d_nand +* u24 net-_u2-pad10_ net-_u2-pad11_ net-_u24-pad3_ d_nand +* u25 net-_u2-pad12_ net-_u2-pad13_ net-_u25-pad3_ d_nand +* u26 net-_u2-pad14_ net-_u2-pad15_ net-_u26-pad3_ d_nand +* u29 net-_u23-pad3_ net-_u23-pad3_ net-_u29-pad3_ d_nand +* u30 net-_u24-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nand +* u31 net-_u25-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u26-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_nand +* u41 net-_u29-pad3_ net-_u30-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u31-pad3_ net-_u32-pad3_ net-_u42-pad3_ d_nand +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nand +* u49 net-_u42-pad3_ net-_u42-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u48-pad3_ net-_u49-pad3_ net-_u50-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad1_ d_nand +* u5 net-_u2-pad9_ net-_u5-pad2_ d_inverter +x5 net-_u5-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad1_ 5_and +x2 net-_u4-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad2_ 4_and +x1 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ net-_u36-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u10-pad2_ net-_u16-pad3_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u36 net-_u36-pad1_ net-_u16-pad3_ net-_u36-pad3_ d_nor +* u43 net-_u35-pad3_ net-_u35-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u36-pad3_ net-_u36-pad3_ net-_u44-pad3_ d_nor +* u47 net-_u43-pad3_ net-_u44-pad3_ net-_u47-pad3_ d_nor +x3 net-_u12-pad1_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad1_ 4_and +x4 net-_u4-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad2_ 4_and +* u17 net-_u15-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u18 net-_u16-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u28 net-_u17-pad3_ net-_u18-pad3_ net-_u28-pad3_ d_nor +* u37 net-_u27-pad3_ net-_u27-pad3_ net-_u37-pad3_ d_nor +* u38 net-_u28-pad3_ net-_u28-pad3_ net-_u38-pad3_ d_nor +* u45 net-_u37-pad3_ net-_u38-pad3_ net-_u45-pad3_ d_nor +* u19 net-_u13-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and +* u20 net-_u14-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u15-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u16-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u33 net-_u19-pad3_ net-_u20-pad3_ net-_u33-pad3_ d_nor +* u34 net-_u21-pad3_ net-_u22-pad3_ net-_u34-pad3_ d_nor +* u39 net-_u33-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_nor +* u40 net-_u34-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u46 net-_u39-pad3_ net-_u40-pad3_ net-_u46-pad3_ d_nor +* u3 net-_u2-pad10_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u2-pad11_ net-_u4-pad2_ d_inverter +* u6 net-_u2-pad12_ net-_u13-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u8 net-_u2-pad14_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u1-pad9_ net-_u11-pad2_ adc_bridge_1 +* u54 net-_u52-pad1_ net-_u10-pad2_ net-_u52-pad2_ d_nand +* u52 net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ dac_bridge_5 +* u51 net-_u50-pad3_ net-_u50-pad3_ net-_u51-pad3_ d_nand +a1 [net-_u11-pad2_ net-_u2-pad9_ ] net-_u23-pad3_ u23 +a2 [net-_u2-pad10_ net-_u2-pad11_ ] net-_u24-pad3_ u24 +a3 [net-_u2-pad12_ net-_u2-pad13_ ] net-_u25-pad3_ u25 +a4 [net-_u2-pad14_ net-_u2-pad15_ ] net-_u26-pad3_ u26 +a5 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u29-pad3_ u29 +a6 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a7 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32 +a9 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u41-pad3_ u41 +a10 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u42-pad3_ u42 +a11 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a12 [net-_u42-pad3_ net-_u42-pad3_ ] net-_u49-pad3_ u49 +a13 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u50-pad3_ u50 +a14 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad1_ u53 +a15 net-_u2-pad9_ net-_u5-pad2_ u5 +a16 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u36-pad1_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a19 [net-_u35-pad3_ net-_u35-pad3_ ] net-_u43-pad3_ u43 +a20 [net-_u36-pad3_ net-_u36-pad3_ ] net-_u44-pad3_ u44 +a21 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a22 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a23 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a24 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u28-pad3_ u28 +a26 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u37-pad3_ u37 +a27 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u38-pad3_ u38 +a28 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u45-pad3_ u45 +a29 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a30 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a31 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a32 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a33 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u33-pad3_ u33 +a34 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u34-pad3_ u34 +a35 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a36 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a37 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u46-pad3_ u46 +a38 net-_u2-pad10_ net-_u12-pad1_ u3 +a39 net-_u12-pad1_ net-_u12-pad2_ u12 +a40 net-_u2-pad11_ net-_u4-pad2_ u4 +a41 net-_u2-pad12_ net-_u13-pad1_ u6 +a42 net-_u13-pad1_ net-_u13-pad2_ u13 +a43 net-_u2-pad13_ net-_u14-pad1_ u7 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u2-pad14_ net-_u15-pad1_ u8 +a46 net-_u15-pad1_ net-_u15-pad2_ u15 +a47 net-_u2-pad15_ net-_u16-pad1_ u9 +a48 net-_u10-pad1_ net-_u10-pad2_ u10 +a49 [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a50 [net-_u1-pad9_ ] [net-_u11-pad2_ ] u11 +a51 [net-_u52-pad1_ net-_u10-pad2_ ] net-_u52-pad2_ u54 +a52 [net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ ] [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ ] u52 +a53 [net-_u50-pad3_ net-_u50-pad3_ ] net-_u51-pad3_ u51 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u52 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS148_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml new file mode 100644 index 00000000..6d21696c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u23 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u26><u29 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u32><u41 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u41><u42 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u42><u48 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u48><u49 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u49><u50 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u50><u53 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u53><u5 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u5><u16 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u16><u35 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u35><u36 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u36><u43 name="type">d_nor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_nor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u44><u47 name="type">d_nor<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u47><u17 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u18><u27 name="type">d_nor<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_nor<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u28><u37 name="type">d_nor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u37><u38 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u38><u45 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u45><u19 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u22><u33 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u34><u39 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u39><u40 name="type">d_nor<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u40><u46 name="type">d_nor<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u46><u3 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u12><u4 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u6><u13 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u13><u7 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u7><u14 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u14><u8 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u8><u15 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u15><u9 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u10><u2 name="type">adc_bridge<field145 name="Enter value for in_low (default=1.0)" /><field146 name="Enter value for in_high (default=2.0)" /><field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /></u2><u11 name="type">adc_bridge<field149 name="Enter value for in_low (default=1.0)" /><field150 name="Enter value for in_high (default=2.0)" /><field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /></u11><u54 name="type">d_nand<field153 name="Enter Rise Delay (default=1.0e-9)" /><field154 name="Enter Fall Delay (default=1.0e-9)" /><field155 name="Enter Input Load (default=1.0e-12)" /></u54><u52 name="type">dac_bridge<field156 name="Enter value for out_low (default=0.0)" /><field157 name="Enter value for out_high (default=5.0)" /><field158 name="Enter value for out_undef (default=0.5)" /><field159 name="Enter value for input load (default=1.0e-12)" /><field160 name="Enter the Rise Time (default=1.0e-9)" /><field161 name="Enter the Fall Time (default=1.0e-9)" /></u52><u51 name="type">d_nand<field162 name="Enter Rise Delay (default=1.0e-9)" /><field163 name="Enter Fall Delay (default=1.0e-9)" /><field164 name="Enter Input Load (default=1.0e-12)" /></u51></model><devicemodel /><subcircuit><x5><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x2><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x1><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x3><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/analysis b/library/SubcircuitLibrary/SN74LS148_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL064_sub/NPN.lib b/library/SubcircuitLibrary/TL064_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TL064_sub/PJF.lib b/library/SubcircuitLibrary/TL064_sub/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/library/SubcircuitLibrary/TL064_sub/PNP.lib b/library/SubcircuitLibrary/TL064_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC-cache.lib b/library/SubcircuitLibrary/TL064_sub/TL064_IC-cache.lib new file mode 100644 index 00000000..48972885 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PJF +# +DEF eSim_PJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_PJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_p +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 -45 0 -5 15 -5 -15 -45 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir new file mode 100644 index 00000000..9251e8d5 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir @@ -0,0 +1,175 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\TL064_IC\TL064_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 19:04:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q4 Net-_Q2-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q15 Net-_Q14-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q17 Net-_Q14-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q3 Net-_J1-Pad1_ Net-_Q3-Pad2_ Net-_Q2-Pad1_ eSim_PNP +J2 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_p +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_p +J5 Net-_J1-Pad1_ Net-_J5-Pad2_ Net-_C1-Pad2_ jfet_p +J6 Net-_J1-Pad1_ Net-_J5-Pad2_ Net-_C1-Pad2_ jfet_p +Q1 Net-_J1-Pad3_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN +Q6 Net-_C1-Pad2_ Net-_J1-Pad3_ Net-_Q6-Pad3_ eSim_NPN +R3 Net-_Q1-Pad3_ Net-_Q10-Pad3_ 34 +R5 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 35 +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad1_ Net-_Q14-Pad3_ eSim_NPN +R9 Net-_Q14-Pad1_ Net-_Q19-Pad1_ 220 +R8 Net-_Q14-Pad3_ Net-_C1-Pad1_ 45k +Q13 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN +Q16 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN +Q19 Net-_Q19-Pad1_ Net-_Q14-Pad3_ Net-_C1-Pad1_ eSim_NPN +Q10 Net-_C1-Pad2_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +R7 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 7 +Q26 Net-_Q15-Pad3_ Net-_Q19-Pad1_ Net-_Q25-Pad2_ eSim_NPN +Q29 Net-_Q15-Pad3_ Net-_Q19-Pad1_ Net-_Q25-Pad2_ eSim_NPN +R15 Net-_Q25-Pad2_ Net-_Q28-Pad3_ 270 +Q28 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q28-Pad3_ eSim_PNP +Q30 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q28-Pad3_ eSim_PNP +R16 Net-_Q25-Pad3_ Net-_Q25-Pad2_ 64 +Q25 Net-_Q19-Pad1_ Net-_Q25-Pad2_ Net-_Q25-Pad3_ eSim_NPN +Q39 Net-_J11-Pad2_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q38 Net-_J9-Pad1_ Net-_J11-Pad1_ Net-_J11-Pad2_ eSim_PNP +Q41 Net-_J11-Pad1_ Net-_J11-Pad1_ Net-_J11-Pad2_ eSim_PNP +J9 Net-_J9-Pad1_ Net-_J11-Pad1_ Net-_J11-Pad3_ jfet_p +J11 Net-_J11-Pad1_ Net-_J11-Pad2_ Net-_J11-Pad3_ jfet_p +Q40 Net-_J11-Pad1_ Net-_Q35-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q42 Net-_J11-Pad1_ Net-_Q35-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q36 Net-_J11-Pad1_ Net-_Q35-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R19 Net-_J11-Pad3_ Net-_Q35-Pad1_ 3.5k +Q35 Net-_Q35-Pad1_ Net-_J11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q49 Net-_Q15-Pad2_ Net-_Q15-Pad2_ Net-_Q3-Pad2_ eSim_NPN +Q50 Net-_Q10-Pad3_ Net-_J11-Pad2_ Net-_Q3-Pad2_ eSim_PNP +Q7 Net-_Q7-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q9 Net-_Q7-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q21 Net-_Q20-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q23 Net-_Q20-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q8 Net-_J3-Pad1_ Net-_Q51-Pad3_ Net-_Q7-Pad1_ eSim_PNP +J4 Net-_J3-Pad1_ Net-_J3-Pad2_ Net-_J3-Pad3_ jfet_p +J3 Net-_J3-Pad1_ Net-_J3-Pad2_ Net-_J3-Pad3_ jfet_p +J7 Net-_J3-Pad1_ Net-_J7-Pad2_ Net-_C2-Pad2_ jfet_p +J8 Net-_J3-Pad1_ Net-_J7-Pad2_ Net-_C2-Pad2_ jfet_p +Q5 Net-_J3-Pad3_ Net-_J3-Pad3_ Net-_Q5-Pad3_ eSim_NPN +Q11 Net-_C2-Pad2_ Net-_J3-Pad3_ Net-_Q11-Pad3_ eSim_NPN +R4 Net-_Q5-Pad3_ Net-_Q10-Pad3_ 34 +R6 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 35 +Q20 Net-_Q20-Pad1_ Net-_Q20-Pad1_ Net-_Q20-Pad3_ eSim_NPN +R12 Net-_Q20-Pad1_ Net-_Q24-Pad1_ 220 +R11 Net-_Q20-Pad3_ Net-_C2-Pad1_ 45k +Q18 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q12-Pad2_ eSim_NPN +Q22 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q12-Pad2_ eSim_NPN +Q24 Net-_Q24-Pad1_ Net-_Q20-Pad3_ Net-_C2-Pad1_ eSim_NPN +Q12 Net-_C2-Pad2_ Net-_Q12-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10p +R10 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 7 +Q31 Net-_Q15-Pad3_ Net-_Q24-Pad1_ Net-_Q27-Pad2_ eSim_NPN +Q33 Net-_Q15-Pad3_ Net-_Q24-Pad1_ Net-_Q27-Pad2_ eSim_NPN +R17 Net-_Q27-Pad2_ Net-_Q32-Pad3_ 270 +Q32 Net-_Q10-Pad3_ Net-_C2-Pad1_ Net-_Q32-Pad3_ eSim_PNP +Q34 Net-_Q10-Pad3_ Net-_C2-Pad1_ Net-_Q32-Pad3_ eSim_PNP +R18 Net-_Q27-Pad3_ Net-_Q27-Pad2_ 64 +Q27 Net-_Q24-Pad1_ Net-_Q27-Pad2_ Net-_Q27-Pad3_ eSim_NPN +Q45 Net-_J12-Pad2_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q44 Net-_J10-Pad1_ Net-_J10-Pad2_ Net-_J12-Pad2_ eSim_PNP +Q47 Net-_J10-Pad2_ Net-_J10-Pad2_ Net-_J12-Pad2_ eSim_PNP +J10 Net-_J10-Pad1_ Net-_J10-Pad2_ Net-_J10-Pad3_ jfet_p +J12 Net-_J10-Pad2_ Net-_J12-Pad2_ Net-_J10-Pad3_ jfet_p +Q46 Net-_J10-Pad2_ Net-_Q37-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q48 Net-_J10-Pad2_ Net-_Q37-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q43 Net-_J10-Pad2_ Net-_Q37-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R20 Net-_J10-Pad3_ Net-_Q37-Pad1_ 3.5k +Q37 Net-_Q37-Pad1_ Net-_J10-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q51 Net-_Q21-Pad2_ Net-_Q21-Pad2_ Net-_Q51-Pad3_ eSim_NPN +Q52 Net-_Q10-Pad3_ Net-_J12-Pad2_ Net-_Q51-Pad3_ eSim_PNP +U1 Net-_Q25-Pad3_ Net-_J1-Pad2_ Net-_J5-Pad2_ Net-_Q15-Pad3_ Net-_J7-Pad2_ Net-_J3-Pad2_ Net-_Q27-Pad3_ Net-_Q80-Pad3_ Net-_J15-Pad2_ Net-_J19-Pad2_ Net-_Q10-Pad3_ Net-_J16-Pad2_ Net-_J13-Pad2_ Net-_Q77-Pad3_ PORT +Q54 Net-_Q54-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q56 Net-_Q54-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q67 Net-_Q66-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q69 Net-_Q66-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q55 Net-_J13-Pad1_ Net-_Q101-Pad3_ Net-_Q54-Pad1_ eSim_PNP +J14 Net-_J13-Pad1_ Net-_J13-Pad2_ Net-_J13-Pad3_ jfet_p +J13 Net-_J13-Pad1_ Net-_J13-Pad2_ Net-_J13-Pad3_ jfet_p +J16 Net-_J13-Pad1_ Net-_J16-Pad2_ Net-_C3-Pad2_ jfet_p +J18 Net-_J13-Pad1_ Net-_J16-Pad2_ Net-_C3-Pad2_ jfet_p +Q53 Net-_J13-Pad3_ Net-_J13-Pad3_ Net-_Q53-Pad3_ eSim_NPN +Q58 Net-_C3-Pad2_ Net-_J13-Pad3_ Net-_Q58-Pad3_ eSim_NPN +R23 Net-_Q53-Pad3_ Net-_Q10-Pad3_ 34 +R25 Net-_Q58-Pad3_ Net-_Q10-Pad3_ 35 +Q66 Net-_Q66-Pad1_ Net-_Q66-Pad1_ Net-_Q66-Pad3_ eSim_NPN +R29 Net-_Q66-Pad1_ Net-_Q70-Pad1_ 220 +R28 Net-_Q66-Pad3_ Net-_C3-Pad1_ 45k +Q65 Net-_C3-Pad1_ Net-_C3-Pad2_ Net-_Q62-Pad2_ eSim_NPN +Q68 Net-_C3-Pad1_ Net-_C3-Pad2_ Net-_Q62-Pad2_ eSim_NPN +Q70 Net-_Q70-Pad1_ Net-_Q66-Pad3_ Net-_C3-Pad1_ eSim_NPN +Q62 Net-_C3-Pad2_ Net-_Q62-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10p +R27 Net-_Q62-Pad2_ Net-_Q10-Pad3_ 7 +Q78 Net-_Q15-Pad3_ Net-_Q70-Pad1_ Net-_Q77-Pad2_ eSim_NPN +Q81 Net-_Q15-Pad3_ Net-_Q70-Pad1_ Net-_Q77-Pad2_ eSim_NPN +R34 Net-_Q77-Pad2_ Net-_Q79-Pad3_ 270 +Q79 Net-_Q10-Pad3_ Net-_C3-Pad1_ Net-_Q79-Pad3_ eSim_PNP +Q82 Net-_Q10-Pad3_ Net-_C3-Pad1_ Net-_Q79-Pad3_ eSim_PNP +R36 Net-_Q77-Pad3_ Net-_Q77-Pad2_ 64 +Q77 Net-_Q70-Pad1_ Net-_Q77-Pad2_ Net-_Q77-Pad3_ eSim_NPN +Q91 Net-_J23-Pad2_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q89 Net-_J21-Pad1_ Net-_J21-Pad2_ Net-_J23-Pad2_ eSim_PNP +Q93 Net-_J21-Pad2_ Net-_J21-Pad2_ Net-_J23-Pad2_ eSim_PNP +J21 Net-_J21-Pad1_ Net-_J21-Pad2_ Net-_J21-Pad3_ jfet_p +J23 Net-_J21-Pad2_ Net-_J23-Pad2_ Net-_J21-Pad3_ jfet_p +Q92 Net-_J21-Pad2_ Net-_Q87-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q94 Net-_J21-Pad2_ Net-_Q87-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q88 Net-_J21-Pad2_ Net-_Q87-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R39 Net-_J21-Pad3_ Net-_Q87-Pad1_ 3.5k +Q87 Net-_Q87-Pad1_ Net-_J21-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q101 Net-_Q101-Pad1_ Net-_Q101-Pad1_ Net-_Q101-Pad3_ eSim_NPN +Q102 Net-_Q10-Pad3_ Net-_J23-Pad2_ Net-_Q101-Pad3_ eSim_PNP +Q59 Net-_Q59-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q61 Net-_Q59-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q73 Net-_Q72-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q75 Net-_Q72-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q60 Net-_J15-Pad1_ Net-_Q103-Pad3_ Net-_Q59-Pad1_ eSim_PNP +J17 Net-_J15-Pad1_ Net-_J15-Pad2_ Net-_J15-Pad3_ jfet_p +J15 Net-_J15-Pad1_ Net-_J15-Pad2_ Net-_J15-Pad3_ jfet_p +J19 Net-_J15-Pad1_ Net-_J19-Pad2_ Net-_C4-Pad2_ jfet_p +J20 Net-_J15-Pad1_ Net-_J19-Pad2_ Net-_C4-Pad2_ jfet_p +Q57 Net-_J15-Pad3_ Net-_J15-Pad3_ Net-_Q57-Pad3_ eSim_NPN +Q63 Net-_C4-Pad2_ Net-_J15-Pad3_ Net-_Q63-Pad3_ eSim_NPN +R24 Net-_Q57-Pad3_ Net-_Q10-Pad3_ 34 +R26 Net-_Q63-Pad3_ Net-_Q10-Pad3_ 35 +Q72 Net-_Q72-Pad1_ Net-_Q72-Pad1_ Net-_Q72-Pad3_ eSim_NPN +R32 Net-_Q72-Pad1_ Net-_Q76-Pad1_ 220 +R31 Net-_Q72-Pad3_ Net-_C4-Pad1_ 45k +Q71 Net-_C4-Pad1_ Net-_C4-Pad2_ Net-_Q64-Pad2_ eSim_NPN +Q74 Net-_C4-Pad1_ Net-_C4-Pad2_ Net-_Q64-Pad2_ eSim_NPN +Q76 Net-_Q76-Pad1_ Net-_Q72-Pad3_ Net-_C4-Pad1_ eSim_NPN +Q64 Net-_C4-Pad2_ Net-_Q64-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 10p +R30 Net-_Q64-Pad2_ Net-_Q10-Pad3_ 7 +Q83 Net-_Q15-Pad3_ Net-_Q76-Pad1_ Net-_Q80-Pad2_ eSim_NPN +Q85 Net-_Q15-Pad3_ Net-_Q76-Pad1_ Net-_Q80-Pad2_ eSim_NPN +R37 Net-_Q80-Pad2_ Net-_Q84-Pad3_ 270 +Q84 Net-_Q10-Pad3_ Net-_C4-Pad1_ Net-_Q84-Pad3_ eSim_PNP +Q86 Net-_Q10-Pad3_ Net-_C4-Pad1_ Net-_Q84-Pad3_ eSim_PNP +R38 Net-_Q80-Pad3_ Net-_Q80-Pad2_ 64 +Q80 Net-_Q76-Pad1_ Net-_Q80-Pad2_ Net-_Q80-Pad3_ eSim_NPN +Q97 Net-_J24-Pad2_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q96 Net-_J22-Pad1_ Net-_J22-Pad2_ Net-_J24-Pad2_ eSim_PNP +Q99 Net-_J22-Pad2_ Net-_J22-Pad2_ Net-_J24-Pad2_ eSim_PNP +J22 Net-_J22-Pad1_ Net-_J22-Pad2_ Net-_J22-Pad3_ jfet_p +J24 Net-_J22-Pad2_ Net-_J24-Pad2_ Net-_J22-Pad3_ jfet_p +Q98 Net-_J22-Pad2_ Net-_Q100-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q100 Net-_J22-Pad2_ Net-_Q100-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q95 Net-_J22-Pad2_ Net-_Q100-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R40 Net-_J22-Pad3_ Net-_Q100-Pad2_ 3.5k +Q90 Net-_Q100-Pad2_ Net-_J22-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q103 Net-_Q103-Pad1_ Net-_Q103-Pad1_ Net-_Q103-Pad3_ eSim_NPN +Q104 Net-_Q10-Pad3_ Net-_J24-Pad2_ Net-_Q103-Pad3_ eSim_PNP + +.end diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir.out b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir.out new file mode 100644 index 00000000..6787b7e5 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir.out @@ -0,0 +1,179 @@ +* d:\fossee\esim\library\subcircuitlibrary\tl064_ic\tl064_ic.cir + +.include PJF.lib +.include NPN.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q4 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q17 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q3 net-_j1-pad1_ net-_q3-pad2_ net-_q2-pad1_ Q2N2907A +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j5 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +j6 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +q1 net-_j1-pad3_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_j1-pad3_ net-_q6-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q10-pad3_ 34 +r5 net-_q6-pad3_ net-_q10-pad3_ 35 +q14 net-_q14-pad1_ net-_q14-pad1_ net-_q14-pad3_ Q2N2222 +r9 net-_q14-pad1_ net-_q19-pad1_ 220 +r8 net-_q14-pad3_ net-_c1-pad1_ 45k +q13 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q16 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q19 net-_q19-pad1_ net-_q14-pad3_ net-_c1-pad1_ Q2N2222 +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +r7 net-_q10-pad2_ net-_q10-pad3_ 7 +q26 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +q29 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +r15 net-_q25-pad2_ net-_q28-pad3_ 270 +q28 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +q30 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +r16 net-_q25-pad3_ net-_q25-pad2_ 64 +q25 net-_q19-pad1_ net-_q25-pad2_ net-_q25-pad3_ Q2N2222 +q39 net-_j11-pad2_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q38 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +q41 net-_j11-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +j9 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad3_ J2N3820 +j11 net-_j11-pad1_ net-_j11-pad2_ net-_j11-pad3_ J2N3820 +q40 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q42 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q36 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +r19 net-_j11-pad3_ net-_q35-pad1_ 3.5k +q35 net-_q35-pad1_ net-_j11-pad3_ net-_q10-pad3_ Q2N2222 +q49 net-_q15-pad2_ net-_q15-pad2_ net-_q3-pad2_ Q2N2222 +q50 net-_q10-pad3_ net-_j11-pad2_ net-_q3-pad2_ Q2N2907A +q7 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q9 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q21 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q23 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q8 net-_j3-pad1_ net-_q51-pad3_ net-_q7-pad1_ Q2N2907A +j4 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j3 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j7 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +j8 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +q5 net-_j3-pad3_ net-_j3-pad3_ net-_q5-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_j3-pad3_ net-_q11-pad3_ Q2N2222 +r4 net-_q5-pad3_ net-_q10-pad3_ 34 +r6 net-_q11-pad3_ net-_q10-pad3_ 35 +q20 net-_q20-pad1_ net-_q20-pad1_ net-_q20-pad3_ Q2N2222 +r12 net-_q20-pad1_ net-_q24-pad1_ 220 +r11 net-_q20-pad3_ net-_c2-pad1_ 45k +q18 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q22 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q24 net-_q24-pad1_ net-_q20-pad3_ net-_c2-pad1_ Q2N2222 +q12 net-_c2-pad2_ net-_q12-pad2_ net-_q10-pad3_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +r10 net-_q12-pad2_ net-_q10-pad3_ 7 +q31 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +q33 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +r17 net-_q27-pad2_ net-_q32-pad3_ 270 +q32 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +q34 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +r18 net-_q27-pad3_ net-_q27-pad2_ 64 +q27 net-_q24-pad1_ net-_q27-pad2_ net-_q27-pad3_ Q2N2222 +q45 net-_j12-pad2_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q44 net-_j10-pad1_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +q47 net-_j10-pad2_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +j10 net-_j10-pad1_ net-_j10-pad2_ net-_j10-pad3_ J2N3820 +j12 net-_j10-pad2_ net-_j12-pad2_ net-_j10-pad3_ J2N3820 +q46 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q48 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q43 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +r20 net-_j10-pad3_ net-_q37-pad1_ 3.5k +q37 net-_q37-pad1_ net-_j10-pad3_ net-_q10-pad3_ Q2N2222 +q51 net-_q21-pad2_ net-_q21-pad2_ net-_q51-pad3_ Q2N2222 +q52 net-_q10-pad3_ net-_j12-pad2_ net-_q51-pad3_ Q2N2907A +* u1 net-_q25-pad3_ net-_j1-pad2_ net-_j5-pad2_ net-_q15-pad3_ net-_j7-pad2_ net-_j3-pad2_ net-_q27-pad3_ net-_q80-pad3_ net-_j15-pad2_ net-_j19-pad2_ net-_q10-pad3_ net-_j16-pad2_ net-_j13-pad2_ net-_q77-pad3_ port +q54 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q56 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q67 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q69 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q55 net-_j13-pad1_ net-_q101-pad3_ net-_q54-pad1_ Q2N2907A +j14 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j13 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j16 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +j18 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +q53 net-_j13-pad3_ net-_j13-pad3_ net-_q53-pad3_ Q2N2222 +q58 net-_c3-pad2_ net-_j13-pad3_ net-_q58-pad3_ Q2N2222 +r23 net-_q53-pad3_ net-_q10-pad3_ 34 +r25 net-_q58-pad3_ net-_q10-pad3_ 35 +q66 net-_q66-pad1_ net-_q66-pad1_ net-_q66-pad3_ Q2N2222 +r29 net-_q66-pad1_ net-_q70-pad1_ 220 +r28 net-_q66-pad3_ net-_c3-pad1_ 45k +q65 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q68 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q70 net-_q70-pad1_ net-_q66-pad3_ net-_c3-pad1_ Q2N2222 +q62 net-_c3-pad2_ net-_q62-pad2_ net-_q10-pad3_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +r27 net-_q62-pad2_ net-_q10-pad3_ 7 +q78 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +q81 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +r34 net-_q77-pad2_ net-_q79-pad3_ 270 +q79 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +q82 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +r36 net-_q77-pad3_ net-_q77-pad2_ 64 +q77 net-_q70-pad1_ net-_q77-pad2_ net-_q77-pad3_ Q2N2222 +q91 net-_j23-pad2_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q89 net-_j21-pad1_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +q93 net-_j21-pad2_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +j21 net-_j21-pad1_ net-_j21-pad2_ net-_j21-pad3_ J2N3820 +j23 net-_j21-pad2_ net-_j23-pad2_ net-_j21-pad3_ J2N3820 +q92 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q94 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q88 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +r39 net-_j21-pad3_ net-_q87-pad1_ 3.5k +q87 net-_q87-pad1_ net-_j21-pad3_ net-_q10-pad3_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad1_ net-_q101-pad3_ Q2N2222 +q102 net-_q10-pad3_ net-_j23-pad2_ net-_q101-pad3_ Q2N2907A +q59 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q61 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q73 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q75 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q60 net-_j15-pad1_ net-_q103-pad3_ net-_q59-pad1_ Q2N2907A +j17 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j15 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j19 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +j20 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +q57 net-_j15-pad3_ net-_j15-pad3_ net-_q57-pad3_ Q2N2222 +q63 net-_c4-pad2_ net-_j15-pad3_ net-_q63-pad3_ Q2N2222 +r24 net-_q57-pad3_ net-_q10-pad3_ 34 +r26 net-_q63-pad3_ net-_q10-pad3_ 35 +q72 net-_q72-pad1_ net-_q72-pad1_ net-_q72-pad3_ Q2N2222 +r32 net-_q72-pad1_ net-_q76-pad1_ 220 +r31 net-_q72-pad3_ net-_c4-pad1_ 45k +q71 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q74 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q76 net-_q76-pad1_ net-_q72-pad3_ net-_c4-pad1_ Q2N2222 +q64 net-_c4-pad2_ net-_q64-pad2_ net-_q10-pad3_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +r30 net-_q64-pad2_ net-_q10-pad3_ 7 +q83 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +q85 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +r37 net-_q80-pad2_ net-_q84-pad3_ 270 +q84 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +q86 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +r38 net-_q80-pad3_ net-_q80-pad2_ 64 +q80 net-_q76-pad1_ net-_q80-pad2_ net-_q80-pad3_ Q2N2222 +q97 net-_j24-pad2_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q96 net-_j22-pad1_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +q99 net-_j22-pad2_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +j22 net-_j22-pad1_ net-_j22-pad2_ net-_j22-pad3_ J2N3820 +j24 net-_j22-pad2_ net-_j24-pad2_ net-_j22-pad3_ J2N3820 +q98 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q100 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q95 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +r40 net-_j22-pad3_ net-_q100-pad2_ 3.5k +q90 net-_q100-pad2_ net-_j22-pad3_ net-_q10-pad3_ Q2N2222 +q103 net-_q103-pad1_ net-_q103-pad1_ net-_q103-pad3_ Q2N2222 +q104 net-_q10-pad3_ net-_j24-pad2_ net-_q103-pad3_ Q2N2907A +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.pro b/library/SubcircuitLibrary/TL064_sub/TL064_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.sch b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sch new file mode 100644 index 00000000..85273f71 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sch @@ -0,0 +1,3533 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:TL064_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 47244 39370 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q2 +U 1 1 668A6280 +P 4900 4400 +F 0 "Q2" H 4800 4450 50 0000 R CNN +F 1 "eSim_PNP" H 4850 4550 50 0000 R CNN +F 2 "" H 5100 4500 29 0000 C CNN +F 3 "" H 4900 4400 60 0000 C CNN + 1 4900 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 668A6281 +P 5350 4400 +F 0 "Q4" H 5250 4450 50 0000 R CNN +F 1 "eSim_PNP" H 5300 4550 50 0000 R CNN +F 2 "" H 5550 4500 29 0000 C CNN +F 3 "" H 5350 4400 60 0000 C CNN + 1 5350 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 668A6282 +P 8600 4450 +F 0 "Q15" H 8500 4500 50 0000 R CNN +F 1 "eSim_PNP" H 8550 4600 50 0000 R CNN +F 2 "" H 8800 4550 29 0000 C CNN +F 3 "" H 8600 4450 60 0000 C CNN + 1 8600 4450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 668A6283 +P 9050 4450 +F 0 "Q17" H 8950 4500 50 0000 R CNN +F 1 "eSim_PNP" H 9000 4600 50 0000 R CNN +F 2 "" H 9250 4550 29 0000 C CNN +F 3 "" H 9050 4450 60 0000 C CNN + 1 9050 4450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 668A6284 +P 5150 5600 +F 0 "Q3" H 5050 5650 50 0000 R CNN +F 1 "eSim_PNP" H 5100 5750 50 0000 R CNN +F 2 "" H 5350 5700 29 0000 C CNN +F 3 "" H 5150 5600 60 0000 C CNN + 1 5150 5600 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J2 +U 1 1 668A6285 +P 4700 6700 +F 0 "J2" H 4600 6750 50 0000 R CNN +F 1 "jfet_p" H 4650 6850 50 0000 R CNN +F 2 "" H 4900 6800 29 0000 C CNN +F 3 "" H 4700 6700 60 0000 C CNN + 1 4700 6700 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J1 +U 1 1 668A6286 +P 3850 6700 +F 0 "J1" H 3750 6750 50 0000 R CNN +F 1 "jfet_p" H 3800 6850 50 0000 R CNN +F 2 "" H 4050 6800 29 0000 C CNN +F 3 "" H 3850 6700 60 0000 C CNN + 1 3850 6700 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J5 +U 1 1 668A6287 +P 5700 6700 +F 0 "J5" H 5600 6750 50 0000 R CNN +F 1 "jfet_p" H 5650 6850 50 0000 R CNN +F 2 "" H 5900 6800 29 0000 C CNN +F 3 "" H 5700 6700 60 0000 C CNN + 1 5700 6700 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J6 +U 1 1 668A6288 +P 6350 6700 +F 0 "J6" H 6250 6750 50 0000 R CNN +F 1 "jfet_p" H 6300 6850 50 0000 R CNN +F 2 "" H 6550 6800 29 0000 C CNN +F 3 "" H 6350 6700 60 0000 C CNN + 1 6350 6700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 668A6289 +P 4400 8400 +F 0 "Q1" H 4300 8450 50 0000 R CNN +F 1 "eSim_NPN" H 4350 8550 50 0000 R CNN +F 2 "" H 4600 8500 29 0000 C CNN +F 3 "" H 4400 8400 60 0000 C CNN + 1 4400 8400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 668A628A +P 5700 8400 +F 0 "Q6" H 5600 8450 50 0000 R CNN +F 1 "eSim_NPN" H 5650 8550 50 0000 R CNN +F 2 "" H 5900 8500 29 0000 C CNN +F 3 "" H 5700 8400 60 0000 C CNN + 1 5700 8400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 668A628B +P 4250 9600 +F 0 "R3" H 4300 9730 50 0000 C CNN +F 1 "34" H 4300 9550 50 0000 C CNN +F 2 "" H 4300 9580 30 0000 C CNN +F 3 "" V 4300 9650 30 0000 C CNN + 1 4250 9600 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 668A628C +P 5750 9600 +F 0 "R5" H 5800 9730 50 0000 C CNN +F 1 "35" H 5800 9550 50 0000 C CNN +F 2 "" H 5800 9580 30 0000 C CNN +F 3 "" V 5800 9650 30 0000 C CNN + 1 5750 9600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 668A628D +P 8450 5450 +F 0 "Q14" H 8350 5500 50 0000 R CNN +F 1 "eSim_NPN" H 8400 5600 50 0000 R CNN +F 2 "" H 8650 5550 29 0000 C CNN +F 3 "" H 8450 5450 60 0000 C CNN + 1 8450 5450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 668A628E +P 9300 5200 +F 0 "R9" H 9350 5330 50 0000 C CNN +F 1 "220" H 9350 5150 50 0000 C CNN +F 2 "" H 9350 5180 30 0000 C CNN +F 3 "" V 9350 5250 30 0000 C CNN + 1 9300 5200 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 668A628F +P 8500 6100 +F 0 "R8" H 8550 6230 50 0000 C CNN +F 1 "45k" H 8550 6050 50 0000 C CNN +F 2 "" H 8550 6080 30 0000 C CNN +F 3 "" V 8550 6150 30 0000 C CNN + 1 8500 6100 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 668A6290 +P 8200 7450 +F 0 "Q13" H 8100 7500 50 0000 R CNN +F 1 "eSim_NPN" H 8150 7600 50 0000 R CNN +F 2 "" H 8400 7550 29 0000 C CNN +F 3 "" H 8200 7450 60 0000 C CNN + 1 8200 7450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 668A6291 +P 8650 7450 +F 0 "Q16" H 8550 7500 50 0000 R CNN +F 1 "eSim_NPN" H 8600 7600 50 0000 R CNN +F 2 "" H 8850 7550 29 0000 C CNN +F 3 "" H 8650 7450 60 0000 C CNN + 1 8650 7450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 668A6292 +P 9250 5850 +F 0 "Q19" H 9150 5900 50 0000 R CNN +F 1 "eSim_NPN" H 9200 6000 50 0000 R CNN +F 2 "" H 9450 5950 29 0000 C CNN +F 3 "" H 9250 5850 60 0000 C CNN + 1 9250 5850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 668A6293 +P 6500 8900 +F 0 "Q10" H 6400 8950 50 0000 R CNN +F 1 "eSim_NPN" H 6450 9050 50 0000 R CNN +F 2 "" H 6700 9000 29 0000 C CNN +F 3 "" H 6500 8900 60 0000 C CNN + 1 6500 8900 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 668A6294 +P 6800 7700 +F 0 "C1" H 6825 7800 50 0000 L CNN +F 1 "10p" H 6825 7600 50 0000 L CNN +F 2 "" H 6838 7550 30 0000 C CNN +F 3 "" H 6800 7700 60 0000 C CNN + 1 6800 7700 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 668A6295 +P 8450 9300 +F 0 "R7" H 8500 9430 50 0000 C CNN +F 1 "7" H 8500 9250 50 0000 C CNN +F 2 "" H 8500 9280 30 0000 C CNN +F 3 "" V 8500 9350 30 0000 C CNN + 1 8450 9300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q26 +U 1 1 668A6296 +P 11600 5600 +F 0 "Q26" H 11500 5650 50 0000 R CNN +F 1 "eSim_NPN" H 11550 5750 50 0000 R CNN +F 2 "" H 11800 5700 29 0000 C CNN +F 3 "" H 11600 5600 60 0000 C CNN + 1 11600 5600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q29 +U 1 1 668A6297 +P 12100 5600 +F 0 "Q29" H 12000 5650 50 0000 R CNN +F 1 "eSim_NPN" H 12050 5750 50 0000 R CNN +F 2 "" H 12300 5700 29 0000 C CNN +F 3 "" H 12100 5600 60 0000 C CNN + 1 12100 5600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R15 +U 1 1 668A6298 +P 11950 6800 +F 0 "R15" H 12000 6930 50 0000 C CNN +F 1 "270" H 12000 6750 50 0000 C CNN +F 2 "" H 12000 6780 30 0000 C CNN +F 3 "" V 12000 6850 30 0000 C CNN + 1 11950 6800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q28 +U 1 1 668A6299 +P 11800 7700 +F 0 "Q28" H 11700 7750 50 0000 R CNN +F 1 "eSim_PNP" H 11750 7850 50 0000 R CNN +F 2 "" H 12000 7800 29 0000 C CNN +F 3 "" H 11800 7700 60 0000 C CNN + 1 11800 7700 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q30 +U 1 1 668A629A +P 12200 7700 +F 0 "Q30" H 12100 7750 50 0000 R CNN +F 1 "eSim_PNP" H 12150 7850 50 0000 R CNN +F 2 "" H 12400 7800 29 0000 C CNN +F 3 "" H 12200 7700 60 0000 C CNN + 1 12200 7700 + 1 0 0 1 +$EndComp +$Comp +L resistor R16 +U 1 1 668A629B +P 12600 6350 +F 0 "R16" H 12650 6480 50 0000 C CNN +F 1 "64" H 12650 6300 50 0000 C CNN +F 2 "" H 12650 6330 30 0000 C CNN +F 3 "" V 12650 6400 30 0000 C CNN + 1 12600 6350 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q25 +U 1 1 668A629D +P 10800 6200 +F 0 "Q25" H 10700 6250 50 0000 R CNN +F 1 "eSim_NPN" H 10750 6350 50 0000 R CNN +F 2 "" H 11000 6300 29 0000 C CNN +F 3 "" H 10800 6200 60 0000 C CNN + 1 10800 6200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q39 +U 1 1 668A629E +P 16200 4400 +F 0 "Q39" H 16100 4450 50 0000 R CNN +F 1 "eSim_PNP" H 16150 4550 50 0000 R CNN +F 2 "" H 16400 4500 29 0000 C CNN +F 3 "" H 16200 4400 60 0000 C CNN + 1 16200 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q38 +U 1 1 668A629F +P 16050 5300 +F 0 "Q38" H 15950 5350 50 0000 R CNN +F 1 "eSim_PNP" H 16000 5450 50 0000 R CNN +F 2 "" H 16250 5400 29 0000 C CNN +F 3 "" H 16050 5300 60 0000 C CNN + 1 16050 5300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q41 +U 1 1 668A62A0 +P 16450 5300 +F 0 "Q41" H 16350 5350 50 0000 R CNN +F 1 "eSim_PNP" H 16400 5450 50 0000 R CNN +F 2 "" H 16650 5400 29 0000 C CNN +F 3 "" H 16450 5300 60 0000 C CNN + 1 16450 5300 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J9 +U 1 1 668A62A1 +P 15800 6600 +F 0 "J9" H 15700 6650 50 0000 R CNN +F 1 "jfet_p" H 15750 6750 50 0000 R CNN +F 2 "" H 16000 6700 29 0000 C CNN +F 3 "" H 15800 6600 60 0000 C CNN + 1 15800 6600 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J11 +U 1 1 668A62A2 +P 17000 6600 +F 0 "J11" H 16900 6650 50 0000 R CNN +F 1 "jfet_p" H 16950 6750 50 0000 R CNN +F 2 "" H 17200 6700 29 0000 C CNN +F 3 "" H 17000 6600 60 0000 C CNN + 1 17000 6600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q40 +U 1 1 668A62A3 +P 16200 8050 +F 0 "Q40" H 16100 8100 50 0000 R CNN +F 1 "eSim_NPN" H 16150 8200 50 0000 R CNN +F 2 "" H 16400 8150 29 0000 C CNN +F 3 "" H 16200 8050 60 0000 C CNN + 1 16200 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q42 +U 1 1 668A62A4 +P 16650 8050 +F 0 "Q42" H 16550 8100 50 0000 R CNN +F 1 "eSim_NPN" H 16600 8200 50 0000 R CNN +F 2 "" H 16850 8150 29 0000 C CNN +F 3 "" H 16650 8050 60 0000 C CNN + 1 16650 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q36 +U 1 1 668A62A5 +P 15800 8050 +F 0 "Q36" H 15700 8100 50 0000 R CNN +F 1 "eSim_NPN" H 15750 8200 50 0000 R CNN +F 2 "" H 16000 8150 29 0000 C CNN +F 3 "" H 15800 8050 60 0000 C CNN + 1 15800 8050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R19 +U 1 1 668A62A6 +P 15050 7450 +F 0 "R19" H 15100 7580 50 0000 C CNN +F 1 "3.5k" H 15100 7400 50 0000 C CNN +F 2 "" H 15100 7430 30 0000 C CNN +F 3 "" V 15100 7500 30 0000 C CNN + 1 15050 7450 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q35 +U 1 1 668A62A7 +P 15000 8500 +F 0 "Q35" H 14900 8550 50 0000 R CNN +F 1 "eSim_NPN" H 14950 8650 50 0000 R CNN +F 2 "" H 15200 8600 29 0000 C CNN +F 3 "" H 15000 8500 60 0000 C CNN + 1 15000 8500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q49 +U 1 1 668A62A8 +P 18900 4700 +F 0 "Q49" H 18800 4750 50 0000 R CNN +F 1 "eSim_NPN" H 18850 4850 50 0000 R CNN +F 2 "" H 19100 4800 29 0000 C CNN +F 3 "" H 18900 4700 60 0000 C CNN + 1 18900 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q50 +U 1 1 668A62A9 +P 18900 5650 +F 0 "Q50" H 18800 5700 50 0000 R CNN +F 1 "eSim_PNP" H 18850 5800 50 0000 R CNN +F 2 "" H 19100 5750 29 0000 C CNN +F 3 "" H 18900 5650 60 0000 C CNN + 1 18900 5650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 668A93A8 +P 5850 21300 +F 0 "Q7" H 5750 21350 50 0000 R CNN +F 1 "eSim_PNP" H 5800 21450 50 0000 R CNN +F 2 "" H 6050 21400 29 0000 C CNN +F 3 "" H 5850 21300 60 0000 C CNN + 1 5850 21300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 668A93AE +P 6300 21300 +F 0 "Q9" H 6200 21350 50 0000 R CNN +F 1 "eSim_PNP" H 6250 21450 50 0000 R CNN +F 2 "" H 6500 21400 29 0000 C CNN +F 3 "" H 6300 21300 60 0000 C CNN + 1 6300 21300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q21 +U 1 1 668A93B4 +P 9550 21350 +F 0 "Q21" H 9450 21400 50 0000 R CNN +F 1 "eSim_PNP" H 9500 21500 50 0000 R CNN +F 2 "" H 9750 21450 29 0000 C CNN +F 3 "" H 9550 21350 60 0000 C CNN + 1 9550 21350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q23 +U 1 1 668A93BA +P 10000 21350 +F 0 "Q23" H 9900 21400 50 0000 R CNN +F 1 "eSim_PNP" H 9950 21500 50 0000 R CNN +F 2 "" H 10200 21450 29 0000 C CNN +F 3 "" H 10000 21350 60 0000 C CNN + 1 10000 21350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 668A93C0 +P 6100 22500 +F 0 "Q8" H 6000 22550 50 0000 R CNN +F 1 "eSim_PNP" H 6050 22650 50 0000 R CNN +F 2 "" H 6300 22600 29 0000 C CNN +F 3 "" H 6100 22500 60 0000 C CNN + 1 6100 22500 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J4 +U 1 1 668A93C6 +P 5650 23600 +F 0 "J4" H 5550 23650 50 0000 R CNN +F 1 "jfet_p" H 5600 23750 50 0000 R CNN +F 2 "" H 5850 23700 29 0000 C CNN +F 3 "" H 5650 23600 60 0000 C CNN + 1 5650 23600 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J3 +U 1 1 668A93CC +P 4800 23600 +F 0 "J3" H 4700 23650 50 0000 R CNN +F 1 "jfet_p" H 4750 23750 50 0000 R CNN +F 2 "" H 5000 23700 29 0000 C CNN +F 3 "" H 4800 23600 60 0000 C CNN + 1 4800 23600 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J7 +U 1 1 668A93D2 +P 6650 23600 +F 0 "J7" H 6550 23650 50 0000 R CNN +F 1 "jfet_p" H 6600 23750 50 0000 R CNN +F 2 "" H 6850 23700 29 0000 C CNN +F 3 "" H 6650 23600 60 0000 C CNN + 1 6650 23600 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J8 +U 1 1 668A93D8 +P 7300 23600 +F 0 "J8" H 7200 23650 50 0000 R CNN +F 1 "jfet_p" H 7250 23750 50 0000 R CNN +F 2 "" H 7500 23700 29 0000 C CNN +F 3 "" H 7300 23600 60 0000 C CNN + 1 7300 23600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 668A93DE +P 5350 25300 +F 0 "Q5" H 5250 25350 50 0000 R CNN +F 1 "eSim_NPN" H 5300 25450 50 0000 R CNN +F 2 "" H 5550 25400 29 0000 C CNN +F 3 "" H 5350 25300 60 0000 C CNN + 1 5350 25300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 668A93E4 +P 6650 25300 +F 0 "Q11" H 6550 25350 50 0000 R CNN +F 1 "eSim_NPN" H 6600 25450 50 0000 R CNN +F 2 "" H 6850 25400 29 0000 C CNN +F 3 "" H 6650 25300 60 0000 C CNN + 1 6650 25300 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 668A93EA +P 5200 26500 +F 0 "R4" H 5250 26630 50 0000 C CNN +F 1 "34" H 5250 26450 50 0000 C CNN +F 2 "" H 5250 26480 30 0000 C CNN +F 3 "" V 5250 26550 30 0000 C CNN + 1 5200 26500 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 668A93F0 +P 6700 26500 +F 0 "R6" H 6750 26630 50 0000 C CNN +F 1 "35" H 6750 26450 50 0000 C CNN +F 2 "" H 6750 26480 30 0000 C CNN +F 3 "" V 6750 26550 30 0000 C CNN + 1 6700 26500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 668A93F6 +P 9400 22350 +F 0 "Q20" H 9300 22400 50 0000 R CNN +F 1 "eSim_NPN" H 9350 22500 50 0000 R CNN +F 2 "" H 9600 22450 29 0000 C CNN +F 3 "" H 9400 22350 60 0000 C CNN + 1 9400 22350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R12 +U 1 1 668A93FC +P 10250 22100 +F 0 "R12" H 10300 22230 50 0000 C CNN +F 1 "220" H 10300 22050 50 0000 C CNN +F 2 "" H 10300 22080 30 0000 C CNN +F 3 "" V 10300 22150 30 0000 C CNN + 1 10250 22100 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 668A9402 +P 9450 23000 +F 0 "R11" H 9500 23130 50 0000 C CNN +F 1 "45k" H 9500 22950 50 0000 C CNN +F 2 "" H 9500 22980 30 0000 C CNN +F 3 "" V 9500 23050 30 0000 C CNN + 1 9450 23000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 668A9408 +P 9150 24350 +F 0 "Q18" H 9050 24400 50 0000 R CNN +F 1 "eSim_NPN" H 9100 24500 50 0000 R CNN +F 2 "" H 9350 24450 29 0000 C CNN +F 3 "" H 9150 24350 60 0000 C CNN + 1 9150 24350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q22 +U 1 1 668A940E +P 9600 24350 +F 0 "Q22" H 9500 24400 50 0000 R CNN +F 1 "eSim_NPN" H 9550 24500 50 0000 R CNN +F 2 "" H 9800 24450 29 0000 C CNN +F 3 "" H 9600 24350 60 0000 C CNN + 1 9600 24350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q24 +U 1 1 668A9414 +P 10200 22750 +F 0 "Q24" H 10100 22800 50 0000 R CNN +F 1 "eSim_NPN" H 10150 22900 50 0000 R CNN +F 2 "" H 10400 22850 29 0000 C CNN +F 3 "" H 10200 22750 60 0000 C CNN + 1 10200 22750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 668A941A +P 7450 25800 +F 0 "Q12" H 7350 25850 50 0000 R CNN +F 1 "eSim_NPN" H 7400 25950 50 0000 R CNN +F 2 "" H 7650 25900 29 0000 C CNN +F 3 "" H 7450 25800 60 0000 C CNN + 1 7450 25800 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 668A9420 +P 7750 24600 +F 0 "C2" H 7775 24700 50 0000 L CNN +F 1 "10p" H 7775 24500 50 0000 L CNN +F 2 "" H 7788 24450 30 0000 C CNN +F 3 "" H 7750 24600 60 0000 C CNN + 1 7750 24600 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 668A9426 +P 9400 26200 +F 0 "R10" H 9450 26330 50 0000 C CNN +F 1 "7" H 9450 26150 50 0000 C CNN +F 2 "" H 9450 26180 30 0000 C CNN +F 3 "" V 9450 26250 30 0000 C CNN + 1 9400 26200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q31 +U 1 1 668A942C +P 12550 22500 +F 0 "Q31" H 12450 22550 50 0000 R CNN +F 1 "eSim_NPN" H 12500 22650 50 0000 R CNN +F 2 "" H 12750 22600 29 0000 C CNN +F 3 "" H 12550 22500 60 0000 C CNN + 1 12550 22500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q33 +U 1 1 668A9432 +P 13050 22500 +F 0 "Q33" H 12950 22550 50 0000 R CNN +F 1 "eSim_NPN" H 13000 22650 50 0000 R CNN +F 2 "" H 13250 22600 29 0000 C CNN +F 3 "" H 13050 22500 60 0000 C CNN + 1 13050 22500 + 1 0 0 -1 +$EndComp +$Comp +L resistor R17 +U 1 1 668A9438 +P 12900 23700 +F 0 "R17" H 12950 23830 50 0000 C CNN +F 1 "270" H 12950 23650 50 0000 C CNN +F 2 "" H 12950 23680 30 0000 C CNN +F 3 "" V 12950 23750 30 0000 C CNN + 1 12900 23700 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q32 +U 1 1 668A943E +P 12750 24600 +F 0 "Q32" H 12650 24650 50 0000 R CNN +F 1 "eSim_PNP" H 12700 24750 50 0000 R CNN +F 2 "" H 12950 24700 29 0000 C CNN +F 3 "" H 12750 24600 60 0000 C CNN + 1 12750 24600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q34 +U 1 1 668A9444 +P 13150 24600 +F 0 "Q34" H 13050 24650 50 0000 R CNN +F 1 "eSim_PNP" H 13100 24750 50 0000 R CNN +F 2 "" H 13350 24700 29 0000 C CNN +F 3 "" H 13150 24600 60 0000 C CNN + 1 13150 24600 + 1 0 0 1 +$EndComp +$Comp +L resistor R18 +U 1 1 668A944A +P 13550 23250 +F 0 "R18" H 13600 23380 50 0000 C CNN +F 1 "64" H 13600 23200 50 0000 C CNN +F 2 "" H 13600 23230 30 0000 C CNN +F 3 "" V 13600 23300 30 0000 C CNN + 1 13550 23250 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q27 +U 1 1 668A9456 +P 11750 23100 +F 0 "Q27" H 11650 23150 50 0000 R CNN +F 1 "eSim_NPN" H 11700 23250 50 0000 R CNN +F 2 "" H 11950 23200 29 0000 C CNN +F 3 "" H 11750 23100 60 0000 C CNN + 1 11750 23100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q45 +U 1 1 668A945D +P 17150 21300 +F 0 "Q45" H 17050 21350 50 0000 R CNN +F 1 "eSim_PNP" H 17100 21450 50 0000 R CNN +F 2 "" H 17350 21400 29 0000 C CNN +F 3 "" H 17150 21300 60 0000 C CNN + 1 17150 21300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q44 +U 1 1 668A9463 +P 17000 22200 +F 0 "Q44" H 16900 22250 50 0000 R CNN +F 1 "eSim_PNP" H 16950 22350 50 0000 R CNN +F 2 "" H 17200 22300 29 0000 C CNN +F 3 "" H 17000 22200 60 0000 C CNN + 1 17000 22200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q47 +U 1 1 668A9469 +P 17400 22200 +F 0 "Q47" H 17300 22250 50 0000 R CNN +F 1 "eSim_PNP" H 17350 22350 50 0000 R CNN +F 2 "" H 17600 22300 29 0000 C CNN +F 3 "" H 17400 22200 60 0000 C CNN + 1 17400 22200 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J10 +U 1 1 668A946F +P 16750 23500 +F 0 "J10" H 16650 23550 50 0000 R CNN +F 1 "jfet_p" H 16700 23650 50 0000 R CNN +F 2 "" H 16950 23600 29 0000 C CNN +F 3 "" H 16750 23500 60 0000 C CNN + 1 16750 23500 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J12 +U 1 1 668A9475 +P 17950 23500 +F 0 "J12" H 17850 23550 50 0000 R CNN +F 1 "jfet_p" H 17900 23650 50 0000 R CNN +F 2 "" H 18150 23600 29 0000 C CNN +F 3 "" H 17950 23500 60 0000 C CNN + 1 17950 23500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q46 +U 1 1 668A947B +P 17150 24950 +F 0 "Q46" H 17050 25000 50 0000 R CNN +F 1 "eSim_NPN" H 17100 25100 50 0000 R CNN +F 2 "" H 17350 25050 29 0000 C CNN +F 3 "" H 17150 24950 60 0000 C CNN + 1 17150 24950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q48 +U 1 1 668A9481 +P 17600 24950 +F 0 "Q48" H 17500 25000 50 0000 R CNN +F 1 "eSim_NPN" H 17550 25100 50 0000 R CNN +F 2 "" H 17800 25050 29 0000 C CNN +F 3 "" H 17600 24950 60 0000 C CNN + 1 17600 24950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q43 +U 1 1 668A9487 +P 16750 24950 +F 0 "Q43" H 16650 25000 50 0000 R CNN +F 1 "eSim_NPN" H 16700 25100 50 0000 R CNN +F 2 "" H 16950 25050 29 0000 C CNN +F 3 "" H 16750 24950 60 0000 C CNN + 1 16750 24950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R20 +U 1 1 668A948D +P 16000 24350 +F 0 "R20" H 16050 24480 50 0000 C CNN +F 1 "3.5k" H 16050 24300 50 0000 C CNN +F 2 "" H 16050 24330 30 0000 C CNN +F 3 "" V 16050 24400 30 0000 C CNN + 1 16000 24350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q37 +U 1 1 668A9493 +P 15950 25400 +F 0 "Q37" H 15850 25450 50 0000 R CNN +F 1 "eSim_NPN" H 15900 25550 50 0000 R CNN +F 2 "" H 16150 25500 29 0000 C CNN +F 3 "" H 15950 25400 60 0000 C CNN + 1 15950 25400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q51 +U 1 1 668A9499 +P 19850 21600 +F 0 "Q51" H 19750 21650 50 0000 R CNN +F 1 "eSim_NPN" H 19800 21750 50 0000 R CNN +F 2 "" H 20050 21700 29 0000 C CNN +F 3 "" H 19850 21600 60 0000 C CNN + 1 19850 21600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q52 +U 1 1 668A949F +P 19850 22550 +F 0 "Q52" H 19750 22600 50 0000 R CNN +F 1 "eSim_PNP" H 19800 22700 50 0000 R CNN +F 2 "" H 20050 22650 29 0000 C CNN +F 3 "" H 19850 22550 60 0000 C CNN + 1 19850 22550 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 668AF097 +P 17700 3650 +F 0 "U1" H 17750 3750 30 0000 C CNN +F 1 "PORT" H 17700 3650 30 0000 C CNN +F 2 "" H 17700 3650 60 0000 C CNN +F 3 "" H 17700 3650 60 0000 C CNN + 4 17700 3650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 668BFB6F +P 13750 6400 +F 0 "U1" H 13800 6500 30 0000 C CNN +F 1 "PORT" H 13750 6400 30 0000 C CNN +F 2 "" H 13750 6400 60 0000 C CNN +F 3 "" H 13750 6400 60 0000 C CNN + 1 13750 6400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 668C172A +P 1250 6700 +F 0 "U1" H 1300 6800 30 0000 C CNN +F 1 "PORT" H 1250 6700 30 0000 C CNN +F 2 "" H 1250 6700 60 0000 C CNN +F 3 "" H 1250 6700 60 0000 C CNN + 2 1250 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 668C2142 +P 7150 6700 +F 0 "U1" H 7200 6800 30 0000 C CNN +F 1 "PORT" H 7150 6700 30 0000 C CNN +F 2 "" H 7150 6700 60 0000 C CNN +F 3 "" H 7150 6700 60 0000 C CNN + 3 7150 6700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 668C5033 +P 2200 23600 +F 0 "U1" H 2250 23700 30 0000 C CNN +F 1 "PORT" H 2200 23600 30 0000 C CNN +F 2 "" H 2200 23600 60 0000 C CNN +F 3 "" H 2200 23600 60 0000 C CNN + 6 2200 23600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 668C6285 +P 8100 23600 +F 0 "U1" H 8150 23700 30 0000 C CNN +F 1 "PORT" H 8100 23600 30 0000 C CNN +F 2 "" H 8100 23600 60 0000 C CNN +F 3 "" H 8100 23600 60 0000 C CNN + 5 8100 23600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 668C7455 +P 14700 23300 +F 0 "U1" H 14750 23400 30 0000 C CNN +F 1 "PORT" H 14700 23300 30 0000 C CNN +F 2 "" H 14700 23300 60 0000 C CNN +F 3 "" H 14700 23300 60 0000 C CNN + 7 14700 23300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 668D0777 +P 20750 10300 +F 0 "U1" H 20800 10400 30 0000 C CNN +F 1 "PORT" H 20750 10300 30 0000 C CNN +F 2 "" H 20750 10300 60 0000 C CNN +F 3 "" H 20750 10300 60 0000 C CNN + 11 20750 10300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q54 +U 1 1 668A7956 +P 27050 5000 +F 0 "Q54" H 26950 5050 50 0000 R CNN +F 1 "eSim_PNP" H 27000 5150 50 0000 R CNN +F 2 "" H 27250 5100 29 0000 C CNN +F 3 "" H 27050 5000 60 0000 C CNN + 1 27050 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q56 +U 1 1 668A795C +P 27500 5000 +F 0 "Q56" H 27400 5050 50 0000 R CNN +F 1 "eSim_PNP" H 27450 5150 50 0000 R CNN +F 2 "" H 27700 5100 29 0000 C CNN +F 3 "" H 27500 5000 60 0000 C CNN + 1 27500 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q67 +U 1 1 668A7962 +P 30750 5050 +F 0 "Q67" H 30650 5100 50 0000 R CNN +F 1 "eSim_PNP" H 30700 5200 50 0000 R CNN +F 2 "" H 30950 5150 29 0000 C CNN +F 3 "" H 30750 5050 60 0000 C CNN + 1 30750 5050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q69 +U 1 1 668A7968 +P 31200 5050 +F 0 "Q69" H 31100 5100 50 0000 R CNN +F 1 "eSim_PNP" H 31150 5200 50 0000 R CNN +F 2 "" H 31400 5150 29 0000 C CNN +F 3 "" H 31200 5050 60 0000 C CNN + 1 31200 5050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q55 +U 1 1 668A796E +P 27300 6200 +F 0 "Q55" H 27200 6250 50 0000 R CNN +F 1 "eSim_PNP" H 27250 6350 50 0000 R CNN +F 2 "" H 27500 6300 29 0000 C CNN +F 3 "" H 27300 6200 60 0000 C CNN + 1 27300 6200 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J14 +U 1 1 668A7974 +P 26850 7300 +F 0 "J14" H 26750 7350 50 0000 R CNN +F 1 "jfet_p" H 26800 7450 50 0000 R CNN +F 2 "" H 27050 7400 29 0000 C CNN +F 3 "" H 26850 7300 60 0000 C CNN + 1 26850 7300 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J13 +U 1 1 668A797A +P 26000 7300 +F 0 "J13" H 25900 7350 50 0000 R CNN +F 1 "jfet_p" H 25950 7450 50 0000 R CNN +F 2 "" H 26200 7400 29 0000 C CNN +F 3 "" H 26000 7300 60 0000 C CNN + 1 26000 7300 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J16 +U 1 1 668A7980 +P 27850 7300 +F 0 "J16" H 27750 7350 50 0000 R CNN +F 1 "jfet_p" H 27800 7450 50 0000 R CNN +F 2 "" H 28050 7400 29 0000 C CNN +F 3 "" H 27850 7300 60 0000 C CNN + 1 27850 7300 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J18 +U 1 1 668A7986 +P 28500 7300 +F 0 "J18" H 28400 7350 50 0000 R CNN +F 1 "jfet_p" H 28450 7450 50 0000 R CNN +F 2 "" H 28700 7400 29 0000 C CNN +F 3 "" H 28500 7300 60 0000 C CNN + 1 28500 7300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q53 +U 1 1 668A798C +P 26550 9000 +F 0 "Q53" H 26450 9050 50 0000 R CNN +F 1 "eSim_NPN" H 26500 9150 50 0000 R CNN +F 2 "" H 26750 9100 29 0000 C CNN +F 3 "" H 26550 9000 60 0000 C CNN + 1 26550 9000 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q58 +U 1 1 668A7992 +P 27850 9000 +F 0 "Q58" H 27750 9050 50 0000 R CNN +F 1 "eSim_NPN" H 27800 9150 50 0000 R CNN +F 2 "" H 28050 9100 29 0000 C CNN +F 3 "" H 27850 9000 60 0000 C CNN + 1 27850 9000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R23 +U 1 1 668A7998 +P 26400 10200 +F 0 "R23" H 26450 10330 50 0000 C CNN +F 1 "34" H 26450 10150 50 0000 C CNN +F 2 "" H 26450 10180 30 0000 C CNN +F 3 "" V 26450 10250 30 0000 C CNN + 1 26400 10200 + 0 1 1 0 +$EndComp +$Comp +L resistor R25 +U 1 1 668A799E +P 27900 10200 +F 0 "R25" H 27950 10330 50 0000 C CNN +F 1 "35" H 27950 10150 50 0000 C CNN +F 2 "" H 27950 10180 30 0000 C CNN +F 3 "" V 27950 10250 30 0000 C CNN + 1 27900 10200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q66 +U 1 1 668A79A4 +P 30600 6050 +F 0 "Q66" H 30500 6100 50 0000 R CNN +F 1 "eSim_NPN" H 30550 6200 50 0000 R CNN +F 2 "" H 30800 6150 29 0000 C CNN +F 3 "" H 30600 6050 60 0000 C CNN + 1 30600 6050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R29 +U 1 1 668A79AA +P 31450 5800 +F 0 "R29" H 31500 5930 50 0000 C CNN +F 1 "220" H 31500 5750 50 0000 C CNN +F 2 "" H 31500 5780 30 0000 C CNN +F 3 "" V 31500 5850 30 0000 C CNN + 1 31450 5800 + 0 1 1 0 +$EndComp +$Comp +L resistor R28 +U 1 1 668A79B0 +P 30650 6700 +F 0 "R28" H 30700 6830 50 0000 C CNN +F 1 "45k" H 30700 6650 50 0000 C CNN +F 2 "" H 30700 6680 30 0000 C CNN +F 3 "" V 30700 6750 30 0000 C CNN + 1 30650 6700 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q65 +U 1 1 668A79B6 +P 30350 8050 +F 0 "Q65" H 30250 8100 50 0000 R CNN +F 1 "eSim_NPN" H 30300 8200 50 0000 R CNN +F 2 "" H 30550 8150 29 0000 C CNN +F 3 "" H 30350 8050 60 0000 C CNN + 1 30350 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q68 +U 1 1 668A79BC +P 30800 8050 +F 0 "Q68" H 30700 8100 50 0000 R CNN +F 1 "eSim_NPN" H 30750 8200 50 0000 R CNN +F 2 "" H 31000 8150 29 0000 C CNN +F 3 "" H 30800 8050 60 0000 C CNN + 1 30800 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q70 +U 1 1 668A79C2 +P 31400 6450 +F 0 "Q70" H 31300 6500 50 0000 R CNN +F 1 "eSim_NPN" H 31350 6600 50 0000 R CNN +F 2 "" H 31600 6550 29 0000 C CNN +F 3 "" H 31400 6450 60 0000 C CNN + 1 31400 6450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q62 +U 1 1 668A79C8 +P 28650 9500 +F 0 "Q62" H 28550 9550 50 0000 R CNN +F 1 "eSim_NPN" H 28600 9650 50 0000 R CNN +F 2 "" H 28850 9600 29 0000 C CNN +F 3 "" H 28650 9500 60 0000 C CNN + 1 28650 9500 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C3 +U 1 1 668A79CE +P 28950 8300 +F 0 "C3" H 28975 8400 50 0000 L CNN +F 1 "10p" H 28975 8200 50 0000 L CNN +F 2 "" H 28988 8150 30 0000 C CNN +F 3 "" H 28950 8300 60 0000 C CNN + 1 28950 8300 + 0 1 1 0 +$EndComp +$Comp +L resistor R27 +U 1 1 668A79D4 +P 30600 9900 +F 0 "R27" H 30650 10030 50 0000 C CNN +F 1 "7" H 30650 9850 50 0000 C CNN +F 2 "" H 30650 9880 30 0000 C CNN +F 3 "" V 30650 9950 30 0000 C CNN + 1 30600 9900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q78 +U 1 1 668A79DA +P 33750 6200 +F 0 "Q78" H 33650 6250 50 0000 R CNN +F 1 "eSim_NPN" H 33700 6350 50 0000 R CNN +F 2 "" H 33950 6300 29 0000 C CNN +F 3 "" H 33750 6200 60 0000 C CNN + 1 33750 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q81 +U 1 1 668A79E0 +P 34250 6200 +F 0 "Q81" H 34150 6250 50 0000 R CNN +F 1 "eSim_NPN" H 34200 6350 50 0000 R CNN +F 2 "" H 34450 6300 29 0000 C CNN +F 3 "" H 34250 6200 60 0000 C CNN + 1 34250 6200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R34 +U 1 1 668A79E6 +P 34100 7400 +F 0 "R34" H 34150 7530 50 0000 C CNN +F 1 "270" H 34150 7350 50 0000 C CNN +F 2 "" H 34150 7380 30 0000 C CNN +F 3 "" V 34150 7450 30 0000 C CNN + 1 34100 7400 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q79 +U 1 1 668A79EC +P 33950 8300 +F 0 "Q79" H 33850 8350 50 0000 R CNN +F 1 "eSim_PNP" H 33900 8450 50 0000 R CNN +F 2 "" H 34150 8400 29 0000 C CNN +F 3 "" H 33950 8300 60 0000 C CNN + 1 33950 8300 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q82 +U 1 1 668A79F2 +P 34350 8300 +F 0 "Q82" H 34250 8350 50 0000 R CNN +F 1 "eSim_PNP" H 34300 8450 50 0000 R CNN +F 2 "" H 34550 8400 29 0000 C CNN +F 3 "" H 34350 8300 60 0000 C CNN + 1 34350 8300 + 1 0 0 1 +$EndComp +$Comp +L resistor R36 +U 1 1 668A79F8 +P 34750 6950 +F 0 "R36" H 34800 7080 50 0000 C CNN +F 1 "64" H 34800 6900 50 0000 C CNN +F 2 "" H 34800 6930 30 0000 C CNN +F 3 "" V 34800 7000 30 0000 C CNN + 1 34750 6950 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q77 +U 1 1 668A79FE +P 32950 6800 +F 0 "Q77" H 32850 6850 50 0000 R CNN +F 1 "eSim_NPN" H 32900 6950 50 0000 R CNN +F 2 "" H 33150 6900 29 0000 C CNN +F 3 "" H 32950 6800 60 0000 C CNN + 1 32950 6800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q91 +U 1 1 668A7A04 +P 38350 5000 +F 0 "Q91" H 38250 5050 50 0000 R CNN +F 1 "eSim_PNP" H 38300 5150 50 0000 R CNN +F 2 "" H 38550 5100 29 0000 C CNN +F 3 "" H 38350 5000 60 0000 C CNN + 1 38350 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q89 +U 1 1 668A7A0A +P 38200 5900 +F 0 "Q89" H 38100 5950 50 0000 R CNN +F 1 "eSim_PNP" H 38150 6050 50 0000 R CNN +F 2 "" H 38400 6000 29 0000 C CNN +F 3 "" H 38200 5900 60 0000 C CNN + 1 38200 5900 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q93 +U 1 1 668A7A10 +P 38600 5900 +F 0 "Q93" H 38500 5950 50 0000 R CNN +F 1 "eSim_PNP" H 38550 6050 50 0000 R CNN +F 2 "" H 38800 6000 29 0000 C CNN +F 3 "" H 38600 5900 60 0000 C CNN + 1 38600 5900 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J21 +U 1 1 668A7A16 +P 37950 7200 +F 0 "J21" H 37850 7250 50 0000 R CNN +F 1 "jfet_p" H 37900 7350 50 0000 R CNN +F 2 "" H 38150 7300 29 0000 C CNN +F 3 "" H 37950 7200 60 0000 C CNN + 1 37950 7200 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J23 +U 1 1 668A7A1C +P 39150 7200 +F 0 "J23" H 39050 7250 50 0000 R CNN +F 1 "jfet_p" H 39100 7350 50 0000 R CNN +F 2 "" H 39350 7300 29 0000 C CNN +F 3 "" H 39150 7200 60 0000 C CNN + 1 39150 7200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q92 +U 1 1 668A7A22 +P 38350 8650 +F 0 "Q92" H 38250 8700 50 0000 R CNN +F 1 "eSim_NPN" H 38300 8800 50 0000 R CNN +F 2 "" H 38550 8750 29 0000 C CNN +F 3 "" H 38350 8650 60 0000 C CNN + 1 38350 8650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q94 +U 1 1 668A7A28 +P 38800 8650 +F 0 "Q94" H 38700 8700 50 0000 R CNN +F 1 "eSim_NPN" H 38750 8800 50 0000 R CNN +F 2 "" H 39000 8750 29 0000 C CNN +F 3 "" H 38800 8650 60 0000 C CNN + 1 38800 8650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q88 +U 1 1 668A7A2E +P 37950 8650 +F 0 "Q88" H 37850 8700 50 0000 R CNN +F 1 "eSim_NPN" H 37900 8800 50 0000 R CNN +F 2 "" H 38150 8750 29 0000 C CNN +F 3 "" H 37950 8650 60 0000 C CNN + 1 37950 8650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R39 +U 1 1 668A7A34 +P 37200 8050 +F 0 "R39" H 37250 8180 50 0000 C CNN +F 1 "3.5k" H 37250 8000 50 0000 C CNN +F 2 "" H 37250 8030 30 0000 C CNN +F 3 "" V 37250 8100 30 0000 C CNN + 1 37200 8050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q87 +U 1 1 668A7A3A +P 37150 9100 +F 0 "Q87" H 37050 9150 50 0000 R CNN +F 1 "eSim_NPN" H 37100 9250 50 0000 R CNN +F 2 "" H 37350 9200 29 0000 C CNN +F 3 "" H 37150 9100 60 0000 C CNN + 1 37150 9100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q101 +U 1 1 668A7A40 +P 41050 5300 +F 0 "Q101" H 40950 5350 50 0000 R CNN +F 1 "eSim_NPN" H 41000 5450 50 0000 R CNN +F 2 "" H 41250 5400 29 0000 C CNN +F 3 "" H 41050 5300 60 0000 C CNN + 1 41050 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q102 +U 1 1 668A7A46 +P 41050 6250 +F 0 "Q102" H 40950 6300 50 0000 R CNN +F 1 "eSim_PNP" H 41000 6400 50 0000 R CNN +F 2 "" H 41250 6350 29 0000 C CNN +F 3 "" H 41050 6250 60 0000 C CNN + 1 41050 6250 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 668A7B49 +P 35900 7000 +F 0 "U1" H 35950 7100 30 0000 C CNN +F 1 "PORT" H 35900 7000 30 0000 C CNN +F 2 "" H 35900 7000 60 0000 C CNN +F 3 "" H 35900 7000 60 0000 C CNN + 14 35900 7000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 668A7B4F +P 23400 7300 +F 0 "U1" H 23450 7400 30 0000 C CNN +F 1 "PORT" H 23400 7300 30 0000 C CNN +F 2 "" H 23400 7300 60 0000 C CNN +F 3 "" H 23400 7300 60 0000 C CNN + 13 23400 7300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 668A7B55 +P 29300 7300 +F 0 "U1" H 29350 7400 30 0000 C CNN +F 1 "PORT" H 29300 7300 30 0000 C CNN +F 2 "" H 29300 7300 60 0000 C CNN +F 3 "" H 29300 7300 60 0000 C CNN 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9500 +Wire Wire Line + 8500 8500 8500 9200 +Connection ~ 5800 10300 +Wire Wire Line + 6400 10300 6400 9100 +Connection ~ 8550 6950 +Wire Wire Line + 7150 6950 8550 6950 +Wire Wire Line + 7150 7700 7150 6950 +Wire Wire Line + 6950 7700 7150 7700 +Connection ~ 6400 7700 +Wire Wire Line + 6400 7700 6400 8700 +Connection ~ 5800 7700 +Wire Wire Line + 5800 7700 6650 7700 +Wire Wire Line + 8450 7450 8000 7450 +Wire Wire Line + 8750 7800 8750 7650 +Wire Wire Line + 8300 7650 8300 8500 +Connection ~ 8550 5850 +Wire Wire Line + 9050 5850 8550 5850 +Wire Wire Line + 9350 5400 9350 5650 +Wire Wire Line + 8550 5650 8550 6000 +Wire Wire Line + 8750 7200 8750 7250 +Wire Wire Line + 8300 7250 8300 7200 +Connection ~ 8550 5000 +Wire Wire Line + 8100 5450 8100 5000 +Wire Wire Line + 8250 5450 8100 5450 +Connection ~ 8900 4750 +Connection ~ 8900 5000 +Wire Wire Line + 8900 5000 8900 4750 +Wire Wire Line + 9150 4750 9150 4650 +Wire Wire Line + 8700 4750 9150 4750 +Wire Wire Line + 8700 4650 8700 4750 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6800 34150 6800 +Connection ~ 28700 7300 +Wire Wire Line + 23650 7300 26650 7300 +Connection ~ 25800 7300 +Connection ~ 41150 10900 +Connection ~ 38250 4400 +Connection ~ 40500 5000 +Wire Wire Line + 40500 5000 40500 5300 +Wire Wire Line + 40500 5300 40850 5300 +Connection ~ 41150 5700 +Wire Wire Line + 29050 6200 27500 6200 +Wire Wire Line + 29050 5700 29050 6200 +Wire Wire Line + 41150 5700 29050 5700 +Connection ~ 38900 10900 +Wire Wire Line + 41150 6450 41150 11000 +Connection ~ 39350 6250 +Wire Wire Line + 40850 6250 39350 6250 +Wire Wire Line + 41150 5500 41150 6050 +Connection ~ 38550 5000 +Wire Wire Line + 41150 5000 41150 5100 +Connection ~ 38250 5450 +Wire Wire Line + 39350 5450 38250 5450 +Wire Wire Line + 39350 5450 39350 7200 +Connection ~ 38900 9150 +Wire Wire Line + 38900 9150 38050 9150 +Wire Wire Line + 38050 9150 38050 8850 +Connection ~ 38900 9000 +Wire Wire Line + 38450 9000 38900 9000 +Wire Wire Line + 38450 8850 38450 9000 +Connection ~ 37250 10900 +Wire Wire Line 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33850 5900 +Wire Wire Line + 31500 6200 34050 6200 +Connection ~ 30650 9500 +Wire Wire Line + 28850 9500 30650 9500 +Connection ~ 28550 10900 +Wire Wire Line + 30650 10900 30650 10100 +Wire Wire Line + 30650 9100 30650 9800 +Connection ~ 27950 10900 +Wire Wire Line + 28550 10900 28550 9700 +Connection ~ 30700 7550 +Wire Wire Line + 29300 7550 30700 7550 +Wire Wire Line + 29300 8300 29300 7550 +Wire Wire Line + 29100 8300 29300 8300 +Connection ~ 28550 8300 +Wire Wire Line + 28550 8300 28550 9300 +Connection ~ 27950 8300 +Wire Wire Line + 27950 8300 28800 8300 +Wire Wire Line + 30600 8050 30150 8050 +Wire Wire Line + 30900 8400 30900 8250 +Wire Wire Line + 30450 8250 30450 9100 +Connection ~ 30700 6450 +Wire Wire Line + 31200 6450 30700 6450 +Wire Wire Line + 31500 6000 31500 6250 +Wire Wire Line + 30700 6250 30700 6600 +Wire Wire Line + 30900 7800 30900 7850 +Wire Wire Line + 30450 7850 30450 7800 +Connection ~ 30700 5600 +Wire Wire Line + 30250 6050 30250 5600 +Wire Wire Line + 30400 6050 30250 6050 +Connection ~ 31050 5350 +Connection ~ 31050 5600 +Wire Wire Line + 31050 5600 31050 5350 +Wire Wire Line + 31300 5350 31300 5250 +Wire Wire Line + 30850 5350 31300 5350 +Wire Wire Line + 30850 5250 30850 5350 +Wire Wire Line + 31500 5600 31500 5700 +Wire Wire Line + 30250 5600 31500 5600 +Wire Wire Line + 30700 5850 30700 5600 +Wire Wire Line + 27950 10900 27950 10400 +Wire Wire Line + 26450 10900 41150 10900 +Wire Wire Line + 26450 10400 26450 10900 +Wire Wire Line + 27950 9200 27950 10100 +Wire Wire Line + 26450 9200 26450 10100 +Connection ~ 26450 8350 +Connection ~ 27200 9000 +Wire Wire Line + 27200 8350 27200 9000 +Wire Wire Line + 26450 8350 27200 8350 +Wire Wire Line + 26750 9000 27650 9000 +Connection ~ 26450 7600 +Wire Wire Line + 26450 7600 26450 8800 +Connection ~ 27950 7650 +Wire Wire Line + 27950 7650 27950 8800 +Wire Wire Line + 28400 7650 28400 7500 +Wire Wire Line + 27750 7650 28400 7650 +Wire Wire Line + 27750 7500 27750 7650 +Wire Wire Line + 26950 7600 26950 7500 +Wire Wire Line + 26100 7600 26950 7600 +Wire Wire Line + 26100 7500 26100 7600 +Connection ~ 27200 7000 +Wire Wire Line + 27200 7000 27200 6400 +Wire Wire Line + 28400 7000 28400 7100 +Connection ~ 26950 7000 +Connection ~ 27750 7000 +Wire Wire Line + 27750 7000 27750 7100 +Wire Wire Line + 26100 7000 26100 7100 +Wire Wire Line + 26100 7000 28400 7000 +Wire Wire Line + 26950 7000 26950 7100 +Wire Wire Line + 28050 7300 29050 7300 +Connection ~ 27200 5250 +Wire Wire Line + 27200 6000 27200 5250 +Wire Wire Line + 27400 5250 27400 5200 +Wire Wire Line + 26950 5250 27400 5250 +Wire Wire Line + 26950 5200 26950 5250 +Wire Wire Line + 27400 4400 38250 4400 +Wire Wire Line + 30850 4800 30850 4850 +Wire Wire Line + 31300 4800 31300 4850 +Wire Wire Line + 27700 5050 31450 5050 +Wire Wire Line + 27400 4400 27400 4800 +Wire Wire Line + 26950 4800 26950 4750 +Wire Wire Line + 27250 5000 27700 5000 +Wire Wire Line + 19600 14550 43700 14550 +Wire Wire Line + 21500 17000 39300 17000 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H 31650 21400 60 0000 C CNN + 1 31650 21400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q60 +U 1 1 668B1BFE +P 27750 22550 +F 0 "Q60" H 27650 22600 50 0000 R CNN +F 1 "eSim_PNP" H 27700 22700 50 0000 R CNN +F 2 "" H 27950 22650 29 0000 C CNN +F 3 "" H 27750 22550 60 0000 C CNN + 1 27750 22550 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J17 +U 1 1 668B1C04 +P 27300 23650 +F 0 "J17" H 27200 23700 50 0000 R CNN +F 1 "jfet_p" H 27250 23800 50 0000 R CNN +F 2 "" H 27500 23750 29 0000 C CNN +F 3 "" H 27300 23650 60 0000 C CNN + 1 27300 23650 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J15 +U 1 1 668B1C0A +P 26450 23650 +F 0 "J15" H 26350 23700 50 0000 R CNN +F 1 "jfet_p" H 26400 23800 50 0000 R CNN +F 2 "" H 26650 23750 29 0000 C CNN +F 3 "" H 26450 23650 60 0000 C CNN + 1 26450 23650 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J19 +U 1 1 668B1C10 +P 28300 23650 +F 0 "J19" H 28200 23700 50 0000 R CNN +F 1 "jfet_p" H 28250 23800 50 0000 R CNN +F 2 "" H 28500 23750 29 0000 C CNN +F 3 "" H 28300 23650 60 0000 C CNN + 1 28300 23650 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J20 +U 1 1 668B1C16 +P 28950 23650 +F 0 "J20" H 28850 23700 50 0000 R CNN +F 1 "jfet_p" H 28900 23800 50 0000 R CNN +F 2 "" H 29150 23750 29 0000 C CNN +F 3 "" H 28950 23650 60 0000 C CNN + 1 28950 23650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q57 +U 1 1 668B1C1C +P 27000 25350 +F 0 "Q57" H 26900 25400 50 0000 R CNN +F 1 "eSim_NPN" H 26950 25500 50 0000 R CNN +F 2 "" H 27200 25450 29 0000 C CNN +F 3 "" H 27000 25350 60 0000 C CNN + 1 27000 25350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q63 +U 1 1 668B1C22 +P 28300 25350 +F 0 "Q63" H 28200 25400 50 0000 R CNN +F 1 "eSim_NPN" H 28250 25500 50 0000 R CNN +F 2 "" H 28500 25450 29 0000 C CNN +F 3 "" H 28300 25350 60 0000 C CNN + 1 28300 25350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R24 +U 1 1 668B1C28 +P 26850 26550 +F 0 "R24" H 26900 26680 50 0000 C CNN +F 1 "34" H 26900 26500 50 0000 C CNN +F 2 "" H 26900 26530 30 0000 C CNN +F 3 "" V 26900 26600 30 0000 C CNN + 1 26850 26550 + 0 1 1 0 +$EndComp +$Comp +L resistor R26 +U 1 1 668B1C2E +P 28350 26550 +F 0 "R26" H 28400 26680 50 0000 C CNN +F 1 "35" H 28400 26500 50 0000 C CNN +F 2 "" H 28400 26530 30 0000 C CNN +F 3 "" V 28400 26600 30 0000 C CNN + 1 28350 26550 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q72 +U 1 1 668B1C34 +P 31050 22400 +F 0 "Q72" H 30950 22450 50 0000 R CNN +F 1 "eSim_NPN" H 31000 22550 50 0000 R CNN +F 2 "" H 31250 22500 29 0000 C CNN +F 3 "" H 31050 22400 60 0000 C CNN + 1 31050 22400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R32 +U 1 1 668B1C3A +P 31900 22150 +F 0 "R32" H 31950 22280 50 0000 C CNN +F 1 "220" H 31950 22100 50 0000 C CNN +F 2 "" H 31950 22130 30 0000 C CNN +F 3 "" V 31950 22200 30 0000 C CNN + 1 31900 22150 + 0 1 1 0 +$EndComp +$Comp +L resistor R31 +U 1 1 668B1C40 +P 31100 23050 +F 0 "R31" H 31150 23180 50 0000 C CNN +F 1 "45k" H 31150 23000 50 0000 C CNN +F 2 "" H 31150 23030 30 0000 C CNN +F 3 "" V 31150 23100 30 0000 C CNN + 1 31100 23050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q71 +U 1 1 668B1C46 +P 30800 24400 +F 0 "Q71" H 30700 24450 50 0000 R CNN +F 1 "eSim_NPN" H 30750 24550 50 0000 R CNN +F 2 "" H 31000 24500 29 0000 C CNN +F 3 "" H 30800 24400 60 0000 C CNN + 1 30800 24400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q74 +U 1 1 668B1C4C +P 31250 24400 +F 0 "Q74" H 31150 24450 50 0000 R CNN +F 1 "eSim_NPN" H 31200 24550 50 0000 R CNN +F 2 "" H 31450 24500 29 0000 C CNN +F 3 "" H 31250 24400 60 0000 C CNN + 1 31250 24400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q76 +U 1 1 668B1C52 +P 31850 22800 +F 0 "Q76" H 31750 22850 50 0000 R CNN +F 1 "eSim_NPN" H 31800 22950 50 0000 R CNN +F 2 "" H 32050 22900 29 0000 C CNN +F 3 "" H 31850 22800 60 0000 C CNN + 1 31850 22800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q64 +U 1 1 668B1C58 +P 29100 25850 +F 0 "Q64" H 29000 25900 50 0000 R CNN +F 1 "eSim_NPN" H 29050 26000 50 0000 R CNN +F 2 "" H 29300 25950 29 0000 C CNN +F 3 "" H 29100 25850 60 0000 C CNN + 1 29100 25850 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 668B1C5E +P 29400 24650 +F 0 "C4" H 29425 24750 50 0000 L CNN +F 1 "10p" H 29425 24550 50 0000 L CNN +F 2 "" H 29438 24500 30 0000 C CNN +F 3 "" H 29400 24650 60 0000 C CNN + 1 29400 24650 + 0 1 1 0 +$EndComp +$Comp +L resistor R30 +U 1 1 668B1C64 +P 31050 26250 +F 0 "R30" H 31100 26380 50 0000 C CNN +F 1 "7" H 31100 26200 50 0000 C CNN +F 2 "" H 31100 26230 30 0000 C CNN +F 3 "" V 31100 26300 30 0000 C CNN + 1 31050 26250 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q83 +U 1 1 668B1C6A +P 34200 22550 +F 0 "Q83" H 34100 22600 50 0000 R CNN +F 1 "eSim_NPN" H 34150 22700 50 0000 R CNN +F 2 "" H 34400 22650 29 0000 C CNN +F 3 "" H 34200 22550 60 0000 C CNN + 1 34200 22550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q85 +U 1 1 668B1C70 +P 34700 22550 +F 0 "Q85" H 34600 22600 50 0000 R CNN +F 1 "eSim_NPN" H 34650 22700 50 0000 R CNN +F 2 "" H 34900 22650 29 0000 C CNN +F 3 "" H 34700 22550 60 0000 C CNN + 1 34700 22550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R37 +U 1 1 668B1C76 +P 34550 23750 +F 0 "R37" H 34600 23880 50 0000 C CNN +F 1 "270" H 34600 23700 50 0000 C CNN +F 2 "" H 34600 23730 30 0000 C CNN +F 3 "" V 34600 23800 30 0000 C CNN + 1 34550 23750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q84 +U 1 1 668B1C7C +P 34400 24650 +F 0 "Q84" H 34300 24700 50 0000 R CNN +F 1 "eSim_PNP" H 34350 24800 50 0000 R CNN +F 2 "" H 34600 24750 29 0000 C CNN +F 3 "" H 34400 24650 60 0000 C CNN + 1 34400 24650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q86 +U 1 1 668B1C82 +P 34800 24650 +F 0 "Q86" H 34700 24700 50 0000 R CNN +F 1 "eSim_PNP" H 34750 24800 50 0000 R CNN +F 2 "" H 35000 24750 29 0000 C CNN +F 3 "" H 34800 24650 60 0000 C CNN + 1 34800 24650 + 1 0 0 1 +$EndComp +$Comp +L resistor R38 +U 1 1 668B1C88 +P 35200 23300 +F 0 "R38" H 35250 23430 50 0000 C CNN +F 1 "64" H 35250 23250 50 0000 C CNN +F 2 "" H 35250 23280 30 0000 C CNN +F 3 "" V 35250 23350 30 0000 C CNN + 1 35200 23300 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q80 +U 1 1 668B1C8E +P 33400 23150 +F 0 "Q80" H 33300 23200 50 0000 R CNN +F 1 "eSim_NPN" H 33350 23300 50 0000 R CNN +F 2 "" H 33600 23250 29 0000 C CNN +F 3 "" H 33400 23150 60 0000 C CNN + 1 33400 23150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q97 +U 1 1 668B1C94 +P 38800 21350 +F 0 "Q97" H 38700 21400 50 0000 R CNN +F 1 "eSim_PNP" H 38750 21500 50 0000 R CNN +F 2 "" H 39000 21450 29 0000 C CNN +F 3 "" H 38800 21350 60 0000 C CNN + 1 38800 21350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q96 +U 1 1 668B1C9A +P 38650 22250 +F 0 "Q96" H 38550 22300 50 0000 R CNN +F 1 "eSim_PNP" H 38600 22400 50 0000 R CNN +F 2 "" H 38850 22350 29 0000 C CNN +F 3 "" H 38650 22250 60 0000 C CNN + 1 38650 22250 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q99 +U 1 1 668B1CA0 +P 39050 22250 +F 0 "Q99" H 38950 22300 50 0000 R CNN +F 1 "eSim_PNP" H 39000 22400 50 0000 R CNN +F 2 "" H 39250 22350 29 0000 C CNN +F 3 "" H 39050 22250 60 0000 C CNN + 1 39050 22250 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J22 +U 1 1 668B1CA6 +P 38400 23550 +F 0 "J22" H 38300 23600 50 0000 R CNN +F 1 "jfet_p" H 38350 23700 50 0000 R CNN +F 2 "" H 38600 23650 29 0000 C CNN +F 3 "" H 38400 23550 60 0000 C CNN + 1 38400 23550 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J24 +U 1 1 668B1CAC +P 39600 23550 +F 0 "J24" H 39500 23600 50 0000 R CNN +F 1 "jfet_p" H 39550 23700 50 0000 R CNN +F 2 "" H 39800 23650 29 0000 C CNN +F 3 "" H 39600 23550 60 0000 C CNN + 1 39600 23550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q98 +U 1 1 668B1CB2 +P 38800 25000 +F 0 "Q98" H 38700 25050 50 0000 R CNN +F 1 "eSim_NPN" H 38750 25150 50 0000 R CNN +F 2 "" H 39000 25100 29 0000 C CNN +F 3 "" H 38800 25000 60 0000 C CNN + 1 38800 25000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q100 +U 1 1 668B1CB8 +P 39250 25000 +F 0 "Q100" H 39150 25050 50 0000 R CNN +F 1 "eSim_NPN" H 39200 25150 50 0000 R CNN +F 2 "" H 39450 25100 29 0000 C CNN +F 3 "" H 39250 25000 60 0000 C CNN + 1 39250 25000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q95 +U 1 1 668B1CBE +P 38400 25000 +F 0 "Q95" H 38300 25050 50 0000 R CNN +F 1 "eSim_NPN" H 38350 25150 50 0000 R CNN +F 2 "" H 38600 25100 29 0000 C CNN +F 3 "" H 38400 25000 60 0000 C CNN + 1 38400 25000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R40 +U 1 1 668B1CC4 +P 37650 24400 +F 0 "R40" H 37700 24530 50 0000 C CNN +F 1 "3.5k" H 37700 24350 50 0000 C CNN +F 2 "" H 37700 24380 30 0000 C CNN +F 3 "" V 37700 24450 30 0000 C CNN + 1 37650 24400 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q90 +U 1 1 668B1CCA +P 37600 25450 +F 0 "Q90" H 37500 25500 50 0000 R CNN +F 1 "eSim_NPN" H 37550 25600 50 0000 R CNN +F 2 "" H 37800 25550 29 0000 C CNN +F 3 "" H 37600 25450 60 0000 C CNN + 1 37600 25450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q103 +U 1 1 668B1CD0 +P 41500 21650 +F 0 "Q103" H 41400 21700 50 0000 R CNN +F 1 "eSim_NPN" H 41450 21800 50 0000 R CNN +F 2 "" H 41700 21750 29 0000 C CNN +F 3 "" H 41500 21650 60 0000 C CNN + 1 41500 21650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q104 +U 1 1 668B1CD6 +P 41500 22600 +F 0 "Q104" H 41400 22650 50 0000 R CNN +F 1 "eSim_PNP" H 41450 22750 50 0000 R CNN +F 2 "" H 41700 22700 29 0000 C CNN +F 3 "" H 41500 22600 60 0000 C CNN + 1 41500 22600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 668B1CE8 +P 23850 23650 +F 0 "U1" H 23900 23750 30 0000 C CNN +F 1 "PORT" H 23850 23650 30 0000 C CNN +F 2 "" H 23850 23650 60 0000 C CNN +F 3 "" H 23850 23650 60 0000 C CNN + 9 23850 23650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 668B1CEE +P 29750 23650 +F 0 "U1" H 29800 23750 30 0000 C CNN +F 1 "PORT" H 29750 23650 30 0000 C CNN +F 2 "" H 29750 23650 60 0000 C CNN +F 3 "" H 29750 23650 60 0000 C CNN + 10 29750 23650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 668B1CF4 +P 36350 23350 +F 0 "U1" H 36400 23450 30 0000 C CNN +F 1 "PORT" H 36350 23350 30 0000 C CNN +F 2 "" H 36350 23350 60 0000 C CNN +F 3 "" H 36350 23350 60 0000 C CNN + 8 36350 23350 + -1 0 0 1 +$EndComp +Connection ~ 34600 24250 +Wire Wire Line + 34500 24250 34600 24250 +Wire Wire Line + 34600 23950 34600 24300 +Wire Wire Line + 34600 24300 34900 24300 +Connection ~ 30900 24750 +Wire Wire Line + 31350 24750 30900 24750 +Wire Wire Line + 30900 25450 31100 25450 +Connection ~ 31150 24150 +Wire Wire Line + 31150 23250 31150 24150 +Wire Wire Line + 30900 24150 31350 24150 +Connection ~ 27850 21100 +Wire Wire Line + 27400 21100 27850 21100 +Connection ~ 31550 21050 +Wire Wire Line + 31500 21050 31550 21050 +Wire Wire Line + 31500 21150 31500 21050 +Wire Wire Line + 31300 21150 31500 21150 +Wire Wire Line + 31550 20750 31550 21150 +Wire Wire Line + 31550 21150 31750 21150 +Connection ~ 29000 25100 +Wire Wire Line + 30600 25100 29000 25100 +Wire Wire Line + 30600 24400 30600 25100 +Connection ~ 34600 23150 +Wire Wire Line + 33600 23150 34600 23150 +Connection ~ 29150 23650 +Wire Wire Line + 24100 23650 27100 23650 +Connection ~ 26250 23650 +Connection ~ 41600 27250 +Connection ~ 38700 20750 +Connection ~ 40950 21350 +Wire Wire Line + 40950 21350 40950 21650 +Wire Wire Line + 40950 21650 41300 21650 +Connection ~ 41600 22050 +Wire Wire Line + 29500 22550 27950 22550 +Wire Wire Line + 29500 22050 29500 22550 +Wire Wire Line + 41600 22050 29500 22050 +Connection ~ 39350 27250 +Wire Wire Line + 41600 27250 41600 22800 +Connection ~ 39800 22600 +Wire Wire Line + 41300 22600 39800 22600 +Wire Wire Line + 41600 21850 41600 22400 +Connection ~ 39000 21350 +Wire Wire Line + 41600 21350 41600 21450 +Connection ~ 38700 21800 +Wire Wire Line + 39800 21800 38700 21800 +Wire Wire Line + 39800 21800 39800 23550 +Connection ~ 39350 25500 +Wire Wire Line + 39350 25500 38500 25500 +Wire Wire Line + 38500 25500 38500 25200 +Connection ~ 39350 25350 +Wire Wire Line + 38900 25350 39350 25350 +Wire Wire Line + 38900 25200 38900 25350 +Connection ~ 37700 27250 +Wire Wire Line + 39350 27250 39350 25200 +Connection ~ 38200 25000 +Connection ~ 37700 25000 +Connection ~ 37550 24200 +Wire Wire Line + 37550 24000 37550 24200 +Wire Wire Line + 38300 24000 37550 24000 +Wire Wire Line + 38300 23750 38300 24000 +Connection ~ 37700 24200 +Wire Wire Line + 37250 25450 37250 24200 +Wire Wire Line + 37400 25450 37250 25450 +Connection ~ 34700 27250 +Wire Wire Line + 37700 27250 37700 25650 +Wire Wire Line + 37700 24600 37700 25250 +Wire Wire Line + 37700 24200 37700 24300 +Wire Wire Line + 37250 24200 39500 24200 +Wire Wire Line + 39500 24200 39500 23750 +Connection ~ 39250 23550 +Wire Wire Line + 39250 23550 38600 23550 +Connection ~ 39250 22750 +Wire Wire Line + 38950 22750 39250 22750 +Wire Wire Line + 38950 22450 38950 22750 +Connection ~ 39250 23200 +Wire Wire Line + 39250 23200 39500 23200 +Wire Wire Line + 39500 23200 39500 23350 +Connection ~ 39250 24700 +Wire Wire Line + 39250 24700 39250 22250 +Wire Wire Line + 39250 22250 38850 22250 +Connection ~ 38900 24700 +Wire Wire Line + 38900 24800 38900 24700 +Wire Wire Line + 39350 24700 39350 24800 +Wire Wire Line + 38500 24700 39350 24700 +Wire Wire Line + 38500 24800 38500 24700 +Connection ~ 38600 25000 +Wire Wire Line + 37700 25000 39050 25000 +Wire Wire Line + 38300 22900 38300 23350 +Wire Wire Line + 38550 22900 38300 22900 +Wire Wire Line + 38550 22450 38550 22900 +Connection ~ 38700 22000 +Wire Wire Line + 38700 21550 38700 22000 +Wire Wire Line + 38950 22000 38950 22050 +Wire Wire Line + 38550 22000 38950 22000 +Wire Wire Line + 38550 22050 38550 22000 +Connection ~ 31450 21400 +Wire Wire Line + 31900 21400 31900 21350 +Wire Wire Line + 31900 21350 41600 21350 +Connection ~ 34550 20750 +Connection ~ 31000 21400 +Wire Wire Line + 28150 21350 28150 21400 +Connection ~ 35700 23350 +Wire Wire Line + 35700 23550 35700 23350 +Wire Wire Line + 33300 23550 35700 23550 +Wire Wire Line + 33300 23350 33300 23550 +Connection ~ 33300 22550 +Wire Wire Line + 33300 22950 33300 22550 +Connection ~ 31950 24050 +Wire Wire Line + 31950 23000 31950 24050 +Connection ~ 34000 22550 +Connection ~ 31950 22550 +Wire Wire Line + 35300 23350 36100 23350 +Connection ~ 34600 23350 +Wire Wire Line + 34600 23350 35000 23350 +Connection ~ 34700 24900 +Connection ~ 31100 27250 +Wire Wire Line + 34700 27250 34700 24900 +Connection ~ 34200 24650 +Connection ~ 31150 24050 +Wire Wire Line + 31150 24050 33750 24050 +Wire Wire Line + 33750 24050 33750 24650 +Wire Wire Line + 34900 24900 34900 24850 +Wire Wire Line + 34500 24900 34900 24900 +Wire Wire Line + 34500 24850 34500 24900 +Wire Wire Line + 34900 24300 34900 24450 +Wire Wire Line + 34500 24250 34500 24450 +Wire Wire Line + 33750 24650 34600 24650 +Connection ~ 34600 22850 +Wire Wire Line + 34600 22850 34600 23650 +Wire Wire Line + 34800 22850 34800 22750 +Wire Wire Line + 34300 22850 34800 22850 +Wire Wire Line + 34300 22750 34300 22850 +Connection ~ 34550 22250 +Connection ~ 31550 20750 +Wire Wire Line + 34550 20750 34550 22250 +Wire Wire Line + 34800 22250 34800 22350 +Wire Wire Line + 34300 22250 34800 22250 +Wire Wire Line + 34300 22350 34300 22250 +Wire Wire Line + 31950 22550 34500 22550 +Connection ~ 31100 25850 +Wire Wire Line + 29300 25850 31100 25850 +Connection ~ 29000 27250 +Wire Wire Line + 31100 27250 31100 26450 +Wire Wire Line + 31100 25450 31100 26150 +Connection ~ 28400 27250 +Wire Wire Line + 29000 27250 29000 26050 +Connection ~ 31150 23900 +Wire Wire Line + 29750 23900 31150 23900 +Wire Wire Line + 29750 24650 29750 23900 +Wire Wire Line + 29550 24650 29750 24650 +Connection ~ 29000 24650 +Wire Wire Line + 29000 24650 29000 25650 +Connection ~ 28400 24650 +Wire Wire Line + 28400 24650 29250 24650 +Wire Wire Line + 31050 24400 30600 24400 +Wire Wire Line + 31350 24750 31350 24600 +Wire Wire Line + 30900 24600 30900 25450 +Connection ~ 31150 22800 +Wire Wire Line + 31650 22800 31150 22800 +Wire Wire Line + 31950 22350 31950 22600 +Wire Wire Line + 31150 22600 31150 22950 +Wire Wire Line + 31350 24150 31350 24200 +Wire Wire Line + 30900 24200 30900 24150 +Connection ~ 31150 21950 +Wire Wire Line + 30700 22400 30700 21950 +Wire Wire Line + 30850 22400 30700 22400 +Connection ~ 31500 21700 +Connection ~ 31500 21950 +Wire Wire Line + 31500 21950 31500 21700 +Wire Wire Line + 31750 21700 31750 21600 +Wire Wire Line + 31300 21700 31750 21700 +Wire Wire Line + 31300 21600 31300 21700 +Wire Wire Line + 31950 21950 31950 22050 +Wire Wire Line + 30700 21950 31950 21950 +Wire Wire Line + 31150 22200 31150 21950 +Wire Wire Line + 28400 27250 28400 26750 +Wire Wire Line + 26900 27250 43700 27250 +Wire Wire Line + 26900 26750 26900 27250 +Wire Wire Line + 28400 25550 28400 26450 +Wire Wire Line + 26900 25550 26900 26450 +Connection ~ 26900 24700 +Connection ~ 27650 25350 +Wire Wire Line + 27650 24700 27650 25350 +Wire Wire Line + 26900 24700 27650 24700 +Wire Wire Line + 27200 25350 28100 25350 +Connection ~ 26900 23950 +Wire Wire Line + 26900 23950 26900 25150 +Connection ~ 28400 24000 +Wire Wire Line + 28400 24000 28400 25150 +Wire Wire Line + 28850 24000 28850 23850 +Wire Wire Line + 28200 24000 28850 24000 +Wire Wire Line + 28200 23850 28200 24000 +Wire Wire Line + 27400 23950 27400 23850 +Wire Wire Line + 26550 23950 27400 23950 +Wire Wire Line + 26550 23850 26550 23950 +Connection ~ 27650 23350 +Wire Wire Line + 27650 23350 27650 22750 +Wire Wire Line + 28850 23350 28850 23450 +Connection ~ 27400 23350 +Connection ~ 28200 23350 +Wire Wire Line + 28200 23350 28200 23450 +Wire Wire Line + 26550 23350 26550 23450 +Wire Wire Line + 26550 23350 28850 23350 +Wire Wire Line + 27400 23350 27400 23450 +Wire Wire Line + 28500 23650 29500 23650 +Connection ~ 27650 21600 +Wire Wire Line + 27650 22350 27650 21600 +Wire Wire Line + 27850 21600 27850 21550 +Wire Wire Line + 27400 21600 27850 21600 +Wire Wire Line + 27400 21550 27400 21600 +Wire Wire Line + 27850 20750 39300 20750 +Wire Wire Line + 31300 21150 31300 21200 +Wire Wire Line + 31750 21150 31750 21200 +Wire Wire Line + 28150 21400 31900 21400 +Wire Wire Line + 27850 20750 27850 21150 +Wire Wire Line + 27400 21150 27400 21100 +Wire Wire Line + 27700 21350 28150 21350 +Wire Wire Line + 39300 20750 39300 17000 +Wire Wire Line + 38700 21150 38700 20750 +Wire Wire Line + 43700 27250 43700 14550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.sub b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sub new file mode 100644 index 00000000..28e70962 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sub @@ -0,0 +1,173 @@ +* Subcircuit TL064_IC +.subckt TL064_IC net-_q25-pad3_ net-_j1-pad2_ net-_j5-pad2_ net-_q15-pad3_ net-_j7-pad2_ net-_j3-pad2_ net-_q27-pad3_ net-_q80-pad3_ net-_j15-pad2_ net-_j19-pad2_ net-_q10-pad3_ net-_j16-pad2_ net-_j13-pad2_ net-_q77-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\tl064_ic\tl064_ic.cir +.include PJF.lib +.include NPN.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q4 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q17 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q3 net-_j1-pad1_ net-_q3-pad2_ net-_q2-pad1_ Q2N2907A +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j5 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +j6 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +q1 net-_j1-pad3_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_j1-pad3_ net-_q6-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q10-pad3_ 34 +r5 net-_q6-pad3_ net-_q10-pad3_ 35 +q14 net-_q14-pad1_ net-_q14-pad1_ net-_q14-pad3_ Q2N2222 +r9 net-_q14-pad1_ net-_q19-pad1_ 220 +r8 net-_q14-pad3_ net-_c1-pad1_ 45k +q13 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q16 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q19 net-_q19-pad1_ net-_q14-pad3_ net-_c1-pad1_ Q2N2222 +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +r7 net-_q10-pad2_ net-_q10-pad3_ 7 +q26 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +q29 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +r15 net-_q25-pad2_ net-_q28-pad3_ 270 +q28 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +q30 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +r16 net-_q25-pad3_ net-_q25-pad2_ 64 +q25 net-_q19-pad1_ net-_q25-pad2_ net-_q25-pad3_ Q2N2222 +q39 net-_j11-pad2_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q38 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +q41 net-_j11-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +j9 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad3_ J2N3820 +j11 net-_j11-pad1_ net-_j11-pad2_ net-_j11-pad3_ J2N3820 +q40 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q42 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q36 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +r19 net-_j11-pad3_ net-_q35-pad1_ 3.5k +q35 net-_q35-pad1_ net-_j11-pad3_ net-_q10-pad3_ Q2N2222 +q49 net-_q15-pad2_ net-_q15-pad2_ net-_q3-pad2_ Q2N2222 +q50 net-_q10-pad3_ net-_j11-pad2_ net-_q3-pad2_ Q2N2907A +q7 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q9 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q21 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q23 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q8 net-_j3-pad1_ net-_q51-pad3_ net-_q7-pad1_ Q2N2907A +j4 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j3 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j7 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +j8 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +q5 net-_j3-pad3_ net-_j3-pad3_ net-_q5-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_j3-pad3_ net-_q11-pad3_ Q2N2222 +r4 net-_q5-pad3_ net-_q10-pad3_ 34 +r6 net-_q11-pad3_ net-_q10-pad3_ 35 +q20 net-_q20-pad1_ net-_q20-pad1_ net-_q20-pad3_ Q2N2222 +r12 net-_q20-pad1_ net-_q24-pad1_ 220 +r11 net-_q20-pad3_ net-_c2-pad1_ 45k +q18 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q22 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q24 net-_q24-pad1_ net-_q20-pad3_ net-_c2-pad1_ Q2N2222 +q12 net-_c2-pad2_ net-_q12-pad2_ net-_q10-pad3_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +r10 net-_q12-pad2_ net-_q10-pad3_ 7 +q31 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +q33 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +r17 net-_q27-pad2_ net-_q32-pad3_ 270 +q32 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +q34 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +r18 net-_q27-pad3_ net-_q27-pad2_ 64 +q27 net-_q24-pad1_ net-_q27-pad2_ net-_q27-pad3_ Q2N2222 +q45 net-_j12-pad2_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q44 net-_j10-pad1_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +q47 net-_j10-pad2_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +j10 net-_j10-pad1_ net-_j10-pad2_ net-_j10-pad3_ J2N3820 +j12 net-_j10-pad2_ net-_j12-pad2_ net-_j10-pad3_ J2N3820 +q46 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q48 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q43 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +r20 net-_j10-pad3_ net-_q37-pad1_ 3.5k +q37 net-_q37-pad1_ net-_j10-pad3_ net-_q10-pad3_ Q2N2222 +q51 net-_q21-pad2_ net-_q21-pad2_ net-_q51-pad3_ Q2N2222 +q52 net-_q10-pad3_ net-_j12-pad2_ net-_q51-pad3_ Q2N2907A +q54 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q56 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q67 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q69 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q55 net-_j13-pad1_ net-_q101-pad3_ net-_q54-pad1_ Q2N2907A +j14 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j13 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j16 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +j18 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +q53 net-_j13-pad3_ net-_j13-pad3_ net-_q53-pad3_ Q2N2222 +q58 net-_c3-pad2_ net-_j13-pad3_ net-_q58-pad3_ Q2N2222 +r23 net-_q53-pad3_ net-_q10-pad3_ 34 +r25 net-_q58-pad3_ net-_q10-pad3_ 35 +q66 net-_q66-pad1_ net-_q66-pad1_ net-_q66-pad3_ Q2N2222 +r29 net-_q66-pad1_ net-_q70-pad1_ 220 +r28 net-_q66-pad3_ net-_c3-pad1_ 45k +q65 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q68 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q70 net-_q70-pad1_ net-_q66-pad3_ net-_c3-pad1_ Q2N2222 +q62 net-_c3-pad2_ net-_q62-pad2_ net-_q10-pad3_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +r27 net-_q62-pad2_ net-_q10-pad3_ 7 +q78 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +q81 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +r34 net-_q77-pad2_ net-_q79-pad3_ 270 +q79 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +q82 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +r36 net-_q77-pad3_ net-_q77-pad2_ 64 +q77 net-_q70-pad1_ net-_q77-pad2_ net-_q77-pad3_ Q2N2222 +q91 net-_j23-pad2_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q89 net-_j21-pad1_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +q93 net-_j21-pad2_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +j21 net-_j21-pad1_ net-_j21-pad2_ net-_j21-pad3_ J2N3820 +j23 net-_j21-pad2_ net-_j23-pad2_ net-_j21-pad3_ J2N3820 +q92 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q94 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q88 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +r39 net-_j21-pad3_ net-_q87-pad1_ 3.5k +q87 net-_q87-pad1_ net-_j21-pad3_ net-_q10-pad3_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad1_ net-_q101-pad3_ Q2N2222 +q102 net-_q10-pad3_ net-_j23-pad2_ net-_q101-pad3_ Q2N2907A +q59 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q61 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q73 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q75 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q60 net-_j15-pad1_ net-_q103-pad3_ net-_q59-pad1_ Q2N2907A +j17 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j15 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j19 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +j20 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +q57 net-_j15-pad3_ net-_j15-pad3_ net-_q57-pad3_ Q2N2222 +q63 net-_c4-pad2_ net-_j15-pad3_ net-_q63-pad3_ Q2N2222 +r24 net-_q57-pad3_ net-_q10-pad3_ 34 +r26 net-_q63-pad3_ net-_q10-pad3_ 35 +q72 net-_q72-pad1_ net-_q72-pad1_ net-_q72-pad3_ Q2N2222 +r32 net-_q72-pad1_ net-_q76-pad1_ 220 +r31 net-_q72-pad3_ net-_c4-pad1_ 45k +q71 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q74 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q76 net-_q76-pad1_ net-_q72-pad3_ net-_c4-pad1_ Q2N2222 +q64 net-_c4-pad2_ net-_q64-pad2_ net-_q10-pad3_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +r30 net-_q64-pad2_ net-_q10-pad3_ 7 +q83 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +q85 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +r37 net-_q80-pad2_ net-_q84-pad3_ 270 +q84 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +q86 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +r38 net-_q80-pad3_ net-_q80-pad2_ 64 +q80 net-_q76-pad1_ net-_q80-pad2_ net-_q80-pad3_ Q2N2222 +q97 net-_j24-pad2_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q96 net-_j22-pad1_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +q99 net-_j22-pad2_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +j22 net-_j22-pad1_ net-_j22-pad2_ net-_j22-pad3_ J2N3820 +j24 net-_j22-pad2_ net-_j24-pad2_ net-_j22-pad3_ J2N3820 +q98 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q100 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q95 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +r40 net-_j22-pad3_ net-_q100-pad2_ 3.5k +q90 net-_q100-pad2_ net-_j22-pad3_ net-_q10-pad3_ Q2N2222 +q103 net-_q103-pad1_ net-_q103-pad1_ net-_q103-pad3_ Q2N2222 +q104 net-_q10-pad3_ net-_j24-pad2_ net-_q103-pad3_ Q2N2907A +* Control Statements + +.ends TL064_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC_Previous_Values.xml b/library/SubcircuitLibrary/TL064_sub/TL064_IC_Previous_Values.xml new file mode 100644 index 00000000..91ee9448 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j2><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j1><j5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j5><j6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j6><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q26><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q26><q29><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q29><q28><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q28><q30><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q30><q25><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q39><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q39><q38><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q38><q41><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q41><j9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j9><j11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j11><q40><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q40><q42><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q42><q36><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q36><q35><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q35><q49><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q49><q50><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q50><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><j4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j4><j3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j3><j7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j7><j8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j8><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q31><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q31><q33><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q33><q32><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q32><q34><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q34><q27><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q27><q45><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q45><q44><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q44><q47><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q47><j10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j10><j12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j12><q46><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q46><q48><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q48><q43><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q43><q37><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q37><q51><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q51><q52><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q52><q54><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q54><q56><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q56><q67><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q67><q69><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q69><q55><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q55><j14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j14><j13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j13><j16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j16><j18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j18><q53><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q53><q58><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q58><q66><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q66><q65><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q65><q68><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q68><q70><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q70><q62><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q62><q78><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q78><q81><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q81><q79><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q79><q82><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q82><q77><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q77><q91><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q91><q89><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q89><q93><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q93><j21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j21><j23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j23><q92><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q92><q94><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q94><q88><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q88><q87><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q87><q101><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q101><q102><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q102><q59><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q59><q61><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q61><q73><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q73><q75><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q75><q60><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q60><j17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j17><j15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j15><j19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j19><j20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j20><q57><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q57><q63><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q63><q72><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q72><q71><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q71><q74><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q74><q76><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q76><q64><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q64><q83><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q83><q85><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q85><q84><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q84><q86><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q86><q80><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q80><q97><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q97><q96><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q96><q99><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q99><j22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j22><j24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j24><q98><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q98><q100><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q100><q95><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q95><q90><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q90><q103><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q103><q104><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q104></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL064_sub/analysis b/library/SubcircuitLibrary/TL064_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL331_sub/D.lib b/library/SubcircuitLibrary/TL331_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/TL331_sub/NPN.lib b/library/SubcircuitLibrary/TL331_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TL331_sub/PNP.lib b/library/SubcircuitLibrary/TL331_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TL331_sub/TL331-cache.lib b/library/SubcircuitLibrary/TL331_sub/TL331-cache.lib new file mode 100644 index 00000000..da24d97c --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331-cache.lib @@ -0,0 +1,160 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.cir b/library/SubcircuitLibrary/TL331_sub/TL331.cir new file mode 100644 index 00000000..83280b33 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.cir @@ -0,0 +1,28 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\TL331\TL331.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/24 00:57:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +D2 Net-_D2-Pad1_ Net-_D1-Pad2_ 10u +I2 Net-_I1-Pad1_ Net-_I2-Pad2_ 80u +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ 10u +Q2 Net-_Q2-Pad1_ Net-_D1-Pad2_ Net-_I2-Pad2_ eSim_PNP +Q5 Net-_Q4-Pad1_ Net-_D3-Pad2_ Net-_I2-Pad2_ eSim_PNP +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q1 GND Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_PNP +D4 Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q6 GND Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_PNP +I4 Net-_I1-Pad1_ Net-_I4-Pad2_ 80u +Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q7 Net-_I4-Pad2_ Net-_Q4-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_I4-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R1 Net-_I1-Pad1_ Net-_Q8-Pad1_ 300 +I1 Net-_I1-Pad1_ Net-_D2-Pad1_ 80u +I3 Net-_I1-Pad1_ Net-_D3-Pad1_ 80u +U1 Net-_D1-Pad1_ Net-_D4-Pad1_ Net-_Q3-Pad3_ Net-_I1-Pad1_ Net-_Q8-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.cir.out b/library/SubcircuitLibrary/TL331_sub/TL331.cir.out new file mode 100644 index 00000000..c83f3e00 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.cir.out @@ -0,0 +1,32 @@ +* d:\fossee\esim\library\subcircuitlibrary\tl331\tl331.cir + +.include PNP.lib +.include NPN.lib +.include D.lib +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +q5 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 gnd net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 gnd net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +i4 net-_i1-pad1_ net-_i4-pad2_ 80u +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q3-pad3_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_i1-pad1_ net-_q8-pad1_ 300 +i1 net-_i1-pad1_ net-_d2-pad1_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 80u +* u1 net-_d1-pad1_ net-_d4-pad1_ net-_q3-pad3_ net-_i1-pad1_ net-_q8-pad1_ port +.tran 0e-00 0e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.pro b/library/SubcircuitLibrary/TL331_sub/TL331.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.sch b/library/SubcircuitLibrary/TL331_sub/TL331.sch new file mode 100644 index 00000000..118b584f --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.sch @@ -0,0 +1,417 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:TL331-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_Diode D2 +U 1 1 6668A495 +P 4700 2900 +F 0 "D2" H 4700 3000 50 0000 C CNN +F 1 "10u" H 4700 2800 50 0000 C CIN +F 2 "" H 4700 2900 60 0000 C CNN +F 3 "" H 4700 2900 60 0000 C CNN + 1 4700 2900 + 0 1 1 0 +$EndComp +$Comp +L dc I2 +U 1 1 6668A496 +P 5900 2050 +F 0 "I2" H 5700 2150 60 0000 C CNN +F 1 "80u" H 5700 2000 60 0000 C CNN +F 2 "R1" H 5600 2050 60 0000 C CNN +F 3 "" H 5900 2050 60 0000 C CNN + 1 5900 2050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6668A497 +P 6900 2800 +F 0 "D3" H 6900 2900 50 0000 C CNN +F 1 "10u" H 6900 2700 50 0000 C CNN +F 2 "" H 6900 2800 60 0000 C CNN +F 3 "" H 6900 2800 60 0000 C CNN + 1 6900 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 6668A498 +P 5300 3100 +F 0 "Q2" H 5200 3150 50 0000 R CNN +F 1 "eSim_PNP" H 5250 3250 50 0000 R CNN +F 2 "" H 5500 3200 29 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 1 5300 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 6668A499 +P 6500 3100 +F 0 "Q5" H 6400 3150 50 0000 R CNN +F 1 "eSim_PNP" H 6450 3250 50 0000 R CNN +F 2 "" H 6700 3200 29 0000 C CNN +F 3 "" H 6500 3100 60 0000 C CNN + 1 6500 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6668A49A +P 4200 3100 +F 0 "D1" H 4200 3200 50 0000 C CNN +F 1 "eSim_Diode" H 4200 3000 50 0000 C CNN +F 2 "" H 4200 3100 60 0000 C CNN +F 3 "" H 4200 3100 60 0000 C CNN + 1 4200 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 6668A49B +P 4600 3450 +F 0 "Q1" H 4500 3500 50 0000 R CNN +F 1 "eSim_PNP" H 4550 3600 50 0000 R CNN +F 2 "" H 4800 3550 29 0000 C CNN +F 3 "" H 4600 3450 60 0000 C CNN + 1 4600 3450 + 1 0 0 1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 6668A49C +P 4700 3950 +F 0 "#PWR1" H 4700 3700 50 0001 C CNN +F 1 "GND" H 4700 3800 50 0000 C CNN +F 2 "" H 4700 3950 50 0001 C CNN +F 3 "" H 4700 3950 50 0001 C CNN + 1 4700 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6668A49D +P 7400 3100 +F 0 "D4" H 7400 3200 50 0000 C CNN +F 1 "eSim_Diode" H 7400 3000 50 0000 C CNN +F 2 "" H 7400 3100 60 0000 C CNN +F 3 "" H 7400 3100 60 0000 C CNN + 1 7400 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6668A49E +P 7000 3500 +F 0 "Q6" H 6900 3550 50 0000 R CNN +F 1 "eSim_PNP" H 6950 3650 50 0000 R CNN +F 2 "" H 7200 3600 29 0000 C CNN +F 3 "" H 7000 3500 60 0000 C CNN + 1 7000 3500 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR2 +U 1 1 6668A4A1 +P 6900 4000 +F 0 "#PWR2" H 6900 3750 50 0001 C CNN +F 1 "GND" H 6900 3850 50 0000 C CNN +F 2 "" H 6900 4000 50 0001 C CNN +F 3 "" H 6900 4000 50 0001 C CNN + 1 6900 4000 + 1 0 0 -1 +$EndComp +$Comp +L dc I4 +U 1 1 6668A4A2 +P 8600 2550 +F 0 "I4" H 8400 2650 60 0000 C CNN +F 1 "80u" H 8400 2500 60 0000 C CNN +F 2 "R1" H 8300 2550 60 0000 C CNN +F 3 "" H 8600 2550 60 0000 C CNN + 1 8600 2550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6668A4A3 +P 5500 5500 +F 0 "Q3" H 5400 5550 50 0000 R CNN +F 1 "eSim_NPN" H 5450 5650 50 0000 R CNN +F 2 "" H 5700 5600 29 0000 C CNN +F 3 "" H 5500 5500 60 0000 C CNN + 1 5500 5500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6668A4A4 +P 6300 5500 +F 0 "Q4" H 6200 5550 50 0000 R CNN +F 1 "eSim_NPN" H 6250 5650 50 0000 R CNN +F 2 "" H 6500 5600 29 0000 C CNN +F 3 "" H 6300 5500 60 0000 C CNN + 1 6300 5500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6668A4A5 +P 8300 4900 +F 0 "Q7" H 8200 4950 50 0000 R CNN +F 1 "eSim_NPN" H 8250 5050 50 0000 R CNN +F 2 "" H 8500 5000 29 0000 C CNN +F 3 "" H 8300 4900 60 0000 C CNN + 1 8300 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 6668A4A6 +P 9000 4200 +F 0 "Q8" H 8900 4250 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4350 50 0000 R CNN +F 2 "" H 9200 4300 29 0000 C CNN +F 3 "" H 9000 4200 60 0000 C CNN + 1 9000 4200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 6668A4AE +P 9150 3000 +F 0 "R1" H 9200 3130 50 0000 C CNN +F 1 "300" H 9200 2950 50 0000 C CNN +F 2 "" H 9200 2980 30 0000 C CNN +F 3 "" V 9200 3050 30 0000 C CNN + 1 9150 3000 + 0 1 1 0 +$EndComp +Wire Wire Line + 5400 2900 6400 2900 +Wire Wire Line + 5900 2500 5900 2900 +Connection ~ 5900 2900 +Wire Wire Line + 4350 3100 5100 3100 +Wire Wire Line + 4700 3050 4700 3250 +Connection ~ 4700 3100 +Wire Wire Line + 4050 3450 4050 3100 +Connection ~ 4050 3450 +Wire Wire Line + 4700 3650 4700 3950 +Wire Wire Line + 7550 3100 7650 3100 +Wire Wire Line + 7650 3100 7650 4800 +Wire Wire Line + 7200 3500 7650 3500 +Connection ~ 7650 3500 +Wire Wire Line + 6900 3700 6900 4000 +Wire Wire Line + 5400 3300 5400 5300 +Wire Wire Line + 6400 3300 6400 5300 +Wire Wire Line + 5700 5500 6100 5500 +Wire Wire Line + 5400 5000 5900 5000 +Wire Wire Line + 5900 5000 5900 5500 +Connection ~ 5900 5500 +Connection ~ 5400 5000 +Wire Wire Line + 8600 4700 8400 4700 +Wire Wire Line + 8800 4200 8600 4200 +Connection ~ 8600 4200 +Wire Wire Line + 8100 4900 6400 4900 +Connection ~ 6400 4900 +Wire Wire Line + 9100 5800 9100 4400 +Wire Wire Line + 8400 5800 8400 5100 +Connection ~ 8600 1600 +Wire Wire Line + 8600 1600 8600 2100 +Wire Wire Line + 8600 3000 8600 4700 +Wire Wire Line + 5400 5700 5400 5800 +Wire Wire Line + 5400 5800 9400 5800 +Connection ~ 9100 5800 +Connection ~ 8400 5800 +Wire Wire Line + 6400 5700 6400 5800 +Connection ~ 6400 5800 +Wire Wire Line + 3800 3450 4400 3450 +Wire Wire Line + 9200 3200 9200 4000 +Connection ~ 9200 4000 +Wire Wire Line + 9200 1600 9200 2900 +Connection ~ 9200 1600 +Wire Wire Line + 4700 2500 4700 2750 +$Comp +L dc I1 +U 1 1 6668A4AF +P 4950 2050 +F 0 "I1" H 4750 2150 60 0000 C CNN +F 1 "80u" H 4750 2000 60 0000 C CNN +F 2 "R1" H 4650 2050 60 0000 C CNN +F 3 "" H 4950 2050 60 0000 C CNN + 1 4950 2050 + -1 0 0 -1 +$EndComp +Connection ~ 5900 1600 +Wire Wire Line + 4950 2500 4700 2500 +$Comp +L dc I3 +U 1 1 6668A4B0 +P 6900 2100 +F 0 "I3" H 6700 2200 60 0000 C CNN +F 1 "80u" H 6700 2050 60 0000 C CNN +F 2 "R1" H 6600 2100 60 0000 C CNN +F 3 "" H 6900 2100 60 0000 C CNN + 1 6900 2100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6900 1600 6900 1650 +Connection ~ 6900 1600 +Wire Wire Line + 6900 2650 6900 2550 +Wire Wire Line + 6900 3100 6700 3100 +Wire Wire Line + 6900 2950 6900 3300 +Connection ~ 6900 3100 +Wire Wire Line + 7250 3100 7250 3000 +Wire Wire Line + 7250 3000 6900 3000 +Connection ~ 6900 3000 +Wire Wire Line + 4950 1600 9550 1600 +$Comp +L PORT U1 +U 1 1 6668A70E +P 3550 3450 +F 0 "U1" H 3600 3550 30 0000 C CNN +F 1 "PORT" H 3550 3450 30 0000 C CNN +F 2 "" H 3550 3450 60 0000 C CNN +F 3 "" H 3550 3450 60 0000 C CNN + 1 3550 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6668AEAF +P 9650 5800 +F 0 "U1" H 9700 5900 30 0000 C CNN +F 1 "PORT" H 9650 5800 30 0000 C CNN +F 2 "" H 9650 5800 60 0000 C CNN +F 3 "" H 9650 5800 60 0000 C CNN + 3 9650 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 6668B053 +P 3600 4800 +F 0 "U1" H 3650 4900 30 0000 C CNN +F 1 "PORT" H 3600 4800 30 0000 C CNN +F 2 "" H 3600 4800 60 0000 C CNN +F 3 "" H 3600 4800 60 0000 C CNN + 2 3600 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7650 4800 3850 4800 +$Comp +L PORT U1 +U 4 1 6668B3C5 +P 9800 1600 +F 0 "U1" H 9850 1700 30 0000 C CNN +F 1 "PORT" H 9800 1600 30 0000 C CNN +F 2 "" H 9800 1600 60 0000 C CNN +F 3 "" H 9800 1600 60 0000 C CNN + 4 9800 1600 + -1 0 0 1 +$EndComp +Wire Wire Line + 9100 4000 9700 4000 +$Comp +L PORT U1 +U 5 1 6668B51E +P 9950 4000 +F 0 "U1" H 10000 4100 30 0000 C CNN +F 1 "PORT" H 9950 4000 30 0000 C CNN +F 2 "" H 9950 4000 60 0000 C CNN +F 3 "" H 9950 4000 60 0000 C CNN + 5 9950 4000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.sub b/library/SubcircuitLibrary/TL331_sub/TL331.sub new file mode 100644 index 00000000..32456e21 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.sub @@ -0,0 +1,26 @@ +* Subcircuit TL331 +.subckt TL331 net-_d1-pad1_ net-_d4-pad1_ net-_q3-pad3_ net-_i1-pad1_ net-_q8-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\tl331\tl331.cir +.include PNP.lib +.include NPN.lib +.include D.lib +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +q5 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 gnd net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 gnd net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +i4 net-_i1-pad1_ net-_i4-pad2_ 80u +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q3-pad3_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_i1-pad1_ net-_q8-pad1_ 300 +i1 net-_i1-pad1_ net-_d2-pad1_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 80u +* Control Statements + +.ends TL331
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL331_sub/TL331_Previous_Values.xml b/library/SubcircuitLibrary/TL331_sub/TL331_Previous_Values.xml new file mode 100644 index 00000000..a8bf8200 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i2 name="Source type">80u</i2><i4 name="Source type">80u</i4><i1 name="Source type">80u</i1><i3 name="Source type">80u</i3></source><model /><devicemodel><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><d4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">ns</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL331_sub/analysis b/library/SubcircuitLibrary/TL331_sub/analysis new file mode 100644 index 00000000..657c34c3 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-09 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TS391_sub/D.lib b/library/SubcircuitLibrary/TS391_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/TS391_sub/NPN.lib b/library/SubcircuitLibrary/TS391_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TS391_sub/PNP.lib b/library/SubcircuitLibrary/TS391_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC-cache.lib b/library/SubcircuitLibrary/TS391_sub/TS391_IC-cache.lib new file mode 100644 index 00000000..4e32f85d --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir new file mode 100644 index 00000000..80ee839f --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir @@ -0,0 +1,29 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\TS391_IC\TS391_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/24 20:07:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +I1 Net-_I1-Pad1_ Net-_D2-Pad1_ 3.5u +I2 Net-_I1-Pad1_ Net-_I2-Pad2_ 100u +I3 Net-_I1-Pad1_ Net-_D3-Pad1_ 3.5u +I4 Net-_I1-Pad1_ Net-_I4-Pad2_ 100u +D2 Net-_D2-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q4 Net-_Q4-Pad1_ Net-_D3-Pad2_ Net-_I2-Pad2_ eSim_PNP +Q2 Net-_Q2-Pad1_ Net-_D1-Pad2_ Net-_I2-Pad2_ eSim_PNP +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q1 Net-_Q1-Pad1_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q5 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q6 Net-_Q1-Pad1_ Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_PNP +Q7 Net-_I4-Pad2_ Net-_Q4-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_I4-Pad2_ Net-_Q1-Pad1_ eSim_NPN +R2 Net-_I1-Pad1_ Net-_Q8-Pad1_ 3.5k +R1 Net-_R1-Pad1_ Net-_D4-Pad1_ 1k +U1 Net-_Q8-Pad1_ Net-_Q1-Pad1_ Net-_R1-Pad1_ Net-_D1-Pad1_ Net-_I1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir.out b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir.out new file mode 100644 index 00000000..f88d796d --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir.out @@ -0,0 +1,33 @@ +* d:\fossee\esim\library\subcircuitlibrary\ts391_ic\ts391_ic.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +i1 net-_i1-pad1_ net-_d2-pad1_ 3.5u +i2 net-_i1-pad1_ net-_i2-pad2_ 100u +i3 net-_i1-pad1_ net-_d3-pad1_ 3.5u +i4 net-_i1-pad1_ net-_i4-pad2_ 100u +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q5 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_q1-pad1_ net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q1-pad1_ Q2N2222 +r2 net-_i1-pad1_ net-_q8-pad1_ 3.5k +r1 net-_r1-pad1_ net-_d4-pad1_ 1k +* u1 net-_q8-pad1_ net-_q1-pad1_ net-_r1-pad1_ net-_d1-pad1_ net-_i1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.pro b/library/SubcircuitLibrary/TS391_sub/TS391_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.sch b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sch new file mode 100644 index 00000000..ff55972c --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sch @@ -0,0 +1,451 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:TS391-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dc I1 +U 1 1 6676E0A1 +P 3550 1900 +F 0 "I1" H 3350 2000 60 0000 C CNN +F 1 "3.5u" H 3350 1850 60 0000 C CNN +F 2 "R1" H 3250 1900 60 0000 C CNN +F 3 "" H 3550 1900 60 0000 C CNN + 1 3550 1900 + 1 0 0 -1 +$EndComp +$Comp +L dc I2 +U 1 1 6676E0A2 +P 4750 2100 +F 0 "I2" H 4550 2200 60 0000 C CNN +F 1 "100u" H 4550 2050 60 0000 C CNN +F 2 "R1" H 4450 2100 60 0000 C CNN +F 3 "" H 4750 2100 60 0000 C CNN + 1 4750 2100 + 1 0 0 -1 +$EndComp +$Comp +L dc I3 +U 1 1 6676E0A3 +P 5750 1900 +F 0 "I3" H 5550 2000 60 0000 C CNN +F 1 "3.5u" H 5550 1850 60 0000 C CNN +F 2 "R1" H 5450 1900 60 0000 C CNN +F 3 "" H 5750 1900 60 0000 C CNN + 1 5750 1900 + 1 0 0 -1 +$EndComp +$Comp +L dc I4 +U 1 1 6676E0A4 +P 6850 2100 +F 0 "I4" H 6650 2200 60 0000 C CNN +F 1 "100u" H 6650 2050 60 0000 C CNN +F 2 "R1" H 6550 2100 60 0000 C CNN +F 3 "" H 6850 2100 60 0000 C CNN + 1 6850 2100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6676E0A5 +P 3550 2650 +F 0 "D2" H 3550 2750 50 0000 C CNN +F 1 "eSim_Diode" H 3550 2550 50 0000 C CNN +F 2 "" H 3550 2650 60 0000 C CNN +F 3 "" H 3550 2650 60 0000 C CNN + 1 3550 2650 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 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+$Comp +L PORT U1 +U 2 1 6676E663 +P 7500 4850 +F 0 "U1" H 7550 4950 30 0000 C CNN +F 1 "PORT" H 7500 4850 30 0000 C CNN +F 2 "" H 7500 4850 60 0000 C CNN +F 3 "" H 7500 4850 60 0000 C CNN + 2 7500 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 6676E958 +P 1500 4100 +F 0 "U1" H 1550 4200 30 0000 C CNN +F 1 "PORT" H 1500 4100 30 0000 C CNN +F 2 "" H 1500 4100 60 0000 C CNN +F 3 "" H 1500 4100 60 0000 C CNN + 3 1500 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6676ED45 +P 5400 750 +F 0 "U1" H 5450 850 30 0000 C CNN +F 1 "PORT" H 5400 750 30 0000 C CNN +F 2 "" H 5400 750 60 0000 C CNN +F 3 "" H 5400 750 60 0000 C CNN + 5 5400 750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6676FEAD +P 1850 2900 +F 0 "U1" H 1900 3000 30 0000 C CNN +F 1 "PORT" H 1850 2900 30 0000 C CNN +F 2 "" H 1850 2900 60 0000 C CNN +F 3 "" H 1850 2900 60 0000 C CNN + 4 1850 2900 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.sub b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sub new file mode 100644 index 00000000..fbdbaba2 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sub @@ -0,0 +1,27 @@ +* Subcircuit TS391_IC +.subckt TS391_IC net-_q8-pad1_ net-_q1-pad1_ net-_r1-pad1_ net-_d1-pad1_ net-_i1-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\ts391_ic\ts391_ic.cir +.include NPN.lib +.include PNP.lib +.include D.lib +i1 net-_i1-pad1_ net-_d2-pad1_ 3.5u +i2 net-_i1-pad1_ net-_i2-pad2_ 100u +i3 net-_i1-pad1_ net-_d3-pad1_ 3.5u +i4 net-_i1-pad1_ net-_i4-pad2_ 100u +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q5 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_q1-pad1_ net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q1-pad1_ Q2N2222 +r2 net-_i1-pad1_ net-_q8-pad1_ 3.5k +r1 net-_r1-pad1_ net-_d4-pad1_ 1k +* Control Statements + +.ends TS391_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC_Previous_Values.xml b/library/SubcircuitLibrary/TS391_sub/TS391_IC_Previous_Values.xml new file mode 100644 index 00000000..8353f882 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i1 name="Source type">3.5u</i1><i2 name="Source type">100u</i2><i3 name="Source type">3.5u</i3><i4 name="Source type">100u</i4></source><model /><devicemodel><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TS391_sub/analysis b/library/SubcircuitLibrary/TS391_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |