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* d:\fossee\esim\library\subcircuitlibrary\cd4556bms_ic\cd4556bms_ic.cir
* u3 net-_u2-pad4_ net-_u10-pad1_ d_inverter
* u4 net-_u2-pad5_ net-_u4-pad2_ d_inverter
* u5 net-_u2-pad6_ net-_u16-pad2_ d_inverter
* u6 net-_u10-pad1_ net-_u11-pad1_ d_inverter
* u7 net-_u4-pad2_ net-_u10-pad2_ d_inverter
* u8 net-_u10-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_nand
* u12 net-_u12-pad1_ net-_u12-pad1_ net-_u12-pad3_ d_nand
* u16 net-_u12-pad3_ net-_u16-pad2_ net-_u16-pad3_ d_nand
* u9 net-_u11-pad1_ net-_u4-pad2_ net-_u13-pad1_ d_nand
* u13 net-_u13-pad1_ net-_u13-pad1_ net-_u13-pad3_ d_nand
* u17 net-_u13-pad3_ net-_u16-pad2_ net-_u17-pad3_ d_nand
* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand
* u14 net-_u10-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_nand
* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand
* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nand
* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand
* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand
* u20 net-_u16-pad3_ net-_u20-pad2_ d_inverter
* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter
* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter
* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter
* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3
* u24 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ dac_bridge_4
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
* u26 net-_u25-pad4_ net-_u26-pad2_ d_inverter
* u27 net-_u25-pad5_ net-_u27-pad2_ d_inverter
* u28 net-_u25-pad6_ net-_u28-pad2_ d_inverter
* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter
* u30 net-_u27-pad2_ net-_u30-pad2_ d_inverter
* u31 net-_u26-pad2_ net-_u27-pad2_ net-_u31-pad3_ d_nand
* u35 net-_u31-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_nand
* u39 net-_u35-pad3_ net-_u28-pad2_ net-_u39-pad3_ d_nand
* u32 net-_u29-pad2_ net-_u27-pad2_ net-_u32-pad3_ d_nand
* u36 net-_u32-pad3_ net-_u32-pad3_ net-_u36-pad3_ d_nand
* u40 net-_u36-pad3_ net-_u28-pad2_ net-_u40-pad3_ d_nand
* u33 net-_u26-pad2_ net-_u30-pad2_ net-_u33-pad3_ d_nand
* u37 net-_u33-pad3_ net-_u33-pad3_ net-_u37-pad3_ d_nand
* u41 net-_u37-pad3_ net-_u28-pad2_ net-_u41-pad3_ d_nand
* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_nand
* u38 net-_u34-pad3_ net-_u34-pad3_ net-_u38-pad3_ d_nand
* u42 net-_u38-pad3_ net-_u28-pad2_ net-_u42-pad3_ d_nand
* u43 net-_u39-pad3_ net-_u43-pad2_ d_inverter
* u44 net-_u40-pad3_ net-_u44-pad2_ d_inverter
* u45 net-_u41-pad3_ net-_u45-pad2_ d_inverter
* u46 net-_u42-pad3_ net-_u46-pad2_ d_inverter
* u25 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ adc_bridge_3
* u47 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ dac_bridge_4
a1 net-_u2-pad4_ net-_u10-pad1_ u3
a2 net-_u2-pad5_ net-_u4-pad2_ u4
a3 net-_u2-pad6_ net-_u16-pad2_ u5
a4 net-_u10-pad1_ net-_u11-pad1_ u6
a5 net-_u4-pad2_ net-_u10-pad2_ u7
a6 [net-_u10-pad1_ net-_u4-pad2_ ] net-_u12-pad1_ u8
a7 [net-_u12-pad1_ net-_u12-pad1_ ] net-_u12-pad3_ u12
a8 [net-_u12-pad3_ net-_u16-pad2_ ] net-_u16-pad3_ u16
a9 [net-_u11-pad1_ net-_u4-pad2_ ] net-_u13-pad1_ u9
a10 [net-_u13-pad1_ net-_u13-pad1_ ] net-_u13-pad3_ u13
a11 [net-_u13-pad3_ net-_u16-pad2_ ] net-_u17-pad3_ u17
a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
a13 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14
a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18
a15 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
a16 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15
a17 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19
a18 net-_u16-pad3_ net-_u20-pad2_ u20
a19 net-_u17-pad3_ net-_u21-pad2_ u21
a20 net-_u18-pad3_ net-_u22-pad2_ u22
a21 net-_u19-pad3_ net-_u23-pad2_ u23
a22 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2
a23 [net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] u24
a24 net-_u25-pad4_ net-_u26-pad2_ u26
a25 net-_u25-pad5_ net-_u27-pad2_ u27
a26 net-_u25-pad6_ net-_u28-pad2_ u28
a27 net-_u26-pad2_ net-_u29-pad2_ u29
a28 net-_u27-pad2_ net-_u30-pad2_ u30
a29 [net-_u26-pad2_ net-_u27-pad2_ ] net-_u31-pad3_ u31
a30 [net-_u31-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35
a31 [net-_u35-pad3_ net-_u28-pad2_ ] net-_u39-pad3_ u39
a32 [net-_u29-pad2_ net-_u27-pad2_ ] net-_u32-pad3_ u32
a33 [net-_u32-pad3_ net-_u32-pad3_ ] net-_u36-pad3_ u36
a34 [net-_u36-pad3_ net-_u28-pad2_ ] net-_u40-pad3_ u40
a35 [net-_u26-pad2_ net-_u30-pad2_ ] net-_u33-pad3_ u33
a36 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u37-pad3_ u37
a37 [net-_u37-pad3_ net-_u28-pad2_ ] net-_u41-pad3_ u41
a38 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34
a39 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u38-pad3_ u38
a40 [net-_u38-pad3_ net-_u28-pad2_ ] net-_u42-pad3_ u42
a41 net-_u39-pad3_ net-_u43-pad2_ u43
a42 net-_u40-pad3_ net-_u44-pad2_ u44
a43 net-_u41-pad3_ net-_u45-pad2_ u45
a44 net-_u42-pad3_ net-_u46-pad2_ u46
a45 [net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ ] [net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ ] u25
a46 [net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ ] [net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ ] u47
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge
.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge
.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
.tran 0.01e-03 100e-03 0e-00
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
|
