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| author | Josh Blum | 2009-10-12 12:16:12 -0700 |
|---|---|---|
| committer | Josh Blum | 2009-10-12 12:16:12 -0700 |
| commit | 5b74bb4d34f381fa8a8af1e1d96ea2d673a8be71 (patch) | |
| tree | ad6a9f64e3b610d008b0fb612772efd4162a82aa /usrp2/fpga/testbench/cmdfile | |
| parent | 57e810d3f07909947a9fb2daeb507b439d5f4f50 (diff) | |
| parent | 38d5389f3054164a2f04d6e4e8fe381aa5ee03fc (diff) | |
| download | gnuradio-5b74bb4d34f381fa8a8af1e1d96ea2d673a8be71.tar.gz gnuradio-5b74bb4d34f381fa8a8af1e1d96ea2d673a8be71.tar.bz2 gnuradio-5b74bb4d34f381fa8a8af1e1d96ea2d673a8be71.zip | |
Merge commit '38d5389f3054164a2f04d6e4e8fe381aa5ee03fc' into vrt
Diffstat (limited to 'usrp2/fpga/testbench/cmdfile')
| -rw-r--r-- | usrp2/fpga/testbench/cmdfile | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile index 1063f428e..8083eb92a 100644 --- a/usrp2/fpga/testbench/cmdfile +++ b/usrp2/fpga/testbench/cmdfile @@ -3,11 +3,14 @@ -y . -y ../top/u2_core -y ../control_lib +-y ../control_lib/newfifo -y ../serdes -y ../sdr_lib -y ../timing -y ../coregen -y ../extram +-y ../simple_gemac +-y ../simple_gemac/miim # Models -y ../models @@ -17,24 +20,8 @@ -y ../opencores/8b10b -y ../opencores/spi/rtl/verilog +incdir+../opencores/spi/rtl/verilog --y ../opencores/wb_conbus/rtl/verilog -+incdir+../opencores/wb_conbus/rtl/verilog -y ../opencores/i2c/rtl/verilog +incdir+../opencores/i2c/rtl/verilog -y ../opencores/aemb/rtl/verilog -y ../opencores/simple_pic/rtl -# Ethernet -+incdir+../eth/rtl/verilog --y ../eth/rtl/verilog --y ../eth/rtl/verilog/MAC_tx --y ../eth/rtl/verilog/MAC_rx --y ../eth/rtl/verilog/miim --y ../eth/rtl/verilog/TECH --y ../eth/rtl/verilog/TECH/xilinx --y ../eth/rtl/verilog/RMON --y ../eth --y ../eth/bench/verilog - -# Ethernet Models --y ../eth/bench/verilog |