From 7eea883c377f64862a4d83f1b33a83fdf3cfc392 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Mon, 31 Aug 2009 12:08:30 -0700
Subject: Merged SVN matt/new_eth r10782:11633 into new_eth

* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth
  -r10782:11633

* Patch applied with no conflicts or fuzz.
---
 usrp2/fpga/testbench/cmdfile | 1 +
 1 file changed, 1 insertion(+)

(limited to 'usrp2/fpga/testbench/cmdfile')

diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile
index 1063f428e..ed251665c 100644
--- a/usrp2/fpga/testbench/cmdfile
+++ b/usrp2/fpga/testbench/cmdfile
@@ -3,6 +3,7 @@
 -y .
 -y ../top/u2_core
 -y ../control_lib
+-y ../control_lib/newfifo
 -y ../serdes
 -y ../sdr_lib
 -y ../timing
-- 
cgit 


From 21e931766545ff93dda5ef1b72dd03f3786967ab Mon Sep 17 00:00:00 2001
From: Matt Ettus
Date: Thu, 1 Oct 2009 00:21:24 -0700
Subject: fullchip sim now compiles again, after moving eth and models over to
 new simple_gemac

---
 usrp2/fpga/testbench/cmdfile | 18 ++----------------
 1 file changed, 2 insertions(+), 16 deletions(-)

(limited to 'usrp2/fpga/testbench/cmdfile')

diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile
index ed251665c..8083eb92a 100644
--- a/usrp2/fpga/testbench/cmdfile
+++ b/usrp2/fpga/testbench/cmdfile
@@ -9,6 +9,8 @@
 -y ../timing
 -y ../coregen
 -y ../extram
+-y ../simple_gemac
+-y ../simple_gemac/miim
 
 # Models
 -y ../models
@@ -18,24 +20,8 @@
 -y ../opencores/8b10b
 -y ../opencores/spi/rtl/verilog
 +incdir+../opencores/spi/rtl/verilog
--y ../opencores/wb_conbus/rtl/verilog
-+incdir+../opencores/wb_conbus/rtl/verilog
 -y ../opencores/i2c/rtl/verilog
 +incdir+../opencores/i2c/rtl/verilog
 -y ../opencores/aemb/rtl/verilog
 -y ../opencores/simple_pic/rtl
 
-# Ethernet
-+incdir+../eth/rtl/verilog
--y ../eth/rtl/verilog
--y ../eth/rtl/verilog/MAC_tx
--y ../eth/rtl/verilog/MAC_rx
--y ../eth/rtl/verilog/miim
--y ../eth/rtl/verilog/TECH
--y ../eth/rtl/verilog/TECH/xilinx
--y ../eth/rtl/verilog/RMON
--y ../eth
--y ../eth/bench/verilog
-
-# Ethernet Models
--y ../eth/bench/verilog
-- 
cgit