1 files changed, 3 insertions, 16 deletions
diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile
index 1063f428e..8083eb92a 100644
--- a/usrp2/fpga/testbench/cmdfile
+++ b/usrp2/fpga/testbench/cmdfile
@@ -3,11 +3,14 @@
 -y .
 -y ../top/u2_core
 -y ../control_lib
+-y ../control_lib/newfifo
 -y ../serdes
 -y ../sdr_lib
 -y ../timing
 -y ../coregen
 -y ../extram
+-y ../simple_gemac
+-y ../simple_gemac/miim
 
 # Models
 -y ../models
@@ -17,24 +20,8 @@
 -y ../opencores/8b10b
 -y ../opencores/spi/rtl/verilog
 +incdir+../opencores/spi/rtl/verilog
--y ../opencores/wb_conbus/rtl/verilog
-+incdir+../opencores/wb_conbus/rtl/verilog
 -y ../opencores/i2c/rtl/verilog
 +incdir+../opencores/i2c/rtl/verilog
 -y ../opencores/aemb/rtl/verilog
 -y ../opencores/simple_pic/rtl
 
-# Ethernet
-+incdir+../eth/rtl/verilog
--y ../eth/rtl/verilog
--y ../eth/rtl/verilog/MAC_tx
--y ../eth/rtl/verilog/MAC_rx
--y ../eth/rtl/verilog/miim
--y ../eth/rtl/verilog/TECH
--y ../eth/rtl/verilog/TECH/xilinx
--y ../eth/rtl/verilog/RMON
--y ../eth
--y ../eth/bench/verilog
-
-# Ethernet Models
--y ../eth/bench/verilog