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| author | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
|---|---|---|
| committer | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
| commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
| tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-ams/ashenden/compliant/subprograms | |
| parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
| download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip | |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/subprograms')
43 files changed, 2866 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd new file mode 100644 index 0000000..377f266 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity addu is +end entity addu; + + +architecture test of addu is + + subtype word32 is bit_vector(31 downto 0); + + -- code in book + + procedure addu ( a, b : in word32; + result : out word32; overflow : out boolean ) is + variable sum : word32; + variable carry : bit := '0'; + begin + for index in sum'reverse_range loop + sum(index) := a(index) xor b(index) xor carry; + carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) ); + end loop; + result := sum; + overflow := carry = '1'; + end procedure addu; + + -- end code in book + +begin + + stimulus : process is + + -- code in book (in text) + + variable PC, next_PC : word32; + variable overflow_flag : boolean; + -- . . . + + -- end code in book + + begin + PC := X"0000_0010"; + + -- code in book (in text) + + addu ( PC, X"0000_0004", next_PC, overflow_flag); + + -- end code in book + + PC := X"FFFF_FFFC"; + addu ( PC, X"0000_0004", next_PC, overflow_flag); + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd new file mode 100644 index 0000000..55d250c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity average_sample is +end entity average_sample; + + + +architecture test of average_sample is + + procedure average_test is + + variable average : real := 0.0; + type sample_array is array (positive range <>) of real; + constant samples : sample_array := + ( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 ); + + -- code from book + + procedure average_samples is + variable total : real := 0.0; + begin + assert samples'length > 0 severity failure; + for index in samples'range loop + total := total + samples(index); + end loop; + average := total / real(samples'length); + end procedure average_samples; + + -- end code from book + + begin + + -- code from book (in text) + + average_samples; + + -- end code from book + + end procedure average_test; + + +begin + + average_test; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd new file mode 100644 index 0000000..bbcf283 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd @@ -0,0 +1,75 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity bv_lt is +end entity bv_lt; + + + +architecture test of bv_lt is + + -- code from book + + procedure bv_lt ( bv1, bv2 : in bit_vector; result : out boolean ) is + variable tmp1 : bit_vector(bv1'range) := bv1; + variable tmp2 : bit_vector(bv2'range) := bv2; + begin + tmp1(tmp1'left) := not tmp1(tmp1'left); + tmp2(tmp2'left) := not tmp2(tmp2'left); + result := tmp1 < tmp2; + end procedure bv_lt; + + -- end code from book + +begin + + stimulus : process is + + subtype byte is bit_vector(0 to 7); + variable result : boolean; + + begin + bv_lt( byte'(X"02"), byte'(X"04"), result ); + assert result; + + bv_lt( byte'(X"02"), byte'(X"02"), result ); + assert not result; + + bv_lt( byte'(X"02"), byte'(X"02"), result ); + assert not result; + + bv_lt( byte'(X"FC"), byte'(X"04"), result ); + assert result; + + bv_lt( byte'(X"04"), byte'(X"FC"), result ); + assert not result; + + bv_lt( byte'(X"FC"), byte'(X"FC"), result ); + assert not result; + + bv_lt( byte'(X"FC"), byte'(X"FE"), result ); + assert result; + + bv_lt( byte'(X"FE"), byte'(X"FC"), result ); + assert not result; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd new file mode 100644 index 0000000..94fe982 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity bv_to_natural is +end entity bv_to_natural; + + + +architecture test of bv_to_natural is + + -- code from book + + function bv_to_natural ( bv : in bit_vector ) return natural is + variable result : natural := 0; + begin + for index in bv'range loop + result := result * 2 + bit'pos(bv(index)); + end loop; + return result; + end function bv_to_natural; + + -- end code from book + + signal data : bit_vector(0 to 7); + constant address : bit_vector(0 to 3) := "0101"; + constant Taccess : delay_length := 80 ns; + +begin + + tester : process is + + constant rom_size : natural := 8; + constant word_size : natural := 8; + + -- code from book (in text) + + type rom_array is array (natural range 0 to rom_size-1) + of bit_vector(0 to word_size-1); + variable rom_data : rom_array; + + -- end code from book + + begin + + rom_data := (X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07"); + + -- code from book (in text) + + data <= rom_data ( bv_to_natural(address) ) after Taccess; + + -- end code from book + + wait; + end process tester; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd new file mode 100644 index 0000000..9df92fc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd @@ -0,0 +1,111 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity cache is +end entity cache; + +-- end not in book + + + +architecture behavioral of cache is + -- not in book + subtype word is bit_vector(0 to 31); + signal mem_addr : natural; + signal mem_data_in : word; + signal mem_read, mem_ack : bit := '0'; + -- end not in book +begin + + behavior : process is + + -- not in book + constant block_size : positive := 4; + type cache_block is array (0 to block_size - 1) of word; + type store_array is array (0 to 15) of cache_block; + variable data_store : store_array; + variable entry_index : natural := 1; + variable miss_base_address : natural := 16; + -- end not in book + + -- . . . + + procedure read_block( start_address : natural; + entry : out cache_block ) is + + variable memory_address_reg : natural; + variable memory_data_reg : word; + + procedure read_memory_word is + begin + mem_addr <= memory_address_reg; + mem_read <= '1'; + wait until mem_ack = '1'; + memory_data_reg := mem_data_in; + mem_read <= '0'; + wait until mem_ack = '0'; + end procedure read_memory_word; + + begin -- read_block + for offset in 0 to block_size - 1 loop + memory_address_reg := start_address + offset; + read_memory_word; + entry(offset) := memory_data_reg; + end loop; + end procedure read_block; + + begin -- behavior + -- . . . + read_block( miss_base_address, data_store(entry_index) ); + -- . . . + -- not in book + wait; + -- end not in book + end process behavior; + + + -- not in book + + memory : process is + + type store_array is array (0 to 31) of word; + constant store : store_array := + ( X"00000000", X"00000001", X"00000002", X"00000003", + X"00000004", X"00000005", X"00000006", X"00000007", + X"00000008", X"00000009", X"0000000a", X"0000000b", + X"0000000c", X"0000000d", X"0000000e", X"0000000f", + X"00000010", X"00000011", X"00000012", X"00000013", + X"00000014", X"00000015", X"00000016", X"00000017", + X"00000018", X"00000019", X"0000001a", X"0000001b", + X"0000001c", X"0000001d", X"0000001e", X"0000001f" ); + + begin + wait until mem_read = '1'; + mem_data_in <= store(mem_addr); + mem_ack <= '1'; + wait until mem_read = '0'; + mem_ack <= '0'; + end process memory; + + -- end not in book + + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd new file mode 100644 index 0000000..3c93af7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity check_setup is +end entity check_setup; + + + +architecture test of check_setup is + + -- code from book + + procedure check_setup ( signal data, clock : in bit; + constant Tsu : in time ) is + begin + if clock'event and clock = '1' then + assert data'last_event >= Tsu + report "setup time violation" severity error; + end if; + end procedure check_setup; + + -- end code from book + + signal ready, phi2 : bit := '0'; + constant Tsu_rdy_clk : delay_length := 4 ns; + +begin + + -- code from book (in text) + + check_ready_setup : check_setup ( data => ready, clock => phi2, + Tsu => Tsu_rdy_clk ); + + -- end code from book + + clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0'; + + stimulus : ready <= '1' after 4 ns, + '0' after 56 ns, + '1' after 87 ns, + '0' after 130 ns; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd new file mode 100644 index 0000000..950971a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd @@ -0,0 +1,81 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity control_processor is + generic ( Tpd : delay_length := 3 ns ); +end entity control_processor; + +-- end not in book + + + +architecture rtl of control_processor is + + type func_code is (add, subtract); + + signal op1, op2, dest : integer; + signal Z_flag : boolean; + signal func : func_code; + -- . . . + +begin + + alu : process is + + procedure do_arith_op is + variable result : integer; + begin + case func is + when add => + result := op1 + op2; + when subtract => + result := op1 - op2; + end case; + dest <= result after Tpd; + Z_flag <= result = 0 after Tpd; + end procedure do_arith_op; + + begin + -- . . . + do_arith_op; + -- . . . + -- not in book + wait on op1, op2, func; + -- end not in book + end process alu; + + -- . . . + + -- not in book + + stimulus : process is + begin + op1 <= 0; op2 <= 0; wait for 10 ns; + op1 <= 10; op2 <= 3; wait for 10 ns; + func <= subtract; wait for 10 ns; + op2 <= 10; wait for 10 ns; + + wait; + end process stimulus; + + -- end not in book + +end architecture rtl; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd new file mode 100644 index 0000000..521a2f6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd @@ -0,0 +1,80 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity control_sequencer is +end entity control_sequencer; + + + +architecture test of control_sequencer is + + signal phase1, phase2, reg_file_write_en, + A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0'; + +begin + + -- code from book + + control_sequencer : process is + + procedure control_write_back is + begin + wait until phase1 = '1'; + reg_file_write_en <= '1'; + wait until phase2 = '0'; + reg_file_write_en <= '0'; + end procedure control_write_back; + + procedure control_arith_op is + begin + wait until phase1 = '1'; + A_reg_out_en <= '1'; + B_reg_out_en <= '1'; + wait until phase1 = '0'; + A_reg_out_en <= '0'; + B_reg_out_en <= '0'; + wait until phase2 = '1'; + C_reg_load_en <= '1'; + wait until phase2 = '0'; + C_reg_load_en <= '0'; + control_write_back; -- call procedure + end procedure control_arith_op; + + -- . . . + + begin + -- . . . + control_arith_op; -- call procedure + -- . . . + -- not in book + wait; + -- end not in book + end process control_sequencer; + + -- end code from book + + + clock_gen : process is + begin + phase1 <= '1' after 10 ns, '0' after 20 ns; + phase2 <= '1' after 30 ns, '0' after 40 ns; + wait for 40 ns; + end process clock_gen; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd new file mode 100644 index 0000000..78435f8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd @@ -0,0 +1,85 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity do_arith_op is +end entity do_arith_op; + + +architecture test of do_arith_op is + + type func_code is (add, subtract); + + signal op1 : integer := 10; + signal op2 : integer := 3; + signal dest : integer := 0; + signal func : func_code := add; + + signal Z_flag : boolean := false; + + constant Tpd : delay_length := 3 ns; + +begin + + stimulus : process is + + -- code from book + + procedure do_arith_op ( op : in func_code ) is + variable result : integer; + begin + case op is + when add => + result := op1 + op2; + when subtract => + result := op1 - op2; + end case; + dest <= result after Tpd; + Z_flag <= result = 0 after Tpd; + end procedure do_arith_op; + + -- end code from book + + begin + wait for 10 ns; + + -- code from book (in text) + + do_arith_op ( add ); + + -- end code from book + + wait for 10 ns; + + -- code from book (in text) + + do_arith_op ( func ); + + -- end code from book + + wait for 10 ns; + do_arith_op ( subtract ); + wait for 10 ns; + op2 <= 10; + wait for 10 ns; + do_arith_op ( subtract ); + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd new file mode 100644 index 0000000..0bebf8a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +architecture arch of ent is + + type t is . . .; + + signal s : t; + + procedure p1 ( . . . ) is + variable v1 : t; + begin + v1 := s; + end procedure p1; + +begin -- arch + + proc1 : process is + + variable v2 : t; + + procedure p2 ( . . . ) is + variable v3 : t; + begin + p1 ( v2, v3, . . . ); + end procedure p2; + + begin -- proc1 + p2 ( v2, . . . ); + end process proc1; + + proc2 : process is + . . . + begin -- proc2 + p1 ( . . . ); + end process proc2; + +end architecture arch; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd new file mode 100644 index 0000000..a4efe78 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd @@ -0,0 +1,89 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity find_first_set is +end entity find_first_set; + + + +architecture test of find_first_set is + + -- code from book + + procedure find_first_set ( v : in bit_vector; + found : out boolean; + first_set_index : out natural ) is + begin + for index in v'range loop + if v(index) = '1' then + found := true; + first_set_index := index; + return; + end if; + end loop; + found := false; + end procedure find_first_set; + + -- end code from book + +begin + + stimulus : process is + + -- code from book (in text) + + variable int_req : bit_vector (7 downto 0); + variable top_priority : natural; + variable int_pending : boolean; + -- . . . + + -- end code from book + + constant block_count : natural := 16; + + -- code from book (in text) + + variable free_block_map : bit_vector(0 to block_count-1); + variable first_free_block : natural; + variable free_block_found : boolean; + -- . . . + + -- end code from book + + begin + int_req := "00010000"; + + -- code from book (in text) + + find_first_set ( int_req, int_pending, top_priority ); + + -- end code from book + + free_block_map := (others => '0'); + + -- code from book (in text) + + find_first_set ( free_block_map, free_block_found, first_free_block ); + + -- end code from book + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd new file mode 100644 index 0000000..e001657 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity freq_detect is + port ( terminal input : electrical; + terminal freq_out : electrical ); +end entity freq_detect; + +---------------------------------------------------------------- + +architecture threshold_crossing of freq_detect is + + quantity v_in across input to electrical_ref; + quantity v_out across i_out through freq_out to electrical_ref; + signal freq : real := 0.0; + constant threshold : real := 0.0; + constant scale_factor : real := 1.0e-6; + +begin + + detect: process ( v_in'above(threshold) ) is + variable t_previous : real := real'low; + begin + if v_in > threshold then + freq <= scale_factor / ( now - t_previous ); + t_previous := now; + end if; + end process detect; + + v_out == freq'ramp(1.0e-9, 1.0e-9); + +end threshold_crossing; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd new file mode 100644 index 0000000..c4cd40d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd @@ -0,0 +1,62 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity generate_clock is +end entity generate_clock; + + + +library ieee; use ieee.std_logic_1164.all; + +architecture test of generate_clock is + + -- code from book + + procedure generate_clock ( signal clk : out std_ulogic; + constant Tperiod, Tpulse, Tphase : in time ) is + begin + wait for Tphase; + loop + clk <= '1', '0' after Tpulse; + wait for Tperiod; + end loop; + end procedure generate_clock; + + -- end code from book + + -- code from book (in text) + + signal phi1, phi2 : std_ulogic := '0'; + -- . . . + + -- end code from book + +begin + + -- code from book (in text) + + gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns, + Tphase => 0 ns ); + + gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns, + Tphase => 25 ns ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd new file mode 100644 index 0000000..e20b60b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd @@ -0,0 +1,55 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity hold_time_checker is +end entity hold_time_checker; + + + +architecture test of hold_time_checker is + + constant Thold_d_clk : delay_length := 3 ns; + + signal clk, d : bit := '0'; + +begin + + -- code from book + + hold_time_checker : process ( clk, d ) is + variable last_clk_edge_time : time := 0 fs; + begin + if clk'event and clk = '1' then + last_clk_edge_time := now; + end if; + if d'event then + assert now - last_clk_edge_time >= Thold_d_clk + report "hold time violation"; + end if; + end process hold_time_checker; + + -- end code from book + + clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0'; + + stimulus : d <= '1' after 15 ns, + '0' after 53 ns, + '1' after 72 ns; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd new file mode 100644 index 0000000..b6aa145 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd @@ -0,0 +1,65 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity increment is +end entity increment; + + + +architecture test of increment is + + subtype word32 is bit_vector(31 downto 0); + + -- code from book + + procedure increment ( a : inout word32; by : in word32 := X"0000_0001" ) is + variable sum : word32; + variable carry : bit := '0'; + begin + for index in a'reverse_range loop + sum(index) := a(index) xor by(index) xor carry; + carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) ); + end loop; + a := sum; + end procedure increment; + + -- end code from book + +begin + + stimulus : process is + + variable count : word32 := X"0001_1100"; + + begin + + -- code from book (in text) + + increment(count, X"0000_0004"); + + increment(count); + + increment(count, by => open); + + -- end code from book + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt new file mode 100644 index 0000000..2a966d2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt @@ -0,0 +1,52 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 9 - Subprograms +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +average_samples.vhd entity average_samples test Figure 9-1 +control_processor.vhd entity control_processor rtl Figure 9-2 +instruction_interpreter.vhd entity instruction_interpreter test Figure 9-3 +control_sequencer.vhd entity control_sequencer test Figure 9-4 +instruction_interpreter-1.vhd entity instruction_interpreter test Figure 9-5 +do_arith_op.vhd entity do_arith_op test Figure 9-6 +addu.vhd entity addu test Figure 9-7 +negate.vhd entity negate test Figure 9-8 +receiver.vhd entity receiver behavioral Figure 9-9 +signal_generator.vhd entity signal_generator top_level Figure 9-10 +increment.vhd entity increment test Figure 9-11 +find_first_set.vhd entity find_first_set test Figure 9-12 +bv_lt.vhd entity bv_lt test Figure 9-13 +check_setup.vhd entity check_setup test Figure 9-14 +generate_clock.vhd entity generate_clock test Figure 9-15 +limited.vhd entity limited test Figure 9-16 +bv_to_natural.vhd entity bv_to_natural test Figure 9-17 +network_driver.vhd entity network_driver test Figure 9-18 +hold_time_checker.vhd entity hold_time_checker test Figure 9-19 +v_source.vhd entity v_source source_sine Figure 9-20 +freq_detect.vhd entity freq_detect threshold_crossing Figure 9-21 +mixer.vhd entity mixer weighted Figure 9-22 +mixer_wa.vhd entity mixer_wa weighted -- +motor_system.vhd entity motor_control_system state_space Figure 9-24 +motor_system_wa.vhd entity motor_control_system_wa simple -- +reg_ctrl.vhd entity reg_ctrl bool_eqn Figure 9-25 +ent.vhd -- arch Figure 9-26 +cache.vhd entity cache behavioral Figure 9-27 +p1.vhd -- -- Figure 9-28 +inline_01.vhd entity inline_01 test Section 9.2 +inline_02.vhd entity inline_02 test Section 9.3 +inline_03.vhd entity inline_03 test Section 9.4 +inline_04a.vhd entity inline_04a test Section 9.4 +inline_05a.vhd entity inline_05a test Section 9.4 +inline_06a.vhd entity inline_06a -- Section 9.4 +inline_07.vhd entity inline_07 test Section 9.6 +inline_08.vhd entity inline_08 test Section 9.6 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_v_source.vhd entity tb_v_source TB_v_source v_source.vhd +tb_freq_detect.vhd entity tb_freq_detect TB_freq_detect freq_detect.vhd +tb_mixer.vhd entity tb_mixer TB_mixer mixer_wa.vhd +tb_motor_system.vhd entity tb_motor_system TB_motor_system motor_system_wa.vhd +tb_reg_ctrl.vhd entity tb_reg_ctrl test reg_ctrl.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd new file mode 100644 index 0000000..69a308e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd @@ -0,0 +1,70 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_01 is + +end entity inline_01; + + +---------------------------------------------------------------- + + +architecture test of inline_01 is +begin + + + process_2_a : process is + + type t1 is (t1_1, t1_2); + type t2 is (t2_1, t2_2); + type t3 is (t3_1, t3_2); + type t4 is (t4_1, t4_2); + + constant v4 : t4 := t4_1; + + constant val1 : t1 := t1_1; + constant val2 : t2 := t2_1; + variable var3 : t3 := t3_1; + constant val4 : t4 := t4_1; + + -- code from book: + + procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is + begin + -- . . . + end procedure p; + + -- end of code from book + + begin + + -- code from book: + + p ( val1, val2, var3, val4 ); + p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 ); + p ( val1, val2, f4 => open, f3 => var3 ); + p ( val1, val2, var3 ); + + -- end of code from book + + wait; + end process process_2_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd new file mode 100644 index 0000000..ac3ece6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd @@ -0,0 +1,77 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_02 is + +end entity inline_02; + + +---------------------------------------------------------------- + + +architecture test of inline_02 is + + constant val1 : integer := 1; + + procedure p ( signal s1, s2 : in bit; val1 : in integer ) is + begin + null; + end procedure p; + +begin + + + block_3_a : block is + + signal s1, s2 : bit; + + begin + + -- code from book: + + call_proc : p ( s1, s2, val1 ); + + -- end of code from book + + end block block_3_a; + + + ---------------- + + + block_3_b : block is + + signal s1, s2 : bit; + + begin + + -- code from book: + + call_proc : process is + begin + p ( s1, s2, val1 ); + wait on s1, s2; + end process call_proc; + + -- end of code from book + + end block block_3_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd new file mode 100644 index 0000000..e9570b3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd @@ -0,0 +1,73 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_03 is + +end entity inline_03; + + +---------------------------------------------------------------- + + +library ieee; use ieee.numeric_bit.all; + +architecture test of inline_03 is + + constant T_delay_adder : delay_length := 10 ns; + + -- code from book: + + function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is + begin + -- . . . + -- not in book + return bit_vector(unsigned(bv1) + unsigned(bv2)); + -- end not in book + end function bv_add; + + signal source1, source2, sum : bit_vector(0 to 31); + + -- end of code from book + + +begin + + + -- code from book: + + adder : sum <= bv_add(source1, source2) after T_delay_adder; + + -- end of code from book + + + ---------------- + + + stimulus : process is + begin + wait for 50 ns; + source1 <= X"00000002"; source2 <= X"00000003"; wait for 50 ns; + source2 <= X"FFFFFFF0"; wait for 50 ns; + source1 <= X"00000010"; wait for 50 ns; + + wait; + end process stimulus; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd new file mode 100644 index 0000000..21c42c0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_04a is + +end entity inline_04a; + + +architecture test of inline_04a is + + -- code from book + + function vector_multiply ( p : real_vector; r : real ) return real_vector is + variable result : real_vector(p'range); + begin + for index in p'range loop + result(index) := p(index) * r; + end loop; + return result; + end function vector_multiply; + + -- + + quantity scale_factor : real; + quantity source_position, scaled_position : real_vector(1 to 3); + + -- end code from book + +begin + + -- code from book + + scaled_position == vector_multiply ( source_position, scale_factor ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd new file mode 100644 index 0000000..d6eeefc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_05a is + +end entity inline_05a; + + +architecture test of inline_05a is + + function limited ( value, min, max : real ) return real is + begin + if value > max then + return max; + elsif value < min then + return min; + else + return value; + end if; + end function limited; + + quantity v_in, v_amplified : real; + constant gain : real := 10.0; + constant v_neg : real := -10.0; + constant v_pos : real := 10.0; + +begin + + -- code from book + + v_amplified == limited ( gain * v_in, v_neg, v_pos ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd new file mode 100644 index 0000000..2f50845 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_06a is + + -- code from book: + + impure function now return delay_length; + + -- end of code from book + + impure function now return delay_length is + begin + return std.standard.now; + end function now; + + -- code from book: + + impure function now return real; + + -- end of code from book + + impure function now return real is + begin + return std.standard.now; + end function now; + +end entity inline_06a; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd new file mode 100644 index 0000000..cf99a5b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd @@ -0,0 +1,82 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_07 is + +end entity inline_07; + + +---------------------------------------------------------------- + + +library ieee; use ieee.numeric_bit.all; + +architecture test of inline_07 is +begin + + + process_5_a : process is + + -- code from book: + + procedure increment ( a : inout integer; n : in integer := 1 ) is -- . . . + -- not in book + begin + a := a + n; + end procedure increment; + -- end not in book; + + procedure increment ( a : inout bit_vector; n : in bit_vector := B"1" ) is -- . . . + -- not in book + begin + a := bit_vector(signed(a) + signed(n)); + end procedure increment; + -- end not in book; + + procedure increment ( a : inout bit_vector; n : in integer := 1 ) is -- . . . + -- not in book + begin + a := bit_vector(signed(a) + to_signed(n, a'length)); + end procedure increment; + -- end not in book; + + variable count_int : integer := 2; + variable count_bv : bit_vector (15 downto 0) := X"0002"; + + -- end of code from book + + begin + + -- code from book: + + increment ( count_int, 2 ); + increment ( count_int ); + + increment ( count_bv, X"0002"); + increment ( count_bv, 1 ); + + -- increment ( count_bv ); + + -- end of code from book + + wait; + end process process_5_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd new file mode 100644 index 0000000..01b5eb5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd @@ -0,0 +1,93 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_08 is + +end entity inline_08; + + +---------------------------------------------------------------- + + +library ieee; use ieee.numeric_bit.all; + +architecture test of inline_08 is +begin + + + process_5_b : process is + + -- code from book: + + function "+" ( left, right : in bit_vector ) return bit_vector is + begin + -- . . . + -- not in book + return bit_vector( "+"(signed(left), signed(right)) ); + -- end not in book + end function "+"; + + variable addr_reg : bit_vector(31 downto 0); + -- . . . + + -- end of code from book + + -- code from book: + + function "abs" ( right : in bit_vector ) return bit_vector is + begin + -- . . . + -- not in book + if right(right'left) = '0' then + return right; + else + return bit_vector( "-"(signed(right)) ); + end if; + -- end not in book + end function "abs"; + + variable accumulator : bit_vector(31 downto 0); + -- . . . + + -- end of code from book + + begin + + -- code from book: + + addr_reg := addr_reg + X"0000_0004"; + + -- end of code from book + + accumulator := X"000000FF"; + + -- code from book: + + accumulator := abs accumulator; + + -- end of code from book + + accumulator := X"FFFFFFFE"; + accumulator := abs accumulator; + + wait; + end process process_5_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd new file mode 100644 index 0000000..d72fe64 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd @@ -0,0 +1,86 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity instruction_interpreter is +end entity instruction_interpreter; + + +architecture test of instruction_interpreter is + + subtype word is bit_vector(31 downto 0); + + signal address_bus, data_bus_in : word := X"0000_0000"; + signal mem_read, mem_request, mem_ready, reset : bit := '0'; + +begin + + -- code from book + + instruction_interpreter : process is + + -- . . . + + -- not in book + variable mem_address_reg, mem_data_reg : word; + -- end not in book + + procedure read_memory is + begin + address_bus <= mem_address_reg; + mem_read <= '1'; + mem_request <= '1'; + wait until mem_ready = '1' or reset = '1'; + if reset = '1' then + return; + end if; + mem_data_reg := data_bus_in; + mem_request <= '0'; + wait until mem_ready = '0'; + end procedure read_memory; + + begin + -- . . . -- initialization + -- not in book + if reset = '1' then + wait until reset = '0'; + end if; + -- end not in book + loop + -- . . . + read_memory; + exit when reset = '1'; + -- . . . + end loop; + end process instruction_interpreter; + + -- end code from book + + + memory : process is + begin + wait until mem_request = '1'; + data_bus_in <= X"1111_1111"; + mem_ready <= '1' after 10 ns; + wait until mem_request = '0'; + mem_ready <= '0' after 10 ns; + end process memory; + + reset <= '1' after 85 ns; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd new file mode 100644 index 0000000..594ef76 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd @@ -0,0 +1,90 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity instruction_interpreter is +end entity instruction_interpreter; + + +library ieee; use ieee.numeric_bit.all; + +architecture test of instruction_interpreter is + + subtype word is unsigned(31 downto 0); + + signal address_bus, data_bus_in : word := X"0000_0000"; + signal mem_read, mem_request, mem_ready : bit := '0'; + +begin + + -- code from book + + instruction_interpreter : process is + + variable mem_address_reg, mem_data_reg, + prog_counter, instr_reg, accumulator, index_reg : word; + -- . . . + -- not in book + type opcode_type is (load_mem); + constant opcode : opcode_type := load_mem; + constant displacement : word := X"0000_0010"; + -- end not in book + + procedure read_memory is + begin + address_bus <= mem_address_reg; + mem_read <= '1'; + mem_request <= '1'; + wait until mem_ready = '1'; + mem_data_reg := data_bus_in; + mem_request <= '0'; + wait until mem_ready = '0'; + end procedure read_memory; + + begin + -- . . . -- initialization + loop + -- fetch next instruction + mem_address_reg := prog_counter; + read_memory; -- call procedure + instr_reg := mem_data_reg; + -- . . . + case opcode is + -- . . . + when load_mem => + mem_address_reg := index_reg + displacement; + read_memory; -- call procedure + accumulator := mem_data_reg; + -- . . . + end case; + end loop; + end process instruction_interpreter; + + -- end code from book + + + memory : process is + begin + wait until mem_request = '1'; + data_bus_in <= X"1111_1111"; + mem_ready <= '1'; + wait until mem_request = '0'; + mem_ready <= '0'; + end process memory; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd new file mode 100644 index 0000000..79f9e43 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd @@ -0,0 +1,88 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity limited is +end entity limited; + + + +architecture test of limited is + + -- code from book + + function limited ( value, min, max : real ) return real is + begin + if value > max then + return max; + elsif value < min then + return min; + else + return value; + end if; + end function limited; + + -- end code from book + +begin + + tester : process is + + variable new_temperature, current_temperature, increment : real; + variable new_motor_speed, old_motor_speed, + scale_factor, error : real; + + begin + + current_temperature := 75.0; + increment := 10.0; + + -- code from book (in text) + + new_temperature := limited ( current_temperature + increment, 10.0, 100.0 ); + + -- end code from book + + increment := 60.0; + new_temperature := limited ( current_temperature + increment, 10.0, 100.0 ); + increment := -100.0; + new_temperature := limited ( current_temperature + increment, 10.0, 100.0 ); + + old_motor_speed := 1000.0; + scale_factor := 5.0; + error := 5.0; + + -- code from book (in text) + + new_motor_speed := old_motor_speed + + scale_factor * limited ( error, -10.0, +10.0 ); + + -- end code from book + + error := 15.0; + new_motor_speed := old_motor_speed + + scale_factor * limited ( error, -10.0, +10.0 ); + + error := -20.0; + new_motor_speed := old_motor_speed + + scale_factor * limited ( error, -10.0, +10.0 ); + + wait; + end process tester; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd new file mode 100644 index 0000000..8dd8369 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd @@ -0,0 +1,47 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity mixer is + port ( terminal inputs : electrical_vector(1 to 8); + terminal output : electrical ); +end entity mixer; + +---------------------------------------------------------------- + +architecture weighted of mixer is + + quantity v_in across inputs; + quantity v_out across i_out through output; + constant gains : real_vector(1 to 8) + := ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 ); + +begin + + apply_weights : procedural is + variable sum : real := 0.0; + begin + for index in v_in'range loop + sum := sum + v_in(index) * gains(index); + end loop; + v_out := sum; + end procedural apply_weights; + +end architecture weighted; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd new file mode 100644 index 0000000..1f30454 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity mixer_wa is + port ( terminal inputs : electrical_vector(1 to 8); + terminal output : electrical ); +end entity mixer_wa; + +---------------------------------------------------------------- + +architecture weighted of mixer_wa is + + quantity v_in across inputs; + quantity v_out across i_out through output; + quantity v1, v2, v3, v4, v5, v6, v7, v8 : real; + constant gains : real_vector(1 to 8) + := ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 ); + +begin + + v1 == v_in(1) * gains(1); + v2 == v_in(2) * gains(2); + v3 == v_in(3) * gains(3); + v4 == v_in(4) * gains(4); + v5 == v_in(5) * gains(5); + v6 == v_in(6) * gains(6); + v7 == v_in(7) * gains(7); + v8 == v_in(8) * gains(8); + + v_out == v1 + v2 + v3 + v4 + v5 + v6 + v7 + v8; + +end architecture weighted; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd new file mode 100644 index 0000000..42f4d0f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd @@ -0,0 +1,60 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity motor_system is + port ( terminal vp, vm : electrical; + terminal px : electrical_vector(1 to 3) ); +end entity motor_system; + +---------------------------------------------------------------- + +architecture state_space of motor_system is + + quantity v_in across vp to vm; + quantity x across i_x through px to electrical_ref; + constant Tfb : real := 0.001; + constant Kfb : real := 1.0; + constant Te : real := 0.001; + constant Ke : real := 1.0; + constant Tm : real := 0.1; + constant Km : real := 1.0; + + type real_matrix is array (1 to 3, 1 to 3) of real; + constant c : real_matrix := ( ( -1.0/Tfb, 0.0, Kfb/Tfb ), + ( -Ke/Te, -1.0/Te, 0.0 ), + ( 0.0, Km/Tm, -1.0/Tm ) ); + +begin + + state_eqn : procedural is + variable sum : real_vector(1 to 3) := (0.0, 0.0, 0.0); + begin + for i in 1 to 3 loop + for j in 1 to 3 loop + sum(i) := sum(i) + c(i, j) * x(j); + end loop; + end loop; + x(1)'dot := sum(1); + x(2)'dot := sum(2) + (Ke/Te)*v_in; + x(3)'dot := sum(3); + end procedural state_eqn; + +end architecture state_space; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd new file mode 100644 index 0000000..90c6110 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity motor_system_wa is + port ( terminal vp, vm, px1, px2, px3 : electrical); -- 2 inputs, 3 outputs +end entity motor_system_wa; + +---------------------------------------------------------------- + +architecture simple of motor_system_wa is + + quantity v_in across vp to vm; -- Inout voltage/Current + quantity x1 across ix1 through px1 to electrical_ref; + quantity x2 across ix2 through px2 to electrical_ref; + quantity x3 across ix3 through px3 to electrical_ref; + constant Tfb : real := 0.001; + constant Kfb : real := 1.0; + constant Te : real := 0.001; + constant Ke : real := 1.0; + constant Tm : real := 0.1; + constant Km : real := 1.0; + constant c11 : real := -1.0/Tfb; + constant c12 : real := 0.0; + constant c13 : real := Kfb/Tfb; + constant c21 : real := -Ke/Te; + constant c22 : real := -1.0/Te; + constant c23 : real := 0.0; + constant c31 : real := 0.0; + constant c32 : real := Km/Tm; + constant c33 : real := -1.0/Tm; + +begin -- architecture simple + + x1'dot == c11*x1 + c12*x2 + c13*x3; + x2'dot == c21*x1 + c22*x2 + c23*x3 + (Ke/Te)*v_in; + x3'dot == c31*x1 + c32*x2 + c33*x3; + +end architecture simple; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd new file mode 100644 index 0000000..8c10cf0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd @@ -0,0 +1,67 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity negate is +end entity negate; + + +architecture test of negate is + + subtype word32 is bit_vector(31 downto 0); + + -- code in book + + procedure negate ( a : inout word32 ) is + variable carry_in : bit := '1'; + variable carry_out : bit; + begin + a := not a; + for index in a'reverse_range loop + carry_out := a(index) and carry_in; + a(index) := a(index) xor carry_in; + carry_in := carry_out; + end loop; + end procedure negate; + + -- end code in book + +begin + + stimulus : process is + + -- code in book (in text) + + variable op1 : word32; + -- . . . + + -- end code in book + + begin + op1 := X"0000_0002"; + + -- code in book (in text) + + negate ( op1 ); + + -- end code in book + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd new file mode 100644 index 0000000..02461c8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd @@ -0,0 +1,71 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity network_driver is +end entity network_driver; + + +architecture test of network_driver is + + constant target_host_id : natural := 10; + constant my_host_id : natural := 5; + type pkt_types is (control_pkt, other_pkt); + type pkt_header is record + dest, src : natural; + pkt_type : pkt_types; + seq : natural; + end record; + +begin + + -- code from book + + network_driver : process is + + constant seq_modulo : natural := 2**5; + subtype seq_number is natural range 0 to seq_modulo-1; + variable next_seq_number : seq_number := 0; + -- . . . + -- not in book + variable new_header : pkt_header; + -- end not in book + + impure function generate_seq_number return seq_number is + variable number : seq_number; + begin + number := next_seq_number; + next_seq_number := (next_seq_number + 1) mod seq_modulo; + return number; + end function generate_seq_number; + + begin -- network_driver + -- not in book + wait for 10 ns; + -- end not in book + -- . . . + new_header := pkt_header'( dest => target_host_id, + src => my_host_id, + pkt_type => control_pkt, + seq => generate_seq_number ); + -- . . . + end process network_driver; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd new file mode 100644 index 0000000..22627f9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd @@ -0,0 +1,36 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +procedure p1 is + + variable v : integer; + + procedure p2 is + variable v : integer; + begin -- p2 + . . . + v := v + 1; + . . . + end procedure p2; + +begin -- p1 + . . . + v := 2 * v; + . . . +end procedure p1; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd new file mode 100644 index 0000000..0c8a0b1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd @@ -0,0 +1,85 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity receiver is +end entity receiver; + + +-- code from book + +architecture behavioral of receiver is + + -- . . . -- type declarations, etc + + -- not in book + + subtype packet_index_range is integer range 1 to 8; + type packet_array is array (packet_index_range) of bit; + + -- end not in book + + signal recovered_data : bit; + signal recovered_clock : bit; + -- . . . + + procedure receive_packet ( signal rx_data : in bit; + signal rx_clock : in bit; + data_buffer : out packet_array ) is + begin + for index in packet_index_range loop + wait until rx_clock = '1'; + data_buffer(index) := rx_data; + end loop; + end procedure receive_packet; + +begin + + packet_assembler : process is + variable packet : packet_array; + begin + -- . . . + receive_packet ( recovered_data, recovered_clock, packet ); + -- . . . + end process packet_assembler; + + -- . . . + + + -- not in book + + data_generator : recovered_data <= '1' after 5 ns, + '0' after 15 ns, + '1' after 25 ns, + '0' after 35 ns, + '0' after 45 ns, + '1' after 55 ns, + '0' after 65 ns, + '1' after 75 ns; + + clock_generator : process is + begin + recovered_clock <= '0' after 2 ns, '1' after 10 ns; + wait for 10 ns; + end process clock_generator; + + -- end not in book + +end architecture behavioral; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd new file mode 100644 index 0000000..8d9c884 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd @@ -0,0 +1,37 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity reg_ctrl is + port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic; + reg_rd, reg_wr : out std_ulogic ); +end entity reg_ctrl; + +-------------------------------------------------- + +architecture bool_eqn of reg_ctrl is +begin + + rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en; + + rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en + and not cpu_clk; + +end architecture bool_eqn; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd new file mode 100644 index 0000000..b61730f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity signal_generator is + generic ( period : delay_length := 20 ns; + pulse_count : natural := 5 ); +end entity signal_generator; + +-- end not in book + + +library ieee; use ieee.std_logic_1164.all; + +architecture top_level of signal_generator is + + signal raw_signal : std_ulogic; + -- . . . + + procedure generate_pulse_train ( width, separation : in delay_length; + number : in natural; + signal s : out std_ulogic ) is + begin + for count in 1 to number loop + s <= '1', '0' after width; + wait for width + separation; + end loop; + end procedure generate_pulse_train; + +begin + + raw_signal_generator : process is + begin + -- . . . + generate_pulse_train ( width => period / 2, + separation => period - period / 2, + number => pulse_count, + s => raw_signal ); + -- . . . + -- not in book + wait; + -- end not in book + end process raw_signal_generator; + + -- . . . + +end architecture top_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd new file mode 100644 index 0000000..2715117 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_freq_detect is + +end tb_freq_detect; + +architecture TB_freq_detect of tb_freq_detect is + terminal in_src, freq_out : electrical; + -- Component declarations + -- Signal declarations +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 200.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + + freq1 : entity work.freq_detect(threshold_crossing) + port map( + input => in_src, + freq_out => freq_out + ); +end TB_freq_detect; + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd new file mode 100644 index 0000000..e0526b0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd @@ -0,0 +1,123 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_mixer is +end tb_mixer; + +architecture TB_mixer of tb_mixer is + -- Component declarations + -- Signal declarations + terminal mix_in : electrical_vector(1 to 8); + terminal pseudo_gnd : electrical; +begin + -- Signal assignments + -- Component instances + v3 : entity work.v_sine(ideal) + generic map( + amplitude => 5.0, + freq => 1.0e3 + ) + port map( + pos => mix_in(7), + neg => ELECTRICAL_REF + ); + v4 : entity work.v_sine(ideal) + generic map( + amplitude => 4.0, + freq => 2.0e3 + ) + port map( + pos => mix_in(8), + neg => ELECTRICAL_REF + ); + v9 : entity work.v_sine(ideal) + generic map( + freq => 1.0e3, + amplitude => 5.0 + ) + port map( + pos => mix_in(5), + neg => ELECTRICAL_REF + ); + v10 : entity work.v_sine(ideal) + generic map( + freq => 2.0e3, + amplitude => 4.0 + ) + port map( + pos => mix_in(6), + neg => ELECTRICAL_REF + ); + R2 : entity work.resistor(ideal) + generic map( + res => 1.0e3 + ) + port map( + p1 => pseudo_gnd, + p2 => ELECTRICAL_REF + ); + mixer1 : entity work.mixer_wa(weighted) + port map( + inputs => mix_in, + output => pseudo_gnd + ); + v14 : entity work.v_sine(ideal) + generic map( + amplitude => 4.0, + freq => 2.0e3 + ) + port map( + pos => mix_in(2), + neg => ELECTRICAL_REF + ); + v15 : entity work.v_sine(ideal) + generic map( + amplitude => 5.0, + freq => 1.0e3 + ) + port map( + pos => mix_in(1), + neg => ELECTRICAL_REF + ); + v16 : entity work.v_sine(ideal) + generic map( + freq => 2.0e3, + amplitude => 4.0 + ) + port map( + pos => mix_in(4), + neg => ELECTRICAL_REF + ); + v17 : entity work.v_sine(ideal) + generic map( + freq => 1.0e3, + amplitude => 5.0 + ) + port map( + pos => mix_in(3), + neg => ELECTRICAL_REF + ); +end TB_mixer; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd new file mode 100644 index 0000000..77fc0d4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_motor_system is +end tb_motor_system ; + +architecture TB_motor_system of tb_motor_system is + -- Component declarations + -- Signal declarations + terminal in_src, x1_out, x2_out, x3_out : electrical; + +begin + v7 : entity work.v_sine(ideal) + generic map( + freq => 10.0, + amplitude => 1.0 + ) + port map( + pos => in_src, + neg => electrical_ref + ); + state_var1: entity work.motor_system_wa(simple) + port map( + vp => in_src, + vm => ELECTRICAL_REF, + px1 => x1_out, + px2 => x2_out, + px3 => x3_out + ); +end TB_motor_system ; + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd new file mode 100644 index 0000000..c08db00 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_reg_ctrl is +end entity tb_reg_ctrl; + + + +library ieee; use ieee.std_logic_1164.all; +library util; + +architecture test of tb_reg_ctrl is + + signal reg_addr_decoded, rd, wr, io_en, + cpu_clk, reg_rd, reg_wr : std_ulogic := '0'; + signal test_vector : std_ulogic_vector(1 to 5); + + use util.stimulus_generators.all; + +begin + + dut : entity work.reg_ctrl + port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr ); + + stimulus : process is + begin + all_possible_values( bv => test_vector, + delay_between_values => 10 ns ); + wait; + end process stimulus; + + (reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd new file mode 100644 index 0000000..e509b55 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_v_source is + +end tb_v_source ; + +architecture TB_v_source of tb_v_source is + terminal in_src, out_flt : electrical; + -- Component declarations + -- Signal declarations +begin + -- Signal assignments + -- Component instances + vio : entity work.v_source(source_sine) + port map( + p => in_src, + m => ELECTRICAL_REF + ); + + R1 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => in_src, + p2 => electrical_ref + ); +end TB_v_source ; + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd new file mode 100644 index 0000000..845d65c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd @@ -0,0 +1,35 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; +library ieee; use ieee.math_real.all; + +entity v_source is + port ( terminal p, m : electrical ); +end entity v_source; + +---------------------------------------------------------------- + +architecture source_sine of v_source is + constant ampl : real := 1.0; + constant freq : real := 60.0; + quantity v across i through p to m; +begin + v == ampl * sin(2.0 * math_pi * freq * now); +end architecture source_sine; |