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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd')
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd new file mode 100644 index 0000000..2715117 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_freq_detect is + +end tb_freq_detect; + +architecture TB_freq_detect of tb_freq_detect is + terminal in_src, freq_out : electrical; + -- Component declarations + -- Signal declarations +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 200.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + + freq1 : entity work.freq_detect(threshold_crossing) + port map( + input => in_src, + freq_out => freq_out + ); +end TB_freq_detect; + + |