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authorTristan Gingold2013-12-20 04:48:54 +0100
committerTristan Gingold2013-12-20 04:48:54 +0100
commit6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch)
treebd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
parentbd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff)
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Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl')
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diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
new file mode 100644
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--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
@@ -0,0 +1,15 @@
+entity test_output is
+ port (
+ output : inout integer := 10
+ );
+end test_output;
+
+architecture only of test_output is
+begin -- test_output
+ test: process
+ begin -- process test
+ assert output = 10 report "test failed" severity error;
+ assert output /= 10 report "test passed" severity note;
+ wait;
+ end process test;
+end only;