Import vests testsuite

2 files changed, 30 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-array-type-through-inout-port.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-array-type-through-inout-port.vhdl
new file mode 100644
index 0000000..819c592
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-array-type-through-inout-port.vhdl
@@ -0,0 +1,15 @@
+entity test_output is
+  port (
+    output : inout bit_vector( 1 downto 0 ) := "10"
+    );
+end test_output;
+
+architecture only of test_output is
+begin  -- test_output
+  test: process
+  begin  -- process test
+    assert output = "10" report "test failed" severity error;
+    assert output /= "10" report "test passed" severity note;
+    wait;
+  end process test;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
new file mode 100644
index 0000000..294ddda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
@@ -0,0 +1,15 @@
+entity test_output is
+  port (
+    output : inout integer := 10
+    );
+end test_output;
+
+architecture only of test_output is
+begin  -- test_output
+  test: process
+  begin  -- process test
+    assert output = 10 report "test failed" severity error;
+    assert output /= 10 report "test passed" severity note;
+    wait;
+  end process test;
+end only;