From 6c3f709174e8e4d5411f851cedb7d84c38d3b04a Mon Sep 17 00:00:00 2001
From: Tristan Gingold
Date: Fri, 20 Dec 2013 04:48:54 +0100
Subject: Import vests testsuite

---
 .../entities/pass-integer-through-inout-port.vhdl         | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl

(limited to 'testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl')

diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
new file mode 100644
index 0000000..294ddda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
@@ -0,0 +1,15 @@
+entity test_output is
+  port (
+    output : inout integer := 10
+    );
+end test_output;
+
+architecture only of test_output is
+begin  -- test_output
+  test: process
+  begin  -- process test
+    assert output = 10 report "test failed" severity error;
+    assert output /= 10 report "test passed" severity note;
+    wait;
+  end process test;
+end only;
-- 
cgit