diff options
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub')
| -rw-r--r-- | library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub new file mode 100644 index 00000000..03f01494 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub @@ -0,0 +1,83 @@ +* Subcircuit 133 +.subckt 133 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\133\133.cir +.include 3_nor.sub +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u8 net-_u1-pad7_ net-_u8-pad2_ d_inverter +* u9 net-_u1-pad8_ net-_u9-pad2_ d_inverter +* u10 net-_u1-pad9_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad11_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad12_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad13_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u17-pad1_ 3_nor +x2 net-_u5-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u17-pad2_ 3_nor +x3 net-_u8-pad2_ net-_u9-pad2_ net-_u10-pad2_ net-_u16-pad1_ 3_nor +x4 net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u16-pad2_ 3_nor +* u15 net-_u14-pad2_ net-_u15-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u18 net-_u16-pad3_ net-_u15-pad2_ net-_u18-pad3_ d_nand +* u19 net-_u17-pad3_ net-_u18-pad3_ net-_u1-pad14_ d_nor +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad3_ net-_u4-pad2_ u4 +a4 net-_u1-pad4_ net-_u5-pad2_ u5 +a5 net-_u1-pad5_ net-_u6-pad2_ u6 +a6 net-_u1-pad6_ net-_u7-pad2_ u7 +a7 net-_u1-pad7_ net-_u8-pad2_ u8 +a8 net-_u1-pad8_ net-_u9-pad2_ u9 +a9 net-_u1-pad9_ net-_u10-pad2_ u10 +a10 net-_u1-pad10_ net-_u11-pad2_ u11 +a11 net-_u1-pad11_ net-_u12-pad2_ u12 +a12 net-_u1-pad12_ net-_u13-pad2_ u13 +a13 net-_u1-pad13_ net-_u14-pad2_ u14 +a14 net-_u14-pad2_ net-_u15-pad2_ u15 +a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a16 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u16-pad3_ net-_u15-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u1-pad14_ u19 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 133
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