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242 files changed, 20257 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030-cache.lib b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030-cache.lib new file mode 100644 index 00000000..391547eb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 74_1030 +# +DEF 74_1030 X 0 40 Y Y 1 F N +F0 "X" -150 -350 60 H V C CNN +F1 "74_1030" -150 600 60 H V C CNN +F2 "" -150 600 60 H I C CNN +F3 "" -150 600 60 H I C CNN +DRAW +S 100 550 -350 -250 0 1 0 N +X A1 1 -550 500 200 R 50 50 1 1 I +X A2 2 -550 400 200 R 50 50 1 1 I +X A3 3 -550 300 200 R 50 50 1 1 I +X A4 4 -550 200 200 R 50 50 1 1 I +X A5 5 -550 100 200 R 50 50 1 1 I +X A6 6 -550 0 200 R 50 50 1 1 I +X A7 7 -550 -100 200 R 50 50 1 1 I +X A8 8 -550 -200 200 R 50 50 1 1 I +X OUT 9 300 200 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir new file mode 100644 index 00000000..be5e3da1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir @@ -0,0 +1,30 @@ +* C:\Users\Shanthipriya\eSim-Workspace\030\030.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 13:20:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U9-Pad9_ Net-_U9-Pad10_ Net-_U9-Pad11_ Net-_U9-Pad12_ Net-_U9-Pad13_ Net-_U9-Pad14_ Net-_U9-Pad15_ Net-_U9-Pad16_ Net-_U10-Pad1_ 74_1030 +U9 A1 A2 A3 A4 A5 A6 A7 A8 Net-_U9-Pad9_ Net-_U9-Pad10_ Net-_U9-Pad11_ Net-_U9-Pad12_ Net-_U9-Pad13_ Net-_U9-Pad14_ Net-_U9-Pad15_ Net-_U9-Pad16_ adc_bridge_8 +U10 Net-_U10-Pad1_ OUT dac_bridge_1 +v1 A1 GND pulse +v2 A2 GND pulse +v3 A3 GND pulse +v4 A4 GND pulse +v5 A5 GND pulse +v6 A6 GND pulse +v7 A7 GND pulse +v8 A8 GND pulse +U11 OUT plot_v1 +U1 A1 plot_v1 +U2 A2 plot_v1 +U3 A3 plot_v1 +U4 A4 plot_v1 +U5 A5 plot_v1 +U6 A6 plot_v1 +U7 A7 plot_v1 +U8 A8 plot_v1 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir.out b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir.out new file mode 100644 index 00000000..75b8bced --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir.out @@ -0,0 +1,39 @@ +* c:\users\shanthipriya\esim-workspace\030\030.cir + +.include 74_1030.sub +x1 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ net-_u10-pad1_ 74_1030 +* u9 a1 a2 a3 a4 a5 a6 a7 a8 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ adc_bridge_8 +* u10 net-_u10-pad1_ out dac_bridge_1 +v1 a1 gnd pulse(0 5 0 1n 1n 2m 4m) +v2 a2 gnd pulse(0 5 0 1n 1n 4m 8m) +v3 a3 gnd pulse(0 5 0 1n 1n 8m 16m) +v4 a4 gnd pulse(0 5 0 1n 1n 16m 32m) +v5 a5 gnd pulse(0 5 0 1n 1n 32m 64m) +v6 a6 gnd pulse(0 5 0 1n 1n 64 128m) +v7 a7 gnd pulse(0 5 0 1n 1n 128m 256m) +v8 a8 gnd pulse(0 5 0 1n 1n 256m 512m) +* u11 out plot_v1 +* u1 a1 plot_v1 +* u2 a2 plot_v1 +* u3 a3 plot_v1 +* u4 a4 plot_v1 +* u5 a5 plot_v1 +* u6 a6 plot_v1 +* u7 a7 plot_v1 +* u8 a8 plot_v1 +a1 [a1 a2 a3 a4 a5 a6 a7 a8 ] [net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ ] u9 +a2 [net-_u10-pad1_ ] [out ] u10 +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 1e-03 300e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out)+6 v(a1)+12 v(a2)+18 v(a3)+24 v(a4)+30 v(a5)+36v(a6)+42 v(a7)+48 v(a8) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.pro b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.proj b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.proj new file mode 100644 index 00000000..57fa3d19 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.proj @@ -0,0 +1 @@ +schematicFile 030.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.sch b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.sch new file mode 100644 index 00000000..bbd27c39 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.sch @@ -0,0 +1,481 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 74_1030 X1 +U 1 1 68380FB2 +P 6050 3750 +F 0 "X1" H 5900 3400 60 0000 C CNN +F 1 "74_1030" H 5900 4350 60 0000 C CNN +F 2 "" H 5900 4350 60 0001 C CNN +F 3 "" H 5900 4350 60 0001 C CNN + 1 6050 3750 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U9 +U 1 1 68380FD5 +P 4950 3300 +F 0 "U9" H 4950 3300 60 0000 C CNN +F 1 "adc_bridge_8" H 4950 3450 60 0000 C CNN +F 2 "" H 4950 3300 60 0000 C CNN +F 3 "" H 4950 3300 60 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U10 +U 1 1 68381012 +P 6950 3600 +F 0 "U10" H 6950 3600 60 0000 C CNN +F 1 "dac_bridge_1" H 6950 3750 60 0000 C CNN +F 2 "" H 6950 3600 60 0000 C CNN +F 3 "" H 6950 3600 60 0000 C CNN + 1 6950 3600 + 1 0 0 -1 +$EndComp +$Comp +L pulse v1 +U 1 1 68381047 +P 950 5950 +F 0 "v1" H 750 6050 60 0000 C CNN +F 1 "pulse" H 750 5900 60 0000 C CNN +F 2 "R1" H 650 5950 60 0000 C CNN +F 3 "" H 950 5950 60 0000 C CNN + 1 950 5950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 6838112C +P 950 6750 +F 0 "#PWR01" H 950 6500 50 0001 C CNN +F 1 "GND" H 950 6600 50 0000 C CNN +F 2 "" H 950 6750 50 0001 C CNN +F 3 "" H 950 6750 50 0001 C CNN + 1 950 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 950 6750 950 6400 +$Comp +L pulse v2 +U 1 1 68381175 +P 1350 6200 +F 0 "v2" H 1150 6300 60 0000 C CNN +F 1 "pulse" H 1150 6150 60 0000 C CNN +F 2 "R1" H 1050 6200 60 0000 C CNN +F 3 "" H 1350 6200 60 0000 C CNN + 1 1350 6200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 6838117B +P 1350 7000 +F 0 "#PWR02" H 1350 6750 50 0001 C CNN +F 1 "GND" H 1350 6850 50 0000 C CNN +F 2 "" H 1350 7000 50 0001 C CNN +F 3 "" H 1350 7000 50 0001 C CNN + 1 1350 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 7000 1350 6650 +$Comp +L pulse v3 +U 1 1 683811BA +P 1850 5950 +F 0 "v3" H 1650 6050 60 0000 C CNN +F 1 "pulse" H 1650 5900 60 0000 C CNN +F 2 "R1" H 1550 5950 60 0000 C CNN +F 3 "" H 1850 5950 60 0000 C CNN + 1 1850 5950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 683811C0 +P 1850 6750 +F 0 "#PWR03" H 1850 6500 50 0001 C CNN +F 1 "GND" H 1850 6600 50 0000 C CNN +F 2 "" H 1850 6750 50 0001 C CNN +F 3 "" H 1850 6750 50 0001 C CNN + 1 1850 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1850 6750 1850 6400 +$Comp +L pulse v4 +U 1 1 683811C7 +P 2250 6200 +F 0 "v4" H 2050 6300 60 0000 C CNN +F 1 "pulse" H 2050 6150 60 0000 C CNN +F 2 "R1" H 1950 6200 60 0000 C CNN +F 3 "" H 2250 6200 60 0000 C CNN + 1 2250 6200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 683811CD +P 2250 7000 +F 0 "#PWR04" H 2250 6750 50 0001 C CNN +F 1 "GND" H 2250 6850 50 0000 C CNN +F 2 "" H 2250 7000 50 0001 C CNN +F 3 "" H 2250 7000 50 0001 C CNN + 1 2250 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2250 7000 2250 6650 +$Comp +L pulse v5 +U 1 1 6838126E +P 2650 5850 +F 0 "v5" H 2450 5950 60 0000 C CNN +F 1 "pulse" H 2450 5800 60 0000 C CNN +F 2 "R1" H 2350 5850 60 0000 C CNN +F 3 "" H 2650 5850 60 0000 C CNN + 1 2650 5850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 68381274 +P 2650 6650 +F 0 "#PWR05" H 2650 6400 50 0001 C CNN +F 1 "GND" H 2650 6500 50 0000 C CNN +F 2 "" H 2650 6650 50 0001 C CNN +F 3 "" H 2650 6650 50 0001 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 6650 2650 6300 +$Comp +L pulse v6 +U 1 1 6838127B +P 3050 6100 +F 0 "v6" H 2850 6200 60 0000 C CNN +F 1 "pulse" H 2850 6050 60 0000 C CNN +F 2 "R1" H 2750 6100 60 0000 C CNN +F 3 "" H 3050 6100 60 0000 C CNN + 1 3050 6100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 68381281 +P 3050 6900 +F 0 "#PWR06" H 3050 6650 50 0001 C CNN +F 1 "GND" H 3050 6750 50 0000 C CNN +F 2 "" H 3050 6900 50 0001 C CNN +F 3 "" H 3050 6900 50 0001 C CNN + 1 3050 6900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 6900 3050 6550 +$Comp +L pulse v7 +U 1 1 68381288 +P 3550 5850 +F 0 "v7" H 3350 5950 60 0000 C CNN +F 1 "pulse" H 3350 5800 60 0000 C CNN +F 2 "R1" H 3250 5850 60 0000 C CNN +F 3 "" H 3550 5850 60 0000 C CNN + 1 3550 5850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 6838128E +P 3550 6650 +F 0 "#PWR07" H 3550 6400 50 0001 C CNN +F 1 "GND" H 3550 6500 50 0000 C CNN +F 2 "" H 3550 6650 50 0001 C CNN +F 3 "" H 3550 6650 50 0001 C CNN + 1 3550 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3550 6650 3550 6300 +$Comp +L pulse v8 +U 1 1 68381295 +P 3950 6100 +F 0 "v8" H 3750 6200 60 0000 C CNN +F 1 "pulse" H 3750 6050 60 0000 C CNN +F 2 "R1" H 3650 6100 60 0000 C CNN +F 3 "" H 3950 6100 60 0000 C CNN + 1 3950 6100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 6838129B +P 3950 6900 +F 0 "#PWR08" H 3950 6650 50 0001 C CNN +F 1 "GND" H 3950 6750 50 0000 C CNN +F 2 "" H 3950 6900 50 0001 C CNN +F 3 "" H 3950 6900 50 0001 C CNN + 1 3950 6900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 6900 3950 6550 +Wire Wire Line + 3950 5650 3950 3950 +Wire Wire Line + 3950 3950 4350 3950 +Wire Wire Line + 3500 2700 3500 5400 +Wire Wire Line + 3500 3850 4350 3850 +Wire Wire Line + 3500 5400 3550 5400 +Wire Wire Line + 3050 5650 3050 3750 +Wire Wire Line + 3050 3750 4350 3750 +Wire Wire Line + 2650 5400 2650 3650 +Wire Wire Line + 2650 3650 4350 3650 +Wire Wire Line + 2250 3550 4350 3550 +Wire Wire Line + 1850 2700 1850 5500 +Wire Wire Line + 1850 3450 4350 3450 +Wire Wire Line + 1350 5750 1350 3350 +Wire Wire Line + 1350 3350 4350 3350 +Wire Wire Line + 950 2650 950 5500 +Wire Wire Line + 950 3250 4350 3250 +Connection ~ 950 3250 +Wire Wire Line + 1400 2650 1400 3350 +Connection ~ 1400 3350 +Connection ~ 1850 3450 +Connection ~ 2250 3550 +Wire Wire Line + 2250 2700 2250 5750 +Wire Wire Line + 2700 2700 2700 3650 +Connection ~ 2700 3650 +Wire Wire Line + 3150 2750 3150 3750 +Connection ~ 3150 3750 +Connection ~ 3500 3850 +Wire Wire Line + 3950 2750 3950 4000 +Connection ~ 3950 4000 +Text GLabel 750 3000 0 60 Input ~ 0 +A1 +Wire Wire Line + 750 3000 950 3000 +Connection ~ 950 3000 +Text GLabel 1200 3000 0 60 Input ~ 0 +A2 +Text GLabel 1650 3050 0 60 Input ~ 0 +A3 +Text GLabel 2050 3050 0 60 Input ~ 0 +A4 +Text GLabel 2450 3050 0 60 Input ~ 0 +A5 +Text GLabel 2950 3050 0 60 Input ~ 0 +A6 +Text GLabel 3350 3100 0 60 Input ~ 0 +A7 +Text GLabel 3700 3100 0 60 Input ~ 0 +A8 +Wire Wire Line + 1200 3000 1400 3000 +Connection ~ 1400 3000 +Wire Wire Line + 1650 3050 1850 3050 +Connection ~ 1850 3050 +Wire Wire Line + 2050 3050 2250 3050 +Connection ~ 2250 3050 +Wire Wire Line + 2450 3050 2700 3050 +Connection ~ 2700 3050 +Wire Wire Line + 2950 3050 3150 3050 +Connection ~ 3150 3050 +Wire Wire Line + 3350 3100 3500 3100 +Connection ~ 3500 3100 +Wire Wire Line + 3700 3100 3950 3100 +Connection ~ 3950 3100 +$Comp +L plot_v1 U11 +U 1 1 68381BED +P 8600 3650 +F 0 "U11" H 8600 4150 60 0000 C CNN +F 1 "plot_v1" H 8800 4000 60 0000 C CNN +F 2 "" H 8600 3650 60 0000 C CNN +F 3 "" H 8600 3650 60 0000 C CNN + 1 8600 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8600 3450 8600 3550 +Wire Wire Line + 8600 3550 7500 3550 +$Comp +L plot_v1 U1 +U 1 1 68381CC3 +P 950 2850 +F 0 "U1" H 950 3350 60 0000 C CNN +F 1 "plot_v1" H 1150 3200 60 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 1 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 68381D1C +P 1400 2850 +F 0 "U2" H 1400 3350 60 0000 C CNN +F 1 "plot_v1" H 1600 3200 60 0000 C CNN +F 2 "" H 1400 2850 60 0000 C CNN +F 3 "" H 1400 2850 60 0000 C CNN + 1 1400 2850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 68381D5D +P 1850 2900 +F 0 "U3" H 1850 3400 60 0000 C CNN +F 1 "plot_v1" H 2050 3250 60 0000 C CNN +F 2 "" H 1850 2900 60 0000 C CNN +F 3 "" H 1850 2900 60 0000 C CNN + 1 1850 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 68381DAE +P 2250 2900 +F 0 "U4" H 2250 3400 60 0000 C CNN +F 1 "plot_v1" H 2450 3250 60 0000 C CNN +F 2 "" H 2250 2900 60 0000 C CNN +F 3 "" H 2250 2900 60 0000 C CNN + 1 2250 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 68381DED +P 2700 2900 +F 0 "U5" H 2700 3400 60 0000 C CNN +F 1 "plot_v1" H 2900 3250 60 0000 C CNN +F 2 "" H 2700 2900 60 0000 C CNN +F 3 "" H 2700 2900 60 0000 C CNN + 1 2700 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 68381E26 +P 3150 2950 +F 0 "U6" H 3150 3450 60 0000 C CNN +F 1 "plot_v1" H 3350 3300 60 0000 C CNN +F 2 "" H 3150 2950 60 0000 C CNN +F 3 "" H 3150 2950 60 0000 C CNN + 1 3150 2950 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 68381E61 +P 3500 2900 +F 0 "U7" H 3500 3400 60 0000 C CNN +F 1 "plot_v1" H 3700 3250 60 0000 C CNN +F 2 "" H 3500 2900 60 0000 C CNN +F 3 "" H 3500 2900 60 0000 C CNN + 1 3500 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 68381EC5 +P 3950 2950 +F 0 "U8" H 3950 3450 60 0000 C CNN +F 1 "plot_v1" H 4150 3300 60 0000 C CNN +F 2 "" H 3950 2950 60 0000 C CNN +F 3 "" H 3950 2950 60 0000 C CNN + 1 3950 2950 + 1 0 0 -1 +$EndComp +Text GLabel 7750 3200 0 60 Input ~ 0 +OUT +Wire Wire Line + 7750 3200 7900 3200 +Wire Wire Line + 7900 3200 7900 3550 +Connection ~ 7900 3550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030_Previous_Values.xml new file mode 100644 index 00000000..d86518a7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">4m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">8m</field5><field5 name="Period">16m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">16m</field5><field5 name="Period">32m</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">32m</field5><field5 name="Period">64m</field5></v5><v6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">64</field5><field5 name="Period">128m</field5></v6><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">128m</field5><field5 name="Period">256m</field5></v7><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">256m</field5><field5 name="Period">512m</field5></v8></source><model><u9 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74_1030</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">300</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030-cache.lib b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030-cache.lib new file mode 100644 index 00000000..ce6d8814 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir new file mode 100644 index 00000000..7e1232c1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74_1030\74_1030.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 21:55:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nand +U4 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ d_nand +U5 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U5-Pad3_ d_nand +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_nand +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_nand +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad9_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir.out b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir.out new file mode 100644 index 00000000..27abdd10 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.pro b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sch b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sch new file mode 100644 index 00000000..c5547636 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sch @@ -0,0 +1,256 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 6835E69D +P 4550 2300 +F 0 "U2" H 4550 2300 60 0000 C CNN +F 1 "d_nand" H 4600 2400 60 0000 C CNN +F 2 "" H 4550 2300 60 0000 C CNN +F 3 "" H 4550 2300 60 0000 C CNN + 1 4550 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 6835E6D9 +P 4550 2500 +F 0 "U3" H 4550 2500 60 0000 C CNN +F 1 "d_nand" H 4600 2600 60 0000 C CNN +F 2 "" H 4550 2500 60 0000 C CNN +F 3 "" H 4550 2500 60 0000 C CNN + 1 4550 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 6835E714 +P 4550 2700 +F 0 "U4" H 4550 2700 60 0000 C CNN +F 1 "d_nand" H 4600 2800 60 0000 C CNN +F 2 "" H 4550 2700 60 0000 C CNN +F 3 "" H 4550 2700 60 0000 C CNN + 1 4550 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 6835E790 +P 4550 2900 +F 0 "U5" H 4550 2900 60 0000 C CNN +F 1 "d_nand" H 4600 3000 60 0000 C CNN +F 2 "" H 4550 2900 60 0000 C CNN +F 3 "" H 4550 2900 60 0000 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U6 +U 1 1 6835E7DD +P 5550 2400 +F 0 "U6" H 5550 2400 60 0000 C CNN +F 1 "d_nand" H 5600 2500 60 0000 C CNN +F 2 "" H 5550 2400 60 0000 C CNN +F 3 "" H 5550 2400 60 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 6835E828 +P 5550 2800 +F 0 "U7" H 5550 2800 60 0000 C CNN +F 1 "d_nand" H 5600 2900 60 0000 C CNN +F 2 "" H 5550 2800 60 0000 C CNN +F 3 "" H 5550 2800 60 0000 C CNN + 1 5550 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 6835E851 +P 6600 2600 +F 0 "U8" H 6600 2600 60 0000 C CNN +F 1 "d_nand" H 6650 2700 60 0000 C CNN +F 2 "" H 6600 2600 60 0000 C CNN +F 3 "" H 6600 2600 60 0000 C CNN + 1 6600 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 2250 5100 2250 +Wire Wire Line + 5100 2250 5100 2300 +Wire Wire Line + 5000 2450 5100 2450 +Wire Wire Line + 5100 2450 5100 2400 +Wire Wire Line + 5000 2650 5100 2650 +Wire Wire Line + 5100 2650 5100 2700 +Wire Wire Line + 5000 2850 5100 2850 +Wire Wire Line + 5100 2850 5100 2800 +Wire Wire Line + 6000 2350 6150 2350 +Wire Wire Line + 6150 2350 6150 2500 +Wire Wire Line + 6000 2750 6150 2750 +Wire Wire Line + 6150 2750 6150 2600 +$Comp +L PORT U1 +U 1 1 6835E8E4 +P 3850 2200 +F 0 "U1" H 3900 2300 30 0000 C CNN +F 1 "PORT" H 3850 2200 30 0000 C CNN +F 2 "" H 3850 2200 60 0000 C CNN +F 3 "" H 3850 2200 60 0000 C CNN + 1 3850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6835E93D +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6835E97C +P 3850 2400 +F 0 "U1" H 3900 2500 30 0000 C CNN +F 1 "PORT" H 3850 2400 30 0000 C CNN +F 2 "" H 3850 2400 60 0000 C CNN +F 3 "" H 3850 2400 60 0000 C CNN + 3 3850 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6835E9BD +P 3850 2500 +F 0 "U1" H 3900 2600 30 0000 C CNN +F 1 "PORT" H 3850 2500 30 0000 C CNN +F 2 "" H 3850 2500 60 0000 C CNN +F 3 "" H 3850 2500 60 0000 C CNN + 4 3850 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6835E9FE +P 3850 2600 +F 0 "U1" H 3900 2700 30 0000 C CNN +F 1 "PORT" H 3850 2600 30 0000 C CNN +F 2 "" H 3850 2600 60 0000 C CNN +F 3 "" H 3850 2600 60 0000 C CNN + 5 3850 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6835EA45 +P 3850 2700 +F 0 "U1" H 3900 2800 30 0000 C CNN +F 1 "PORT" H 3850 2700 30 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 6 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6835EA7E +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 7 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6835EACB +P 3850 2900 +F 0 "U1" H 3900 3000 30 0000 C CNN +F 1 "PORT" H 3850 2900 30 0000 C CNN +F 2 "" H 3850 2900 60 0000 C CNN +F 3 "" H 3850 2900 60 0000 C CNN + 8 3850 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6835EB2B +P 7300 2550 +F 0 "U1" H 7350 2650 30 0000 C CNN +F 1 "PORT" H 7300 2550 30 0000 C CNN +F 2 "" H 7300 2550 60 0000 C CNN +F 3 "" H 7300 2550 60 0000 C CNN + 9 7300 2550 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sub b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sub new file mode 100644 index 00000000..f5fa4db7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sub @@ -0,0 +1,34 @@ +* Subcircuit 74_1030 +.subckt 74_1030 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74_1030
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030_Previous_Values.xml new file mode 100644 index 00000000..598bf495 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030-cache.lib b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030-cache.lib new file mode 100644 index 00000000..ce6d8814 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir new file mode 100644 index 00000000..7e1232c1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74_1030\74_1030.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 21:55:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nand +U4 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ d_nand +U5 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U5-Pad3_ d_nand +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_nand +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_nand +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad9_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir.out b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir.out new file mode 100644 index 00000000..27abdd10 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.pro b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sch b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sch new file mode 100644 index 00000000..c5547636 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sch @@ -0,0 +1,256 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 6835E69D +P 4550 2300 +F 0 "U2" H 4550 2300 60 0000 C CNN +F 1 "d_nand" H 4600 2400 60 0000 C CNN +F 2 "" H 4550 2300 60 0000 C CNN +F 3 "" H 4550 2300 60 0000 C CNN + 1 4550 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 6835E6D9 +P 4550 2500 +F 0 "U3" H 4550 2500 60 0000 C CNN +F 1 "d_nand" H 4600 2600 60 0000 C CNN +F 2 "" H 4550 2500 60 0000 C CNN +F 3 "" H 4550 2500 60 0000 C CNN + 1 4550 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 6835E714 +P 4550 2700 +F 0 "U4" H 4550 2700 60 0000 C CNN +F 1 "d_nand" H 4600 2800 60 0000 C CNN +F 2 "" H 4550 2700 60 0000 C CNN +F 3 "" H 4550 2700 60 0000 C CNN + 1 4550 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 6835E790 +P 4550 2900 +F 0 "U5" H 4550 2900 60 0000 C CNN +F 1 "d_nand" H 4600 3000 60 0000 C CNN +F 2 "" H 4550 2900 60 0000 C CNN +F 3 "" H 4550 2900 60 0000 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U6 +U 1 1 6835E7DD +P 5550 2400 +F 0 "U6" H 5550 2400 60 0000 C CNN +F 1 "d_nand" H 5600 2500 60 0000 C CNN +F 2 "" H 5550 2400 60 0000 C CNN +F 3 "" H 5550 2400 60 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 6835E828 +P 5550 2800 +F 0 "U7" H 5550 2800 60 0000 C CNN +F 1 "d_nand" H 5600 2900 60 0000 C CNN +F 2 "" H 5550 2800 60 0000 C CNN +F 3 "" H 5550 2800 60 0000 C CNN + 1 5550 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 6835E851 +P 6600 2600 +F 0 "U8" H 6600 2600 60 0000 C CNN +F 1 "d_nand" H 6650 2700 60 0000 C CNN +F 2 "" H 6600 2600 60 0000 C CNN +F 3 "" H 6600 2600 60 0000 C CNN + 1 6600 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 2250 5100 2250 +Wire Wire Line + 5100 2250 5100 2300 +Wire Wire Line + 5000 2450 5100 2450 +Wire Wire Line + 5100 2450 5100 2400 +Wire Wire Line + 5000 2650 5100 2650 +Wire Wire Line + 5100 2650 5100 2700 +Wire Wire Line + 5000 2850 5100 2850 +Wire Wire Line + 5100 2850 5100 2800 +Wire Wire Line + 6000 2350 6150 2350 +Wire Wire Line + 6150 2350 6150 2500 +Wire Wire Line + 6000 2750 6150 2750 +Wire Wire Line + 6150 2750 6150 2600 +$Comp +L PORT U1 +U 1 1 6835E8E4 +P 3850 2200 +F 0 "U1" H 3900 2300 30 0000 C CNN +F 1 "PORT" H 3850 2200 30 0000 C CNN +F 2 "" H 3850 2200 60 0000 C CNN +F 3 "" H 3850 2200 60 0000 C CNN + 1 3850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6835E93D +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6835E97C +P 3850 2400 +F 0 "U1" H 3900 2500 30 0000 C CNN +F 1 "PORT" H 3850 2400 30 0000 C CNN +F 2 "" H 3850 2400 60 0000 C CNN +F 3 "" H 3850 2400 60 0000 C CNN + 3 3850 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6835E9BD +P 3850 2500 +F 0 "U1" H 3900 2600 30 0000 C CNN +F 1 "PORT" H 3850 2500 30 0000 C CNN +F 2 "" H 3850 2500 60 0000 C CNN +F 3 "" H 3850 2500 60 0000 C CNN + 4 3850 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6835E9FE +P 3850 2600 +F 0 "U1" H 3900 2700 30 0000 C CNN +F 1 "PORT" H 3850 2600 30 0000 C CNN +F 2 "" H 3850 2600 60 0000 C CNN +F 3 "" H 3850 2600 60 0000 C CNN + 5 3850 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6835EA45 +P 3850 2700 +F 0 "U1" H 3900 2800 30 0000 C CNN +F 1 "PORT" H 3850 2700 30 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 6 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6835EA7E +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 7 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6835EACB +P 3850 2900 +F 0 "U1" H 3900 3000 30 0000 C CNN +F 1 "PORT" H 3850 2900 30 0000 C CNN +F 2 "" H 3850 2900 60 0000 C CNN +F 3 "" H 3850 2900 60 0000 C CNN + 8 3850 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6835EB2B +P 7300 2550 +F 0 "U1" H 7350 2650 30 0000 C CNN +F 1 "PORT" H 7300 2550 30 0000 C CNN +F 2 "" H 7300 2550 60 0000 C CNN +F 3 "" H 7300 2550 60 0000 C CNN + 9 7300 2550 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sub b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sub new file mode 100644 index 00000000..f5fa4db7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sub @@ -0,0 +1,34 @@ +* Subcircuit 74_1030 +.subckt 74_1030 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74_1030
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030_Previous_Values.xml new file mode 100644 index 00000000..598bf495 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/analysis b/library/SubcircuitLibrary/esim_ic_files/54act11030/analysis new file mode 100644 index 00000000..f05a6cd0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/analysis @@ -0,0 +1 @@ +.tran 1e-03 300e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283-cache.lib new file mode 100644 index 00000000..007a4e66 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283-cache.lib @@ -0,0 +1,117 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_5 +# +DEF dac_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir new file mode 100644 index 00000000..61d06ffa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir @@ -0,0 +1,20 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74AC283\74AC283.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/07/25 22:10:48 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U6-Pad1_ Net-_X1-Pad5_ full_adder +X2 Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_X1-Pad5_ Net-_U6-Pad2_ Net-_X2-Pad5_ full_adder +X3 Net-_U4-Pad3_ Net-_U4-Pad4_ Net-_X2-Pad5_ Net-_U6-Pad3_ Net-_X3-Pad5_ full_adder +X4 Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_X3-Pad5_ Net-_U6-Pad4_ Net-_U6-Pad5_ full_adder +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ adc_bridge_3 +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ Net-_U3-Pad4_ adc_bridge_2 +U4 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U4-Pad3_ Net-_U4-Pad4_ adc_bridge_2 +U5 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U5-Pad3_ Net-_U5-Pad4_ adc_bridge_2 +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ Net-_U6-Pad5_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ dac_bridge_5 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ ? ? PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir.out new file mode 100644 index 00000000..c177727e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir.out @@ -0,0 +1,37 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ac283\74ac283.cir + +.include full_adder.sub +x1 net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u6-pad1_ net-_x1-pad5_ full_adder +x2 net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ net-_u6-pad2_ net-_x2-pad5_ full_adder +x3 net-_u4-pad3_ net-_u4-pad4_ net-_x2-pad5_ net-_u6-pad3_ net-_x3-pad5_ full_adder +x4 net-_u5-pad3_ net-_u5-pad4_ net-_x3-pad5_ net-_u6-pad4_ net-_u6-pad5_ full_adder +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ net-_u3-pad4_ adc_bridge_2 +* u4 net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2 +* u5 net-_u1-pad8_ net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad4_ adc_bridge_2 +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_5 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? port +a1 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] [net-_u3-pad3_ net-_u3-pad4_ ] u3 +a3 [net-_u1-pad6_ net-_u1-pad7_ ] [net-_u4-pad3_ net-_u4-pad4_ ] u4 +a4 [net-_u1-pad8_ net-_u1-pad9_ ] [net-_u5-pad3_ net-_u5-pad4_ ] u5 +a5 [net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ ] [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u6 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sch new file mode 100644 index 00000000..d10df53c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sch @@ -0,0 +1,449 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 67F3F735 +P 3500 2250 +F 0 "X1" H 4900 2950 60 0000 C CNN +F 1 "full_adder" H 4900 2850 60 0000 C CNN +F 2 "" H 3500 2250 60 0000 C CNN +F 3 "" H 3500 2250 60 0000 C CNN + 1 3500 2250 + 1 0 0 -1 +$EndComp +$Comp +L full_adder X2 +U 1 1 67F3F786 +P 3550 3700 +F 0 "X2" H 4950 4400 60 0000 C CNN +F 1 "full_adder" H 4950 4300 60 0000 C CNN +F 2 "" H 3550 3700 60 0000 C CNN +F 3 "" H 3550 3700 60 0000 C CNN + 1 3550 3700 + 1 0 0 -1 +$EndComp +$Comp +L full_adder X3 +U 1 1 67F3F7B7 +P 3550 5050 +F 0 "X3" H 4950 5750 60 0000 C CNN +F 1 "full_adder" H 4950 5650 60 0000 C CNN +F 2 "" H 3550 5050 60 0000 C CNN +F 3 "" H 3550 5050 60 0000 C CNN + 1 3550 5050 + 1 0 0 -1 +$EndComp +$Comp +L full_adder X4 +U 1 1 67F3F822 +P 3600 6550 +F 0 "X4" H 5000 7250 60 0000 C CNN +F 1 "full_adder" H 5000 7150 60 0000 C CNN +F 2 "" H 3600 6550 60 0000 C CNN +F 3 "" H 3600 6550 60 0000 C CNN + 1 3600 6550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5650 2100 5650 2450 +Wire Wire Line + 5650 2450 4000 2450 +Wire Wire Line + 4000 2450 4000 3550 +Wire Wire Line + 4000 3550 4150 3550 +Wire Wire Line + 5700 3550 5700 3800 +Wire Wire Line + 5700 3800 4000 3800 +Wire Wire Line + 4000 3800 4000 4900 +Wire Wire Line + 4000 4900 4150 4900 +Wire Wire Line + 5700 4900 5700 5300 +Wire Wire Line + 5700 5300 4000 5300 +Wire Wire Line + 4000 5300 4000 6400 +Wire Wire Line + 4000 6400 4200 6400 +$Comp +L adc_bridge_3 U2 +U 1 1 67F3F897 +P 3250 1600 +F 0 "U2" H 3250 1600 60 0000 C CNN +F 1 "adc_bridge_3" H 3250 1750 60 0000 C CNN +F 2 "" H 3250 1600 60 0000 C CNN +F 3 "" H 3250 1600 60 0000 C CNN + 1 3250 1600 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U3 +U 1 1 67F3F8CA +P 3350 2850 +F 0 "U3" H 3350 2850 60 0000 C CNN +F 1 "adc_bridge_2" H 3350 3000 60 0000 C CNN +F 2 "" H 3350 2850 60 0000 C CNN +F 3 "" H 3350 2850 60 0000 C CNN + 1 3350 2850 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U4 +U 1 1 67F3F91B +P 3350 4250 +F 0 "U4" H 3350 4250 60 0000 C CNN +F 1 "adc_bridge_2" H 3350 4400 60 0000 C CNN +F 2 "" H 3350 4250 60 0000 C CNN +F 3 "" H 3350 4250 60 0000 C CNN + 1 3350 4250 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U5 +U 1 1 67F3F95C +P 3350 5750 +F 0 "U5" H 3350 5750 60 0000 C CNN +F 1 "adc_bridge_2" H 3350 5900 60 0000 C CNN +F 2 "" H 3350 5750 60 0000 C CNN +F 3 "" H 3350 5750 60 0000 C CNN + 1 3350 5750 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_5 U6 +U 1 1 67F3F998 +P 7100 3350 +F 0 "U6" H 7100 3350 60 0000 C CNN +F 1 "dac_bridge_5" H 7100 3500 60 0000 C CNN +F 2 "" H 7100 3350 60 0000 C CNN +F 3 "" H 7100 3350 60 0000 C CNN + 1 7100 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 1550 3800 1300 +Wire Wire Line + 3800 1300 4100 1300 +Wire Wire Line + 3800 1650 4100 1650 +Wire Wire Line + 4100 1650 4100 1700 +Wire Wire Line + 3800 1750 3800 2100 +Wire Wire Line + 3800 2100 4100 2100 +Wire Wire Line + 3900 2800 4150 2800 +Wire Wire Line + 4150 2800 4150 2750 +Wire Wire Line + 3900 2900 4150 2900 +Wire Wire Line + 4150 2900 4150 3150 +Wire Wire Line + 3900 4200 4150 4200 +Wire Wire Line + 4150 4200 4150 4100 +Wire Wire Line + 3900 4300 4150 4300 +Wire Wire Line + 4150 4300 4150 4500 +Wire Wire Line + 3900 5700 4200 5700 +Wire Wire Line + 4200 5700 4200 5600 +Wire Wire Line + 3900 5800 4200 5800 +Wire Wire Line + 4200 5800 4200 6000 +Wire Wire Line + 5650 1300 6500 1300 +Wire Wire Line + 6500 1300 6500 3300 +Wire Wire Line + 5700 2750 6150 2750 +Wire Wire Line + 6150 2750 6150 3400 +Wire Wire Line + 6150 3400 6500 3400 +Wire Wire Line + 5700 4100 5800 4100 +Wire Wire Line + 5800 4100 5800 3500 +Wire Wire Line + 5800 3500 6500 3500 +Wire Wire Line + 5750 5600 5900 5600 +Wire Wire Line + 5900 5600 5900 3600 +Wire Wire Line + 5900 3600 6500 3600 +Wire Wire Line + 5750 6400 6000 6400 +Wire Wire Line + 6000 6400 6000 3700 +Wire Wire Line + 6000 3700 6500 3700 +$Comp +L PORT U1 +U 5 1 67F3FBD8 +P 1750 2900 +F 0 "U1" H 1800 3000 30 0000 C CNN +F 1 "PORT" H 1750 2900 30 0000 C CNN +F 2 "" H 1750 2900 60 0000 C CNN +F 3 "" H 1750 2900 60 0000 C CNN + 5 1750 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67F3FC33 +P 1750 4200 +F 0 "U1" H 1800 4300 30 0000 C CNN +F 1 "PORT" H 1750 4200 30 0000 C CNN +F 2 "" H 1750 4200 60 0000 C CNN +F 3 "" H 1750 4200 60 0000 C CNN + 6 1750 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 67F3FC80 +P 1750 4300 +F 0 "U1" H 1800 4400 30 0000 C CNN +F 1 "PORT" H 1750 4300 30 0000 C CNN +F 2 "" H 1750 4300 60 0000 C CNN +F 3 "" H 1750 4300 60 0000 C CNN + 7 1750 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 1550 2650 1550 +Wire Wire Line + 2050 1650 2650 1650 +Wire Wire Line + 2000 1750 2650 1750 +$Comp +L PORT U1 +U 1 1 67F3FD74 +P 1800 1550 +F 0 "U1" H 1850 1650 30 0000 C CNN +F 1 "PORT" H 1800 1550 30 0000 C CNN +F 2 "" H 1800 1550 60 0000 C CNN +F 3 "" H 1800 1550 60 0000 C CNN + 1 1800 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67F3FDD5 +P 1800 1650 +F 0 "U1" H 1850 1750 30 0000 C CNN +F 1 "PORT" H 1800 1650 30 0000 C CNN +F 2 "" H 1800 1650 60 0000 C CNN +F 3 "" H 1800 1650 60 0000 C CNN + 2 1800 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67F3FE38 +P 1750 1750 +F 0 "U1" H 1800 1850 30 0000 C CNN +F 1 "PORT" H 1750 1750 30 0000 C CNN +F 2 "" H 1750 1750 60 0000 C CNN +F 3 "" H 1750 1750 60 0000 C CNN + 3 1750 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67F3FEA1 +P 1750 2800 +F 0 "U1" H 1800 2900 30 0000 C CNN +F 1 "PORT" H 1750 2800 30 0000 C CNN +F 2 "" H 1750 2800 60 0000 C CNN +F 3 "" H 1750 2800 60 0000 C CNN + 4 1750 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 67F3FEEE +P 1850 5700 +F 0 "U1" H 1900 5800 30 0000 C CNN +F 1 "PORT" H 1850 5700 30 0000 C CNN +F 2 "" H 1850 5700 60 0000 C CNN +F 3 "" H 1850 5700 60 0000 C CNN + 8 1850 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67F3FF3B +P 1850 5800 +F 0 "U1" H 1900 5900 30 0000 C CNN +F 1 "PORT" H 1850 5800 30 0000 C CNN +F 2 "" H 1850 5800 60 0000 C CNN +F 3 "" H 1850 5800 60 0000 C CNN + 9 1850 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67F3FF88 +P 8100 3300 +F 0 "U1" H 8150 3400 30 0000 C CNN +F 1 "PORT" H 8100 3300 30 0000 C CNN +F 2 "" H 8100 3300 60 0000 C CNN +F 3 "" H 8100 3300 60 0000 C CNN + 10 8100 3300 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67F3FFED +P 8100 3400 +F 0 "U1" H 8150 3500 30 0000 C CNN +F 1 "PORT" H 8100 3400 30 0000 C CNN +F 2 "" H 8100 3400 60 0000 C CNN +F 3 "" H 8100 3400 60 0000 C CNN + 11 8100 3400 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67F40040 +P 8100 3500 +F 0 "U1" H 8150 3600 30 0000 C CNN +F 1 "PORT" H 8100 3500 30 0000 C CNN +F 2 "" H 8100 3500 60 0000 C CNN +F 3 "" H 8100 3500 60 0000 C CNN + 12 8100 3500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67F40089 +P 8100 3600 +F 0 "U1" H 8150 3700 30 0000 C CNN +F 1 "PORT" H 8100 3600 30 0000 C CNN +F 2 "" H 8100 3600 60 0000 C CNN +F 3 "" H 8100 3600 60 0000 C CNN + 13 8100 3600 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 67F40102 +P 8100 3700 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8100 3700 30 0000 C CNN +F 2 "" H 8100 3700 60 0000 C CNN +F 3 "" H 8100 3700 60 0000 C CNN + 14 8100 3700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2000 2800 2750 2800 +Wire Wire Line + 2000 2900 2750 2900 +Wire Wire Line + 2000 4200 2750 4200 +Wire Wire Line + 2000 4300 2750 4300 +Wire Wire Line + 2100 5700 2750 5700 +Wire Wire Line + 2100 5800 2750 5800 +Wire Wire Line + 7650 3300 7850 3300 +Wire Wire Line + 7650 3400 7850 3400 +Wire Wire Line + 7650 3500 7850 3500 +Wire Wire Line + 7650 3600 7850 3600 +Wire Wire Line + 7650 3700 7850 3700 +$Comp +L PORT U1 +U 15 1 67F40B32 +P 8400 4150 +F 0 "U1" H 8450 4250 30 0000 C CNN +F 1 "PORT" H 8400 4150 30 0000 C CNN +F 2 "" H 8400 4150 60 0000 C CNN +F 3 "" H 8400 4150 60 0000 C CNN + 15 8400 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67F40B8B +P 8400 4350 +F 0 "U1" H 8450 4450 30 0000 C CNN +F 1 "PORT" H 8400 4350 30 0000 C CNN +F 2 "" H 8400 4350 60 0000 C CNN +F 3 "" H 8400 4350 60 0000 C CNN + 16 8400 4350 + 1 0 0 -1 +$EndComp +NoConn ~ 8650 4150 +NoConn ~ 8650 4350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sub b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sub new file mode 100644 index 00000000..368d89c9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sub @@ -0,0 +1,31 @@ +* Subcircuit 74AC283 +.subckt 74AC283 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ac283\74ac283.cir +.include full_adder.sub +x1 net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u6-pad1_ net-_x1-pad5_ full_adder +x2 net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ net-_u6-pad2_ net-_x2-pad5_ full_adder +x3 net-_u4-pad3_ net-_u4-pad4_ net-_x2-pad5_ net-_u6-pad3_ net-_x3-pad5_ full_adder +x4 net-_u5-pad3_ net-_u5-pad4_ net-_x3-pad5_ net-_u6-pad4_ net-_u6-pad5_ full_adder +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ net-_u3-pad4_ adc_bridge_2 +* u4 net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2 +* u5 net-_u1-pad8_ net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad4_ adc_bridge_2 +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_5 +a1 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] [net-_u3-pad3_ net-_u3-pad4_ ] u3 +a3 [net-_u1-pad6_ net-_u1-pad7_ ] [net-_u4-pad3_ net-_u4-pad4_ ] u4 +a4 [net-_u1-pad8_ net-_u1-pad9_ ] [net-_u5-pad3_ net-_u5-pad4_ ] u5 +a5 [net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ ] [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u6 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends 74AC283
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283_Previous_Values.xml new file mode 100644 index 00000000..e0fa4837 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">adc_bridge<field9 name="Enter value for in_low (default=1.0)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u5><u6 name="type">dac_bridge<field17 name="Enter value for out_low (default=0.0)" /><field18 name="Enter value for out_high (default=5.0)" /><field19 name="Enter value for out_undef (default=0.5)" /><field20 name="Enter value for input load (default=1.0e-12)" /><field21 name="Enter the Rise Time (default=1.0e-9)" /><field22 name="Enter the Fall Time (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x2><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x3><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x4></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/analysis b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/analysis new file mode 100644 index 00000000..1ff7c211 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/analysis @@ -0,0 +1 @@ +.tran 0.01e-06 2e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-cache.lib new file mode 100644 index 00000000..0e92eab0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-cache.lib @@ -0,0 +1,81 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 283 +# +DEF 283 X 0 40 Y Y 1 F N +F0 "X" -400 100 60 H V C CNN +F1 "283" -350 1500 60 H V C CNN +F2 "" -350 1500 60 H I C CNN +F3 "" -350 1500 60 H I C CNN +DRAW +S 0 1400 -800 200 0 1 0 N +X A1 1 -1000 1200 200 R 50 50 1 1 I +X B1 2 -1000 750 200 R 50 50 1 1 I +X C0 3 -1000 1300 200 R 50 50 1 1 I +X A2 4 -1000 1100 200 R 50 50 1 1 I +X B2 5 -1000 650 200 R 50 50 1 1 I +X A3 6 -1000 1000 200 R 50 50 1 1 I +X B3 7 -1000 550 200 R 50 50 1 1 I +X A4 8 -1000 900 200 R 50 50 1 1 I +X B4 9 -1000 450 200 R 50 50 1 1 I +X S1 10 200 1050 200 L 50 50 1 1 O +X S2 11 200 950 200 L 50 50 1 1 O +X S3 12 200 850 200 L 50 50 1 1 O +X S4 13 200 750 200 L 50 50 1 1 O +X C_out 14 200 600 200 L 50 50 1 1 O +X GND 15 -1000 300 200 R 50 50 1 1 N +X vcc 16 200 1300 200 L 50 50 1 1 N +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-rescue.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-rescue.lib new file mode 100644 index 00000000..09091d02 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-rescue.lib @@ -0,0 +1,32 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 283-RESCUE-4_bit_FA +# +DEF 283-RESCUE-4_bit_FA X 0 40 Y Y 1 F N +F0 "X" -400 100 60 H V C CNN +F1 "283-RESCUE-4_bit_FA" -350 1500 60 H V C CNN +F2 "" -350 1500 60 H I C CNN +F3 "" -350 1500 60 H I C CNN +DRAW +S 0 1400 -800 200 0 1 0 N +X A1 1 -1000 1200 200 R 50 50 1 1 I +X B1 2 -1000 750 200 R 50 50 1 1 I +X C0 3 -1000 1300 200 R 50 50 1 1 I +X A2 4 -1000 1100 200 R 50 50 1 1 I +X B2 5 -1000 650 200 R 50 50 1 1 I +X A3 6 -1000 1000 200 R 50 50 1 1 I +X B3 6 -1000 550 200 R 50 50 1 1 I +X A4 8 -1000 900 200 R 50 50 1 1 I +X B4 9 -1000 450 200 R 50 50 1 1 I +X S1 10 200 1050 200 L 50 50 1 1 O +X S2 11 200 950 200 L 50 50 1 1 O +X S3 12 200 850 200 L 50 50 1 1 O +X S4 13 200 750 200 L 50 50 1 1 O +X C_out 14 200 600 200 L 50 50 1 1 O +X GND 15 -1000 300 200 R 50 50 1 1 N +X vcc 16 200 1300 200 L 50 50 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir new file mode 100644 index 00000000..083e3772 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir @@ -0,0 +1,34 @@ +* C:\Users\Shanthipriya\eSim-Workspace\4_bit_FA\4_bit_FA.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/08/25 10:08:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 C0 plot_v1 +U3 A1 plot_v1 +U4 A2 plot_v1 +U5 A3 plot_v1 +U7 A4 plot_v1 +U1 B1 plot_v1 +U6 B4 plot_v1 +U8 B3 plot_v1 +U9 B2 plot_v1 +U10 S1 plot_v1 +U11 S2 plot_v1 +U12 S3 plot_v1 +U13 S4 plot_v1 +U14 C_out plot_v1 +X1 A1 B1 C0 A2 B2 A3 B3 A4 B4 S1 S2 S3 S4 C_out ? ? 283 +v1 C0 GND pulse +v2 A1 GND pulse +v3 A2 GND pulse +v4 A3 GND pulse +v5 A4 GND pulse +v6 B1 GND pulse +v7 B2 GND pulse +v8 B3 GND pulse +v9 B4 GND pulse + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir.out new file mode 100644 index 00000000..db240b25 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir.out @@ -0,0 +1,37 @@ +* c:\users\shanthipriya\esim-workspace\4_bit_fa\4_bit_fa.cir + +.include 74AC283.sub +* u2 c0 plot_v1 +* u3 a1 plot_v1 +* u4 a2 plot_v1 +* u5 a3 plot_v1 +* u7 a4 plot_v1 +* u1 b1 plot_v1 +* u6 b4 plot_v1 +* u8 b3 plot_v1 +* u9 b2 plot_v1 +* u10 s1 plot_v1 +* u11 s2 plot_v1 +* u12 s3 plot_v1 +* u13 s4 plot_v1 +* u14 c_out plot_v1 +x1 a1 b1 c0 a2 b2 a3 b3 a4 b4 s1 s2 s3 s4 c_out ? ? 74AC283 +v1 c0 gnd pulse(0 5 0 1n 1n 250u 5120u) +v2 a1 gnd pulse(0 5 0 1n 1n 10u 20u) +v3 a2 gnd pulse(0 5 0 1n 1n 20u 40u) +v4 a3 gnd pulse(0 5 0 1n 1n 40u 80u) +v5 a4 gnd pulse(0 5 0 1n 1n 80u 160u) +v6 b1 gnd pulse(0 5 0 1n 1n 160u 320u) +v7 b2 gnd pulse(0 5 0 1n 1n 320u 640u) +v8 b3 gnd pulse(0 5 0 1n 1n 640u 1280u) +v9 b4 gnd pulse(0 5 0 1n 1n 1280u 2560u) +.tran 0.01e-06 2e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(c0)+6v(a1)+12 v(a2)+18v(a3)+24 v(a4)+30 v(b1)+36 v(b2)+42 v(b3)+48v(b4)+54 v(s1)+60 v(s2)+66 v(s3)+72v(s4)+78v(c_out) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.pro new file mode 100644 index 00000000..6dffef6e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.pro @@ -0,0 +1,74 @@ +update=04/07/25 22:12:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=4_bit_FA-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=eSim_Plot +LibName24=transistors +LibName25=conn +LibName26=eSim_User +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_Nghdl +LibName39=eSim_Ngveri +LibName40=eSim_SKY130 +LibName41=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.proj b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.proj new file mode 100644 index 00000000..74da6851 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.proj @@ -0,0 +1 @@ +schematicFile 4_bit_FA.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.sch new file mode 100644 index 00000000..89d7e29d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.sch @@ -0,0 +1,572 @@ +EESchema Schematic File Version 2 +LIBS:4_bit_FA-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:4_bit_FA-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3500 2050 5100 2050 +Wire Wire Line + 5100 2050 5100 2800 +Wire Wire Line + 3500 2350 5000 2350 +Wire Wire Line + 5000 2350 5000 2900 +Wire Wire Line + 5000 2900 5100 2900 +Wire Wire Line + 3500 2650 4900 2650 +Wire Wire Line + 4900 2650 4900 3000 +Wire Wire Line + 4900 3000 5100 3000 +Wire Wire Line + 3500 2950 4800 2950 +Wire Wire Line + 4800 2950 4800 3100 +Wire Wire Line + 4800 3100 5100 3100 +Wire Wire Line + 3500 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3200 +Wire Wire Line + 3500 3550 3850 3550 +Wire Wire Line + 3850 3550 3850 3350 +Wire Wire Line + 3850 3350 5100 3350 +Wire Wire Line + 3500 3850 3900 3850 +Wire Wire Line + 3900 3850 3900 3450 +Wire Wire Line + 3900 3450 5100 3450 +Wire Wire Line + 3500 4150 3950 4150 +Wire Wire Line + 3950 4150 3950 3550 +Wire Wire Line + 3950 3550 5100 3550 +Wire Wire Line + 3500 4450 4000 4450 +Wire Wire Line + 4000 4450 4000 3650 +Wire Wire Line + 4000 3650 5100 3650 +$Comp +L GND #PWR01 +U 1 1 67F3FF9A +P 1600 3450 +F 0 "#PWR01" H 1600 3200 50 0001 C CNN +F 1 "GND" H 1600 3300 50 0000 C CNN +F 2 "" H 1600 3450 50 0001 C CNN +F 3 "" H 1600 3450 50 0001 C CNN + 1 1600 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 2050 1600 2050 +Wire Wire Line + 1600 2050 1600 3450 +Wire Wire Line + 2600 2350 1600 2350 +Connection ~ 1600 2350 +Wire Wire Line + 2600 2650 1600 2650 +Connection ~ 1600 2650 +Wire Wire Line + 2600 2950 1600 2950 +Connection ~ 1600 2950 +Wire Wire Line + 2600 3250 1600 3250 +Connection ~ 1600 3250 +Wire Wire Line + 2600 3550 1800 3550 +Wire Wire Line + 1800 3250 1800 4450 +Connection ~ 1800 3250 +Wire Wire Line + 1800 3850 2600 3850 +Connection ~ 1800 3550 +Wire Wire Line + 1800 4150 2600 4150 +Connection ~ 1800 3850 +Wire Wire Line + 1800 4450 2600 4450 +Connection ~ 1800 4150 +$Comp +L plot_v1 U2 +U 1 1 67F401B5 +P 3650 2100 +F 0 "U2" H 3650 2600 60 0000 C CNN +F 1 "plot_v1" H 3850 2450 60 0000 C CNN +F 2 "" H 3650 2100 60 0000 C CNN +F 3 "" H 3650 2100 60 0000 C CNN + 1 3650 2100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 1900 3650 2050 +Connection ~ 3650 2050 +$Comp +L plot_v1 U3 +U 1 1 67F403E7 +P 3850 2400 +F 0 "U3" H 3850 2900 60 0000 C CNN +F 1 "plot_v1" H 4050 2750 60 0000 C CNN +F 2 "" H 3850 2400 60 0000 C CNN +F 3 "" H 3850 2400 60 0000 C CNN + 1 3850 2400 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 67F40422 +P 4100 2650 +F 0 "U4" H 4100 3150 60 0000 C CNN +F 1 "plot_v1" H 4300 3000 60 0000 C CNN +F 2 "" H 4100 2650 60 0000 C CNN +F 3 "" H 4100 2650 60 0000 C CNN + 1 4100 2650 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 67F4046B +P 4300 3000 +F 0 "U5" H 4300 3500 60 0000 C CNN +F 1 "plot_v1" H 4500 3350 60 0000 C CNN +F 2 "" H 4300 3000 60 0000 C CNN +F 3 "" H 4300 3000 60 0000 C CNN + 1 4300 3000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 67F404AA +P 4550 3350 +F 0 "U7" H 4550 3850 60 0000 C CNN +F 1 "plot_v1" H 4750 3700 60 0000 C CNN +F 2 "" H 4550 3350 60 0000 C CNN +F 3 "" H 4550 3350 60 0000 C CNN + 1 4550 3350 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 67F404E7 +P 3600 3550 +F 0 "U1" H 3600 4050 60 0000 C CNN +F 1 "plot_v1" H 3800 3900 60 0000 C CNN +F 2 "" H 3600 3550 60 0000 C CNN +F 3 "" H 3600 3550 60 0000 C CNN + 1 3600 3550 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 67F405AC +P 4400 4600 +F 0 "U6" H 4400 5100 60 0000 C CNN +F 1 "plot_v1" H 4600 4950 60 0000 C CNN +F 2 "" H 4400 4600 60 0000 C CNN +F 3 "" H 4400 4600 60 0000 C CNN + 1 4400 4600 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 67F405F7 +P 4850 4700 +F 0 "U8" H 4850 5200 60 0000 C CNN +F 1 "plot_v1" H 5050 5050 60 0000 C CNN +F 2 "" H 4850 4700 60 0000 C CNN +F 3 "" H 4850 4700 60 0000 C CNN + 1 4850 4700 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 67F4064A +P 5400 4750 +F 0 "U9" H 5400 5250 60 0000 C CNN +F 1 "plot_v1" H 5600 5100 60 0000 C CNN +F 2 "" H 5400 4750 60 0000 C CNN +F 3 "" H 5400 4750 60 0000 C CNN + 1 5400 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 2200 3850 2350 +Connection ~ 3850 2350 +Wire Wire Line + 4100 2450 4100 2650 +Connection ~ 4100 2650 +Wire Wire Line + 4300 2800 4300 2950 +Connection ~ 4300 2950 +Wire Wire Line + 4550 3150 4550 3250 +Connection ~ 4550 3250 +Wire Wire Line + 3600 3350 3600 3550 +Connection ~ 3600 3550 +Wire Wire Line + 4400 4400 4000 4400 +Connection ~ 4000 4400 +Wire Wire Line + 4850 4500 3850 4500 +Wire Wire Line + 3850 4500 3850 4150 +Connection ~ 3850 4150 +Wire Wire Line + 5400 4550 5400 4650 +Wire Wire Line + 5400 4650 3700 4650 +Wire Wire Line + 3700 4650 3700 3850 +Connection ~ 3700 3850 +Text GLabel 3450 1800 0 60 Input ~ 0 +C0 +Wire Wire Line + 3450 1800 3550 1800 +Wire Wire Line + 3550 1800 3550 2000 +Wire Wire Line + 3550 2000 3650 2000 +Connection ~ 3650 2000 +Text GLabel 3650 2200 0 60 Input ~ 0 +A1 +Wire Wire Line + 3650 2200 3800 2200 +Wire Wire Line + 3800 2200 3800 2300 +Wire Wire Line + 3800 2300 3850 2300 +Connection ~ 3850 2300 +Text GLabel 3850 2500 0 60 Input ~ 0 +A2 +Wire Wire Line + 3850 2500 3950 2500 +Wire Wire Line + 3950 2500 3950 2600 +Wire Wire Line + 3950 2600 4100 2600 +Connection ~ 4100 2600 +Text GLabel 3900 2800 0 60 Input ~ 0 +A3 +Wire Wire Line + 3900 2800 4100 2800 +Wire Wire Line + 4100 2800 4100 2900 +Wire Wire Line + 4100 2900 4300 2900 +Connection ~ 4300 2900 +Text GLabel 4150 3100 0 60 Input ~ 0 +A4 +Wire Wire Line + 4150 3100 4350 3100 +Wire Wire Line + 4350 3100 4350 3200 +Wire Wire Line + 4350 3200 4550 3200 +Connection ~ 4550 3200 +Text GLabel 3450 3400 0 60 Input ~ 0 +B1 +Wire Wire Line + 3450 3400 3450 3500 +Wire Wire Line + 3450 3500 3600 3500 +Connection ~ 3600 3500 +Text GLabel 4300 4850 0 60 Input ~ 0 +B2 +Wire Wire Line + 4300 4850 4400 4850 +Wire Wire Line + 4400 4850 4400 4650 +Connection ~ 4400 4650 +Text GLabel 3900 4800 0 60 Input ~ 0 +B3 +Wire Wire Line + 3900 4800 4050 4800 +Wire Wire Line + 4050 4800 4050 4500 +Connection ~ 4050 4500 +Text GLabel 4100 4150 0 60 Input ~ 0 +B4 +Wire Wire Line + 4100 4150 4150 4150 +Wire Wire Line + 4150 4150 4150 4400 +Connection ~ 4150 4400 +$Comp +L plot_v1 U10 +U 1 1 67F40F19 +P 6800 3250 +F 0 "U10" H 6800 3750 60 0000 C CNN +F 1 "plot_v1" H 7000 3600 60 0000 C CNN +F 2 "" H 6800 3250 60 0000 C CNN +F 3 "" H 6800 3250 60 0000 C CNN + 1 6800 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 67F40F66 +P 7250 3250 +F 0 "U11" H 7250 3750 60 0000 C CNN +F 1 "plot_v1" H 7450 3600 60 0000 C CNN +F 2 "" H 7250 3250 60 0000 C CNN +F 3 "" H 7250 3250 60 0000 C CNN + 1 7250 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 67F40FB3 +P 7700 3250 +F 0 "U12" H 7700 3750 60 0000 C CNN +F 1 "plot_v1" H 7900 3600 60 0000 C CNN +F 2 "" H 7700 3250 60 0000 C CNN +F 3 "" H 7700 3250 60 0000 C CNN + 1 7700 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 67F41000 +P 8100 3250 +F 0 "U13" H 8100 3750 60 0000 C CNN +F 1 "plot_v1" H 8300 3600 60 0000 C CNN +F 2 "" H 8100 3250 60 0000 C CNN +F 3 "" H 8100 3250 60 0000 C CNN + 1 8100 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 67F4104F +P 8500 3250 +F 0 "U14" H 8500 3750 60 0000 C CNN +F 1 "plot_v1" H 8700 3600 60 0000 C CNN +F 2 "" H 8500 3250 60 0000 C CNN +F 3 "" H 8500 3250 60 0000 C CNN + 1 8500 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6800 3050 6300 3050 +Wire Wire Line + 7250 3050 7250 3150 +Wire Wire Line + 7250 3150 6300 3150 +Wire Wire Line + 7700 3050 7700 3250 +Wire Wire Line + 7700 3250 6300 3250 +Wire Wire Line + 8100 3050 8100 3350 +Wire Wire Line + 8100 3350 6300 3350 +Wire Wire Line + 8500 3050 8500 3500 +Wire Wire Line + 8500 3500 6300 3500 +Text GLabel 6500 2950 0 60 Input ~ 0 +S1 +Wire Wire Line + 6500 2950 6550 2950 +Wire Wire Line + 6550 2950 6550 3050 +Connection ~ 6550 3050 +Text GLabel 6400 2600 0 60 Input ~ 0 +S2 +Wire Wire Line + 6400 2600 6600 2600 +Wire Wire Line + 6600 2600 6600 3150 +Connection ~ 6600 3150 +Text GLabel 6400 2350 0 60 Input ~ 0 +S3 +Wire Wire Line + 6400 2350 6650 2350 +Wire Wire Line + 6650 2350 6650 3250 +Connection ~ 6650 3250 +Text GLabel 6400 2100 0 60 Input ~ 0 +S4 +Wire Wire Line + 6400 2100 6700 2100 +Wire Wire Line + 6700 2100 6700 3350 +Connection ~ 6700 3350 +Text GLabel 6850 3600 0 60 Input ~ 0 +C_out +Wire Wire Line + 6850 3600 7000 3600 +Wire Wire Line + 7000 3600 7000 3500 +Connection ~ 7000 3500 +$Comp +L 283 X1 +U 1 1 67F4018C +P 6100 4100 +F 0 "X1" H 5700 4200 60 0000 C CNN +F 1 "283" H 5750 5600 60 0000 C CNN +F 2 "" H 5750 5600 60 0001 C CNN +F 3 "" H 5750 5600 60 0001 C CNN + 1 6100 4100 + 1 0 0 -1 +$EndComp +$Comp +L pulse v1 +U 1 1 67F4A87C +P 3050 2050 +F 0 "v1" H 2850 2150 60 0000 C CNN +F 1 "pulse" H 2850 2000 60 0000 C CNN +F 2 "R1" H 2750 2050 60 0000 C CNN +F 3 "" H 3050 2050 60 0000 C CNN + 1 3050 2050 + 0 1 1 0 +$EndComp +$Comp +L pulse v2 +U 1 1 67F4A8DB +P 3050 2350 +F 0 "v2" H 2850 2450 60 0000 C CNN +F 1 "pulse" H 2850 2300 60 0000 C CNN +F 2 "R1" H 2750 2350 60 0000 C CNN +F 3 "" H 3050 2350 60 0000 C CNN + 1 3050 2350 + 0 1 1 0 +$EndComp +$Comp +L pulse v3 +U 1 1 67F4A950 +P 3050 2650 +F 0 "v3" H 2850 2750 60 0000 C CNN +F 1 "pulse" H 2850 2600 60 0000 C CNN +F 2 "R1" H 2750 2650 60 0000 C CNN +F 3 "" H 3050 2650 60 0000 C CNN + 1 3050 2650 + 0 1 1 0 +$EndComp +$Comp +L pulse v4 +U 1 1 67F4A956 +P 3050 2950 +F 0 "v4" H 2850 3050 60 0000 C CNN +F 1 "pulse" H 2850 2900 60 0000 C CNN +F 2 "R1" H 2750 2950 60 0000 C CNN +F 3 "" H 3050 2950 60 0000 C CNN + 1 3050 2950 + 0 1 1 0 +$EndComp +$Comp +L pulse v5 +U 1 1 67F4A9E6 +P 3050 3250 +F 0 "v5" H 2850 3350 60 0000 C CNN +F 1 "pulse" H 2850 3200 60 0000 C CNN +F 2 "R1" H 2750 3250 60 0000 C CNN +F 3 "" H 3050 3250 60 0000 C CNN + 1 3050 3250 + 0 1 1 0 +$EndComp +$Comp +L pulse v6 +U 1 1 67F4A9EC +P 3050 3550 +F 0 "v6" H 2850 3650 60 0000 C CNN +F 1 "pulse" H 2850 3500 60 0000 C CNN +F 2 "R1" H 2750 3550 60 0000 C CNN +F 3 "" H 3050 3550 60 0000 C CNN + 1 3050 3550 + 0 1 1 0 +$EndComp +$Comp +L pulse v7 +U 1 1 67F4A9F2 +P 3050 3850 +F 0 "v7" H 2850 3950 60 0000 C CNN +F 1 "pulse" H 2850 3800 60 0000 C CNN +F 2 "R1" H 2750 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 1 3050 3850 + 0 1 1 0 +$EndComp +$Comp +L pulse v8 +U 1 1 67F4A9F8 +P 3050 4150 +F 0 "v8" H 2850 4250 60 0000 C CNN +F 1 "pulse" H 2850 4100 60 0000 C CNN +F 2 "R1" H 2750 4150 60 0000 C CNN +F 3 "" H 3050 4150 60 0000 C CNN + 1 3050 4150 + 0 1 1 0 +$EndComp +$Comp +L pulse v9 +U 1 1 67F4AA2C +P 3050 4450 +F 0 "v9" H 2850 4550 60 0000 C CNN +F 1 "pulse" H 2850 4400 60 0000 C CNN +F 2 "R1" H 2750 4450 60 0000 C CNN +F 3 "" H 3050 4450 60 0000 C CNN + 1 3050 4450 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283_Previous_Values.xml new file mode 100644 index 00000000..27d2915b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v4 name="Source type">dc<field1 name="Value">5</field1></v4><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v9 name="Source type">dc<field1 name="Value">5</field1></v9><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">250u</field5><field5 name="Period">5120u</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10u</field5><field5 name="Period">20u</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">20u</field5><field5 name="Period">40u</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">40u</field5><field5 name="Period">80u</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">80u</field5><field5 name="Period">160u</field5></v5><v6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">160u</field5><field5 name="Period">320u</field5></v6><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">320u</field5><field5 name="Period">640u</field5></v7><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">640u</field5><field5 name="Period">1280u</field5></v8><v9 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">1280u</field5><field5 name="Period">2560u</field5></v9></source><model /><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74AC283</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">2</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.pro new file mode 100644 index 00000000..ad45a0b3 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.pro @@ -0,0 +1,44 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sub b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.pro new file mode 100644 index 00000000..582cec8b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Mar 18 20:13:43 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=transistors +LibName3=conn +LibName4=74xx +LibName5=cmos4000 +LibName6=adc-dac +LibName7=memory +LibName8=xilinx +LibName9=microcontrollers +LibName10=dsp +LibName11=microchip +LibName12=analog_switches +LibName13=motorola +LibName14=texas +LibName15=intel +LibName16=audio +LibName17=interface +LibName18=digital-audio +LibName19=philips +LibName20=display +LibName21=cypress +LibName22=siliconi +LibName23=opto +LibName24=atmel +LibName25=contrib +LibName26=valves +LibName27=eSim_Analog +LibName28=eSim_Devices +LibName29=eSim_Digital +LibName30=eSim_Hybrid +LibName31=eSim_Miscellaneous +LibName32=eSim_Plot +LibName33=eSim_Power +LibName34=eSim_Sources +LibName35=eSim_Subckt +LibName36=eSim_User diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sub b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133-cache.lib new file mode 100644 index 00000000..aae6f27a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133-cache.lib @@ -0,0 +1,110 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_nor +# +DEF 3_nor x 0 40 Y Y 1 F N +F0 "x" 0 0 60 H V C CNN +F1 "3_nor" 0 650 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 300 500 -200 100 0 1 0 N +X a 1 -400 400 200 R 50 50 1 1 I +X b 2 -400 300 200 R 50 50 1 1 I +X c 3 -400 200 200 R 50 50 1 1 I +X out 4 500 300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.cir b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.cir new file mode 100644 index 00000000..8cdda3c7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.cir @@ -0,0 +1,33 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\133\133.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 16:10:21 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U8 Net-_U1-Pad7_ Net-_U8-Pad2_ d_inverter +U9 Net-_U1-Pad8_ Net-_U9-Pad2_ d_inverter +U10 Net-_U1-Pad9_ Net-_U10-Pad2_ d_inverter +U11 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad11_ Net-_U12-Pad2_ d_inverter +U13 Net-_U1-Pad12_ Net-_U13-Pad2_ d_inverter +U14 Net-_U1-Pad13_ Net-_U14-Pad2_ d_inverter +x1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U17-Pad1_ 3_nor +x2 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U17-Pad2_ 3_nor +x3 Net-_U8-Pad2_ Net-_U9-Pad2_ Net-_U10-Pad2_ Net-_U16-Pad1_ 3_nor +x4 Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U16-Pad2_ 3_nor +U15 Net-_U14-Pad2_ Net-_U15-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nand +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nand +U18 Net-_U16-Pad3_ Net-_U15-Pad2_ Net-_U18-Pad3_ d_nand +U19 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U1-Pad14_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.cir.out new file mode 100644 index 00000000..268bc674 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.cir.out @@ -0,0 +1,89 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\133\133.cir + +.include 3_nor.sub +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u8 net-_u1-pad7_ net-_u8-pad2_ d_inverter +* u9 net-_u1-pad8_ net-_u9-pad2_ d_inverter +* u10 net-_u1-pad9_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad11_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad12_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad13_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u17-pad1_ 3_nor +x2 net-_u5-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u17-pad2_ 3_nor +x3 net-_u8-pad2_ net-_u9-pad2_ net-_u10-pad2_ net-_u16-pad1_ 3_nor +x4 net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u16-pad2_ 3_nor +* u15 net-_u14-pad2_ net-_u15-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u18 net-_u16-pad3_ net-_u15-pad2_ net-_u18-pad3_ d_nand +* u19 net-_u17-pad3_ net-_u18-pad3_ net-_u1-pad14_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad3_ net-_u4-pad2_ u4 +a4 net-_u1-pad4_ net-_u5-pad2_ u5 +a5 net-_u1-pad5_ net-_u6-pad2_ u6 +a6 net-_u1-pad6_ net-_u7-pad2_ u7 +a7 net-_u1-pad7_ net-_u8-pad2_ u8 +a8 net-_u1-pad8_ net-_u9-pad2_ u9 +a9 net-_u1-pad9_ net-_u10-pad2_ u10 +a10 net-_u1-pad10_ net-_u11-pad2_ u11 +a11 net-_u1-pad11_ net-_u12-pad2_ u12 +a12 net-_u1-pad12_ net-_u13-pad2_ u13 +a13 net-_u1-pad13_ net-_u14-pad2_ u14 +a14 net-_u14-pad2_ net-_u15-pad2_ u15 +a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a16 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u16-pad3_ net-_u15-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u1-pad14_ u19 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.pro b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sch b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sch new file mode 100644 index 00000000..c5edf351 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sch @@ -0,0 +1,543 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:133-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 68383A91 +P 2750 1550 +F 0 "U2" H 2750 1450 60 0000 C CNN +F 1 "d_inverter" H 2750 1700 60 0000 C CNN +F 2 "" H 2800 1500 60 0000 C CNN +F 3 "" H 2800 1500 60 0000 C CNN + 1 2750 1550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 68383AAE +P 2750 1950 +F 0 "U3" H 2750 1850 60 0000 C CNN +F 1 "d_inverter" H 2750 2100 60 0000 C CNN +F 2 "" H 2800 1900 60 0000 C CNN +F 3 "" H 2800 1900 60 0000 C CNN + 1 2750 1950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68383B0D +P 2750 2300 +F 0 "U4" H 2750 2200 60 0000 C CNN +F 1 "d_inverter" H 2750 2450 60 0000 C CNN +F 2 "" H 2800 2250 60 0000 C CNN +F 3 "" H 2800 2250 60 0000 C CNN + 1 2750 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 68383B13 +P 2750 2700 +F 0 "U5" H 2750 2600 60 0000 C CNN +F 1 "d_inverter" H 2750 2850 60 0000 C CNN +F 2 "" H 2800 2650 60 0000 C CNN +F 3 "" H 2800 2650 60 0000 C CNN + 1 2750 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68383B95 +P 2750 3050 +F 0 "U6" H 2750 2950 60 0000 C CNN +F 1 "d_inverter" H 2750 3200 60 0000 C CNN +F 2 "" H 2800 3000 60 0000 C CNN +F 3 "" H 2800 3000 60 0000 C CNN + 1 2750 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68383B9B +P 2750 3450 +F 0 "U7" H 2750 3350 60 0000 C CNN +F 1 "d_inverter" H 2750 3600 60 0000 C CNN +F 2 "" H 2800 3400 60 0000 C CNN +F 3 "" H 2800 3400 60 0000 C CNN + 1 2750 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68383BA1 +P 2750 3800 +F 0 "U8" H 2750 3700 60 0000 C CNN +F 1 "d_inverter" H 2750 3950 60 0000 C CNN +F 2 "" H 2800 3750 60 0000 C CNN +F 3 "" H 2800 3750 60 0000 C CNN + 1 2750 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68383BA7 +P 2750 4200 +F 0 "U9" H 2750 4100 60 0000 C CNN +F 1 "d_inverter" H 2750 4350 60 0000 C CNN +F 2 "" H 2800 4150 60 0000 C CNN +F 3 "" H 2800 4150 60 0000 C CNN + 1 2750 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 68383C6C +P 2750 4500 +F 0 "U10" H 2750 4400 60 0000 C CNN +F 1 "d_inverter" H 2750 4650 60 0000 C CNN +F 2 "" H 2800 4450 60 0000 C CNN +F 3 "" H 2800 4450 60 0000 C CNN + 1 2750 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 68383C72 +P 2750 4850 +F 0 "U11" H 2750 4750 60 0000 C CNN +F 1 "d_inverter" H 2750 5000 60 0000 C CNN +F 2 "" H 2800 4800 60 0000 C CNN +F 3 "" H 2800 4800 60 0000 C CNN + 1 2750 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 68383C78 +P 2750 5250 +F 0 "U12" H 2750 5150 60 0000 C CNN +F 1 "d_inverter" H 2750 5400 60 0000 C CNN +F 2 "" H 2800 5200 60 0000 C CNN +F 3 "" H 2800 5200 60 0000 C CNN + 1 2750 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 68383C7E +P 2750 5600 +F 0 "U13" H 2750 5500 60 0000 C CNN +F 1 "d_inverter" H 2750 5750 60 0000 C CNN +F 2 "" H 2800 5550 60 0000 C CNN +F 3 "" H 2800 5550 60 0000 C CNN + 1 2750 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 68383C84 +P 2750 6000 +F 0 "U14" H 2750 5900 60 0000 C CNN +F 1 "d_inverter" H 2750 6150 60 0000 C CNN +F 2 "" H 2800 5950 60 0000 C CNN +F 3 "" H 2800 5950 60 0000 C CNN + 1 2750 6000 + 1 0 0 -1 +$EndComp +$Comp +L 3_nor x1 +U 1 1 68383C99 +P 4200 2200 +F 0 "x1" H 4200 2200 60 0000 C CNN +F 1 "3_nor" H 4200 2850 60 0000 C CNN +F 2 "" H 4200 2200 60 0001 C CNN +F 3 "" H 4200 2200 60 0001 C CNN + 1 4200 2200 + 1 0 0 -1 +$EndComp +$Comp +L 3_nor x2 +U 1 1 68383CF4 +P 4200 3250 +F 0 "x2" H 4200 3250 60 0000 C CNN +F 1 "3_nor" H 4200 3900 60 0000 C CNN +F 2 "" H 4200 3250 60 0001 C CNN +F 3 "" H 4200 3250 60 0001 C CNN + 1 4200 3250 + 1 0 0 -1 +$EndComp +$Comp +L 3_nor x3 +U 1 1 68383DFC +P 4200 4150 +F 0 "x3" H 4200 4150 60 0000 C CNN +F 1 "3_nor" H 4200 4800 60 0000 C CNN +F 2 "" H 4200 4150 60 0001 C CNN +F 3 "" H 4200 4150 60 0001 C CNN + 1 4200 4150 + 1 0 0 -1 +$EndComp +$Comp +L 3_nor x4 +U 1 1 68383E02 +P 4200 5200 +F 0 "x4" H 4200 5200 60 0000 C CNN +F 1 "3_nor" H 4200 5850 60 0000 C CNN +F 2 "" H 4200 5200 60 0001 C CNN +F 3 "" H 4200 5200 60 0001 C CNN + 1 4200 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 1550 3800 1550 +Wire Wire Line + 3800 1550 3800 1800 +Wire Wire Line + 3050 1950 3800 1950 +Wire Wire Line + 3800 1950 3800 1900 +Wire Wire Line + 3800 2000 3050 2000 +Wire Wire Line + 3050 2000 3050 2300 +Wire Wire Line + 3800 2850 3050 2850 +Wire Wire Line + 3050 2850 3050 2700 +Wire Wire Line + 3800 2950 3050 2950 +Wire Wire Line + 3050 2950 3050 3050 +Wire Wire Line + 3800 3050 3800 3450 +Wire Wire Line + 3800 3450 3050 3450 +Wire Wire Line + 3800 3750 3050 3750 +Wire Wire Line + 3050 3750 3050 3800 +Wire Wire Line + 3800 3850 3200 3850 +Wire Wire Line + 3200 3850 3200 4200 +Wire Wire Line + 3200 4200 3050 4200 +Wire Wire Line + 3800 3950 3800 4500 +Wire Wire Line + 3800 4500 3050 4500 +Wire Wire Line + 3800 4800 3050 4800 +Wire Wire Line + 3050 4800 3050 4850 +Wire Wire Line + 3800 4900 3550 4900 +Wire Wire Line + 3550 4900 3550 5250 +Wire Wire Line + 3550 5250 3050 5250 +Wire Wire Line + 3750 5000 3750 5600 +Wire Wire Line + 3750 5600 3050 5600 +Wire Wire Line + 3750 5000 3800 5000 +$Comp +L d_inverter U15 +U 1 1 68384012 +P 3950 6000 +F 0 "U15" H 3950 5900 60 0000 C CNN +F 1 "d_inverter" H 3950 6150 60 0000 C CNN +F 2 "" H 4000 5950 60 0000 C CNN +F 3 "" H 4000 5950 60 0000 C CNN + 1 3950 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 6000 3050 6000 +$Comp +L d_nand U17 +U 1 1 683840BF +P 6000 2450 +F 0 "U17" H 6000 2450 60 0000 C CNN +F 1 "d_nand" H 6050 2550 60 0000 C CNN +F 2 "" H 6000 2450 60 0000 C CNN +F 3 "" H 6000 2450 60 0000 C CNN + 1 6000 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1900 5550 1900 +Wire Wire Line + 5550 1900 5550 2350 +Wire Wire Line + 5550 2450 5550 2950 +Wire Wire Line + 5550 2950 4700 2950 +$Comp +L d_nand U16 +U 1 1 68384194 +P 5950 4350 +F 0 "U16" H 5950 4350 60 0000 C CNN +F 1 "d_nand" H 6000 4450 60 0000 C CNN +F 2 "" H 5950 4350 60 0000 C CNN +F 3 "" H 5950 4350 60 0000 C CNN + 1 5950 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 3850 5500 3850 +Wire Wire Line + 5500 3850 5500 4250 +Wire Wire Line + 5500 4900 5500 4350 +Wire Wire Line + 4700 4900 5500 4900 +$Comp +L d_nand U18 +U 1 1 683842C4 +P 7250 5200 +F 0 "U18" H 7250 5200 60 0000 C CNN +F 1 "d_nand" H 7300 5300 60 0000 C CNN +F 2 "" H 7250 5200 60 0000 C CNN +F 3 "" H 7250 5200 60 0000 C CNN + 1 7250 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4250 6000 6800 6000 +Wire Wire Line + 6800 6000 6800 5200 +Wire Wire Line + 6400 4300 6800 4300 +Wire Wire Line + 6800 4300 6800 5100 +$Comp +L d_nor U19 +U 1 1 683843A5 +P 8200 3400 +F 0 "U19" H 8200 3400 60 0000 C CNN +F 1 "d_nor" H 8250 3500 60 0000 C CNN +F 2 "" H 8200 3400 60 0000 C CNN +F 3 "" H 8200 3400 60 0000 C CNN + 1 8200 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 2400 7750 2400 +Wire Wire Line + 7750 2400 7750 3300 +Wire Wire Line + 7750 3400 7750 5150 +Wire Wire Line + 7750 5150 7700 5150 +Wire Wire Line + 8850 3350 8650 3350 +$Comp +L PORT U1 +U 1 1 6838464D +P 2200 1550 +F 0 "U1" H 2250 1650 30 0000 C CNN +F 1 "PORT" H 2200 1550 30 0000 C CNN +F 2 "" H 2200 1550 60 0000 C CNN +F 3 "" H 2200 1550 60 0000 C CNN + 1 2200 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 683846C4 +P 2200 1950 +F 0 "U1" H 2250 2050 30 0000 C CNN +F 1 "PORT" H 2200 1950 30 0000 C CNN +F 2 "" H 2200 1950 60 0000 C CNN +F 3 "" H 2200 1950 60 0000 C CNN + 2 2200 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6838471B +P 2200 2300 +F 0 "U1" H 2250 2400 30 0000 C CNN +F 1 "PORT" H 2200 2300 30 0000 C CNN +F 2 "" H 2200 2300 60 0000 C CNN +F 3 "" H 2200 2300 60 0000 C CNN + 3 2200 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68384770 +P 2200 2700 +F 0 "U1" H 2250 2800 30 0000 C CNN +F 1 "PORT" H 2200 2700 30 0000 C CNN +F 2 "" H 2200 2700 60 0000 C CNN +F 3 "" H 2200 2700 60 0000 C CNN + 4 2200 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 683847CB +P 2200 3050 +F 0 "U1" H 2250 3150 30 0000 C CNN +F 1 "PORT" H 2200 3050 30 0000 C CNN +F 2 "" H 2200 3050 60 0000 C CNN +F 3 "" H 2200 3050 60 0000 C CNN + 5 2200 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6838482C +P 2200 3450 +F 0 "U1" H 2250 3550 30 0000 C CNN +F 1 "PORT" H 2200 3450 30 0000 C CNN +F 2 "" H 2200 3450 60 0000 C CNN +F 3 "" H 2200 3450 60 0000 C CNN + 6 2200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68384893 +P 2200 3800 +F 0 "U1" H 2250 3900 30 0000 C CNN +F 1 "PORT" H 2200 3800 30 0000 C CNN +F 2 "" H 2200 3800 60 0000 C CNN +F 3 "" H 2200 3800 60 0000 C CNN + 7 2200 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 683848F2 +P 2200 4200 +F 0 "U1" H 2250 4300 30 0000 C CNN +F 1 "PORT" H 2200 4200 30 0000 C CNN +F 2 "" H 2200 4200 60 0000 C CNN +F 3 "" H 2200 4200 60 0000 C CNN + 8 2200 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68384955 +P 2200 4500 +F 0 "U1" H 2250 4600 30 0000 C CNN +F 1 "PORT" H 2200 4500 30 0000 C CNN +F 2 "" H 2200 4500 60 0000 C CNN +F 3 "" H 2200 4500 60 0000 C CNN + 9 2200 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 683849B6 +P 2200 4850 +F 0 "U1" H 2250 4950 30 0000 C CNN +F 1 "PORT" H 2200 4850 30 0000 C CNN +F 2 "" H 2200 4850 60 0000 C CNN +F 3 "" H 2200 4850 60 0000 C CNN + 10 2200 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 68384A21 +P 2200 5250 +F 0 "U1" H 2250 5350 30 0000 C CNN +F 1 "PORT" H 2200 5250 30 0000 C CNN +F 2 "" H 2200 5250 60 0000 C CNN +F 3 "" H 2200 5250 60 0000 C CNN + 11 2200 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68384A8A +P 2200 5600 +F 0 "U1" H 2250 5700 30 0000 C CNN +F 1 "PORT" H 2200 5600 30 0000 C CNN +F 2 "" H 2200 5600 60 0000 C CNN +F 3 "" H 2200 5600 60 0000 C CNN + 12 2200 5600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 68384AFD +P 2200 6000 +F 0 "U1" H 2250 6100 30 0000 C CNN +F 1 "PORT" H 2200 6000 30 0000 C CNN +F 2 "" H 2200 6000 60 0000 C CNN +F 3 "" H 2200 6000 60 0000 C CNN + 13 2200 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68384B6A +P 9100 3350 +F 0 "U1" H 9150 3450 30 0000 C CNN +F 1 "PORT" H 9100 3350 30 0000 C CNN +F 2 "" H 9100 3350 60 0000 C CNN +F 3 "" H 9100 3350 60 0000 C CNN + 14 9100 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub new file mode 100644 index 00000000..03f01494 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133.sub @@ -0,0 +1,83 @@ +* Subcircuit 133 +.subckt 133 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\133\133.cir +.include 3_nor.sub +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u8 net-_u1-pad7_ net-_u8-pad2_ d_inverter +* u9 net-_u1-pad8_ net-_u9-pad2_ d_inverter +* u10 net-_u1-pad9_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad11_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad12_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad13_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u17-pad1_ 3_nor +x2 net-_u5-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u17-pad2_ 3_nor +x3 net-_u8-pad2_ net-_u9-pad2_ net-_u10-pad2_ net-_u16-pad1_ 3_nor +x4 net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u16-pad2_ 3_nor +* u15 net-_u14-pad2_ net-_u15-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u18 net-_u16-pad3_ net-_u15-pad2_ net-_u18-pad3_ d_nand +* u19 net-_u17-pad3_ net-_u18-pad3_ net-_u1-pad14_ d_nor +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad3_ net-_u4-pad2_ u4 +a4 net-_u1-pad4_ net-_u5-pad2_ u5 +a5 net-_u1-pad5_ net-_u6-pad2_ u6 +a6 net-_u1-pad6_ net-_u7-pad2_ u7 +a7 net-_u1-pad7_ net-_u8-pad2_ u8 +a8 net-_u1-pad8_ net-_u9-pad2_ u9 +a9 net-_u1-pad9_ net-_u10-pad2_ u10 +a10 net-_u1-pad10_ net-_u11-pad2_ u11 +a11 net-_u1-pad11_ net-_u12-pad2_ u12 +a12 net-_u1-pad12_ net-_u13-pad2_ u13 +a13 net-_u1-pad13_ net-_u14-pad2_ u14 +a14 net-_u14-pad2_ net-_u15-pad2_ u15 +a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a16 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u16-pad3_ net-_u15-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u1-pad14_ u19 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 133
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/133_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133_Previous_Values.xml new file mode 100644 index 00000000..43acd9ff --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/133_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u17><u16 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u16><u18 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_nor</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_nor</field></x2><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_nor</field></x3><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_nor</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor-cache.lib new file mode 100644 index 00000000..40b8ccac --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.cir b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.cir new file mode 100644 index 00000000..a5ff5883 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.cir @@ -0,0 +1,13 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_nor\3_nor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/02/25 10:13:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nor +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.cir.out new file mode 100644 index 00000000..e99531ee --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.cir.out @@ -0,0 +1,20 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nor +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.pro b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.sch b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.sch new file mode 100644 index 00000000..de763f58 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.sch @@ -0,0 +1,128 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nor U2 +U 1 1 67ECC038 +P 5250 3400 +F 0 "U2" H 5250 3400 60 0000 C CNN +F 1 "d_nor" H 5300 3500 60 0000 C CNN +F 2 "" H 5250 3400 60 0000 C CNN +F 3 "" H 5250 3400 60 0000 C CNN + 1 5250 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U3 +U 1 1 67ECC07F +P 6150 3450 +F 0 "U3" H 6150 3450 60 0000 C CNN +F 1 "d_nor" H 6200 3550 60 0000 C CNN +F 2 "" H 6150 3450 60 0000 C CNN +F 3 "" H 6150 3450 60 0000 C CNN + 1 6150 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 3450 5550 3450 +Wire Wire Line + 5550 3450 5550 3500 +Wire Wire Line + 5550 3500 4800 3500 +$Comp +L PORT U1 +U 1 1 67ECC0BA +P 4550 3300 +F 0 "U1" H 4600 3400 30 0000 C CNN +F 1 "PORT" H 4550 3300 30 0000 C CNN +F 2 "" H 4550 3300 60 0000 C CNN +F 3 "" H 4550 3300 60 0000 C CNN + 1 4550 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67ECC0FF +P 4550 3400 +F 0 "U1" H 4600 3500 30 0000 C CNN +F 1 "PORT" H 4550 3400 30 0000 C CNN +F 2 "" H 4550 3400 60 0000 C CNN +F 3 "" H 4550 3400 60 0000 C CNN + 2 4550 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67ECC12C +P 4550 3500 +F 0 "U1" H 4600 3600 30 0000 C CNN +F 1 "PORT" H 4550 3500 30 0000 C CNN +F 2 "" H 4550 3500 60 0000 C CNN +F 3 "" H 4550 3500 60 0000 C CNN + 3 4550 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67ECC14F +P 6850 3400 +F 0 "U1" H 6900 3500 30 0000 C CNN +F 1 "PORT" H 6850 3400 30 0000 C CNN +F 2 "" H 6850 3400 60 0000 C CNN +F 3 "" H 6850 3400 60 0000 C CNN + 4 6850 3400 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.sub b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.sub new file mode 100644 index 00000000..3d3a66d3 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_nor +.subckt 3_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nor +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_nor +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 3_nor
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor_Previous_Values.xml new file mode 100644 index 00000000..61fd0102 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/3_nor_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_nor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54als133/analysis new file mode 100644 index 00000000..cd8a1c8d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/analysis @@ -0,0 +1 @@ +.tran 1e-09 50e-06 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133-cache.lib new file mode 100644 index 00000000..f3686e38 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133-cache.lib @@ -0,0 +1,143 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 133 +# +DEF 133 X 0 40 Y Y 1 F N +F0 "X" -100 -800 60 H V C CNN +F1 "133" -150 600 60 H V C CNN +F2 "" -150 600 60 H I C CNN +F3 "" -150 600 60 H I C CNN +DRAW +S 100 550 -350 -750 0 1 0 N +X A1 1 -550 500 200 R 50 50 1 1 I +X A2 2 -550 400 200 R 50 50 1 1 I +X A3 3 -550 300 200 R 50 50 1 1 I +X A4 4 -550 200 200 R 50 50 1 1 I +X A5 5 -550 100 200 R 50 50 1 1 I +X A6 6 -550 0 200 R 50 50 1 1 I +X A7 7 -550 -100 200 R 50 50 1 1 I +X A8 8 -550 -200 200 R 50 50 1 1 I +X A9 9 -550 -300 200 R 50 50 1 1 I +X A10 10 -550 -400 200 R 50 50 1 1 I +X A11 11 -550 -500 200 R 50 50 1 1 I +X A12 12 -550 -600 200 R 50 50 1 1 I +X A13 13 -550 -700 200 R 50 50 1 1 I +X OUT 14 300 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_5 +# +DEF adc_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.cir b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.cir new file mode 100644 index 00000000..4fd11a16 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.cir @@ -0,0 +1,41 @@ +* C:\Users\Shanthipriya\eSim-Workspace\13_nand_ic5\13_nand_ic5.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 16:11:34 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U9 A1 A2 A3 A4 A5 A6 A7 A8 Net-_U9-Pad9_ Net-_U9-Pad10_ Net-_U9-Pad11_ Net-_U9-Pad12_ Net-_U9-Pad13_ Net-_U9-Pad14_ Net-_U9-Pad15_ Net-_U9-Pad16_ adc_bridge_8 +U13 Net-_U13-Pad1_ OUT dac_bridge_1 +v1 A1 GND pulse +v2 A2 GND pulse +v3 A3 GND pulse +v4 A4 GND pulse +v5 A5 GND pulse +v6 A6 GND pulse +v7 A7 GND pulse +v8 A8 GND pulse +U17 OUT plot_v1 +U1 A1 plot_v1 +U2 A2 plot_v1 +U3 A3 plot_v1 +U4 A4 plot_v1 +U5 A5 plot_v1 +U6 A6 plot_v1 +U7 A7 plot_v1 +U8 A8 plot_v1 +U10 A9 A10 A11 A12 A13 Net-_U10-Pad6_ Net-_U10-Pad7_ Net-_U10-Pad8_ Net-_U10-Pad9_ Net-_U10-Pad10_ adc_bridge_5 +v9 A9 GND pulse +v10 A10 GND pulse +v11 A11 GND pulse +v12 A12 GND pulse +v13 A13 GND pulse +U11 A13 plot_v1 +U12 A12 plot_v1 +U14 A11 plot_v1 +U15 A10 plot_v1 +U16 A9 plot_v1 +X1 Net-_U9-Pad9_ Net-_U9-Pad10_ Net-_U9-Pad11_ Net-_U9-Pad12_ Net-_U9-Pad13_ Net-_U9-Pad14_ Net-_U9-Pad15_ Net-_U9-Pad16_ Net-_U10-Pad6_ Net-_U10-Pad7_ Net-_U10-Pad8_ Net-_U10-Pad9_ Net-_U10-Pad10_ Net-_U13-Pad1_ 133 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.cir.out new file mode 100644 index 00000000..22f9594a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.cir.out @@ -0,0 +1,53 @@ +* c:\users\shanthipriya\esim-workspace\13_nand_ic5\13_nand_ic5.cir + +.include 133.sub +* u9 a1 a2 a3 a4 a5 a6 a7 a8 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ adc_bridge_8 +* u13 net-_u13-pad1_ out dac_bridge_1 +v1 a1 gnd pulse(0 5 0 1n 1n 1u 2u) +v2 a2 gnd pulse(0 5 0 1n 1n 2u 4u) +v3 a3 gnd pulse(0 5 0 1n 1n 4u 8u) +v4 a4 gnd pulse(0 5 0 1n 1n 8u 16u) +v5 a5 gnd pulse(0 5 0 1n 1n 16u 32u) +v6 a6 gnd pulse(0 5 0 1n 1n 32u 64u) +v7 a7 gnd pulse(0 5 0 1n 1n 64u 128u) +v8 a8 gnd pulse(0 5 0 1n 1n 128u 256u) +* u17 out plot_v1 +* u1 a1 plot_v1 +* u2 a2 plot_v1 +* u3 a3 plot_v1 +* u4 a4 plot_v1 +* u5 a5 plot_v1 +* u6 a6 plot_v1 +* u7 a7 plot_v1 +* u8 a8 plot_v1 +* u10 a9 a10 a11 a12 a13 net-_u10-pad6_ net-_u10-pad7_ net-_u10-pad8_ net-_u10-pad9_ net-_u10-pad10_ adc_bridge_5 +v9 a9 gnd pulse(0 5 0 1n 1n 256u 512u) +v10 a10 gnd pulse(0 5 0 1n 1n 512u 1024u) +v11 a11 gnd pulse(0 5 0 1n 1n 1024u 2048u) +v12 a12 gnd pulse(0 5 0 1n 1n 2048u 4096u) +v13 a13 gnd pulse(0 5 0 1n 1n 4096u 16192u) +* u11 a13 plot_v1 +* u12 a12 plot_v1 +* u14 a11 plot_v1 +* u15 a10 plot_v1 +* u16 a9 plot_v1 +x1 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ net-_u10-pad6_ net-_u10-pad7_ net-_u10-pad8_ net-_u10-pad9_ net-_u10-pad10_ net-_u13-pad1_ 133 +a1 [a1 a2 a3 a4 a5 a6 a7 a8 ] [net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ ] u9 +a2 [net-_u13-pad1_ ] [out ] u13 +a3 [a9 a10 a11 a12 a13 ] [net-_u10-pad6_ net-_u10-pad7_ net-_u10-pad8_ net-_u10-pad9_ net-_u10-pad10_ ] u10 +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_5, NgSpice Name: adc_bridge +.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 1e-09 50e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out)+6 v(a1)+12v(a2)+18v(a3)+24 v(a4)+30 v(a5)+36 v(a6)+42 v(a7)+48 v(a8)+54 v(a13)+60 v(a12)+66 v(a11)+72 v(a10)+78 v(a9) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.pro b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.proj b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.proj new file mode 100644 index 00000000..05f0892c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.proj @@ -0,0 +1 @@ +schematicFile 13_nand_ic5.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.sch b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.sch new file mode 100644 index 00000000..0467bf1e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als133/sn54als133.sch @@ -0,0 +1,788 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio 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name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">8u</field5><field5 name="Period">16u</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">16u</field5><field5 name="Period">32u</field5></v5><v6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">32u</field5><field5 name="Period">64u</field5></v6><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">64u</field5><field5 name="Period">128u</field5></v7><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">128u</field5><field5 name="Period">256u</field5></v8><v9 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">256u</field5><field5 name="Period">512u</field5></v9><v10 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">512u</field5><field5 name="Period">1024u</field5></v10><v11 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">1024u</field5><field5 name="Period">2048u</field5></v11><v12 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">2048u</field5><field5 name="Period">4096u</field5></v12><v13 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">4096u</field5><field5 name="Period">16192u</field5></v13></source><model><u9 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u9><u13 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u13><u10 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\133</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">50</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ns</field5><field6 name="Stop Combo">us</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375-cache.lib new file mode 100644 index 00000000..c743d042 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.cir b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.cir new file mode 100644 index 00000000..c3a71da2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.cir @@ -0,0 +1,16 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375\4d_375.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/10/25 10:11:18 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ d_and +U4 Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad3_ d_and +U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad3_ d_nor +U6 Net-_U1-Pad3_ Net-_U1-Pad4_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.cir.out new file mode 100644 index 00000000..8f3125d0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.cir.out @@ -0,0 +1,32 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\4d_375\4d_375.cir + +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and +* u4 net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad3_ d_nor +* u6 net-_u1-pad3_ net-_u1-pad4_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 net-_u1-pad2_ net-_u2-pad2_ u2 +a2 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad2_ net-_u1-pad4_ ] net-_u4-pad3_ u4 +a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad3_ u5 +a5 net-_u1-pad3_ net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.pro b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.sch b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.sch new file mode 100644 index 00000000..fd00405b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.sch @@ -0,0 +1,192 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 681ED689 +P 3400 3450 +F 0 "U2" H 3400 3350 60 0000 C CNN +F 1 "d_inverter" H 3400 3600 60 0000 C CNN +F 2 "" H 3450 3400 60 0000 C CNN +F 3 "" H 3450 3400 60 0000 C CNN + 1 3400 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 681ED6AE +P 4550 2500 +F 0 "U3" H 4550 2500 60 0000 C CNN +F 1 "d_and" H 4600 2600 60 0000 C CNN +F 2 "" H 4550 2500 60 0000 C CNN +F 3 "" H 4550 2500 60 0000 C CNN + 1 4550 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 681ED6F1 +P 4550 3500 +F 0 "U4" H 4550 3500 60 0000 C CNN +F 1 "d_and" H 4600 3600 60 0000 C CNN +F 2 "" H 4550 3500 60 0000 C CNN +F 3 "" H 4550 3500 60 0000 C CNN + 1 4550 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 681ED73E +P 5750 3000 +F 0 "U5" H 5750 3000 60 0000 C CNN +F 1 "d_nor" H 5800 3100 60 0000 C CNN +F 2 "" H 5750 3000 60 0000 C CNN +F 3 "" H 5750 3000 60 0000 C CNN + 1 5750 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 681ED77D +P 7000 2950 +F 0 "U6" H 7000 2850 60 0000 C CNN +F 1 "d_inverter" H 7000 3100 60 0000 C CNN +F 2 "" H 7050 2900 60 0000 C CNN +F 3 "" H 7050 2900 60 0000 C CNN + 1 7000 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 3450 2300 3450 +Wire Wire Line + 4100 2500 2800 2500 +Wire Wire Line + 2800 2500 2800 3450 +Connection ~ 2800 3450 +Wire Wire Line + 4100 2400 2200 2400 +Wire Wire Line + 3700 3450 4100 3450 +Wire Wire Line + 4100 3450 4100 3400 +Wire Wire Line + 7300 2950 7900 2950 +Wire Wire Line + 4100 3500 4100 4150 +Wire Wire Line + 4100 4150 7500 4150 +Wire Wire Line + 7500 4150 7500 2950 +Connection ~ 7500 2950 +Wire Wire Line + 6200 2950 6700 2950 +Wire Wire Line + 5000 2450 5300 2450 +Wire Wire Line + 5300 2450 5300 2900 +Wire Wire Line + 5000 3450 5300 3450 +Wire Wire Line + 5300 3450 5300 3000 +Wire Wire Line + 6450 2950 6450 2350 +Wire Wire Line + 6450 2350 7900 2350 +Connection ~ 6450 2950 +$Comp +L PORT U1 +U 1 1 681ED8C7 +P 1950 2400 +F 0 "U1" H 2000 2500 30 0000 C CNN +F 1 "PORT" H 1950 2400 30 0000 C CNN +F 2 "" H 1950 2400 60 0000 C CNN +F 3 "" H 1950 2400 60 0000 C CNN + 1 1950 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 681ED912 +P 2050 3450 +F 0 "U1" H 2100 3550 30 0000 C CNN +F 1 "PORT" H 2050 3450 30 0000 C CNN +F 2 "" H 2050 3450 60 0000 C CNN +F 3 "" H 2050 3450 60 0000 C CNN + 2 2050 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 681ED949 +P 8150 2350 +F 0 "U1" H 8200 2450 30 0000 C CNN +F 1 "PORT" H 8150 2350 30 0000 C CNN +F 2 "" H 8150 2350 60 0000 C CNN +F 3 "" H 8150 2350 60 0000 C CNN + 3 8150 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 681ED9BE +P 8150 2950 +F 0 "U1" H 8200 3050 30 0000 C CNN +F 1 "PORT" H 8150 2950 30 0000 C CNN +F 2 "" H 8150 2950 60 0000 C CNN +F 3 "" H 8150 2950 60 0000 C CNN + 4 8150 2950 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.sub b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.sub new file mode 100644 index 00000000..e39abdd0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375.sub @@ -0,0 +1,26 @@ +* Subcircuit 4d_375 +.subckt 4d_375 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\4d_375\4d_375.cir +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and +* u4 net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad3_ d_nor +* u6 net-_u1-pad3_ net-_u1-pad4_ d_inverter +a1 net-_u1-pad2_ net-_u2-pad2_ u2 +a2 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad2_ net-_u1-pad4_ ] net-_u4-pad3_ u4 +a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad3_ u5 +a5 net-_u1-pad3_ net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 4d_375
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375_Previous_Values.xml new file mode 100644 index 00000000..eb73ebcf --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/4d_375_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54als573/analysis new file mode 100644 index 00000000..df2a21bc --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/analysis @@ -0,0 +1 @@ +.tran 10e-06 100e-03 0e-09
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373-cache.lib new file mode 100644 index 00000000..3965bcb6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_l +# +DEF d_l X 0 40 Y Y 1 F N +F0 "X" 0 -400 60 H V C CNN +F1 "d_l" 0 450 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 300 400 -300 -300 0 1 0 N +X D 1 -500 300 200 R 50 50 1 1 I +X E 2 -500 -150 200 R 50 50 1 1 I +X Qbar 3 500 300 200 L 50 50 1 1 O +X Q 4 500 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.cir b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.cir new file mode 100644 index 00000000..2aa1c47b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.cir @@ -0,0 +1,28 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\ls373\ls373.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/12/25 07:42:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad3_ Net-_U2-Pad2_ ? Net-_U3-Pad2_ d_l +X2 Net-_U1-Pad4_ Net-_U2-Pad2_ ? Net-_U4-Pad2_ d_l +X3 Net-_U1-Pad5_ Net-_U2-Pad2_ ? Net-_U5-Pad2_ d_l +X4 Net-_U1-Pad6_ Net-_U2-Pad2_ ? Net-_U6-Pad2_ d_l +X5 Net-_U1-Pad7_ Net-_U2-Pad2_ ? Net-_U7-Pad2_ d_l +X6 Net-_U1-Pad8_ Net-_U2-Pad2_ ? Net-_U8-Pad2_ d_l +X7 Net-_U1-Pad9_ Net-_U2-Pad2_ ? Net-_U9-Pad2_ d_l +X8 Net-_U1-Pad10_ Net-_U2-Pad2_ ? Net-_U10-Pad2_ d_l +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad11_ d_and +U4 Net-_U1-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad12_ d_and +U5 Net-_U1-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad13_ d_and +U6 Net-_U1-Pad2_ Net-_U6-Pad2_ Net-_U1-Pad14_ d_and +U7 Net-_U1-Pad2_ Net-_U7-Pad2_ Net-_U1-Pad15_ d_and +U8 Net-_U1-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad16_ d_and +U9 Net-_U1-Pad2_ Net-_U9-Pad2_ Net-_U1-Pad17_ d_and +U10 Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U1-Pad18_ d_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.cir.out new file mode 100644 index 00000000..2b95c412 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.cir.out @@ -0,0 +1,57 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\ls373\ls373.cir + +.include 4d_375.sub +x1 net-_u1-pad3_ net-_u2-pad2_ ? net-_u3-pad2_ 4d_375 +x2 net-_u1-pad4_ net-_u2-pad2_ ? net-_u4-pad2_ 4d_375 +x3 net-_u1-pad5_ net-_u2-pad2_ ? net-_u5-pad2_ 4d_375 +x4 net-_u1-pad6_ net-_u2-pad2_ ? net-_u6-pad2_ 4d_375 +x5 net-_u1-pad7_ net-_u2-pad2_ ? net-_u7-pad2_ 4d_375 +x6 net-_u1-pad8_ net-_u2-pad2_ ? net-_u8-pad2_ 4d_375 +x7 net-_u1-pad9_ net-_u2-pad2_ ? net-_u9-pad2_ 4d_375 +x8 net-_u1-pad10_ net-_u2-pad2_ ? net-_u10-pad2_ 4d_375 +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +* u3 net-_u1-pad2_ net-_u3-pad2_ net-_u1-pad11_ d_and +* u4 net-_u1-pad2_ net-_u4-pad2_ net-_u1-pad12_ d_and +* u5 net-_u1-pad2_ net-_u5-pad2_ net-_u1-pad13_ d_and +* u6 net-_u1-pad2_ net-_u6-pad2_ net-_u1-pad14_ d_and +* u7 net-_u1-pad2_ net-_u7-pad2_ net-_u1-pad15_ d_and +* u8 net-_u1-pad2_ net-_u8-pad2_ net-_u1-pad16_ d_and +* u9 net-_u1-pad2_ net-_u9-pad2_ net-_u1-pad17_ d_and +* u10 net-_u1-pad2_ net-_u10-pad2_ net-_u1-pad18_ d_and +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 [net-_u1-pad2_ net-_u3-pad2_ ] net-_u1-pad11_ u3 +a3 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u1-pad12_ u4 +a4 [net-_u1-pad2_ net-_u5-pad2_ ] net-_u1-pad13_ u5 +a5 [net-_u1-pad2_ net-_u6-pad2_ ] net-_u1-pad14_ u6 +a6 [net-_u1-pad2_ net-_u7-pad2_ ] net-_u1-pad15_ u7 +a7 [net-_u1-pad2_ net-_u8-pad2_ ] net-_u1-pad16_ u8 +a8 [net-_u1-pad2_ net-_u9-pad2_ ] net-_u1-pad17_ u9 +a9 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u1-pad18_ u10 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.pro b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.sch b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.sch new file mode 100644 index 00000000..98e8421d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.sch @@ -0,0 +1,574 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ls373-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_l X1 +U 1 1 681F460C +P 5750 1300 +F 0 "X1" H 5750 900 60 0000 C CNN +F 1 "d_l" H 5750 1750 60 0000 C CNN +F 2 "" H 5750 1300 60 0001 C CNN +F 3 "" H 5750 1300 60 0001 C CNN + 1 5750 1300 + 1 0 0 -1 +$EndComp +$Comp +L d_l X2 +U 1 1 681F4668 +P 5750 2050 +F 0 "X2" H 5750 1650 60 0000 C CNN +F 1 "d_l" H 5750 2500 60 0000 C CNN +F 2 "" H 5750 2050 60 0001 C CNN +F 3 "" H 5750 2050 60 0001 C CNN + 1 5750 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_l X3 +U 1 1 681F471D +P 5750 2800 +F 0 "X3" H 5750 2400 60 0000 C CNN +F 1 "d_l" H 5750 3250 60 0000 C CNN +F 2 "" H 5750 2800 60 0001 C CNN +F 3 "" H 5750 2800 60 0001 C CNN + 1 5750 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_l X4 +U 1 1 681F4723 +P 5750 3550 +F 0 "X4" H 5750 3150 60 0000 C CNN +F 1 "d_l" H 5750 4000 60 0000 C CNN +F 2 "" H 5750 3550 60 0001 C CNN +F 3 "" H 5750 3550 60 0001 C CNN + 1 5750 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_l X5 +U 1 1 681F4C25 +P 5750 4300 +F 0 "X5" H 5750 3900 60 0000 C CNN +F 1 "d_l" H 5750 4750 60 0000 C CNN +F 2 "" H 5750 4300 60 0001 C CNN +F 3 "" H 5750 4300 60 0001 C CNN + 1 5750 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_l X6 +U 1 1 681F4C2B +P 5750 5050 +F 0 "X6" H 5750 4650 60 0000 C CNN +F 1 "d_l" H 5750 5500 60 0000 C CNN +F 2 "" H 5750 5050 60 0001 C CNN +F 3 "" H 5750 5050 60 0001 C CNN + 1 5750 5050 + 1 0 0 -1 +$EndComp +$Comp +L d_l X7 +U 1 1 681F4C31 +P 5750 5800 +F 0 "X7" H 5750 5400 60 0000 C CNN +F 1 "d_l" H 5750 6250 60 0000 C CNN +F 2 "" H 5750 5800 60 0001 C CNN +F 3 "" H 5750 5800 60 0001 C CNN + 1 5750 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_l X8 +U 1 1 681F4C37 +P 5750 6550 +F 0 "X8" H 5750 6150 60 0000 C CNN +F 1 "d_l" H 5750 7000 60 0000 C CNN +F 2 "" H 5750 6550 60 0001 C CNN +F 3 "" H 5750 6550 60 0001 C CNN + 1 5750 6550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 6700 4800 6700 +Wire Wire Line + 4800 6700 4800 600 +Wire Wire Line + 5250 1450 4800 1450 +Connection ~ 4800 1450 +Wire Wire Line + 5250 2200 4800 2200 +Connection ~ 4800 2200 +Wire Wire Line + 5250 2950 4800 2950 +Connection ~ 4800 2950 +Wire Wire Line + 5250 3700 4800 3700 +Connection ~ 4800 3700 +Wire Wire Line + 5250 4450 4800 4450 +Connection ~ 4800 4450 +Wire Wire Line + 5250 5200 4800 5200 +Connection ~ 4800 5200 +Wire Wire Line + 5250 5950 4800 5950 +Connection ~ 4800 5950 +Wire Wire Line + 7400 1450 8000 1450 +Wire Wire Line + 7400 2200 8000 2200 +Wire Wire Line + 7400 2950 8000 2950 +Wire Wire Line + 7400 3700 8000 3700 +Wire Wire Line + 7400 4450 8000 4450 +Wire Wire Line + 7400 5200 8000 5200 +Wire Wire Line + 7400 5950 8000 5950 +Wire Wire Line + 7400 6700 8000 6700 +$Comp +L d_inverter U2 +U 1 1 681F58CB +P 4500 600 +F 0 "U2" H 4500 500 60 0000 C CNN +F 1 "d_inverter" H 4500 750 60 0000 C CNN +F 2 "" H 4550 550 60 0000 C CNN +F 3 "" H 4550 550 60 0000 C CNN + 1 4500 600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 1000 4450 1000 +Wire Wire Line + 5250 1750 4450 1750 +Wire Wire Line + 5250 2500 4450 2500 +Wire Wire Line + 5250 3250 4450 3250 +Wire Wire Line + 5250 4000 4450 4000 +Wire Wire Line + 5250 4750 4450 4750 +Wire Wire Line + 5250 5500 4450 5500 +Wire Wire Line + 5250 6250 4450 6250 +$Comp +L PORT U1 +U 1 1 681F5EC8 +P 3950 600 +F 0 "U1" H 4000 700 30 0000 C CNN +F 1 "PORT" H 3950 600 30 0000 C CNN +F 2 "" H 3950 600 60 0000 C CNN +F 3 "" H 3950 600 60 0000 C CNN + 1 3950 600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 681F5F68 +P 4200 1000 +F 0 "U1" H 4250 1100 30 0000 C CNN +F 1 "PORT" H 4200 1000 30 0000 C CNN +F 2 "" H 4200 1000 60 0000 C CNN +F 3 "" H 4200 1000 60 0000 C CNN + 3 4200 1000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 681F5FAB +P 4200 1750 +F 0 "U1" H 4250 1850 30 0000 C CNN +F 1 "PORT" H 4200 1750 30 0000 C CNN +F 2 "" H 4200 1750 60 0000 C CNN +F 3 "" H 4200 1750 60 0000 C CNN + 4 4200 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 681F5FEA +P 4200 2500 +F 0 "U1" H 4250 2600 30 0000 C CNN +F 1 "PORT" H 4200 2500 30 0000 C CNN +F 2 "" H 4200 2500 60 0000 C CNN +F 3 "" H 4200 2500 60 0000 C CNN + 5 4200 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 681F602B +P 4200 3250 +F 0 "U1" H 4250 3350 30 0000 C CNN +F 1 "PORT" H 4200 3250 30 0000 C CNN +F 2 "" H 4200 3250 60 0000 C CNN +F 3 "" H 4200 3250 60 0000 C CNN + 6 4200 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 681F606E +P 4200 4000 +F 0 "U1" H 4250 4100 30 0000 C CNN +F 1 "PORT" H 4200 4000 30 0000 C CNN +F 2 "" H 4200 4000 60 0000 C CNN +F 3 "" H 4200 4000 60 0000 C CNN + 7 4200 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 681F60B5 +P 4200 4750 +F 0 "U1" H 4250 4850 30 0000 C CNN +F 1 "PORT" H 4200 4750 30 0000 C CNN +F 2 "" H 4200 4750 60 0000 C CNN +F 3 "" H 4200 4750 60 0000 C CNN + 8 4200 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 681F60FC +P 4200 5500 +F 0 "U1" H 4250 5600 30 0000 C CNN +F 1 "PORT" H 4200 5500 30 0000 C CNN +F 2 "" H 4200 5500 60 0000 C CNN +F 3 "" H 4200 5500 60 0000 C CNN + 9 4200 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 681F6188 +P 4200 6250 +F 0 "U1" H 4250 6350 30 0000 C CNN +F 1 "PORT" H 4200 6250 30 0000 C CNN +F 2 "" H 4200 6250 60 0000 C CNN +F 3 "" H 4200 6250 60 0000 C CNN + 10 4200 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 681F64D3 +P 8250 1450 +F 0 "U1" H 8300 1550 30 0000 C CNN +F 1 "PORT" H 8250 1450 30 0000 C CNN +F 2 "" H 8250 1450 60 0000 C CNN +F 3 "" H 8250 1450 60 0000 C CNN + 11 8250 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 681F652E +P 8250 2200 +F 0 "U1" H 8300 2300 30 0000 C CNN +F 1 "PORT" H 8250 2200 30 0000 C CNN +F 2 "" H 8250 2200 60 0000 C CNN +F 3 "" H 8250 2200 60 0000 C CNN + 12 8250 2200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 681F658D +P 8250 2950 +F 0 "U1" H 8300 3050 30 0000 C CNN +F 1 "PORT" H 8250 2950 30 0000 C CNN +F 2 "" H 8250 2950 60 0000 C CNN +F 3 "" H 8250 2950 60 0000 C CNN + 13 8250 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 681F65EE +P 8250 3700 +F 0 "U1" H 8300 3800 30 0000 C CNN +F 1 "PORT" H 8250 3700 30 0000 C CNN +F 2 "" H 8250 3700 60 0000 C CNN +F 3 "" H 8250 3700 60 0000 C CNN + 14 8250 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 681F6653 +P 8250 4450 +F 0 "U1" H 8300 4550 30 0000 C CNN +F 1 "PORT" H 8250 4450 30 0000 C CNN +F 2 "" H 8250 4450 60 0000 C CNN +F 3 "" H 8250 4450 60 0000 C CNN + 15 8250 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 681F66C6 +P 8250 5200 +F 0 "U1" H 8300 5300 30 0000 C CNN +F 1 "PORT" H 8250 5200 30 0000 C CNN +F 2 "" H 8250 5200 60 0000 C CNN +F 3 "" H 8250 5200 60 0000 C CNN + 16 8250 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 681F6731 +P 8250 5950 +F 0 "U1" H 8300 6050 30 0000 C CNN +F 1 "PORT" H 8250 5950 30 0000 C CNN +F 2 "" H 8250 5950 60 0000 C CNN +F 3 "" H 8250 5950 60 0000 C CNN + 17 8250 5950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 18 1 681F67A4 +P 8250 6700 +F 0 "U1" H 8300 6800 30 0000 C CNN +F 1 "PORT" H 8250 6700 30 0000 C CNN +F 2 "" H 8250 6700 60 0000 C CNN +F 3 "" H 8250 6700 60 0000 C CNN + 18 8250 6700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 68215E7A +P 3950 800 +F 0 "U1" H 4000 900 30 0000 C CNN +F 1 "PORT" H 3950 800 30 0000 C CNN +F 2 "" H 3950 800 60 0000 C CNN +F 3 "" H 3950 800 60 0000 C CNN + 2 3950 800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 800 6850 800 +Wire Wire Line + 6850 800 6850 6250 +$Comp +L d_and U3 +U 1 1 68215F4D +P 6950 1450 +F 0 "U3" H 6950 1450 60 0000 C CNN +F 1 "d_and" H 7000 1550 60 0000 C CNN +F 2 "" H 6950 1450 60 0000 C CNN +F 3 "" H 6950 1450 60 0000 C CNN + 1 6950 1450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 1000 6500 1000 +Wire Wire Line + 6500 1000 6500 1350 +Wire Wire Line + 6500 1450 6250 1450 +Wire Wire Line + 7400 1400 7400 1450 +$Comp +L d_and U4 +U 1 1 682160E0 +P 6950 2200 +F 0 "U4" H 6950 2200 60 0000 C CNN +F 1 "d_and" H 7000 2300 60 0000 C CNN +F 2 "" H 6950 2200 60 0000 C CNN +F 3 "" H 6950 2200 60 0000 C CNN + 1 6950 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 1750 6500 2100 +Wire Wire Line + 6500 2200 6250 2200 +Wire Wire Line + 7400 2150 7400 2200 +Wire Wire Line + 6850 1750 6500 1750 +Connection ~ 6850 1000 +$Comp +L d_and U5 +U 1 1 68216224 +P 6950 2950 +F 0 "U5" H 6950 2950 60 0000 C CNN +F 1 "d_and" H 7000 3050 60 0000 C CNN +F 2 "" H 6950 2950 60 0000 C CNN +F 3 "" H 6950 2950 60 0000 C CNN + 1 6950 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 2500 6500 2850 +Wire Wire Line + 6500 2950 6250 2950 +Wire Wire Line + 6850 2500 6500 2500 +Connection ~ 6850 1750 +Wire Wire Line + 7400 2900 7400 2950 +$Comp +L d_and U6 +U 1 1 68216384 +P 6950 3700 +F 0 "U6" H 6950 3700 60 0000 C CNN +F 1 "d_and" H 7000 3800 60 0000 C CNN +F 2 "" H 6950 3700 60 0000 C CNN +F 3 "" H 6950 3700 60 0000 C CNN + 1 6950 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 3250 6500 3600 +Wire Wire Line + 6500 3700 6250 3700 +Wire Wire Line + 7400 3650 7400 3700 +Wire Wire Line + 6850 3250 6500 3250 +Connection ~ 6850 2500 +$Comp +L d_and U7 +U 1 1 68216E4F +P 6950 4450 +F 0 "U7" H 6950 4450 60 0000 C CNN +F 1 "d_and" H 7000 4550 60 0000 C CNN +F 2 "" H 6950 4450 60 0000 C CNN +F 3 "" H 6950 4450 60 0000 C CNN + 1 6950 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 4000 6500 4350 +Wire Wire Line + 6500 4450 6250 4450 +Wire Wire Line + 7400 4400 7400 4450 +Wire Wire Line + 6850 4000 6500 4000 +Connection ~ 6850 3250 +$Comp +L d_and U8 +U 1 1 68216F80 +P 6950 5200 +F 0 "U8" H 6950 5200 60 0000 C CNN +F 1 "d_and" H 7000 5300 60 0000 C CNN +F 2 "" H 6950 5200 60 0000 C CNN +F 3 "" H 6950 5200 60 0000 C CNN + 1 6950 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 4750 6500 5100 +Wire Wire Line + 6500 5200 6250 5200 +Wire Wire Line + 7400 5150 7400 5200 +Wire Wire Line + 6850 4750 6500 4750 +Connection ~ 6850 4000 +$Comp +L d_and U9 +U 1 1 6821710F +P 6950 5950 +F 0 "U9" H 6950 5950 60 0000 C CNN +F 1 "d_and" H 7000 6050 60 0000 C CNN +F 2 "" H 6950 5950 60 0000 C CNN +F 3 "" H 6950 5950 60 0000 C CNN + 1 6950 5950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 5500 6500 5850 +Wire Wire Line + 6500 5950 6250 5950 +Wire Wire Line + 7400 5900 7400 5950 +Wire Wire Line + 6850 5500 6500 5500 +Connection ~ 6850 4750 +$Comp +L d_and U10 +U 1 1 682172A8 +P 6950 6700 +F 0 "U10" H 6950 6700 60 0000 C CNN +F 1 "d_and" H 7000 6800 60 0000 C CNN +F 2 "" H 6950 6700 60 0000 C CNN +F 3 "" H 6950 6700 60 0000 C CNN + 1 6950 6700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 6250 6500 6600 +Wire Wire Line + 6500 6700 6250 6700 +Wire Wire Line + 7400 6650 7400 6700 +Wire Wire Line + 6850 6250 6500 6250 +Connection ~ 6850 5500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.sub b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.sub new file mode 100644 index 00000000..4a7b2475 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373.sub @@ -0,0 +1,51 @@ +* Subcircuit ls373 +.subckt ls373 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\ls373\ls373.cir +.include 4d_375.sub +x1 net-_u1-pad3_ net-_u2-pad2_ ? net-_u3-pad2_ 4d_375 +x2 net-_u1-pad4_ net-_u2-pad2_ ? net-_u4-pad2_ 4d_375 +x3 net-_u1-pad5_ net-_u2-pad2_ ? net-_u5-pad2_ 4d_375 +x4 net-_u1-pad6_ net-_u2-pad2_ ? net-_u6-pad2_ 4d_375 +x5 net-_u1-pad7_ net-_u2-pad2_ ? net-_u7-pad2_ 4d_375 +x6 net-_u1-pad8_ net-_u2-pad2_ ? net-_u8-pad2_ 4d_375 +x7 net-_u1-pad9_ net-_u2-pad2_ ? net-_u9-pad2_ 4d_375 +x8 net-_u1-pad10_ net-_u2-pad2_ ? net-_u10-pad2_ 4d_375 +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ net-_u1-pad11_ d_and +* u4 net-_u1-pad2_ net-_u4-pad2_ net-_u1-pad12_ d_and +* u5 net-_u1-pad2_ net-_u5-pad2_ net-_u1-pad13_ d_and +* u6 net-_u1-pad2_ net-_u6-pad2_ net-_u1-pad14_ d_and +* u7 net-_u1-pad2_ net-_u7-pad2_ net-_u1-pad15_ d_and +* u8 net-_u1-pad2_ net-_u8-pad2_ net-_u1-pad16_ d_and +* u9 net-_u1-pad2_ net-_u9-pad2_ net-_u1-pad17_ d_and +* u10 net-_u1-pad2_ net-_u10-pad2_ net-_u1-pad18_ d_and +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 [net-_u1-pad2_ net-_u3-pad2_ ] net-_u1-pad11_ u3 +a3 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u1-pad12_ u4 +a4 [net-_u1-pad2_ net-_u5-pad2_ ] net-_u1-pad13_ u5 +a5 [net-_u1-pad2_ net-_u6-pad2_ ] net-_u1-pad14_ u6 +a6 [net-_u1-pad2_ net-_u7-pad2_ ] net-_u1-pad15_ u7 +a7 [net-_u1-pad2_ net-_u8-pad2_ ] net-_u1-pad16_ u8 +a8 [net-_u1-pad2_ net-_u9-pad2_ ] net-_u1-pad17_ u9 +a9 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u1-pad18_ u10 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends ls373
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373_Previous_Values.xml new file mode 100644 index 00000000..dd6b790d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/ls373_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x2><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x3><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x4><x5><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x5><x6><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x6><x7><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x7><x8><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4d_375</field></x8></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573-cache.lib new file mode 100644 index 00000000..2ac1dc3f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573-cache.lib @@ -0,0 +1,172 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# ls573 +# +DEF ls573 x 0 40 Y Y 1 F N +F0 "x" 50 -300 60 H V C CNN +F1 "ls573" 0 1050 60 H V C CNN +F2 "" 0 1050 60 H I C CNN +F3 "" 0 1050 60 H I C CNN +DRAW +S 400 900 -400 -250 0 1 0 N +X OE 1 -600 800 200 R 50 50 1 1 I +X LE 2 -600 700 200 R 50 50 1 1 I +X 1D 3 -600 550 200 R 50 50 1 1 I +X 2D 4 -600 450 200 R 50 50 1 1 I +X 3D 5 -600 350 200 R 50 50 1 1 I +X 4D 6 -600 250 200 R 50 50 1 1 I +X 5D 7 -600 150 200 R 50 50 1 1 I +X 6D 8 -600 50 200 R 50 50 1 1 I +X 7D 9 -600 -50 200 R 50 50 1 1 I +X 8D 10 -600 -150 200 R 50 50 1 1 I +X 1Q 11 600 800 200 L 50 50 1 1 O +X 2Q 12 600 700 200 L 50 50 1 1 O +X 3Q 13 600 600 200 L 50 50 1 1 O +X 4Q 14 600 500 200 L 50 50 1 1 O +X 5Q 15 600 400 200 L 50 50 1 1 O +X 6Q 16 600 300 200 L 50 50 1 1 O +X 7Q 17 600 200 200 L 50 50 1 1 O +X 8Q 18 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.cir b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.cir new file mode 100644 index 00000000..ddc2f6a5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.cir @@ -0,0 +1,32 @@ +* C:\Users\Shanthipriya\eSim-Workspace\74ls573\74ls573.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/30/25 14:02:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 1D 2D 3D 4D 5D 6D 7D 8D Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8 +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q dac_bridge_8 +U1 oe LE Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2 +v3 1D GND pulse +v4 2D GND pulse +v5 3D GND pulse +v6 4D GND pulse +v7 5D GND pulse +v8 6D GND pulse +v9 7D GND pulse +v10 8D GND pulse +U4 1Q plot_v1 +U5 2Q plot_v1 +U6 3Q plot_v1 +U7 4Q plot_v1 +U8 5Q plot_v1 +U9 6Q plot_v1 +U10 7Q plot_v1 +U11 8Q plot_v1 +x1 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ ls573 +v1 oe GND DC +v2 LE GND DC + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.cir.out new file mode 100644 index 00000000..2b090dc7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.cir.out @@ -0,0 +1,51 @@ +* c:\users\shanthipriya\esim-workspace\74ls573\74ls573.cir + +.include ls373.sub +* u2 1d 2d 3d 4d 5d 6d 7d 8d net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ 1q 2q 3q 4q 5q 6q 7q 8q dac_bridge_8 +* u1 oe le net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2 +v3 1d gnd pulse(0 5 0 1u 1u 4m 8m) +v4 2d gnd pulse(0 5 0m 1u 1u 4m 8m) +v5 3d gnd pulse(0 5 0 1u 1u 4m 8m) +v6 4d gnd pulse(0 5 0 1u 1u 4m 8m) +v7 5d gnd pulse(0 5 0 1u 1u 4m 8m) +v8 6d gnd pulse(0 5 0 1u 1u 4m 8m) +v9 7d gnd pulse(0 5 0 1u 1u 4m 8m) +v10 8d gnd pulse(0 5 0 1u 1u 4m 8m) +* u4 1q plot_v1 +* u5 2q plot_v1 +* u6 3q plot_v1 +* u7 4q plot_v1 +* u8 5q plot_v1 +* u9 6q plot_v1 +* u10 7q plot_v1 +* u11 8q plot_v1 +x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ls373 +v1 oe gnd dc 0 +v2 le gnd dc 5 +a1 [1d 2d 3d 4d 5d 6d 7d 8d ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a2 [net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] [1q 2q 3q 4q 5q 6q 7q 8q ] u3 +a3 [oe le ] [net-_u1-pad3_ net-_u1-pad4_ ] u1 +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 10e-06 100e-03 0e-09 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(1q) +plot v(2q) +plot v(3q) +plot v(4q) +plot v(5q) +plot v(6q) +plot v(7q) +plot v(8q) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.pro b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.proj b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.proj new file mode 100644 index 00000000..a51ca27b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.proj @@ -0,0 +1 @@ +schematicFile 74ls373.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.sch b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.sch new file mode 100644 index 00000000..0ca11790 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573.sch @@ -0,0 +1,614 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74ls573-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L adc_bridge_8 U2 +U 1 1 681F4F2B +P 4400 3000 +F 0 "U2" H 4400 3000 60 0000 C CNN +F 1 "adc_bridge_8" H 4400 3150 60 0000 C CNN +F 2 "" H 4400 3000 60 0000 C CNN +F 3 "" H 4400 3000 60 0000 C CNN + 1 4400 3000 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_8 U3 +U 1 1 681F4F66 +P 6750 2750 +F 0 "U3" H 6750 2750 60 0000 C CNN +F 1 "dac_bridge_8" H 6750 2900 60 0000 C CNN +F 2 "" H 6750 2750 60 0000 C CNN +F 3 "" H 6750 2750 60 0000 C CNN + 1 6750 2750 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U1 +U 1 1 681F4FB3 +P 4400 2700 +F 0 "U1" H 4400 2700 60 0000 C CNN +F 1 "adc_bridge_2" H 4400 2850 60 0000 C CNN +F 2 "" H 4400 2700 60 0000 C CNN +F 3 "" H 4400 2700 60 0000 C CNN + 1 4400 2700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 681F5109 +P 750 3900 +F 0 "#PWR01" H 750 3650 50 0001 C CNN +F 1 "GND" H 750 3750 50 0000 C CNN +F 2 "" H 750 3900 50 0001 C CNN +F 3 "" H 750 3900 50 0001 C CNN + 1 750 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 681F5129 +P 1150 4150 +F 0 "#PWR02" H 1150 3900 50 0001 C CNN +F 1 "GND" H 1150 4000 50 0000 C CNN +F 2 "" H 1150 4150 50 0001 C CNN +F 3 "" H 1150 4150 50 0001 C CNN + 1 1150 4150 + 1 0 0 -1 +$EndComp +$Comp +L pulse v3 +U 1 1 681F5173 +P 1500 4850 +F 0 "v3" H 1300 4950 60 0000 C CNN +F 1 "pulse" H 1300 4800 60 0000 C CNN +F 2 "R1" H 1200 4850 60 0000 C CNN +F 3 "" H 1500 4850 60 0000 C CNN + 1 1500 4850 + 1 0 0 -1 +$EndComp +$Comp +L pulse v4 +U 1 1 681F51F8 +P 1900 4850 +F 0 "v4" H 1700 4950 60 0000 C CNN +F 1 "pulse" H 1700 4800 60 0000 C CNN +F 2 "R1" H 1600 4850 60 0000 C CNN +F 3 "" H 1900 4850 60 0000 C CNN + 1 1900 4850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 681F5233 +P 1500 5550 +F 0 "#PWR03" H 1500 5300 50 0001 C CNN +F 1 "GND" H 1500 5400 50 0000 C CNN +F 2 "" H 1500 5550 50 0001 C CNN +F 3 "" H 1500 5550 50 0001 C CNN + 1 1500 5550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 681F5257 +P 1900 5550 +F 0 "#PWR04" H 1900 5300 50 0001 C CNN +F 1 "GND" H 1900 5400 50 0000 C CNN +F 2 "" H 1900 5550 50 0001 C CNN +F 3 "" H 1900 5550 50 0001 C CNN + 1 1900 5550 + 1 0 0 -1 +$EndComp +$Comp +L pulse v5 +U 1 1 681F52DE +P 2300 4850 +F 0 "v5" H 2100 4950 60 0000 C CNN +F 1 "pulse" H 2100 4800 60 0000 C CNN +F 2 "R1" H 2000 4850 60 0000 C CNN +F 3 "" H 2300 4850 60 0000 C CNN + 1 2300 4850 + 1 0 0 -1 +$EndComp +$Comp +L pulse v6 +U 1 1 681F52E4 +P 2700 4850 +F 0 "v6" H 2500 4950 60 0000 C CNN +F 1 "pulse" H 2500 4800 60 0000 C CNN +F 2 "R1" H 2400 4850 60 0000 C CNN +F 3 "" H 2700 4850 60 0000 C CNN + 1 2700 4850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 681F52EA +P 2300 5550 +F 0 "#PWR05" H 2300 5300 50 0001 C CNN +F 1 "GND" H 2300 5400 50 0000 C CNN +F 2 "" H 2300 5550 50 0001 C CNN +F 3 "" H 2300 5550 50 0001 C CNN + 1 2300 5550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 681F52F0 +P 2700 5550 +F 0 "#PWR06" H 2700 5300 50 0001 C CNN +F 1 "GND" H 2700 5400 50 0000 C CNN +F 2 "" H 2700 5550 50 0001 C CNN +F 3 "" H 2700 5550 50 0001 C CNN + 1 2700 5550 + 1 0 0 -1 +$EndComp +$Comp +L pulse v7 +U 1 1 681F5390 +P 3100 4850 +F 0 "v7" H 2900 4950 60 0000 C CNN +F 1 "pulse" H 2900 4800 60 0000 C CNN +F 2 "R1" H 2800 4850 60 0000 C CNN +F 3 "" H 3100 4850 60 0000 C CNN + 1 3100 4850 + 1 0 0 -1 +$EndComp +$Comp +L pulse v8 +U 1 1 681F5396 +P 3500 4850 +F 0 "v8" H 3300 4950 60 0000 C CNN +F 1 "pulse" H 3300 4800 60 0000 C CNN +F 2 "R1" H 3200 4850 60 0000 C CNN +F 3 "" H 3500 4850 60 0000 C CNN + 1 3500 4850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 681F539C +P 3100 5550 +F 0 "#PWR07" H 3100 5300 50 0001 C CNN +F 1 "GND" H 3100 5400 50 0000 C CNN +F 2 "" H 3100 5550 50 0001 C CNN +F 3 "" H 3100 5550 50 0001 C CNN + 1 3100 5550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 681F53A2 +P 3500 5550 +F 0 "#PWR08" H 3500 5300 50 0001 C CNN +F 1 "GND" H 3500 5400 50 0000 C CNN +F 2 "" H 3500 5550 50 0001 C CNN +F 3 "" H 3500 5550 50 0001 C CNN + 1 3500 5550 + 1 0 0 -1 +$EndComp +$Comp +L pulse v9 +U 1 1 681F53AA +P 3900 4850 +F 0 "v9" H 3700 4950 60 0000 C CNN +F 1 "pulse" H 3700 4800 60 0000 C CNN +F 2 "R1" H 3600 4850 60 0000 C CNN +F 3 "" H 3900 4850 60 0000 C CNN + 1 3900 4850 + 1 0 0 -1 +$EndComp +$Comp +L pulse v10 +U 1 1 681F53B0 +P 4300 4850 +F 0 "v10" H 4100 4950 60 0000 C CNN +F 1 "pulse" H 4100 4800 60 0000 C CNN +F 2 "R1" H 4000 4850 60 0000 C CNN +F 3 "" H 4300 4850 60 0000 C CNN + 1 4300 4850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR09 +U 1 1 681F53B6 +P 3900 5550 +F 0 "#PWR09" H 3900 5300 50 0001 C CNN +F 1 "GND" H 3900 5400 50 0000 C CNN +F 2 "" H 3900 5550 50 0001 C CNN +F 3 "" H 3900 5550 50 0001 C CNN + 1 3900 5550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR010 +U 1 1 681F53BC +P 4300 5550 +F 0 "#PWR010" H 4300 5300 50 0001 C CNN +F 1 "GND" H 4300 5400 50 0000 C CNN +F 2 "" H 4300 5550 50 0001 C CNN +F 3 "" H 4300 5550 50 0001 C CNN + 1 4300 5550 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 681F551B +P 7700 2900 +F 0 "U4" H 7700 3400 60 0000 C CNN +F 1 "plot_v1" H 7900 3250 60 0000 C CNN +F 2 "" H 7700 2900 60 0000 C CNN +F 3 "" H 7700 2900 60 0000 C CNN + 1 7700 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 681F5580 +P 8100 2900 +F 0 "U5" H 8100 3400 60 0000 C CNN +F 1 "plot_v1" H 8300 3250 60 0000 C CNN +F 2 "" H 8100 2900 60 0000 C CNN +F 3 "" H 8100 2900 60 0000 C CNN + 1 8100 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 681F55C9 +P 8450 2900 +F 0 "U6" H 8450 3400 60 0000 C CNN +F 1 "plot_v1" H 8650 3250 60 0000 C CNN +F 2 "" H 8450 2900 60 0000 C CNN +F 3 "" H 8450 2900 60 0000 C CNN + 1 8450 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 681F560E +P 8850 2900 +F 0 "U7" H 8850 3400 60 0000 C CNN +F 1 "plot_v1" H 9050 3250 60 0000 C CNN +F 2 "" H 8850 2900 60 0000 C CNN +F 3 "" H 8850 2900 60 0000 C CNN + 1 8850 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 681F5657 +P 9300 2900 +F 0 "U8" H 9300 3400 60 0000 C CNN +F 1 "plot_v1" H 9500 3250 60 0000 C CNN +F 2 "" H 9300 2900 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GLabel 8500 4250 0 60 Input ~ 0 +6Q +Text GLabel 8700 4350 0 60 Input ~ 0 +7Q +Text GLabel 8900 4450 0 60 Input ~ 0 +8Q +Wire Wire Line + 8500 4250 8500 3200 +Connection ~ 8500 3200 +Text GLabel 2900 1500 2 60 Input ~ 0 +8D +Wire Wire Line + 2900 1500 2900 3950 +Text GLabel 2700 1400 2 60 Input ~ 0 +7D +Wire Wire Line + 2700 1400 2700 2900 +Text GLabel 2500 1300 2 60 Input ~ 0 +6D +Text GLabel 2300 1200 2 60 Input ~ 0 +5D +Wire Wire Line + 2300 1200 2300 2500 +Wire Wire Line + 2500 1300 2500 4100 +Text GLabel 2050 1100 2 60 Input ~ 0 +4D +Wire Wire Line + 2050 1100 2050 3800 +Text GLabel 1850 1000 2 60 Input ~ 0 +3D +Text GLabel 1650 900 2 60 Input ~ 0 +2D +Text GLabel 1450 800 2 60 Input ~ 0 +1D +Wire Wire Line + 1450 800 1450 2950 +Wire Wire Line + 1650 900 1650 3050 +Wire Wire Line + 1850 1000 1850 3350 +Connection ~ 1500 2950 +Connection ~ 1900 3050 +Wire Wire Line + 1850 3350 2300 3350 +Connection ~ 2300 3350 +Wire Wire Line + 2050 3800 2700 3800 +Connection ~ 2700 3800 +Wire Wire Line + 2300 2500 2400 2500 +Wire Wire Line + 2400 2500 2400 4050 +Wire Wire Line + 2400 4050 3100 4050 +Connection ~ 3100 4050 +Wire Wire Line + 2500 4100 3500 4100 +Connection ~ 3500 4100 +Wire Wire Line + 2700 2900 2850 2900 +Wire Wire Line + 2850 2900 2850 3900 +Connection ~ 3700 3900 +Wire Wire Line + 2900 3950 4300 3950 +Connection ~ 4300 3950 +Wire Wire Line + 8050 4050 8050 3000 +Connection ~ 8050 3000 +Wire Wire Line + 8300 4150 8300 3100 +Connection ~ 8300 3100 +Wire Wire Line + 8900 4450 8900 3400 +Connection ~ 8900 3400 +Wire Wire Line + 7650 3850 7650 2800 +Connection ~ 7650 2800 +Wire Wire Line + 8700 4350 8700 3300 +Connection ~ 8700 3300 +$Comp +L ls573 x1 +U 1 1 68215BF4 +P 5550 3500 +F 0 "x1" H 5600 3200 60 0000 C CNN +F 1 "ls573" H 5550 4550 60 0000 C CNN +F 2 "" H 5550 4550 60 0001 C CNN +F 3 "" H 5550 4550 60 0001 C CNN + 1 5550 3500 + 1 0 0 -1 +$EndComp +Text GLabel 750 1800 2 60 Input ~ 0 +oe +Wire Wire Line + 750 1800 750 2650 +Connection ~ 1200 2750 +Text GLabel 1200 1900 2 60 Input ~ 0 +LE +Wire Wire Line + 1200 1900 1200 2750 +$Comp +L DC v1 +U 1 1 68396D07 +P 750 3100 +F 0 "v1" H 550 3200 60 0000 C CNN +F 1 "DC" H 550 3050 60 0000 C CNN +F 2 "R1" H 450 3100 60 0000 C CNN +F 3 "" H 750 3100 60 0000 C CNN + 1 750 3100 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 68396D5A +P 1150 3350 +F 0 "v2" H 950 3450 60 0000 C CNN +F 1 "DC" H 950 3300 60 0000 C CNN +F 2 "R1" H 850 3350 60 0000 C CNN +F 3 "" H 1150 3350 60 0000 C CNN + 1 1150 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573_Previous_Values.xml new file mode 100644 index 00000000..dc8b5216 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54als573/sn54als573_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0m</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v5><v6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v6><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v7><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v8><v9 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v9><v10 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v10><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0m</field3><field4 name="Rise Time">1u</field4><field5 name="Fall Time">1u</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v2></source><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u3><u1 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u1></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\ls373</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ns</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47-cache.lib new file mode 100644 index 00000000..78d3995f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47-cache.lib @@ -0,0 +1,300 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# a_origin +# +DEF a_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "a_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X a 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# b_origin +# +DEF b_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "b_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X b 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# c_origin +# +DEF c_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "c_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X c 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_origin +# +DEF d_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "d_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -50 0 1 0 N +X x 1 -450 250 200 R 50 50 1 1 I +X y 2 -450 150 200 R 50 50 1 1 I +X z 3 -450 50 200 R 50 50 1 1 I +X d 4 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_7 +# +DEF dac_bridge_7 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_7" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -600 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X OUT1 8 550 50 200 L 50 50 1 1 O +X OUT2 9 550 -50 200 L 50 50 1 1 O +X OUT3 10 550 -150 200 L 50 50 1 1 O +X OUT4 11 550 -250 200 L 50 50 1 1 O +X OUT5 12 550 -350 200 L 50 50 1 1 O +X OUT6 13 550 -450 200 L 50 50 1 1 O +X OUT7 14 550 -550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# e_origin +# +DEF e_origin X 0 40 Y Y 1 F N +F0 "X" 0 -400 60 H V C CNN +F1 "e_origin" 0 250 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 200 -250 -200 0 1 0 N +X x 1 -450 100 200 R 50 50 1 1 I +X y 2 -450 0 200 R 50 50 1 1 I +X z 3 -450 -100 200 R 50 50 1 1 I +X e 4 450 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# f_origin +# +DEF f_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "f_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X f 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# g_origin +# +DEF g_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "g_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X g 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir new file mode 100644 index 00000000..a64c338c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir @@ -0,0 +1,31 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls47\74ls47.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:57:49 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X3 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U5-Pad1_ a_origin +X5 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U7-Pad1_ c_origin +X6 Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U8-Pad1_ d_origin +X7 Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U11-Pad1_ e_origin +X8 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U9-Pad1_ f_origin +U1 /w /x /y /z Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ ? ? PORT +U3 /w /x /y /z Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ adc_bridge_4 +X1 /RBI Net-_U3-Pad8_ Net-_U3-Pad7_ Net-_U3-Pad6_ Net-_U4-Pad1_ 4_OR +U4 Net-_U4-Pad1_ Net-_U3-Pad5_ Net-_U4-Pad3_ d_or +X2 /LT /BI Net-_U4-Pad3_ Net-_U10-Pad2_ 3_and +U5 Net-_U5-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_and +U6 Net-_U6-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad2_ d_and +U7 Net-_U7-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_and +U8 Net-_U8-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad4_ d_and +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U9 Net-_U9-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad6_ d_and +U2 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ /LT /BI /RBI adc_bridge_3 +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ Net-_U12-Pad4_ Net-_U11-Pad3_ Net-_U12-Pad6_ Net-_U10-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ dac_bridge_7 +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +X4 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U6-Pad1_ b_origin +X9 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U10-Pad1_ g_origin + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir.out new file mode 100644 index 00000000..21471ca2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir.out @@ -0,0 +1,74 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls47\74ls47.cir + +.include 3_and.sub +.include g_origin.sub +.include e_origin.sub +.include a_origin.sub +.include 4_OR.sub +.include c_origin.sub +.include d_origin.sub +.include b_origin.sub +.include f_origin.sub +x3 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u5-pad1_ a_origin +x5 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u7-pad1_ c_origin +x6 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u8-pad1_ d_origin +x7 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u11-pad1_ e_origin +x8 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u9-pad1_ f_origin +* u1 /w /x /y /z net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? port +* u3 /w /x /y /z net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4 +x1 /rbi net-_u3-pad8_ net-_u3-pad7_ net-_u3-pad6_ net-_u4-pad1_ 4_OR +* u4 net-_u4-pad1_ net-_u3-pad5_ net-_u4-pad3_ d_or +x2 /lt /bi net-_u4-pad3_ net-_u10-pad2_ 3_and +* u5 net-_u5-pad1_ net-_u10-pad2_ net-_u12-pad1_ d_and +* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ d_and +* u7 net-_u7-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u8 net-_u8-pad1_ net-_u10-pad2_ net-_u12-pad4_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u9 net-_u9-pad1_ net-_u10-pad2_ net-_u12-pad6_ d_and +* u2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ /lt /bi /rbi adc_bridge_3 +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_7 +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +x4 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u6-pad1_ b_origin +x9 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u10-pad1_ g_origin +a1 [/w /x /y /z ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3 +a2 [net-_u4-pad1_ net-_u3-pad5_ ] net-_u4-pad3_ u4 +a3 [net-_u5-pad1_ net-_u10-pad2_ ] net-_u12-pad1_ u5 +a4 [net-_u6-pad1_ net-_u10-pad2_ ] net-_u12-pad2_ u6 +a5 [net-_u7-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u7 +a6 [net-_u8-pad1_ net-_u10-pad2_ ] net-_u12-pad4_ u8 +a7 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a8 [net-_u9-pad1_ net-_u10-pad2_ ] net-_u12-pad6_ u9 +a9 [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] [/lt /bi /rbi ] u2 +a10 [net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ ] [net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u12 +a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_7, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sch new file mode 100644 index 00000000..532d7dd4 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sch @@ -0,0 +1,775 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74ls47-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L a_origin X3 +U 1 1 67F6D192 +P 5050 1300 +F 0 "X3" H 5050 1100 60 0000 C CNN +F 1 "a_origin" H 5050 1650 60 0000 C CNN +F 2 "" H 5050 1300 60 0001 C CNN +F 3 "" H 5050 1300 60 0001 C CNN + 1 5050 1300 + 1 0 0 -1 +$EndComp +$Comp +L c_origin X5 +U 1 1 67F6D1E2 +P 5150 3150 +F 0 "X5" H 5150 2950 60 0000 C CNN +F 1 "c_origin" H 5150 3500 60 0000 C CNN +F 2 "" H 5150 3150 60 0001 C CNN +F 3 "" H 5150 3150 60 0001 C CNN + 1 5150 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_origin X6 +U 1 1 67F6D21D +P 5200 3950 +F 0 "X6" H 5200 3750 60 0000 C CNN +F 1 "d_origin" H 5200 4300 60 0000 C CNN +F 2 "" H 5200 3950 60 0001 C CNN +F 3 "" H 5200 3950 60 0001 C CNN + 1 5200 3950 + 1 0 0 -1 +$EndComp +$Comp +L e_origin X7 +U 1 1 67F6D25A +P 5200 4650 +F 0 "X7" H 5200 4250 60 0000 C CNN +F 1 "e_origin" H 5200 4900 60 0000 C CNN +F 2 "" H 5200 4650 60 0001 C CNN +F 3 "" H 5200 4650 60 0001 C CNN + 1 5200 4650 + 1 0 0 -1 +$EndComp +$Comp +L f_origin X8 +U 1 1 67F6D291 +P 5250 5650 +F 0 "X8" H 5250 5450 60 0000 C CNN +F 1 "f_origin" H 5250 6000 60 0000 C CNN +F 2 "" H 5250 5650 60 0001 C CNN +F 3 "" H 5250 5650 60 0001 C CNN + 1 5250 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67F6D2C8 +P 1600 1750 +F 0 "U1" H 1650 1850 30 0000 C CNN +F 1 "PORT" H 1600 1750 30 0000 C CNN +F 2 "" H 1600 1750 60 0000 C CNN +F 3 "" H 1600 1750 60 0000 C CNN + 4 1600 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67F6D311 +P 1250 5500 +F 0 "U1" H 1300 5600 30 0000 C CNN +F 1 "PORT" H 1250 5500 30 0000 C CNN +F 2 "" H 1250 5500 60 0000 C CNN +F 3 "" H 1250 5500 60 0000 C CNN + 5 1250 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67F6D35A +P 1250 5800 +F 0 "U1" H 1300 5900 30 0000 C CNN +F 1 "PORT" H 1250 5800 30 0000 C CNN +F 2 "" H 1250 5800 60 0000 C CNN +F 3 "" H 1250 5800 60 0000 C CNN + 6 1250 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 67F6D385 +P 1250 6100 +F 0 "U1" H 1300 6200 30 0000 C CNN +F 1 "PORT" H 1250 6100 30 0000 C CNN +F 2 "" H 1250 6100 60 0000 C CNN +F 3 "" H 1250 6100 60 0000 C CNN + 7 1250 6100 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U3 +U 1 1 67F6D3BC +P 2950 1400 +F 0 "U3" H 2950 1400 60 0000 C CNN +F 1 "adc_bridge_4" H 2950 1700 60 0000 C CNN +F 2 "" H 2950 1400 60 0000 C CNN +F 3 "" H 2950 1400 60 0000 C CNN + 1 2950 1400 + 1 0 0 -1 +$EndComp +Text Label 2250 1000 0 60 ~ 0 +w +Text Label 2150 1250 0 60 ~ 0 +x +Text Label 2150 1400 0 60 ~ 0 +y +Text Label 2150 1750 0 60 ~ 0 +z +Wire Wire Line + 1850 1000 2400 1000 +Wire Wire Line + 2400 1000 2400 1200 +Wire Wire Line + 1850 1250 2400 1250 +Wire Wire Line + 2400 1250 2400 1300 +Wire Wire Line + 1850 1500 1850 1400 +Wire Wire Line + 1850 1400 2400 1400 +Wire Wire Line + 1850 1750 2400 1750 +Wire Wire Line + 2400 1750 2400 1500 +Wire Wire Line + 3500 1200 3500 1050 +Wire Wire Line + 3500 1050 4600 1050 +Wire Wire Line + 4650 2000 4450 2000 +Wire Wire Line + 4450 1050 4450 6250 +Connection ~ 4450 1050 +Wire Wire Line + 4450 2900 4700 2900 +Connection ~ 4450 2000 +Wire Wire Line + 4450 5400 4800 5400 +Connection ~ 4450 2900 +Wire Wire Line + 3500 1300 3650 1300 +Wire Wire Line + 3650 2600 3650 1150 +Wire Wire Line + 3650 1150 4600 1150 +Wire Wire Line + 4650 2100 4350 2100 +Wire Wire Line + 4350 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+$EndComp +$Comp +L d_and U11 +U 1 1 67F6E5FA +P 6450 4750 +F 0 "U11" H 6450 4750 60 0000 C CNN +F 1 "d_and" H 6500 4850 60 0000 C CNN +F 2 "" H 6450 4750 60 0000 C CNN +F 3 "" H 6450 4750 60 0000 C CNN + 1 6450 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 67F6E64D +P 6400 5650 +F 0 "U9" H 6400 5650 60 0000 C CNN +F 1 "d_and" H 6450 5750 60 0000 C CNN +F 2 "" H 6400 5650 60 0000 C CNN +F 3 "" H 6400 5650 60 0000 C CNN + 1 6400 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 3050 5900 3050 +Wire Wire Line + 5900 3150 5900 3400 +Wire Wire Line + 5900 3400 3750 3400 +Connection ~ 3750 3400 +Wire Wire Line + 5650 3850 5950 3850 +Wire Wire Line + 5950 3950 5850 3950 +Wire Wire Line + 5850 3950 5850 4250 +Wire Wire Line + 5850 4250 3750 4250 +Connection ~ 3750 4250 +Wire Wire Line + 5650 4650 6000 4650 +Wire Wire Line + 6000 4750 6000 4950 +Wire Wire Line + 6000 4950 3750 4950 +Connection ~ 3750 4950 +Wire Wire Line + 5700 5550 5950 5550 +Wire Wire Line + 5950 5650 5950 5900 +Wire Wire Line + 5950 5900 3750 5900 +Connection ~ 3750 5900 +$Comp +L adc_bridge_3 U2 +U 1 1 67F6EB0D +P 1850 4650 +F 0 "U2" H 1850 4650 60 0000 C CNN +F 1 "adc_bridge_3" H 1850 4800 60 0000 C CNN +F 2 "" H 1850 4650 60 0000 C CNN +F 3 "" H 1850 4650 60 0000 C CNN + 1 1850 4650 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 1900 5250 1900 5800 +Wire Wire Line + 1500 5500 1800 5500 +Wire Wire Line + 1800 5500 1800 5250 +Wire Wire Line + 1800 4100 1800 2900 +Wire Wire Line + 1900 5800 1500 5800 +Wire Wire Line + 1900 4100 1900 3200 +Wire Wire Line + 2000 4100 2000 3500 +Wire Wire Line + 2000 3500 2300 3500 +Wire Wire Line + 1500 6100 2000 6100 +Wire Wire Line + 2000 6100 2000 5250 +$Comp +L dac_bridge_7 U12 +U 1 1 67F6F154 +P 8250 2900 +F 0 "U12" H 8250 2900 60 0000 C CNN +F 1 "dac_bridge_7" H 8250 3050 60 0000 C CNN +F 2 "" H 8250 2900 60 0000 C CNN +F 3 "" H 8250 2900 60 0000 C CNN + 1 8250 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 1250 7650 1250 +Wire Wire Line + 7650 1250 7650 2850 +Wire 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0000 C CNN +F 3 "" H 6400 6500 60 0000 C CNN + 1 6400 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 6400 5950 6400 +Wire Wire Line + 5950 6750 5950 6500 +Wire Wire Line + 3150 6750 5950 6750 +Wire Wire Line + 6850 6450 7550 6450 +Connection ~ 3750 6750 +Wire Wire Line + 7550 6450 7550 3450 +Wire Wire Line + 7550 3450 7650 3450 +$Comp +L PORT U1 +U 8 1 67F6FCB5 +P 9400 2850 +F 0 "U1" H 9450 2950 30 0000 C CNN +F 1 "PORT" H 9400 2850 30 0000 C CNN +F 2 "" H 9400 2850 60 0000 C CNN +F 3 "" H 9400 2850 60 0000 C CNN + 8 9400 2850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 67F6FD50 +P 9400 2950 +F 0 "U1" H 9450 3050 30 0000 C CNN +F 1 "PORT" H 9400 2950 30 0000 C CNN +F 2 "" H 9400 2950 60 0000 C CNN +F 3 "" H 9400 2950 60 0000 C CNN + 9 9400 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 67F6FDD8 +P 9400 3050 +F 0 "U1" H 9450 3150 30 0000 C CNN +F 1 "PORT" H 9400 3050 30 0000 C CNN +F 2 "" H 9400 3050 60 0000 C CNN +F 3 "" H 9400 3050 60 0000 C CNN + 10 9400 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 67F6FE4F +P 9400 3150 +F 0 "U1" H 9450 3250 30 0000 C CNN +F 1 "PORT" H 9400 3150 30 0000 C CNN +F 2 "" H 9400 3150 60 0000 C CNN +F 3 "" H 9400 3150 60 0000 C CNN + 11 9400 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 67F6FED2 +P 9400 3250 +F 0 "U1" H 9450 3350 30 0000 C CNN +F 1 "PORT" H 9400 3250 30 0000 C CNN +F 2 "" H 9400 3250 60 0000 C CNN +F 3 "" H 9400 3250 60 0000 C CNN + 12 9400 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 67F6FF61 +P 9400 3350 +F 0 "U1" H 9450 3450 30 0000 C CNN +F 1 "PORT" H 9400 3350 30 0000 C CNN +F 2 "" H 9400 3350 60 0000 C CNN +F 3 "" H 9400 3350 60 0000 C CNN + 13 9400 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 67F6FFE2 +P 9400 3450 +F 0 "U1" H 9450 3550 30 0000 C CNN +F 1 "PORT" H 9400 3450 30 0000 C CNN +F 2 "" H 9400 3450 60 0000 C CNN +F 3 "" H 9400 3450 60 0000 C CNN + 14 9400 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 67F70067 +P 9400 4400 +F 0 "U1" H 9450 4500 30 0000 C CNN +F 1 "PORT" H 9400 4400 30 0000 C CNN +F 2 "" H 9400 4400 60 0000 C CNN +F 3 "" H 9400 4400 60 0000 C CNN + 15 9400 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67F700CE +P 9450 4600 +F 0 "U1" H 9500 4700 30 0000 C CNN +F 1 "PORT" H 9450 4600 30 0000 C CNN +F 2 "" H 9450 4600 60 0000 C CNN +F 3 "" H 9450 4600 60 0000 C CNN + 16 9450 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2850 9150 2850 +Wire Wire Line + 8800 2950 9150 2950 +Wire Wire Line + 8800 3050 9150 3050 +Wire Wire Line + 8800 3150 9150 3150 +Wire Wire Line + 8800 3250 9150 3250 +Wire Wire Line + 8800 3350 9150 3350 +Wire Wire Line + 8800 3450 9150 3450 +NoConn ~ 9650 4400 +NoConn ~ 9700 4600 +Connection ~ 3800 1500 +Connection ~ 3700 1400 +Connection ~ 3650 1300 +Wire Wire Line + 3850 2700 3850 1050 +Connection ~ 3850 1050 +$Comp +L b_origin X4 +U 1 1 67F82B41 +P 5100 2250 +F 0 "X4" H 5100 2050 60 0000 C CNN +F 1 "b_origin" H 5100 2600 60 0000 C CNN +F 2 "" H 5100 2250 60 0001 C CNN +F 3 "" H 5100 2250 60 0001 C CNN + 1 5100 2250 + 1 0 0 -1 +$EndComp +$Comp +L g_origin X9 +U 1 1 67F82BE6 +P 5250 6500 +F 0 "X9" H 5250 6300 60 0000 C CNN +F 1 "g_origin" H 5250 6850 60 0000 C CNN +F 2 "" H 5250 6500 60 0001 C CNN +F 3 "" H 5250 6500 60 0001 C CNN + 1 5250 6500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sub new file mode 100644 index 00000000..a2e7a0fa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sub @@ -0,0 +1,68 @@ +* Subcircuit 74ls47 +.subckt 74ls47 /w /x /y /z net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls47\74ls47.cir +.include 3_and.sub +.include g_origin.sub +.include e_origin.sub +.include a_origin.sub +.include 4_OR.sub +.include c_origin.sub +.include d_origin.sub +.include b_origin.sub +.include f_origin.sub +x3 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u5-pad1_ a_origin +x5 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u7-pad1_ c_origin +x6 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u8-pad1_ d_origin +x7 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u11-pad1_ e_origin +x8 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u9-pad1_ f_origin +* u3 /w /x /y /z net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4 +x1 /rbi net-_u3-pad8_ net-_u3-pad7_ net-_u3-pad6_ net-_u4-pad1_ 4_OR +* u4 net-_u4-pad1_ net-_u3-pad5_ net-_u4-pad3_ d_or +x2 /lt /bi net-_u4-pad3_ net-_u10-pad2_ 3_and +* u5 net-_u5-pad1_ net-_u10-pad2_ net-_u12-pad1_ d_and +* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ d_and +* u7 net-_u7-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u8 net-_u8-pad1_ net-_u10-pad2_ net-_u12-pad4_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u9 net-_u9-pad1_ net-_u10-pad2_ net-_u12-pad6_ d_and +* u2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ /lt /bi /rbi adc_bridge_3 +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_7 +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +x4 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u6-pad1_ b_origin +x9 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u10-pad1_ g_origin +a1 [/w /x /y /z ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3 +a2 [net-_u4-pad1_ net-_u3-pad5_ ] net-_u4-pad3_ u4 +a3 [net-_u5-pad1_ net-_u10-pad2_ ] net-_u12-pad1_ u5 +a4 [net-_u6-pad1_ net-_u10-pad2_ ] net-_u12-pad2_ u6 +a5 [net-_u7-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u7 +a6 [net-_u8-pad1_ net-_u10-pad2_ ] net-_u12-pad4_ u8 +a7 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a8 [net-_u9-pad1_ net-_u10-pad2_ ] net-_u12-pad6_ u9 +a9 [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] [/lt /bi /rbi ] u2 +a10 [net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ ] [net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u12 +a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_7, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74ls47
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47_Previous_Values.xml new file mode 100644 index 00000000..dcbdc226 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u8><u11 name="type">d_and<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u11><u9 name="type">d_and<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u9><u2 name="type">adc_bridge<field26 name="Enter value for in_low (default=1.0)" /><field27 name="Enter value for in_high (default=2.0)" /><field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /></u2><u12 name="type">dac_bridge<field30 name="Enter value for out_low (default=0.0)" /><field31 name="Enter value for out_high (default=5.0)" /><field32 name="Enter value for out_undef (default=0.5)" /><field33 name="Enter value for input load (default=1.0e-12)" /><field34 name="Enter the Rise Time (default=1.0e-9)" /><field35 name="Enter the Fall Time (default=1.0e-9)" /></u12><u10 name="type">d_and<field36 name="Enter Rise Delay (default=1.0e-9)" /><field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /></u10></model><devicemodel /><subcircuit><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\a_origin</field></x3><x5><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\c_origin</field></x5><x6><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\d_origin</field></x6><x7><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\e_origin</field></x7><x8><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\f_origin</field></x8><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\b_origin</field></x4><x9><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\g_origin</field></x9></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin-cache.lib new file mode 100644 index 00000000..cba52382 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir new file mode 100644 index 00000000..7a7f0ef0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir @@ -0,0 +1,20 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\a_origin\a_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 00:37:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /w Net-_U2-Pad2_ d_inverter +U3 /x Net-_U3-Pad2_ d_inverter +U4 /y Net-_U4-Pad2_ d_inverter +U5 /z Net-_U5-Pad2_ d_inverter +X3 /x Net-_U4-Pad2_ /z Net-_X3-Pad4_ 3_and +X1 /w Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_X1-Pad4_ 3_and +X2 Net-_U2-Pad2_ /y /z Net-_X2-Pad4_ 3_and +X4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U5-Pad2_ Net-_X4-Pad4_ 3_and +X5 Net-_X3-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_X4-Pad4_ Net-_U1-Pad5_ 4_OR + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir.out new file mode 100644 index 00000000..0017627e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir.out @@ -0,0 +1,35 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\a_origin\a_origin.cir + +.include 3_and.sub +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x3 /x net-_u4-pad2_ /z net-_x3-pad4_ 3_and +x1 /w net-_u3-pad2_ net-_u4-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ /y /z net-_x2-pad4_ 3_and +x4 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad2_ net-_x4-pad4_ 3_and +x5 net-_x3-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_x4-pad4_ net-_u1-pad5_ 4_OR +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sch new file mode 100644 index 00000000..73d001b6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sch @@ -0,0 +1,312 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:a_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4DD6F +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4DDB6 +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4DE11 +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4DE68 +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E01D +P 2600 2450 +F 0 "U2" H 2600 2350 60 0000 C CNN +F 1 "d_inverter" H 2600 2600 60 0000 C CNN +F 2 "" H 2650 2400 60 0000 C CNN +F 3 "" H 2650 2400 60 0000 C CNN + 1 2600 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E060 +P 3450 2450 +F 0 "U3" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E0A1 +P 4100 2400 +F 0 "U4" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67F4E0D4 +P 4800 2300 +F 0 "U5" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 2100 2600 2100 +Wire Wire Line + 2600 2100 2600 2150 +Connection ~ 2350 2100 +Wire Wire Line + 2600 2750 2600 4150 +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 3450 2750 3450 4250 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 2100 +Connection ~ 3850 2100 +Wire Wire Line + 4100 2050 4100 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 4800 2600 4800 4350 +Wire Wire Line + 3100 2800 5300 2800 +Connection ~ 3100 2800 +Wire Wire Line + 4100 2900 5300 2900 +Connection ~ 4100 2900 +Wire Wire Line + 4450 3000 5300 3000 +Connection ~ 4450 3000 +$Comp +L 3_and X3 +U 1 1 67F4E3C4 +P 5650 2950 +F 0 "X3" H 5750 2900 60 0000 C CNN +F 1 "3_and" H 5800 3100 60 0000 C CNN +F 2 "" H 5650 2950 60 0000 C CNN +F 3 "" H 5650 2950 60 0000 C CNN + 1 5650 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2350 3200 5000 3200 +Connection ~ 2350 3200 +Wire Wire Line + 3450 3300 5000 3300 +Connection ~ 3450 3300 +Wire Wire Line + 4100 3400 5000 3400 +Connection ~ 4100 3400 +$Comp +L 3_and X1 +U 1 1 67F4E48C +P 5350 3350 +F 0 "X1" H 5450 3300 60 0000 C CNN +F 1 "3_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5350 3350 60 0000 C CNN +F 3 "" H 5350 3350 60 0000 C CNN + 1 5350 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 3600 5100 3600 +Connection ~ 2600 3600 +Wire Wire Line + 3850 3700 5100 3700 +Connection ~ 3850 3700 +Wire Wire Line + 4450 3800 5100 3800 +Connection ~ 4450 3800 +$Comp +L 3_and X2 +U 1 1 67F4E565 +P 5450 3750 +F 0 "X2" H 5550 3700 60 0000 C CNN +F 1 "3_and" H 5600 3900 60 0000 C CNN +F 2 "" H 5450 3750 60 0000 C CNN +F 3 "" H 5450 3750 60 0000 C CNN + 1 5450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 4150 5300 4150 +Wire Wire Line + 3450 4250 5300 4250 +Wire Wire Line + 4800 4350 5300 4350 +$Comp +L 3_and X4 +U 1 1 67F4E64C +P 5650 4300 +F 0 "X4" H 5750 4250 60 0000 C CNN +F 1 "3_and" H 5800 4450 60 0000 C CNN +F 2 "" H 5650 4300 60 0000 C CNN +F 3 "" H 5650 4300 60 0000 C CNN + 1 5650 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 3800 4450 1550 +Wire Wire Line + 4100 3400 4100 2700 +Wire Wire Line + 3850 3700 3850 1550 +Wire Wire Line + 3100 2800 3100 1550 +Wire Wire Line + 2350 3200 2350 1550 +$Comp +L 4_OR X5 +U 1 1 67F4E827 +P 7000 3450 +F 0 "X5" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 2900 6650 2900 +Wire Wire Line + 6650 2900 6650 3300 +Wire Wire Line + 5850 3300 6100 3300 +Wire Wire Line + 6100 3300 6100 3400 +Wire Wire Line + 6100 3400 6650 3400 +Wire Wire Line + 5950 3700 6050 3700 +Wire Wire Line + 6050 3700 6050 3500 +Wire Wire Line + 6050 3500 6650 3500 +Wire Wire Line + 6150 4250 6650 4250 +Wire Wire Line + 6650 4250 6650 3600 +Wire Wire Line + 7550 3450 7950 3450 +$Comp +L PORT U1 +U 5 1 67F4E9A9 +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sub new file mode 100644 index 00000000..039707d1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sub @@ -0,0 +1,29 @@ +* Subcircuit a_origin +.subckt a_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\a_origin\a_origin.cir +.include 3_and.sub +.include 4_OR.sub +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x3 /x net-_u4-pad2_ /z net-_x3-pad4_ 3_and +x1 /w net-_u3-pad2_ net-_u4-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ /y /z net-_x2-pad4_ 3_and +x4 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad2_ net-_x4-pad4_ 3_and +x5 net-_x3-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_x4-pad4_ net-_u1-pad5_ 4_OR +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends a_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin_Previous_Values.xml new file mode 100644 index 00000000..0ea212d8 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5></model><devicemodel /><subcircuit><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/analysis new file mode 100644 index 00000000..f482494a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/analysis @@ -0,0 +1 @@ +.tran 1e-03 32e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin-cache.lib new file mode 100644 index 00000000..6bcc3103 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir new file mode 100644 index 00000000..ed5a9067 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir @@ -0,0 +1,20 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\b_origin\b_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:52:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /w Net-_U2-Pad2_ d_inverter +U3 /x Net-_U3-Pad2_ d_inverter +U4 /y Net-_U4-Pad2_ d_inverter +U5 /z Net-_U5-Pad2_ d_inverter +X2 Net-_U7-Pad3_ Net-_U8-Pad3_ Net-_U6-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad5_ 4_OR +X1 Net-_U2-Pad2_ /y /z Net-_X1-Pad4_ 3_and +U6 Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad3_ d_and +U8 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad3_ d_and +U7 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U7-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir.out new file mode 100644 index 00000000..6a79abc5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir.out @@ -0,0 +1,44 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\b_origin\b_origin.cir + +.include 3_and.sub +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x2 net-_u7-pad3_ net-_u8-pad3_ net-_u6-pad3_ net-_x1-pad4_ net-_u1-pad5_ 4_OR +x1 net-_u2-pad2_ /y /z net-_x1-pad4_ 3_and +* u6 net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad3_ d_and +* u8 net-_u3-pad2_ net-_u4-pad2_ net-_u8-pad3_ d_and +* u7 net-_u3-pad2_ net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +a5 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u6-pad3_ u6 +a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u8-pad3_ u8 +a7 [net-_u3-pad2_ net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sch new file mode 100644 index 00000000..a040bf91 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sch @@ -0,0 +1,298 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:b_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4E18C +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4E18D +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4E18E +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4E18F +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E190 +P 2600 2450 +F 0 "U2" H 2600 2350 60 0000 C CNN +F 1 "d_inverter" H 2600 2600 60 0000 C CNN +F 2 "" H 2650 2400 60 0000 C CNN +F 3 "" H 2650 2400 60 0000 C CNN + 1 2600 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E191 +P 3450 2450 +F 0 "U3" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E192 +P 4100 2400 +F 0 "U4" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67F4E193 +P 4800 2300 +F 0 "U5" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X2 +U 1 1 67F4E198 +P 7000 3450 +F 0 "X2" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67F4E199 +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 2350 2100 2600 2100 +Wire Wire Line + 2600 2100 2600 2150 +Connection ~ 2350 2100 +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 2100 +Connection ~ 3850 2100 +Wire Wire Line + 4100 2050 4100 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 6650 3600 6650 4850 +Wire Wire Line + 7550 3450 7950 3450 +Wire Wire Line + 2600 2750 2600 4750 +Wire Wire Line + 2600 3150 5350 3150 +Wire Wire Line + 3450 2750 3450 3550 +Wire Wire Line + 3450 3050 5350 3050 +Wire Wire Line + 3450 3550 5350 3550 +Connection ~ 3450 3050 +Wire Wire Line + 4100 2700 4100 4100 +Wire Wire Line + 4100 3650 5350 3650 +Wire Wire Line + 4100 4100 5300 4100 +Connection ~ 4100 3650 +Wire Wire Line + 4800 2600 4800 4200 +Wire Wire Line + 4800 4200 5300 4200 +Wire Wire Line + 2600 4750 5300 4750 +Connection ~ 2600 3150 +Wire Wire Line + 3850 1550 3850 4850 +Wire Wire Line + 3850 4850 5300 4850 +Wire Wire Line + 4450 1550 4450 4950 +Wire Wire Line + 4450 4950 5300 4950 +Wire Wire Line + 3100 1550 3100 2100 +Wire Wire Line + 2350 1550 2350 2100 +$Comp +L 3_and X1 +U 1 1 67F4E4E1 +P 5650 4900 +F 0 "X1" H 5750 4850 60 0000 C CNN +F 1 "3_and" H 5800 5050 60 0000 C CNN +F 2 "" H 5650 4900 60 0000 C CNN +F 3 "" H 5650 4900 60 0000 C CNN + 1 5650 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F4E574 +P 5750 4200 +F 0 "U6" H 5750 4200 60 0000 C CNN +F 1 "d_and" H 5800 4300 60 0000 C CNN +F 2 "" H 5750 4200 60 0000 C CNN +F 3 "" H 5750 4200 60 0000 C CNN + 1 5750 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 67F4E5DF +P 5800 3650 +F 0 "U8" H 5800 3650 60 0000 C CNN +F 1 "d_and" H 5850 3750 60 0000 C CNN +F 2 "" H 5800 3650 60 0000 C CNN +F 3 "" H 5800 3650 60 0000 C CNN + 1 5800 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F4E62C +P 5800 3150 +F 0 "U7" H 5800 3150 60 0000 C CNN +F 1 "d_and" H 5850 3250 60 0000 C CNN +F 2 "" H 5800 3150 60 0000 C CNN +F 3 "" H 5800 3150 60 0000 C CNN + 1 5800 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6250 3100 6650 3100 +Wire Wire Line + 6650 3100 6650 3300 +Wire Wire Line + 6250 3600 6250 3400 +Wire Wire Line + 6250 3400 6650 3400 +Wire Wire Line + 6200 4150 6500 4150 +Wire Wire Line + 6500 4150 6500 3500 +Wire Wire Line + 6500 3500 6650 3500 +Wire Wire Line + 6650 4850 6150 4850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sub new file mode 100644 index 00000000..320abfc6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sub @@ -0,0 +1,38 @@ +* Subcircuit b_origin +.subckt b_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\b_origin\b_origin.cir +.include 3_and.sub +.include 4_OR.sub +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x2 net-_u7-pad3_ net-_u8-pad3_ net-_u6-pad3_ net-_x1-pad4_ net-_u1-pad5_ 4_OR +x1 net-_u2-pad2_ /y /z net-_x1-pad4_ 3_and +* u6 net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad3_ d_and +* u8 net-_u3-pad2_ net-_u4-pad2_ net-_u8-pad3_ d_and +* u7 net-_u3-pad2_ net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +a5 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u6-pad3_ u6 +a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u8-pad3_ u8 +a7 [net-_u3-pad2_ net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends b_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin_Previous_Values.xml new file mode 100644 index 00000000..497562ca --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u8 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir new file mode 100644 index 00000000..da0eb176 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir @@ -0,0 +1,19 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\c_origin\c_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 00:45:18 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /w Net-_U2-Pad2_ d_inverter +U3 /x Net-_U3-Pad2_ d_inverter +U4 /y Net-_U4-Pad2_ d_inverter +U5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad3_ d_and +U6 Net-_U3-Pad2_ /z Net-_U6-Pad3_ d_and +U7 Net-_U2-Pad2_ /x Net-_U7-Pad3_ d_and +U8 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U8-Pad3_ d_or +U9 Net-_U8-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad5_ d_or + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out new file mode 100644 index 00000000..6eb3a7d8 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out @@ -0,0 +1,44 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\c_origin\c_origin.cir + +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u3-pad2_ /z net-_u6-pad3_ d_and +* u7 net-_u2-pad2_ /x net-_u7-pad3_ d_and +* u8 net-_u5-pad3_ net-_u6-pad3_ net-_u8-pad3_ d_or +* u9 net-_u8-pad3_ net-_u7-pad3_ net-_u1-pad5_ d_or +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u3-pad2_ /z ] net-_u6-pad3_ u6 +a6 [net-_u2-pad2_ /x ] net-_u7-pad3_ u7 +a7 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u8-pad3_ u8 +a8 [net-_u8-pad3_ net-_u7-pad3_ ] net-_u1-pad5_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sch new file mode 100644 index 00000000..6fec8e04 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sch @@ -0,0 +1,260 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:c_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4E33E +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4E33F +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4E340 +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4E341 +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E342 +P 2600 2450 +F 0 "U2" H 2600 2350 60 0000 C CNN +F 1 "d_inverter" H 2600 2600 60 0000 C CNN +F 2 "" H 2650 2400 60 0000 C CNN +F 3 "" H 2650 2400 60 0000 C CNN + 1 2600 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E343 +P 3450 2450 +F 0 "U3" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E344 +P 4100 2400 +F 0 "U4" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 2100 2600 2100 +Wire Wire Line + 2600 2100 2600 2150 +Connection ~ 2350 2100 +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 4100 2050 4100 2100 +Connection ~ 4450 1950 +Wire Wire Line + 3100 1550 3100 3800 +Wire Wire Line + 2350 1550 2350 2100 +Wire Wire Line + 3450 2900 5400 2900 +Connection ~ 3450 2900 +Wire Wire Line + 4100 3000 5400 3000 +Connection ~ 4100 3000 +Wire Wire Line + 3450 3200 5400 3200 +Connection ~ 3450 3200 +Wire Wire Line + 4450 3300 5400 3300 +Connection ~ 4450 3300 +Wire Wire Line + 2600 3700 5400 3700 +Connection ~ 2600 3700 +Wire Wire Line + 3100 3800 5400 3800 +Wire Wire Line + 3450 3200 3450 2750 +Wire Wire Line + 2600 3700 2600 2750 +Wire Wire Line + 4100 3000 4100 2700 +Wire Wire Line + 4450 3300 4450 1550 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 1550 +$Comp +L d_and U5 +U 1 1 67F4E64B +P 5850 3000 +F 0 "U5" H 5850 3000 60 0000 C CNN +F 1 "d_and" H 5900 3100 60 0000 C CNN +F 2 "" H 5850 3000 60 0000 C CNN +F 3 "" H 5850 3000 60 0000 C CNN + 1 5850 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F4E6B2 +P 5850 3300 +F 0 "U6" H 5850 3300 60 0000 C CNN +F 1 "d_and" H 5900 3400 60 0000 C CNN +F 2 "" H 5850 3300 60 0000 C CNN +F 3 "" H 5850 3300 60 0000 C CNN + 1 5850 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F4E707 +P 5850 3800 +F 0 "U7" H 5850 3800 60 0000 C CNN +F 1 "d_and" H 5900 3900 60 0000 C CNN +F 2 "" H 5850 3800 60 0000 C CNN +F 3 "" H 5850 3800 60 0000 C CNN + 1 5850 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 67F4E744 +P 6750 3050 +F 0 "U8" H 6750 3050 60 0000 C CNN +F 1 "d_or" H 6750 3150 60 0000 C CNN +F 2 "" H 6750 3050 60 0000 C CNN +F 3 "" H 6750 3050 60 0000 C CNN + 1 6750 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 3050 6300 3250 +$Comp +L d_or U9 +U 1 1 67F4E7EF +P 7650 3100 +F 0 "U9" H 7650 3100 60 0000 C CNN +F 1 "d_or" H 7650 3200 60 0000 C CNN +F 2 "" H 7650 3100 60 0000 C CNN +F 3 "" H 7650 3100 60 0000 C CNN + 1 7650 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 3750 7200 3750 +Wire Wire Line + 7200 3750 7200 3100 +$Comp +L PORT U1 +U 5 1 67F4E938 +P 8350 3050 +F 0 "U1" H 8400 3150 30 0000 C CNN +F 1 "PORT" H 8350 3050 30 0000 C CNN +F 2 "" H 8350 3050 60 0000 C CNN +F 3 "" H 8350 3050 60 0000 C CNN + 5 8350 3050 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sub new file mode 100644 index 00000000..fbe2fd03 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sub @@ -0,0 +1,38 @@ +* Subcircuit c_origin +.subckt c_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\c_origin\c_origin.cir +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u3-pad2_ /z net-_u6-pad3_ d_and +* u7 net-_u2-pad2_ /x net-_u7-pad3_ d_and +* u8 net-_u5-pad3_ net-_u6-pad3_ net-_u8-pad3_ d_or +* u9 net-_u8-pad3_ net-_u7-pad3_ net-_u1-pad5_ d_or +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u3-pad2_ /z ] net-_u6-pad3_ u6 +a6 [net-_u2-pad2_ /x ] net-_u7-pad3_ u7 +a7 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u8-pad3_ u8 +a8 [net-_u8-pad3_ net-_u7-pad3_ ] net-_u1-pad5_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends c_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin_Previous_Values.xml new file mode 100644 index 00000000..4a1451aa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_or<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin-cache.lib new file mode 100644 index 00000000..6bcc3103 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir new file mode 100644 index 00000000..d11eba94 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir @@ -0,0 +1,19 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\d_origin\d_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 00:47:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /x /y /z Net-_U1-Pad4_ PORT +U2 /x Net-_U2-Pad2_ d_inverter +U3 /y Net-_U3-Pad2_ d_inverter +U4 /z Net-_U4-Pad2_ d_inverter +X2 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad4_ 4_OR +U5 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad3_ d_and +U6 Net-_U2-Pad2_ /y Net-_U6-Pad3_ d_and +U7 /y Net-_U4-Pad2_ Net-_U7-Pad3_ d_and +X1 /x Net-_U3-Pad2_ /z Net-_X1-Pad4_ 3_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir.out new file mode 100644 index 00000000..53010be0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\d_origin\d_origin.cir + +.include 3_and.sub +.include 4_OR.sub +* u1 /x /y /z net-_u1-pad4_ port +* u2 /x net-_u2-pad2_ d_inverter +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x2 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_x1-pad4_ net-_u1-pad4_ 4_OR +* u5 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u2-pad2_ /y net-_u6-pad3_ d_and +* u7 /y net-_u4-pad2_ net-_u7-pad3_ d_and +x1 /x net-_u3-pad2_ /z net-_x1-pad4_ 3_and +a1 /x net-_u2-pad2_ u2 +a2 /y net-_u3-pad2_ u3 +a3 /z net-_u4-pad2_ u4 +a4 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad2_ /y ] net-_u6-pad3_ u6 +a6 [/y net-_u4-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sch new file mode 100644 index 00000000..ec9a3d9e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sch @@ -0,0 +1,270 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:d_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4E50B +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 1 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4E50C +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 2 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4E50D +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 3 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E50F +P 3450 2450 +F 0 "U2" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E510 +P 4100 2400 +F 0 "U3" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E511 +P 4800 2300 +F 0 "U4" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X2 +U 1 1 67F4E512 +P 7050 3400 +F 0 "X2" H 7200 3300 60 0000 C CNN +F 1 "4_OR" H 7200 3500 60 0000 C CNN +F 2 "" H 7050 3400 60 0000 C CNN +F 3 "" H 7050 3400 60 0000 C CNN + 1 7050 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4E513 +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L d_and U5 +U 1 1 67F4E754 +P 5650 3000 +F 0 "U5" H 5650 3000 60 0000 C CNN +F 1 "d_and" H 5700 3100 60 0000 C CNN +F 2 "" H 5650 3000 60 0000 C CNN +F 3 "" H 5650 3000 60 0000 C CNN + 1 5650 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F4E7A8 +P 5650 3300 +F 0 "U6" H 5650 3300 60 0000 C CNN +F 1 "d_and" H 5700 3400 60 0000 C CNN +F 2 "" H 5650 3300 60 0000 C CNN +F 3 "" H 5650 3300 60 0000 C CNN + 1 5650 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F4E7E1 +P 5700 3600 +F 0 "U7" H 5700 3600 60 0000 C CNN +F 1 "d_and" H 5750 3700 60 0000 C CNN +F 2 "" H 5700 3600 60 0000 C CNN +F 3 "" H 5700 3600 60 0000 C CNN + 1 5700 3600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 67F4E85E +P 5550 4050 +F 0 "X1" H 5650 4000 60 0000 C CNN +F 1 "3_and" H 5700 4200 60 0000 C CNN +F 2 "" H 5550 4050 60 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 2100 +Connection ~ 3850 2100 +Wire Wire Line + 4100 2050 4100 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 7600 3400 8000 3400 +Wire Wire Line + 3100 1550 3100 3900 +Wire Wire Line + 3450 2900 5200 2900 +Connection ~ 3450 2900 +Wire Wire Line + 4800 3000 5200 3000 +Connection ~ 4800 3000 +Wire Wire Line + 3450 3200 5200 3200 +Connection ~ 3450 3200 +Wire Wire Line + 3850 3300 5200 3300 +Connection ~ 3850 3300 +Wire Wire Line + 3850 3500 5250 3500 +Connection ~ 3850 3500 +Wire Wire Line + 4800 3600 5250 3600 +Connection ~ 4800 3600 +Wire Wire Line + 3100 3900 5200 3900 +Wire Wire Line + 4100 4000 5200 4000 +Connection ~ 4100 4000 +Wire Wire Line + 4450 4100 5200 4100 +Connection ~ 4450 4100 +Wire Wire Line + 4450 4100 4450 1550 +Wire Wire Line + 4100 4000 4100 2700 +Wire Wire Line + 4800 3600 4800 2600 +Wire Wire Line + 3850 1550 3850 3500 +Wire Wire Line + 3450 2750 3450 3200 +Wire Wire Line + 6100 2950 6700 2950 +Wire Wire Line + 6700 2950 6700 3250 +Wire Wire Line + 6100 3250 6550 3250 +Wire Wire Line + 6550 3250 6550 3350 +Wire Wire Line + 6550 3350 6700 3350 +Wire Wire Line + 6150 3550 6150 3450 +Wire Wire Line + 6150 3450 6700 3450 +Wire Wire Line + 6050 4000 6700 4000 +Wire Wire Line + 6700 4000 6700 3550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sub new file mode 100644 index 00000000..142ad7c3 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sub @@ -0,0 +1,34 @@ +* Subcircuit d_origin +.subckt d_origin /x /y /z net-_u1-pad4_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\d_origin\d_origin.cir +.include 3_and.sub +.include 4_OR.sub +* u2 /x net-_u2-pad2_ d_inverter +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x2 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_x1-pad4_ net-_u1-pad4_ 4_OR +* u5 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u2-pad2_ /y net-_u6-pad3_ d_and +* u7 /y net-_u4-pad2_ net-_u7-pad3_ d_and +x1 /x net-_u3-pad2_ /z net-_x1-pad4_ 3_and +a1 /x net-_u2-pad2_ u2 +a2 /y net-_u3-pad2_ u3 +a3 /z net-_u4-pad2_ u4 +a4 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad2_ /y ] net-_u6-pad3_ u6 +a6 [/y net-_u4-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends d_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin_Previous_Values.xml new file mode 100644 index 00000000..a999d337 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/eSim b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/eSim new file mode 160000 +Subproject de13d725c1ffd3e0754b22c0070c0a8be8b829e diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir new file mode 100644 index 00000000..6f011078 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir @@ -0,0 +1,16 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\e_origin\e_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:14:48 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /x /y /z Net-_U1-Pad4_ PORT +U2 /x Net-_U2-Pad2_ d_inverter +U3 /z Net-_U3-Pad2_ d_inverter +U4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad3_ d_and +U5 /y Net-_U3-Pad2_ Net-_U5-Pad3_ d_and +U6 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad4_ d_or + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir.out new file mode 100644 index 00000000..9aa2614a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir.out @@ -0,0 +1,32 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\e_origin\e_origin.cir + +* u1 /x /y /z net-_u1-pad4_ port +* u2 /x net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /y net-_u3-pad2_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_or +a1 /x net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/y net-_u3-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sch new file mode 100644 index 00000000..6054d4fa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:e_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F6CA9D +P 3600 2450 +F 0 "U1" H 3650 2550 30 0000 C CNN +F 1 "PORT" H 3600 2450 30 0000 C CNN +F 2 "" H 3600 2450 60 0000 C CNN +F 3 "" H 3600 2450 60 0000 C CNN + 1 3600 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67F6CAC2 +P 3600 2850 +F 0 "U1" H 3650 2950 30 0000 C CNN +F 1 "PORT" H 3600 2850 30 0000 C CNN +F 2 "" H 3600 2850 60 0000 C CNN +F 3 "" H 3600 2850 60 0000 C CNN + 2 3600 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67F6CAED +P 3600 3250 +F 0 "U1" H 3650 3350 30 0000 C CNN +F 1 "PORT" H 3600 3250 30 0000 C CNN +F 2 "" H 3600 3250 60 0000 C CNN +F 3 "" H 3600 3250 60 0000 C CNN + 3 3600 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 2450 4250 2450 +$Comp +L d_inverter U2 +U 1 1 67F6CB20 +P 4550 2450 +F 0 "U2" H 4550 2350 60 0000 C CNN +F 1 "d_inverter" H 4550 2600 60 0000 C CNN +F 2 "" H 4600 2400 60 0000 C CNN +F 3 "" H 4600 2400 60 0000 C CNN + 1 4550 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F6CB80 +P 4600 3250 +F 0 "U3" H 4600 3150 60 0000 C CNN +F 1 "d_inverter" H 4600 3400 60 0000 C CNN +F 2 "" H 4650 3200 60 0000 C CNN +F 3 "" H 4650 3200 60 0000 C CNN + 1 4600 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 3250 4300 3250 +Wire Wire Line + 4850 2450 5600 2450 +Wire Wire Line + 4900 3250 5250 3250 +Wire Wire Line + 5050 3250 5050 2550 +Wire Wire Line + 5050 2550 5600 2550 +Wire Wire Line + 3850 2850 5600 2850 +Wire Wire Line + 5250 3250 5250 2950 +Wire Wire Line + 5250 2950 5600 2950 +Connection ~ 5050 3250 +$Comp +L d_and U4 +U 1 1 67F6CBCC +P 6050 2550 +F 0 "U4" H 6050 2550 60 0000 C CNN +F 1 "d_and" H 6100 2650 60 0000 C CNN +F 2 "" H 6050 2550 60 0000 C CNN +F 3 "" H 6050 2550 60 0000 C CNN + 1 6050 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 67F6CC03 +P 6050 2950 +F 0 "U5" H 6050 2950 60 0000 C CNN +F 1 "d_and" H 6100 3050 60 0000 C CNN +F 2 "" H 6050 2950 60 0000 C CNN +F 3 "" H 6050 2950 60 0000 C CNN + 1 6050 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 67F6CC38 +P 7200 2600 +F 0 "U6" H 7200 2600 60 0000 C CNN +F 1 "d_or" H 7200 2700 60 0000 C CNN +F 2 "" H 7200 2600 60 0000 C CNN +F 3 "" H 7200 2600 60 0000 C CNN + 1 7200 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 2500 6750 2500 +Wire Wire Line + 6500 2900 6750 2900 +Wire Wire Line + 6750 2900 6750 2600 +Wire Wire Line + 7650 2550 7900 2550 +$Comp +L PORT U1 +U 4 1 67F6CCD0 +P 8150 2550 +F 0 "U1" H 8200 2650 30 0000 C CNN +F 1 "PORT" H 8150 2550 30 0000 C CNN +F 2 "" H 8150 2550 60 0000 C CNN +F 3 "" H 8150 2550 60 0000 C CNN + 4 8150 2550 + -1 0 0 1 +$EndComp +Text Label 3950 2450 0 60 ~ 0 +x +Text Label 4000 2850 0 60 ~ 0 +y +Text Label 3950 3250 0 60 ~ 0 +z +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub new file mode 100644 index 00000000..7be62924 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub @@ -0,0 +1,26 @@ +* Subcircuit e_origin +.subckt e_origin /x /y /z net-_u1-pad4_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\e_origin\e_origin.cir +* u2 /x net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /y net-_u3-pad2_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_or +a1 /x net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/y net-_u3-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends e_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin_Previous_Values.xml new file mode 100644 index 00000000..54d54feb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_or<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin-cache.lib new file mode 100644 index 00000000..20f5c6cc --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin-cache.lib @@ -0,0 +1,96 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir new file mode 100644 index 00000000..f630a09c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\f_origin\f_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 01:12:40 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /y Net-_U2-Pad2_ d_inverter +U3 /z Net-_U3-Pad2_ d_inverter +X1 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad5_ 4_OR +U4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad3_ d_and +U5 /x Net-_U2-Pad2_ Net-_U5-Pad3_ d_and +U6 /x Net-_U3-Pad2_ Net-_U6-Pad3_ d_and +U7 /w Net-_U2-Pad2_ Net-_U7-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir.out new file mode 100644 index 00000000..2a00b16f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir.out @@ -0,0 +1,38 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\f_origin\f_origin.cir + +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /y net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +x1 net-_u4-pad3_ net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad5_ 4_OR +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /x net-_u2-pad2_ net-_u5-pad3_ d_and +* u6 /x net-_u3-pad2_ net-_u6-pad3_ d_and +* u7 /w net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /y net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/x net-_u2-pad2_ ] net-_u5-pad3_ u5 +a5 [/x net-_u3-pad2_ ] net-_u6-pad3_ u6 +a6 [/w net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sch new file mode 100644 index 00000000..fc4bf555 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sch @@ -0,0 +1,259 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:a_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F6CCB0 +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F6CCB1 +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F6CCB2 +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F6CCB3 +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F6CCB6 +P 4100 2400 +F 0 "U2" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F6CCB7 +P 4800 2300 +F 0 "U3" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +Wire Wire Line + 3850 1550 3850 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 4100 2700 4100 4100 +Wire Wire Line + 3100 1550 3100 3600 +Wire Wire Line + 2350 1550 2350 4000 +$Comp +L 4_OR X1 +U 1 1 67F6CCBC +P 7000 3450 +F 0 "X1" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 2900 6650 3300 +Wire Wire Line + 7550 3450 7950 3450 +$Comp +L PORT U1 +U 5 1 67F6CCBD +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2900 4100 2850 +Wire Wire Line + 4100 2850 5150 2850 +Connection ~ 4100 2900 +Wire Wire Line + 4800 2950 5150 2950 +Connection ~ 4800 2950 +Wire Wire Line + 3100 3250 5150 3250 +Wire Wire Line + 4100 3350 5150 3350 +Connection ~ 4100 3350 +Wire Wire Line + 3100 3600 5150 3600 +Connection ~ 3100 3250 +Wire Wire Line + 4800 3700 5150 3700 +Connection ~ 4800 3700 +Wire Wire Line + 2350 4000 5150 4000 +Wire Wire Line + 4100 4100 5150 4100 +Wire Wire Line + 4450 1950 4450 1550 +Wire Wire Line + 3850 2100 4100 2100 +$Comp +L d_and U4 +U 1 1 67F6D0F4 +P 5600 2950 +F 0 "U4" H 5600 2950 60 0000 C CNN +F 1 "d_and" H 5650 3050 60 0000 C CNN +F 2 "" H 5600 2950 60 0000 C CNN +F 3 "" H 5600 2950 60 0000 C CNN + 1 5600 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 67F6D131 +P 5600 3350 +F 0 "U5" H 5600 3350 60 0000 C CNN +F 1 "d_and" H 5650 3450 60 0000 C CNN +F 2 "" H 5600 3350 60 0000 C CNN +F 3 "" H 5600 3350 60 0000 C CNN + 1 5600 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F6D172 +P 5600 3700 +F 0 "U6" H 5600 3700 60 0000 C CNN +F 1 "d_and" H 5650 3800 60 0000 C CNN +F 2 "" H 5600 3700 60 0000 C CNN +F 3 "" H 5600 3700 60 0000 C CNN + 1 5600 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F6D1AD +P 5600 4100 +F 0 "U7" H 5600 4100 60 0000 C CNN +F 1 "d_and" H 5650 4200 60 0000 C CNN +F 2 "" H 5600 4100 60 0000 C CNN +F 3 "" H 5600 4100 60 0000 C CNN + 1 5600 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 2900 6050 2900 +Wire Wire Line + 6050 3300 6350 3300 +Wire Wire Line + 6350 3300 6350 3400 +Wire Wire Line + 6350 3400 6650 3400 +Wire Wire Line + 6050 3650 6050 3500 +Wire Wire Line + 6050 3500 6650 3500 +Wire Wire Line + 6050 4050 6650 4050 +Wire Wire Line + 6650 4050 6650 3600 +Wire Wire Line + 4800 3700 4800 2600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sub new file mode 100644 index 00000000..275719f1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sub @@ -0,0 +1,32 @@ +* Subcircuit f_origin +.subckt f_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\f_origin\f_origin.cir +.include 4_OR.sub +* u2 /y net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +x1 net-_u4-pad3_ net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad5_ 4_OR +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /x net-_u2-pad2_ net-_u5-pad3_ d_and +* u6 /x net-_u3-pad2_ net-_u6-pad3_ d_and +* u7 /w net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /y net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/x net-_u2-pad2_ ] net-_u5-pad3_ u5 +a5 [/x net-_u3-pad2_ ] net-_u6-pad3_ u6 +a6 [/w net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends f_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin_Previous_Values.xml new file mode 100644 index 00000000..592103c4 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin-cache.lib new file mode 100644 index 00000000..20f5c6cc --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin-cache.lib @@ -0,0 +1,96 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir new file mode 100644 index 00000000..0a0e3f41 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir @@ -0,0 +1,19 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\g_origin\g_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:54:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U3 /y Net-_U3-Pad2_ d_inverter +U4 /z Net-_U4-Pad2_ d_inverter +X1 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U8-Pad3_ Net-_U1-Pad5_ 4_OR +U2 /x Net-_U2-Pad2_ d_inverter +U5 Net-_U2-Pad2_ /y Net-_U5-Pad3_ d_and +U6 /y Net-_U4-Pad2_ Net-_U6-Pad3_ d_and +U7 /x Net-_U3-Pad2_ Net-_U7-Pad3_ d_and +U8 /w Net-_U2-Pad2_ Net-_U8-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir.out new file mode 100644 index 00000000..bb3b0ad0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir.out @@ -0,0 +1,42 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\g_origin\g_origin.cir + +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x1 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad5_ 4_OR +* u2 /x net-_u2-pad2_ d_inverter +* u5 net-_u2-pad2_ /y net-_u5-pad3_ d_and +* u6 /y net-_u4-pad2_ net-_u6-pad3_ d_and +* u7 /x net-_u3-pad2_ net-_u7-pad3_ d_and +* u8 /w net-_u2-pad2_ net-_u8-pad3_ d_and +a1 /y net-_u3-pad2_ u3 +a2 /z net-_u4-pad2_ u4 +a3 /x net-_u2-pad2_ u2 +a4 [net-_u2-pad2_ /y ] net-_u5-pad3_ u5 +a5 [/y net-_u4-pad2_ ] net-_u6-pad3_ u6 +a6 [/x net-_u3-pad2_ ] net-_u7-pad3_ u7 +a7 [/w net-_u2-pad2_ ] net-_u8-pad3_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sch new file mode 100644 index 00000000..c0ef7cdd --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sch @@ -0,0 +1,272 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:g_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F6CE89 +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F6CE8A +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F6CE8B +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F6CE8C +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U3 +U 1 1 67F6CE8D +P 4100 2400 +F 0 "U3" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F6CE8E +P 4800 2300 +F 0 "U4" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X1 +U 1 1 67F6CE8F +P 7000 3450 +F 0 "X1" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67F6CE90 +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 3850 1550 3850 3500 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 3100 1550 3100 3900 +Wire Wire Line + 2350 1550 2350 4250 +Wire Wire Line + 7550 3450 7950 3450 +Wire Wire Line + 4450 1950 4450 1550 +Wire Wire Line + 3850 2100 4100 2100 +Wire Wire Line + 6650 3600 6650 4300 +$Comp +L d_inverter U2 +U 1 1 67F6CFF0 +P 3350 2350 +F 0 "U2" H 3350 2250 60 0000 C CNN +F 1 "d_inverter" H 3350 2500 60 0000 C CNN +F 2 "" H 3400 2300 60 0000 C CNN +F 3 "" H 3400 2300 60 0000 C CNN + 1 3350 2350 + 0 1 1 0 +$EndComp +Wire Wire Line + 3350 2650 3350 4350 +Wire Wire Line + 3350 3000 5250 3000 +Wire Wire Line + 3850 3100 5250 3100 +Connection ~ 3850 2100 +Wire Wire Line + 3850 3500 5250 3500 +Connection ~ 3850 3100 +Wire Wire Line + 4800 3600 5250 3600 +Connection ~ 4800 3600 +Wire Wire Line + 3100 3900 5250 3900 +Wire Wire Line + 4100 2700 4100 4000 +Wire Wire Line + 4100 4000 5250 4000 +Wire Wire Line + 2350 4250 5250 4250 +Wire Wire Line + 3350 4350 5250 4350 +Connection ~ 3350 3000 +Wire Wire Line + 4800 3600 4800 2600 +$Comp +L d_and U5 +U 1 1 67F6D168 +P 5700 3100 +F 0 "U5" H 5700 3100 60 0000 C CNN +F 1 "d_and" H 5750 3200 60 0000 C CNN +F 2 "" H 5700 3100 60 0000 C CNN +F 3 "" H 5700 3100 60 0000 C CNN + 1 5700 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F6D1A7 +P 5700 3600 +F 0 "U6" H 5700 3600 60 0000 C CNN +F 1 "d_and" H 5750 3700 60 0000 C CNN +F 2 "" H 5700 3600 60 0000 C CNN +F 3 "" H 5700 3600 60 0000 C CNN + 1 5700 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F6D1E4 +P 5700 4000 +F 0 "U7" H 5700 4000 60 0000 C CNN +F 1 "d_and" H 5750 4100 60 0000 C CNN +F 2 "" H 5700 4000 60 0000 C CNN +F 3 "" H 5700 4000 60 0000 C CNN + 1 5700 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 67F6D21B +P 5700 4350 +F 0 "U8" H 5700 4350 60 0000 C CNN +F 1 "d_and" H 5750 4450 60 0000 C CNN +F 2 "" H 5700 4350 60 0000 C CNN +F 3 "" H 5700 4350 60 0000 C CNN + 1 5700 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 4300 6150 4300 +Wire Wire Line + 6150 3950 6500 3950 +Wire Wire Line + 6500 3950 6500 3500 +Wire Wire Line + 6500 3500 6650 3500 +Wire Wire Line + 6150 3550 6150 3400 +Wire Wire Line + 6150 3400 6650 3400 +Wire Wire Line + 6150 3050 6650 3050 +Wire Wire Line + 6650 3050 6650 3300 +Wire Wire Line + 3350 2050 3100 2050 +Connection ~ 3100 2050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub new file mode 100644 index 00000000..e87dde76 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub @@ -0,0 +1,36 @@ +* Subcircuit g_origin +.subckt g_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\g_origin\g_origin.cir +.include 4_OR.sub +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x1 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad5_ 4_OR +* u2 /x net-_u2-pad2_ d_inverter +* u5 net-_u2-pad2_ /y net-_u5-pad3_ d_and +* u6 /y net-_u4-pad2_ net-_u6-pad3_ d_and +* u7 /x net-_u3-pad2_ net-_u7-pad3_ d_and +* u8 /w net-_u2-pad2_ net-_u8-pad3_ d_and +a1 /y net-_u3-pad2_ u3 +a2 /z net-_u4-pad2_ u4 +a3 /x net-_u2-pad2_ u2 +a4 [net-_u2-pad2_ /y ] net-_u5-pad3_ u5 +a5 [/y net-_u4-pad2_ ] net-_u6-pad3_ u6 +a6 [/x net-_u3-pad2_ ] net-_u7-pad3_ u7 +a7 [/w net-_u2-pad2_ ] net-_u8-pad3_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends g_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin_Previous_Values.xml new file mode 100644 index 00000000..80c572a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48-cache.lib new file mode 100644 index 00000000..18dc2f16 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 74_48 +# +DEF 74_48 X 0 40 Y Y 1 F N +F0 "X" -700 100 60 H V C CNN +F1 "74_48" -750 1150 60 H V C CNN +F2 "" -700 350 60 H I C CNN +F3 "" -700 350 60 H I C CNN +DRAW +S -300 1100 -1100 150 0 1 0 N +X w 1 -1300 1050 200 R 50 50 1 1 I +X x 2 -1300 950 200 R 50 50 1 1 I +X y 3 -1300 850 200 R 50 50 1 1 I +X z 4 -1300 750 200 R 50 50 1 1 I +X LT 5 -1300 600 200 R 50 50 1 1 I +X BI 6 -1300 500 200 R 50 50 1 1 I +X RBI 7 -1300 400 200 R 50 50 1 1 I +X a 8 -100 850 200 L 50 50 1 1 O +X b 9 -100 750 200 L 50 50 1 1 O +X c 10 -100 650 200 L 50 50 1 1 O +X d 11 -100 550 200 L 50 50 1 1 O +X e 12 -100 450 200 L 50 50 1 1 O +X f 13 -100 350 200 L 50 50 1 1 O +X g 14 -100 250 200 L 50 50 1 1 O +X GND 15 -1300 250 200 R 50 50 1 1 N +X vcc 16 -100 1000 200 L 50 50 1 1 N +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir new file mode 100644 index 00000000..bcc8495b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir @@ -0,0 +1,29 @@ +* C:\Users\Shanthipriya\eSim-Workspace\7447\7447.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 02:00:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v1 W GND pulse +v2 X GND pulse +v3 Y GND pulse +v4 Z GND pulse +v5 Net-_X1-Pad5_ GND DC +v6 Net-_X1-Pad6_ GND DC +v7 Net-_X1-Pad7_ GND DC +U1 Z plot_v1 +U2 Y plot_v1 +U3 X plot_v1 +U4 W plot_v1 +U5 a plot_v1 +U6 b plot_v1 +U7 c plot_v1 +U8 d plot_v1 +U9 e plot_v1 +U10 f plot_v1 +U11 g plot_v1 +X1 W X Y Z Net-_X1-Pad5_ Net-_X1-Pad6_ Net-_X1-Pad7_ a b c d e f g ? ? 74_48 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir.out new file mode 100644 index 00000000..2f14333c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir.out @@ -0,0 +1,32 @@ +* c:\users\shanthipriya\esim-workspace\7447\7447.cir + +.include 74ls47.sub +v1 w gnd pulse(0 5 0 1n 1n 16m 32m) +v2 x gnd pulse(0 5 0 1n 1n 8m 16m) +v3 y gnd pulse(0 5 0 1n 1n 4m 8m) +v4 z gnd pulse(0 5 0 1n 1n 2m 4m) +v5 net-_x1-pad5_ gnd dc 5 +v6 net-_x1-pad6_ gnd dc 5 +v7 net-_x1-pad7_ gnd dc 5 +* u1 z plot_v1 +* u2 y plot_v1 +* u3 x plot_v1 +* u4 w plot_v1 +* u5 a plot_v1 +* u6 b plot_v1 +* u7 c plot_v1 +* u8 d plot_v1 +* u9 e plot_v1 +* u10 f plot_v1 +* u11 g plot_v1 +x1 w x y z net-_x1-pad5_ net-_x1-pad6_ net-_x1-pad7_ a b c d e f g ? ? 74ls47 +.tran 1e-03 32e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(z)+6v(y)+12 v(x)+18 v(w)+24 v(a)+30v(b)+36 v(c)+42v(d)+48 v(e)+54v(f)+60v(g) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.proj b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.proj new file mode 100644 index 00000000..4fc1deab --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.proj @@ -0,0 +1 @@ +schematicFile 7447.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.sch new file mode 100644 index 00000000..fa498ac7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.sch @@ -0,0 +1,442 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:7448_ic1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pulse v1 +U 1 1 67F6DCAF +P 3000 1200 +F 0 "v1" H 2800 1300 60 0000 C CNN +F 1 "pulse" H 2800 1150 60 0000 C CNN +F 2 "R1" H 2700 1200 60 0000 C CNN +F 3 "" H 3000 1200 60 0000 C CNN + 1 3000 1200 + 0 1 1 0 +$EndComp +$Comp +L pulse v2 +U 1 1 67F6DCF2 +P 3000 1700 +F 0 "v2" H 2800 1800 60 0000 C CNN +F 1 "pulse" H 2800 1650 60 0000 C CNN +F 2 "R1" H 2700 1700 60 0000 C CNN +F 3 "" H 3000 1700 60 0000 C CNN + 1 3000 1700 + 0 1 1 0 +$EndComp +$Comp +L pulse v3 +U 1 1 67F6DD65 +P 3000 2200 +F 0 "v3" H 2800 2300 60 0000 C CNN +F 1 "pulse" H 2800 2150 60 0000 C CNN +F 2 "R1" H 2700 2200 60 0000 C CNN +F 3 "" H 3000 2200 60 0000 C CNN + 1 3000 2200 + 0 1 1 0 +$EndComp +$Comp +L pulse v4 +U 1 1 67F6DD6B +P 3000 2700 +F 0 "v4" H 2800 2800 60 0000 C CNN +F 1 "pulse" H 2800 2650 60 0000 C CNN +F 2 "R1" H 2700 2700 60 0000 C CNN +F 3 "" H 3000 2700 60 0000 C CNN + 1 3000 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 3450 1200 5300 1200 +Wire Wire Line + 4700 1200 4700 2400 +Wire Wire Line + 3450 1700 4800 1700 +Wire Wire Line + 4500 1700 4500 2500 +Wire Wire Line + 4500 2500 4700 2500 +Wire Wire Line + 3450 2200 4350 2200 +Wire Wire Line + 4350 2200 4350 2600 +Wire Wire Line + 4350 2600 4700 2600 +Wire Wire Line + 3450 2700 4700 2700 +$Comp +L DC v5 +U 1 1 67F6DE86 +P 3050 3150 +F 0 "v5" H 2850 3250 60 0000 C CNN +F 1 "DC" H 2850 3100 60 0000 C CNN +F 2 "R1" H 2750 3150 60 0000 C CNN +F 3 "" H 3050 3150 60 0000 C CNN + 1 3050 3150 + 0 1 1 0 +$EndComp +$Comp +L DC v6 +U 1 1 67F6DEC1 +P 3050 3650 +F 0 "v6" H 2850 3750 60 0000 C CNN +F 1 "DC" H 2850 3600 60 0000 C CNN +F 2 "R1" H 2750 3650 60 0000 C CNN +F 3 "" H 3050 3650 60 0000 C CNN + 1 3050 3650 + 0 1 1 0 +$EndComp +$Comp +L DC v7 +U 1 1 67F6DF04 +P 3100 4150 +F 0 "v7" H 2900 4250 60 0000 C CNN +F 1 "DC" H 2900 4100 60 0000 C CNN +F 2 "R1" H 2800 4150 60 0000 C CNN +F 3 "" H 3100 4150 60 0000 C CNN + 1 3100 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 3500 3150 3500 2850 +Wire Wire Line + 3500 2850 4700 2850 +Wire Wire Line + 3500 3650 3600 3650 +Wire Wire Line + 3600 3650 3600 2950 +Wire Wire Line + 3600 2950 4700 2950 +Wire Wire Line + 3550 4150 3700 4150 +Wire Wire Line + 3700 4150 3700 3050 +Wire Wire Line + 3700 3050 4700 3050 +$Comp +L GND #PWR01 +U 1 1 67F6DFE6 +P 2450 4300 +F 0 "#PWR01" H 2450 4050 50 0001 C CNN +F 1 "GND" H 2450 4150 50 0000 C CNN +F 2 "" H 2450 4300 50 0001 C CNN +F 3 "" H 2450 4300 50 0001 C CNN + 1 2450 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 4150 2450 4150 +Wire Wire Line + 2450 1200 2450 4300 +Wire Wire Line + 2600 3650 2450 3650 +Connection ~ 2450 4150 +Wire Wire Line + 2600 3150 2450 3150 +Connection ~ 2450 3650 +Wire Wire Line + 2550 2700 2450 2700 +Connection ~ 2450 3150 +Wire Wire Line + 2550 2200 2450 2200 +Connection ~ 2450 2700 +Wire Wire Line + 2550 1700 2450 1700 +Connection ~ 2450 2200 +Wire Wire Line + 2550 1200 2450 1200 +Connection ~ 2450 1700 +$Comp +L plot_v1 U1 +U 1 1 67F6E0F7 +P 3850 1200 +F 0 "U1" H 3850 1700 60 0000 C CNN +F 1 "plot_v1" H 4050 1550 60 0000 C CNN +F 2 "" H 3850 1200 60 0000 C CNN +F 3 "" H 3850 1200 60 0000 C CNN + 1 3850 1200 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 67F6E12E +P 4300 1200 +F 0 "U2" H 4300 1700 60 0000 C CNN +F 1 "plot_v1" H 4500 1550 60 0000 C CNN +F 2 "" H 4300 1200 60 0000 C CNN +F 3 "" H 4300 1200 60 0000 C CNN + 1 4300 1200 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 67F6E18B +P 4800 1250 +F 0 "U3" H 4800 1750 60 0000 C CNN +F 1 "plot_v1" H 5000 1600 60 0000 C CNN +F 2 "" H 4800 1250 60 0000 C CNN +F 3 "" H 4800 1250 60 0000 C CNN + 1 4800 1250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 67F6E1BC +P 5300 1250 +F 0 "U4" H 5300 1750 60 0000 C CNN +F 1 "plot_v1" H 5500 1600 60 0000 C CNN +F 2 "" H 5300 1250 60 0000 C CNN +F 3 "" H 5300 1250 60 0000 C CNN + 1 5300 1250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 1000 3850 2700 +Connection ~ 3850 2700 +Wire Wire Line + 4300 1000 4300 2200 +Connection ~ 4300 2200 +Wire Wire Line + 4800 1700 4800 1050 +Connection ~ 4500 1700 +Wire Wire Line + 5300 1200 5300 1050 +Connection ~ 4700 1200 +Text GLabel 5050 1350 0 60 Input ~ 0 +W +Wire Wire Line + 5050 1350 5150 1350 +Wire Wire Line + 5150 1350 5150 1200 +Connection ~ 5150 1200 +Text GLabel 4500 1550 0 60 Input ~ 0 +X +Wire Wire Line + 4500 1550 4800 1550 +Connection ~ 4800 1550 +Text GLabel 4150 1900 0 60 Input ~ 0 +Y +Wire Wire Line + 4150 1900 4300 1900 +Connection ~ 4300 1900 +Text GLabel 3650 2450 0 60 Input ~ 0 +Z +Wire Wire Line + 3650 2450 3850 2450 +Connection ~ 3850 2450 +$Comp +L plot_v1 U5 +U 1 1 67F6E42E +P 6300 2800 +F 0 "U5" H 6300 3300 60 0000 C CNN +F 1 "plot_v1" H 6500 3150 60 0000 C CNN +F 2 "" H 6300 2800 60 0000 C CNN +F 3 "" H 6300 2800 60 0000 C CNN + 1 6300 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 67F6E47D +P 6750 2800 +F 0 "U6" H 6750 3300 60 0000 C CNN +F 1 "plot_v1" H 6950 3150 60 0000 C CNN +F 2 "" H 6750 2800 60 0000 C CNN +F 3 "" H 6750 2800 60 0000 C CNN + 1 6750 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 67F6E4BA +P 7150 2800 +F 0 "U7" H 7150 3300 60 0000 C CNN +F 1 "plot_v1" H 7350 3150 60 0000 C CNN +F 2 "" H 7150 2800 60 0000 C CNN +F 3 "" H 7150 2800 60 0000 C CNN + 1 7150 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 67F6E4FB +P 7550 2800 +F 0 "U8" H 7550 3300 60 0000 C CNN +F 1 "plot_v1" H 7750 3150 60 0000 C CNN +F 2 "" H 7550 2800 60 0000 C CNN +F 3 "" H 7550 2800 60 0000 C CNN + 1 7550 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 67F6E53C +P 8000 2800 +F 0 "U9" H 8000 3300 60 0000 C CNN +F 1 "plot_v1" H 8200 3150 60 0000 C CNN +F 2 "" H 8000 2800 60 0000 C CNN +F 3 "" H 8000 2800 60 0000 C CNN + 1 8000 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 67F6E57F +P 8400 2800 +F 0 "U10" H 8400 3300 60 0000 C CNN +F 1 "plot_v1" H 8600 3150 60 0000 C CNN +F 2 "" H 8400 2800 60 0000 C CNN +F 3 "" H 8400 2800 60 0000 C CNN + 1 8400 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 67F6E5BC +P 8800 2800 +F 0 "U11" H 8800 3300 60 0000 C CNN +F 1 "plot_v1" H 9000 3150 60 0000 C CNN +F 2 "" H 8800 2800 60 0000 C CNN +F 3 "" H 8800 2800 60 0000 C CNN + 1 8800 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 2600 5900 2600 +Wire Wire Line + 6750 2600 6750 2700 +Wire Wire Line + 6750 2700 5900 2700 +Wire Wire Line + 7150 2600 7150 2800 +Wire Wire Line + 7150 2800 5900 2800 +Wire Wire Line + 7550 2600 7550 2900 +Wire Wire Line + 7550 2900 5900 2900 +Wire Wire Line + 8000 2600 8000 3000 +Wire Wire Line + 8000 3000 5900 3000 +Wire Wire Line + 8400 2600 8400 3100 +Wire Wire Line + 8400 3100 5900 3100 +Wire Wire Line + 8800 2600 8800 3200 +Wire Wire Line + 8800 3200 5900 3200 +Text GLabel 6100 3300 0 60 Input ~ 0 +a +Wire Wire Line + 6100 3300 6150 3300 +Wire Wire Line + 6150 3300 6150 2600 +Connection ~ 6150 2600 +Text GLabel 6050 3500 0 60 Input ~ 0 +b +Wire Wire Line + 6050 3500 6300 3500 +Wire Wire Line + 6300 3500 6300 2700 +Connection ~ 6300 2700 +Text GLabel 6450 3350 0 60 Input ~ 0 +c +Wire Wire Line + 6450 3350 6550 3350 +Wire Wire Line + 6550 3350 6550 2800 +Connection ~ 6550 2800 +Text GLabel 6550 3550 0 60 Input ~ 0 +d +Wire Wire Line + 6550 3550 6700 3550 +Wire Wire Line + 6700 3550 6700 2900 +Connection ~ 6700 2900 +Text GLabel 6850 3350 0 60 Input ~ 0 +e +Wire Wire Line + 6850 3350 6900 3350 +Wire Wire Line + 6900 3350 6900 3000 +Connection ~ 6900 3000 +Text GLabel 6950 3500 0 60 Input ~ 0 +f +Wire Wire Line + 6950 3500 7050 3500 +Wire Wire Line + 7050 3500 7050 3100 +Connection ~ 7050 3100 +Text GLabel 7250 3400 0 60 Input ~ 0 +g +Wire Wire Line + 7250 3400 7300 3400 +Wire Wire Line + 7300 3400 7300 3200 +Connection ~ 7300 3200 +$Comp +L 74_48 X? +U 1 1 67F82B18 +P 6000 3450 +F 0 "X?" H 5250 3500 60 0000 C CNN +F 1 "74_48" H 5250 4650 60 0000 C CNN +F 2 "" H 6000 3450 60 0001 C CNN +F 3 "" H 6000 3450 60 0001 C CNN + 1 6000 3450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48_Previous_Values.xml new file mode 100644 index 00000000..96049e0e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">16m</field5><field5 name="Period">32m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">8m</field5><field5 name="Period">16m</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">4m</field5></v4><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v6 name="Source type">dc<field1 name="Value">5</field1></v6><v7 name="Source type">dc<field1 name="Value">5</field1></v7></source><model /><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls47</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">32</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/analysis new file mode 100644 index 00000000..c178a1dc --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/analysis @@ -0,0 +1 @@ +.tran 1e-09 5e-06 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72-cache.lib new file mode 100644 index 00000000..1cdee83e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72-cache.lib @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir new file mode 100644 index 00000000..f3277b9f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\internal72\internal72.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 09:40:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U5-Pad3_ d_nand +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U7 Net-_U5-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_dff +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_dff +U6 Net-_U1-Pad2_ Net-_U6-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ ? ? Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir.out new file mode 100644 index 00000000..ec11a6c2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir + +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sch new file mode 100644 index 00000000..a5f97c98 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sch @@ -0,0 +1,299 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:internal72-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 68314F2B +P 4150 2800 +F 0 "U3" H 4150 2800 60 0000 C CNN +F 1 "d_nand" H 4200 2900 60 0000 C CNN +F 2 "" H 4150 2800 60 0000 C CNN +F 3 "" H 4150 2800 60 0000 C CNN + 1 4150 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68314FDD +P 4150 3350 +F 0 "U4" H 4150 3350 60 0000 C CNN +F 1 "d_nand" H 4200 3450 60 0000 C CNN +F 2 "" H 4150 3350 60 0000 C CNN +F 3 "" H 4150 3350 60 0000 C CNN + 1 4150 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68315038 +P 5250 3100 +F 0 "U5" H 5250 3100 60 0000 C CNN +F 1 "d_nand" H 5300 3200 60 0000 C CNN +F 2 "" H 5250 3100 60 0000 C CNN +F 3 "" H 5250 3100 60 0000 C CNN + 1 5250 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 2750 4800 2750 +Wire Wire Line + 4800 2750 4800 3000 +Wire Wire Line + 4600 3300 4800 3300 +Wire Wire Line + 4800 3300 4800 3100 +$Comp +L d_inverter U2 +U 1 1 68315089 +P 3200 3250 +F 0 "U2" H 3200 3150 60 0000 C CNN +F 1 "d_inverter" H 3200 3400 60 0000 C CNN +F 2 "" H 3250 3200 60 0000 C CNN +F 3 "" H 3250 3200 60 0000 C CNN + 1 3200 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 3250 3700 3250 +Wire Wire Line + 3700 2800 2600 2800 +Wire Wire Line + 2650 3250 2900 3250 +$Comp +L d_dff U7 +U 1 1 683150F6 +P 6850 3400 +F 0 "U7" H 6850 3400 60 0000 C CNN +F 1 "d_dff" H 6850 3550 60 0000 C CNN +F 2 "" H 6850 3400 60 0000 C CNN +F 3 "" H 6850 3400 60 0000 C CNN + 1 6850 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U8 +U 1 1 68315165 +P 8650 3400 +F 0 "U8" H 8650 3400 60 0000 C CNN +F 1 "d_dff" H 8650 3550 60 0000 C CNN +F 2 "" H 8650 3400 60 0000 C CNN +F 3 "" H 8650 3400 60 0000 C CNN + 1 8650 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 3050 6300 3050 +Wire Wire Line + 3700 3350 3400 3350 +Wire Wire Line + 3400 3350 3400 4300 +Wire Wire Line + 3400 4300 7650 4300 +Wire Wire Line + 7400 3050 8100 3050 +Wire Wire Line + 7650 4300 7650 3050 +Connection ~ 7650 3050 +Wire Wire Line + 7400 3700 7700 3700 +Wire Wire Line + 7700 3700 7700 1950 +Wire Wire Line + 7700 1950 3400 1950 +Wire Wire Line + 3400 1950 3400 2700 +Wire Wire Line + 3400 2700 3700 2700 +Wire Wire Line + 6300 3700 2600 3700 +$Comp +L d_inverter U6 +U 1 1 68315227 +P 6300 4750 +F 0 "U6" H 6300 4650 60 0000 C CNN +F 1 "d_inverter" H 6300 4900 60 0000 C CNN +F 2 "" H 6350 4700 60 0000 C CNN +F 3 "" H 6350 4700 60 0000 C CNN + 1 6300 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6000 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3700 +Connection ~ 5550 3700 +Wire Wire Line + 6600 4750 7900 4750 +Wire Wire Line + 7900 4750 7900 3700 +Wire Wire Line + 7900 3700 8100 3700 +Wire Wire Line + 6850 4200 8650 4200 +Wire Wire Line + 8650 4000 8650 5000 +Connection ~ 8650 4200 +Wire Wire Line + 6850 2750 6850 2350 +Wire Wire Line + 6850 2350 8650 2350 +Wire Wire Line + 8650 1400 8650 2750 +Connection ~ 8650 2350 +Wire Wire Line + 6850 4200 6850 4000 +$Comp +L PORT U1 +U 1 1 683153A5 +P 2350 2800 +F 0 "U1" H 2400 2900 30 0000 C CNN +F 1 "PORT" H 2350 2800 30 0000 C CNN +F 2 "" H 2350 2800 60 0000 C CNN +F 3 "" H 2350 2800 60 0000 C CNN + 1 2350 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 683153DC +P 2400 3250 +F 0 "U1" H 2450 3350 30 0000 C CNN +F 1 "PORT" H 2400 3250 30 0000 C CNN +F 2 "" H 2400 3250 60 0000 C CNN +F 3 "" H 2400 3250 60 0000 C CNN + 3 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6831542D +P 2350 3700 +F 0 "U1" H 2400 3800 30 0000 C CNN +F 1 "PORT" H 2350 3700 30 0000 C CNN +F 2 "" H 2350 3700 60 0000 C CNN +F 3 "" H 2350 3700 60 0000 C CNN + 2 2350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6831548B +P 8400 5000 +F 0 "U1" H 8450 5100 30 0000 C CNN +F 1 "PORT" H 8400 5000 30 0000 C CNN +F 2 "" H 8400 5000 60 0000 C CNN +F 3 "" H 8400 5000 60 0000 C CNN + 7 8400 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68315516 +P 8400 1400 +F 0 "U1" H 8450 1500 30 0000 C CNN +F 1 "PORT" H 8400 1400 30 0000 C CNN +F 2 "" H 8400 1400 60 0000 C CNN +F 3 "" H 8400 1400 60 0000 C CNN + 6 8400 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68315583 +P 9450 3050 +F 0 "U1" H 9500 3150 30 0000 C CNN +F 1 "PORT" H 9450 3050 30 0000 C CNN +F 2 "" H 9450 3050 60 0000 C CNN +F 3 "" H 9450 3050 60 0000 C CNN + 8 9450 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 683155FA +P 9450 3700 +F 0 "U1" H 9500 3800 30 0000 C CNN +F 1 "PORT" H 9450 3700 30 0000 C CNN +F 2 "" H 9450 3700 60 0000 C CNN +F 3 "" H 9450 3700 60 0000 C CNN + 9 9450 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6831563D +P 7050 5450 +F 0 "U1" H 7100 5550 30 0000 C CNN +F 1 "PORT" H 7050 5450 30 0000 C CNN +F 2 "" H 7050 5450 60 0000 C CNN +F 3 "" H 7050 5450 60 0000 C CNN + 4 7050 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68315682 +P 7050 5650 +F 0 "U1" H 7100 5750 30 0000 C CNN +F 1 "PORT" H 7050 5650 30 0000 C CNN +F 2 "" H 7050 5650 60 0000 C CNN +F 3 "" H 7050 5650 60 0000 C CNN + 5 7050 5650 + 1 0 0 -1 +$EndComp +NoConn ~ 7300 5450 +NoConn ~ 7300 5650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sub new file mode 100644 index 00000000..4ff0c262 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sub @@ -0,0 +1,34 @@ +* Subcircuit internal72 +.subckt internal72 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends internal72
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72_Previous_Values.xml new file mode 100644 index 00000000..ec31c02b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u4 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /></u3><u3 name="type">d_srlatch<field1 name="Enter SR Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for SR Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_srlatch<field12 name="Enter SR Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for SR Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u6><u2 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_and<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_dff<field13 name="Enter Clk Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Clk Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u7><u8 name="type">d_dff<field23 name="Enter Clk Delay (default=1.0e-9)" /><field24 name="Enter Set Delay (default=1.0e-9)" /><field25 name="Enter Reset Delay (default=1.0)" /><field26 name="Enter IC (default=0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter value for Clk Load (default=1.0e-12)" /><field29 name="Enter value for Set Load (default=1.0e-12)" /><field30 name="Enter value for Reset Load (default=1.0e-12)" /><field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72-cache.lib new file mode 100644 index 00000000..1cdee83e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72-cache.lib @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir new file mode 100644 index 00000000..f3277b9f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\internal72\internal72.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 09:40:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U5-Pad3_ d_nand +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U7 Net-_U5-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_dff +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_dff +U6 Net-_U1-Pad2_ Net-_U6-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ ? ? Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out new file mode 100644 index 00000000..ec11a6c2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir + +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sch new file mode 100644 index 00000000..a5f97c98 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sch @@ -0,0 +1,299 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:internal72-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 68314F2B +P 4150 2800 +F 0 "U3" H 4150 2800 60 0000 C CNN +F 1 "d_nand" H 4200 2900 60 0000 C CNN +F 2 "" H 4150 2800 60 0000 C CNN +F 3 "" H 4150 2800 60 0000 C CNN + 1 4150 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68314FDD +P 4150 3350 +F 0 "U4" H 4150 3350 60 0000 C CNN +F 1 "d_nand" H 4200 3450 60 0000 C CNN +F 2 "" H 4150 3350 60 0000 C CNN +F 3 "" H 4150 3350 60 0000 C CNN + 1 4150 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68315038 +P 5250 3100 +F 0 "U5" H 5250 3100 60 0000 C CNN +F 1 "d_nand" H 5300 3200 60 0000 C CNN +F 2 "" H 5250 3100 60 0000 C CNN +F 3 "" H 5250 3100 60 0000 C CNN + 1 5250 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 2750 4800 2750 +Wire Wire Line + 4800 2750 4800 3000 +Wire Wire Line + 4600 3300 4800 3300 +Wire Wire Line + 4800 3300 4800 3100 +$Comp +L d_inverter U2 +U 1 1 68315089 +P 3200 3250 +F 0 "U2" H 3200 3150 60 0000 C CNN +F 1 "d_inverter" H 3200 3400 60 0000 C CNN +F 2 "" H 3250 3200 60 0000 C CNN +F 3 "" H 3250 3200 60 0000 C CNN + 1 3200 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 3250 3700 3250 +Wire Wire Line + 3700 2800 2600 2800 +Wire Wire Line + 2650 3250 2900 3250 +$Comp +L d_dff U7 +U 1 1 683150F6 +P 6850 3400 +F 0 "U7" H 6850 3400 60 0000 C CNN +F 1 "d_dff" H 6850 3550 60 0000 C CNN +F 2 "" H 6850 3400 60 0000 C CNN +F 3 "" H 6850 3400 60 0000 C CNN + 1 6850 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U8 +U 1 1 68315165 +P 8650 3400 +F 0 "U8" H 8650 3400 60 0000 C CNN +F 1 "d_dff" H 8650 3550 60 0000 C CNN +F 2 "" H 8650 3400 60 0000 C CNN +F 3 "" H 8650 3400 60 0000 C CNN + 1 8650 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 3050 6300 3050 +Wire Wire Line + 3700 3350 3400 3350 +Wire Wire Line + 3400 3350 3400 4300 +Wire Wire Line + 3400 4300 7650 4300 +Wire Wire Line + 7400 3050 8100 3050 +Wire Wire Line + 7650 4300 7650 3050 +Connection ~ 7650 3050 +Wire Wire Line + 7400 3700 7700 3700 +Wire Wire Line + 7700 3700 7700 1950 +Wire Wire Line + 7700 1950 3400 1950 +Wire Wire Line + 3400 1950 3400 2700 +Wire Wire Line + 3400 2700 3700 2700 +Wire Wire Line + 6300 3700 2600 3700 +$Comp +L d_inverter U6 +U 1 1 68315227 +P 6300 4750 +F 0 "U6" H 6300 4650 60 0000 C CNN +F 1 "d_inverter" H 6300 4900 60 0000 C CNN +F 2 "" H 6350 4700 60 0000 C CNN +F 3 "" H 6350 4700 60 0000 C CNN + 1 6300 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6000 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3700 +Connection ~ 5550 3700 +Wire Wire Line + 6600 4750 7900 4750 +Wire Wire Line + 7900 4750 7900 3700 +Wire Wire Line + 7900 3700 8100 3700 +Wire Wire Line + 6850 4200 8650 4200 +Wire Wire Line + 8650 4000 8650 5000 +Connection ~ 8650 4200 +Wire Wire Line + 6850 2750 6850 2350 +Wire Wire Line + 6850 2350 8650 2350 +Wire Wire Line + 8650 1400 8650 2750 +Connection ~ 8650 2350 +Wire Wire Line + 6850 4200 6850 4000 +$Comp +L PORT U1 +U 1 1 683153A5 +P 2350 2800 +F 0 "U1" H 2400 2900 30 0000 C CNN +F 1 "PORT" H 2350 2800 30 0000 C CNN +F 2 "" H 2350 2800 60 0000 C CNN +F 3 "" H 2350 2800 60 0000 C CNN + 1 2350 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 683153DC +P 2400 3250 +F 0 "U1" H 2450 3350 30 0000 C CNN +F 1 "PORT" H 2400 3250 30 0000 C CNN +F 2 "" H 2400 3250 60 0000 C CNN +F 3 "" H 2400 3250 60 0000 C CNN + 3 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6831542D +P 2350 3700 +F 0 "U1" H 2400 3800 30 0000 C CNN +F 1 "PORT" H 2350 3700 30 0000 C CNN +F 2 "" H 2350 3700 60 0000 C CNN +F 3 "" H 2350 3700 60 0000 C CNN + 2 2350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6831548B +P 8400 5000 +F 0 "U1" H 8450 5100 30 0000 C CNN +F 1 "PORT" H 8400 5000 30 0000 C CNN +F 2 "" H 8400 5000 60 0000 C CNN +F 3 "" H 8400 5000 60 0000 C CNN + 7 8400 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68315516 +P 8400 1400 +F 0 "U1" H 8450 1500 30 0000 C CNN +F 1 "PORT" H 8400 1400 30 0000 C CNN +F 2 "" H 8400 1400 60 0000 C CNN +F 3 "" H 8400 1400 60 0000 C CNN + 6 8400 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68315583 +P 9450 3050 +F 0 "U1" H 9500 3150 30 0000 C CNN +F 1 "PORT" H 9450 3050 30 0000 C CNN +F 2 "" H 9450 3050 60 0000 C CNN +F 3 "" H 9450 3050 60 0000 C CNN + 8 9450 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 683155FA +P 9450 3700 +F 0 "U1" H 9500 3800 30 0000 C CNN +F 1 "PORT" H 9450 3700 30 0000 C CNN +F 2 "" H 9450 3700 60 0000 C CNN +F 3 "" H 9450 3700 60 0000 C CNN + 9 9450 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6831563D +P 7050 5450 +F 0 "U1" H 7100 5550 30 0000 C CNN +F 1 "PORT" H 7050 5450 30 0000 C CNN +F 2 "" H 7050 5450 60 0000 C CNN +F 3 "" H 7050 5450 60 0000 C CNN + 4 7050 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68315682 +P 7050 5650 +F 0 "U1" H 7100 5750 30 0000 C CNN +F 1 "PORT" H 7050 5650 30 0000 C CNN +F 2 "" H 7050 5650 60 0000 C CNN +F 3 "" H 7050 5650 60 0000 C CNN + 5 7050 5650 + 1 0 0 -1 +$EndComp +NoConn ~ 7300 5450 +NoConn ~ 7300 5650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sub new file mode 100644 index 00000000..4ff0c262 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sub @@ -0,0 +1,34 @@ +* Subcircuit internal72 +.subckt internal72 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends internal72
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72_Previous_Values.xml new file mode 100644 index 00000000..ec31c02b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u4 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /></u3><u3 name="type">d_srlatch<field1 name="Enter SR Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for SR Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_srlatch<field12 name="Enter SR Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for SR Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u6><u2 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_and<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_dff<field13 name="Enter Clk Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Clk Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u7><u8 name="type">d_dff<field23 name="Enter Clk Delay (default=1.0e-9)" /><field24 name="Enter Set Delay (default=1.0e-9)" /><field25 name="Enter Reset Delay (default=1.0)" /><field26 name="Enter IC (default=0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter value for Clk Load (default=1.0e-12)" /><field29 name="Enter value for Set Load (default=1.0e-12)" /><field30 name="Enter value for Reset Load (default=1.0e-12)" /><field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff-cache.lib new file mode 100644 index 00000000..ce6d8814 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir new file mode 100644 index 00000000..2a7b848b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir @@ -0,0 +1,17 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\jkff\jkff.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/13/25 23:38:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U2-Pad3_ d_nand +U4 Net-_U2-Pad3_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U1-Pad2_ Net-_U5-Pad3_ d_nand +U6 Net-_U4-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad4_ d_nand +U7 Net-_U1-Pad4_ Net-_U5-Pad3_ Net-_U1-Pad5_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out new file mode 100644 index 00000000..03c161c5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out @@ -0,0 +1,36 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\jkff\jkff.cir + +* u2 net-_u1-pad5_ net-_u1-pad1_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad2_ net-_u5-pad3_ d_nand +* u6 net-_u4-pad3_ net-_u1-pad5_ net-_u1-pad4_ d_nand +* u7 net-_u1-pad4_ net-_u5-pad3_ net-_u1-pad5_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad5_ net-_u1-pad1_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u1-pad5_ ] net-_u1-pad4_ u6 +a6 [net-_u1-pad4_ net-_u5-pad3_ ] net-_u1-pad5_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sch new file mode 100644 index 00000000..82e3efd9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sch @@ -0,0 +1,230 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 68238979 +P 3900 2300 +F 0 "U2" H 3900 2300 60 0000 C CNN +F 1 "d_nand" H 3950 2400 60 0000 C CNN +F 2 "" H 3900 2300 60 0000 C CNN +F 3 "" H 3900 2300 60 0000 C CNN + 1 3900 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 6823899E +P 4900 2350 +F 0 "U4" H 4900 2350 60 0000 C CNN +F 1 "d_nand" H 4950 2450 60 0000 C CNN +F 2 "" H 4900 2350 60 0000 C CNN +F 3 "" H 4900 2350 60 0000 C CNN + 1 4900 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 68238A3B +P 3900 3500 +F 0 "U3" H 3900 3500 60 0000 C CNN +F 1 "d_nand" H 3950 3600 60 0000 C CNN +F 2 "" H 3900 3500 60 0000 C CNN +F 3 "" H 3900 3500 60 0000 C CNN + 1 3900 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68238A41 +P 4950 3550 +F 0 "U5" H 4950 3550 60 0000 C CNN +F 1 "d_nand" H 5000 3650 60 0000 C CNN +F 2 "" H 4950 3550 60 0000 C CNN +F 3 "" H 4950 3550 60 0000 C CNN + 1 4950 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 2250 4350 2250 +Wire Wire Line + 4500 3450 4350 3450 +$Comp +L d_nand U6 +U 1 1 68238A9E +P 6300 2400 +F 0 "U6" H 6300 2400 60 0000 C CNN +F 1 "d_nand" H 6350 2500 60 0000 C CNN +F 2 "" H 6300 2400 60 0000 C CNN +F 3 "" H 6300 2400 60 0000 C CNN + 1 6300 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 68238B01 +P 6300 3500 +F 0 "U7" H 6300 3500 60 0000 C CNN +F 1 "d_nand" H 6350 3600 60 0000 C CNN +F 2 "" H 6300 3500 60 0000 C CNN +F 3 "" H 6300 3500 60 0000 C CNN + 1 6300 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3450 2200 3450 1950 +Wire Wire Line + 3450 1950 7250 1950 +Wire Wire Line + 6750 2350 7600 2350 +Wire Wire Line + 6750 3450 7650 3450 +Wire Wire Line + 7250 1950 7250 3450 +Connection ~ 7250 3450 +Wire Wire Line + 7100 2350 7100 3850 +Wire Wire Line + 7100 3850 3450 3850 +Wire Wire Line + 3450 3850 3450 3500 +Connection ~ 7100 2350 +Wire Wire Line + 7000 2350 7000 3050 +Wire Wire Line + 7000 3050 5850 3050 +Wire Wire Line + 5850 3050 5850 3400 +Connection ~ 7000 2350 +Wire Wire Line + 5850 2400 5850 2800 +Wire Wire Line + 5850 2800 6900 2800 +Wire Wire Line + 6900 2800 6900 3450 +Connection ~ 6900 3450 +Wire Wire Line + 5850 2300 5350 2300 +Wire Wire Line + 5850 3500 5400 3500 +Wire Wire Line + 4450 2350 4400 2350 +Wire Wire Line + 4400 2350 4400 3550 +Wire Wire Line + 4400 3550 4500 3550 +Wire Wire Line + 3450 2300 3000 2300 +Wire Wire Line + 3450 3400 3000 3400 +Wire Wire Line + 4400 2800 3000 2800 +Connection ~ 4400 2800 +$Comp +L PORT U1 +U 1 1 68238C95 +P 2750 2300 +F 0 "U1" H 2800 2400 30 0000 C CNN +F 1 "PORT" H 2750 2300 30 0000 C CNN +F 2 "" H 2750 2300 60 0000 C CNN +F 3 "" H 2750 2300 60 0000 C CNN + 1 2750 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68238CDA +P 2750 2800 +F 0 "U1" H 2800 2900 30 0000 C CNN +F 1 "PORT" H 2750 2800 30 0000 C CNN +F 2 "" H 2750 2800 60 0000 C CNN +F 3 "" H 2750 2800 60 0000 C CNN + 2 2750 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68238D13 +P 2750 3400 +F 0 "U1" H 2800 3500 30 0000 C CNN +F 1 "PORT" H 2750 3400 30 0000 C CNN +F 2 "" H 2750 3400 60 0000 C CNN +F 3 "" H 2750 3400 60 0000 C CNN + 3 2750 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68238D5C +P 7850 2350 +F 0 "U1" H 7900 2450 30 0000 C CNN +F 1 "PORT" H 7850 2350 30 0000 C CNN +F 2 "" H 7850 2350 60 0000 C CNN +F 3 "" H 7850 2350 60 0000 C CNN + 4 7850 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68238DF5 +P 7900 3450 +F 0 "U1" H 7950 3550 30 0000 C CNN +F 1 "PORT" H 7900 3450 30 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 5 7900 3450 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sub new file mode 100644 index 00000000..2d292618 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sub @@ -0,0 +1,30 @@ +* Subcircuit jkff +.subckt jkff net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\jkff\jkff.cir +* u2 net-_u1-pad5_ net-_u1-pad1_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad2_ net-_u5-pad3_ d_nand +* u6 net-_u4-pad3_ net-_u1-pad5_ net-_u1-pad4_ d_nand +* u7 net-_u1-pad4_ net-_u5-pad3_ net-_u1-pad5_ d_nand +a1 [net-_u1-pad5_ net-_u1-pad1_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u1-pad5_ ] net-_u1-pad4_ u6 +a6 [net-_u1-pad4_ net-_u5-pad3_ ] net-_u1-pad5_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends jkff
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff_Previous_Values.xml new file mode 100644 index 00000000..2493eac7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-cache.lib new file mode 100644 index 00000000..d4d3e35d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# internal72 +# +DEF internal72 x 0 40 Y Y 1 F N +F0 "x" 0 -150 60 H V C CNN +F1 "internal72" 0 650 60 H V C CNN +F2 "" 0 -150 60 H I C CNN +F3 "" 0 -150 60 H I C CNN +DRAW +S 200 550 -250 -100 0 1 0 N +X j 1 -450 500 200 R 50 50 1 1 I +X clk 2 -450 400 200 R 50 50 1 1 I +X k 3 -450 300 200 R 50 50 1 1 I +X vcc 4 -450 0 200 R 50 50 1 1 I +X gnd 5 400 450 200 L 50 50 1 1 O +X pre 6 -450 200 200 R 50 50 1 1 I +X clr 7 -450 100 200 R 50 50 1 1 I +X Q 8 400 350 200 L 50 50 1 1 O +X Qnot 9 400 250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-rescue.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-rescue.lib new file mode 100644 index 00000000..00ebd155 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-rescue.lib @@ -0,0 +1,25 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# internal72-RESCUE-72 +# +DEF internal72-RESCUE-72 x 0 40 Y Y 1 F N +F0 "x" 0 -150 60 H V C CNN +F1 "internal72-RESCUE-72" 0 650 60 H V C CNN +F2 "" 0 -150 60 H I C CNN +F3 "" 0 -150 60 H I C CNN +DRAW +S 200 550 -250 -100 0 1 0 N +X j 1 -450 500 200 R 50 50 1 1 I +X k 2 -450 300 200 R 50 50 1 1 I +X clk 3 -450 400 200 R 50 50 1 1 I +X pre 4 -450 200 200 R 50 50 1 1 I +X gnd 5 400 450 200 L 50 50 1 1 O +X vcc 6 -450 0 200 R 50 50 1 1 I +X clr 7 -450 100 200 R 50 50 1 1 I +X Q 8 400 350 200 L 50 50 1 1 O +X Qnot 9 400 250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir new file mode 100644 index 00000000..cbc2fbb8 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir @@ -0,0 +1,24 @@ +* C:\Users\Shanthipriya\eSim-Workspace\72\72.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 09:48:04 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Qnot plot_v1 +U7 Q plot_v1 +U3 k plot_v1 +U1 j plot_v1 +U2 clk plot_v1 +v3 k GND pulse +v2 clk GND pulse +v1 j GND pulse +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Q Qnot dac_bridge_2 +U5 j clk k Net-_U5-Pad4_ Net-_U5-Pad5_ Net-_U5-Pad6_ adc_bridge_3 +x1 Net-_U5-Pad4_ Net-_U5-Pad5_ Net-_U5-Pad6_ ? ? Net-_U4-Pad3_ Net-_U4-Pad4_ Net-_U6-Pad1_ Net-_U6-Pad2_ internal72 +v4 pre GND DC +U4 pre clr Net-_U4-Pad3_ Net-_U4-Pad4_ adc_bridge_2 +v5 clr GND DC + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir.out new file mode 100644 index 00000000..f43756bd --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir.out @@ -0,0 +1,36 @@ +* c:\users\shanthipriya\esim-workspace\72\72.cir + +.include internal72.sub +* u8 qnot plot_v1 +* u7 q plot_v1 +* u3 k plot_v1 +* u1 j plot_v1 +* u2 clk plot_v1 +v3 k gnd pulse(5 0 0.3u 1n 1n 1u 2.1u) +v2 clk gnd pulse(0 5 0.1u 1n 1n 20n 45n) +v1 j gnd pulse(0 5 0.5u 1n 1n 1u 2.1u) +* u6 net-_u6-pad1_ net-_u6-pad2_ q qnot dac_bridge_2 +* u5 j clk k net-_u5-pad4_ net-_u5-pad5_ net-_u5-pad6_ adc_bridge_3 +x1 net-_u5-pad4_ net-_u5-pad5_ net-_u5-pad6_ ? ? net-_u4-pad3_ net-_u4-pad4_ net-_u6-pad1_ net-_u6-pad2_ internal72 +v4 pre gnd dc 0 +* u4 pre clr net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2 +v5 clr gnd dc 0 +a1 [net-_u6-pad1_ net-_u6-pad2_ ] [q qnot ] u6 +a2 [j clk k ] [net-_u5-pad4_ net-_u5-pad5_ net-_u5-pad6_ ] u5 +a3 [pre clr ] [net-_u4-pad3_ net-_u4-pad4_ ] u4 +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 1e-09 5e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(qnot)+6 v(q)+12 v(k)+18 v(j)+24 v(clk) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.pro new file mode 100644 index 00000000..ae6dd82f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.pro @@ -0,0 +1,74 @@ +update=05/23/25 21:51:07 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=72-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=eSim_Plot +LibName24=transistors +LibName25=conn +LibName26=eSim_User +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_Nghdl +LibName39=eSim_Ngveri +LibName40=eSim_SKY130 +LibName41=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.proj b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.proj new file mode 100644 index 00000000..a16f094e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.proj @@ -0,0 +1 @@ +schematicFile 72.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.sch new file mode 100644 index 00000000..658788a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.sch @@ -0,0 +1,375 @@ +EESchema Schematic File Version 2 +LIBS:72-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:72-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 8450 3250 +Wire Wire Line + 8450 2850 8450 3250 +Wire Wire Line + 8350 2850 8450 2850 +Text GLabel 8350 2850 0 60 Input ~ 0 +Qnot +Connection ~ 7850 3150 +Wire Wire Line + 7850 2800 7850 3150 +Wire Wire Line + 7550 2800 7850 2800 +Text GLabel 7550 2800 0 60 Input ~ 0 +Q +Connection ~ 2250 2750 +Wire Wire Line + 1850 2750 2250 2750 +Text GLabel 1850 2750 0 60 Input ~ 0 +k +Connection ~ 1050 2550 +Wire Wire Line + 650 2550 1050 2550 +Text GLabel 650 2550 0 60 Input ~ 0 +j +Connection ~ 1600 2600 +Wire Wire Line + 1300 2600 1600 2600 +Text GLabel 1300 2600 0 60 Input ~ 0 +clk +Wire Wire Line + 8650 3250 7400 3250 +Wire Wire Line + 8650 2700 8650 3250 +Wire Wire Line + 8000 3150 7400 3150 +Wire Wire Line + 8000 2700 8000 3150 +Connection ~ 2250 3200 +Wire Wire Line + 2250 2250 2250 3200 +Connection ~ 1600 3100 +Wire Wire Line + 1050 2200 1050 3000 +Connection ~ 1050 3000 +Wire Wire Line + 1600 2400 1600 3100 +$Comp +L plot_v1 U8 +U 1 1 6830214F +P 8650 2900 +F 0 "U8" H 8650 3400 60 0000 C CNN +F 1 "plot_v1" H 8850 3250 60 0000 C CNN +F 2 "" H 8650 2900 60 0000 C CNN +F 3 "" H 8650 2900 60 0000 C CNN + 1 8650 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 6830214E +P 8000 2900 +F 0 "U7" H 8000 3400 60 0000 C CNN +F 1 "plot_v1" H 8200 3250 60 0000 C CNN +F 2 "" H 8000 2900 60 0000 C CNN +F 3 "" H 8000 2900 60 0000 C CNN + 1 8000 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 6830214D +P 2250 2450 +F 0 "U3" H 2250 2950 60 0000 C CNN +F 1 "plot_v1" H 2450 2800 60 0000 C CNN +F 2 "" H 2250 2450 60 0000 C CNN +F 3 "" H 2250 2450 60 0000 C CNN + 1 2250 2450 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 6830214C +P 1050 2400 +F 0 "U1" H 1050 2900 60 0000 C CNN +F 1 "plot_v1" H 1250 2750 60 0000 C CNN +F 2 "" H 1050 2400 60 0000 C CNN +F 3 "" H 1050 2400 60 0000 C CNN + 1 1050 2400 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 6830214B +P 1600 2600 +F 0 "U2" H 1600 3100 60 0000 C CNN +F 1 "plot_v1" H 1800 2950 60 0000 C CNN +F 2 "" H 1600 2600 60 0000 C CNN +F 3 "" H 1600 2600 60 0000 C CNN + 1 1600 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 3200 3400 3200 +Wire Wire Line + 1750 3750 1750 3200 +Wire Wire Line + 1300 3100 3400 3100 +Wire Wire Line + 1300 3450 1300 3100 +Wire Wire Line + 850 3000 3400 3000 +Wire Wire Line + 850 3100 850 3000 +Wire Wire Line + 1750 4650 1750 4850 +$Comp +L GND #PWR01 +U 1 1 6830214A +P 1750 4850 +F 0 "#PWR01" H 1750 4600 50 0001 C CNN +F 1 "GND" H 1750 4700 50 0000 C CNN +F 2 "" H 1750 4850 50 0001 C CNN +F 3 "" H 1750 4850 50 0001 C CNN + 1 1750 4850 + 1 0 0 -1 +$EndComp +$Comp +L pulse v3 +U 1 1 68302149 +P 1750 4200 +F 0 "v3" H 1550 4300 60 0000 C CNN +F 1 "pulse" H 1550 4150 60 0000 C CNN +F 2 "R1" H 1450 4200 60 0000 C CNN +F 3 "" H 1750 4200 60 0000 C CNN + 1 1750 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 4350 1300 4550 +$Comp +L GND #PWR02 +U 1 1 68302148 +P 1300 4550 +F 0 "#PWR02" H 1300 4300 50 0001 C CNN +F 1 "GND" H 1300 4400 50 0000 C CNN +F 2 "" H 1300 4550 50 0001 C CNN +F 3 "" H 1300 4550 50 0001 C CNN + 1 1300 4550 + 1 0 0 -1 +$EndComp +$Comp +L pulse v2 +U 1 1 68302147 +P 1300 3900 +F 0 "v2" H 1100 4000 60 0000 C CNN +F 1 "pulse" H 1100 3850 60 0000 C CNN +F 2 "R1" H 1000 3900 60 0000 C CNN +F 3 "" H 1300 3900 60 0000 C CNN + 1 1300 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 850 4000 850 4200 +$Comp +L GND #PWR03 +U 1 1 68302146 +P 850 4200 +F 0 "#PWR03" H 850 3950 50 0001 C CNN +F 1 "GND" H 850 4050 50 0000 C CNN +F 2 "" H 850 4200 50 0001 C CNN +F 3 "" H 850 4200 50 0001 C CNN + 1 850 4200 + 1 0 0 -1 +$EndComp +$Comp +L pulse v1 +U 1 1 68302145 +P 850 3550 +F 0 "v1" H 650 3650 60 0000 C CNN +F 1 "pulse" H 650 3500 60 0000 C CNN +F 2 "R1" H 550 3550 60 0000 C CNN +F 3 "" H 850 3550 60 0000 C CNN + 1 850 3550 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U6 +U 1 1 68302144 +P 6850 3200 +F 0 "U6" H 6850 3200 60 0000 C CNN +F 1 "dac_bridge_2" H 6900 3350 60 0000 C CNN +F 2 "" H 6850 3200 60 0000 C CNN +F 3 "" H 6850 3200 60 0000 C CNN + 1 6850 3200 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U5 +U 1 1 68302143 +P 4000 3050 +F 0 "U5" H 4000 3050 60 0000 C CNN +F 1 "adc_bridge_3" H 4000 3200 60 0000 C CNN +F 2 "" H 4000 3050 60 0000 C CNN +F 3 "" H 4000 3050 60 0000 C CNN + 1 4000 3050 + 1 0 0 -1 +$EndComp +$Comp +L internal72 x1 +U 1 1 6831481A +P 5450 3500 +F 0 "x1" H 5450 3350 60 0000 C CNN +F 1 "internal72" H 5450 4150 60 0000 C CNN +F 2 "" H 5450 3350 60 0001 C CNN +F 3 "" H 5450 3350 60 0001 C CNN + 1 5450 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3000 4550 3000 +Wire Wire Line + 5000 3100 4550 3100 +Wire Wire Line + 5000 3200 4550 3200 +Wire Wire Line + 6400 3150 5850 3150 +Wire Wire Line + 6400 3250 5850 3250 +$Comp +L DC v4 +U 1 1 68314951 +P 2400 4950 +F 0 "v4" H 2200 5050 60 0000 C CNN +F 1 "DC" H 2200 4900 60 0000 C CNN +F 2 "R1" H 2100 4950 60 0000 C CNN +F 3 "" H 2400 4950 60 0000 C CNN + 1 2400 4950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 68314998 +P 2400 5750 +F 0 "#PWR04" H 2400 5500 50 0001 C CNN +F 1 "GND" H 2400 5600 50 0000 C CNN +F 2 "" H 2400 5750 50 0001 C CNN +F 3 "" H 2400 5750 50 0001 C CNN + 1 2400 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2400 5750 2400 5400 +$Comp +L adc_bridge_2 U4 +U 1 1 683149F6 +P 3450 3750 +F 0 "U4" H 3450 3750 60 0000 C CNN +F 1 "adc_bridge_2" H 3450 3900 60 0000 C CNN +F 2 "" H 3450 3750 60 0000 C CNN +F 3 "" H 3450 3750 60 0000 C CNN + 1 3450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 3700 2400 3700 +Wire Wire Line + 2400 3700 2400 4500 +$Comp +L DC v5 +U 1 1 68314ACB +P 3000 4950 +F 0 "v5" H 2800 5050 60 0000 C CNN +F 1 "DC" H 2800 4900 60 0000 C CNN +F 2 "R1" H 2700 4950 60 0000 C CNN +F 3 "" H 3000 4950 60 0000 C CNN + 1 3000 4950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 68314AD1 +P 3000 5950 +F 0 "#PWR05" H 3000 5700 50 0001 C CNN +F 1 "GND" H 3000 5800 50 0000 C CNN +F 2 "" H 3000 5950 50 0001 C CNN +F 3 "" H 3000 5950 50 0001 C CNN + 1 3000 5950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 5400 3000 5950 +Wire Wire Line + 3000 4500 2850 4500 +Wire Wire Line + 2850 4500 2850 3800 +Wire Wire Line + 4000 3700 4250 3700 +Wire Wire Line + 4250 3700 4250 3300 +Wire Wire Line + 4250 3300 5000 3300 +Wire Wire Line + 4000 3800 4300 3800 +Wire Wire Line + 4300 3800 4300 3400 +Wire Wire Line + 4300 3400 5000 3400 +Text GLabel 2050 3800 0 60 Input ~ 0 +pre +Wire Wire Line + 2050 3800 2400 3800 +Connection ~ 2400 3800 +Text GLabel 3450 4250 2 60 Input ~ 0 +clr +Wire Wire Line + 3450 4250 2850 4250 +Connection ~ 2850 4250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72_Previous_Values.xml new file mode 100644 index 00000000..d2f9a188 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0.5u</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">1u</field5><field5 name="Period">2.1u</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0.1u</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">20n</field5><field5 name="Period">45n</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">5</field1><field2 name="Pulse Value">0</field2><field3 name="Delay Time">0.3u</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">1u</field5><field5 name="Period">2.1u</field5></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v5 name="Source type">dc<field1 name="Value">0</field1></v5></source><model><u5 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u5><u6 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u6><u4 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u4><u4 name="type">d_inverter<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_jkff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for JK Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\internal72</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">5</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ns</field5><field6 name="Stop Combo">us</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90-cache.lib new file mode 100644 index 00000000..268e1bb1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90-cache.lib @@ -0,0 +1,99 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_jkff +# +DEF d_jkff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_jkff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X J 1 -800 400 200 R 50 50 1 1 I +X K 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir new file mode 100644 index 00000000..78ecb37d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir @@ -0,0 +1,21 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls90\74ls90.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/15/25 15:54:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 /JK /JK /CLK /R01 /R91 /QA ? d_jkff +U4 Net-_U3-Pad3_ Net-_U3-Pad3_ /CLK /R01 /R91 /QB ? d_jkff +U8 Net-_U5-Pad3_ Net-_U5-Pad3_ /CLK /R01 /R91 /QC ? d_jkff +U11 Net-_U10-Pad3_ Net-_U10-Pad3_ /CLK /R01 /R91 /QD Net-_U11-Pad7_ d_jkff +U3 Net-_U11-Pad7_ /QA Net-_U3-Pad3_ d_and +U5 /QA /QB Net-_U5-Pad3_ d_and +U7 /QA /QD Net-_U10-Pad2_ d_and +U6 /QA /QB Net-_U6-Pad3_ d_and +U9 Net-_U6-Pad3_ /QC Net-_U10-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U1 /R91 /CLK /R01 /JK ? ? ? ? /QA /QB /QC /QD PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir.out new file mode 100644 index 00000000..b942ea4d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir.out @@ -0,0 +1,52 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls90\74ls90.cir + +* u2 /jk /jk /clk /r01 /r91 /qa ? d_jkff +* u4 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? d_jkff +* u8 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? d_jkff +* u11 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ d_jkff +* u3 net-_u11-pad7_ /qa net-_u3-pad3_ d_and +* u5 /qa /qb net-_u5-pad3_ d_and +* u7 /qa /qd net-_u10-pad2_ d_and +* u6 /qa /qb net-_u6-pad3_ d_and +* u9 net-_u6-pad3_ /qc net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u1 /r91 /clk /r01 /jk ? ? ? ? /qa /qb /qc /qd port +a1 /jk /jk /clk /r01 /r91 /qa ? u2 +a2 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? u4 +a3 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? u8 +a4 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ u11 +a5 [net-_u11-pad7_ /qa ] net-_u3-pad3_ u3 +a6 [/qa /qb ] net-_u5-pad3_ u5 +a7 [/qa /qd ] net-_u10-pad2_ u7 +a8 [/qa /qb ] net-_u6-pad3_ u6 +a9 [net-_u6-pad3_ /qc ] net-_u10-pad1_ u9 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u4 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u8 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u11 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sch new file mode 100644 index 00000000..b8a1d6e2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sch @@ -0,0 +1,494 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_jkff U2 +U 1 1 6825B2FF +P 2800 3400 +F 0 "U2" H 2800 3400 60 0000 C CNN +F 1 "d_jkff" H 2850 3550 60 0000 C CNN +F 2 "" H 2800 3400 60 0000 C CNN +F 3 "" H 2800 3400 60 0000 C CNN + 1 2800 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U4 +U 1 1 6825B328 +P 5000 3400 +F 0 "U4" H 5000 3400 60 0000 C CNN +F 1 "d_jkff" H 5050 3550 60 0000 C CNN +F 2 "" H 5000 3400 60 0000 C CNN +F 3 "" H 5000 3400 60 0000 C CNN + 1 5000 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U8 +U 1 1 6825B407 +P 7250 3400 +F 0 "U8" H 7250 3400 60 0000 C CNN +F 1 "d_jkff" H 7300 3550 60 0000 C CNN +F 2 "" H 7250 3400 60 0000 C CNN +F 3 "" H 7250 3400 60 0000 C CNN + 1 7250 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U11 +U 1 1 6825B40D +P 9450 3400 +F 0 "U11" H 9450 3400 60 0000 C CNN +F 1 "d_jkff" H 9500 3550 60 0000 C CNN +F 2 "" H 9450 3400 60 0000 C CNN +F 3 "" H 9450 3400 60 0000 C CNN + 1 9450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 2650 9450 2650 +Connection ~ 5000 2650 +Connection ~ 7250 2650 +Wire Wire Line + 2800 4200 9450 4200 +Connection ~ 7250 4200 +Connection ~ 5000 4200 +Wire Wire Line + 3550 800 3550 2650 +Wire Wire Line + 1850 800 3550 800 +Connection ~ 3550 2650 +Wire Wire Line + 2000 3850 1850 3850 +Wire Wire Line + 1850 3850 1850 1100 +Wire Wire Line + 2000 3000 1850 3000 +Connection ~ 1850 3000 +Wire Wire Line + 2000 3400 1750 3400 +Wire Wire Line + 1750 1400 1750 4600 +Wire Wire Line + 1750 4600 8350 4600 +Wire Wire Line + 3950 4600 3950 3400 +Wire Wire Line + 3950 3400 4200 3400 +Connection ~ 1750 3400 +Wire Wire Line + 6150 4600 6150 3400 +Wire Wire Line + 6150 3400 6450 3400 +Connection ~ 3950 4600 +Wire Wire Line + 8350 4600 8350 3400 +Wire Wire Line + 8350 3400 8650 3400 +Connection ~ 6150 4600 +$Comp +L d_and U3 +U 1 1 6825B512 +P 4200 1600 +F 0 "U3" H 4200 1600 60 0000 C CNN +F 1 "d_and" H 4250 1700 60 0000 C CNN +F 2 "" H 4200 1600 60 0000 C CNN +F 3 "" H 4200 1600 60 0000 C CNN + 1 4200 1600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 1600 3750 5850 +Wire Wire Line + 3750 3000 3600 3000 +Connection ~ 3750 3000 +NoConn ~ 3600 3850 +NoConn ~ 5800 3850 +NoConn ~ 8050 3850 +Wire Wire Line + 4200 3000 4200 2000 +Wire Wire Line + 4200 2000 4650 2000 +Wire Wire Line + 4650 2000 4650 1550 +Wire Wire Line + 4200 3850 4050 3850 +Wire Wire Line + 4050 3850 4050 2950 +Wire Wire Line + 4050 2950 4200 2950 +Connection ~ 4200 2950 +$Comp +L d_and U5 +U 1 1 6825B774 +P 6150 1700 +F 0 "U5" H 6150 1700 60 0000 C CNN +F 1 "d_and" H 6200 1800 60 0000 C CNN +F 2 "" H 6150 1700 60 0000 C CNN +F 3 "" H 6150 1700 60 0000 C CNN + 1 6150 1700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 6825B7B9 +P 6600 1400 +F 0 "U7" H 6600 1400 60 0000 C CNN +F 1 "d_and" H 6650 1500 60 0000 C CNN +F 2 "" H 6600 1400 60 0000 C CNN +F 3 "" H 6600 1400 60 0000 C CNN + 1 6600 1400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 6825B80C +P 6450 650 +F 0 "U6" H 6450 650 60 0000 C CNN +F 1 "d_and" H 6500 750 60 0000 C CNN +F 2 "" H 6450 650 60 0000 C CNN +F 3 "" H 6450 650 60 0000 C CNN + 1 6450 650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 6825B87D +P 7750 700 +F 0 "U9" H 7750 700 60 0000 C CNN +F 1 "d_and" H 7800 800 60 0000 C CNN +F 2 "" H 7750 700 60 0000 C CNN +F 3 "" H 7750 700 60 0000 C CNN + 1 7750 700 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 6825B8B4 +P 8300 1050 +F 0 "U10" H 8300 1050 60 0000 C CNN +F 1 "d_or" H 8300 1150 60 0000 C CNN +F 2 "" H 8300 1050 60 0000 C CNN +F 3 "" H 8300 1050 60 0000 C CNN + 1 8300 1050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 1700 5700 2850 +Wire Wire Line + 5700 2850 5800 2850 +Wire Wire Line + 5800 2850 5800 5850 +Connection ~ 5800 3000 +Wire Wire Line + 5700 1600 4850 1600 +Wire Wire Line + 4850 550 4850 1800 +Wire Wire Line + 4850 1800 3750 1800 +Connection ~ 3750 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Wire Line + 8250 1500 8250 5850 +Wire Wire Line + 8250 1500 7300 1500 +Wire Wire Line + 7300 1500 7300 700 +Connection ~ 8250 3000 +Wire Wire Line + 7300 600 6900 600 +Wire Wire Line + 6600 1650 6600 2550 +Wire Wire Line + 6600 2550 6250 2550 +Wire Wire Line + 6250 2550 6250 3850 +Wire Wire Line + 6250 3850 6450 3850 +Wire Wire Line + 6450 3000 6250 3000 +Connection ~ 6250 3000 +Wire Wire Line + 6150 1300 5850 1300 +Wire Wire Line + 5850 1300 5850 550 +Connection ~ 5850 550 +Wire Wire Line + 3750 1500 3750 1150 +Wire Wire Line + 3750 1150 10850 1150 +Wire Wire Line + 10850 1150 10850 3850 +Wire Wire Line + 10850 3850 10250 3850 +Wire Wire Line + 3300 4200 3300 4300 +Wire Wire Line + 3300 4300 1650 4300 +Wire Wire Line + 1650 4300 1650 1750 +Connection ~ 3300 4200 +$Comp +L PORT U1 +U 3 1 6825C341 +P 1600 800 +F 0 "U1" H 1650 900 30 0000 C CNN +F 1 "PORT" H 1600 800 30 0000 C CNN +F 2 "" H 1600 800 60 0000 C CNN +F 3 "" H 1600 800 60 0000 C CNN + 3 1600 800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6825C3B9 +P 1600 1100 +F 0 "U1" H 1650 1200 30 0000 C CNN +F 1 "PORT" H 1600 1100 30 0000 C CNN +F 2 "" H 1600 1100 60 0000 C CNN +F 3 "" H 1600 1100 60 0000 C CNN + 4 1600 1100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6825C422 +P 1500 1400 +F 0 "U1" H 1550 1500 30 0000 C CNN +F 1 "PORT" H 1500 1400 30 0000 C CNN +F 2 "" H 1500 1400 60 0000 C CNN +F 3 "" H 1500 1400 60 0000 C CNN + 2 1500 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6825C479 +P 1400 1750 +F 0 "U1" H 1450 1850 30 0000 C CNN +F 1 "PORT" H 1400 1750 30 0000 C CNN +F 2 "" H 1400 1750 60 0000 C CNN +F 3 "" H 1400 1750 60 0000 C CNN + 1 1400 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6825C4DE +P 3500 5850 +F 0 "U1" H 3550 5950 30 0000 C CNN +F 1 "PORT" H 3500 5850 30 0000 C CNN +F 2 "" H 3500 5850 60 0000 C CNN +F 3 "" H 3500 5850 60 0000 C CNN + 9 3500 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6825C543 +P 5550 5850 +F 0 "U1" H 5600 5950 30 0000 C CNN +F 1 "PORT" H 5550 5850 30 0000 C CNN +F 2 "" H 5550 5850 60 0000 C CNN +F 3 "" H 5550 5850 60 0000 C CNN + 10 5550 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6825C5B8 +P 8000 5850 +F 0 "U1" H 8050 5950 30 0000 C CNN +F 1 "PORT" H 8000 5850 30 0000 C CNN +F 2 "" H 8000 5850 60 0000 C CNN +F 3 "" H 8000 5850 60 0000 C CNN + 11 8000 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6825C637 +P 10200 5850 +F 0 "U1" H 10250 5950 30 0000 C CNN +F 1 "PORT" H 10200 5850 30 0000 C CNN +F 2 "" H 10200 5850 60 0000 C CNN +F 3 "" H 10200 5850 60 0000 C CNN + 12 10200 5850 + 1 0 0 -1 +$EndComp +Text Label 2650 800 0 60 ~ 0 +R01 +$Comp +L PORT U1 +U 5 1 6825C6D3 +P 1750 5100 +F 0 "U1" H 1800 5200 30 0000 C CNN +F 1 "PORT" H 1750 5100 30 0000 C CNN +F 2 "" H 1750 5100 60 0000 C CNN +F 3 "" H 1750 5100 60 0000 C CNN + 5 1750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 5100 2600 5100 +NoConn ~ 2600 5100 +Text Label 2250 5100 0 60 ~ 0 +R02 +Text Label 1850 1200 0 60 ~ 0 +JK +Text Label 1750 1600 0 60 ~ 0 +CLK +Text Label 1650 2200 0 60 ~ 0 +R91 +$Comp +L PORT U1 +U 6 1 6825C88D +P 1750 5450 +F 0 "U1" H 1800 5550 30 0000 C CNN +F 1 "PORT" H 1750 5450 30 0000 C CNN +F 2 "" H 1750 5450 60 0000 C CNN +F 3 "" H 1750 5450 60 0000 C CNN + 6 1750 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 5450 2600 5450 +NoConn ~ 2600 5450 +Text Label 2300 5450 0 60 ~ 0 +R92 +Text Label 3750 5050 0 60 ~ 0 +QA +Text Label 5800 4950 0 60 ~ 0 +QB +Text Label 8250 4900 0 60 ~ 0 +QC +Text Label 10450 4800 0 60 ~ 0 +QD +$Comp +L PORT U1 +U 7 1 6825CE65 +P 1750 5800 +F 0 "U1" H 1800 5900 30 0000 C CNN +F 1 "PORT" H 1750 5800 30 0000 C CNN +F 2 "" H 1750 5800 60 0000 C CNN +F 3 "" H 1750 5800 60 0000 C CNN + 7 1750 5800 + 1 0 0 -1 +$EndComp +NoConn ~ 2000 5800 +$Comp +L PORT U1 +U 8 1 6825CEDB +P 1750 6000 +F 0 "U1" H 1800 6100 30 0000 C CNN +F 1 "PORT" H 1750 6000 30 0000 C CNN +F 2 "" H 1750 6000 60 0000 C CNN +F 3 "" H 1750 6000 60 0000 C CNN + 8 1750 6000 + 1 0 0 -1 +$EndComp +NoConn ~ 2000 6000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sub new file mode 100644 index 00000000..1830a145 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sub @@ -0,0 +1,46 @@ +* Subcircuit 74ls90 +.subckt 74ls90 /r91 /clk /r01 /jk ? ? ? ? /qa /qb /qc /qd +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls90\74ls90.cir +* u2 /jk /jk /clk /r01 /r91 /qa ? d_jkff +* u4 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? d_jkff +* u8 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? d_jkff +* u11 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ d_jkff +* u3 net-_u11-pad7_ /qa net-_u3-pad3_ d_and +* u5 /qa /qb net-_u5-pad3_ d_and +* u7 /qa /qd net-_u10-pad2_ d_and +* u6 /qa /qb net-_u6-pad3_ d_and +* u9 net-_u6-pad3_ /qc net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +a1 /jk /jk /clk /r01 /r91 /qa ? u2 +a2 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? u4 +a3 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? u8 +a4 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ u11 +a5 [net-_u11-pad7_ /qa ] net-_u3-pad3_ u3 +a6 [/qa /qb ] net-_u5-pad3_ u5 +a7 [/qa /qd ] net-_u10-pad2_ u7 +a8 [/qa /qb ] net-_u6-pad3_ u6 +a9 [net-_u6-pad3_ /qc ] net-_u10-pad1_ u9 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u4 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u8 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u11 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74ls90
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90_Previous_Values.xml new file mode 100644 index 00000000..05fccb1a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u4 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u4><u8 name="type">d_jkff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for JK Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u8><u11 name="type">d_jkff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for JK Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u11><u3 name="type">d_and<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_and<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_and<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_and<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_and<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_or<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u10></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/analysis new file mode 100644 index 00000000..af548eb1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/analysis @@ -0,0 +1 @@ +.tran 0.1e-06 100e-06 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90-cache.lib new file mode 100644 index 00000000..6ac291da --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 54LS90 +# +DEF 54LS90 X 0 40 Y Y 1 F N +F0 "X" -100 -550 60 H V C CNN +F1 "54LS90" 50 1100 60 H V C CNN +F2 "" 50 1100 60 H I C CNN +F3 "" 50 1100 60 H I C CNN +DRAW +S 300 1000 -400 -400 0 1 0 N +X R91 1 -600 100 200 R 50 50 1 1 I +X CLK 2 -600 300 200 R 50 50 1 1 I +X R01 3 -600 900 200 R 50 50 1 1 I +X JK 4 -600 500 200 R 50 50 1 1 I +X R02 5 -600 700 200 R 50 50 1 1 I +X R92 6 -600 -100 200 R 50 50 1 1 I +X VCC 7 -600 -300 200 R 50 50 1 1 I +X GND 8 500 900 200 L 50 50 1 1 O +X QA 9 500 700 200 L 50 50 1 1 O +X QB 10 500 500 200 L 50 50 1 1 O +X QC 11 500 300 200 L 50 50 1 1 O +X QD 12 500 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir new file mode 100644 index 00000000..1374b669 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir @@ -0,0 +1,29 @@ +* C:\Users\Shanthipriya\eSim-Workspace\sn74ls90\sn74ls90.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/15/25 17:30:55 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U4-Pad2_ clock Net-_U3-Pad2_ Net-_U1-Pad2_ ? ? ? ? Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ 54LS90 +v3 Net-_U2-Pad1_ GND pulse +U2 Net-_U2-Pad1_ clock adc_bridge_1 +U5 clock plot_v1 +v1 Net-_U1-Pad1_ GND DC +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ adc_bridge_1 +v2 Net-_U3-Pad1_ GND DC +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ adc_bridge_1 +v4 Net-_U4-Pad1_ GND DC +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ adc_bridge_1 +U6 QA plot_v1 +U7 QB plot_v1 +U8 QC plot_v1 +U9 QD plot_v1 +R4 QD GND 10K +R3 QC GND 10K +R2 QB GND 10K +R1 QA GND 10K +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ QA QB QC QD dac_bridge_4 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir.out new file mode 100644 index 00000000..61732f8b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir.out @@ -0,0 +1,47 @@ +* c:\users\shanthipriya\esim-workspace\sn74ls90\sn74ls90.cir + +.include 74ls90.sub +x1 net-_u4-pad2_ clock net-_u3-pad2_ net-_u1-pad2_ ? ? ? ? net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ 74ls90 +v3 net-_u2-pad1_ gnd pulse(0 5 0 1n 1n 5u 10u) +* u2 net-_u2-pad1_ clock adc_bridge_1 +* u5 clock plot_v1 +v1 net-_u1-pad1_ gnd dc 5 +* u1 net-_u1-pad1_ net-_u1-pad2_ adc_bridge_1 +v2 net-_u3-pad1_ gnd dc 1 +* u3 net-_u3-pad1_ net-_u3-pad2_ adc_bridge_1 +v4 net-_u4-pad1_ gnd dc 1 +* u4 net-_u4-pad1_ net-_u4-pad2_ adc_bridge_1 +* u6 qa plot_v1 +* u7 qb plot_v1 +* u8 qc plot_v1 +* u9 qd plot_v1 +r4 qd gnd 10k +r3 qc gnd 10k +r2 qb gnd 10k +r1 qa gnd 10k +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ qa qb qc qd dac_bridge_4 +a1 [net-_u2-pad1_ ] [clock ] u2 +a2 [net-_u1-pad1_ ] [net-_u1-pad2_ ] u1 +a3 [net-_u3-pad1_ ] [net-_u3-pad2_ ] u3 +a4 [net-_u4-pad1_ ] [net-_u4-pad2_ ] u4 +a5 [net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ ] [qa qb qc qd ] u10 +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0.1e-06 100e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(qd)+6 v(qc)+12 v(qb)+18v(qa)+24 v(clock) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.proj b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.proj new file mode 100644 index 00000000..015ebc9c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.proj @@ -0,0 +1 @@ +schematicFile sn74ls90.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.sch new file mode 100644 index 00000000..3cd9bdbf --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.sch @@ -0,0 +1,440 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 54LS90 X1 +U 1 1 6825C471 +P 5500 3450 +F 0 "X1" H 5400 2900 60 0000 C CNN +F 1 "54LS90" H 5550 4550 60 0000 C CNN +F 2 "" H 5550 4550 60 0001 C CNN +F 3 "" H 5550 4550 60 0001 C CNN + 1 5500 3450 + 1 0 0 -1 +$EndComp +$Comp +L pulse v3 +U 1 1 6825C505 +P 1050 3450 +F 0 "v3" H 850 3550 60 0000 C CNN +F 1 "pulse" H 850 3400 60 0000 C CNN +F 2 "R1" H 750 3450 60 0000 C CNN +F 3 "" H 1050 3450 60 0000 C CNN + 1 1050 3450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 6825C540 +P 1050 4200 +F 0 "#PWR01" H 1050 3950 50 0001 C CNN +F 1 "GND" H 1050 4050 50 0000 C CNN +F 2 "" H 1050 4200 50 0001 C CNN +F 3 "" H 1050 4200 50 0001 C CNN + 1 1050 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 4200 1050 3900 +$Comp +L adc_bridge_1 U2 +U 1 1 6825C55C +P 1950 3050 +F 0 "U2" H 1950 3050 60 0000 C CNN +F 1 "adc_bridge_1" H 1950 3200 60 0000 C CNN +F 2 "" H 1950 3050 60 0000 C CNN +F 3 "" H 1950 3050 60 0000 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 3000 1050 3000 +Wire Wire Line + 2500 3000 2850 3000 +Wire Wire Line + 2850 3000 2850 3150 +Wire Wire Line + 2850 3150 4900 3150 +$Comp +L plot_v1 U5 +U 1 1 6825C5C6 +P 2850 3200 +F 0 "U5" H 2850 3700 60 0000 C CNN +F 1 "plot_v1" H 3050 3550 60 0000 C CNN +F 2 "" H 2850 3200 60 0000 C CNN +F 3 "" H 2850 3200 60 0000 C CNN + 1 2850 3200 + 1 0 0 -1 +$EndComp +Text GLabel 2500 2750 0 60 Input ~ 0 +clock +Wire Wire Line + 2500 2750 2600 2750 +Wire Wire Line + 2600 2750 2600 3000 +Connection ~ 2600 3000 +$Comp +L DC v1 +U 1 1 6825C612 +P 900 2350 +F 0 "v1" H 700 2450 60 0000 C CNN +F 1 "DC" H 700 2300 60 0000 C CNN +F 2 "R1" H 600 2350 60 0000 C CNN +F 3 "" H 900 2350 60 0000 C CNN + 1 900 2350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 6825C703 +P 900 3000 +F 0 "#PWR02" H 900 2750 50 0001 C CNN +F 1 "GND" H 900 2850 50 0000 C CNN +F 2 "" H 900 3000 50 0001 C CNN +F 3 "" H 900 3000 50 0001 C CNN + 1 900 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 900 3000 900 2800 +Wire Wire Line + 3300 2950 4900 2950 +$Comp +L adc_bridge_1 U1 +U 1 1 6825CB17 +P 1900 1950 +F 0 "U1" H 1900 1950 60 0000 C CNN +F 1 "adc_bridge_1" H 1900 2100 60 0000 C CNN +F 2 "" H 1900 1950 60 0000 C CNN +F 3 "" H 1900 1950 60 0000 C CNN + 1 1900 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2450 1900 3300 1900 +Wire Wire Line + 3300 1900 3300 2950 +Wire Wire Line + 1300 1900 900 1900 +$Comp +L DC v2 +U 1 1 6825CCA7 +P 1000 1150 +F 0 "v2" H 800 1250 60 0000 C CNN +F 1 "DC" H 800 1100 60 0000 C CNN +F 2 "R1" H 700 1150 60 0000 C CNN +F 3 "" H 1000 1150 60 0000 C CNN + 1 1000 1150 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U3 +U 1 1 6825CCAD +P 2000 750 +F 0 "U3" H 2000 750 60 0000 C CNN +F 1 "adc_bridge_1" H 2000 900 60 0000 C CNN +F 2 "" H 2000 750 60 0000 C CNN +F 3 "" H 2000 750 60 0000 C CNN + 1 2000 750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2550 700 3400 700 +Wire Wire Line + 1400 700 1000 700 +$Comp +L GND #PWR03 +U 1 1 6825CCD8 +P 1000 1600 +F 0 "#PWR03" H 1000 1350 50 0001 C CNN +F 1 "GND" H 1000 1450 50 0000 C CNN +F 2 "" H 1000 1600 50 0001 C CNN +F 3 "" H 1000 1600 50 0001 C CNN + 1 1000 1600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 700 3400 2550 +Wire Wire Line + 3400 2550 4900 2550 +$Comp +L DC v4 +U 1 1 6825CE12 +P 1550 4100 +F 0 "v4" H 1350 4200 60 0000 C CNN +F 1 "DC" H 1350 4050 60 0000 C CNN +F 2 "R1" H 1250 4100 60 0000 C CNN +F 3 "" H 1550 4100 60 0000 C CNN + 1 1550 4100 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U4 +U 1 1 6825CE18 +P 2550 3700 +F 0 "U4" H 2550 3700 60 0000 C CNN +F 1 "adc_bridge_1" H 2550 3850 60 0000 C CNN +F 2 "" H 2550 3700 60 0000 C CNN +F 3 "" H 2550 3700 60 0000 C CNN + 1 2550 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 3650 3950 3650 +Wire Wire Line + 1950 3650 1550 3650 +$Comp +L GND #PWR04 +U 1 1 6825CE20 +P 1550 4550 +F 0 "#PWR04" H 1550 4300 50 0001 C CNN +F 1 "GND" H 1550 4400 50 0000 C CNN +F 2 "" H 1550 4550 50 0001 C CNN +F 3 "" H 1550 4550 50 0001 C CNN + 1 1550 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3650 3950 3350 +Wire Wire Line + 3950 3350 4900 3350 +$Comp +L plot_v1 U6 +U 1 1 6825CE66 +P 8400 2900 +F 0 "U6" H 8400 3400 60 0000 C CNN +F 1 "plot_v1" H 8600 3250 60 0000 C CNN +F 2 "" H 8400 2900 60 0000 C CNN +F 3 "" H 8400 2900 60 0000 C CNN + 1 8400 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 6825CEA5 +P 8900 2900 +F 0 "U7" H 8900 3400 60 0000 C CNN +F 1 "plot_v1" H 9100 3250 60 0000 C CNN +F 2 "" H 8900 2900 60 0000 C CNN +F 3 "" H 8900 2900 60 0000 C CNN + 1 8900 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 6825CF44 +P 9350 2900 +F 0 "U8" H 9350 3400 60 0000 C CNN +F 1 "plot_v1" H 9550 3250 60 0000 C CNN +F 2 "" H 9350 2900 60 0000 C CNN +F 3 "" H 9350 2900 60 0000 C CNN + 1 9350 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 6825CF4A +P 9850 2900 +F 0 "U9" H 9850 3400 60 0000 C CNN +F 1 "plot_v1" H 10050 3250 60 0000 C CNN +F 2 "" H 9850 2900 60 0000 C CNN +F 3 "" H 9850 2900 60 0000 C CNN + 1 9850 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 2700 8400 2700 +Wire Wire Line + 8900 2700 8900 2900 +Wire Wire Line + 8900 2900 7750 2900 +Wire Wire Line + 9350 2700 9350 3100 +Wire Wire Line + 9350 3100 7750 3100 +Wire Wire Line + 7500 3300 9850 3300 +Wire Wire Line + 9850 3300 9850 2700 +Text GLabel 8050 3600 0 60 Input ~ 0 +QA +Wire Wire Line + 8050 3600 8050 2700 +Connection ~ 8050 2700 +Text GLabel 8250 3800 0 60 Input ~ 0 +QB +Wire Wire Line + 8250 3800 8250 2900 +Connection ~ 8250 2900 +Text GLabel 8500 4000 0 60 Input ~ 0 +QC +Text GLabel 8700 4200 0 60 Input ~ 0 +QD +Wire Wire Line + 8550 4000 8500 4000 +Wire Wire Line + 8550 3100 8550 4000 +Connection ~ 8550 3100 +Wire Wire Line + 8700 4200 8800 4200 +Wire Wire Line + 8800 4200 8800 3300 +Connection ~ 8800 3300 +$Comp +L resistor R4 +U 1 1 6825D1F5 +P 9950 3350 +F 0 "R4" H 10000 3480 50 0000 C CNN +F 1 "10K" H 10000 3300 50 0000 C CNN +F 2 "" H 10000 3330 30 0000 C CNN +F 3 "" V 10000 3400 30 0000 C CNN + 1 9950 3350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 6825D252 +P 9450 3150 +F 0 "R3" H 9500 3280 50 0000 C CNN +F 1 "10K" H 9500 3100 50 0000 C CNN +F 2 "" H 9500 3130 30 0000 C CNN +F 3 "" V 9500 3200 30 0000 C CNN + 1 9450 3150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 6825D2B5 +P 9000 2950 +F 0 "R2" H 9050 3080 50 0000 C CNN +F 1 "10K" H 9050 2900 50 0000 C CNN +F 2 "" H 9050 2930 30 0000 C CNN +F 3 "" V 9050 3000 30 0000 C CNN + 1 9000 2950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 6825D326 +P 8500 2750 +F 0 "R1" H 8550 2880 50 0000 C CNN +F 1 "10K" H 8550 2700 50 0000 C CNN +F 2 "" H 8550 2730 30 0000 C CNN +F 3 "" V 8550 2800 30 0000 C CNN + 1 8500 2750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 6825D38D +P 10900 3350 +F 0 "#PWR05" H 10900 3100 50 0001 C CNN +F 1 "GND" H 10900 3200 50 0000 C CNN +F 2 "" H 10900 3350 50 0001 C CNN +F 3 "" H 10900 3350 50 0001 C CNN + 1 10900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8700 2700 10900 2700 +Wire Wire Line + 10900 2700 10900 3350 +Wire Wire Line + 10150 3300 10900 3300 +Connection ~ 10900 3300 +Wire Wire Line + 9650 3100 10900 3100 +Connection ~ 10900 3100 +Wire Wire Line + 9200 2900 10900 2900 +Connection ~ 10900 2900 +$Comp +L dac_bridge_4 U10 +U 1 1 6825D8D1 +P 6950 3050 +F 0 "U10" H 6950 3050 60 0000 C CNN +F 1 "dac_bridge_4" H 6950 3350 60 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6400 2850 6400 2750 +Wire Wire Line + 6400 2750 6000 2750 +Wire Wire Line + 6400 2950 6000 2950 +Wire Wire Line + 6400 3050 6000 3050 +Wire Wire Line + 6000 3050 6000 3150 +Wire Wire Line + 6400 3150 6400 3350 +Wire Wire Line + 6400 3350 6000 3350 +Wire Wire Line + 7500 2850 7500 2700 +Wire Wire Line + 7500 2950 7750 2950 +Wire Wire Line + 7750 2950 7750 2900 +Wire Wire Line + 7500 3050 7750 3050 +Wire Wire Line + 7750 3050 7750 3100 +Wire Wire Line + 7500 3150 7500 3300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90_Previous_Values.xml new file mode 100644 index 00000000..36b30476 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">5u</field5><field5 name="Period">10u</field5></v3><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">1</field1></v2><v4 name="Source type">dc<field1 name="Value">1</field1></v4></source><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2><u1 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u1><u3 name="type">adc_bridge<field9 name="Enter value for in_low (default=1.0)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u4><u10 name="type">dac_bridge<field17 name="Enter value for out_low (default=0.0)" /><field18 name="Enter value for out_high (default=5.0)" /><field19 name="Enter value for out_undef (default=0.5)" /><field20 name="Enter value for input load (default=1.0e-12)" /><field21 name="Enter the Rise Time (default=1.0e-9)" /><field22 name="Enter the Fall Time (default=1.0e-9)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls90</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">us</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375-cache.lib new file mode 100644 index 00000000..ba413bed --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dlatch +# +DEF d_dlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dlatch" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X EN 2 -550 -300 200 R 50 50 1 1 I +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir new file mode 100644 index 00000000..6b47a2b0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir @@ -0,0 +1,15 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\375\375.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 23:29:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ ? ? Net-_U1-Pad3_ Net-_U1-Pad10_ d_dlatch +U3 Net-_U1-Pad4_ Net-_U1-Pad2_ ? ? Net-_U1-Pad5_ Net-_U1-Pad11_ d_dlatch +U4 Net-_U1-Pad6_ Net-_U1-Pad2_ ? ? Net-_U1-Pad7_ Net-_U1-Pad12_ d_dlatch +U5 Net-_U1-Pad8_ Net-_U1-Pad2_ ? ? Net-_U1-Pad9_ Net-_U1-Pad13_ d_dlatch +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir.out new file mode 100644 index 00000000..1b07f6fd --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir.out @@ -0,0 +1,28 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\375\375.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ d_dlatch +* u3 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ d_dlatch +* u4 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ d_dlatch +* u5 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ d_dlatch +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port +a1 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ u2 +a2 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ u3 +a3 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ u4 +a4 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ u5 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.pro b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sch b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sch new file mode 100644 index 00000000..2d5ef983 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sch @@ -0,0 +1,308 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:375-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dlatch U2 +U 1 1 6835F8D0 +P 3100 3000 +F 0 "U2" H 3100 3000 60 0000 C CNN +F 1 "d_dlatch" H 3100 3150 60 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 1 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U3 +U 1 1 6835F917 +P 4750 3000 +F 0 "U3" H 4750 3000 60 0000 C CNN +F 1 "d_dlatch" H 4750 3150 60 0000 C CNN +F 2 "" H 4750 3000 60 0000 C CNN +F 3 "" H 4750 3000 60 0000 C CNN + 1 4750 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U4 +U 1 1 6835F948 +P 6450 3000 +F 0 "U4" H 6450 3000 60 0000 C CNN +F 1 "d_dlatch" H 6450 3150 60 0000 C CNN +F 2 "" H 6450 3000 60 0000 C CNN +F 3 "" H 6450 3000 60 0000 C CNN + 1 6450 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U5 +U 1 1 6835F97D +P 8150 3000 +F 0 "U5" H 8150 3000 60 0000 C CNN +F 1 "d_dlatch" H 8150 3150 60 0000 C CNN +F 2 "" H 8150 3000 60 0000 C CNN +F 3 "" H 8150 3000 60 0000 C CNN + 1 8150 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2550 3300 2550 4350 +Wire Wire Line + 2550 4350 7600 4350 +Wire Wire Line + 7600 4350 7600 3300 +Wire Wire Line + 5900 3300 5850 3300 +Wire Wire Line + 5850 3300 5850 4350 +Connection ~ 5850 4350 +Wire Wire Line + 4200 3300 4000 3300 +Wire Wire Line + 4000 3300 4000 4350 +Connection ~ 4000 4350 +Wire Wire Line + 2550 2650 1950 2650 +Wire Wire Line + 1950 2650 1950 1750 +Wire Wire Line + 4200 2650 4000 2650 +Wire Wire Line + 4000 2650 4000 1650 +Wire Wire Line + 5900 2650 5700 2650 +Wire Wire Line + 5700 2650 5700 1650 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 1650 +Wire Wire Line + 3650 2650 3800 2650 +Wire Wire Line + 3800 2650 3800 4950 +Wire Wire Line + 5300 2650 5600 2650 +Wire Wire Line + 5600 2650 5600 5050 +Wire Wire Line + 7000 2650 7250 2650 +Wire Wire Line + 7250 2650 7250 5050 +Wire Wire Line + 8700 2650 9000 2650 +Wire Wire Line + 9000 2650 9000 5100 +$Comp +L PORT U1 +U 1 1 6835FA8C +P 1700 1750 +F 0 "U1" H 1750 1850 30 0000 C CNN +F 1 "PORT" H 1700 1750 30 0000 C CNN +F 2 "" H 1700 1750 60 0000 C CNN +F 3 "" H 1700 1750 60 0000 C CNN + 1 1700 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6835FADB +P 3750 1650 +F 0 "U1" H 3800 1750 30 0000 C CNN +F 1 "PORT" H 3750 1650 30 0000 C CNN +F 2 "" H 3750 1650 60 0000 C CNN +F 3 "" H 3750 1650 60 0000 C CNN + 4 3750 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6835FB28 +P 5450 1650 +F 0 "U1" H 5500 1750 30 0000 C CNN +F 1 "PORT" H 5450 1650 30 0000 C CNN +F 2 "" H 5450 1650 60 0000 C CNN +F 3 "" H 5450 1650 60 0000 C CNN + 6 5450 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6835FB6B +P 7150 1650 +F 0 "U1" H 7200 1750 30 0000 C CNN +F 1 "PORT" H 7150 1650 30 0000 C CNN +F 2 "" H 7150 1650 60 0000 C CNN +F 3 "" H 7150 1650 60 0000 C CNN + 8 7150 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6835FBC2 +P 2300 4350 +F 0 "U1" H 2350 4450 30 0000 C CNN +F 1 "PORT" H 2300 4350 30 0000 C CNN +F 2 "" H 2300 4350 60 0000 C CNN +F 3 "" H 2300 4350 60 0000 C CNN + 2 2300 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6835FC17 +P 3550 4950 +F 0 "U1" H 3600 5050 30 0000 C CNN +F 1 "PORT" H 3550 4950 30 0000 C CNN +F 2 "" H 3550 4950 60 0000 C CNN +F 3 "" H 3550 4950 60 0000 C CNN + 3 3550 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6835FC84 +P 5350 5050 +F 0 "U1" H 5400 5150 30 0000 C CNN +F 1 "PORT" H 5350 5050 30 0000 C CNN +F 2 "" H 5350 5050 60 0000 C CNN +F 3 "" H 5350 5050 60 0000 C CNN + 5 5350 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6835FCDF +P 7000 5050 +F 0 "U1" H 7050 5150 30 0000 C CNN +F 1 "PORT" H 7000 5050 30 0000 C CNN +F 2 "" H 7000 5050 60 0000 C CNN +F 3 "" H 7000 5050 60 0000 C CNN + 7 7000 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6835FD3C +P 8750 5100 +F 0 "U1" H 8800 5200 30 0000 C CNN +F 1 "PORT" H 8750 5100 30 0000 C CNN +F 2 "" H 8750 5100 60 0000 C CNN +F 3 "" H 8750 5100 60 0000 C CNN + 9 8750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 3300 3650 4650 +Wire Wire Line + 3650 4650 3400 4650 +Wire Wire Line + 5300 3300 5300 4700 +Wire Wire Line + 5300 4700 5150 4700 +Wire Wire Line + 7000 3300 7000 4700 +Wire Wire Line + 7000 4700 6850 4700 +Wire Wire Line + 8700 3300 8700 4650 +Wire Wire Line + 8700 4650 8550 4650 +$Comp +L PORT U1 +U 10 1 6835FE64 +P 3150 4650 +F 0 "U1" H 3200 4750 30 0000 C CNN +F 1 "PORT" H 3150 4650 30 0000 C CNN +F 2 "" H 3150 4650 60 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 10 3150 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6835FEC7 +P 4900 4700 +F 0 "U1" H 4950 4800 30 0000 C CNN +F 1 "PORT" H 4900 4700 30 0000 C CNN +F 2 "" H 4900 4700 60 0000 C CNN +F 3 "" H 4900 4700 60 0000 C CNN + 11 4900 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6835FF20 +P 6600 4700 +F 0 "U1" H 6650 4800 30 0000 C CNN +F 1 "PORT" H 6600 4700 30 0000 C CNN +F 2 "" H 6600 4700 60 0000 C CNN +F 3 "" H 6600 4700 60 0000 C CNN + 12 6600 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6835FF77 +P 8300 4650 +F 0 "U1" H 8350 4750 30 0000 C CNN +F 1 "PORT" H 8300 4650 30 0000 C CNN +F 2 "" H 8300 4650 60 0000 C CNN +F 3 "" H 8300 4650 60 0000 C CNN + 13 8300 4650 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub new file mode 100644 index 00000000..2ebb644d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub @@ -0,0 +1,22 @@ +* Subcircuit 375 +.subckt 375 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\375\375.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ d_dlatch +* u3 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ d_dlatch +* u4 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ d_dlatch +* u5 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ d_dlatch +a1 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ u2 +a2 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ u3 +a3 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ u4 +a4 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ u5 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends 375
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375_Previous_Values.xml new file mode 100644 index 00000000..2eb57a73 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_dlatch<field1 name="Enter Data Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for Data Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_dlatch<field12 name="Enter Data Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_dlatch<field23 name="Enter Data Delay (default=1.0e-9)" /><field24 name="Enter Enable Delay (default=1.0e-9)" /><field25 name="Enter Set Delay (default=1.0e-9)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter IC (default=0)" /><field28 name="Enter value for Data Load (default=1.0e-12)" /><field29 name="Enter value for Enable Load (default=1.0e-12)" /><field30 name="Enter value for Set Load (default=1.0e-12)" /><field31 name="Enter value for Reset Load (default=1.0e-12)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">d_dlatch<field34 name="Enter Data Delay (default=1.0e-9)" /><field35 name="Enter Enable Delay (default=1.0e-9)" /><field36 name="Enter Set Delay (default=1.0e-9)" /><field37 name="Enter Reset Delay (default=1.0)" /><field38 name="Enter IC (default=0)" /><field39 name="Enter value for Data Load (default=1.0e-12)" /><field40 name="Enter value for Enable Load (default=1.0e-12)" /><field41 name="Enter value for Set Load (default=1.0e-12)" /><field42 name="Enter value for Reset Load (default=1.0e-12)" /><field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /></u5></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/analysis b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/analysis new file mode 100644 index 00000000..f496aec4 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/analysis @@ -0,0 +1 @@ +.tran 1e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375-cache.lib new file mode 100644 index 00000000..3154fa3d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 373 +# +DEF 373 X 0 40 Y Y 1 F N +F0 "X" -50 -200 60 H V C CNN +F1 "373" -50 700 60 H V C CNN +F2 "" -50 700 60 H I C CNN +F3 "" -50 700 60 H I C CNN +DRAW +S 200 650 -300 -150 0 1 0 N +X do 1 -500 600 200 R 50 50 1 1 I +X en 2 -500 150 200 R 50 50 1 1 I +X Q0 3 400 600 200 L 50 50 1 1 O +X d2 4 -500 500 200 R 50 50 1 1 I +X Q1 5 400 500 200 L 50 50 1 1 O +X d3 6 -500 400 200 R 50 50 1 1 I +X Q2 7 400 400 200 L 50 50 1 1 O +X d4 8 -500 300 200 R 50 50 1 1 I +X Q3 9 400 300 200 L 50 50 1 1 O +X Q0_1 10 400 200 200 L 50 50 1 1 O +X Q0_2 11 400 100 200 L 50 50 1 1 O +X Q0_3 12 400 0 200 L 50 50 1 1 O +X Q0_4 13 400 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_5 +# +DEF adc_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir new file mode 100644 index 00000000..4054588f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir @@ -0,0 +1,31 @@ +* C:\Users\Shanthipriya\eSim-Workspace\375_ic3\375_ic3.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 23:44:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v2 1D GND pulse +v3 2D GND pulse +v4 3D GND pulse +v5 4D GND pulse +v1 E GND pulse +U4 Q0 plot_v1 +U5 Q1 plot_v1 +U6 Q2 plot_v1 +U7 Q3 plot_v1 +U8 Q0_1 plot_v1 +U9 Q0_2 plot_v1 +U10 Q0_3 plot_v1 +U3 Q0_4 plot_v1 +U1 1D E 2D 3D 4D Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ adc_bridge_5 +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Q0 Q1 Q2 Q3 Q0_1 Q0_2 Q0_3 Q0_4 dac_bridge_8 +X1 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U2-Pad1_ Net-_U1-Pad8_ Net-_U2-Pad2_ Net-_U1-Pad9_ Net-_U2-Pad3_ Net-_U1-Pad10_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ 373 +U13 1D plot_v1 +U14 E plot_v1 +U15 2D plot_v1 +U11 3D plot_v1 +U12 4D plot_v1 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir.out new file mode 100644 index 00000000..0e2b2b72 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir.out @@ -0,0 +1,43 @@ +* c:\users\shanthipriya\esim-workspace\375_ic3\375_ic3.cir + +.include 375.sub +v2 1d gnd pulse(0 5 0 1n 1n 4m 8m) +v3 2d gnd pulse(0 5 0 1n 1n 8m 16m) +v4 3d gnd pulse(0 5 0 1n 1n 16m 32m) +v5 4d gnd pulse(0 5 0 1n 1n 32m 64m) +v1 e gnd pulse(0 5 0 1n 1n 2m 4m) +* u4 q0 plot_v1 +* u5 q1 plot_v1 +* u6 q2 plot_v1 +* u7 q3 plot_v1 +* u8 q0_1 plot_v1 +* u9 q0_2 plot_v1 +* u10 q0_3 plot_v1 +* u3 q0_4 plot_v1 +* u1 1d e 2d 3d 4d net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ adc_bridge_5 +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ q0 q1 q2 q3 q0_1 q0_2 q0_3 q0_4 dac_bridge_8 +x1 net-_u1-pad6_ net-_u1-pad7_ net-_u2-pad1_ net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad9_ net-_u2-pad3_ net-_u1-pad10_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ 375 +* u13 1d plot_v1 +* u14 e plot_v1 +* u15 2d plot_v1 +* u11 3d plot_v1 +* u12 4d plot_v1 +a1 [1d e 2d 3d 4d ] [net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ] u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] [q0 q1 q2 q3 q0_1 q0_2 q0_3 q0_4 ] u2 +* Schematic Name: adc_bridge_5, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 1e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(1d)+6 v(e)+12v(q0)+18v(q0_1) +plot v(2d)+6 v(e)+12v(q1)+18 v(q0_2) +plot v(3d)+6 v(e)+12v(q2)+18v(q0_3) +plot v(4d)6 v(e)+12v(q3)+18v(q0_4) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.pro b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.proj b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.proj new file mode 100644 index 00000000..07f4ec98 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.proj @@ -0,0 +1 @@ +schematicFile 375_ic3.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.sch b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.sch new file mode 100644 index 00000000..142db262 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.sch @@ -0,0 +1,550 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:375_ic3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 2250 2600 3550 2600 +Wire Wire Line + 1750 1950 3650 1950 +Wire Wire Line + 1750 3450 3500 3450 +Wire Wire Line + 2800 4850 1750 4850 +Wire Wire Line + 1750 6300 2900 6300 +$Comp +L pulse v2 +U 1 1 6835FCBB +P 1750 2400 +F 0 "v2" H 1550 2500 60 0000 C CNN +F 1 "pulse" H 1550 2350 60 0000 C CNN +F 2 "R1" H 1450 2400 60 0000 C CNN +F 3 "" H 1750 2400 60 0000 C CNN + 1 1750 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 6835FCBC +P 1750 3000 +F 0 "#PWR01" H 1750 2750 50 0001 C CNN +F 1 "GND" H 1750 2850 50 0000 C CNN +F 2 "" H 1750 3000 50 0001 C CNN +F 3 "" H 1750 3000 50 0001 C CNN + 1 1750 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 3000 1750 2850 +$Comp +L pulse v3 +U 1 1 6835FCBD +P 1750 3900 +F 0 "v3" H 1550 4000 60 0000 C CNN +F 1 "pulse" H 1550 3850 60 0000 C CNN +F 2 "R1" H 1450 3900 60 0000 C CNN +F 3 "" H 1750 3900 60 0000 C CNN + 1 1750 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 6835FCBE +P 1750 4500 +F 0 "#PWR02" H 1750 4250 50 0001 C CNN +F 1 "GND" H 1750 4350 50 0000 C CNN +F 2 "" H 1750 4500 50 0001 C CNN +F 3 "" H 1750 4500 50 0001 C CNN + 1 1750 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 4500 1750 4350 +$Comp +L pulse v4 +U 1 1 6835FCBF +P 1750 5300 +F 0 "v4" H 1550 5400 60 0000 C CNN +F 1 "pulse" H 1550 5250 60 0000 C CNN +F 2 "R1" H 1450 5300 60 0000 C CNN +F 3 "" H 1750 5300 60 0000 C CNN + 1 1750 5300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 6835FCC0 +P 1750 5900 +F 0 "#PWR03" H 1750 5650 50 0001 C CNN +F 1 "GND" H 1750 5750 50 0000 C CNN +F 2 "" H 1750 5900 50 0001 C CNN +F 3 "" H 1750 5900 50 0001 C CNN + 1 1750 5900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 5900 1750 5750 +$Comp +L pulse v5 +U 1 1 6835FCC1 +P 1750 6750 +F 0 "v5" H 1550 6850 60 0000 C CNN +F 1 "pulse" H 1550 6700 60 0000 C CNN +F 2 "R1" H 1450 6750 60 0000 C CNN +F 3 "" H 1750 6750 60 0000 C CNN + 1 1750 6750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 6835FCC2 +P 1750 7350 +F 0 "#PWR04" H 1750 7100 50 0001 C CNN +F 1 "GND" H 1750 7200 50 0000 C CNN +F 2 "" H 1750 7350 50 0001 C CNN +F 3 "" H 1750 7350 50 0001 C CNN + 1 1750 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 7350 1750 7200 +Wire Wire Line + 2250 3200 1100 3200 +Connection ~ 2250 3200 +$Comp +L pulse v1 +U 1 1 6835FCC3 +P 1100 3650 +F 0 "v1" H 900 3750 60 0000 C CNN +F 1 "pulse" H 900 3600 60 0000 C CNN +F 2 "R1" H 800 3650 60 0000 C CNN +F 3 "" H 1100 3650 60 0000 C CNN + 1 1100 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 6835FCC4 +P 1100 4250 +F 0 "#PWR05" H 1100 4000 50 0001 C CNN +F 1 "GND" H 1100 4100 50 0000 C CNN +F 2 "" H 1100 4250 50 0001 C CNN +F 3 "" H 1100 4250 50 0001 C CNN + 1 1100 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 4250 1100 4100 +$Comp +L plot_v1 U4 +U 1 1 6835FCC5 +P 10150 1950 +F 0 "U4" H 10150 2450 60 0000 C CNN +F 1 "plot_v1" H 10350 2300 60 0000 C CNN +F 2 "" H 10150 1950 60 0000 C CNN +F 3 "" H 10150 1950 60 0000 C CNN + 1 10150 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 1750 10150 1750 +$Comp +L plot_v1 U5 +U 1 1 6835FCC6 +P 10150 2600 +F 0 "U5" H 10150 3100 60 0000 C CNN +F 1 "plot_v1" H 10350 2950 60 0000 C CNN +F 2 "" H 10150 2600 60 0000 C CNN +F 3 "" H 10150 2600 60 0000 C CNN + 1 10150 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8250 2400 10150 2400 +Text GLabel 9650 2100 0 60 Input ~ 0 +Q1 +Wire Wire Line + 9650 2100 9850 2100 +Wire Wire Line + 9850 2100 9850 2400 +Text GLabel 8900 1350 0 60 Input ~ 0 +Q0 +Wire Wire Line + 8900 1350 9100 1350 +Wire Wire Line + 9100 1350 9100 1750 +Connection ~ 9850 2400 +$Comp +L plot_v1 U6 +U 1 1 6835FCC7 +P 10150 3450 +F 0 "U6" H 10150 3950 60 0000 C CNN +F 1 "plot_v1" H 10350 3800 60 0000 C CNN +F 2 "" H 10150 3450 60 0000 C CNN +F 3 "" H 10150 3450 60 0000 C CNN + 1 10150 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 3250 10150 3250 +$Comp +L plot_v1 U7 +U 1 1 6835FCC8 +P 10150 4100 +F 0 "U7" H 10150 4600 60 0000 C CNN +F 1 "plot_v1" H 10350 4450 60 0000 C CNN +F 2 "" H 10150 4100 60 0000 C CNN +F 3 "" H 10150 4100 60 0000 C CNN + 1 10150 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8400 3900 10150 3900 +Text GLabel 9000 3400 0 60 Input ~ 0 +Q3 +Wire Wire Line + 9000 3400 9200 3400 +Wire Wire Line + 9200 3400 9200 3900 +Connection ~ 9800 3250 +Text GLabel 9600 2950 0 60 Input ~ 0 +Q2 +Wire Wire Line + 9600 2950 9800 2950 +Wire Wire Line + 9800 2950 9800 3250 +$Comp +L plot_v1 U8 +U 1 1 6835FCC9 +P 10150 4850 +F 0 "U8" H 10150 5350 60 0000 C CNN +F 1 "plot_v1" H 10350 5200 60 0000 C CNN +F 2 "" H 10150 4850 60 0000 C CNN +F 3 "" H 10150 4850 60 0000 C CNN + 1 10150 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9200 4650 10150 4650 +$Comp +L plot_v1 U9 +U 1 1 6835FCCA +P 10150 5500 +F 0 "U9" H 10150 6000 60 0000 C CNN +F 1 "plot_v1" H 10350 5850 60 0000 C CNN +F 2 "" H 10150 5500 60 0000 C CNN +F 3 "" H 10150 5500 60 0000 C CNN + 1 10150 5500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 5300 10150 5300 +Text GLabel 9650 5000 0 60 Input ~ 0 +Q0_2 +Wire Wire Line + 9650 5000 9850 5000 +Wire Wire Line + 9850 5000 9850 5300 +Connection ~ 9800 4650 +Text GLabel 9600 4350 0 60 Input ~ 0 +Q0_1 +Wire Wire Line + 9600 4350 9800 4350 +Wire Wire Line + 9800 4350 9800 4650 +Connection ~ 9850 5300 +$Comp +L plot_v1 U10 +U 1 1 6835FCCB +P 10150 6300 +F 0 "U10" H 10150 6800 60 0000 C CNN +F 1 "plot_v1" H 10350 6650 60 0000 C CNN +F 2 "" H 10150 6300 60 0000 C CNN +F 3 "" H 10150 6300 60 0000 C CNN + 1 10150 6300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 6100 10150 6100 +$Comp +L plot_v1 U3 +U 1 1 6835FCCC +P 9850 6950 +F 0 "U3" H 9850 7450 60 0000 C CNN +F 1 "plot_v1" H 10050 7300 60 0000 C CNN +F 2 "" H 9850 6950 60 0000 C CNN +F 3 "" H 9850 6950 60 0000 C CNN + 1 9850 6950 + 1 0 0 -1 +$EndComp +Text GLabel 9350 6450 0 60 Input ~ 0 +Q0_4 +Wire Wire Line + 9350 6450 9550 6450 +Connection ~ 9800 6100 +Text GLabel 9600 5800 0 60 Input ~ 0 +Q0_3 +Wire Wire Line + 9600 5800 9800 5800 +Wire Wire Line + 9800 5800 9800 6100 +Connection ~ 9850 6750 +Text GLabel 2200 1800 0 60 Input ~ 0 +1D +Wire Wire Line + 2200 1800 2350 1800 +Wire Wire Line + 2350 1800 2350 1950 +Connection ~ 2350 1950 +Text GLabel 2300 2350 0 60 Input ~ 0 +E +Wire Wire Line + 2300 2350 2450 2350 +Wire Wire Line + 2450 2350 2450 2600 +Connection ~ 2450 2600 +Text GLabel 2500 3150 0 60 Input ~ 0 +2D +Wire Wire Line + 2600 3150 2600 3450 +Connection ~ 2600 3450 +Text GLabel 2000 4450 0 60 Input ~ 0 +3D +Wire Wire Line + 2000 4450 2150 4450 +Wire Wire Line + 2150 4450 2150 4850 +Connection ~ 2150 4850 +Text GLabel 2000 5800 0 60 Input ~ 0 +4D +Wire Wire Line + 2000 5800 2150 5800 +Wire Wire Line + 2150 5800 2150 6300 +Connection ~ 2150 6300 +$Comp +L adc_bridge_5 U1 +U 1 1 6835FCCD +P 4250 3850 +F 0 "U1" H 4250 3850 60 0000 C CNN +F 1 "adc_bridge_5" H 4250 4000 60 0000 C CNN +F 2 "" H 4250 3850 60 0000 C CNN +F 3 "" H 4250 3850 60 0000 C CNN + 1 4250 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 1950 3650 3800 +Wire Wire Line + 3550 2600 3550 3900 +Wire Wire Line + 3550 3900 3650 3900 +Wire Wire Line + 3500 3450 3500 4000 +Wire Wire Line + 3500 4000 3650 4000 +Wire Wire Line + 2250 3200 2250 2600 +Wire Wire Line + 2800 4850 2800 4100 +Wire Wire Line + 2800 4100 3650 4100 +Wire Wire Line + 2900 6300 2900 4200 +Wire Wire Line + 2900 4200 3650 4200 +$Comp +L dac_bridge_8 U2 +U 1 1 6835FCCE +P 7600 3850 +F 0 "U2" H 7600 3850 60 0000 C CNN +F 1 "dac_bridge_8" H 7600 4000 60 0000 C CNN +F 2 "" H 7600 3850 60 0000 C CNN +F 3 "" H 7600 3850 60 0000 C CNN + 1 7600 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 3800 8150 1750 +Wire Wire Line + 8150 3900 8250 3900 +Wire Wire Line + 8250 3900 8250 2400 +Wire Wire Line + 8150 4000 8300 4000 +Wire Wire Line + 8300 4000 8300 3250 +Wire Wire Line + 8150 4100 8400 4100 +Wire Wire Line + 8400 4100 8400 3900 +Wire Wire Line + 8150 4200 9200 4200 +Wire Wire Line + 9200 4200 9200 4650 +Wire Wire Line + 8150 4300 9150 4300 +Wire Wire Line + 9150 4300 9150 5300 +Wire Wire Line + 8150 4400 9000 4400 +Wire Wire Line + 9000 4400 9000 6100 +Wire Wire Line + 8150 4500 8900 4500 +Wire Wire Line + 8900 4500 8900 6750 +Wire Wire Line + 2500 3150 2600 3150 +Connection ~ 9100 1750 +Connection ~ 9200 3900 +Wire Wire Line + 4800 3800 6100 3800 +Wire Wire Line + 4800 3900 5300 3900 +Wire Wire Line + 5300 3900 5300 4250 +Wire Wire Line + 5300 4250 6100 4250 +Wire Wire Line + 4800 4000 5400 4000 +Wire Wire Line + 5400 4000 5400 3900 +Wire Wire Line + 5400 3900 6100 3900 +Wire Wire Line + 4800 4100 5550 4100 +Wire Wire Line + 5550 4100 5550 4000 +Wire Wire Line + 5550 4000 6100 4000 +Wire Wire Line + 4800 4200 5750 4200 +Wire Wire Line + 5750 4200 5750 4100 +$Comp +L 373 X1 +U 1 1 6835FEE3 +P 6600 4400 +F 0 "X1" H 6550 4200 60 0000 C CNN +F 1 "373" H 6550 5100 60 0000 C CNN +F 2 "" H 6550 5100 60 0001 C CNN +F 3 "" H 6550 5100 60 0001 C CNN + 1 6600 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5750 4100 6100 4100 +Wire Wire Line + 8900 6750 9850 6750 +Wire Wire Line + 9550 6450 9550 6750 +Connection ~ 9550 6750 +$Comp +L plot_v1 U13 +U 1 1 68360BA7 +P 2350 2000 +F 0 "U13" H 2350 2500 60 0000 C CNN +F 1 "plot_v1" H 2550 2350 60 0000 C CNN +F 2 "" H 2350 2000 60 0000 C CNN +F 3 "" H 2350 2000 60 0000 C CNN + 1 2350 2000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 68360C82 +P 2450 2550 +F 0 "U14" H 2450 3050 60 0000 C CNN +F 1 "plot_v1" H 2650 2900 60 0000 C CNN +F 2 "" H 2450 2550 60 0000 C CNN +F 3 "" H 2450 2550 60 0000 C CNN + 1 2450 2550 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U15 +U 1 1 68360CD7 +P 2600 3350 +F 0 "U15" H 2600 3850 60 0000 C CNN +F 1 "plot_v1" H 2800 3700 60 0000 C CNN +F 2 "" H 2600 3350 60 0000 C CNN +F 3 "" H 2600 3350 60 0000 C CNN + 1 2600 3350 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 68360D2A +P 2150 4650 +F 0 "U11" H 2150 5150 60 0000 C CNN +F 1 "plot_v1" H 2350 5000 60 0000 C CNN +F 2 "" H 2150 4650 60 0000 C CNN +F 3 "" H 2150 4650 60 0000 C CNN + 1 2150 4650 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 68360D89 +P 2150 6000 +F 0 "U12" H 2150 6500 60 0000 C CNN +F 1 "plot_v1" H 2350 6350 60 0000 C CNN +F 2 "" H 2150 6000 60 0000 C CNN +F 3 "" H 2150 6000 60 0000 C CNN + 1 2150 6000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375_Previous_Values.xml new file mode 100644 index 00000000..5035a68a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">8m</field5><field5 name="Period">16m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">16m</field5><field5 name="Period">32m</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">32m</field5><field5 name="Period">64m</field5></v5><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">4m</field5></v1></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\375</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
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