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-rw-r--r--library/SubcircuitLibrary/HCF4042B/HCF4042B-cache.lib156
-rw-r--r--library/SubcircuitLibrary/HCF4042B/HCF4042B.cir76
-rw-r--r--library/SubcircuitLibrary/HCF4042B/HCF4042B.cir.out214
-rw-r--r--library/SubcircuitLibrary/HCF4042B/HCF4042B.pro73
-rw-r--r--library/SubcircuitLibrary/HCF4042B/HCF4042B.sch1515
-rw-r--r--library/SubcircuitLibrary/HCF4042B/HCF4042B.sub208
-rw-r--r--library/SubcircuitLibrary/HCF4042B/HCF4042B_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/HCF4042B/NMOS-180nm.lib13
-rw-r--r--library/SubcircuitLibrary/HCF4042B/PMOS-180nm.lib11
-rw-r--r--library/SubcircuitLibrary/HCF4042B/analysis1
10 files changed, 2268 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B-cache.lib b/library/SubcircuitLibrary/HCF4042B/HCF4042B-cache.lib
new file mode 100644
index 00000000..1efb9919
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B-cache.lib
@@ -0,0 +1,156 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B.cir b/library/SubcircuitLibrary/HCF4042B/HCF4042B.cir
new file mode 100644
index 00000000..bec0282f
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B.cir
@@ -0,0 +1,76 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\HCF4042B\HCF4042B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 11:33:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M3 Net-_M1-Pad3_ Net-_M10-Pad2_ Net-_M1-Pad1_ VSS mosfet_n
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ VDD mosfet_p
+M9 Net-_M1-Pad3_ Net-_M10-Pad2_ Net-_M11-Pad1_ VSS mosfet_n
+M11 Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ VDD mosfet_p
+U6 Net-_M1-Pad3_ Net-_U13-Pad1_ adc_bridge_1
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U29 Net-_U13-Pad2_ Net-_U29-Pad2_ d_inverter
+U36 Net-_U29-Pad2_ Net-_U1-Pad2_ d_buffer
+U19 Net-_U13-Pad2_ Net-_U19-Pad2_ d_inverter
+U20 Net-_U19-Pad2_ Net-_U12-Pad2_ d_buffer
+U12 Net-_M11-Pad1_ Net-_U12-Pad2_ adc_bridge_1
+U32 Net-_U12-Pad2_ Net-_U1-Pad3_ d_inverter
+U1 Net-_M1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_M2-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_M4-Pad1_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_M7-Pad1_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ VDD VSS PORT
+M5 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M2-Pad1_ VSS mosfet_n
+M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M10-Pad1_ VDD mosfet_p
+M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ VSS mosfet_n
+M13 Net-_M10-Pad3_ Net-_M1-Pad2_ Net-_M10-Pad1_ VDD mosfet_p
+U7 Net-_M10-Pad1_ Net-_U16-Pad1_ adc_bridge_1
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+U30 Net-_U16-Pad2_ Net-_U30-Pad2_ d_inverter
+U39 Net-_U30-Pad2_ Net-_U1-Pad5_ d_buffer
+U22 Net-_U16-Pad2_ Net-_U22-Pad2_ d_inverter
+U23 Net-_U22-Pad2_ Net-_U14-Pad2_ d_buffer
+U14 Net-_M10-Pad3_ Net-_U14-Pad2_ adc_bridge_1
+U33 Net-_U14-Pad2_ Net-_U1-Pad6_ d_inverter
+M6 Net-_M12-Pad1_ Net-_M10-Pad2_ Net-_M4-Pad1_ VSS mosfet_n
+M4 Net-_M4-Pad1_ Net-_M1-Pad2_ Net-_M12-Pad1_ VDD mosfet_p
+M12 Net-_M12-Pad1_ Net-_M10-Pad2_ Net-_M12-Pad3_ VSS mosfet_n
+M14 Net-_M12-Pad3_ Net-_M1-Pad2_ Net-_M12-Pad1_ VDD mosfet_p
+U8 Net-_M12-Pad1_ Net-_U17-Pad1_ adc_bridge_1
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter
+U31 Net-_U17-Pad2_ Net-_U31-Pad2_ d_inverter
+U40 Net-_U31-Pad2_ Net-_U1-Pad8_ d_buffer
+U25 Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter
+U26 Net-_U25-Pad2_ Net-_U15-Pad2_ d_buffer
+U15 Net-_M12-Pad3_ Net-_U15-Pad2_ adc_bridge_1
+U35 Net-_U15-Pad2_ Net-_U1-Pad9_ d_inverter
+M8 Net-_M15-Pad1_ Net-_M10-Pad2_ Net-_M7-Pad1_ VSS mosfet_n
+M7 Net-_M7-Pad1_ Net-_M1-Pad2_ Net-_M15-Pad1_ VDD mosfet_p
+M15 Net-_M15-Pad1_ Net-_M10-Pad2_ Net-_M15-Pad3_ VSS mosfet_n
+M16 Net-_M15-Pad3_ Net-_M1-Pad2_ Net-_M15-Pad1_ VDD mosfet_p
+U9 Net-_M15-Pad1_ Net-_U21-Pad1_ adc_bridge_1
+U21 Net-_U21-Pad1_ Net-_U21-Pad2_ d_inverter
+U34 Net-_U21-Pad2_ Net-_U34-Pad2_ d_inverter
+U42 Net-_U34-Pad2_ Net-_U1-Pad11_ d_buffer
+U27 Net-_U21-Pad2_ Net-_U27-Pad2_ d_inverter
+U28 Net-_U27-Pad2_ Net-_U18-Pad2_ d_buffer
+U18 Net-_M15-Pad3_ Net-_U18-Pad2_ adc_bridge_1
+U37 Net-_U18-Pad2_ Net-_U1-Pad12_ d_inverter
+U4 Net-_U1-Pad13_ Net-_U10-Pad1_ d_inverter
+M17 Net-_M17-Pad1_ Net-_M17-Pad2_ Net-_M17-Pad3_ VSS mosfet_n
+M18 Net-_M17-Pad3_ Net-_M18-Pad2_ Net-_M17-Pad1_ VDD mosfet_p
+M20 Net-_M17-Pad3_ Net-_M17-Pad2_ Net-_M19-Pad1_ VSS mosfet_n
+M19 Net-_M19-Pad1_ Net-_M18-Pad2_ Net-_M17-Pad3_ VDD mosfet_p
+U10 Net-_U10-Pad1_ Net-_M17-Pad1_ dac_bridge_1
+U2 Net-_U1-Pad13_ Net-_M19-Pad1_ dac_bridge_1
+U44 Net-_U43-Pad2_ Net-_U44-Pad2_ d_inverter
+U43 Net-_U41-Pad2_ Net-_U43-Pad2_ d_inverter
+U41 Net-_M17-Pad3_ Net-_U41-Pad2_ adc_bridge_1
+U45 Net-_U44-Pad2_ Net-_M10-Pad2_ dac_bridge_1
+U46 Net-_U43-Pad2_ Net-_M1-Pad2_ dac_bridge_1
+U3 Net-_U1-Pad14_ Net-_U11-Pad1_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U24 Net-_U11-Pad2_ Net-_U24-Pad2_ d_buffer
+U38 Net-_U24-Pad2_ Net-_M17-Pad2_ dac_bridge_1
+U5 Net-_U11-Pad1_ Net-_M18-Pad2_ dac_bridge_1
+
+.end
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B.cir.out b/library/SubcircuitLibrary/HCF4042B/HCF4042B.cir.out
new file mode 100644
index 00000000..4b5f9c7d
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B.cir.out
@@ -0,0 +1,214 @@
+* c:\fossee\esim\library\subcircuitlibrary\hcf4042b\hcf4042b.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m3 net-_m1-pad3_ net-_m10-pad2_ net-_m1-pad1_ vss CMOSN W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+m9 net-_m1-pad3_ net-_m10-pad2_ net-_m11-pad1_ vss CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+* u6 net-_m1-pad3_ net-_u13-pad1_ adc_bridge_1
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u36 net-_u29-pad2_ net-_u1-pad2_ d_buffer
+* u19 net-_u13-pad2_ net-_u19-pad2_ d_inverter
+* u20 net-_u19-pad2_ net-_u12-pad2_ d_buffer
+* u12 net-_m11-pad1_ net-_u12-pad2_ adc_bridge_1
+* u32 net-_u12-pad2_ net-_u1-pad3_ d_inverter
+* u1 net-_m1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_m4-pad1_ net-_u1-pad8_ net-_u1-pad9_ net-_m7-pad1_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ vdd vss port
+m5 net-_m10-pad1_ net-_m10-pad2_ net-_m2-pad1_ vss CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1
+m13 net-_m10-pad3_ net-_m1-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1
+* u7 net-_m10-pad1_ net-_u16-pad1_ adc_bridge_1
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u30 net-_u16-pad2_ net-_u30-pad2_ d_inverter
+* u39 net-_u30-pad2_ net-_u1-pad5_ d_buffer
+* u22 net-_u16-pad2_ net-_u22-pad2_ d_inverter
+* u23 net-_u22-pad2_ net-_u14-pad2_ d_buffer
+* u14 net-_m10-pad3_ net-_u14-pad2_ adc_bridge_1
+* u33 net-_u14-pad2_ net-_u1-pad6_ d_inverter
+m6 net-_m12-pad1_ net-_m10-pad2_ net-_m4-pad1_ vss CMOSN W=100u L=100u M=1
+m4 net-_m4-pad1_ net-_m1-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m10-pad2_ net-_m12-pad3_ vss CMOSN W=100u L=100u M=1
+m14 net-_m12-pad3_ net-_m1-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1
+* u8 net-_m12-pad1_ net-_u17-pad1_ adc_bridge_1
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u31 net-_u17-pad2_ net-_u31-pad2_ d_inverter
+* u40 net-_u31-pad2_ net-_u1-pad8_ d_buffer
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u26 net-_u25-pad2_ net-_u15-pad2_ d_buffer
+* u15 net-_m12-pad3_ net-_u15-pad2_ adc_bridge_1
+* u35 net-_u15-pad2_ net-_u1-pad9_ d_inverter
+m8 net-_m15-pad1_ net-_m10-pad2_ net-_m7-pad1_ vss CMOSN W=100u L=100u M=1
+m7 net-_m7-pad1_ net-_m1-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m15 net-_m15-pad1_ net-_m10-pad2_ net-_m15-pad3_ vss CMOSN W=100u L=100u M=1
+m16 net-_m15-pad3_ net-_m1-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+* u9 net-_m15-pad1_ net-_u21-pad1_ adc_bridge_1
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u34 net-_u21-pad2_ net-_u34-pad2_ d_inverter
+* u42 net-_u34-pad2_ net-_u1-pad11_ d_buffer
+* u27 net-_u21-pad2_ net-_u27-pad2_ d_inverter
+* u28 net-_u27-pad2_ net-_u18-pad2_ d_buffer
+* u18 net-_m15-pad3_ net-_u18-pad2_ adc_bridge_1
+* u37 net-_u18-pad2_ net-_u1-pad12_ d_inverter
+* u4 net-_u1-pad13_ net-_u10-pad1_ d_inverter
+m17 net-_m17-pad1_ net-_m17-pad2_ net-_m17-pad3_ vss CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m18-pad2_ net-_m17-pad1_ vdd CMOSP W=100u L=100u M=1
+m20 net-_m17-pad3_ net-_m17-pad2_ net-_m19-pad1_ vss CMOSN W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m18-pad2_ net-_m17-pad3_ vdd CMOSP W=100u L=100u M=1
+* u10 net-_u10-pad1_ net-_m17-pad1_ dac_bridge_1
+* u2 net-_u1-pad13_ net-_m19-pad1_ dac_bridge_1
+* u44 net-_u43-pad2_ net-_u44-pad2_ d_inverter
+* u43 net-_u41-pad2_ net-_u43-pad2_ d_inverter
+* u41 net-_m17-pad3_ net-_u41-pad2_ adc_bridge_1
+* u45 net-_u44-pad2_ net-_m10-pad2_ dac_bridge_1
+* u46 net-_u43-pad2_ net-_m1-pad2_ dac_bridge_1
+* u3 net-_u1-pad14_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u24 net-_u11-pad2_ net-_u24-pad2_ d_buffer
+* u38 net-_u24-pad2_ net-_m17-pad2_ dac_bridge_1
+* u5 net-_u11-pad1_ net-_m18-pad2_ dac_bridge_1
+a1 [net-_m1-pad3_ ] [net-_u13-pad1_ ] u6
+a2 net-_u13-pad1_ net-_u13-pad2_ u13
+a3 net-_u13-pad2_ net-_u29-pad2_ u29
+a4 net-_u29-pad2_ net-_u1-pad2_ u36
+a5 net-_u13-pad2_ net-_u19-pad2_ u19
+a6 net-_u19-pad2_ net-_u12-pad2_ u20
+a7 [net-_m11-pad1_ ] [net-_u12-pad2_ ] u12
+a8 net-_u12-pad2_ net-_u1-pad3_ u32
+a9 [net-_m10-pad1_ ] [net-_u16-pad1_ ] u7
+a10 net-_u16-pad1_ net-_u16-pad2_ u16
+a11 net-_u16-pad2_ net-_u30-pad2_ u30
+a12 net-_u30-pad2_ net-_u1-pad5_ u39
+a13 net-_u16-pad2_ net-_u22-pad2_ u22
+a14 net-_u22-pad2_ net-_u14-pad2_ u23
+a15 [net-_m10-pad3_ ] [net-_u14-pad2_ ] u14
+a16 net-_u14-pad2_ net-_u1-pad6_ u33
+a17 [net-_m12-pad1_ ] [net-_u17-pad1_ ] u8
+a18 net-_u17-pad1_ net-_u17-pad2_ u17
+a19 net-_u17-pad2_ net-_u31-pad2_ u31
+a20 net-_u31-pad2_ net-_u1-pad8_ u40
+a21 net-_u17-pad2_ net-_u25-pad2_ u25
+a22 net-_u25-pad2_ net-_u15-pad2_ u26
+a23 [net-_m12-pad3_ ] [net-_u15-pad2_ ] u15
+a24 net-_u15-pad2_ net-_u1-pad9_ u35
+a25 [net-_m15-pad1_ ] [net-_u21-pad1_ ] u9
+a26 net-_u21-pad1_ net-_u21-pad2_ u21
+a27 net-_u21-pad2_ net-_u34-pad2_ u34
+a28 net-_u34-pad2_ net-_u1-pad11_ u42
+a29 net-_u21-pad2_ net-_u27-pad2_ u27
+a30 net-_u27-pad2_ net-_u18-pad2_ u28
+a31 [net-_m15-pad3_ ] [net-_u18-pad2_ ] u18
+a32 net-_u18-pad2_ net-_u1-pad12_ u37
+a33 net-_u1-pad13_ net-_u10-pad1_ u4
+a34 [net-_u10-pad1_ ] [net-_m17-pad1_ ] u10
+a35 [net-_u1-pad13_ ] [net-_m19-pad1_ ] u2
+a36 net-_u43-pad2_ net-_u44-pad2_ u44
+a37 net-_u41-pad2_ net-_u43-pad2_ u43
+a38 [net-_m17-pad3_ ] [net-_u41-pad2_ ] u41
+a39 [net-_u44-pad2_ ] [net-_m10-pad2_ ] u45
+a40 [net-_u43-pad2_ ] [net-_m1-pad2_ ] u46
+a41 net-_u1-pad14_ net-_u11-pad1_ u3
+a42 net-_u11-pad1_ net-_u11-pad2_ u11
+a43 net-_u11-pad2_ net-_u24-pad2_ u24
+a44 [net-_u24-pad2_ ] [net-_m17-pad2_ ] u38
+a45 [net-_u11-pad1_ ] [net-_m18-pad2_ ] u5
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u42 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u28 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u41 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u45 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u46 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B.pro b/library/SubcircuitLibrary/HCF4042B/HCF4042B.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B.sch b/library/SubcircuitLibrary/HCF4042B/HCF4042B.sch
new file mode 100644
index 00000000..6a5d9996
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B.sch
@@ -0,0 +1,1515 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
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+ 1 20650 21950
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+U 1 1 68566089
+P 19300 26350
+F 0 "U11" H 19300 26250 60 0000 C CNN
+F 1 "d_inverter" H 19300 26500 60 0000 C CNN
+F 2 "" H 19350 26300 60 0000 C CNN
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+ 1 19300 26350
+ 1 0 0 -1
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+U 1 1 68566156
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+F 0 "U24" H 20300 26300 60 0000 C CNN
+F 1 "d_buffer" H 20300 26400 60 0000 C CNN
+F 2 "" H 20300 26350 60 0000 C CNN
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+ 1 20300 26350
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+F 2 "" H 23400 8700 60 0000 C CNN
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+ 5 23400 8700
+ -1 0 0 1
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+F 1 "dac_bridge_1" H 21900 26550 60 0000 C CNN
+F 2 "" H 21900 26400 60 0000 C CNN
+F 3 "" H 21900 26400 60 0000 C CNN
+ 1 21900 26400
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+F 2 "" H 18250 27450 60 0000 C CNN
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+ 17750 9900 17950 9900
+Connection ~ 17950 9900
+Wire Wire Line
+ 20250 9600 20250 9800
+Wire Wire Line
+ 20250 9000 20250 8700
+Connection ~ 20250 8700
+Wire Wire Line
+ 20100 11000 21100 11000
+Wire Wire Line
+ 20250 11000 20250 10950
+Wire Wire Line
+ 18800 9850 18950 9850
+Wire Wire Line
+ 18950 9850 18950 11000
+Connection ~ 18800 9850
+Connection ~ 20250 11000
+Wire Wire Line
+ 16600 8650 16800 8650
+Connection ~ 16800 8650
+Wire Wire Line
+ 22600 8700 23150 8700
+Wire Wire Line
+ 21700 11000 22600 11000
+Wire Wire Line
+ 17100 13200 16900 13200
+Wire Wire Line
+ 16900 13200 16900 13650
+Wire Wire Line
+ 16900 13650 17100 13650
+Wire Wire Line
+ 17500 13650 17600 13650
+Wire Wire Line
+ 17600 13650 17600 13200
+Wire Wire Line
+ 17600 13200 17500 13200
+Wire Wire Line
+ 17400 13400 17350 13400
+Wire Wire Line
+ 17350 13400 17350 13500
+Wire Wire Line
+ 17350 13500 17450 13500
+Wire Wire Line
+ 17450 13500 17450 13550
+Wire Wire Line
+ 18300 14600 18350 14600
+Wire Wire Line
+ 18300 14500 18050 14500
+Wire Wire Line
+ 18050 14850 18300 14850
+Wire Wire Line
+ 18700 14500 18900 14500
+Wire Wire Line
+ 18900 14500 18900 14850
+Wire Wire Line
+ 18900 14850 18700 14850
+Wire Wire Line
+ 18650 14750 18650 14650
+Wire Wire Line
+ 18650 14650 18700 14650
+Wire Wire Line
+ 17100 13450 17100 13300
+Wire Wire Line
+ 17100 13300 17150 13300
+Wire Wire Line
+ 17600 13500 18050 13500
+Wire Wire Line
+ 17850 13500 17850 14700
+Connection ~ 17600 13500
+Connection ~ 17850 13500
+Wire Wire Line
+ 19200 13500 19500 13500
+Wire Wire Line
+ 21350 13500 21550 13500
+Wire Wire Line
+ 20100 13500 20750 13500
+Wire Wire Line
+ 18050 14500 18050 14850
+Wire Wire Line
+ 17850 14700 18050 14700
+Connection ~ 18050 14700
+Wire Wire Line
+ 20350 14400 20350 14600
+Wire Wire Line
+ 20350 13800 20350 13500
+Connection ~ 20350 13500
+Wire Wire Line
+ 20200 15800 21200 15800
+Wire Wire Line
+ 20350 15800 20350 15750
+Wire Wire Line
+ 18900 14650 19050 14650
+Wire Wire Line
+ 19050 14650 19050 15800
+Connection ~ 18900 14650
+Connection ~ 20350 15800
+Wire Wire Line
+ 16700 13450 16900 13450
+Connection ~ 16900 13450
+Wire Wire Line
+ 22700 13500 23250 13500
+Wire Wire Line
+ 21800 15800 22700 15800
+Wire Wire Line
+ 17450 17850 17250 17850
+Wire Wire Line
+ 17250 17850 17250 18300
+Wire Wire Line
+ 17250 18300 17450 18300
+Wire Wire Line
+ 17850 18300 17950 18300
+Wire Wire Line
+ 17950 18300 17950 17850
+Wire Wire Line
+ 17950 17850 17850 17850
+Wire Wire Line
+ 17750 18050 17700 18050
+Wire Wire Line
+ 17700 18050 17700 18150
+Wire Wire Line
+ 17700 18150 17800 18150
+Wire Wire Line
+ 17800 18150 17800 18200
+Wire Wire Line
+ 18650 19250 18700 19250
+Wire Wire Line
+ 18650 19150 18400 19150
+Wire Wire Line
+ 18400 19500 18650 19500
+Wire Wire Line
+ 19050 19150 19250 19150
+Wire Wire Line
+ 19250 19150 19250 19500
+Wire Wire Line
+ 19250 19500 19050 19500
+Wire Wire Line
+ 19000 19400 19000 19300
+Wire Wire Line
+ 19000 19300 19050 19300
+Wire Wire Line
+ 17450 18100 17450 17950
+Wire Wire Line
+ 17450 17950 17500 17950
+Wire Wire Line
+ 17950 18150 18400 18150
+Wire Wire Line
+ 18200 18150 18200 19350
+Connection ~ 17950 18150
+Connection ~ 18200 18150
+Wire Wire Line
+ 19550 18150 19850 18150
+Wire Wire Line
+ 21700 18150 21900 18150
+Wire Wire Line
+ 20450 18150 21100 18150
+Wire Wire Line
+ 18400 19150 18400 19500
+Wire Wire Line
+ 18200 19350 18400 19350
+Connection ~ 18400 19350
+Wire Wire Line
+ 20700 19050 20700 19250
+Wire Wire Line
+ 20700 18450 20700 18150
+Connection ~ 20700 18150
+Wire Wire Line
+ 20550 20450 21550 20450
+Wire Wire Line
+ 20700 20450 20700 20400
+Wire Wire Line
+ 19250 19300 19400 19300
+Wire Wire Line
+ 19400 19300 19400 20450
+Connection ~ 19250 19300
+Connection ~ 20700 20450
+Wire Wire Line
+ 17050 18100 17250 18100
+Connection ~ 17250 18100
+Wire Wire Line
+ 23050 18150 23600 18150
+Wire Wire Line
+ 22150 20450 23050 20450
+Wire Wire Line
+ 20450 22200 20500 22200
+Wire Wire Line
+ 20450 22100 20200 22100
+Wire Wire Line
+ 20200 22450 20450 22450
+Wire Wire Line
+ 20850 22100 21050 22100
+Wire Wire Line
+ 21050 22100 21050 22450
+Wire Wire Line
+ 21050 22450 20850 22450
+Wire Wire Line
+ 20800 22350 20800 22250
+Wire Wire Line
+ 20800 22250 20850 22250
+Wire Wire Line
+ 20200 22100 20200 22450
+Wire Wire Line
+ 19700 22300 20200 22300
+Connection ~ 20200 22300
+Wire Wire Line
+ 21050 22250 21650 22250
+Connection ~ 21050 22250
+Wire Wire Line
+ 20450 23700 20250 23700
+Wire Wire Line
+ 20250 23700 20250 24150
+Wire Wire Line
+ 20250 24150 20450 24150
+Wire Wire Line
+ 20850 24150 20950 24150
+Wire Wire Line
+ 20950 24150 20950 23700
+Wire Wire Line
+ 20950 23700 20850 23700
+Wire Wire Line
+ 20750 23900 20700 23900
+Wire Wire Line
+ 20700 23900 20700 24000
+Wire Wire Line
+ 20700 24000 20800 24000
+Wire Wire Line
+ 20800 24000 20800 24050
+Wire Wire Line
+ 20450 23950 20450 23800
+Wire Wire Line
+ 20450 23800 20500 23800
+Connection ~ 20950 24000
+Wire Wire Line
+ 17700 23950 20250 23950
+Connection ~ 20250 23950
+Wire Wire Line
+ 20650 22750 20650 23400
+Wire Wire Line
+ 21200 22250 21200 24000
+Wire Wire Line
+ 21200 24000 20950 24000
+Wire Wire Line
+ 18550 22300 18150 22300
+Wire Wire Line
+ 17550 22300 17550 22850
+Wire Wire Line
+ 17700 23950 17700 24000
+Wire Wire Line
+ 17700 24000 17550 24000
+Wire Wire Line
+ 21650 22250 21650 22300
+Connection ~ 21200 22250
+Wire Wire Line
+ 22800 22300 23550 22300
+Wire Wire Line
+ 23550 22300 23550 22200
+Wire Wire Line
+ 23550 22200 23700 22200
+Wire Wire Line
+ 24300 22200 24650 22200
+Wire Wire Line
+ 25250 22200 25650 22200
+Wire Wire Line
+ 24450 22200 24450 23350
+Wire Wire Line
+ 24450 23350 25700 23350
+Connection ~ 24450 22200
+Wire Wire Line
+ 26800 22200 26800 21100
+Wire Wire Line
+ 26800 21100 18850 21100
+Wire Wire Line
+ 18850 21100 18850 19800
+Wire Wire Line
+ 17650 15450 17650 17550
+Wire Wire Line
+ 17650 17400 16550 17400
+Wire Wire Line
+ 16550 17400 16550 20050
+Wire Wire Line
+ 16550 20050 18850 20050
+Connection ~ 18850 20050
+Wire Wire Line
+ 16100 15450 18500 15450
+Wire Wire Line
+ 18500 15450 18500 15150
+Connection ~ 17650 17400
+Wire Wire Line
+ 16100 15450 16100 12850
+Wire Wire Line
+ 16100 12850 17300 12850
+Wire Wire Line
+ 17300 10450 17300 12900
+Connection ~ 17650 15450
+Wire Wire Line
+ 15500 10450 18400 10450
+Wire Wire Line
+ 18400 10450 18400 10350
+Connection ~ 17300 12850
+Wire Wire Line
+ 15500 10450 15500 8100
+Wire Wire Line
+ 15500 8100 17200 8100
+Connection ~ 17300 10450
+Wire Wire Line
+ 17200 8100 17200 6850
+Wire Wire Line
+ 15900 6850 18250 6850
+Wire Wire Line
+ 18250 6850 18250 6750
+Wire Wire Line
+ 15900 6850 15900 4500
+Wire Wire Line
+ 15900 4500 17050 4500
+Connection ~ 17200 6850
+Wire Wire Line
+ 15500 18850 27550 18850
+Wire Wire Line
+ 27550 18850 27550 23450
+Wire Wire Line
+ 27550 23450 27000 23450
+Wire Wire Line
+ 27000 23450 27000 23350
+Wire Wire Line
+ 27000 23350 26850 23350
+Wire Wire Line
+ 17650 18850 17650 18600
+Connection ~ 18850 18850
+Wire Wire Line
+ 15500 12000 15500 18850
+Wire Wire Line
+ 15500 13950 18500 13950
+Connection ~ 17650 18850
+Wire Wire Line
+ 18500 13950 18500 14200
+Connection ~ 17300 13950
+Wire Wire Line
+ 13900 12000 15500 12000
+Wire Wire Line
+ 13900 5550 13900 12000
+Wire Wire Line
+ 13900 9150 18400 9150
+Connection ~ 15500 13950
+Wire Wire Line
+ 18400 9150 18400 9400
+Connection ~ 17200 9150
+Wire Wire Line
+ 13900 5550 18250 5550
+Connection ~ 13900 9150
+Wire Wire Line
+ 18250 5550 18250 5800
+Connection ~ 17050 5550
+Wire Wire Line
+ 16650 22300 17550 22300
+Wire Wire Line
+ 19600 26350 19800 26350
+Wire Wire Line
+ 17850 26350 19000 26350
+Wire Wire Line
+ 16600 26350 17250 26350
+Wire Wire Line
+ 20950 26350 21300 26350
+Wire Wire Line
+ 22450 26350 22450 25300
+Wire Wire Line
+ 22450 25300 19200 25300
+Wire Wire Line
+ 19200 25300 19200 23050
+Wire Wire Line
+ 19200 23050 20650 23050
+Connection ~ 20650 23050
+Wire Wire Line
+ 18300 26850 18300 26350
+Connection ~ 18300 26350
+Wire Wire Line
+ 18300 28000 23600 28000
+Wire Wire Line
+ 23600 28000 23600 24450
+Wire Wire Line
+ 23600 24450 20650 24450
+Wire Wire Line
+ 20650 21800 20650 21600
+Wire Wire Line
+ 20650 21600 22150 21600
+Wire Wire Line
+ 22150 21600 22150 24450
+Connection ~ 22150 24450
+Wire Wire Line
+ 12300 4350 12600 4350
+Wire Wire Line
+ 12650 4550 12300 4550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B.sub b/library/SubcircuitLibrary/HCF4042B/HCF4042B.sub
new file mode 100644
index 00000000..cef2b4db
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B.sub
@@ -0,0 +1,208 @@
+* Subcircuit HCF4042B
+.subckt HCF4042B net-_m1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_m4-pad1_ net-_u1-pad8_ net-_u1-pad9_ net-_m7-pad1_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ vdd vss
+* c:\fossee\esim\library\subcircuitlibrary\hcf4042b\hcf4042b.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m3 net-_m1-pad3_ net-_m10-pad2_ net-_m1-pad1_ vss CMOSN W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+m9 net-_m1-pad3_ net-_m10-pad2_ net-_m11-pad1_ vss CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+* u6 net-_m1-pad3_ net-_u13-pad1_ adc_bridge_1
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u36 net-_u29-pad2_ net-_u1-pad2_ d_buffer
+* u19 net-_u13-pad2_ net-_u19-pad2_ d_inverter
+* u20 net-_u19-pad2_ net-_u12-pad2_ d_buffer
+* u12 net-_m11-pad1_ net-_u12-pad2_ adc_bridge_1
+* u32 net-_u12-pad2_ net-_u1-pad3_ d_inverter
+m5 net-_m10-pad1_ net-_m10-pad2_ net-_m2-pad1_ vss CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1
+m13 net-_m10-pad3_ net-_m1-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1
+* u7 net-_m10-pad1_ net-_u16-pad1_ adc_bridge_1
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u30 net-_u16-pad2_ net-_u30-pad2_ d_inverter
+* u39 net-_u30-pad2_ net-_u1-pad5_ d_buffer
+* u22 net-_u16-pad2_ net-_u22-pad2_ d_inverter
+* u23 net-_u22-pad2_ net-_u14-pad2_ d_buffer
+* u14 net-_m10-pad3_ net-_u14-pad2_ adc_bridge_1
+* u33 net-_u14-pad2_ net-_u1-pad6_ d_inverter
+m6 net-_m12-pad1_ net-_m10-pad2_ net-_m4-pad1_ vss CMOSN W=100u L=100u M=1
+m4 net-_m4-pad1_ net-_m1-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m10-pad2_ net-_m12-pad3_ vss CMOSN W=100u L=100u M=1
+m14 net-_m12-pad3_ net-_m1-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1
+* u8 net-_m12-pad1_ net-_u17-pad1_ adc_bridge_1
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u31 net-_u17-pad2_ net-_u31-pad2_ d_inverter
+* u40 net-_u31-pad2_ net-_u1-pad8_ d_buffer
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u26 net-_u25-pad2_ net-_u15-pad2_ d_buffer
+* u15 net-_m12-pad3_ net-_u15-pad2_ adc_bridge_1
+* u35 net-_u15-pad2_ net-_u1-pad9_ d_inverter
+m8 net-_m15-pad1_ net-_m10-pad2_ net-_m7-pad1_ vss CMOSN W=100u L=100u M=1
+m7 net-_m7-pad1_ net-_m1-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m15 net-_m15-pad1_ net-_m10-pad2_ net-_m15-pad3_ vss CMOSN W=100u L=100u M=1
+m16 net-_m15-pad3_ net-_m1-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+* u9 net-_m15-pad1_ net-_u21-pad1_ adc_bridge_1
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u34 net-_u21-pad2_ net-_u34-pad2_ d_inverter
+* u42 net-_u34-pad2_ net-_u1-pad11_ d_buffer
+* u27 net-_u21-pad2_ net-_u27-pad2_ d_inverter
+* u28 net-_u27-pad2_ net-_u18-pad2_ d_buffer
+* u18 net-_m15-pad3_ net-_u18-pad2_ adc_bridge_1
+* u37 net-_u18-pad2_ net-_u1-pad12_ d_inverter
+* u4 net-_u1-pad13_ net-_u10-pad1_ d_inverter
+m17 net-_m17-pad1_ net-_m17-pad2_ net-_m17-pad3_ vss CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m18-pad2_ net-_m17-pad1_ vdd CMOSP W=100u L=100u M=1
+m20 net-_m17-pad3_ net-_m17-pad2_ net-_m19-pad1_ vss CMOSN W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m18-pad2_ net-_m17-pad3_ vdd CMOSP W=100u L=100u M=1
+* u10 net-_u10-pad1_ net-_m17-pad1_ dac_bridge_1
+* u2 net-_u1-pad13_ net-_m19-pad1_ dac_bridge_1
+* u44 net-_u43-pad2_ net-_u44-pad2_ d_inverter
+* u43 net-_u41-pad2_ net-_u43-pad2_ d_inverter
+* u41 net-_m17-pad3_ net-_u41-pad2_ adc_bridge_1
+* u45 net-_u44-pad2_ net-_m10-pad2_ dac_bridge_1
+* u46 net-_u43-pad2_ net-_m1-pad2_ dac_bridge_1
+* u3 net-_u1-pad14_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u24 net-_u11-pad2_ net-_u24-pad2_ d_buffer
+* u38 net-_u24-pad2_ net-_m17-pad2_ dac_bridge_1
+* u5 net-_u11-pad1_ net-_m18-pad2_ dac_bridge_1
+a1 [net-_m1-pad3_ ] [net-_u13-pad1_ ] u6
+a2 net-_u13-pad1_ net-_u13-pad2_ u13
+a3 net-_u13-pad2_ net-_u29-pad2_ u29
+a4 net-_u29-pad2_ net-_u1-pad2_ u36
+a5 net-_u13-pad2_ net-_u19-pad2_ u19
+a6 net-_u19-pad2_ net-_u12-pad2_ u20
+a7 [net-_m11-pad1_ ] [net-_u12-pad2_ ] u12
+a8 net-_u12-pad2_ net-_u1-pad3_ u32
+a9 [net-_m10-pad1_ ] [net-_u16-pad1_ ] u7
+a10 net-_u16-pad1_ net-_u16-pad2_ u16
+a11 net-_u16-pad2_ net-_u30-pad2_ u30
+a12 net-_u30-pad2_ net-_u1-pad5_ u39
+a13 net-_u16-pad2_ net-_u22-pad2_ u22
+a14 net-_u22-pad2_ net-_u14-pad2_ u23
+a15 [net-_m10-pad3_ ] [net-_u14-pad2_ ] u14
+a16 net-_u14-pad2_ net-_u1-pad6_ u33
+a17 [net-_m12-pad1_ ] [net-_u17-pad1_ ] u8
+a18 net-_u17-pad1_ net-_u17-pad2_ u17
+a19 net-_u17-pad2_ net-_u31-pad2_ u31
+a20 net-_u31-pad2_ net-_u1-pad8_ u40
+a21 net-_u17-pad2_ net-_u25-pad2_ u25
+a22 net-_u25-pad2_ net-_u15-pad2_ u26
+a23 [net-_m12-pad3_ ] [net-_u15-pad2_ ] u15
+a24 net-_u15-pad2_ net-_u1-pad9_ u35
+a25 [net-_m15-pad1_ ] [net-_u21-pad1_ ] u9
+a26 net-_u21-pad1_ net-_u21-pad2_ u21
+a27 net-_u21-pad2_ net-_u34-pad2_ u34
+a28 net-_u34-pad2_ net-_u1-pad11_ u42
+a29 net-_u21-pad2_ net-_u27-pad2_ u27
+a30 net-_u27-pad2_ net-_u18-pad2_ u28
+a31 [net-_m15-pad3_ ] [net-_u18-pad2_ ] u18
+a32 net-_u18-pad2_ net-_u1-pad12_ u37
+a33 net-_u1-pad13_ net-_u10-pad1_ u4
+a34 [net-_u10-pad1_ ] [net-_m17-pad1_ ] u10
+a35 [net-_u1-pad13_ ] [net-_m19-pad1_ ] u2
+a36 net-_u43-pad2_ net-_u44-pad2_ u44
+a37 net-_u41-pad2_ net-_u43-pad2_ u43
+a38 [net-_m17-pad3_ ] [net-_u41-pad2_ ] u41
+a39 [net-_u44-pad2_ ] [net-_m10-pad2_ ] u45
+a40 [net-_u43-pad2_ ] [net-_m1-pad2_ ] u46
+a41 net-_u1-pad14_ net-_u11-pad1_ u3
+a42 net-_u11-pad1_ net-_u11-pad2_ u11
+a43 net-_u11-pad2_ net-_u24-pad2_ u24
+a44 [net-_u24-pad2_ ] [net-_m17-pad2_ ] u38
+a45 [net-_u11-pad1_ ] [net-_m18-pad2_ ] u5
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u42 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u28 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u41 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u45 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u46 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends HCF4042B \ No newline at end of file
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B_Previous_Values.xml b/library/SubcircuitLibrary/HCF4042B/HCF4042B_Previous_Values.xml
new file mode 100644
index 00000000..f375c3af
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u6 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u6><u13 name="type">d_inverter<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u13><u29 name="type">d_inverter<field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter Input Load (default=1.0e-12)" /></u29><u36 name="type">d_buffer<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u36><u19 name="type">d_inverter<field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_buffer<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u20><u12 name="type">adc_bridge<field20 name="Enter value for in_low (default=1.0)" /><field21 name="Enter value for in_high (default=2.0)" /><field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /></u12><u32 name="type">d_inverter<field24 name="Enter Rise Delay (default=1.0e-9)" /><field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /></u32><u7 name="type">adc_bridge<field27 name="Enter value for in_low (default=1.0)" /><field28 name="Enter value for in_high (default=2.0)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u7><u16 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u16><u30 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u30><u39 name="type">d_buffer<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u39><u22 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_buffer<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u23><u14 name="type">adc_bridge<field46 name="Enter value for in_low (default=1.0)" /><field47 name="Enter value for in_high (default=2.0)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /><field49 name="Enter Fall Delay (default=1.0e-9)" /></u14><u33 name="type">d_inverter<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u33><u8 name="type">adc_bridge<field53 name="Enter value for in_low (default=1.0)" /><field54 name="Enter value for in_high (default=2.0)" /><field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /></u8><u17 name="type">d_inverter<field57 name="Enter Rise Delay (default=1.0e-9)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /></u17><u31 name="type">d_inverter<field60 name="Enter Rise Delay (default=1.0e-9)" /><field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /></u31><u40 name="type">d_buffer<field63 name="Enter Rise Delay (default=1.0e-9)" /><field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /></u40><u25 name="type">d_inverter<field66 name="Enter Rise Delay (default=1.0e-9)" /><field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_buffer<field69 name="Enter Rise Delay (default=1.0e-9)" /><field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /></u26><u15 name="type">adc_bridge<field72 name="Enter value for in_low (default=1.0)" /><field73 name="Enter value for in_high (default=2.0)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /></u15><u35 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u35><u9 name="type">adc_bridge<field79 name="Enter value for in_low (default=1.0)" /><field80 name="Enter value for in_high (default=2.0)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /><field82 name="Enter Fall Delay (default=1.0e-9)" /></u9><u21 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u21><u34 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u34><u42 name="type">d_buffer<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u42><u27 name="type">d_inverter<field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_buffer<field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /></u28><u18 name="type">adc_bridge<field98 name="Enter value for in_low (default=1.0)" /><field99 name="Enter value for in_high (default=2.0)" /><field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /></u18><u37 name="type">d_inverter<field102 name="Enter Rise Delay (default=1.0e-9)" /><field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /></u37><u4 name="type">d_inverter<field105 name="Enter Rise Delay (default=1.0e-9)" /><field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /></u4><u10 name="type">dac_bridge<field108 name="Enter value for out_low (default=0.0)" /><field109 name="Enter value for out_high (default=5.0)" /><field110 name="Enter value for out_undef (default=0.5)" /><field111 name="Enter value for input load (default=1.0e-12)" /><field112 name="Enter the Rise Time (default=1.0e-9)" /><field113 name="Enter the Fall Time (default=1.0e-9)" /></u10><u2 name="type">dac_bridge<field114 name="Enter value for out_low (default=0.0)" /><field115 name="Enter value for out_high (default=5.0)" /><field116 name="Enter value for out_undef (default=0.5)" /><field117 name="Enter value for input load (default=1.0e-12)" /><field118 name="Enter the Rise Time (default=1.0e-9)" /><field119 name="Enter the Fall Time (default=1.0e-9)" /></u2><u44 name="type">d_inverter<field120 name="Enter Rise Delay (default=1.0e-9)" /><field121 name="Enter Fall Delay (default=1.0e-9)" /><field122 name="Enter Input Load (default=1.0e-12)" /></u44><u43 name="type">d_inverter<field123 name="Enter Rise Delay (default=1.0e-9)" /><field124 name="Enter Fall Delay (default=1.0e-9)" /><field125 name="Enter Input Load (default=1.0e-12)" /></u43><u41 name="type">adc_bridge<field126 name="Enter value for in_low (default=1.0)" /><field127 name="Enter value for in_high (default=2.0)" /><field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /></u41><u45 name="type">dac_bridge<field130 name="Enter value for out_low (default=0.0)" /><field131 name="Enter value for out_high (default=5.0)" /><field132 name="Enter value for out_undef (default=0.5)" /><field133 name="Enter value for input load (default=1.0e-12)" /><field134 name="Enter the Rise Time (default=1.0e-9)" /><field135 name="Enter the Fall Time (default=1.0e-9)" /></u45><u46 name="type">dac_bridge<field136 name="Enter value for out_low (default=0.0)" /><field137 name="Enter value for out_high (default=5.0)" /><field138 name="Enter value for out_undef (default=0.5)" /><field139 name="Enter value for input load (default=1.0e-12)" /><field140 name="Enter the Rise Time (default=1.0e-9)" /><field141 name="Enter the Fall Time (default=1.0e-9)" /></u46><u3 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u3><u11 name="type">d_inverter<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u11><u24 name="type">d_buffer<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u24><u38 name="type">dac_bridge<field151 name="Enter value for out_low (default=0.0)" /><field152 name="Enter value for out_high (default=5.0)" /><field153 name="Enter value for out_undef (default=0.5)" /><field154 name="Enter value for input load (default=1.0e-12)" /><field155 name="Enter the Rise Time (default=1.0e-9)" /><field156 name="Enter the Fall Time (default=1.0e-9)" /></u38><u5 name="type">dac_bridge<field157 name="Enter value for out_low (default=0.0)" /><field158 name="Enter value for out_high (default=5.0)" /><field159 name="Enter value for out_undef (default=0.5)" /><field160 name="Enter value for input load (default=1.0e-12)" /><field161 name="Enter the Rise Time (default=1.0e-9)" /><field162 name="Enter the Fall Time (default=1.0e-9)" /></u5></model><devicemodel><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m1><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m13><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m14><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m15><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m17><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m18><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m20><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m19></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/HCF4042B/NMOS-180nm.lib b/library/SubcircuitLibrary/HCF4042B/NMOS-180nm.lib
new file mode 100644
index 00000000..51e9b119
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3
++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286
++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078
++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/HCF4042B/PMOS-180nm.lib b/library/SubcircuitLibrary/HCF4042B/PMOS-180nm.lib
new file mode 100644
index 00000000..032b5b95
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9
++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3
++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/HCF4042B/analysis b/library/SubcircuitLibrary/HCF4042B/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/HCF4042B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-07-05 01:32:47 +0000