diff options
Diffstat (limited to 'library')
229 files changed, 20467 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74F350/3_and-cache.lib b/library/SubcircuitLibrary/74F350/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/3_and.cir b/library/SubcircuitLibrary/74F350/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.cir.out b/library/SubcircuitLibrary/74F350/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.pro b/library/SubcircuitLibrary/74F350/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/3_and.sch b/library/SubcircuitLibrary/74F350/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/3_and.sub b/library/SubcircuitLibrary/74F350/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350-cache.lib b/library/SubcircuitLibrary/74F350/74F350-cache.lib new file mode 100644 index 00000000..8256d8a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350-cache.lib @@ -0,0 +1,112 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/74F350.cir b/library/SubcircuitLibrary/74F350/74F350.cir new file mode 100644 index 00000000..87560c28 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir @@ -0,0 +1,48 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\74F350\74F350.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:58:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X16 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad7_ Net-_U16-Pad1_ 3_and +X15 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U16-Pad2_ 3_and +X14 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad5_ Net-_U13-Pad1_ 3_and +X13 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U13-Pad2_ 3_and +X12 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U12-Pad1_ 3_and +X11 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U12-Pad2_ 3_and +X10 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U9-Pad1_ 3_and +X9 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U9-Pad2_ 3_and +X8 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U8-Pad1_ 3_and +X7 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U8-Pad2_ 3_and +X6 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U6-Pad1_ 3_and +X5 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U6-Pad2_ 3_and +X4 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad1_ 3_and +X3 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad2_ 3_and +X2 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U2-Pad1_ 3_and +X1 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad1_ Net-_U2-Pad2_ 3_and +U26 Net-_U1-Pad13_ Net-_U10-Pad1_ d_inverter +U24 Net-_U1-Pad10_ Net-_U24-Pad2_ d_inverter +U22 Net-_U1-Pad9_ Net-_U22-Pad2_ d_inverter +U25 Net-_U24-Pad2_ Net-_U25-Pad2_ d_inverter +U23 Net-_U22-Pad2_ Net-_U23-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U20 Net-_U10-Pad1_ Net-_U14-Pad3_ Net-_U1-Pad15_ d_and +U15 Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U1-Pad14_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad12_ d_and +U5 Net-_U10-Pad1_ Net-_U3-Pad3_ Net-_U1-Pad11_ d_and +U14 Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U7 Net-_U7-Pad1_ Net-_U6-Pad3_ Net-_U10-Pad2_ d_or +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U14-Pad1_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad1_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U11-Pad2_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U7-Pad1_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ d_or +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_or +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.cir.out b/library/SubcircuitLibrary/74F350/74F350.cir.out new file mode 100644 index 00000000..b90caa5e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir.out @@ -0,0 +1,113 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir + +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.pro b/library/SubcircuitLibrary/74F350/74F350.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/74F350.sch b/library/SubcircuitLibrary/74F350/74F350.sch new file mode 100644 index 00000000..989985a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sch @@ -0,0 +1,1000 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:74F350-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X16 +U 1 1 679DB336 +P 15400 7400 +F 0 "X16" H 15500 7350 60 0000 C CNN +F 1 "3_and" H 15550 7550 60 0000 C CNN +F 2 "" H 15400 7400 60 0000 C CNN +F 3 "" H 15400 7400 60 0000 C CNN + 1 15400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X15 +U 1 1 679DB473 +P 14650 7400 +F 0 "X15" H 14750 7350 60 0000 C CNN +F 1 "3_and" H 14800 7550 60 0000 C CNN +F 2 "" H 14650 7400 60 0000 C CNN +F 3 "" H 14650 7400 60 0000 C CNN + 1 14650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X14 +U 1 1 679DB4EB +P 14050 7400 +F 0 "X14" H 14150 7350 60 0000 C CNN +F 1 "3_and" H 14200 7550 60 0000 C CNN +F 2 "" H 14050 7400 60 0000 C CNN +F 3 "" H 14050 7400 60 0000 C CNN + 1 14050 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X13 +U 1 1 679DB4F1 +P 13300 7400 +F 0 "X13" H 13400 7350 60 0000 C CNN +F 1 "3_and" H 13450 7550 60 0000 C CNN +F 2 "" H 13300 7400 60 0000 C CNN +F 3 "" H 13300 7400 60 0000 C CNN + 1 13300 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X12 +U 1 1 679DB5C3 +P 12750 7400 +F 0 "X12" H 12850 7350 60 0000 C CNN +F 1 "3_and" H 12900 7550 60 0000 C CNN +F 2 "" H 12750 7400 60 0000 C CNN +F 3 "" H 12750 7400 60 0000 C CNN + 1 12750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X11 +U 1 1 679DB5C9 +P 12000 7400 +F 0 "X11" H 12100 7350 60 0000 C CNN +F 1 "3_and" H 12150 7550 60 0000 C CNN +F 2 "" H 12000 7400 60 0000 C CNN +F 3 "" H 12000 7400 60 0000 C CNN + 1 12000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X10 +U 1 1 679DB5CF +P 11400 7400 +F 0 "X10" H 11500 7350 60 0000 C CNN +F 1 "3_and" H 11550 7550 60 0000 C CNN +F 2 "" H 11400 7400 60 0000 C CNN +F 3 "" H 11400 7400 60 0000 C CNN + 1 11400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X9 +U 1 1 679DB5D5 +P 10650 7400 +F 0 "X9" H 10750 7350 60 0000 C CNN +F 1 "3_and" H 10800 7550 60 0000 C CNN +F 2 "" H 10650 7400 60 0000 C CNN +F 3 "" H 10650 7400 60 0000 C CNN + 1 10650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X8 +U 1 1 679DB885 +P 10100 7400 +F 0 "X8" H 10200 7350 60 0000 C CNN +F 1 "3_and" H 10250 7550 60 0000 C CNN +F 2 "" H 10100 7400 60 0000 C CNN +F 3 "" H 10100 7400 60 0000 C CNN + 1 10100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X7 +U 1 1 679DB88B +P 9350 7400 +F 0 "X7" H 9450 7350 60 0000 C CNN +F 1 "3_and" H 9500 7550 60 0000 C CNN +F 2 "" H 9350 7400 60 0000 C CNN +F 3 "" H 9350 7400 60 0000 C CNN + 1 9350 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X6 +U 1 1 679DB891 +P 8750 7400 +F 0 "X6" H 8850 7350 60 0000 C CNN +F 1 "3_and" H 8900 7550 60 0000 C CNN +F 2 "" H 8750 7400 60 0000 C CNN +F 3 "" H 8750 7400 60 0000 C CNN + 1 8750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X5 +U 1 1 679DB897 +P 8000 7400 +F 0 "X5" H 8100 7350 60 0000 C CNN +F 1 "3_and" H 8150 7550 60 0000 C CNN +F 2 "" H 8000 7400 60 0000 C CNN +F 3 "" H 8000 7400 60 0000 C CNN + 1 8000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X4 +U 1 1 679DB89D +P 7450 7400 +F 0 "X4" H 7550 7350 60 0000 C CNN +F 1 "3_and" H 7600 7550 60 0000 C CNN +F 2 "" H 7450 7400 60 0000 C CNN +F 3 "" H 7450 7400 60 0000 C CNN + 1 7450 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X3 +U 1 1 679DB8A3 +P 6700 7400 +F 0 "X3" H 6800 7350 60 0000 C CNN +F 1 "3_and" H 6850 7550 60 0000 C CNN +F 2 "" H 6700 7400 60 0000 C CNN +F 3 "" H 6700 7400 60 0000 C CNN + 1 6700 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X2 +U 1 1 679DB8A9 +P 6100 7400 +F 0 "X2" H 6200 7350 60 0000 C CNN +F 1 "3_and" H 6250 7550 60 0000 C CNN +F 2 "" H 6100 7400 60 0000 C CNN +F 3 "" H 6100 7400 60 0000 C CNN + 1 6100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X1 +U 1 1 679DB8AF +P 5350 7400 +F 0 "X1" H 5450 7350 60 0000 C CNN +F 1 "3_and" H 5500 7550 60 0000 C CNN +F 2 "" H 5350 7400 60 0000 C CNN +F 3 "" H 5350 7400 60 0000 C CNN + 1 5350 7400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U26 +U 1 1 679DBBC7 +P 17700 3200 +F 0 "U26" H 17700 3100 60 0000 C CNN +F 1 "d_inverter" H 17700 3350 60 0000 C CNN +F 2 "" H 17750 3150 60 0000 C CNN +F 3 "" H 17750 3150 60 0000 C CNN + 1 17700 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 679DBC88 +P 16900 3200 +F 0 "U24" H 16900 3100 60 0000 C CNN +F 1 "d_inverter" H 16900 3350 60 0000 C CNN +F 2 "" H 16950 3150 60 0000 C CNN +F 3 "" H 16950 3150 60 0000 C CNN + 1 16900 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U22 +U 1 1 679DBCDF +P 16150 3200 +F 0 "U22" H 16150 3100 60 0000 C CNN +F 1 "d_inverter" H 16150 3350 60 0000 C CNN +F 2 "" H 16200 3150 60 0000 C CNN +F 3 "" H 16200 3150 60 0000 C CNN + 1 16150 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U25 +U 1 1 679DBD6D +P 16900 4200 +F 0 "U25" H 16900 4100 60 0000 C CNN +F 1 "d_inverter" H 16900 4350 60 0000 C CNN +F 2 "" H 16950 4150 60 0000 C CNN +F 3 "" H 16950 4150 60 0000 C CNN + 1 16900 4200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U23 +U 1 1 679DBD73 +P 16150 4200 +F 0 "U23" H 16150 4100 60 0000 C CNN +F 1 "d_inverter" H 16150 4350 60 0000 C CNN +F 2 "" H 16200 4150 60 0000 C CNN +F 3 "" H 16200 4150 60 0000 C CNN + 1 16150 4200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 679EA80D +P 17700 2050 +F 0 "U1" H 17750 2150 30 0000 C CNN +F 1 "PORT" H 17700 2050 30 0000 C CNN +F 2 "" H 17700 2050 60 0000 C CNN +F 3 "" H 17700 2050 60 0000 C CNN + 13 17700 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 679EAA26 +P 16900 2050 +F 0 "U1" H 16950 2150 30 0000 C CNN +F 1 "PORT" H 16900 2050 30 0000 C CNN +F 2 "" H 16900 2050 60 0000 C CNN +F 3 "" H 16900 2050 60 0000 C CNN + 10 16900 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 679EAAAF +P 16150 2100 +F 0 "U1" H 16200 2200 30 0000 C CNN +F 1 "PORT" H 16150 2100 30 0000 C CNN +F 2 "" H 16150 2100 60 0000 C CNN +F 3 "" H 16150 2100 60 0000 C CNN + 9 16150 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 679EAB54 +P 15350 2150 +F 0 "U1" H 15400 2250 30 0000 C CNN +F 1 "PORT" H 15350 2150 30 0000 C CNN +F 2 "" H 15350 2150 60 0000 C CNN +F 3 "" H 15350 2150 60 0000 C CNN + 7 15350 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 679EAD32 +P 14600 2150 +F 0 "U1" H 14650 2250 30 0000 C CNN +F 1 "PORT" H 14600 2150 30 0000 C CNN +F 2 "" H 14600 2150 60 0000 C CNN +F 3 "" H 14600 2150 60 0000 C CNN + 6 14600 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 679EAD38 +P 14000 2150 +F 0 "U1" H 14050 2250 30 0000 C CNN +F 1 "PORT" H 14000 2150 30 0000 C CNN +F 2 "" H 14000 2150 60 0000 C CNN +F 3 "" H 14000 2150 60 0000 C CNN + 5 14000 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 679EAD3E +P 13250 2150 +F 0 "U1" H 13300 2250 30 0000 C CNN +F 1 "PORT" H 13250 2150 30 0000 C CNN +F 2 "" H 13250 2150 60 0000 C CNN +F 3 "" H 13250 2150 60 0000 C CNN + 4 13250 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 679EB065 +P 10600 2300 +F 0 "U1" H 10650 2400 30 0000 C CNN +F 1 "PORT" H 10600 2300 30 0000 C CNN +F 2 "" H 10600 2300 60 0000 C CNN +F 3 "" H 10600 2300 60 0000 C CNN + 3 10600 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 679EB06B +P 7950 2200 +F 0 "U1" H 8000 2300 30 0000 C CNN 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+F 3 "" H 11900 12050 60 0000 C CNN + 1 11900 12050 + 0 1 1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 679F0140 +P 9200 12200 +F 0 "U10" H 9200 12200 60 0000 C CNN +F 1 "d_and" H 9250 12300 60 0000 C CNN +F 2 "" H 9200 12200 60 0000 C CNN +F 3 "" H 9200 12200 60 0000 C CNN + 1 9200 12200 + 0 1 1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 679F01D7 +P 6550 12200 +F 0 "U5" H 6550 12200 60 0000 C CNN +F 1 "d_and" H 6600 12300 60 0000 C CNN +F 2 "" H 6550 12200 60 0000 C CNN +F 3 "" H 6550 12200 60 0000 C CNN + 1 6550 12200 + 0 1 1 0 +$EndComp +Wire Wire Line + 6600 12750 6600 12650 +Wire Wire Line + 9250 12700 9250 12650 +Wire Wire Line + 17700 11300 15050 11300 +Wire Wire Line + 15050 10850 15050 11600 +Wire Wire Line + 15050 11600 14650 11600 +Wire Wire Line + 7100 10850 15050 10850 +Wire Wire Line + 12300 11600 12000 11600 +Connection ~ 15050 11300 +Wire Wire Line + 9950 11750 9300 11750 +Connection ~ 12300 10850 +Wire Wire Line + 7100 11750 6650 11750 +Connection ~ 9950 10850 +$Comp +L d_or U14 +U 1 1 67A37333 +P 14500 10350 +F 0 "U14" H 14500 10350 60 0000 C CNN +F 1 "d_or" H 14500 10450 60 0000 C CNN +F 2 "" H 14500 10350 60 0000 C CNN +F 3 "" H 14500 10350 60 0000 C CNN + 1 14500 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U11 +U 1 1 67A375DC +P 11850 10350 +F 0 "U11" H 11850 10350 60 0000 C CNN +F 1 "d_or" H 11850 10450 60 0000 C CNN +F 2 "" H 11850 10350 60 0000 C CNN +F 3 "" H 11850 10350 60 0000 C CNN + 1 11850 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U7 +U 1 1 67A376D5 +P 9150 10450 +F 0 "U7" H 9150 10450 60 0000 C CNN +F 1 "d_or" H 9150 10550 60 0000 C CNN +F 2 "" H 9150 10450 60 0000 C CNN +F 3 "" H 9150 10450 60 0000 C CNN + 1 9150 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U3 +U 1 1 67A377D6 +P 6500 10450 +F 0 "U3" H 6500 10450 60 0000 C CNN +F 1 "d_or" H 6500 10550 60 0000 C CNN +F 2 "" H 6500 10450 60 0000 C CNN +F 3 "" H 6500 10450 60 0000 C CNN + 1 6500 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U16 +U 1 1 67A37A21 +P 15150 8950 +F 0 "U16" H 15150 8950 60 0000 C CNN +F 1 "d_or" H 15150 9050 60 0000 C CNN +F 2 "" H 15150 8950 60 0000 C CNN +F 3 "" H 15150 8950 60 0000 C CNN + 1 15150 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U13 +U 1 1 67A37ADA +P 13700 8950 +F 0 "U13" H 13700 8950 60 0000 C CNN +F 1 "d_or" H 13700 9050 60 0000 C CNN +F 2 "" H 13700 8950 60 0000 C CNN +F 3 "" H 13700 8950 60 0000 C CNN + 1 13700 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U12 +U 1 1 67A37C7D +P 12500 8950 +F 0 "U12" H 12500 8950 60 0000 C CNN +F 1 "d_or" H 12500 9050 60 0000 C CNN +F 2 "" H 12500 8950 60 0000 C CNN +F 3 "" H 12500 8950 60 0000 C CNN + 1 12500 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U9 +U 1 1 67A37CFE +P 11050 8950 +F 0 "U9" H 11050 8950 60 0000 C CNN +F 1 "d_or" H 11050 9050 60 0000 C CNN +F 2 "" H 11050 8950 60 0000 C CNN +F 3 "" H 11050 8950 60 0000 C CNN + 1 11050 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U8 +U 1 1 67A37DF9 +P 9800 9050 +F 0 "U8" H 9800 9050 60 0000 C CNN +F 1 "d_or" H 9800 9150 60 0000 C CNN +F 2 "" H 9800 9050 60 0000 C CNN +F 3 "" H 9800 9050 60 0000 C CNN + 1 9800 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U6 +U 1 1 67A37FCE +P 8350 9050 +F 0 "U6" H 8350 9050 60 0000 C CNN +F 1 "d_or" H 8350 9150 60 0000 C CNN +F 2 "" H 8350 9050 60 0000 C CNN +F 3 "" H 8350 9050 60 0000 C CNN + 1 8350 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U4 +U 1 1 67A38059 +P 7150 9050 +F 0 "U4" H 7150 9050 60 0000 C CNN +F 1 "d_or" H 7150 9150 60 0000 C CNN +F 2 "" H 7150 9050 60 0000 C CNN +F 3 "" H 7150 9050 60 0000 C CNN + 1 7150 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U2 +U 1 1 67A38154 +P 5700 9050 +F 0 "U2" H 5700 9050 60 0000 C CNN +F 1 "d_or" H 5700 9150 60 0000 C CNN +F 2 "" H 5700 9050 60 0000 C CNN +F 3 "" H 5700 9050 60 0000 C CNN + 1 5700 9050 + 0 1 1 0 +$EndComp +Wire Wire Line + 12300 11600 12300 10850 +Wire Wire Line + 9950 11750 9950 10850 +Wire Wire Line + 7100 10850 7100 11750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/74F350.sub b/library/SubcircuitLibrary/74F350/74F350.sub new file mode 100644 index 00000000..39ba9abb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sub @@ -0,0 +1,107 @@ +* Subcircuit 74F350 +.subckt 74F350 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74F350
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml new file mode 100644 index 00000000..bc7f0ee5 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u26 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u26><u24 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u24><u22 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u22><u25 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u25><u23 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u21 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nor<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u12 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u13><u11 name="type">d_nor<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u11><u7 name="type">d_nor<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_nor<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u6><u2 name="type">d_nor<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nor<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u3><u20 name="type">d_tristate<field52 name="Enter Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Enable Load (default=1.0e-12)" /></u20><u15 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u15><u10 name="type">d_tristate<field58 name="Enter Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Enable Load (default=1.0e-12)" /></u10><u5 name="type">d_tristate<field61 name="Enter Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Enable Load (default=1.0e-12)" /></u5><u4 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u9><u14 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u14><u19 name="type">d_inverter<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u19><u10 name="type">d_nand<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_nand<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_nand<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u4><u20 name="type">d_and<field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u20><u15 name="type">d_and<field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u10><u5 name="type">d_and<field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u5><u14 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u11 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u11><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u3 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u16 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u16><u13 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u13><u12 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u12><u9 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u9><u8 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u8><u6 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_or<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x10><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x15><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x16></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/analysis b/library/SubcircuitLibrary/74F350/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/3_and-cache.lib b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir b/library/SubcircuitLibrary/CD4532B/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir.out b/library/SubcircuitLibrary/CD4532B/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.pro b/library/SubcircuitLibrary/CD4532B/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sch b/library/SubcircuitLibrary/CD4532B/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sub b/library/SubcircuitLibrary/CD4532B/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir b/library/SubcircuitLibrary/CD4532B/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir.out b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.pro b/library/SubcircuitLibrary/CD4532B/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sch b/library/SubcircuitLibrary/CD4532B/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sub b/library/SubcircuitLibrary/CD4532B/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and-cache.lib b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir b/library/SubcircuitLibrary/CD4532B/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir.out b/library/SubcircuitLibrary/CD4532B/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.pro b/library/SubcircuitLibrary/CD4532B/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sch b/library/SubcircuitLibrary/CD4532B/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sub b/library/SubcircuitLibrary/CD4532B/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib new file mode 100644 index 00000000..fbb8d926 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir b/library/SubcircuitLibrary/CD4532B/CD4532B.cir new file mode 100644 index 00000000..cd581690 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir @@ -0,0 +1,54 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\CD4532B\CD4532B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/10/25 20:14:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad11_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U4 Net-_U1-Pad13_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad1_ Net-_U11-Pad1_ d_inverter +U7 Net-_U1-Pad2_ Net-_U12-Pad1_ d_inverter +U8 Net-_U1-Pad3_ Net-_U13-Pad1_ d_inverter +U6 Net-_U1-Pad4_ Net-_U6-Pad2_ d_inverter +U9 Net-_U1-Pad5_ Net-_U14-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +X1 Net-_U2-Pad2_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_X1-Pad5_ 4_OR +X2 Net-_U13-Pad2_ Net-_U11-Pad2_ Net-_U4-Pad2_ ? Net-_X2-Pad5_ 4_OR +X3 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X3-Pad5_ 4_OR +X4 Net-_U4-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X4-Pad5_ 4_OR +U22 Net-_U22-Pad1_ Net-_U16-Pad1_ d_inverter +U23 Net-_U23-Pad1_ Net-_U15-Pad1_ d_inverter +U24 Net-_U16-Pad1_ Net-_U15-Pad1_ Net-_U24-Pad3_ d_nand +X5 Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U19-Pad3_ Net-_U6-Pad2_ Net-_U25-Pad1_ 4_and +X6 Net-_X3-Pad5_ Net-_X4-Pad5_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U27-Pad1_ 4_and +X7 Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U26-Pad1_ 4_and +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U29 Net-_U25-Pad2_ Net-_U14-Pad2_ Net-_U29-Pad3_ d_nand +U30 Net-_U27-Pad2_ Net-_U14-Pad2_ Net-_U30-Pad3_ d_nand +U31 Net-_U26-Pad2_ Net-_U14-Pad2_ Net-_U31-Pad3_ d_nand +U32 Net-_U24-Pad3_ Net-_U1-Pad5_ Net-_U32-Pad3_ d_nand +U34 Net-_U29-Pad3_ Net-_U1-Pad9_ d_inverter +U33 Net-_U30-Pad3_ Net-_U1-Pad7_ d_inverter +U36 Net-_U31-Pad3_ Net-_U1-Pad6_ d_inverter +U37 Net-_U32-Pad3_ Net-_U1-Pad14_ d_inverter +U35 Net-_U20-Pad3_ Net-_U1-Pad15_ d_inverter +U19 Net-_U13-Pad2_ Net-_U12-Pad1_ Net-_U19-Pad3_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +X8 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U22-Pad1_ 4_OR +X9 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U23-Pad1_ 4_OR +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U17 Net-_U1-Pad5_ Net-_U17-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U18 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_or +U20 Net-_U18-Pad3_ Net-_U17-Pad2_ Net-_U20-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out new file mode 100644 index 00000000..40e32465 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out @@ -0,0 +1,159 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.pro b/library/SubcircuitLibrary/CD4532B/CD4532B.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sch b/library/SubcircuitLibrary/CD4532B/CD4532B.sch new file mode 100644 index 00000000..626b76df --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sch @@ -0,0 +1,1074 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid 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"PORT" H 3950 8700 30 0000 C CNN +F 2 "" H 3950 8700 60 0000 C CNN +F 3 "" H 3950 8700 60 0000 C CNN + 3 3950 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67A67BC3 +P 3950 9300 +F 0 "U1" H 4000 9400 30 0000 C CNN +F 1 "PORT" H 3950 9300 30 0000 C CNN +F 2 "" H 3950 9300 60 0000 C CNN +F 3 "" H 3950 9300 60 0000 C CNN + 4 3950 9300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67A67DDA +P 3400 10500 +F 0 "U1" H 3450 10600 30 0000 C CNN +F 1 "PORT" H 3400 10500 30 0000 C CNN +F 2 "" H 3400 10500 60 0000 C CNN +F 3 "" H 3400 10500 60 0000 C CNN + 10 3400 10500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67A67EF9 +P 3200 11450 +F 0 "U1" H 3250 11550 30 0000 C CNN +F 1 "PORT" H 3200 11450 30 0000 C CNN +F 2 "" H 3200 11450 60 0000 C CNN +F 3 "" H 3200 11450 60 0000 C CNN + 5 3200 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67A681F4 +P 18200 4850 +F 0 "U1" H 18250 4950 30 0000 C CNN +F 1 "PORT" H 18200 4850 30 0000 C CNN +F 2 "" H 18200 4850 60 0000 C CNN +F 3 "" H 18200 4850 60 0000 C CNN + 9 18200 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 67A68454 +P 18750 6750 +F 0 "U1" H 18800 6850 30 0000 C CNN +F 1 "PORT" H 18750 6750 30 0000 C CNN +F 2 "" H 18750 6750 60 0000 C CNN +F 3 "" H 18750 6750 60 0000 C CNN + 7 18750 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 67A68779 +P 18800 8500 +F 0 "U1" H 18850 8600 30 0000 C CNN +F 1 "PORT" H 18800 8500 30 0000 C CNN +F 2 "" H 18800 8500 60 0000 C CNN +F 3 "" H 18800 8500 60 0000 C CNN + 6 18800 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 67A68A78 +P 18850 10300 +F 0 "U1" H 18900 10400 30 0000 C CNN +F 1 "PORT" H 18850 10300 30 0000 C CNN +F 2 "" H 18850 10300 60 0000 C CNN +F 3 "" H 18850 10300 60 0000 C CNN + 14 18850 10300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 67A68BEF +P 18850 10900 +F 0 "U1" H 18900 11000 30 0000 C CNN +F 1 "PORT" H 18850 10900 30 0000 C CNN +F 2 "" H 18850 10900 60 0000 C CNN +F 3 "" H 18850 10900 60 0000 C CNN + 15 18850 10900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67A68CDF +P 18650 9150 +F 0 "U1" H 18700 9250 30 0000 C CNN +F 1 "PORT" H 18650 9150 30 0000 C CNN +F 2 "" H 18650 9150 60 0000 C CNN +F 3 "" H 18650 9150 60 0000 C CNN + 8 18650 9150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67A68D6C +P 18650 9350 +F 0 "U1" H 18700 9450 30 0000 C CNN +F 1 "PORT" H 18650 9350 30 0000 C CNN +F 2 "" H 18650 9350 60 0000 C CNN +F 3 "" H 18650 9350 60 0000 C CNN + 16 18650 9350 + 1 0 0 -1 +$EndComp +NoConn ~ 18900 9150 +NoConn ~ 18900 9350 +$Comp +L 4_OR X8 +U 1 1 67AA119F +P 10550 9600 +F 0 "X8" H 10700 9500 60 0000 C CNN +F 1 "4_OR" H 10700 9700 60 0000 C CNN +F 2 "" H 10550 9600 60 0000 C CNN +F 3 "" H 10550 9600 60 0000 C CNN + 1 10550 9600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10200 9700 10200 9650 +Wire Wire Line + 10200 9800 10200 9750 +$Comp +L 4_OR X9 +U 1 1 67AA15F9 +P 10600 10300 +F 0 "X9" H 10750 10200 60 0000 C CNN +F 1 "4_OR" H 10750 10400 60 0000 C CNN +F 2 "" H 10600 10300 60 0000 C CNN +F 3 "" H 10600 10300 60 0000 C CNN + 1 10600 10300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10250 10350 10100 10350 +Wire Wire Line + 10100 10350 10100 10400 +Wire Wire Line + 10250 10500 10250 10450 +Wire Wire Line + 11250 9600 11100 9600 +Wire Wire Line + 11350 10300 11150 10300 +$Comp +L d_inverter U16 +U 1 1 67AA23A3 +P 12750 10700 +F 0 "U16" H 12750 10600 60 0000 C CNN +F 1 "d_inverter" H 12750 10850 60 0000 C CNN +F 2 "" H 12800 10650 60 0000 C CNN +F 3 "" H 12800 10650 60 0000 C CNN + 1 12750 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 67AA2430 +P 12750 11050 +F 0 "U17" H 12750 10950 60 0000 C CNN +F 1 "d_inverter" H 12750 11200 60 0000 C CNN +F 2 "" H 12800 11000 60 0000 C CNN +F 3 "" H 12800 11000 60 0000 C CNN + 1 12750 11050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 67AA24BF +P 12750 10350 +F 0 "U15" H 12750 10250 60 0000 C CNN +F 1 "d_inverter" H 12750 10500 60 0000 C CNN +F 2 "" H 12800 10300 60 0000 C CNN +F 3 "" H 12800 10300 60 0000 C CNN + 1 12750 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 67AA2582 +P 13650 10500 +F 0 "U18" H 13650 10500 60 0000 C CNN +F 1 "d_or" H 13650 10600 60 0000 C CNN +F 2 "" H 13650 10500 60 0000 C CNN +F 3 "" H 13650 10500 60 0000 C CNN + 1 13650 10500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 67AA2694 +P 14200 10950 +F 0 "U20" H 14200 10950 60 0000 C CNN +F 1 "d_or" H 14200 11050 60 0000 C CNN +F 2 "" H 14200 10950 60 0000 C CNN +F 3 "" H 14200 10950 60 0000 C CNN + 1 14200 10950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14100 10450 14200 10450 +Wire Wire Line + 14200 10450 14200 10700 +Wire Wire Line + 14200 10700 13650 10700 +Wire Wire Line + 13650 10700 13650 10850 +Wire Wire Line + 13650 10850 13750 10850 +Wire Wire Line + 13050 10350 13200 10350 +Wire Wire Line + 13200 10350 13200 10400 +Wire Wire Line + 13200 10500 13200 10700 +Wire Wire Line + 13200 10700 13050 10700 +Wire Wire Line + 13050 11050 13650 11050 +Wire Wire Line + 13650 11050 13650 10950 +Wire Wire Line + 13650 10950 13750 10950 +Wire Wire Line + 6400 11050 12450 11050 +Wire Wire Line + 6400 11050 6400 11450 +Wire Wire Line + 11950 11050 11950 11250 +Wire Wire Line + 11950 11250 14800 11250 +Connection ~ 11950 11050 +Wire Wire Line + 14950 10350 14800 10350 +Wire Wire Line + 14800 10350 14800 11250 +Wire Wire Line + 11850 9600 12300 9600 +Wire Wire Line + 12300 9600 12300 9550 +Wire Wire Line + 12300 9550 12900 9550 +Wire Wire Line + 11950 10300 12250 10300 +Wire Wire Line + 12250 9950 12250 10350 +Wire Wire Line + 12250 9950 12650 9950 +Wire Wire Line + 12650 9950 12650 9650 +Wire Wire Line + 12650 9650 12900 9650 +Wire Wire Line + 12250 10350 12450 10350 +Connection ~ 12250 10300 +Wire Wire Line + 12100 9600 12100 10700 +Wire Wire Line + 12100 10700 12450 10700 +Connection ~ 12100 9600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sub b/library/SubcircuitLibrary/CD4532B/CD4532B.sub new file mode 100644 index 00000000..4f812629 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sub @@ -0,0 +1,153 @@ +* Subcircuit CD4532B +.subckt CD4532B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends CD4532B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml new file mode 100644 index 00000000..cd7a8a8d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u22 name="type">d_inverter<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u22><u17 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u23 name="type">d_inverter<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u27 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u26><u28 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_nand<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u32><u34 name="type">d_inverter<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u34><u33 name="type">d_inverter<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u33><u36 name="type">d_inverter<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u36><u37 name="type">d_inverter<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u37><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u35><u19 name="type">d_or<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_or<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_or<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u38 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u39><u16 name="type">d_inverter<field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_inverter<field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u17><u15 name="type">d_inverter<field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x8><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x4><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x3><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x9><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/analysis b/library/SubcircuitLibrary/CD4532B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir new file mode 100644 index 00000000..e0c1478f --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\HD74LS152\HD74LS152.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/18/25 21:34:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U1-Pad5_ Net-_U12-Pad2_ Net-_U24-Pad1_ d_and +U9 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U24-Pad2_ d_and +U10 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_and +U15 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and +U16 Net-_U1-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_and +U17 Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +U18 Net-_U1-Pad13_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U19 Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U19-Pad3_ d_and +U20 Net-_U1-Pad12_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U21-Pad3_ d_and +U22 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and +U23 Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U23-Pad3_ d_and +U32 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_or +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U25 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U25-Pad3_ d_and +U26 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U26-Pad3_ d_and +U27 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U27-Pad3_ d_and +U28 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U28-Pad3_ d_and +U29 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U29-Pad3_ d_and +U30 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U30-Pad3_ d_and +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_and +U33 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_or +U35 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_or +U34 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U34-Pad3_ d_or +U36 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U36-Pad3_ d_or +U37 Net-_U35-Pad3_ Net-_U34-Pad3_ Net-_U37-Pad3_ d_or +U38 Net-_U36-Pad3_ Net-_U37-Pad3_ Net-_U38-Pad3_ d_or +U39 Net-_U38-Pad3_ Net-_U1-Pad6_ d_inverter +U4 Net-_U1-Pad10_ Net-_U12-Pad2_ d_inverter +U7 Net-_U12-Pad2_ Net-_U10-Pad2_ d_inverter +U2 Net-_U1-Pad9_ Net-_U11-Pad1_ d_inverter +U5 Net-_U11-Pad1_ Net-_U13-Pad1_ d_inverter +U3 Net-_U1-Pad8_ Net-_U11-Pad2_ d_inverter +U6 Net-_U11-Pad2_ Net-_U17-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out new file mode 100644 index 00000000..db09e46d --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out @@ -0,0 +1,164 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir + +* u8 net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and +* u9 net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and +* u10 net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u16 net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and +* u17 net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u18 net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and +* u20 net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and +* u21 net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u23 net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and +* u25 net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and +* u26 net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and +* u27 net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and +* u28 net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and +* u29 net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and +* u30 net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and +* u31 net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or +* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or +* u36 net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or +* u37 net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or +* u38 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or +* u39 net-_u38-pad3_ net-_u1-pad6_ d_inverter +* u4 net-_u1-pad10_ net-_u12-pad2_ d_inverter +* u7 net-_u12-pad2_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u11-pad1_ d_inverter +* u5 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad2_ d_inverter +* u6 net-_u11-pad2_ net-_u17-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9 +a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19 +a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23 +a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27 +a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28 +a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30 +a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31 +a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34 +a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36 +a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37 +a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38 +a32 net-_u38-pad3_ net-_u1-pad6_ u39 +a33 net-_u1-pad10_ net-_u12-pad2_ u4 +a34 net-_u12-pad2_ net-_u10-pad2_ u7 +a35 net-_u1-pad9_ net-_u11-pad1_ u2 +a36 net-_u11-pad1_ net-_u13-pad1_ u5 +a37 net-_u1-pad8_ net-_u11-pad2_ u3 +a38 net-_u11-pad2_ net-_u17-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch new file mode 100644 index 00000000..70c27f62 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch @@ -0,0 +1,904 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:HD74LS152-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 678A887C +P 11800 5150 +F 0 "U8" H 11800 5150 60 0000 C CNN +F 1 "d_and" H 11850 5250 60 0000 C CNN +F 2 "" H 11800 5150 60 0000 C CNN +F 3 "" H 11800 5150 60 0000 C CNN + 1 11800 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 678A889E +P 11800 5400 +F 0 "U9" H 11800 5400 60 0000 C CNN +F 1 "d_and" H 11850 5500 60 0000 C CNN +F 2 "" H 11800 5400 60 0000 C CNN +F 3 "" H 11800 5400 60 0000 C CNN + 1 11800 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 678A88F4 +P 11800 5850 +F 0 "U10" H 11800 5850 60 0000 C CNN +F 1 "d_and" H 11850 5950 60 0000 C CNN +F 2 "" H 11800 5850 60 0000 C CNN +F 3 "" H 11800 5850 60 0000 C CNN + 1 11800 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 678A88FA +P 11800 6100 +F 0 "U11" H 11800 6100 60 0000 C CNN +F 1 "d_and" H 11850 6200 60 0000 C CNN +F 2 "" H 11800 6100 60 0000 C CNN +F 3 "" H 11800 6100 60 0000 C CNN + 1 11800 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 678A8C48 +P 11800 6600 +F 0 "U12" H 11800 6600 60 0000 C CNN +F 1 "d_and" H 11850 6700 60 0000 C CNN +F 2 "" H 11800 6600 60 0000 C CNN +F 3 "" H 11800 6600 60 0000 C CNN + 1 11800 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 678A8C4E +P 11800 6850 +F 0 "U13" H 11800 6850 60 0000 C CNN +F 1 "d_and" H 11850 6950 60 0000 C CNN +F 2 "" H 11800 6850 60 0000 C CNN +F 3 "" H 11800 6850 60 0000 C CNN + 1 11800 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 678A8C54 +P 11800 7300 +F 0 "U14" H 11800 7300 60 0000 C CNN +F 1 "d_and" H 11850 7400 60 0000 C CNN +F 2 "" H 11800 7300 60 0000 C CNN +F 3 "" H 11800 7300 60 0000 C CNN + 1 11800 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 678A8C5A +P 11800 7550 +F 0 "U15" H 11800 7550 60 0000 C CNN +F 1 "d_and" H 11850 7650 60 0000 C CNN +F 2 "" H 11800 7550 60 0000 C CNN +F 3 "" H 11800 7550 60 0000 C CNN + 1 11800 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 678A8D88 +P 11800 8000 +F 0 "U16" H 11800 8000 60 0000 C CNN +F 1 "d_and" H 11850 8100 60 0000 C CNN +F 2 "" H 11800 8000 60 0000 C CNN +F 3 "" H 11800 8000 60 0000 C CNN + 1 11800 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 678A8D8E +P 11800 8250 +F 0 "U17" H 11800 8250 60 0000 C CNN +F 1 "d_and" H 11850 8350 60 0000 C CNN +F 2 "" H 11800 8250 60 0000 C CNN +F 3 "" H 11800 8250 60 0000 C CNN + 1 11800 8250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 678A8D94 +P 11800 8700 +F 0 "U18" H 11800 8700 60 0000 C CNN +F 1 "d_and" H 11850 8800 60 0000 C CNN +F 2 "" H 11800 8700 60 0000 C CNN +F 3 "" H 11800 8700 60 0000 C CNN + 1 11800 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 678A8D9A +P 11800 8950 +F 0 "U19" H 11800 8950 60 0000 C CNN +F 1 "d_and" H 11850 9050 60 0000 C CNN +F 2 "" H 11800 8950 60 0000 C CNN +F 3 "" H 11800 8950 60 0000 C CNN + 1 11800 8950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 678A8DA0 +P 11800 9450 +F 0 "U20" H 11800 9450 60 0000 C CNN +F 1 "d_and" H 11850 9550 60 0000 C CNN +F 2 "" H 11800 9450 60 0000 C CNN +F 3 "" H 11800 9450 60 0000 C CNN + 1 11800 9450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 678A8DA6 +P 11800 9700 +F 0 "U21" H 11800 9700 60 0000 C CNN +F 1 "d_and" H 11850 9800 60 0000 C CNN +F 2 "" H 11800 9700 60 0000 C CNN +F 3 "" H 11800 9700 60 0000 C CNN + 1 11800 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 678A8DAC +P 11800 10150 +F 0 "U22" H 11800 10150 60 0000 C CNN +F 1 "d_and" H 11850 10250 60 0000 C CNN +F 2 "" H 11800 10150 60 0000 C CNN +F 3 "" H 11800 10150 60 0000 C CNN + 1 11800 10150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 678A8DB2 +P 11800 10400 +F 0 "U23" H 11800 10400 60 0000 C CNN +F 1 "d_and" H 11850 10500 60 0000 C CNN +F 2 "" H 11800 10400 60 0000 C CNN +F 3 "" H 11800 10400 60 0000 C CNN + 1 11800 10400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 678A8DCA +P 14800 5700 +F 0 "U32" H 14800 5700 60 0000 C CNN +F 1 "d_or" H 14800 5800 60 0000 C CNN +F 2 "" H 14800 5700 60 0000 C CNN +F 3 "" H 14800 5700 60 0000 C CNN + 1 14800 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 678A8E8A +P 12850 5300 +F 0 "U24" H 12850 5300 60 0000 C CNN +F 1 "d_and" H 12900 5400 60 0000 C CNN +F 2 "" H 12850 5300 60 0000 C CNN +F 3 "" H 12850 5300 60 0000 C CNN + 1 12850 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 678A8FC4 +P 12850 6000 +F 0 "U25" H 12850 6000 60 0000 C CNN +F 1 "d_and" H 12900 6100 60 0000 C CNN +F 2 "" H 12850 6000 60 0000 C CNN +F 3 "" H 12850 6000 60 0000 C CNN + 1 12850 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 678A920D +P 12850 6750 +F 0 "U26" H 12850 6750 60 0000 C CNN +F 1 "d_and" H 12900 6850 60 0000 C CNN +F 2 "" H 12850 6750 60 0000 C CNN +F 3 "" H 12850 6750 60 0000 C CNN + 1 12850 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 678A94C5 +P 12850 7450 +F 0 "U27" H 12850 7450 60 0000 C CNN +F 1 "d_and" H 12900 7550 60 0000 C CNN +F 2 "" H 12850 7450 60 0000 C CNN +F 3 "" H 12850 7450 60 0000 C CNN + 1 12850 7450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 678A94CB +P 12850 8200 +F 0 "U28" H 12850 8200 60 0000 C CNN +F 1 "d_and" H 12900 8300 60 0000 C CNN +F 2 "" H 12850 8200 60 0000 C CNN +F 3 "" H 12850 8200 60 0000 C CNN + 1 12850 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U29 +U 1 1 678A98CF +P 12850 8850 +F 0 "U29" H 12850 8850 60 0000 C CNN +F 1 "d_and" H 12900 8950 60 0000 C CNN +F 2 "" H 12850 8850 60 0000 C CNN +F 3 "" H 12850 8850 60 0000 C CNN + 1 12850 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U30 +U 1 1 678A98D5 +P 12850 9550 +F 0 "U30" H 12850 9550 60 0000 C CNN +F 1 "d_and" H 12900 9650 60 0000 C CNN +F 2 "" H 12850 9550 60 0000 C CNN +F 3 "" H 12850 9550 60 0000 C CNN + 1 12850 9550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U31 +U 1 1 678A98DB +P 12850 10300 +F 0 "U31" H 12850 10300 60 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6650 60 0000 C CNN +F 3 "" H 16150 6650 60 0000 C CNN + 1 16150 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_or U37 +U 1 1 678A9DEC +P 16200 9200 +F 0 "U37" H 16200 9200 60 0000 C CNN +F 1 "d_or" H 16200 9300 60 0000 C CNN +F 2 "" H 16200 9200 60 0000 C CNN +F 3 "" H 16200 9200 60 0000 C CNN + 1 16200 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U38 +U 1 1 678A9E94 +P 17350 7850 +F 0 "U38" H 17350 7850 60 0000 C CNN +F 1 "d_or" H 17350 7950 60 0000 C CNN +F 2 "" H 17350 7850 60 0000 C CNN +F 3 "" H 17350 7850 60 0000 C CNN + 1 17350 7850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 678A9F5D +P 18300 7800 +F 0 "U39" H 18300 7700 60 0000 C CNN +F 1 "d_inverter" H 18300 7950 60 0000 C CNN +F 2 "" H 18350 7750 60 0000 C CNN +F 3 "" H 18350 7750 60 0000 C CNN + 1 18300 7800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 678AABC1 +P 6750 11250 +F 0 "U4" H 6750 11150 60 0000 C CNN +F 1 "d_inverter" H 6750 11400 60 0000 C CNN +F 2 "" H 6800 11200 60 0000 C CNN +F 3 "" H 6800 11200 60 0000 C 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7900 30 0000 C CNN +F 1 "PORT" H 19200 7800 30 0000 C CNN +F 2 "" H 19200 7800 60 0000 C CNN +F 3 "" H 19200 7800 60 0000 C CNN + 6 19200 7800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 678BA3D2 +P 6500 5050 +F 0 "U1" H 6550 5150 30 0000 C CNN +F 1 "PORT" H 6500 5050 30 0000 C CNN +F 2 "" H 6500 5050 60 0000 C CNN +F 3 "" H 6500 5050 60 0000 C CNN + 5 6500 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 678BA4DF +P 6450 5750 +F 0 "U1" H 6500 5850 30 0000 C CNN +F 1 "PORT" H 6450 5750 30 0000 C CNN +F 2 "" H 6450 5750 60 0000 C CNN +F 3 "" H 6450 5750 60 0000 C CNN + 4 6450 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 678BA54C +P 6450 6500 +F 0 "U1" H 6500 6600 30 0000 C CNN +F 1 "PORT" H 6450 6500 30 0000 C CNN +F 2 "" H 6450 6500 60 0000 C CNN +F 3 "" H 6450 6500 60 0000 C CNN + 3 6450 6500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 678BA63F +P 6450 7200 +F 0 "U1" H 6500 7300 30 0000 C CNN +F 1 "PORT" H 6450 7200 30 0000 C CNN +F 2 "" H 6450 7200 60 0000 C CNN +F 3 "" H 6450 7200 60 0000 C CNN + 2 6450 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 678BA760 +P 6450 7900 +F 0 "U1" H 6500 8000 30 0000 C CNN +F 1 "PORT" H 6450 7900 30 0000 C CNN +F 2 "" H 6450 7900 60 0000 C CNN +F 3 "" H 6450 7900 60 0000 C CNN + 1 6450 7900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 678BAA39 +P 6500 8600 +F 0 "U1" H 6550 8700 30 0000 C CNN +F 1 "PORT" H 6500 8600 30 0000 C CNN +F 2 "" H 6500 8600 60 0000 C CNN +F 3 "" H 6500 8600 60 0000 C CNN + 13 6500 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 678BAAB4 +P 6350 9350 +F 0 "U1" H 6400 9450 30 0000 C CNN +F 1 "PORT" H 6350 9350 30 0000 C CNN +F 2 "" H 6350 9350 60 0000 C CNN +F 3 "" H 6350 9350 60 0000 C CNN + 12 6350 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 678BAB2F +P 6350 10050 +F 0 "U1" H 6400 10150 30 0000 C CNN +F 1 "PORT" H 6350 10050 30 0000 C CNN +F 2 "" H 6350 10050 60 0000 C CNN +F 3 "" H 6350 10050 60 0000 C CNN + 11 6350 10050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 678BAD20 +P 5850 11250 +F 0 "U1" H 5900 11350 30 0000 C CNN +F 1 "PORT" H 5850 11250 30 0000 C CNN +F 2 "" H 5850 11250 60 0000 C CNN +F 3 "" H 5850 11250 60 0000 C CNN + 10 5850 11250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 678BAD9B +P 5850 11950 +F 0 "U1" H 5900 12050 30 0000 C CNN +F 1 "PORT" H 5850 11950 30 0000 C CNN +F 2 "" H 5850 11950 60 0000 C CNN +F 3 "" H 5850 11950 60 0000 C CNN + 9 5850 11950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 678BB0C4 +P 5850 12700 +F 0 "U1" H 5900 12800 30 0000 C CNN +F 1 "PORT" H 5850 12700 30 0000 C CNN +F 2 "" H 5850 12700 60 0000 C CNN +F 3 "" H 5850 12700 60 0000 C CNN + 8 5850 12700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 678BB437 +P 13400 11500 +F 0 "U1" H 13450 11600 30 0000 C CNN +F 1 "PORT" H 13400 11500 30 0000 C CNN +F 2 "" H 13400 11500 60 0000 C CNN +F 3 "" H 13400 11500 60 0000 C CNN + 7 13400 11500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 678BB54B +P 13400 11750 +F 0 "U1" H 13450 11850 30 0000 C CNN +F 1 "PORT" H 13400 11750 30 0000 C CNN +F 2 "" H 13400 11750 60 0000 C CNN +F 3 "" H 13400 11750 60 0000 C CNN + 14 13400 11750 + 1 0 0 -1 +$EndComp +NoConn ~ 13650 11500 +NoConn ~ 13650 11750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub new file mode 100644 index 00000000..3604a713 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub @@ -0,0 +1,158 @@ +* Subcircuit HD74LS152 +.subckt HD74LS152 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir +* u8 net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and +* u9 net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and +* u10 net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u16 net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and +* u17 net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u18 net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and +* u20 net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and +* u21 net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u23 net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and +* u25 net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and +* u26 net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and +* u27 net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and +* u28 net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and +* u29 net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and +* u30 net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and +* u31 net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or +* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or +* u36 net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or +* u37 net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or +* u38 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or +* u39 net-_u38-pad3_ net-_u1-pad6_ d_inverter +* u4 net-_u1-pad10_ net-_u12-pad2_ d_inverter +* u7 net-_u12-pad2_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u11-pad1_ d_inverter +* u5 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad2_ d_inverter +* u6 net-_u11-pad2_ net-_u17-pad2_ d_inverter +a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9 +a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19 +a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23 +a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27 +a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28 +a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30 +a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31 +a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34 +a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36 +a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37 +a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38 +a32 net-_u38-pad3_ net-_u1-pad6_ u39 +a33 net-_u1-pad10_ net-_u12-pad2_ u4 +a34 net-_u12-pad2_ net-_u10-pad2_ u7 +a35 net-_u1-pad9_ net-_u11-pad1_ u2 +a36 net-_u11-pad1_ net-_u13-pad1_ u5 +a37 net-_u1-pad8_ net-_u11-pad2_ u3 +a38 net-_u11-pad2_ net-_u17-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends HD74LS152
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml new file mode 100644 index 00000000..044e3a73 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u21><u22 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /></u22><u23 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /></u23><u32 name="type">d_or<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /></u32><u24 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /></u24><u25 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /></u25><u26 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /></u26><u27 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /></u27><u28 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /></u28><u29 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /></u29><u30 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /></u30><u31 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /></u33><u35 name="type">d_or<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /></u35><u34 name="type">d_or<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /></u34><u36 name="type">d_or<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /></u36><u37 name="type">d_or<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u37><u38 name="type">d_or<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u39><u4 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /></u4><u7 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /></u7><u2 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u2><u5 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /></u5><u3 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/analysis b/library/SubcircuitLibrary/HD74LS152/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/D.lib b/library/SubcircuitLibrary/MC1489_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib b/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir new file mode 100644 index 00000000..fc367dfd --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0\MC1489_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 19:55:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 6.7K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out new file mode 100644 index 00000000..f87cb465 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro b/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch new file mode 100644 index 00000000..9370a9cd --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "6.7K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub new file mode 100644 index 00000000..3b1419b5 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub @@ -0,0 +1,18 @@ +* Subcircuit MC1489_0 +.subckt MC1489_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* Control Statements + +.ends MC1489_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml b/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/NPN.lib b/library/SubcircuitLibrary/MC1489_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC1489_0/analysis b/library/SubcircuitLibrary/MC1489_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib new file mode 100644 index 00000000..26ac6e60 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib @@ -0,0 +1,120 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir new file mode 100644 index 00000000..895e7634 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL\NAND_GATE_FINAL.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:44:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 500 +R2 Net-_R1-Pad1_ Net-_Q3-Pad1_ 60k +R4 Net-_Q4-Pad1_ Net-_R1-Pad1_ 10k +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_D1-Pad2_ Net-_Q3-Pad3_ GND eSim_NPN +R3 Net-_Q3-Pad3_ GND 10k +U1 Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_D1-Pad2_ Net-_R1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out new file mode 100644 index 00000000..2c658aae --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir + +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 500 +r2 net-_r1-pad1_ net-_q3-pad1_ 60k +r4 net-_q4-pad1_ net-_r1-pad1_ 10k +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 10k +* u1 net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch new file mode 100644 index 00000000..99c63cf9 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:NAND_GATE_FINAL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67704AAF +P 3150 4650 +F 0 "Q2" H 3050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3100 4800 50 0000 R CNN +F 2 "" H 3350 4750 29 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 1 3150 4650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 67704B0A +P 2350 4650 +F 0 "Q1" H 2250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2300 4800 50 0000 R CNN +F 2 "" H 2550 4750 29 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 1 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67704BF2 +P 2700 3400 +F 0 "R1" H 2750 3530 50 0000 C CNN +F 1 "500" H 2750 3350 50 0000 C CNN +F 2 "" H 2750 3380 30 0000 C CNN +F 3 "" V 2750 3450 30 0000 C CNN + 1 2700 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67704C41 +P 3600 3400 +F 0 "R2" H 3650 3530 50 0000 C CNN +F 1 "60k" H 3650 3350 50 0000 C CNN +F 2 "" H 3650 3380 30 0000 C CNN +F 3 "" V 3650 3450 30 0000 C CNN + 1 3600 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67704C62 +P 4650 3500 +F 0 "R4" H 4700 3630 50 0000 C CNN +F 1 "10k" H 4700 3450 50 0000 C CNN +F 2 "" H 4700 3480 30 0000 C CNN +F 3 "" V 4700 3550 30 0000 C CNN + 1 4650 3500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67704C93 +P 4500 4050 +F 0 "Q4" H 4400 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4450 4200 50 0000 R CNN +F 2 "" H 4700 4150 29 0000 C CNN +F 3 "" H 4500 4050 60 0000 C CNN + 1 4500 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67704CC8 +P 3900 4350 +F 0 "Q3" H 3800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4500 50 0000 R CNN +F 2 "" H 4100 4450 29 0000 C CNN +F 3 "" H 3900 4350 60 0000 C CNN + 1 3900 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67704D0D +P 4600 4600 +F 0 "D1" H 4600 4700 50 0000 C CNN +F 1 "eSim_Diode" H 4600 4500 50 0000 C CNN +F 2 "" H 4600 4600 60 0000 C CNN +F 3 "" H 4600 4600 60 0000 C CNN + 1 4600 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 67704DC5 +P 4500 5250 +F 0 "Q5" H 4400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5400 50 0000 R CNN +F 2 "" H 4700 5350 29 0000 C CNN +F 3 "" H 4500 5250 60 0000 C CNN + 1 4500 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 67704DD6 +P 3950 5500 +F 0 "R3" H 4000 5630 50 0000 C CNN +F 1 "10k" V 4000 5450 50 0000 C CNN +F 2 "" H 4000 5480 30 0000 C CNN +F 3 "" V 4000 5550 30 0000 C CNN + 1 3950 5500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 67705207 +P 2450 5250 +F 0 "U1" H 2500 5350 30 0000 C CNN +F 1 "PORT" H 2450 5250 30 0000 C CNN +F 2 "" H 2450 5250 60 0000 C CNN +F 3 "" H 2450 5250 60 0000 C CNN + 1 2450 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67705289 +P 3050 5250 +F 0 "U1" H 3100 5350 30 0000 C CNN +F 1 "PORT" H 3050 5250 30 0000 C CNN +F 2 "" H 3050 5250 60 0000 C CNN +F 3 "" H 3050 5250 60 0000 C CNN + 2 3050 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677052CE +P 5300 4900 +F 0 "U1" H 5350 5000 30 0000 C CNN +F 1 "PORT" H 5300 4900 30 0000 C CNN +F 2 "" H 5300 4900 60 0000 C CNN +F 3 "" H 5300 4900 60 0000 C CNN + 3 5300 4900 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67705545 +P 4750 5800 +F 0 "#PWR01" H 4750 5550 50 0001 C CNN +F 1 "GND" H 4750 5650 50 0000 C CNN +F 2 "" H 4750 5800 50 0001 C CNN +F 3 "" H 4750 5800 50 0001 C CNN + 1 4750 5800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3050 4450 2450 4450 +Wire Wire Line + 3350 4150 2150 4150 +Wire Wire Line + 3350 4650 3350 4150 +Wire Wire Line + 2150 4150 2150 4650 +Connection ~ 2750 4450 +Wire Wire Line + 4000 4550 4000 5400 +Wire Wire Line + 4300 5250 4000 5250 +Connection ~ 4000 5250 +Wire Wire Line + 4600 5050 4600 4750 +Wire Wire Line + 4600 4450 4600 4250 +Wire Wire Line + 4600 3850 4600 3600 +Wire Wire Line + 3650 4050 4300 4050 +Wire Wire Line + 4000 4050 4000 4150 +Wire Wire Line + 3650 4050 3650 3600 +Connection ~ 4000 4050 +Wire Wire Line + 2750 3300 2750 3050 +Wire Wire Line + 4600 3050 4600 3300 +Wire Wire Line + 3650 3300 3650 3050 +Connection ~ 3650 3050 +Wire Wire Line + 2450 4850 2450 5000 +Wire Wire Line + 3050 4850 3050 5000 +Wire Wire Line + 4000 5700 4000 5800 +Wire Wire Line + 4000 5800 4750 5800 +Wire Wire Line + 4600 4900 5050 4900 +Connection ~ 4600 4900 +Connection ~ 4600 5800 +Connection ~ 4600 3050 +Wire Wire Line + 4600 5800 4600 5450 +$Comp +L PORT U1 +U 4 1 677060E6 +P 4750 2700 +F 0 "U1" H 4800 2800 30 0000 C CNN +F 1 "PORT" H 4750 2700 30 0000 C CNN +F 2 "" H 4750 2700 60 0000 C CNN +F 3 "" H 4750 2700 60 0000 C CNN + 4 4750 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 4750 2950 4750 3050 +Connection ~ 4750 3050 +Wire Wire Line + 4750 3050 2750 3050 +Connection ~ 4600 3750 +Wire Wire Line + 2750 3600 2750 4150 +Connection ~ 2750 4150 +Wire Wire Line + 3700 4350 2750 4350 +Wire Wire Line + 2750 4350 2750 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub new file mode 100644 index 00000000..544c5e10 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub @@ -0,0 +1,18 @@ +* Subcircuit NAND_GATE_FINAL +.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 500 +r2 net-_r1-pad1_ net-_q3-pad1_ 60k +r4 net-_q4-pad1_ net-_r1-pad1_ 10k +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 10k +* Control Statements + +.ends NAND_GATE_FINAL
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml new file mode 100644 index 00000000..0eb364f5 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis b/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib new file mode 100644 index 00000000..32e7ba06 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib @@ -0,0 +1,756 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 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150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# OTA_CA3080 +# +DEF OTA_CA3080 X 0 40 Y Y 1 F N +F0 "X" 200 300 60 H V C CNN +F1 "OTA_CA3080" 50 0 60 H V C CNN +F2 "" 50 0 60 H I C CNN +F3 "" 50 0 60 H I C CNN +DRAW +C 200 -100 50 0 1 0 N +C 250 -100 50 0 1 0 N +P 6 0 1 0 -350 350 -350 -450 650 0 -350 450 -350 300 -350 350 N +X A 1 300 350 200 D 50 50 1 1 I +X B 2 -550 -300 200 R 50 50 1 1 I +X C 3 -550 250 200 R 50 50 1 1 I +X D 4 0 -500 200 U 50 50 1 1 I +X E 5 550 250 200 D 50 50 1 1 I +X F 6 850 0 200 L 50 50 1 1 O +X G 7 0 500 200 D 50 50 1 1 I +X H 8 300 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm3909 +# +DEF lm3909 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "lm3909" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1000 400 1050 -450 0 1 0 N +X ~ 1 -750 -650 200 U 50 50 1 1 I +X ~ 2 -200 -650 200 U 50 50 1 1 I +X ~ 3 350 -650 200 U 50 50 1 1 I +X ~ 4 850 -650 200 U 50 50 1 1 I +X ~ 5 850 600 200 D 50 50 1 1 I +X ~ 6 350 600 200 D 50 50 1 1 I +X ~ 7 -200 600 200 D 50 50 1 1 I +X ~ 8 -750 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# nand_ttl +# +DEF nand_ttl X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "nand_ttl" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -580 156 1081 -250 -777 0 1 0 N 400 -300 -350 -900 +A -361 -420 770 90 892 0 1 0 N 400 -300 -350 350 +C 500 -300 112 0 1 0 N +P 2 0 1 0 -350 -300 -350 -900 N +P 2 0 1 0 -350 350 -350 -300 N +X A 1 -550 150 200 R 50 50 1 1 I +X B 2 -550 -650 200 R 50 50 1 1 I +X C 3 800 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54180/SN54180-cache.lib b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib new file mode 100644 index 00000000..27b0f7f2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir b/library/SubcircuitLibrary/SN54180/SN54180.cir new file mode 100644 index 00000000..89146f7f --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN54180\SN54180.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/07/25 23:03:34 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U2-Pad3_ d_xnor +U3 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U3-Pad3_ d_xnor +U4 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad3_ d_xnor +U5 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U5-Pad3_ d_xnor +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U10-Pad1_ d_xnor +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_xor +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_xor +U9 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U1-Pad4_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad3_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U1-Pad4_ Net-_U13-Pad3_ d_and +U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad5_ d_nor +U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U1-Pad6_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir.out b/library/SubcircuitLibrary/SN54180/SN54180.cir.out new file mode 100644 index 00000000..18993e8b --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.cir.out @@ -0,0 +1,68 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir + +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54180/SN54180.pro b/library/SubcircuitLibrary/SN54180/SN54180.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sch b/library/SubcircuitLibrary/SN54180/SN54180.sch new file mode 100644 index 00000000..1534f8b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.sch @@ -0,0 +1,499 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN54180-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xnor U2 +U 1 1 677290B0 +P 6050 7300 +F 0 "U2" H 6050 7300 60 0000 C CNN +F 1 "d_xnor" H 6100 7400 47 0000 C CNN +F 2 "" H 6050 7300 60 0000 C CNN +F 3 "" H 6050 7300 60 0000 C CNN + 1 6050 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U3 +U 1 1 677290E7 +P 6050 7750 +F 0 "U3" H 6050 7750 60 0000 C CNN +F 1 "d_xnor" H 6100 7850 47 0000 C CNN +F 2 "" H 6050 7750 60 0000 C CNN +F 3 "" H 6050 7750 60 0000 C CNN + 1 6050 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U4 +U 1 1 67729137 +P 6050 8200 +F 0 "U4" H 6050 8200 60 0000 C CNN +F 1 "d_xnor" H 6100 8300 47 0000 C CNN +F 2 "" H 6050 8200 60 0000 C CNN +F 3 "" H 6050 8200 60 0000 C CNN + 1 6050 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U5 +U 1 1 6772913D +P 6050 8650 +F 0 "U5" H 6050 8650 60 0000 C CNN +F 1 "d_xnor" H 6100 8750 47 0000 C CNN +F 2 "" H 6050 8650 60 0000 C CNN +F 3 "" H 6050 8650 60 0000 C CNN + 1 6050 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U8 +U 1 1 6772915D +P 8600 7950 +F 0 "U8" H 8600 7950 60 0000 C CNN +F 1 "d_xnor" H 8650 8050 47 0000 C CNN +F 2 "" H 8600 7950 60 0000 C CNN +F 3 "" H 8600 7950 60 0000 C CNN + 1 8600 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 677291A8 +P 7350 7500 +F 0 "U6" H 7350 7500 60 0000 C CNN +F 1 "d_xor" H 7400 7600 47 0000 C CNN +F 2 "" H 7350 7500 60 0000 C CNN +F 3 "" H 7350 7500 60 0000 C CNN + 1 7350 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 677291CD +P 7350 8400 +F 0 "U7" H 7350 8400 60 0000 C CNN +F 1 "d_xor" H 7400 8500 47 0000 C CNN +F 2 "" H 7350 8400 60 0000 C CNN +F 3 "" H 7350 8400 60 0000 C CNN + 1 7350 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 67729482 +P 9800 7900 +F 0 "U9" H 9800 7800 60 0000 C CNN +F 1 "d_inverter" H 9800 8050 60 0000 C CNN +F 2 "" H 9850 7850 60 0000 C CNN +F 3 "" H 9850 7850 60 0000 C CNN + 1 9800 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 67729715 +P 11450 7250 +F 0 "U10" H 11450 7250 60 0000 C CNN +F 1 "d_and" H 11500 7350 60 0000 C CNN +F 2 "" H 11450 7250 60 0000 C CNN +F 3 "" H 11450 7250 60 0000 C CNN + 1 11450 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 6772978A +P 11450 7750 +F 0 "U11" H 11450 7750 60 0000 C CNN +F 1 "d_and" H 11500 7850 60 0000 C CNN +F 2 "" H 11450 7750 60 0000 C CNN +F 3 "" H 11450 7750 60 0000 C CNN + 1 11450 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 677297EE +P 11450 8200 +F 0 "U12" H 11450 8200 60 0000 C CNN +F 1 "d_and" H 11500 8300 60 0000 C CNN +F 2 "" H 11450 8200 60 0000 C CNN +F 3 "" H 11450 8200 60 0000 C CNN + 1 11450 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 677297F4 +P 11450 8700 +F 0 "U13" H 11450 8700 60 0000 C CNN +F 1 "d_and" H 11500 8800 60 0000 C CNN +F 2 "" H 11450 8700 60 0000 C CNN +F 3 "" H 11450 8700 60 0000 C CNN + 1 11450 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 67729834 +P 13400 7550 +F 0 "U14" H 13400 7550 60 0000 C CNN +F 1 "d_nor" H 13450 7650 60 0000 C CNN +F 2 "" H 13400 7550 60 0000 C CNN +F 3 "" H 13400 7550 60 0000 C CNN + 1 13400 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 677299D9 +P 13400 8450 +F 0 "U15" H 13400 8450 60 0000 C CNN +F 1 "d_nor" H 13450 8550 60 0000 C CNN +F 2 "" H 13400 8450 60 0000 C CNN +F 3 "" H 13400 8450 60 0000 C CNN + 1 13400 8450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 7200 4850 7200 +Wire Wire Line + 5600 7300 4850 7300 +Wire Wire Line + 5600 7650 4850 7650 +Wire Wire Line + 5600 7750 4850 7750 +Wire Wire Line + 5600 8100 4850 8100 +Wire Wire Line + 5600 8200 4850 8200 +Wire Wire Line + 5600 8550 4850 8550 +Wire Wire Line + 5600 8650 4850 8650 +Wire Wire Line + 6500 7250 6750 7250 +Wire Wire Line + 6750 7250 6750 7400 +Wire Wire Line + 6750 7400 6900 7400 +Wire Wire Line + 6900 7500 6750 7500 +Wire Wire Line + 6750 7500 6750 7700 +Wire Wire Line + 6750 7700 6500 7700 +Wire Wire Line + 6500 8150 6700 8150 +Wire Wire Line + 6700 8150 6700 8300 +Wire Wire Line + 6700 8300 6900 8300 +Wire Wire Line + 6900 8400 6700 8400 +Wire Wire Line + 6700 8400 6700 8600 +Wire Wire Line + 6700 8600 6500 8600 +Wire Wire Line + 7800 7450 8000 7450 +Wire Wire Line + 8000 7450 8000 7850 +Wire Wire Line + 8000 7850 8150 7850 +Wire Wire Line + 8150 7950 8000 7950 +Wire Wire Line + 8000 7950 8000 8350 +Wire Wire Line + 8000 8350 7800 8350 +Wire Wire Line + 9050 7900 9500 7900 +Wire Wire Line + 11000 7150 9300 7150 +Wire Wire Line + 9300 7150 9300 8200 +Connection ~ 9300 7900 +Wire Wire Line + 9300 8200 11000 8200 +Wire Wire Line + 10350 7250 11000 7250 +Wire Wire Line + 10350 7250 10350 9350 +Wire Wire Line + 10350 8700 11000 8700 +Wire Wire Line + 11000 7650 10550 7650 +Wire Wire Line + 10550 7650 10550 8600 +Wire Wire Line + 10550 8600 11000 8600 +Wire Wire Line + 11000 7750 10800 7750 +Wire Wire Line + 10800 7750 10800 9550 +Wire Wire Line + 10800 8100 11000 8100 +Wire Wire Line + 10100 7900 10550 7900 +Connection ~ 10550 7900 +Wire Wire Line + 10350 9350 4850 9350 +Connection ~ 10350 8700 +Wire Wire Line + 10800 9550 4850 9550 +Connection ~ 10800 8100 +Wire Wire Line + 11900 7200 12500 7200 +Wire Wire Line + 12500 7200 12500 7450 +Wire Wire Line + 12500 7450 12950 7450 +Wire Wire Line + 12500 7550 12950 7550 +Wire Wire Line + 12500 7550 12500 7700 +Wire Wire Line + 12500 7700 11900 7700 +Wire Wire Line + 11900 8150 12500 8150 +Wire Wire Line + 12500 8150 12500 8350 +Wire Wire Line + 12500 8350 12950 8350 +Wire Wire Line + 12950 8450 12500 8450 +Wire Wire Line + 12500 8450 12500 8650 +Wire Wire Line + 12500 8650 11900 8650 +Wire Wire Line + 13850 7500 14550 7500 +Wire Wire Line + 13850 8400 14550 8400 +$Comp +L PORT U1 +U 1 1 677964E3 +P 4600 8550 +F 0 "U1" H 4650 8650 30 0000 C CNN +F 1 "PORT" H 4600 8550 30 0000 C CNN +F 2 "" H 4600 8550 60 0000 C CNN +F 3 "" H 4600 8550 60 0000 C CNN + 1 4600 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 677965B0 +P 4600 8750 +F 0 "U1" H 4650 8850 30 0000 C CNN +F 1 "PORT" H 4600 8750 30 0000 C CNN +F 2 "" H 4600 8750 60 0000 C CNN +F 3 "" H 4600 8750 60 0000 C CNN + 2 4600 8750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 8650 4850 8750 +$Comp +L PORT U1 +U 3 1 6779664F +P 4600 9550 +F 0 "U1" H 4650 9650 30 0000 C CNN +F 1 "PORT" H 4600 9550 30 0000 C CNN +F 2 "" H 4600 9550 60 0000 C CNN +F 3 "" H 4600 9550 60 0000 C CNN + 3 4600 9550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67796694 +P 4600 9350 +F 0 "U1" H 4650 9450 30 0000 C CNN +F 1 "PORT" H 4600 9350 30 0000 C CNN +F 2 "" H 4600 9350 60 0000 C CNN +F 3 "" H 4600 9350 60 0000 C CNN + 4 4600 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 677975B7 +P 14800 7500 +F 0 "U1" H 14850 7600 30 0000 C CNN +F 1 "PORT" H 14800 7500 30 0000 C CNN +F 2 "" H 14800 7500 60 0000 C CNN +F 3 "" H 14800 7500 60 0000 C CNN + 5 14800 7500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6779764E +P 14800 8400 +F 0 "U1" H 14850 8500 30 0000 C CNN +F 1 "PORT" H 14800 8400 30 0000 C CNN +F 2 "" H 14800 8400 60 0000 C CNN +F 3 "" H 14800 8400 60 0000 C CNN + 6 14800 8400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67798A6F +P 4600 7200 +F 0 "U1" H 4650 7300 30 0000 C CNN +F 1 "PORT" H 4600 7200 30 0000 C CNN +F 2 "" H 4600 7200 60 0000 C CNN +F 3 "" H 4600 7200 60 0000 C CNN + 8 4600 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67798ABE +P 4600 7400 +F 0 "U1" H 4650 7500 30 0000 C CNN +F 1 "PORT" H 4600 7400 30 0000 C CNN +F 2 "" H 4600 7400 60 0000 C CNN +F 3 "" H 4600 7400 60 0000 C CNN + 9 4600 7400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67798B09 +P 4200 7550 +F 0 "U1" H 4250 7650 30 0000 C CNN +F 1 "PORT" H 4200 7550 30 0000 C CNN +F 2 "" H 4200 7550 60 0000 C CNN +F 3 "" H 4200 7550 60 0000 C CNN + 10 4200 7550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67798B62 +P 4200 7800 +F 0 "U1" H 4250 7900 30 0000 C CNN +F 1 "PORT" H 4200 7800 30 0000 C CNN +F 2 "" H 4200 7800 60 0000 C CNN +F 3 "" H 4200 7800 60 0000 C CNN + 11 4200 7800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67798BAD +P 4450 8000 +F 0 "U1" H 4500 8100 30 0000 C CNN +F 1 "PORT" H 4450 8000 30 0000 C CNN +F 2 "" H 4450 8000 60 0000 C CNN +F 3 "" H 4450 8000 60 0000 C CNN + 12 4450 8000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67798BFE +P 4450 8250 +F 0 "U1" H 4500 8350 30 0000 C CNN +F 1 "PORT" H 4450 8250 30 0000 C CNN +F 2 "" H 4450 8250 60 0000 C CNN +F 3 "" H 4450 8250 60 0000 C CNN + 13 4450 8250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 7550 4850 7550 +Wire Wire Line + 4850 7550 4850 7650 +Wire Wire Line + 4450 7800 4850 7800 +Wire Wire Line + 4850 7800 4850 7750 +Wire Wire Line + 4850 7300 4850 7400 +Wire Wire Line + 4700 8000 4850 8000 +Wire Wire Line + 4850 8000 4850 8100 +Wire Wire Line + 4700 8250 4850 8250 +Wire Wire Line + 4850 8250 4850 8200 +$Comp +L PORT U1 +U 7 1 677A3419 +P 5650 10400 +F 0 "U1" H 5700 10500 30 0000 C CNN +F 1 "PORT" H 5650 10400 30 0000 C CNN +F 2 "" H 5650 10400 60 0000 C CNN +F 3 "" H 5650 10400 60 0000 C CNN + 7 5650 10400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 677A353F +P 5650 10650 +F 0 "U1" H 5700 10750 30 0000 C CNN +F 1 "PORT" H 5650 10650 30 0000 C CNN +F 2 "" H 5650 10650 60 0000 C CNN +F 3 "" H 5650 10650 60 0000 C CNN + 14 5650 10650 + 1 0 0 -1 +$EndComp +NoConn ~ 5900 10400 +NoConn ~ 5900 10650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sub b/library/SubcircuitLibrary/SN54180/SN54180.sub new file mode 100644 index 00000000..34693793 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.sub @@ -0,0 +1,62 @@ +* Subcircuit SN54180 +.subckt SN54180 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN54180
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml new file mode 100644 index 00000000..a66526b3 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_xnor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_xnor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u5><u8 name="type">d_xnor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u8><u6 name="type">d_xor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/analysis b/library/SubcircuitLibrary/SN54180/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib b/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro b/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro new file mode 100644 index 00000000..81bd9ad4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro @@ -0,0 +1,70 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Subckt +LibName23=transistors +LibName24=conn +LibName25=eSim_Plot +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User + diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib b/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib b/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib b/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib new file mode 100644 index 00000000..3e8d471c --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir new file mode 100644 index 00000000..f00d5bd3 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN54LS183\SN54LS183.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/10/25 22:53:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad2_ Net-_U18-Pad2_ Net-_U20-Pad2_ d_and +U4 Net-_U2-Pad1_ Net-_U18-Pad2_ Net-_U28-Pad2_ d_and +U5 Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U16-Pad1_ d_and +U16 Net-_U16-Pad1_ Net-_U1-Pad1_ Net-_U16-Pad3_ d_and +U6 Net-_U2-Pad1_ Net-_U1-Pad3_ Net-_U17-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_U1-Pad1_ Net-_U17-Pad3_ d_and +U7 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U18-Pad1_ d_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U8 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U19-Pad1_ d_and +U19 Net-_U19-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +U9 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U25-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad11_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U21 Net-_U12-Pad3_ Net-_U1-Pad13_ Net-_U21-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U13-Pad3_ d_and +U22 Net-_U13-Pad3_ Net-_U1-Pad13_ Net-_U22-Pad3_ d_and +U25 Net-_U25-Pad1_ Net-_U10-Pad3_ Net-_U25-Pad3_ d_nor +U31 Net-_U25-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad10_ d_nor +U29 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U29-Pad3_ d_nor +U30 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U30-Pad3_ d_nor +U33 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U1-Pad8_ d_nor +U14 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U14-Pad3_ d_and +U23 Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_and +U15 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U15-Pad3_ d_and +U24 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_and +U1 Net-_U1-Pad1_ ? Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ ? Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U35 Net-_U1-Pad4_ Net-_U2-Pad1_ d_inverter +U34 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U36 Net-_U1-Pad1_ Net-_U18-Pad2_ d_inverter +U38 Net-_U1-Pad11_ Net-_U11-Pad1_ d_inverter +U37 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U39 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter +U20 Net-_U2-Pad3_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_or +U28 Net-_U20-Pad3_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_or +U40 Net-_U28-Pad3_ Net-_U1-Pad5_ d_inverter +U41 Net-_U32-Pad3_ Net-_U1-Pad6_ d_inverter +U26 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_or +U27 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_or +U32 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U32-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out new file mode 100644 index 00000000..198578d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out @@ -0,0 +1,172 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54ls183\sn54ls183.cir + +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad2_ net-_u18-pad2_ net-_u20-pad2_ d_and +* u4 net-_u2-pad1_ net-_u18-pad2_ net-_u28-pad2_ d_and +* u5 net-_u1-pad4_ net-_u2-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u1-pad1_ net-_u16-pad3_ d_and +* u6 net-_u2-pad1_ net-_u1-pad3_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u1-pad1_ net-_u17-pad3_ d_and +* u7 net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad4_ net-_u1-pad3_ net-_u19-pad1_ d_and +* u19 net-_u19-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad1_ net-_u25-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad11_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u21 net-_u12-pad3_ net-_u1-pad13_ net-_u21-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad12_ net-_u13-pad3_ d_and +* u22 net-_u13-pad3_ net-_u1-pad13_ net-_u22-pad3_ d_and +* u25 net-_u25-pad1_ net-_u10-pad3_ net-_u25-pad3_ d_nor +* u31 net-_u25-pad3_ net-_u11-pad3_ net-_u1-pad10_ d_nor +* u29 net-_u21-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nor +* u33 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad8_ d_nor +* u14 net-_u11-pad1_ net-_u10-pad1_ net-_u14-pad3_ d_and +* u23 net-_u14-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_and +* u15 net-_u1-pad11_ net-_u1-pad12_ net-_u15-pad3_ d_and +* u24 net-_u15-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_and +* u1 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u35 net-_u1-pad4_ net-_u2-pad1_ d_inverter +* u34 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u36 net-_u1-pad1_ net-_u18-pad2_ d_inverter +* u38 net-_u1-pad11_ net-_u11-pad1_ d_inverter +* u37 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u39 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u20 net-_u2-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u28 net-_u20-pad3_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u40 net-_u28-pad3_ net-_u1-pad5_ d_inverter +* u41 net-_u32-pad3_ net-_u1-pad6_ d_inverter +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_or +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_or +* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_or +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad2_ net-_u18-pad2_ ] net-_u20-pad2_ u3 +a3 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u28-pad2_ u4 +a4 [net-_u1-pad4_ net-_u2-pad2_ ] net-_u16-pad1_ u5 +a5 [net-_u16-pad1_ net-_u1-pad1_ ] net-_u16-pad3_ u16 +a6 [net-_u2-pad1_ net-_u1-pad3_ ] net-_u17-pad1_ u6 +a7 [net-_u17-pad1_ net-_u1-pad1_ ] net-_u17-pad3_ u17 +a8 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u18-pad1_ u7 +a9 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u19-pad1_ u8 +a11 [net-_u19-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a12 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u25-pad1_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a16 [net-_u12-pad3_ net-_u1-pad13_ ] net-_u21-pad3_ u21 +a17 [net-_u11-pad1_ net-_u1-pad12_ ] net-_u13-pad3_ u13 +a18 [net-_u13-pad3_ net-_u1-pad13_ ] net-_u22-pad3_ u22 +a19 [net-_u25-pad1_ net-_u10-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u25-pad3_ net-_u11-pad3_ ] net-_u1-pad10_ u31 +a21 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad8_ u33 +a24 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +a25 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u15-pad3_ u15 +a27 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a28 net-_u1-pad4_ net-_u2-pad1_ u35 +a29 net-_u1-pad3_ net-_u2-pad2_ u34 +a30 net-_u1-pad1_ net-_u18-pad2_ u36 +a31 net-_u1-pad11_ net-_u11-pad1_ u38 +a32 net-_u1-pad12_ net-_u10-pad1_ u37 +a33 net-_u1-pad13_ net-_u10-pad2_ u39 +a34 [net-_u2-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a35 [net-_u20-pad3_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a36 net-_u28-pad3_ net-_u1-pad5_ u40 +a37 net-_u32-pad3_ net-_u1-pad6_ u41 +a38 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a39 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a40 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro b/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch new file mode 100644 index 00000000..b972d850 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch @@ -0,0 +1,993 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN54LS183-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 67812973 +P 12300 3250 +F 0 "U2" H 12300 3250 60 0000 C CNN +F 1 "d_and" H 12350 3350 60 0000 C CNN +F 2 "" H 12300 3250 60 0000 C CNN +F 3 "" H 12300 3250 60 0000 C CNN + 1 12300 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 67812A00 +P 12300 3650 +F 0 "U3" H 12300 3650 60 0000 C CNN +F 1 "d_and" H 12350 3750 60 0000 C CNN +F 2 "" H 12300 3650 60 0000 C CNN +F 3 "" H 12300 3650 60 0000 C CNN + 1 12300 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 67812A24 +P 12300 4000 +F 0 "U4" H 12300 4000 60 0000 C CNN +F 1 "d_and" H 12350 4100 60 0000 C CNN +F 2 "" H 12300 4000 60 0000 C CNN +F 3 "" H 12300 4000 60 0000 C CNN + 1 12300 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 67812AC5 +P 12300 4600 +F 0 "U5" H 12300 4600 60 0000 C CNN +F 1 "d_and" H 12350 4700 60 0000 C CNN +F 2 "" H 12300 4600 60 0000 C CNN +F 3 "" H 12300 4600 60 0000 C CNN + 1 12300 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 67812ACB +P 13250 4850 +F 0 "U16" H 13250 4850 60 0000 C CNN +F 1 "d_and" H 13300 4950 60 0000 C CNN +F 2 "" H 13250 4850 60 0000 C CNN +F 3 "" H 13250 4850 60 0000 C CNN + 1 13250 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67812AD1 +P 12300 5350 +F 0 "U6" H 12300 5350 60 0000 C CNN +F 1 "d_and" H 12350 5450 60 0000 C CNN +F 2 "" H 12300 5350 60 0000 C CNN +F 3 "" H 12300 5350 60 0000 C CNN + 1 12300 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 67812AE3 +P 13250 5600 +F 0 "U17" H 13250 5600 60 0000 C CNN +F 1 "d_and" H 13300 5700 60 0000 C CNN +F 2 "" H 13250 5600 60 0000 C CNN +F 3 "" H 13250 5600 60 0000 C CNN + 1 13250 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67813298 +P 12300 6050 +F 0 "U7" H 12300 6050 60 0000 C CNN +F 1 "d_and" H 12350 6150 60 0000 C CNN +F 2 "" H 12300 6050 60 0000 C CNN +F 3 "" H 12300 6050 60 0000 C CNN + 1 12300 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 6781329E +P 13250 6300 +F 0 "U18" H 13250 6300 60 0000 C CNN +F 1 "d_and" H 13300 6400 60 0000 C CNN +F 2 "" H 13250 6300 60 0000 C CNN +F 3 "" H 13250 6300 60 0000 C CNN + 1 13250 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 678132A4 +P 12300 6800 +F 0 "U8" H 12300 6800 60 0000 C CNN +F 1 "d_and" H 12350 6900 60 0000 C CNN +F 2 "" H 12300 6800 60 0000 C CNN +F 3 "" H 12300 6800 60 0000 C CNN + 1 12300 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 678132AA +P 13250 7050 +F 0 "U19" H 13250 7050 60 0000 C CNN +F 1 "d_and" H 13300 7150 60 0000 C CNN +F 2 "" H 13250 7050 60 0000 C CNN +F 3 "" H 13250 7050 60 0000 C CNN + 1 13250 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 678150DC +P 12750 8100 +F 0 "U9" H 12750 8100 60 0000 C CNN +F 1 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15600 10300 +Wire Wire Line + 13200 9400 13250 9400 +Wire Wire Line + 13250 9400 13250 9600 +Wire Wire Line + 13200 10150 13250 10150 +Wire Wire Line + 13250 10150 13250 10350 +Wire Wire Line + 13200 10850 13200 11050 +Wire Wire Line + 13200 11050 13250 11050 +Wire Wire Line + 13200 11600 13250 11600 +Wire Wire Line + 13250 11600 13250 11800 +Wire Wire Line + 14150 9650 14550 9650 +Wire Wire Line + 14550 9650 14550 10250 +Wire Wire Line + 14550 10250 14700 10250 +Wire Wire Line + 14700 10350 14550 10350 +Wire Wire Line + 14550 10350 14550 10400 +Wire Wire Line + 14550 10400 14150 10400 +Wire Wire Line + 14150 11100 14500 11100 +Wire Wire Line + 14500 11100 14500 11000 +Wire Wire Line + 14500 11000 14700 11000 +Wire Wire Line + 14700 11100 14600 11100 +Wire Wire Line + 14600 11100 14600 11850 +Wire Wire Line + 14600 11850 14150 11850 +Wire Wire Line + 12300 8000 10200 8000 +Wire Wire Line + 10200 8000 10200 10800 +Wire Wire Line + 8250 8950 10200 8950 +Wire Wire Line + 12300 8750 10200 8750 +Connection ~ 10200 8750 +Wire Wire Line + 10200 10100 12300 10100 +Connection ~ 10200 8950 +Wire Wire Line + 10200 10800 12300 10800 +Connection ~ 10200 10100 +Wire Wire Line + 12300 8100 11900 8100 +Wire Wire Line + 11900 8100 11900 10900 +Wire Wire Line + 11900 8400 12300 8400 +Wire Wire Line + 8200 9650 11900 9650 +Connection ~ 11900 8400 +Wire Wire Line + 12300 9450 11900 9450 +Connection ~ 11900 9450 +Wire Wire Line + 11900 10900 12300 10900 +Connection ~ 11900 9650 +Wire Wire Line + 12300 8500 12100 8500 +Wire Wire Line + 12100 8500 12100 11900 +Wire Wire Line + 12100 8850 12300 8850 +Wire Wire Line + 8250 10300 12100 10300 +Connection ~ 12100 8850 +Wire Wire Line + 12100 11900 13250 11900 +Connection ~ 12100 10300 +Wire Wire Line + 5600 8950 7650 8950 +Wire Wire Line + 6750 9200 11250 9200 +Wire Wire Line + 11250 9200 11250 11550 +Wire Wire Line + 11250 9350 12300 9350 +Wire Wire Line + 11250 11550 12300 11550 +Connection ~ 11250 9350 +Wire Wire Line + 5750 9650 7600 9650 +Wire Wire Line + 6750 9950 11450 9950 +Wire Wire Line + 11450 9950 11450 11650 +Wire Wire Line + 11450 10200 12300 10200 +Wire Wire Line + 11450 11650 12300 11650 +Connection ~ 11450 10200 +Wire Wire Line + 5800 10300 7650 10300 +Wire Wire Line + 6750 10650 12500 10650 +Wire Wire Line + 12500 10650 12500 10450 +Wire Wire Line + 12500 10450 13250 10450 +Wire Wire Line + 13250 9700 12250 9700 +Wire Wire Line + 12250 9700 12250 9800 +Wire Wire Line + 12250 9800 10650 9800 +Wire Wire Line + 10650 9800 10650 10650 +Connection ~ 10650 10650 +Wire Wire Line + 13250 11150 12100 11150 +Connection ~ 12100 11150 +Wire Wire Line + 15850 8550 18100 8550 +Wire Wire Line + 16800 10650 18150 10650 +Wire Wire Line + 6750 10650 6750 10300 +Connection ~ 6750 10300 +Wire Wire Line + 6750 9950 6750 9650 +Connection ~ 6750 9650 +Wire Wire Line + 6750 9200 6750 8950 +Connection ~ 6750 8950 +$Comp +L d_inverter U35 +U 1 1 67815B9E +P 7500 4100 +F 0 "U35" H 7500 4000 60 0000 C CNN +F 1 "d_inverter" H 7500 4250 60 0000 C CNN +F 2 "" H 7550 4050 60 0000 C CNN +F 3 "" H 7550 4050 60 0000 C CNN + 1 7500 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 67815C4E +P 7450 4800 +F 0 "U34" H 7450 4700 60 0000 C CNN +F 1 "d_inverter" H 7450 4950 60 0000 C CNN +F 2 "" H 7500 4750 60 0000 C CNN +F 3 "" H 7500 4750 60 0000 C CNN + 1 7450 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 67815CF8 +P 7500 5450 +F 0 "U36" H 7500 5350 60 0000 C CNN +F 1 "d_inverter" H 7500 5600 60 0000 C CNN +F 2 "" H 7550 5400 60 0000 C CNN +F 3 "" H 7550 5400 60 0000 C CNN + 1 7500 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U38 +U 1 1 6781606F +P 7950 8950 +F 0 "U38" H 7950 8850 60 0000 C CNN +F 1 "d_inverter" H 7950 9100 60 0000 C CNN +F 2 "" H 8000 8900 60 0000 C CNN +F 3 "" H 8000 8900 60 0000 C CNN + 1 7950 8950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 6781613E +P 7900 9650 +F 0 "U37" H 7900 9550 60 0000 C CNN +F 1 "d_inverter" H 7900 9800 60 0000 C CNN +F 2 "" H 7950 9600 60 0000 C CNN +F 3 "" H 7950 9600 60 0000 C CNN + 1 7900 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 678161F7 +P 7950 10300 +F 0 "U39" H 7950 10200 60 0000 C CNN +F 1 "d_inverter" H 7950 10450 60 0000 C CNN +F 2 "" H 8000 10250 60 0000 C CNN +F 3 "" H 8000 10250 60 0000 C CNN + 1 7950 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 67817C3D +P 13700 3450 +F 0 "U20" H 13700 3450 60 0000 C CNN +F 1 "d_or" H 13700 3550 60 0000 C CNN +F 2 "" H 13700 3450 60 0000 C CNN +F 3 "" H 13700 3450 60 0000 C CNN + 1 13700 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 67817CC0 +P 14950 3750 +F 0 "U28" H 14950 3750 60 0000 C CNN +F 1 "d_or" H 14950 3850 60 0000 C CNN +F 2 "" H 14950 3750 60 0000 C CNN +F 3 "" H 14950 3750 60 0000 C CNN + 1 14950 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U40 +U 1 1 67817DB5 +P 16000 3700 +F 0 "U40" H 16000 3600 60 0000 C CNN +F 1 "d_inverter" H 16000 3850 60 0000 C CNN +F 2 "" H 16050 3650 60 0000 C CNN +F 3 "" H 16050 3650 60 0000 C CNN + 1 16000 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U41 +U 1 1 67817F5D +P 16850 5800 +F 0 "U41" H 16850 5700 60 0000 C CNN +F 1 "d_inverter" H 16850 5950 60 0000 C CNN +F 2 "" H 16900 5750 60 0000 C CNN +F 3 "" H 16900 5750 60 0000 C CNN + 1 16850 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U26 +U 1 1 67818050 +P 14700 5500 +F 0 "U26" H 14700 5500 60 0000 C CNN +F 1 "d_or" H 14700 5600 60 0000 C CNN +F 2 "" H 14700 5500 60 0000 C CNN +F 3 "" H 14700 5500 60 0000 C CNN + 1 14700 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U27 +U 1 1 678180E7 +P 14700 6250 +F 0 "U27" H 14700 6250 60 0000 C CNN +F 1 "d_or" H 14700 6350 60 0000 C CNN +F 2 "" H 14700 6250 60 0000 C CNN +F 3 "" H 14700 6250 60 0000 C CNN + 1 14700 6250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 67818172 +P 15900 5850 +F 0 "U32" H 15900 5850 60 0000 C CNN +F 1 "d_or" H 15900 5950 60 0000 C CNN +F 2 "" H 15900 5850 60 0000 C CNN +F 3 "" H 15900 5850 60 0000 C CNN + 1 15900 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16350 5800 16550 5800 +Wire Wire Line + 17150 5800 17750 5800 +Wire Wire Line + 15700 3700 15400 3700 +Wire Wire Line + 16300 3700 17750 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub new file mode 100644 index 00000000..713804f7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub @@ -0,0 +1,166 @@ +* Subcircuit SN54LS183 +.subckt SN54LS183 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54ls183\sn54ls183.cir +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad2_ net-_u18-pad2_ net-_u20-pad2_ d_and +* u4 net-_u2-pad1_ net-_u18-pad2_ net-_u28-pad2_ d_and +* u5 net-_u1-pad4_ net-_u2-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u1-pad1_ net-_u16-pad3_ d_and +* u6 net-_u2-pad1_ net-_u1-pad3_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u1-pad1_ net-_u17-pad3_ d_and +* u7 net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad4_ net-_u1-pad3_ net-_u19-pad1_ d_and +* u19 net-_u19-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad1_ net-_u25-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad11_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u21 net-_u12-pad3_ net-_u1-pad13_ net-_u21-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad12_ net-_u13-pad3_ d_and +* u22 net-_u13-pad3_ net-_u1-pad13_ net-_u22-pad3_ d_and +* u25 net-_u25-pad1_ net-_u10-pad3_ net-_u25-pad3_ d_nor +* u31 net-_u25-pad3_ net-_u11-pad3_ net-_u1-pad10_ d_nor +* u29 net-_u21-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nor +* u33 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad8_ d_nor +* u14 net-_u11-pad1_ net-_u10-pad1_ net-_u14-pad3_ d_and +* u23 net-_u14-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_and +* u15 net-_u1-pad11_ net-_u1-pad12_ net-_u15-pad3_ d_and +* u24 net-_u15-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_and +* u35 net-_u1-pad4_ net-_u2-pad1_ d_inverter +* u34 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u36 net-_u1-pad1_ net-_u18-pad2_ d_inverter +* u38 net-_u1-pad11_ net-_u11-pad1_ d_inverter +* u37 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u39 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u20 net-_u2-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u28 net-_u20-pad3_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u40 net-_u28-pad3_ net-_u1-pad5_ d_inverter +* u41 net-_u32-pad3_ net-_u1-pad6_ d_inverter +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_or +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_or +* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_or +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad2_ net-_u18-pad2_ ] net-_u20-pad2_ u3 +a3 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u28-pad2_ u4 +a4 [net-_u1-pad4_ net-_u2-pad2_ ] net-_u16-pad1_ u5 +a5 [net-_u16-pad1_ net-_u1-pad1_ ] net-_u16-pad3_ u16 +a6 [net-_u2-pad1_ net-_u1-pad3_ ] net-_u17-pad1_ u6 +a7 [net-_u17-pad1_ net-_u1-pad1_ ] net-_u17-pad3_ u17 +a8 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u18-pad1_ u7 +a9 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u19-pad1_ u8 +a11 [net-_u19-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a12 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u25-pad1_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a16 [net-_u12-pad3_ net-_u1-pad13_ ] net-_u21-pad3_ u21 +a17 [net-_u11-pad1_ net-_u1-pad12_ ] net-_u13-pad3_ u13 +a18 [net-_u13-pad3_ net-_u1-pad13_ ] net-_u22-pad3_ u22 +a19 [net-_u25-pad1_ net-_u10-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u25-pad3_ net-_u11-pad3_ ] net-_u1-pad10_ u31 +a21 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad8_ u33 +a24 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +a25 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u15-pad3_ u15 +a27 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a28 net-_u1-pad4_ net-_u2-pad1_ u35 +a29 net-_u1-pad3_ net-_u2-pad2_ u34 +a30 net-_u1-pad1_ net-_u18-pad2_ u36 +a31 net-_u1-pad11_ net-_u11-pad1_ u38 +a32 net-_u1-pad12_ net-_u10-pad1_ u37 +a33 net-_u1-pad13_ net-_u10-pad2_ u39 +a34 [net-_u2-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a35 [net-_u20-pad3_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a36 net-_u28-pad3_ net-_u1-pad5_ u40 +a37 net-_u32-pad3_ net-_u1-pad6_ u41 +a38 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a39 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a40 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN54LS183
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml b/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml new file mode 100644 index 00000000..ce7d687a --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u16 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u16><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u17 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u17><u20 name="type">d_nor<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u20><u28 name="type">d_nor<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u26 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u26><u27 name="type">d_nor<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u27><u32 name="type">d_nor<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u32><u7 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u7><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u8><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u9 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u12><u21 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u13><u22 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u22><u25 name="type">d_nor<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u25><u31 name="type">d_nor<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u31><u29 name="type">d_nor<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u29><u30 name="type">d_nor<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u30><u33 name="type">d_nor<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u14 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u14><u23 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u23><u15 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u15><u24 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u24><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34><u36 name="type">d_inverter<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u36><u38 name="type">d_inverter<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u38><u37 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u37><u39 name="type">d_inverter<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u39><u20 name="type">d_or<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u20><u28 name="type">d_or<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u28><u40 name="type">d_inverter<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u40><u41 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u41><u26 name="type">d_or<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u26><u27 name="type">d_or<field115 name="Enter Fall Delay (default=1.0e-9)" /><field116 name="Enter Input Load (default=1.0e-12)" /><field117 name="Enter Rise Delay (default=1.0e-9)" /></u27><u32 name="type">d_or<field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /></u32></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/analysis b/library/SubcircuitLibrary/SN54LS183/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/D.lib b/library/SubcircuitLibrary/SN55188/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN55188/NPN.lib b/library/SubcircuitLibrary/SN55188/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188/PNP.lib b/library/SubcircuitLibrary/SN55188/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188/SN55188-cache.lib b/library/SubcircuitLibrary/SN55188/SN55188-cache.lib new file mode 100644 index 00000000..e532722e --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# SN55188_0 +# +DEF SN55188_0 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "SN55188_0" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 200 450 -300 0 1 0 N +X Vcc+ 1 -600 100 200 R 50 50 1 1 I +X A 2 -100 400 200 D 50 50 1 1 I +X B 3 200 400 200 D 50 50 1 1 I +X gnd 4 0 -500 200 U 50 50 1 1 I +X Vcc- 5 -600 -200 200 R 50 50 1 1 I +X OUTPUT 6 650 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188/SN55188.cir b/library/SubcircuitLibrary/SN55188/SN55188.cir new file mode 100644 index 00000000..d12a8992 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188\SN55188.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 00:32:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Vcc+ Net-_U1-Pad2_ Net-_U1-Pad2_ gnd Vcc- Net-_U1-Pad3_ SN55188_0 +X3 Vcc+ Net-_U1-Pad9_ Net-_U1-Pad10_ gnd Vcc- Net-_U1-Pad8_ SN55188_0 +X1 Vcc+ Net-_U1-Pad4_ Net-_U1-Pad5_ gnd Vcc- Net-_U1-Pad6_ SN55188_0 +X4 Vcc+ Net-_U1-Pad12_ Net-_U1-Pad13_ gnd Vcc- Net-_U1-Pad11_ SN55188_0 +U1 Vcc- Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ gnd Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Vcc+ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188.cir.out b/library/SubcircuitLibrary/SN55188/SN55188.cir.out new file mode 100644 index 00000000..70d80115 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188\sn55188.cir + +.include SN55188_0.sub +x2 vcc+ net-_u1-pad2_ net-_u1-pad2_ gnd vcc- net-_u1-pad3_ SN55188_0 +x3 vcc+ net-_u1-pad9_ net-_u1-pad10_ gnd vcc- net-_u1-pad8_ SN55188_0 +x1 vcc+ net-_u1-pad4_ net-_u1-pad5_ gnd vcc- net-_u1-pad6_ SN55188_0 +x4 vcc+ net-_u1-pad12_ net-_u1-pad13_ gnd vcc- net-_u1-pad11_ SN55188_0 +* u1 vcc- net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ vcc+ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188.pro b/library/SubcircuitLibrary/SN55188/SN55188.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188/SN55188.sch b/library/SubcircuitLibrary/SN55188/SN55188.sch new file mode 100644 index 00000000..55a59692 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.sch @@ -0,0 +1,347 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SN55188_0 X2 +U 1 1 679A4CEC +P 5350 3700 +F 0 "X2" H 5350 3700 60 0000 C CNN +F 1 "SN55188_0" H 5350 3600 60 0000 C CNN +F 2 "" H 5350 3700 60 0001 C CNN +F 3 "" H 5350 3700 60 0001 C CNN + 1 5350 3700 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X3 +U 1 1 679A4D5D +P 7150 3700 +F 0 "X3" H 7150 3700 60 0000 C CNN +F 1 "SN55188_0" H 7150 3600 60 0000 C CNN +F 2 "" H 7150 3700 60 0001 C CNN +F 3 "" H 7150 3700 60 0001 C CNN + 1 7150 3700 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X1 +U 1 1 679A4D76 +P 5300 5100 +F 0 "X1" H 5300 5100 60 0000 C CNN +F 1 "SN55188_0" H 5300 5000 60 0000 C CNN +F 2 "" H 5300 5100 60 0001 C CNN +F 3 "" H 5300 5100 60 0001 C CNN + 1 5300 5100 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X4 +U 1 1 679A4D97 +P 7200 5150 +F 0 "X4" H 7200 5150 60 0000 C CNN +F 1 "SN55188_0" H 7200 5050 60 0000 C CNN +F 2 "" H 7200 5150 60 0001 C CNN +F 3 "" H 7200 5150 60 0001 C CNN + 1 7200 5150 + 1 0 0 -1 +$EndComp +Text GLabel 5500 4200 2 60 Input ~ 0 +gnd +Text GLabel 5450 5600 2 60 Input ~ 0 +gnd +Text GLabel 7350 5650 2 60 Input ~ 0 +gnd +Text GLabel 7300 4200 2 60 Input ~ 0 +gnd +Text GLabel 4600 3600 0 60 Input ~ 0 +Vcc+ +Text GLabel 4700 4800 0 60 Input ~ 0 +Vcc+ +Text GLabel 6550 3400 0 60 Input ~ 0 +Vcc+ +Text GLabel 6600 4850 0 60 Input ~ 0 +Vcc+ +Text GLabel 4700 5550 0 60 Input ~ 0 +Vcc- +Text GLabel 6600 5550 0 60 Input ~ 0 +Vcc- +Text GLabel 4600 3900 0 60 Input ~ 0 +Vcc- +Text GLabel 6550 4100 0 60 Input ~ 0 +Vcc- +$Comp +L PORT U1 +U 14 1 679A4FA0 +P 6150 3550 +F 0 "U1" H 6200 3650 30 0000 C CNN +F 1 "PORT" H 6150 3550 30 0000 C CNN +F 2 "" H 6150 3550 60 0000 C CNN +F 3 "" H 6150 3550 60 0000 C CNN + 14 6150 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 679A4FBF +P 7700 4600 +F 0 "U1" H 7750 4700 30 0000 C CNN +F 1 "PORT" H 7700 4600 30 0000 C CNN +F 2 "" H 7700 4600 60 0000 C CNN +F 3 "" H 7700 4600 60 0000 C CNN + 13 7700 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A4FF6 +P 6350 5150 +F 0 "U1" H 6400 5250 30 0000 C CNN +F 1 "PORT" H 6350 5150 30 0000 C CNN +F 2 "" H 6350 5150 60 0000 C CNN +F 3 "" H 6350 5150 60 0000 C CNN + 6 6350 5150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 679A5019 +P 6750 4200 +F 0 "U1" H 6800 4300 30 0000 C CNN +F 1 "PORT" H 6750 4200 30 0000 C CNN +F 2 "" H 6750 4200 60 0000 C CNN +F 3 "" H 6750 4200 60 0000 C CNN + 7 6750 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679A503E +P 7850 4000 +F 0 "U1" H 7900 4100 30 0000 C CNN +F 1 "PORT" H 7850 4000 30 0000 C CNN +F 2 "" H 7850 4000 60 0000 C CNN +F 3 "" H 7850 4000 60 0000 C CNN + 8 7850 4000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 679A5065 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 9 6750 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 679A508E +P 7650 3150 +F 0 "U1" H 7700 3250 30 0000 C CNN +F 1 "PORT" H 7650 3150 30 0000 C CNN +F 2 "" H 7650 3150 60 0000 C CNN +F 3 "" H 7650 3150 60 0000 C CNN + 10 7650 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 679A50B9 +P 8250 5200 +F 0 "U1" H 8300 5300 30 0000 C CNN +F 1 "PORT" H 8250 5200 30 0000 C CNN +F 2 "" H 8250 5200 60 0000 C CNN +F 3 "" H 8250 5200 60 0000 C CNN + 11 8250 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A50E6 +P 4850 4450 +F 0 "U1" H 4900 4550 30 0000 C CNN +F 1 "PORT" H 4850 4450 30 0000 C CNN +F 2 "" H 4850 4450 60 0000 C CNN +F 3 "" H 4850 4450 60 0000 C CNN + 4 4850 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A5115 +P 5850 4450 +F 0 "U1" H 5900 4550 30 0000 C CNN +F 1 "PORT" H 5850 4450 30 0000 C CNN +F 2 "" H 5850 4450 60 0000 C CNN +F 3 "" H 5850 4450 60 0000 C CNN + 5 5850 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 679A5146 +P 6800 4600 +F 0 "U1" H 6850 4700 30 0000 C CNN +F 1 "PORT" H 6800 4600 30 0000 C CNN +F 2 "" H 6800 4600 60 0000 C CNN +F 3 "" H 6800 4600 60 0000 C CNN + 12 6800 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A5179 +P 6300 3750 +F 0 "U1" H 6350 3850 30 0000 C CNN +F 1 "PORT" H 6300 3750 30 0000 C CNN +F 2 "" H 6300 3750 60 0000 C CNN +F 3 "" H 6300 3750 60 0000 C CNN + 3 6300 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A51C2 +P 5100 3000 +F 0 "U1" H 5150 3100 30 0000 C CNN +F 1 "PORT" H 5100 3000 30 0000 C CNN +F 2 "" H 5100 3000 60 0000 C CNN +F 3 "" H 5100 3000 60 0000 C CNN + 2 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A51F9 +P 6200 3950 +F 0 "U1" H 6250 4050 30 0000 C CNN +F 1 "PORT" H 6200 3950 30 0000 C CNN +F 2 "" H 6200 3950 60 0000 C CNN +F 3 "" H 6200 3950 60 0000 C CNN + 1 6200 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 5600 5450 5600 +Wire Wire Line + 7200 5650 7350 5650 +Wire Wire Line + 7000 4200 7300 4200 +Wire Wire Line + 5350 4200 5500 4200 +Wire Wire Line + 4750 3600 4600 3600 +Wire Wire Line + 4750 3900 4600 3900 +Wire Wire Line + 6550 3600 6550 3400 +Wire Wire Line + 6550 3900 6550 4100 +Wire Wire Line + 6600 5050 6600 4850 +Wire Wire Line + 6600 5350 6600 5550 +Wire Wire Line + 4700 5300 4700 5550 +Wire Wire Line + 4700 5000 4700 4800 +Wire Wire Line + 5250 3300 5550 3300 +Wire Wire Line + 5350 3300 5350 3000 +Connection ~ 5350 3300 +Wire Wire Line + 6450 3950 6550 3950 +Connection ~ 6550 3950 +Wire Wire Line + 6400 3550 6550 3550 +Connection ~ 6550 3550 +Connection ~ 7150 4200 +Wire Wire Line + 7050 3300 7050 3150 +Wire Wire Line + 7050 3150 7000 3150 +Wire Wire Line + 7350 3300 7350 3150 +Wire Wire Line + 7350 3150 7400 3150 +Wire Wire Line + 7100 4750 7100 4600 +Wire Wire Line + 7100 4600 7050 4600 +Wire Wire Line + 7400 4750 7400 4600 +Wire Wire Line + 7400 4600 7450 4600 +Wire Wire Line + 5200 4700 5200 4450 +Wire Wire Line + 5200 4450 5100 4450 +Wire Wire Line + 5500 4700 5500 4450 +Wire Wire Line + 5500 4450 5600 4450 +Wire Wire Line + 7800 3750 7850 3750 +Wire Wire Line + 7850 5200 8000 5200 +Wire Wire Line + 5950 5150 6100 5150 +Wire Wire Line + 6000 3750 6050 3750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188/SN55188.sub b/library/SubcircuitLibrary/SN55188/SN55188.sub new file mode 100644 index 00000000..eedf8204 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.sub @@ -0,0 +1,11 @@ +* Subcircuit SN55188 +.subckt SN55188 vcc- net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ vcc+ +* c:\fossee\esim\library\subcircuitlibrary\sn55188\sn55188.cir +.include SN55188_0.sub +x2 vcc+ net-_u1-pad2_ net-_u1-pad2_ gnd vcc- net-_u1-pad3_ SN55188_0 +x3 vcc+ net-_u1-pad9_ net-_u1-pad10_ gnd vcc- net-_u1-pad8_ SN55188_0 +x1 vcc+ net-_u1-pad4_ net-_u1-pad5_ gnd vcc- net-_u1-pad6_ SN55188_0 +x4 vcc+ net-_u1-pad12_ net-_u1-pad13_ gnd vcc- net-_u1-pad11_ SN55188_0 +* Control Statements + +.ends SN55188
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib b/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib new file mode 100644 index 00000000..fa8f67b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.cir b/library/SubcircuitLibrary/SN55188/SN55188_0.cir new file mode 100644 index 00000000..f4dc9203 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0\SN55188_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:31:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D4-Pad2_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_D9-Pad1_ eSim_NPN +Q3 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q5 Net-_D5-Pad2_ Net-_Q3-Pad3_ Net-_Q2-Pad2_ eSim_NPN +R3 Net-_Q1-Pad1_ Net-_D9-Pad1_ 10k +R1 Net-_D4-Pad2_ Net-_Q1-Pad2_ 3.6k +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +R2 Net-_D8-Pad2_ Net-_D1-Pad1_ 8.2k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_D8-Pad2_ Net-_D5-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R4 Net-_D8-Pad2_ Net-_D5-Pad1_ 6.2k +R6 Net-_Q4-Pad3_ Net-_D6-Pad2_ 70 +D6 Net-_D5-Pad2_ Net-_D6-Pad2_ eSim_Diode +D7 Net-_D6-Pad2_ Net-_D5-Pad2_ eSim_Diode +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +R7 Net-_Q2-Pad2_ Net-_D9-Pad1_ 70 +R5 Net-_Q3-Pad3_ Net-_D9-Pad1_ 3.7k +D9 Net-_D9-Pad1_ Net-_D6-Pad2_ eSim_Diode +R8 Net-_D6-Pad2_ Net-_R8-Pad2_ 300 +D8 Net-_D6-Pad2_ Net-_D8-Pad2_ eSim_Diode +U1 Net-_D8-Pad2_ Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_Q1-Pad2_ Net-_D9-Pad1_ Net-_R8-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out b/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out new file mode 100644 index 00000000..e8b8112c --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out @@ -0,0 +1,37 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* u1 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.pro b/library/SubcircuitLibrary/SN55188/SN55188_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.sch b/library/SubcircuitLibrary/SN55188/SN55188_0.sch new file mode 100644 index 00000000..d377648b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.sch @@ -0,0 +1,482 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188_0-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 679A4558 +P 5150 3900 +F 0 "Q1" H 5050 3950 50 0000 R CNN +F 1 "eSim_PNP" H 5100 4050 50 0000 R CNN +F 2 "" H 5350 4000 29 0000 C CNN +F 3 "" H 5150 3900 60 0000 C CNN + 1 5150 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A45B5 +P 6150 5150 +F 0 "Q2" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A45D0 +P 6500 4500 +F 0 "Q3" H 6400 4550 50 0000 R CNN +F 1 "eSim_NPN" H 6450 4650 50 0000 R CNN +F 2 "" H 6700 4600 29 0000 C CNN +F 3 "" H 6500 4500 60 0000 C CNN + 1 6500 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 679A45F1 +P 7650 4750 +F 0 "Q5" H 7550 4800 50 0000 R CNN +F 1 "eSim_NPN" H 7600 4900 50 0000 R CNN +F 2 "" H 7850 4850 29 0000 C CNN +F 3 "" H 7650 4750 60 0000 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 679A462D +P 5200 4900 +F 0 "R3" H 5250 5030 50 0000 C CNN +F 1 "10k" H 5250 4850 50 0000 C CNN +F 2 "" H 5250 4880 30 0000 C CNN +F 3 "" V 5250 4950 30 0000 C CNN + 1 5200 4900 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 679A468F +P 4700 3600 +F 0 "R1" H 4750 3730 50 0000 C CNN +F 1 "3.6k" H 4750 3550 50 0000 C CNN +F 2 "" H 4750 3580 30 0000 C CNN +F 3 "" V 4750 3650 30 0000 C CNN + 1 4700 3600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 679A46FA +P 5250 3150 +F 0 "D4" H 5250 3250 50 0000 C CNN +F 1 "eSim_Diode" H 5250 3050 50 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 679A4721 +P 5250 2750 +F 0 "D3" H 5250 2850 50 0000 C CNN +F 1 "eSim_Diode" H 5250 2650 50 0000 C CNN +F 2 "" H 5250 2750 60 0000 C CNN +F 3 "" H 5250 2750 60 0000 C CNN + 1 5250 2750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 679A492E +P 5200 2000 +F 0 "R2" H 5250 2130 50 0000 C CNN +F 1 "8.2k" H 5250 1950 50 0000 C CNN +F 2 "" H 5250 1980 30 0000 C CNN +F 3 "" V 5250 2050 30 0000 C CNN + 1 5200 2000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 679A4971 +P 4650 2300 +F 0 "D1" H 4650 2400 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2200 50 0000 C CNN +F 2 "" H 4650 2300 60 0000 C CNN +F 3 "" H 4650 2300 60 0000 C CNN + 1 4650 2300 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 679A49A2 +P 4650 2550 +F 0 "D2" H 4650 2650 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2450 50 0000 C CNN +F 2 "" H 4650 2550 60 0000 C CNN +F 3 "" H 4650 2550 60 0000 C CNN + 1 4650 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 679A4B4C +P 7050 2200 +F 0 "Q4" H 6950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 7000 2350 50 0000 R CNN +F 2 "" H 7250 2300 29 0000 C CNN +F 3 "" H 7050 2200 60 0000 C CNN + 1 7050 2200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 679A4B8A +P 6350 1950 +F 0 "R4" H 6400 2080 50 0000 C CNN +F 1 "6.2k" H 6400 1900 50 0000 C CNN +F 2 "" H 6400 1930 30 0000 C CNN +F 3 "" V 6400 2000 30 0000 C CNN + 1 6350 1950 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A4C18 +P 7100 2800 +F 0 "R6" H 7150 2930 50 0000 C CNN +F 1 "70" H 7150 2750 50 0000 C CNN +F 2 "" H 7150 2780 30 0000 C CNN +F 3 "" V 7150 2850 30 0000 C CNN + 1 7100 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 679A4CD7 +P 7150 3200 +F 0 "D6" H 7150 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7150 3100 50 0000 C CNN +F 2 "" H 7150 3200 60 0000 C CNN +F 3 "" H 7150 3200 60 0000 C CNN + 1 7150 3200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 679A4D12 +P 7950 3200 +F 0 "D7" H 7950 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7950 3100 50 0000 C CNN +F 2 "" H 7950 3200 60 0000 C CNN +F 3 "" H 7950 3200 60 0000 C CNN + 1 7950 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 679A4DFD +P 6900 3350 +F 0 "D5" H 6900 3450 50 0000 C CNN +F 1 "eSim_Diode" H 6900 3250 50 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 1 6900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5250 4800 +Wire Wire Line + 5250 5100 5250 5350 +Wire Wire Line + 4350 5350 8450 5350 +Wire Wire Line + 6300 4500 5250 4500 +Connection ~ 5250 4500 +Wire Wire Line + 6050 4950 6050 4500 +Connection ~ 6050 4500 +Connection ~ 5250 5350 +Wire Wire Line + 4750 3800 4750 3900 +Wire Wire Line + 4250 3900 4950 3900 +Wire Wire Line + 4750 3500 4750 3400 +Wire Wire Line + 4750 3400 5250 3400 +Wire Wire Line + 5250 3300 5250 3700 +Connection ~ 4750 3900 +Wire Wire Line + 5250 2900 5250 3000 +Connection ~ 5250 3400 +Wire Wire Line + 5250 2600 5250 2200 +Wire Wire Line + 4800 2550 5250 2550 +Connection ~ 5250 2550 +Wire Wire Line + 4800 2300 5250 2300 +Connection ~ 5250 2300 +Wire Wire Line + 4500 2300 4100 2300 +Wire Wire Line + 4500 2550 4100 2550 +Wire Wire Line + 5250 1900 5250 1700 +Wire Wire Line + 4100 1700 8100 1700 +Wire Wire Line + 7150 1700 7150 2000 +Connection ~ 5250 1700 +Wire Wire Line + 6400 1850 6400 1700 +Connection ~ 6400 1700 +Wire Wire Line + 6400 2150 6400 3350 +Wire Wire Line + 6400 2200 6850 2200 +Wire Wire Line + 7150 2400 7150 2700 +Wire Wire Line + 7150 3000 8750 3000 +Wire Wire Line + 7050 3350 7950 3350 +Wire Wire Line + 7150 3050 7150 3000 +Wire Wire Line + 7950 3050 7950 3000 +Connection ~ 7950 3000 +Wire Wire Line + 6400 3350 6750 3350 +Wire Wire Line + 6700 3350 6700 3500 +Connection ~ 7150 3350 +Connection ~ 6700 3350 +Connection ~ 6400 2200 +Connection ~ 5250 4200 +Wire Wire Line + 6600 4300 6600 3500 +Wire Wire Line + 6600 3500 6700 3500 +$Comp +L resistor R7 +U 1 1 679A536E +P 7700 5100 +F 0 "R7" H 7750 5230 50 0000 C CNN +F 1 "70" H 7750 5050 50 0000 C CNN +F 2 "" H 7750 5080 30 0000 C CNN +F 3 "" V 7750 5150 30 0000 C CNN + 1 7700 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7750 5350 7750 5300 +Connection ~ 6050 5350 +Wire Wire Line + 7750 5000 7750 4950 +Wire Wire Line + 6350 5150 7550 5150 +Wire Wire Line + 7550 5150 7550 5000 +Wire Wire Line + 7550 5000 7750 5000 +Wire Wire Line + 6600 4700 6600 4800 +Wire Wire Line + 6600 4800 7450 4800 +Wire Wire Line + 7450 4800 7450 4750 +$Comp +L resistor R5 +U 1 1 679A55E9 +P 7000 5000 +F 0 "R5" H 7050 5130 50 0000 C CNN +F 1 "3.7k" H 7050 4950 50 0000 C CNN +F 2 "" H 7050 4980 30 0000 C CNN +F 3 "" V 7050 5050 30 0000 C CNN + 1 7000 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7050 4900 7050 4800 +Connection ~ 7050 4800 +Wire Wire Line + 7050 5200 7050 5350 +Connection ~ 7050 5350 +$Comp +L eSim_Diode D9 +U 1 1 679A5738 +P 8450 4050 +F 0 "D9" H 8450 4150 50 0000 C CNN +F 1 "eSim_Diode" H 8450 3950 50 0000 C CNN +F 2 "" H 8450 4050 60 0000 C CNN +F 3 "" H 8450 4050 60 0000 C CNN + 1 8450 4050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8450 5350 8450 4200 +Connection ~ 7750 5350 +Wire Wire Line + 8450 3900 8450 3000 +Connection ~ 8450 3000 +$Comp +L resistor R8 +U 1 1 679A5A13 +P 8850 3050 +F 0 "R8" H 8900 3180 50 0000 C CNN +F 1 "300" H 8900 3000 50 0000 C CNN +F 2 "" H 8900 3030 30 0000 C CNN +F 3 "" V 8900 3100 30 0000 C CNN + 1 8850 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 3000 9250 3000 +$Comp +L eSim_Diode D8 +U 1 1 679A5C7A +P 8100 2150 +F 0 "D8" H 8100 2250 50 0000 C CNN +F 1 "eSim_Diode" H 8100 2050 50 0000 C CNN +F 2 "" H 8100 2150 60 0000 C CNN +F 3 "" H 8100 2150 60 0000 C CNN + 1 8100 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8100 2300 8100 3000 +Connection ~ 8100 3000 +Wire Wire Line + 8100 1700 8100 2000 +Connection ~ 7150 1700 +$Comp +L PORT U1 +U 2 1 679A6ACB +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A6B0E +P 4000 3900 +F 0 "U1" H 4050 4000 30 0000 C CNN +F 1 "PORT" H 4000 3900 30 0000 C CNN +F 2 "" H 4000 3900 60 0000 C CNN +F 3 "" H 4000 3900 60 0000 C CNN + 4 4000 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A6B53 +P 3850 2550 +F 0 "U1" H 3900 2650 30 0000 C CNN +F 1 "PORT" H 3850 2550 30 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 3 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A6BB3 +P 3850 1700 +F 0 "U1" H 3900 1800 30 0000 C CNN +F 1 "PORT" H 3850 1700 30 0000 C CNN +F 2 "" H 3850 1700 60 0000 C CNN +F 3 "" H 3850 1700 60 0000 C CNN + 1 3850 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A6BFC +P 4100 5350 +F 0 "U1" H 4150 5450 30 0000 C CNN +F 1 "PORT" H 4100 5350 30 0000 C CNN +F 2 "" H 4100 5350 60 0000 C CNN +F 3 "" H 4100 5350 60 0000 C CNN + 5 4100 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A6C47 +P 9500 3000 +F 0 "U1" H 9550 3100 30 0000 C CNN +F 1 "PORT" H 9500 3000 30 0000 C CNN +F 2 "" H 9500 3000 60 0000 C CNN +F 3 "" H 9500 3000 60 0000 C CNN + 6 9500 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 3350 7950 4550 +Wire Wire Line + 7950 4550 7750 4550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.sub b/library/SubcircuitLibrary/SN55188/SN55188_0.sub new file mode 100644 index 00000000..c9c0104a --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.sub @@ -0,0 +1,31 @@ +* Subcircuit SN55188_0 +.subckt SN55188_0 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* Control Statements + +.ends SN55188_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml b/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml new file mode 100644 index 00000000..5ada64f3 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml b/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml new file mode 100644 index 00000000..61a626af --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x1><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/analysis b/library/SubcircuitLibrary/SN55188/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/D.lib b/library/SubcircuitLibrary/SN55188_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN55188_0/NPN.lib b/library/SubcircuitLibrary/SN55188_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188_0/PNP.lib b/library/SubcircuitLibrary/SN55188_0/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib b/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib new file mode 100644 index 00000000..fa8f67b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir new file mode 100644 index 00000000..f4dc9203 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0\SN55188_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:31:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D4-Pad2_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_D9-Pad1_ eSim_NPN +Q3 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q5 Net-_D5-Pad2_ Net-_Q3-Pad3_ Net-_Q2-Pad2_ eSim_NPN +R3 Net-_Q1-Pad1_ Net-_D9-Pad1_ 10k +R1 Net-_D4-Pad2_ Net-_Q1-Pad2_ 3.6k +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +R2 Net-_D8-Pad2_ Net-_D1-Pad1_ 8.2k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_D8-Pad2_ Net-_D5-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R4 Net-_D8-Pad2_ Net-_D5-Pad1_ 6.2k +R6 Net-_Q4-Pad3_ Net-_D6-Pad2_ 70 +D6 Net-_D5-Pad2_ Net-_D6-Pad2_ eSim_Diode +D7 Net-_D6-Pad2_ Net-_D5-Pad2_ eSim_Diode +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +R7 Net-_Q2-Pad2_ Net-_D9-Pad1_ 70 +R5 Net-_Q3-Pad3_ Net-_D9-Pad1_ 3.7k +D9 Net-_D9-Pad1_ Net-_D6-Pad2_ eSim_Diode +R8 Net-_D6-Pad2_ Net-_R8-Pad2_ 300 +D8 Net-_D6-Pad2_ Net-_D8-Pad2_ eSim_Diode +U1 Net-_D8-Pad2_ Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_Q1-Pad2_ Net-_D9-Pad1_ Net-_R8-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out new file mode 100644 index 00000000..e8b8112c --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out @@ -0,0 +1,37 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* u1 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro b/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch new file mode 100644 index 00000000..d377648b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch @@ -0,0 +1,482 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188_0-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 679A4558 +P 5150 3900 +F 0 "Q1" H 5050 3950 50 0000 R CNN +F 1 "eSim_PNP" H 5100 4050 50 0000 R CNN +F 2 "" H 5350 4000 29 0000 C CNN +F 3 "" H 5150 3900 60 0000 C CNN + 1 5150 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A45B5 +P 6150 5150 +F 0 "Q2" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A45D0 +P 6500 4500 +F 0 "Q3" H 6400 4550 50 0000 R CNN +F 1 "eSim_NPN" H 6450 4650 50 0000 R CNN +F 2 "" H 6700 4600 29 0000 C CNN +F 3 "" H 6500 4500 60 0000 C CNN + 1 6500 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 679A45F1 +P 7650 4750 +F 0 "Q5" H 7550 4800 50 0000 R CNN +F 1 "eSim_NPN" H 7600 4900 50 0000 R CNN +F 2 "" H 7850 4850 29 0000 C CNN +F 3 "" H 7650 4750 60 0000 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 679A462D +P 5200 4900 +F 0 "R3" H 5250 5030 50 0000 C CNN +F 1 "10k" H 5250 4850 50 0000 C CNN +F 2 "" H 5250 4880 30 0000 C CNN +F 3 "" V 5250 4950 30 0000 C CNN + 1 5200 4900 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 679A468F +P 4700 3600 +F 0 "R1" H 4750 3730 50 0000 C CNN +F 1 "3.6k" H 4750 3550 50 0000 C CNN +F 2 "" H 4750 3580 30 0000 C CNN +F 3 "" V 4750 3650 30 0000 C CNN + 1 4700 3600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 679A46FA +P 5250 3150 +F 0 "D4" H 5250 3250 50 0000 C CNN +F 1 "eSim_Diode" H 5250 3050 50 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 679A4721 +P 5250 2750 +F 0 "D3" H 5250 2850 50 0000 C CNN +F 1 "eSim_Diode" H 5250 2650 50 0000 C CNN +F 2 "" H 5250 2750 60 0000 C CNN +F 3 "" H 5250 2750 60 0000 C CNN + 1 5250 2750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 679A492E +P 5200 2000 +F 0 "R2" H 5250 2130 50 0000 C CNN +F 1 "8.2k" H 5250 1950 50 0000 C CNN +F 2 "" H 5250 1980 30 0000 C CNN +F 3 "" V 5250 2050 30 0000 C CNN + 1 5200 2000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 679A4971 +P 4650 2300 +F 0 "D1" H 4650 2400 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2200 50 0000 C CNN +F 2 "" H 4650 2300 60 0000 C CNN +F 3 "" H 4650 2300 60 0000 C CNN + 1 4650 2300 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 679A49A2 +P 4650 2550 +F 0 "D2" H 4650 2650 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2450 50 0000 C CNN +F 2 "" H 4650 2550 60 0000 C CNN +F 3 "" H 4650 2550 60 0000 C CNN + 1 4650 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 679A4B4C +P 7050 2200 +F 0 "Q4" H 6950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 7000 2350 50 0000 R CNN +F 2 "" H 7250 2300 29 0000 C CNN +F 3 "" H 7050 2200 60 0000 C CNN + 1 7050 2200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 679A4B8A +P 6350 1950 +F 0 "R4" H 6400 2080 50 0000 C CNN +F 1 "6.2k" H 6400 1900 50 0000 C CNN +F 2 "" H 6400 1930 30 0000 C CNN +F 3 "" V 6400 2000 30 0000 C CNN + 1 6350 1950 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A4C18 +P 7100 2800 +F 0 "R6" H 7150 2930 50 0000 C CNN +F 1 "70" H 7150 2750 50 0000 C CNN +F 2 "" H 7150 2780 30 0000 C CNN +F 3 "" V 7150 2850 30 0000 C CNN + 1 7100 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 679A4CD7 +P 7150 3200 +F 0 "D6" H 7150 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7150 3100 50 0000 C CNN +F 2 "" H 7150 3200 60 0000 C CNN +F 3 "" H 7150 3200 60 0000 C CNN + 1 7150 3200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 679A4D12 +P 7950 3200 +F 0 "D7" H 7950 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7950 3100 50 0000 C CNN +F 2 "" H 7950 3200 60 0000 C CNN +F 3 "" H 7950 3200 60 0000 C CNN + 1 7950 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 679A4DFD +P 6900 3350 +F 0 "D5" H 6900 3450 50 0000 C CNN +F 1 "eSim_Diode" H 6900 3250 50 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 1 6900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5250 4800 +Wire Wire Line + 5250 5100 5250 5350 +Wire Wire Line + 4350 5350 8450 5350 +Wire Wire Line + 6300 4500 5250 4500 +Connection ~ 5250 4500 +Wire Wire Line + 6050 4950 6050 4500 +Connection ~ 6050 4500 +Connection ~ 5250 5350 +Wire Wire Line + 4750 3800 4750 3900 +Wire Wire Line + 4250 3900 4950 3900 +Wire Wire Line + 4750 3500 4750 3400 +Wire Wire Line + 4750 3400 5250 3400 +Wire Wire Line + 5250 3300 5250 3700 +Connection ~ 4750 3900 +Wire Wire Line + 5250 2900 5250 3000 +Connection ~ 5250 3400 +Wire Wire Line + 5250 2600 5250 2200 +Wire Wire Line + 4800 2550 5250 2550 +Connection ~ 5250 2550 +Wire Wire Line + 4800 2300 5250 2300 +Connection ~ 5250 2300 +Wire Wire Line + 4500 2300 4100 2300 +Wire Wire Line + 4500 2550 4100 2550 +Wire Wire Line + 5250 1900 5250 1700 +Wire Wire Line + 4100 1700 8100 1700 +Wire Wire Line + 7150 1700 7150 2000 +Connection ~ 5250 1700 +Wire Wire Line + 6400 1850 6400 1700 +Connection ~ 6400 1700 +Wire Wire Line + 6400 2150 6400 3350 +Wire Wire Line + 6400 2200 6850 2200 +Wire Wire Line + 7150 2400 7150 2700 +Wire Wire Line + 7150 3000 8750 3000 +Wire Wire Line + 7050 3350 7950 3350 +Wire Wire Line + 7150 3050 7150 3000 +Wire Wire Line + 7950 3050 7950 3000 +Connection ~ 7950 3000 +Wire Wire Line + 6400 3350 6750 3350 +Wire Wire Line + 6700 3350 6700 3500 +Connection ~ 7150 3350 +Connection ~ 6700 3350 +Connection ~ 6400 2200 +Connection ~ 5250 4200 +Wire Wire Line + 6600 4300 6600 3500 +Wire Wire Line + 6600 3500 6700 3500 +$Comp +L resistor R7 +U 1 1 679A536E +P 7700 5100 +F 0 "R7" H 7750 5230 50 0000 C CNN +F 1 "70" H 7750 5050 50 0000 C CNN +F 2 "" H 7750 5080 30 0000 C CNN +F 3 "" V 7750 5150 30 0000 C CNN + 1 7700 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7750 5350 7750 5300 +Connection ~ 6050 5350 +Wire Wire Line + 7750 5000 7750 4950 +Wire Wire Line + 6350 5150 7550 5150 +Wire Wire Line + 7550 5150 7550 5000 +Wire Wire Line + 7550 5000 7750 5000 +Wire Wire Line + 6600 4700 6600 4800 +Wire Wire Line + 6600 4800 7450 4800 +Wire Wire Line + 7450 4800 7450 4750 +$Comp +L resistor R5 +U 1 1 679A55E9 +P 7000 5000 +F 0 "R5" H 7050 5130 50 0000 C CNN +F 1 "3.7k" H 7050 4950 50 0000 C CNN +F 2 "" H 7050 4980 30 0000 C CNN +F 3 "" V 7050 5050 30 0000 C CNN + 1 7000 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7050 4900 7050 4800 +Connection ~ 7050 4800 +Wire Wire Line + 7050 5200 7050 5350 +Connection ~ 7050 5350 +$Comp +L eSim_Diode D9 +U 1 1 679A5738 +P 8450 4050 +F 0 "D9" H 8450 4150 50 0000 C CNN +F 1 "eSim_Diode" H 8450 3950 50 0000 C CNN +F 2 "" H 8450 4050 60 0000 C CNN +F 3 "" H 8450 4050 60 0000 C CNN + 1 8450 4050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8450 5350 8450 4200 +Connection ~ 7750 5350 +Wire Wire Line + 8450 3900 8450 3000 +Connection ~ 8450 3000 +$Comp +L resistor R8 +U 1 1 679A5A13 +P 8850 3050 +F 0 "R8" H 8900 3180 50 0000 C CNN +F 1 "300" H 8900 3000 50 0000 C CNN +F 2 "" H 8900 3030 30 0000 C CNN +F 3 "" V 8900 3100 30 0000 C CNN + 1 8850 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 3000 9250 3000 +$Comp +L eSim_Diode D8 +U 1 1 679A5C7A +P 8100 2150 +F 0 "D8" H 8100 2250 50 0000 C CNN +F 1 "eSim_Diode" H 8100 2050 50 0000 C CNN +F 2 "" H 8100 2150 60 0000 C CNN +F 3 "" H 8100 2150 60 0000 C CNN + 1 8100 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8100 2300 8100 3000 +Connection ~ 8100 3000 +Wire Wire Line + 8100 1700 8100 2000 +Connection ~ 7150 1700 +$Comp +L PORT U1 +U 2 1 679A6ACB +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A6B0E +P 4000 3900 +F 0 "U1" H 4050 4000 30 0000 C CNN +F 1 "PORT" H 4000 3900 30 0000 C CNN +F 2 "" H 4000 3900 60 0000 C CNN +F 3 "" H 4000 3900 60 0000 C CNN + 4 4000 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A6B53 +P 3850 2550 +F 0 "U1" H 3900 2650 30 0000 C CNN +F 1 "PORT" H 3850 2550 30 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 3 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A6BB3 +P 3850 1700 +F 0 "U1" H 3900 1800 30 0000 C CNN +F 1 "PORT" H 3850 1700 30 0000 C CNN +F 2 "" H 3850 1700 60 0000 C CNN +F 3 "" H 3850 1700 60 0000 C CNN + 1 3850 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A6BFC +P 4100 5350 +F 0 "U1" H 4150 5450 30 0000 C CNN +F 1 "PORT" H 4100 5350 30 0000 C CNN +F 2 "" H 4100 5350 60 0000 C CNN +F 3 "" H 4100 5350 60 0000 C CNN + 5 4100 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A6C47 +P 9500 3000 +F 0 "U1" H 9550 3100 30 0000 C CNN +F 1 "PORT" H 9500 3000 30 0000 C CNN +F 2 "" H 9500 3000 60 0000 C CNN +F 3 "" H 9500 3000 60 0000 C CNN + 6 9500 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 3350 7950 4550 +Wire Wire Line + 7950 4550 7750 4550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub new file mode 100644 index 00000000..c9c0104a --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub @@ -0,0 +1,31 @@ +* Subcircuit SN55188_0 +.subckt SN55188_0 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* Control Statements + +.ends SN55188_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml b/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml new file mode 100644 index 00000000..5ada64f3 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/analysis b/library/SubcircuitLibrary/SN55188_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/3_and-cache.lib b/library/SubcircuitLibrary/SN74351/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir b/library/SubcircuitLibrary/SN74351/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir.out b/library/SubcircuitLibrary/SN74351/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.pro b/library/SubcircuitLibrary/SN74351/3_and.pro new file mode 100644 index 00000000..da3e199e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74351/3_and.sch b/library/SubcircuitLibrary/SN74351/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/3_and.sub b/library/SubcircuitLibrary/SN74351/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and-cache.lib b/library/SubcircuitLibrary/SN74351/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and-rescue.lib b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir b/library/SubcircuitLibrary/SN74351/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir.out b/library/SubcircuitLibrary/SN74351/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.pro b/library/SubcircuitLibrary/SN74351/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/5_and.sch b/library/SubcircuitLibrary/SN74351/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/5_and.sub b/library/SubcircuitLibrary/SN74351/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351-cache.lib b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib new file mode 100644 index 00000000..212e1ab7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir b/library/SubcircuitLibrary/SN74351/SN74351.cir new file mode 100644 index 00000000..f13d0354 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN74351\SN74351.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 22:36:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad6_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad1_ 5_and +X2 Net-_U1-Pad7_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad2_ 5_and +X3 Net-_U1-Pad8_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad1_ 5_and +X4 Net-_U1-Pad9_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad2_ 5_and +X5 Net-_U1-Pad14_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad1_ 5_and +X6 Net-_U1-Pad13_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad2_ 5_and +X7 Net-_U1-Pad12_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad1_ 5_and +X8 Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad2_ 5_and +X9 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad11_ Net-_U8-Pad1_ 5_and +X10 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U1-Pad12_ Net-_U8-Pad2_ 5_and +X11 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad13_ Net-_U10-Pad1_ 5_and +X12 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U10-Pad2_ 5_and +X13 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad15_ Net-_U12-Pad1_ 5_and +X14 Net-_U20-Pad1_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad16_ Net-_U12-Pad2_ 5_and +X15 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad17_ Net-_U13-Pad1_ 5_and +X16 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad18_ Net-_U13-Pad2_ 5_and +U5 Net-_U1-Pad2_ Net-_U20-Pad1_ d_inverter +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad4_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad5_ Net-_U4-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad1_ d_and +U21 Net-_U20-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad19_ d_and +U18 Net-_U14-Pad3_ Net-_U16-Pad3_ Net-_U18-Pad3_ d_or +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U16-Pad1_ d_or +U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U14-Pad2_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U14-Pad1_ d_or +U19 Net-_U15-Pad3_ Net-_U17-Pad3_ Net-_U19-Pad3_ d_or +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U15-Pad1_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U22 Net-_U18-Pad3_ Net-_U20-Pad2_ d_inverter +U23 Net-_U19-Pad3_ Net-_U21-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir.out b/library/SubcircuitLibrary/SN74351/SN74351.cir.out new file mode 100644 index 00000000..07b597bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir.out @@ -0,0 +1,117 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir + +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.pro b/library/SubcircuitLibrary/SN74351/SN74351.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sch b/library/SubcircuitLibrary/SN74351/SN74351.sch new file mode 100644 index 00000000..1d50e5b0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sch @@ -0,0 +1,1192 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN74351-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 6795B96A +P 13150 2950 +F 0 "X1" H 13200 2850 60 0000 C CNN +F 1 "5_and" H 13250 3100 60 0000 C CNN +F 2 "" H 13150 2950 60 0000 C CNN +F 3 "" H 13150 2950 60 0000 C CNN + 1 13150 2950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X2 +U 1 1 6795BA47 +P 13150 3650 +F 0 "X2" H 13200 3550 60 0000 C CNN +F 1 "5_and" H 13250 3800 60 0000 C CNN +F 2 "" H 13150 3650 60 0000 C CNN +F 3 "" H 13150 3650 60 0000 C CNN + 1 13150 3650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X3 +U 1 1 6795BAAC +P 13150 4350 +F 0 "X3" H 13200 4250 60 0000 C CNN +F 1 "5_and" H 13250 4500 60 0000 C CNN +F 2 "" H 13150 4350 60 0000 C CNN +F 3 "" H 13150 4350 60 0000 C CNN + 1 13150 4350 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 6795BAB2 +P 13150 5050 +F 0 "X4" H 13200 4950 60 0000 C CNN +F 1 "5_and" H 13250 5200 60 0000 C CNN +F 2 "" H 13150 5050 60 0000 C CNN +F 3 "" H 13150 5050 60 0000 C CNN + 1 13150 5050 + 1 0 0 -1 +$EndComp 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16150 6900 60 0000 C CNN +F 2 "" H 16150 6800 60 0000 C CNN +F 3 "" H 16150 6800 60 0000 C CNN + 1 16150 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U11 +U 1 1 67A38127 +P 14700 7600 +F 0 "U11" H 14700 7600 60 0000 C CNN +F 1 "d_or" H 14700 7700 60 0000 C CNN +F 2 "" H 14700 7600 60 0000 C CNN +F 3 "" H 14700 7600 60 0000 C CNN + 1 14700 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U9 +U 1 1 67A381AE +P 14650 6150 +F 0 "U9" H 14650 6150 60 0000 C CNN +F 1 "d_or" H 14650 6250 60 0000 C CNN +F 2 "" H 14650 6150 60 0000 C CNN +F 3 "" H 14650 6150 60 0000 C CNN + 1 14650 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U7 +U 1 1 67A382B3 +P 14600 4750 +F 0 "U7" H 14600 4750 60 0000 C CNN +F 1 "d_or" H 14600 4850 60 0000 C CNN +F 2 "" H 14600 4750 60 0000 C CNN +F 3 "" H 14600 4750 60 0000 C CNN + 1 14600 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 67A3833C +P 14550 3350 +F 0 "U6" H 14550 3350 60 0000 C CNN +F 1 "d_or" H 14550 3450 60 0000 C CNN +F 2 "" H 14550 3350 60 0000 C CNN +F 3 "" H 14550 3350 60 0000 C CNN + 1 14550 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 67A3867A +P 17250 12150 +F 0 "U19" H 17250 12150 60 0000 C CNN +F 1 "d_or" H 17250 12250 60 0000 C CNN +F 2 "" H 17250 12150 60 0000 C CNN +F 3 "" H 17250 12150 60 0000 C CNN + 1 17250 12150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U17 +U 1 1 67A387A5 +P 16200 13500 +F 0 "U17" H 16200 13500 60 0000 C CNN +F 1 "d_or" H 16200 13600 60 0000 C CNN +F 2 "" H 16200 13500 60 0000 C CNN +F 3 "" H 16200 13500 60 0000 C CNN + 1 16200 13500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 67A38826 +P 16100 10750 +F 0 "U15" H 16100 10750 60 0000 C CNN +F 1 "d_or" H 16100 10850 60 0000 C CNN +F 2 "" H 16100 10750 60 0000 C CNN +F 3 "" H 16100 10750 60 0000 C CNN + 1 16100 10750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 67A38AC4 +P 14600 10050 +F 0 "U8" H 14600 10050 60 0000 C CNN +F 1 "d_or" H 14600 10150 60 0000 C CNN +F 2 "" H 14600 10050 60 0000 C CNN +F 3 "" H 14600 10050 60 0000 C CNN + 1 14600 10050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 67A38B5F +P 14650 11450 +F 0 "U10" H 14650 11450 60 0000 C CNN +F 1 "d_or" H 14650 11550 60 0000 C CNN +F 2 "" H 14650 11450 60 0000 C CNN +F 3 "" H 14650 11450 60 0000 C CNN + 1 14650 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U12 +U 1 1 67A38CFC +P 14700 12850 +F 0 "U12" H 14700 12850 60 0000 C CNN +F 1 "d_or" H 14700 12950 60 0000 C CNN +F 2 "" H 14700 12850 60 0000 C CNN +F 3 "" H 14700 12850 60 0000 C CNN + 1 14700 12850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U13 +U 1 1 67A38D7F +P 14750 14300 +F 0 "U13" H 14750 14300 60 0000 C CNN +F 1 "d_or" H 14750 14400 60 0000 C CNN +F 2 "" H 14750 14300 60 0000 C CNN +F 3 "" H 14750 14300 60 0000 C CNN + 1 14750 14300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 67A393F8 +P 17800 5950 +F 0 "U22" H 17800 5850 60 0000 C CNN +F 1 "d_inverter" H 17800 6100 60 0000 C CNN +F 2 "" H 17850 5900 60 0000 C CNN +F 3 "" H 17850 5900 60 0000 C CNN + 1 17800 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 67A39864 +P 17900 12500 +F 0 "U23" H 17900 12400 60 0000 C CNN +F 1 "d_inverter" H 17900 12650 60 0000 C CNN +F 2 "" H 17950 12450 60 0000 C CNN +F 3 "" H 17950 12450 60 0000 C CNN + 1 17900 12500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17700 12100 17800 12100 +Wire Wire Line + 17800 12100 17800 12250 +Wire Wire Line + 17800 12250 17500 12250 +Wire Wire Line + 17500 12250 17500 12500 +Wire Wire Line + 17500 12500 17600 12500 +Wire Wire Line + 18200 12500 18250 12500 +Wire Wire Line + 18250 12500 18250 12250 +Wire Wire Line + 18250 12250 18150 12250 +Wire Wire Line + 18150 12250 18150 12100 +Wire Wire Line + 18150 12100 18200 12100 +Wire Wire Line + 17650 5400 17700 5400 +Wire Wire Line + 17700 5400 17700 5650 +Wire Wire Line + 17700 5650 17350 5650 +Wire Wire Line + 17350 5650 17350 5950 +Wire Wire Line + 17350 5950 17500 5950 +Wire Wire Line + 18100 5950 18200 5950 +Wire Wire Line + 18200 5950 18200 5650 +Wire Wire Line + 18200 5650 17800 5650 +Wire Wire Line + 17800 5650 17800 5400 +Wire Wire Line + 17800 5400 17950 5400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sub b/library/SubcircuitLibrary/SN74351/SN74351.sub new file mode 100644 index 00000000..87054221 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sub @@ -0,0 +1,111 @@ +* Subcircuit SN74351 +.subckt SN74351 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends SN74351
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml new file mode 100644 index 00000000..77e9ef56 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_nor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u12 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_nor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u19><u5 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u4><u18 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u16><u14 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_nor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u11><u9 name="type">d_nor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u9><u7 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u6><u20 name="type">d_nor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_nor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u18 name="type">d_or<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u14 name="type">d_or<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u16><u11 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u11><u9 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u9><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u6><u19 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u19><u17 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u17><u15 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u15><u8 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u13><u22 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u23></model><devicemodel /><subcircuit><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x15><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x16><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x10></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/analysis b/library/SubcircuitLibrary/SN74351/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/D.lib b/library/SubcircuitLibrary/SN74LS00/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib new file mode 100644 index 00000000..26ac6e60 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib @@ -0,0 +1,120 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir new file mode 100644 index 00000000..68e79d37 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL\NAND_GATE_FINAL.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:38:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k +R2 Net-_R1-Pad1_ Net-_Q3-Pad1_ 1.6k +R4 Net-_Q4-Pad1_ Net-_R1-Pad1_ 130 +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_D1-Pad2_ Net-_Q3-Pad3_ GND eSim_NPN +R3 Net-_Q3-Pad3_ GND 1k +U1 Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_D1-Pad2_ Net-_R1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out new file mode 100644 index 00000000..51032802 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir + +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 4k +r2 net-_r1-pad1_ net-_q3-pad1_ 1.6k +r4 net-_q4-pad1_ net-_r1-pad1_ 130 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 1k +* u1 net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch new file mode 100644 index 00000000..223fa915 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:NAND_GATE_FINAL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67704AAF +P 3150 4650 +F 0 "Q2" H 3050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3100 4800 50 0000 R CNN +F 2 "" H 3350 4750 29 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 1 3150 4650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 67704B0A +P 2350 4650 +F 0 "Q1" H 2250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2300 4800 50 0000 R CNN +F 2 "" H 2550 4750 29 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 1 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67704BF2 +P 2700 3400 +F 0 "R1" H 2750 3530 50 0000 C CNN +F 1 "4k" H 2750 3350 50 0000 C CNN +F 2 "" H 2750 3380 30 0000 C CNN +F 3 "" V 2750 3450 30 0000 C CNN + 1 2700 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67704C41 +P 3600 3400 +F 0 "R2" H 3650 3530 50 0000 C CNN +F 1 "1.6k" H 3650 3350 50 0000 C CNN +F 2 "" H 3650 3380 30 0000 C CNN +F 3 "" V 3650 3450 30 0000 C CNN + 1 3600 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67704C62 +P 4650 3500 +F 0 "R4" H 4700 3630 50 0000 C CNN +F 1 "130" H 4700 3450 50 0000 C CNN +F 2 "" H 4700 3480 30 0000 C CNN +F 3 "" V 4700 3550 30 0000 C CNN + 1 4650 3500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67704C93 +P 4500 4050 +F 0 "Q4" H 4400 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4450 4200 50 0000 R CNN +F 2 "" H 4700 4150 29 0000 C CNN +F 3 "" H 4500 4050 60 0000 C CNN + 1 4500 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67704CC8 +P 3900 4350 +F 0 "Q3" H 3800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4500 50 0000 R CNN +F 2 "" H 4100 4450 29 0000 C CNN +F 3 "" H 3900 4350 60 0000 C CNN + 1 3900 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67704D0D +P 4600 4600 +F 0 "D1" H 4600 4700 50 0000 C CNN +F 1 "eSim_Diode" H 4600 4500 50 0000 C CNN +F 2 "" H 4600 4600 60 0000 C CNN +F 3 "" H 4600 4600 60 0000 C CNN + 1 4600 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 67704DC5 +P 4500 5250 +F 0 "Q5" H 4400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5400 50 0000 R CNN +F 2 "" H 4700 5350 29 0000 C CNN +F 3 "" H 4500 5250 60 0000 C CNN + 1 4500 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 67704DD6 +P 3950 5500 +F 0 "R3" H 4000 5630 50 0000 C CNN +F 1 "1k" V 4000 5450 50 0000 C CNN +F 2 "" H 4000 5480 30 0000 C CNN +F 3 "" V 4000 5550 30 0000 C CNN + 1 3950 5500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 67705207 +P 2450 5250 +F 0 "U1" H 2500 5350 30 0000 C CNN +F 1 "PORT" H 2450 5250 30 0000 C CNN +F 2 "" H 2450 5250 60 0000 C CNN +F 3 "" H 2450 5250 60 0000 C CNN + 1 2450 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67705289 +P 3050 5250 +F 0 "U1" H 3100 5350 30 0000 C CNN +F 1 "PORT" H 3050 5250 30 0000 C CNN +F 2 "" H 3050 5250 60 0000 C CNN +F 3 "" H 3050 5250 60 0000 C CNN + 2 3050 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677052CE +P 5300 4900 +F 0 "U1" H 5350 5000 30 0000 C CNN +F 1 "PORT" H 5300 4900 30 0000 C CNN +F 2 "" H 5300 4900 60 0000 C CNN +F 3 "" H 5300 4900 60 0000 C CNN + 3 5300 4900 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67705545 +P 4750 5800 +F 0 "#PWR01" H 4750 5550 50 0001 C CNN +F 1 "GND" H 4750 5650 50 0000 C CNN +F 2 "" H 4750 5800 50 0001 C CNN +F 3 "" H 4750 5800 50 0001 C CNN + 1 4750 5800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3050 4450 2450 4450 +Wire Wire Line + 3350 4150 2150 4150 +Wire Wire Line + 3350 4650 3350 4150 +Wire Wire Line + 2150 4150 2150 4650 +Connection ~ 2750 4450 +Wire Wire Line + 4000 4550 4000 5400 +Wire Wire Line + 4300 5250 4000 5250 +Connection ~ 4000 5250 +Wire Wire Line + 4600 5050 4600 4750 +Wire Wire Line + 4600 4450 4600 4250 +Wire Wire Line + 4600 3850 4600 3600 +Wire Wire Line + 3650 4050 4300 4050 +Wire Wire Line + 4000 4050 4000 4150 +Wire Wire Line + 3650 4050 3650 3600 +Connection ~ 4000 4050 +Wire Wire Line + 2750 3300 2750 3050 +Wire Wire Line + 4600 3050 4600 3300 +Wire Wire Line + 3650 3300 3650 3050 +Connection ~ 3650 3050 +Wire Wire Line + 2450 4850 2450 5000 +Wire Wire Line + 3050 4850 3050 5000 +Wire Wire Line + 4000 5700 4000 5800 +Wire Wire Line + 4000 5800 4750 5800 +Wire Wire Line + 4600 4900 5050 4900 +Connection ~ 4600 4900 +Connection ~ 4600 5800 +Connection ~ 4600 3050 +Wire Wire Line + 4600 5800 4600 5450 +$Comp +L PORT U1 +U 4 1 677060E6 +P 4750 2700 +F 0 "U1" H 4800 2800 30 0000 C CNN +F 1 "PORT" H 4750 2700 30 0000 C CNN +F 2 "" H 4750 2700 60 0000 C CNN +F 3 "" H 4750 2700 60 0000 C CNN + 4 4750 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 4750 2950 4750 3050 +Connection ~ 4750 3050 +Wire Wire Line + 4750 3050 2750 3050 +Connection ~ 4600 3750 +Wire Wire Line + 2750 3600 2750 4150 +Connection ~ 2750 4150 +Wire Wire Line + 3700 4350 2750 4350 +Wire Wire Line + 2750 4350 2750 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub new file mode 100644 index 00000000..1a1d27ee --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub @@ -0,0 +1,18 @@ +* Subcircuit NAND_GATE_FINAL +.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 4k +r2 net-_r1-pad1_ net-_q3-pad1_ 1.6k +r4 net-_q4-pad1_ net-_r1-pad1_ 130 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 1k +* Control Statements + +.ends NAND_GATE_FINAL
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml new file mode 100644 index 00000000..0eb364f5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/NPN.lib b/library/SubcircuitLibrary/SN74LS00/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib b/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib new file mode 100644 index 00000000..37b0e2e1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib @@ -0,0 +1,60 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir new file mode 100644 index 00000000..4b046591 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS00\SN74LS00.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:31:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad14_ Nand_gate_final +X3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad14_ Nand_gate_final +X2 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad8_ Net-_U1-Pad14_ Nand_gate_final +X4 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad14_ Nand_gate_final +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out new file mode 100644 index 00000000..15fe255d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir + +.include NAND_GATE_FINAL.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL +x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL +x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro b/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch new file mode 100644 index 00000000..8371e33e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch @@ -0,0 +1,304 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Nand_gate_final X1 +U 1 1 67705EB8 +P 4400 3550 +F 0 "X1" H 4400 3550 60 0000 C CNN +F 1 "Nand_gate_final" H 4450 3450 60 0000 C CNN +F 2 "" H 4400 3550 60 0001 C CNN +F 3 "" H 4400 3550 60 0001 C CNN + 1 4400 3550 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X3 +U 1 1 67705EE5 +P 6950 3550 +F 0 "X3" H 6950 3550 60 0000 C CNN +F 1 "Nand_gate_final" H 7000 3450 60 0000 C CNN +F 2 "" H 6950 3550 60 0001 C CNN +F 3 "" H 6950 3550 60 0001 C CNN + 1 6950 3550 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X2 +U 1 1 67705EFE +P 4400 5100 +F 0 "X2" H 4400 5100 60 0000 C CNN +F 1 "Nand_gate_final" H 4450 5000 60 0000 C CNN +F 2 "" H 4400 5100 60 0001 C CNN +F 3 "" H 4400 5100 60 0001 C CNN + 1 4400 5100 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X4 +U 1 1 67705F23 +P 7050 5100 +F 0 "X4" H 7050 5100 60 0000 C CNN +F 1 "Nand_gate_final" H 7100 5000 60 0000 C CNN +F 2 "" H 7050 5100 60 0001 C CNN +F 3 "" H 7050 5100 60 0001 C CNN + 1 7050 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 3050 6700 3050 +Connection ~ 4150 3050 +Wire Wire Line + 4150 4600 2900 4600 +Wire Wire Line + 2900 4600 2900 3050 +Connection ~ 2900 3050 +Wire Wire Line + 6800 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 3050 +Connection ~ 5550 3050 +Wire Wire Line + 3700 4950 3200 4950 +Wire Wire Line + 3200 4950 3200 5450 +Wire Wire Line + 3700 5250 3700 5500 +Wire Wire Line + 5200 5100 5200 5500 +Wire Wire Line + 5200 5500 5250 5500 +Wire Wire Line + 7850 5100 7850 5650 +Wire Wire Line + 7850 5650 7900 5650 +Wire Wire Line + 6350 5250 6350 5600 +Wire Wire Line + 6350 4950 6100 4950 +Wire Wire Line + 6100 4950 6100 5600 +Wire Wire Line + 6250 3700 6250 4050 +Wire Wire Line + 6250 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 4050 +Wire Wire Line + 7750 3550 7750 4000 +Wire Wire Line + 5200 3550 5200 4000 +Wire Wire Line + 3700 3700 3700 4100 +Wire Wire Line + 3700 3400 3400 3400 +Wire Wire Line + 3400 3400 3400 4100 +$Comp +L PORT U1 +U 2 1 6770609D +P 3700 4350 +F 0 "U1" H 3750 4450 30 0000 C CNN +F 1 "PORT" H 3700 4350 30 0000 C CNN +F 2 "" H 3700 4350 60 0000 C CNN +F 3 "" H 3700 4350 60 0000 C CNN + 2 3700 4350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677060F9 +P 5200 4250 +F 0 "U1" H 5250 4350 30 0000 C CNN +F 1 "PORT" H 5200 4250 30 0000 C CNN +F 2 "" H 5200 4250 60 0000 C CNN +F 3 "" H 5200 4250 60 0000 C CNN + 3 5200 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6770612A +P 6250 4300 +F 0 "U1" H 6300 4400 30 0000 C CNN +F 1 "PORT" H 6250 4300 30 0000 C CNN +F 2 "" H 6250 4300 60 0000 C CNN +F 3 "" H 6250 4300 60 0000 C CNN + 5 6250 4300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 67706169 +P 7250 4550 +F 0 "U1" H 7300 4650 30 0000 C CNN +F 1 "PORT" H 7250 4550 30 0000 C CNN +F 2 "" H 7250 4550 60 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 7 7250 4550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 677061B0 +P 3700 5750 +F 0 "U1" H 3750 5850 30 0000 C CNN +F 1 "PORT" H 3700 5750 30 0000 C CNN +F 2 "" H 3700 5750 60 0000 C CNN +F 3 "" H 3700 5750 60 0000 C CNN + 9 3700 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 677061E9 +P 7900 5900 +F 0 "U1" H 7950 6000 30 0000 C CNN +F 1 "PORT" H 7900 5900 30 0000 C CNN +F 2 "" H 7900 5900 60 0000 C CNN +F 3 "" H 7900 5900 60 0000 C CNN + 11 7900 5900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 677062AC +P 5250 5750 +F 0 "U1" H 5300 5850 30 0000 C CNN +F 1 "PORT" H 5250 5750 30 0000 C CNN +F 2 "" H 5250 5750 60 0000 C CNN +F 3 "" H 5250 5750 60 0000 C CNN + 8 5250 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 677062E7 +P 3200 5700 +F 0 "U1" H 3250 5800 30 0000 C CNN +F 1 "PORT" H 3200 5700 30 0000 C CNN +F 2 "" H 3200 5700 60 0000 C CNN +F 3 "" H 3200 5700 60 0000 C CNN + 10 3200 5700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 67706324 +P 6350 5850 +F 0 "U1" H 6400 5950 30 0000 C CNN +F 1 "PORT" H 6350 5850 30 0000 C CNN +F 2 "" H 6350 5850 60 0000 C CNN +F 3 "" H 6350 5850 60 0000 C CNN + 12 6350 5850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 67706363 +P 7750 4250 +F 0 "U1" H 7800 4350 30 0000 C CNN +F 1 "PORT" H 7750 4250 30 0000 C CNN +F 2 "" H 7750 4250 60 0000 C CNN +F 3 "" H 7750 4250 60 0000 C CNN + 6 7750 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 677063A4 +P 6000 4300 +F 0 "U1" H 6050 4400 30 0000 C CNN +F 1 "PORT" H 6000 4300 30 0000 C CNN +F 2 "" H 6000 4300 60 0000 C CNN +F 3 "" H 6000 4300 60 0000 C CNN + 4 6000 4300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 677063EF +P 3400 4350 +F 0 "U1" H 3450 4450 30 0000 C CNN +F 1 "PORT" H 3400 4350 30 0000 C CNN +F 2 "" H 3400 4350 60 0000 C CNN +F 3 "" H 3400 4350 60 0000 C CNN + 1 3400 4350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 6770A61C +P 2500 3300 +F 0 "U1" H 2550 3400 30 0000 C CNN +F 1 "PORT" H 2500 3300 30 0000 C CNN +F 2 "" H 2500 3300 60 0000 C CNN +F 3 "" H 2500 3300 60 0000 C CNN + 14 2500 3300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 6770A667 +P 6100 5850 +F 0 "U1" H 6150 5950 30 0000 C CNN +F 1 "PORT" H 6100 5850 30 0000 C CNN +F 2 "" H 6100 5850 60 0000 C CNN +F 3 "" H 6100 5850 60 0000 C CNN + 13 6100 5850 + 0 -1 -1 0 +$EndComp +NoConn ~ 7250 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub new file mode 100644 index 00000000..2ec1904f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub @@ -0,0 +1,11 @@ +* Subcircuit SN74LS00 +.subckt SN74LS00 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir +.include NAND_GATE_FINAL.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL +x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL +x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL +* Control Statements + +.ends SN74LS00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml new file mode 100644 index 00000000..a24d9a30 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/analysis b/library/SubcircuitLibrary/SN74LS00/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib new file mode 100644 index 00000000..32e7ba06 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib @@ -0,0 +1,756 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# OTA_CA3080 +# +DEF OTA_CA3080 X 0 40 Y Y 1 F N +F0 "X" 200 300 60 H V C CNN +F1 "OTA_CA3080" 50 0 60 H V C CNN +F2 "" 50 0 60 H I C CNN +F3 "" 50 0 60 H I C CNN +DRAW +C 200 -100 50 0 1 0 N +C 250 -100 50 0 1 0 N +P 6 0 1 0 -350 350 -350 -450 650 0 -350 450 -350 300 -350 350 N +X A 1 300 350 200 D 50 50 1 1 I +X B 2 -550 -300 200 R 50 50 1 1 I +X C 3 -550 250 200 R 50 50 1 1 I +X D 4 0 -500 200 U 50 50 1 1 I +X E 5 550 250 200 D 50 50 1 1 I +X F 6 850 0 200 L 50 50 1 1 O +X G 7 0 500 200 D 50 50 1 1 I +X H 8 300 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm3909 +# +DEF lm3909 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "lm3909" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1000 400 1050 -450 0 1 0 N +X ~ 1 -750 -650 200 U 50 50 1 1 I +X ~ 2 -200 -650 200 U 50 50 1 1 I +X ~ 3 350 -650 200 U 50 50 1 1 I +X ~ 4 850 -650 200 U 50 50 1 1 I +X ~ 5 850 600 200 D 50 50 1 1 I +X ~ 6 350 600 200 D 50 50 1 1 I +X ~ 7 -200 600 200 D 50 50 1 1 I +X ~ 8 -750 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# nand_ttl +# +DEF nand_ttl X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "nand_ttl" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -580 156 1081 -250 -777 0 1 0 N 400 -300 -350 -900 +A -361 -420 770 90 892 0 1 0 N 400 -300 -350 350 +C 500 -300 112 0 1 0 N +P 2 0 1 0 -350 -300 -350 -900 N +P 2 0 1 0 -350 350 -350 -300 N +X A 1 -550 150 200 R 50 50 1 1 I +X B 2 -550 -650 200 R 50 50 1 1 I +X C 3 800 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ca3080/D.lib b/library/SubcircuitLibrary/ca3080/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ca3080/NPN.lib b/library/SubcircuitLibrary/ca3080/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/ca3080/PNP.lib b/library/SubcircuitLibrary/ca3080/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/ca3080/analysis b/library/SubcircuitLibrary/ca3080/analysis new file mode 100644 index 00000000..85e6f838 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/analysis @@ -0,0 +1 @@ +.tran 2e-00 6e-00 1e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3080/ca3080-cache.lib b/library/SubcircuitLibrary/ca3080/ca3080-cache.lib new file mode 100644 index 00000000..21197049 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ca3080/ca3080.cir b/library/SubcircuitLibrary/ca3080/ca3080.cir new file mode 100644 index 00000000..4666a808 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.cir @@ -0,0 +1,28 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\ca3080\ca3080.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 11/23/24 19:02:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_D2-Pad1_ Net-_D3-Pad2_ Net-_D3-Pad1_ eSim_PNP +Q1 Net-_D2-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q5 Net-_D4-Pad1_ Net-_Q5-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q6 Net-_Q11-Pad2_ Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_PNP +Q4 Net-_Q11-Pad2_ Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_PNP +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q3 Net-_Q1-Pad3_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q8 Net-_Q10-Pad1_ Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_PNP +Q7 Net-_D4-Pad1_ Net-_D5-Pad2_ Net-_D3-Pad1_ eSim_PNP +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q10 Net-_Q10-Pad1_ Net-_D4-Pad2_ Net-_D5-Pad2_ eSim_PNP +D5 Net-_D3-Pad1_ Net-_D5-Pad2_ eSim_Diode +D6 Net-_D6-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q9 Net-_Q11-Pad2_ Net-_D6-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q11 Net-_Q10-Pad1_ Net-_Q11-Pad2_ Net-_D6-Pad1_ eSim_NPN +U1 ? Net-_Q1-Pad2_ Net-_Q5-Pad2_ Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q10-Pad1_ Net-_D3-Pad1_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/ca3080/ca3080.cir.out b/library/SubcircuitLibrary/ca3080/ca3080.cir.out new file mode 100644 index 00000000..8c0a7960 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.cir.out @@ -0,0 +1,32 @@ +* c:\fossee\esim\library\subcircuitlibrary\ca3080\ca3080.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q11-pad2_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q4 net-_q11-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d1-pad2_ 1N4148 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d1-pad2_ Q2N2222 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +* u1 ? net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q10-pad1_ net-_d3-pad1_ ? port +.tran 2e-00 6e-00 1e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ca3080/ca3080.pro b/library/SubcircuitLibrary/ca3080/ca3080.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ca3080/ca3080.sch b/library/SubcircuitLibrary/ca3080/ca3080.sch new file mode 100644 index 00000000..4f206f03 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.sch @@ -0,0 +1,445 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ca3080-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q2 +U 1 1 6739CE3D +P 3000 2900 +F 0 "Q2" H 2900 2950 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3050 50 0000 R CNN +F 2 "" H 3200 3000 29 0000 C CNN +F 3 "" H 3000 2900 60 0000 C CNN + 1 3000 2900 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6739CEC7 +P 2800 4200 +F 0 "Q1" H 2700 4250 50 0000 R CNN +F 1 "eSim_NPN" H 2750 4350 50 0000 R CNN +F 2 "" H 3000 4300 29 0000 C CNN +F 3 "" H 2800 4200 60 0000 C CNN + 1 2800 4200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6739CEE0 +P 4300 4200 +F 0 "Q5" H 4200 4250 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4350 50 0000 R CNN +F 2 "" H 4500 4300 29 0000 C CNN +F 3 "" H 4300 4200 60 0000 C CNN + 1 4300 4200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6739D026 +P 5000 3100 +F 0 "Q6" H 4900 3150 50 0000 R CNN +F 1 "eSim_PNP" H 4950 3250 50 0000 R CNN +F 2 "" H 5200 3200 29 0000 C CNN +F 3 "" H 5000 3100 60 0000 C CNN + 1 5000 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 6739D114 +P 4150 3400 +F 0 "Q4" H 4050 3450 50 0000 R CNN +F 1 "eSim_PNP" H 4100 3550 50 0000 R CNN +F 2 "" H 4350 3500 29 0000 C CNN +F 3 "" H 4150 3400 60 0000 C CNN + 1 4150 3400 + 1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6739D123 +P 3850 3100 +F 0 "D2" H 3850 3200 50 0000 C CNN +F 1 "eSim_Diode" H 3850 3000 50 0000 C CNN +F 2 "" H 3850 3100 60 0000 C CNN +F 3 "" H 3850 3100 60 0000 C CNN + 1 3850 3100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6739D928 +P 5100 2550 +F 0 "D3" H 5100 2650 50 0000 C CNN +F 1 "eSim_Diode" H 5100 2450 50 0000 C CNN +F 2 "" H 5100 2550 60 0000 C CNN +F 3 "" H 5100 2550 60 0000 C CNN + 1 5100 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6739DE31 +P 2900 5150 +F 0 "D1" H 2900 5250 50 0000 C CNN +F 1 "eSim_Diode" H 2900 5050 50 0000 C CNN +F 2 "" H 2900 5150 60 0000 C CNN +F 3 "" H 2900 5150 60 0000 C CNN + 1 2900 5150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6739DE58 +P 3450 4950 +F 0 "Q3" H 3350 5000 50 0000 R CNN +F 1 "eSim_NPN" H 3400 5100 50 0000 R CNN +F 2 "" H 3650 5050 29 0000 C CNN +F 3 "" H 3450 4950 60 0000 C CNN + 1 3450 4950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6739E7CF +P 6400 3950 +F 0 "Q8" H 6300 4000 50 0000 R CNN +F 1 "eSim_PNP" H 6350 4100 50 0000 R CNN +F 2 "" H 6600 4050 29 0000 C CNN +F 3 "" H 6400 3950 60 0000 C CNN + 1 6400 3950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6739E976 +P 5700 3100 +F 0 "Q7" H 5600 3150 50 0000 R CNN +F 1 "eSim_PNP" H 5650 3250 50 0000 R CNN +F 2 "" H 5900 3200 29 0000 C CNN +F 3 "" H 5700 3100 60 0000 C CNN + 1 5700 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6739E9A5 +P 5950 3650 +F 0 "D4" H 5950 3750 50 0000 C CNN +F 1 "eSim_Diode" H 5950 3550 50 0000 C CNN +F 2 "" H 5950 3650 60 0000 C CNN +F 3 "" H 5950 3650 60 0000 C CNN + 1 5950 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 4400 4200 4400 +Wire Wire Line + 2900 4000 2900 3100 +Wire Wire Line + 4000 3100 4800 3100 +Wire Wire Line + 3950 3400 2900 3400 +Connection ~ 2900 3400 +Wire Wire Line + 3700 3100 3400 3100 +Wire Wire Line + 3400 3100 3400 3400 +Connection ~ 3400 3400 +Wire Wire Line + 4250 3200 4250 3100 +Connection ~ 4250 3100 +Wire Wire Line + 5100 3300 5100 4750 +Wire Wire Line + 5100 3600 4250 3600 +Wire Wire Line + 4500 4200 4500 4600 +Wire Wire Line + 4500 4600 2500 4600 +Wire Wire Line + 2600 4200 2500 4200 +Wire Wire Line + 3200 2900 5100 2900 +Wire Wire Line + 5100 2900 5100 2700 +Wire Wire Line + 2900 2700 2900 2300 +Wire Wire Line + 2900 2300 7950 2300 +Wire Wire Line + 5100 2300 5100 2400 +Wire Wire Line + 2900 5000 2900 4950 +Wire Wire Line + 2500 4950 3250 4950 +Wire Wire Line + 3550 4750 3550 4400 +Connection ~ 3550 4400 +Wire Wire Line + 2900 5300 2900 5550 +Wire Wire Line + 2900 5550 8000 5550 +Wire Wire Line + 3550 5150 3550 5550 +Connection ~ 3550 5550 +Wire Wire Line + 4200 4000 4200 3950 +Wire Wire Line + 4200 3950 6200 3950 +Wire Wire Line + 5600 3300 5600 3950 +Connection ~ 5600 3950 +Wire Wire Line + 5800 3650 5700 3650 +Wire Wire Line + 5700 3650 5700 3950 +Connection ~ 5700 3950 +Wire Wire Line + 6100 3650 7150 3650 +Wire Wire Line + 6500 3650 6500 3750 +Wire Wire Line + 5600 2300 5600 2900 +Connection ~ 5100 2300 +$Comp +L eSim_PNP Q10 +U 1 1 6739F10B +P 7350 3650 +F 0 "Q10" H 7250 3700 50 0000 R CNN +F 1 "eSim_PNP" H 7300 3800 50 0000 R CNN +F 2 "" H 7550 3750 29 0000 C CNN +F 3 "" H 7350 3650 60 0000 C CNN + 1 7350 3650 + 1 0 0 1 +$EndComp +Connection ~ 6500 3650 +$Comp +L eSim_Diode D5 +U 1 1 6739F185 +P 7450 2750 +F 0 "D5" H 7450 2850 50 0000 C CNN +F 1 "eSim_Diode" H 7450 2650 50 0000 C CNN +F 2 "" H 7450 2750 60 0000 C CNN +F 3 "" H 7450 2750 60 0000 C CNN + 1 7450 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 6739F3EA +P 7450 5150 +F 0 "D6" H 7450 5250 50 0000 C CNN +F 1 "eSim_Diode" H 7450 5050 50 0000 C CNN +F 2 "" H 7450 5150 60 0000 C CNN +F 3 "" H 7450 5150 60 0000 C CNN + 1 7450 5150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6739F41F +P 6700 4950 +F 0 "Q9" H 6600 5000 50 0000 R CNN +F 1 "eSim_NPN" H 6650 5100 50 0000 R CNN +F 2 "" H 6900 5050 29 0000 C CNN +F 3 "" H 6700 4950 60 0000 C CNN + 1 6700 4950 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 6739F984 +P 7350 4650 +F 0 "Q11" H 7250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 7300 4800 50 0000 R CNN +F 2 "" H 7550 4750 29 0000 C CNN +F 3 "" H 7350 4650 60 0000 C CNN + 1 7350 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 3850 7450 4450 +Wire Wire Line + 6500 4150 7450 4150 +Connection ~ 7450 4150 +Wire Wire Line + 7450 4850 7450 5000 +Wire Wire Line + 6900 4950 7450 4950 +Connection ~ 7450 4950 +Wire Wire Line + 7450 5300 7450 5550 +Connection ~ 7450 5550 +Wire Wire Line + 6600 5150 6600 5550 +Connection ~ 6600 5550 +Wire Wire Line + 7450 2300 7450 2600 +Connection ~ 5600 2300 +Wire Wire Line + 5900 3100 7450 3100 +Connection ~ 7450 3100 +Wire Wire Line + 5100 4750 6600 4750 +Connection ~ 5100 3600 +Wire Wire Line + 7150 4650 6600 4650 +Wire Wire Line + 6600 4650 6600 4750 +Wire Wire Line + 7450 4350 7950 4350 +Connection ~ 7450 4350 +Connection ~ 7450 2300 +Connection ~ 2900 4950 +$Comp +L PORT U1 +U 7 1 673A5D57 +P 8200 2300 +F 0 "U1" H 8250 2400 30 0000 C CNN +F 1 "PORT" H 8200 2300 30 0000 C CNN +F 2 "" H 8200 2300 60 0000 C CNN +F 3 "" H 8200 2300 60 0000 C CNN + 7 8200 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 673A5F78 +P 8200 4350 +F 0 "U1" H 8250 4450 30 0000 C CNN +F 1 "PORT" H 8200 4350 30 0000 C CNN +F 2 "" H 8200 4350 60 0000 C CNN +F 3 "" H 8200 4350 60 0000 C CNN + 6 8200 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 673A669D +P 2250 4200 +F 0 "U1" H 2300 4300 30 0000 C CNN +F 1 "PORT" H 2250 4200 30 0000 C CNN +F 2 "" H 2250 4200 60 0000 C CNN +F 3 "" H 2250 4200 60 0000 C CNN + 2 2250 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 673A66F6 +P 2250 4600 +F 0 "U1" H 2300 4700 30 0000 C CNN +F 1 "PORT" H 2250 4600 30 0000 C CNN +F 2 "" H 2250 4600 60 0000 C CNN +F 3 "" H 2250 4600 60 0000 C CNN + 3 2250 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 673A7187 +P 2150 1850 +F 0 "U1" H 2200 1950 30 0000 C CNN +F 1 "PORT" H 2150 1850 30 0000 C CNN +F 2 "" H 2150 1850 60 0000 C CNN +F 3 "" H 2150 1850 60 0000 C CNN + 1 2150 1850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 6000 7700 6000 +NoConn ~ 7700 6000 +Wire Wire Line + 2400 1850 2650 1850 +NoConn ~ 2650 1850 +Wire Wire Line + 7450 2900 7450 3450 +$Comp +L PORT U1 +U 5 1 673A9E14 +P 2250 4950 +F 0 "U1" H 2300 5050 30 0000 C CNN +F 1 "PORT" H 2250 4950 30 0000 C CNN +F 2 "" H 2250 4950 60 0000 C CNN +F 3 "" H 2250 4950 60 0000 C CNN + 5 2250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 673AA0F8 +P 8250 5550 +F 0 "U1" H 8300 5650 30 0000 C CNN +F 1 "PORT" H 8250 5550 30 0000 C CNN +F 2 "" H 8250 5550 60 0000 C CNN +F 3 "" H 8250 5550 60 0000 C CNN + 4 8250 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 673AA6CB +P 8150 6000 +F 0 "U1" H 8200 6100 30 0000 C CNN +F 1 "PORT" H 8150 6000 30 0000 C CNN +F 2 "" H 8150 6000 60 0000 C CNN +F 3 "" H 8150 6000 60 0000 C CNN + 8 8150 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ca3080/ca3080.sub b/library/SubcircuitLibrary/ca3080/ca3080.sub new file mode 100644 index 00000000..263cea77 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.sub @@ -0,0 +1,26 @@ +* Subcircuit ca3080 +.subckt ca3080 ? net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q10-pad1_ net-_d3-pad1_ ? +* c:\fossee\esim\library\subcircuitlibrary\ca3080\ca3080.cir +.include NPN.lib +.include PNP.lib +.include D.lib +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q11-pad2_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q4 net-_q11-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d1-pad2_ 1N4148 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d1-pad2_ Q2N2222 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +* Control Statements + +.ends ca3080
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml b/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml new file mode 100644 index 00000000..6442215a --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">1</field1><field2 name="Step Time">2</field2><field3 name="Stop Time">6</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/D.lib b/library/SubcircuitLibrary/mc1489/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib b/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.cir b/library/SubcircuitLibrary/mc1489/MC1489_0.cir new file mode 100644 index 00000000..fc367dfd --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0\MC1489_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 19:55:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 6.7K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out b/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out new file mode 100644 index 00000000..f87cb465 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.pro b/library/SubcircuitLibrary/mc1489/MC1489_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.sch b/library/SubcircuitLibrary/mc1489/MC1489_0.sch new file mode 100644 index 00000000..9370a9cd --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "6.7K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.sub b/library/SubcircuitLibrary/mc1489/MC1489_0.sub new file mode 100644 index 00000000..3b1419b5 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.sub @@ -0,0 +1,18 @@ +* Subcircuit MC1489_0 +.subckt MC1489_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* Control Statements + +.ends MC1489_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml b/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/NPN.lib b/library/SubcircuitLibrary/mc1489/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1489/analysis b/library/SubcircuitLibrary/mc1489/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/mc1489-cache.lib b/library/SubcircuitLibrary/mc1489/mc1489-cache.lib new file mode 100644 index 00000000..cfb8337e --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# MC1489_0 +# +DEF MC1489_0 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "MC1489_0" 0 -100 60 H V C CNN +F2 "" 0 -100 60 H I C CNN +F3 "" 0 -100 60 H I C CNN +DRAW +S -500 150 550 -300 0 1 0 N +X input 1 -700 -100 200 R 50 50 1 1 I +X response_ctrl 2 750 -200 200 L 50 50 1 1 I +X vcc 3 0 -500 200 U 50 50 1 1 O +X out 4 300 350 200 D 50 50 1 1 I +X gnd 5 -300 350 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489/mc1489.cir b/library/SubcircuitLibrary/mc1489/mc1489.cir new file mode 100644 index 00000000..06b9edbc --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1489\mc1489.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 20:02:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ gnd Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad3_ gnd MC1489_0 +X3 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad8_ gnd MC1489_0 +X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_U1-Pad6_ gnd MC1489_0 +X4 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U1-Pad11_ gnd MC1489_0 + +.end diff --git a/library/SubcircuitLibrary/mc1489/mc1489.cir.out b/library/SubcircuitLibrary/mc1489/mc1489.cir.out new file mode 100644 index 00000000..7e7b7cd0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489\mc1489.cir + +.include MC1489_0.sub +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad3_ gnd MC1489_0 +x3 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad8_ gnd MC1489_0 +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad6_ gnd MC1489_0 +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad11_ gnd MC1489_0 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489/mc1489.pro b/library/SubcircuitLibrary/mc1489/mc1489.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489/mc1489.sch b/library/SubcircuitLibrary/mc1489/mc1489.sch new file mode 100644 index 00000000..98f81be3 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.sch @@ -0,0 +1,313 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:mc1489-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5550 4150 5550 4900 +Wire Wire Line + 7700 4200 7700 4850 +Wire Wire Line + 7700 4850 7750 4850 +Wire Wire Line + 5550 4500 7700 4500 +Connection ~ 7700 4500 +Connection ~ 5550 4500 +Wire Wire Line + 8050 5700 8050 5900 +Wire Wire Line + 8050 5900 8150 5900 +Wire Wire Line + 7400 3350 7400 3200 +Wire Wire Line + 5250 3300 5250 3050 +Wire Wire Line + 5850 5750 5850 5950 +Text GLabel 5850 5950 3 60 Input ~ 0 +gnd +Text GLabel 8150 5900 2 60 Input ~ 0 +gnd +Text GLabel 7400 3200 0 60 Input ~ 0 +gnd +Text GLabel 5250 3050 0 60 Input ~ 0 +gnd +Wire Wire Line + 4850 3750 4600 3750 +Wire Wire Line + 4800 5200 4550 5200 +Wire Wire Line + 5250 5750 5000 5750 +Wire Wire Line + 6250 5300 6250 5200 +Wire Wire Line + 7000 5150 7000 5050 +Wire Wire Line + 7450 5700 7300 5700 +Wire Wire Line + 8450 5250 8450 5050 +Wire Wire Line + 8450 3900 8450 4000 +Wire Wire Line + 7000 3800 7000 3950 +Wire Wire Line + 8000 3350 8150 3350 +Wire Wire Line + 5850 3300 5950 3300 +Wire Wire Line + 6300 3850 6300 3700 +$Comp +L PORT U1 +U 3 1 679A35F2 +P 6200 3300 +F 0 "U1" H 6250 3400 30 0000 C CNN +F 1 "PORT" H 6200 3300 30 0000 C CNN +F 2 "" H 6200 3300 60 0000 C CNN +F 3 "" H 6200 3300 60 0000 C CNN + 3 6200 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A361D +P 4750 5750 +F 0 "U1" H 4800 5850 30 0000 C CNN +F 1 "PORT" H 4750 5750 30 0000 C CNN +F 2 "" H 4750 5750 60 0000 C CNN +F 3 "" H 4750 5750 60 0000 C CNN + 6 4750 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A363E +P 6000 5200 +F 0 "U1" H 6050 5300 30 0000 C CNN +F 1 "PORT" H 6000 5200 30 0000 C CNN +F 2 "" H 6000 5200 60 0000 C CNN +F 3 "" H 6000 5200 60 0000 C CNN + 4 6000 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A3661 +P 4300 5200 +F 0 "U1" H 4350 5300 30 0000 C CNN +F 1 "PORT" H 4300 5200 30 0000 C CNN +F 2 "" H 4300 5200 60 0000 C CNN +F 3 "" H 4300 5200 60 0000 C CNN + 5 4300 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3686 +P 4350 3750 +F 0 "U1" H 4400 3850 30 0000 C CNN +F 1 "PORT" H 4350 3750 30 0000 C CNN +F 2 "" H 4350 3750 60 0000 C CNN +F 3 "" H 4350 3750 60 0000 C CNN + 1 4350 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A36AD +P 6050 3700 +F 0 "U1" H 6100 3800 30 0000 C CNN +F 1 "PORT" H 6050 3700 30 0000 C CNN +F 2 "" H 6050 3700 60 0000 C CNN +F 3 "" H 6050 3700 60 0000 C CNN + 2 6050 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679A36D6 +P 4900 3250 +F 0 "U1" H 4950 3350 30 0000 C CNN +F 1 "PORT" H 4900 3250 30 0000 C CNN +F 2 "" H 4900 3250 60 0000 C CNN +F 3 "" H 4900 3250 60 0000 C CNN + 7 4900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 679A3701 +P 6750 3950 +F 0 "U1" H 6800 4050 30 0000 C CNN +F 1 "PORT" H 6750 3950 30 0000 C CNN +F 2 "" H 6750 3950 60 0000 C CNN +F 3 "" H 6750 3950 60 0000 C CNN + 10 6750 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 679A372E +P 6750 5050 +F 0 "U1" H 6800 5150 30 0000 C CNN +F 1 "PORT" H 6750 5050 30 0000 C CNN +F 2 "" H 6750 5050 60 0000 C CNN +F 3 "" H 6750 5050 60 0000 C CNN + 12 6750 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 679A375D +P 7050 5700 +F 0 "U1" H 7100 5800 30 0000 C CNN +F 1 "PORT" H 7050 5700 30 0000 C CNN +F 2 "" H 7050 5700 60 0000 C CNN +F 3 "" H 7050 5700 60 0000 C CNN + 11 7050 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 679A3796 +P 8200 5050 +F 0 "U1" H 8250 5150 30 0000 C CNN +F 1 "PORT" H 8200 5050 30 0000 C CNN +F 2 "" H 8200 5050 60 0000 C CNN +F 3 "" H 8200 5050 60 0000 C CNN + 13 8200 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 679A37C9 +P 8200 4000 +F 0 "U1" H 8250 4100 30 0000 C CNN +F 1 "PORT" H 8200 4000 30 0000 C CNN +F 2 "" H 8200 4000 60 0000 C CNN +F 3 "" H 8200 4000 60 0000 C CNN + 9 8200 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679A37FE +P 8400 3350 +F 0 "U1" H 8450 3450 30 0000 C CNN +F 1 "PORT" H 8400 3350 30 0000 C CNN +F 2 "" H 8400 3350 60 0000 C CNN +F 3 "" H 8400 3350 60 0000 C CNN + 8 8400 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 679A3835 +P 6650 4900 +F 0 "U1" H 6700 5000 30 0000 C CNN +F 1 "PORT" H 6650 4900 30 0000 C CNN +F 2 "" H 6650 4900 60 0000 C CNN +F 3 "" H 6650 4900 60 0000 C CNN + 14 6650 4900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5150 3250 5250 3250 +Connection ~ 5250 3250 +Wire Wire Line + 6650 4650 6650 4500 +Connection ~ 6650 4500 +$Comp +L MC1489_0 X1 +U 1 1 679A3C30 +P 5550 3650 +F 0 "X1" H 5550 3650 60 0000 C CNN +F 1 "MC1489_0" H 5550 3550 60 0000 C CNN +F 2 "" H 5550 3550 60 0001 C CNN +F 3 "" H 5550 3550 60 0001 C CNN + 1 5550 3650 + 1 0 0 -1 +$EndComp +$Comp +L MC1489_0 X3 +U 1 1 679A3C93 +P 7700 3700 +F 0 "X3" H 7700 3700 60 0000 C CNN +F 1 "MC1489_0" H 7700 3600 60 0000 C CNN +F 2 "" H 7700 3600 60 0001 C CNN +F 3 "" H 7700 3600 60 0001 C CNN + 1 7700 3700 + 1 0 0 -1 +$EndComp +$Comp +L MC1489_0 X2 +U 1 1 679A3FCC +P 5550 5400 +F 0 "X2" H 5550 5400 60 0000 C CNN +F 1 "MC1489_0" H 5550 5300 60 0000 C CNN +F 2 "" H 5550 5300 60 0001 C CNN +F 3 "" H 5550 5300 60 0001 C CNN + 1 5550 5400 + -1 0 0 1 +$EndComp +$Comp +L MC1489_0 X4 +U 1 1 679A4021 +P 7750 5350 +F 0 "X4" H 7750 5350 60 0000 C CNN +F 1 "MC1489_0" H 7750 5250 60 0000 C CNN +F 2 "" H 7750 5250 60 0001 C CNN +F 3 "" H 7750 5250 60 0001 C CNN + 1 7750 5350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489/mc1489.sub b/library/SubcircuitLibrary/mc1489/mc1489.sub new file mode 100644 index 00000000..49e98c90 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.sub @@ -0,0 +1,11 @@ +* Subcircuit mc1489 +.subckt mc1489 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489\mc1489.cir +.include MC1489_0.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad3_ gnd MC1489_0 +x3 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad8_ gnd MC1489_0 +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad6_ gnd MC1489_0 +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad11_ gnd MC1489_0 +* Control Statements + +.ends mc1489
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml b/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml new file mode 100644 index 00000000..e3de6ceb --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/D.lib b/library/SubcircuitLibrary/mc1489A_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1489A_0/NPN.lib b/library/SubcircuitLibrary/mc1489A_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1489A_0/analysis b/library/SubcircuitLibrary/mc1489A_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir new file mode 100644 index 00000000..7b3d76c7 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1489A_0\mc1489A_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 01:16:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 1.6K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out new file mode 100644 index 00000000..6fa09c26 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch new file mode 100644 index 00000000..d247d45d --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "1.6K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub new file mode 100644 index 00000000..e9ebfc80 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub @@ -0,0 +1,18 @@ +* Subcircuit mc1489A_0 +.subckt mc1489A_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* Control Statements + +.ends mc1489A_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/NPN.lib b/library/SubcircuitLibrary/tda7050/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/tda7050/PNP.lib b/library/SubcircuitLibrary/tda7050/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/tda7050/analysis b/library/SubcircuitLibrary/tda7050/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/lm_741-cache.lib b/library/SubcircuitLibrary/tda7050/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib b/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib new file mode 100644 index 00000000..1ac4cbd4 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_NPN-RESCUE-lm_741 +# +DEF eSim_NPN-RESCUE-lm_741 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-lm_741" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-lm_741 +# +DEF eSim_PNP-RESCUE-lm_741 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-lm_741" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/lm_741.cir b/library/SubcircuitLibrary/tda7050/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/tda7050/lm_741.cir.out b/library/SubcircuitLibrary/tda7050/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tda7050/lm_741.pro b/library/SubcircuitLibrary/tda7050/lm_741.pro new file mode 100644 index 00000000..e6fc25cb --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.pro @@ -0,0 +1,45 @@ +update=11/23/24 18:57:50 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=lm_741-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_User +LibName11=eSim_Sources +LibName12=eSim_Subckt diff --git a/library/SubcircuitLibrary/tda7050/lm_741.sch b/library/SubcircuitLibrary/tda7050/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 0000 C CNN + 7 9750 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CE90A9E +P 9750 3500 +F 0 "U1" H 9800 3600 30 0000 C CNN +F 1 "PORT" H 9750 3500 30 0000 C CNN +F 2 "" H 9750 3500 60 0000 C CNN +F 3 "" H 9750 3500 60 0000 C CNN + 6 9750 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CE90A9F +P 9700 5550 +F 0 "U1" H 9750 5650 30 0000 C CNN +F 1 "PORT" H 9700 5550 30 0000 C CNN +F 2 "" H 9700 5550 60 0000 C CNN +F 3 "" H 9700 5550 60 0000 C CNN + 4 9700 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3200 3750 3200 +Wire Wire Line + 2750 2900 2750 2950 +Wire Wire Line + 2750 2950 2900 2950 +Wire Wire Line + 2900 2950 2900 3000 +Wire Wire Line + 4200 2900 4200 2950 +Wire Wire Line + 4200 2950 4050 2950 +Wire Wire Line + 4050 2950 4050 3000 +Wire Wire Line + 2900 3400 2900 4400 +Wire Wire Line + 2900 4000 3100 4000 +Wire Wire Line + 4200 2000 4200 2500 +Wire Wire Line + 4200 2350 2750 2350 +Wire Wire Line + 2750 2350 2750 2500 +Wire Wire Line + 5000 2000 4050 2000 +Connection ~ 4200 2350 +Connection ~ 4200 2000 +Wire Wire Line + 3750 2200 3750 2350 +Connection ~ 3750 2350 +Wire Wire Line + 3750 1800 3750 1650 +Wire Wire Line + 3400 1650 7600 1650 +Wire Wire Line + 3400 1650 3400 3800 +Wire Wire Line + 5300 1650 5300 1800 +Connection ~ 3750 1650 +Wire Wire Line + 5300 2200 5300 4500 +Wire Wire Line + 5300 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3200 +Connection ~ 3650 3200 +Connection ~ 2900 4000 +Wire Wire Line + 4050 4400 4050 3400 +Wire Wire Line + 3400 4200 3400 4600 +Wire Wire Line + 3200 4600 3750 4600 +Connection ~ 3400 4600 +Wire Wire Line + 4050 5100 4050 4800 +Wire Wire Line + 3600 5100 3600 4600 +Connection ~ 3600 4600 +Wire Wire Line + 2900 5100 2900 4800 +Wire Wire Line + 2900 5400 2900 5550 +Wire Wire Line + 2900 5550 9450 5550 +Wire Wire Line + 4050 5550 4050 5400 +Wire Wire Line + 3600 5400 3600 5550 +Connection ~ 3600 5550 +Wire Wire Line + 6100 4700 5600 4700 +Wire Wire Line + 6400 2950 6400 4500 +Wire Wire Line + 6400 4250 5900 4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tda7050/lm_741.sub b/library/SubcircuitLibrary/tda7050/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/npn_1.lib b/library/SubcircuitLibrary/tda7050/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/pnp_1.lib b/library/SubcircuitLibrary/tda7050/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/tda7050-cache.lib b/library/SubcircuitLibrary/tda7050/tda7050-cache.lib new file mode 100644 index 00000000..5b8e3633 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/tda7050.cir b/library/SubcircuitLibrary/tda7050/tda7050.cir new file mode 100644 index 00000000..3cb98116 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\tda7050\tda7050.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/08/25 21:45:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad5_ ? Net-_U1-Pad7_ Net-_U1-Pad8_ ? lm_741 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT +X2 ? Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad8_ ? Net-_U1-Pad6_ Net-_U1-Pad5_ ? lm_741 + +.end diff --git a/library/SubcircuitLibrary/tda7050/tda7050.cir.out b/library/SubcircuitLibrary/tda7050/tda7050.cir.out new file mode 100644 index 00000000..dbb02840 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.cir.out @@ -0,0 +1,15 @@ +* c:\fossee\esim\library\subcircuitlibrary\tda7050\tda7050.cir + +.include lm_741.sub +x1 ? net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ ? net-_u1-pad7_ net-_u1-pad8_ ? lm_741 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +x2 ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad8_ ? net-_u1-pad6_ net-_u1-pad5_ ? lm_741 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tda7050/tda7050.pro b/library/SubcircuitLibrary/tda7050/tda7050.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/tda7050/tda7050.sch b/library/SubcircuitLibrary/tda7050/tda7050.sch new file mode 100644 index 00000000..2a82e7a3 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:tda7050-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6000 2750 +Wire Wire Line + 5750 2750 6100 2750 +Wire Wire Line + 5500 4950 5600 4950 +Wire Wire Line + 6700 3500 6700 3450 +Wire Wire Line + 5750 2750 5750 4350 +Wire Wire Line + 5750 3950 6000 3950 +Wire Wire Line + 6000 3950 6000 3900 +Wire Wire Line + 5750 4350 6000 4350 +Connection ~ 5750 3950 +Wire Wire Line + 6000 2950 5300 2950 +$Comp +L lm_741 X1 +U 1 1 678D14D5 +P 6150 3450 +F 0 "X1" H 5950 3450 60 0000 C CNN +F 1 "lm_741" H 6050 3200 60 0000 C CNN +F 2 "" H 6150 3450 60 0000 C CNN +F 3 "" H 6150 3450 60 0000 C CNN + 1 6150 3450 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 679DC622 +P 6350 2750 +F 0 "U1" H 6400 2850 30 0000 C CNN +F 1 "PORT" H 6350 2750 30 0000 C CNN +F 2 "" H 6350 2750 60 0000 C CNN +F 3 "" H 6350 2750 60 0000 C CNN + 8 6350 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679DC653 +P 5500 5500 +F 0 "U1" H 5550 5600 30 0000 C CNN +F 1 "PORT" H 5500 5500 30 0000 C CNN +F 2 "" H 5500 5500 60 0000 C CNN +F 3 "" H 5500 5500 60 0000 C CNN + 5 5500 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679DC678 +P 5300 4700 +F 0 "U1" H 5350 4800 30 0000 C CNN +F 1 "PORT" H 5300 4700 30 0000 C CNN +F 2 "" H 5300 4700 60 0000 C CNN +F 3 "" H 5300 4700 60 0000 C CNN + 4 5300 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679DC69F +P 7000 4800 +F 0 "U1" H 7050 4900 30 0000 C CNN +F 1 "PORT" H 7000 4800 30 0000 C CNN +F 2 "" H 7000 4800 60 0000 C CNN +F 3 "" H 7000 4800 60 0000 C CNN + 6 7000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 679DC6C8 +P 5250 4950 +F 0 "U1" H 5300 5050 30 0000 C CNN +F 1 "PORT" H 5250 4950 30 0000 C CNN +F 2 "" H 5250 4950 60 0000 C CNN +F 3 "" H 5250 4950 60 0000 C CNN + 3 5250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679DC6F3 +P 6950 3500 +F 0 "U1" H 7000 3600 30 0000 C CNN +F 1 "PORT" H 6950 3500 30 0000 C CNN +F 2 "" H 6950 3500 60 0000 C CNN +F 3 "" H 6950 3500 60 0000 C CNN + 7 6950 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679DC720 +P 5300 3600 +F 0 "U1" H 5350 3700 30 0000 C CNN +F 1 "PORT" H 5300 3600 30 0000 C CNN +F 2 "" H 5300 3600 60 0000 C CNN +F 3 "" H 5300 3600 60 0000 C CNN + 2 5300 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679DC74F +P 5150 3350 +F 0 "U1" H 5200 3450 30 0000 C CNN +F 1 "PORT" H 5150 3350 30 0000 C CNN +F 2 "" H 5150 3350 60 0000 C CNN +F 3 "" H 5150 3350 60 0000 C CNN + 1 5150 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 2950 5300 5350 +Wire Wire Line + 5300 5350 6000 5350 +Connection ~ 6000 5350 +Wire Wire Line + 5750 5500 5900 5500 +Wire Wire Line + 5900 5500 5900 5400 +Wire Wire Line + 5900 5400 6000 5400 +Connection ~ 6000 5400 +$Comp +L lm_741 X2 +U 1 1 678D14EC +P 6150 4800 +F 0 "X2" H 5950 4800 60 0000 C CNN +F 1 "lm_741" H 6050 4550 60 0000 C CNN +F 2 "" H 6150 4800 60 0000 C CNN +F 3 "" H 6150 4800 60 0000 C CNN + 1 6150 4800 + 1 0 0 1 +$EndComp +Wire Wire Line + 5550 3600 5600 3600 +Wire Wire Line + 5550 4700 5600 4700 +Wire Wire Line + 6000 5400 6000 5250 +Wire Wire Line + 5400 3350 5600 3350 +Wire Wire Line + 6750 4800 6700 4800 +Wire Wire Line + 6000 3000 6000 2950 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tda7050/tda7050.sub b/library/SubcircuitLibrary/tda7050/tda7050.sub new file mode 100644 index 00000000..a4faab2c --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.sub @@ -0,0 +1,9 @@ +* Subcircuit tda7050 +.subckt tda7050 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\fossee\esim\library\subcircuitlibrary\tda7050\tda7050.cir +.include lm_741.sub +x1 ? net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ ? net-_u1-pad7_ net-_u1-pad8_ ? lm_741 +x2 ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad8_ ? net-_u1-pad6_ net-_u1-pad5_ ? lm_741 +* Control Statements + +.ends tda7050
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml b/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml new file mode 100644 index 00000000..08c5b203 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x2></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |