diff options
Diffstat (limited to 'library/SubcircuitLibrary/HCF4042B/HCF4042B.sub')
| -rw-r--r-- | library/SubcircuitLibrary/HCF4042B/HCF4042B.sub | 208 |
1 files changed, 208 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/HCF4042B/HCF4042B.sub b/library/SubcircuitLibrary/HCF4042B/HCF4042B.sub new file mode 100644 index 00000000..cef2b4db --- /dev/null +++ b/library/SubcircuitLibrary/HCF4042B/HCF4042B.sub @@ -0,0 +1,208 @@ +* Subcircuit HCF4042B +.subckt HCF4042B net-_m1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_m4-pad1_ net-_u1-pad8_ net-_u1-pad9_ net-_m7-pad1_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ vdd vss +* c:\fossee\esim\library\subcircuitlibrary\hcf4042b\hcf4042b.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m3 net-_m1-pad3_ net-_m10-pad2_ net-_m1-pad1_ vss CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1 +m9 net-_m1-pad3_ net-_m10-pad2_ net-_m11-pad1_ vss CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1 +* u6 net-_m1-pad3_ net-_u13-pad1_ adc_bridge_1 +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter +* u36 net-_u29-pad2_ net-_u1-pad2_ d_buffer +* u19 net-_u13-pad2_ net-_u19-pad2_ d_inverter +* u20 net-_u19-pad2_ net-_u12-pad2_ d_buffer +* u12 net-_m11-pad1_ net-_u12-pad2_ adc_bridge_1 +* u32 net-_u12-pad2_ net-_u1-pad3_ d_inverter +m5 net-_m10-pad1_ net-_m10-pad2_ net-_m2-pad1_ vss CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1 +m13 net-_m10-pad3_ net-_m1-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1 +* u7 net-_m10-pad1_ net-_u16-pad1_ adc_bridge_1 +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u30 net-_u16-pad2_ net-_u30-pad2_ d_inverter +* u39 net-_u30-pad2_ net-_u1-pad5_ d_buffer +* u22 net-_u16-pad2_ net-_u22-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u14-pad2_ d_buffer +* u14 net-_m10-pad3_ net-_u14-pad2_ adc_bridge_1 +* u33 net-_u14-pad2_ net-_u1-pad6_ d_inverter +m6 net-_m12-pad1_ net-_m10-pad2_ net-_m4-pad1_ vss CMOSN W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m1-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m10-pad2_ net-_m12-pad3_ vss CMOSN W=100u L=100u M=1 +m14 net-_m12-pad3_ net-_m1-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1 +* u8 net-_m12-pad1_ net-_u17-pad1_ adc_bridge_1 +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u31 net-_u17-pad2_ net-_u31-pad2_ d_inverter +* u40 net-_u31-pad2_ net-_u1-pad8_ d_buffer +* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter +* u26 net-_u25-pad2_ net-_u15-pad2_ d_buffer +* u15 net-_m12-pad3_ net-_u15-pad2_ adc_bridge_1 +* u35 net-_u15-pad2_ net-_u1-pad9_ d_inverter +m8 net-_m15-pad1_ net-_m10-pad2_ net-_m7-pad1_ vss CMOSN W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m1-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m10-pad2_ net-_m15-pad3_ vss CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m1-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1 +* u9 net-_m15-pad1_ net-_u21-pad1_ adc_bridge_1 +* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter +* u34 net-_u21-pad2_ net-_u34-pad2_ d_inverter +* u42 net-_u34-pad2_ net-_u1-pad11_ d_buffer +* u27 net-_u21-pad2_ net-_u27-pad2_ d_inverter +* u28 net-_u27-pad2_ net-_u18-pad2_ d_buffer +* u18 net-_m15-pad3_ net-_u18-pad2_ adc_bridge_1 +* u37 net-_u18-pad2_ net-_u1-pad12_ d_inverter +* u4 net-_u1-pad13_ net-_u10-pad1_ d_inverter +m17 net-_m17-pad1_ net-_m17-pad2_ net-_m17-pad3_ vss CMOSN W=100u L=100u M=1 +m18 net-_m17-pad3_ net-_m18-pad2_ net-_m17-pad1_ vdd CMOSP W=100u L=100u M=1 +m20 net-_m17-pad3_ net-_m17-pad2_ net-_m19-pad1_ vss CMOSN W=100u L=100u M=1 +m19 net-_m19-pad1_ net-_m18-pad2_ net-_m17-pad3_ vdd CMOSP W=100u L=100u M=1 +* u10 net-_u10-pad1_ net-_m17-pad1_ dac_bridge_1 +* u2 net-_u1-pad13_ net-_m19-pad1_ dac_bridge_1 +* u44 net-_u43-pad2_ net-_u44-pad2_ d_inverter +* u43 net-_u41-pad2_ net-_u43-pad2_ d_inverter +* u41 net-_m17-pad3_ net-_u41-pad2_ adc_bridge_1 +* u45 net-_u44-pad2_ net-_m10-pad2_ dac_bridge_1 +* u46 net-_u43-pad2_ net-_m1-pad2_ dac_bridge_1 +* u3 net-_u1-pad14_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u24 net-_u11-pad2_ net-_u24-pad2_ d_buffer +* u38 net-_u24-pad2_ net-_m17-pad2_ dac_bridge_1 +* u5 net-_u11-pad1_ net-_m18-pad2_ dac_bridge_1 +a1 [net-_m1-pad3_ ] [net-_u13-pad1_ ] u6 +a2 net-_u13-pad1_ net-_u13-pad2_ u13 +a3 net-_u13-pad2_ net-_u29-pad2_ u29 +a4 net-_u29-pad2_ net-_u1-pad2_ u36 +a5 net-_u13-pad2_ net-_u19-pad2_ u19 +a6 net-_u19-pad2_ net-_u12-pad2_ u20 +a7 [net-_m11-pad1_ ] [net-_u12-pad2_ ] u12 +a8 net-_u12-pad2_ net-_u1-pad3_ u32 +a9 [net-_m10-pad1_ ] [net-_u16-pad1_ ] u7 +a10 net-_u16-pad1_ net-_u16-pad2_ u16 +a11 net-_u16-pad2_ net-_u30-pad2_ u30 +a12 net-_u30-pad2_ net-_u1-pad5_ u39 +a13 net-_u16-pad2_ net-_u22-pad2_ u22 +a14 net-_u22-pad2_ net-_u14-pad2_ u23 +a15 [net-_m10-pad3_ ] [net-_u14-pad2_ ] u14 +a16 net-_u14-pad2_ net-_u1-pad6_ u33 +a17 [net-_m12-pad1_ ] [net-_u17-pad1_ ] u8 +a18 net-_u17-pad1_ net-_u17-pad2_ u17 +a19 net-_u17-pad2_ net-_u31-pad2_ u31 +a20 net-_u31-pad2_ net-_u1-pad8_ u40 +a21 net-_u17-pad2_ net-_u25-pad2_ u25 +a22 net-_u25-pad2_ net-_u15-pad2_ u26 +a23 [net-_m12-pad3_ ] [net-_u15-pad2_ ] u15 +a24 net-_u15-pad2_ net-_u1-pad9_ u35 +a25 [net-_m15-pad1_ ] [net-_u21-pad1_ ] u9 +a26 net-_u21-pad1_ net-_u21-pad2_ u21 +a27 net-_u21-pad2_ net-_u34-pad2_ u34 +a28 net-_u34-pad2_ net-_u1-pad11_ u42 +a29 net-_u21-pad2_ net-_u27-pad2_ u27 +a30 net-_u27-pad2_ net-_u18-pad2_ u28 +a31 [net-_m15-pad3_ ] [net-_u18-pad2_ ] u18 +a32 net-_u18-pad2_ net-_u1-pad12_ u37 +a33 net-_u1-pad13_ net-_u10-pad1_ u4 +a34 [net-_u10-pad1_ ] [net-_m17-pad1_ ] u10 +a35 [net-_u1-pad13_ ] [net-_m19-pad1_ ] u2 +a36 net-_u43-pad2_ net-_u44-pad2_ u44 +a37 net-_u41-pad2_ net-_u43-pad2_ u43 +a38 [net-_m17-pad3_ ] [net-_u41-pad2_ ] u41 +a39 [net-_u44-pad2_ ] [net-_m10-pad2_ ] u45 +a40 [net-_u43-pad2_ ] [net-_m1-pad2_ ] u46 +a41 net-_u1-pad14_ net-_u11-pad1_ u3 +a42 net-_u11-pad1_ net-_u11-pad2_ u11 +a43 net-_u11-pad2_ net-_u24-pad2_ u24 +a44 [net-_u24-pad2_ ] [net-_m17-pad2_ ] u38 +a45 [net-_u11-pad1_ ] [net-_m18-pad2_ ] u5 +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u8 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u42 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u28 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u41 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u45 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u46 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends HCF4042B
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