diff options
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC/4012_test')
15 files changed, 1319 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib new file mode 100644 index 00000000..6e0697ee --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir new file mode 100644 index 00000000..c81542fc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter
+U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and
+U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out new file mode 100644 index 00000000..b34bbe45 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro new file mode 100644 index 00000000..6ce7d980 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_User
+LibName11=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch new file mode 100644 index 00000000..6b950a1d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 3350 2600 2550 2600
+Wire Wire Line
+ 3350 2700 3150 2700
+Wire Wire Line
+ 3150 2700 3150 2850
+Wire Wire Line
+ 3150 2850 2550 2850
+Wire Wire Line
+ 3350 3200 3150 3200
+Wire Wire Line
+ 3150 3200 3150 3100
+Wire Wire Line
+ 3150 3100 2550 3100
+Wire Wire Line
+ 3350 3300 2550 3300
+Wire Wire Line
+ 5200 2950 5500 2950
+$Comp
+L d_inverter U8
+U 1 1 5CEE55AB
+P 5800 2950
+F 0 "U8" H 5800 2850 60 0000 C CNN
+F 1 "d_inverter" H 5800 3100 60 0000 C CNN
+F 2 "" H 5850 2900 60 0000 C CNN
+F 3 "" H 5850 2900 60 0000 C CNN
+ 1 5800 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 2950 6500 2950
+Wire Wire Line
+ 3400 3950 2600 3950
+Wire Wire Line
+ 3400 4050 3200 4050
+Wire Wire Line
+ 3200 4050 3200 4200
+Wire Wire Line
+ 3200 4200 2600 4200
+Wire Wire Line
+ 3400 4550 3200 4550
+Wire Wire Line
+ 3200 4550 3200 4450
+Wire Wire Line
+ 3200 4450 2600 4450
+Wire Wire Line
+ 3400 4650 2600 4650
+Wire Wire Line
+ 5250 4300 5550 4300
+$Comp
+L d_inverter U9
+U 1 1 5CEE5715
+P 5850 4300
+F 0 "U9" H 5850 4200 60 0000 C CNN
+F 1 "d_inverter" H 5850 4450 60 0000 C CNN
+F 2 "" H 5900 4250 60 0000 C CNN
+F 3 "" H 5900 4250 60 0000 C CNN
+ 1 5850 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 4300 6550 4300
+$Comp
+L PORT U1
+U 2 1 5CEE57D6
+P 2300 2600
+F 0 "U1" H 2350 2700 30 0000 C CNN
+F 1 "PORT" H 2300 2600 30 0000 C CNN
+F 2 "" H 2300 2600 60 0000 C CNN
+F 3 "" H 2300 2600 60 0000 C CNN
+ 2 2300 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE587B
+P 2300 2850
+F 0 "U1" H 2350 2950 30 0000 C CNN
+F 1 "PORT" H 2300 2850 30 0000 C CNN
+F 2 "" H 2300 2850 60 0000 C CNN
+F 3 "" H 2300 2850 60 0000 C CNN
+ 3 2300 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE58AF
+P 2300 3100
+F 0 "U1" H 2350 3200 30 0000 C CNN
+F 1 "PORT" H 2300 3100 30 0000 C CNN
+F 2 "" H 2300 3100 60 0000 C CNN
+F 3 "" H 2300 3100 60 0000 C CNN
+ 4 2300 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE58E6
+P 6800 4300
+F 0 "U1" H 6850 4400 30 0000 C CNN
+F 1 "PORT" H 6800 4300 30 0000 C CNN
+F 2 "" H 6800 4300 60 0000 C CNN
+F 3 "" H 6800 4300 60 0000 C CNN
+ 13 6800 4300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE5922
+P 2300 3300
+AR Path="/5CEE58E6" Ref="U1" Part="1"
+AR Path="/5CEE5922" Ref="U1" Part="5"
+F 0 "U1" H 2350 3400 30 0000 C CNN
+F 1 "PORT" H 2300 3300 30 0000 C CNN
+F 2 "" H 2300 3300 60 0000 C CNN
+F 3 "" H 2300 3300 60 0000 C CNN
+ 5 2300 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CEE596F
+P 2350 3950
+AR Path="/5CEE5922" Ref="U1" Part="5"
+AR Path="/5CEE596F" Ref="U1" Part="9"
+F 0 "U1" H 2400 4050 30 0000 C CNN
+F 1 "PORT" H 2350 3950 30 0000 C CNN
+F 2 "" H 2350 3950 60 0000 C CNN
+F 3 "" H 2350 3950 60 0000 C CNN
+ 9 2350 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE59AF
+P 2350 4200
+AR Path="/5CEE596F" Ref="U1" Part="6"
+AR Path="/5CEE59AF" Ref="U1" Part="10"
+F 0 "U1" H 2400 4300 30 0000 C CNN
+F 1 "PORT" H 2350 4200 30 0000 C CNN
+F 2 "" H 2350 4200 60 0000 C CNN
+F 3 "" H 2350 4200 60 0000 C CNN
+ 10 2350 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE59F6
+P 2350 4450
+AR Path="/5CEE59AF" Ref="U1" Part="7"
+AR Path="/5CEE59F6" Ref="U1" Part="11"
+F 0 "U1" H 2400 4550 30 0000 C CNN
+F 1 "PORT" H 2350 4450 30 0000 C CNN
+F 2 "" H 2350 4450 60 0000 C CNN
+F 3 "" H 2350 4450 60 0000 C CNN
+ 11 2350 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE5A6A
+P 2350 4650
+AR Path="/5CEE59F6" Ref="U1" Part="8"
+AR Path="/5CEE5A6A" Ref="U1" Part="12"
+F 0 "U1" H 2400 4750 30 0000 C CNN
+F 1 "PORT" H 2350 4650 30 0000 C CNN
+F 2 "" H 2350 4650 60 0000 C CNN
+F 3 "" H 2350 4650 60 0000 C CNN
+ 12 2350 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE5BF8
+P 6750 2950
+AR Path="/5CEE5A6A" Ref="U1" Part="9"
+AR Path="/5CEE5BF8" Ref="U1" Part="1"
+F 0 "U1" H 6800 3050 30 0000 C CNN
+F 1 "PORT" H 6750 2950 30 0000 C CNN
+F 2 "" H 6750 2950 60 0000 C CNN
+F 3 "" H 6750 2950 60 0000 C CNN
+ 1 6750 2950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CEE5C72
+P 7850 1450
+F 0 "U1" H 7900 1550 30 0000 C CNN
+F 1 "PORT" H 7850 1450 30 0000 C CNN
+F 2 "" H 7850 1450 60 0000 C CNN
+F 3 "" H 7850 1450 60 0000 C CNN
+ 6 7850 1450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE5D23
+P 7850 1700
+F 0 "U1" H 7900 1800 30 0000 C CNN
+F 1 "PORT" H 7850 1700 30 0000 C CNN
+F 2 "" H 7850 1700 60 0000 C CNN
+F 3 "" H 7850 1700 60 0000 C CNN
+ 7 7850 1700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE5D75
+P 7850 1950
+F 0 "U1" H 7900 2050 30 0000 C CNN
+F 1 "PORT" H 7850 1950 30 0000 C CNN
+F 2 "" H 7850 1950 60 0000 C CNN
+F 3 "" H 7850 1950 60 0000 C CNN
+ 14 7850 1950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5DCA
+P 7850 2250
+F 0 "U1" H 7900 2350 30 0000 C CNN
+F 1 "PORT" H 7850 2250 30 0000 C CNN
+F 2 "" H 7850 2250 60 0000 C CNN
+F 3 "" H 7850 2250 60 0000 C CNN
+ 8 7850 2250
+ -1 0 0 1
+$EndComp
+NoConn ~ 7600 1450
+NoConn ~ 7600 1700
+NoConn ~ 7600 1950
+NoConn ~ 7600 2250
+$Comp
+L d_and U4
+U 1 1 5CEE56F6
+P 3850 4050
+F 0 "U4" H 3850 4050 60 0000 C CNN
+F 1 "d_and" H 3900 4150 60 0000 C CNN
+F 2 "" H 3850 4050 60 0000 C CNN
+F 3 "" H 3850 4050 60 0000 C CNN
+ 1 3850 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 5CEE56FC
+P 3850 4650
+F 0 "U5" H 3850 4650 60 0000 C CNN
+F 1 "d_and" H 3900 4750 60 0000 C CNN
+F 2 "" H 3850 4650 60 0000 C CNN
+F 3 "" H 3850 4650 60 0000 C CNN
+ 1 3850 4650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4350 4600 4300 4600
+Wire Wire Line
+ 4350 4350 4350 4600
+Wire Wire Line
+ 4350 4000 4350 4250
+Wire Wire Line
+ 4300 4000 4350 4000
+$Comp
+L d_and U7
+U 1 1 5CEE5702
+P 4800 4350
+F 0 "U7" H 4800 4350 60 0000 C CNN
+F 1 "d_and" H 4850 4450 60 0000 C CNN
+F 2 "" H 4800 4350 60 0000 C CNN
+F 3 "" H 4800 4350 60 0000 C CNN
+ 1 4800 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4250 2650 4300 2650
+Wire Wire Line
+ 4300 3250 4250 3250
+Wire Wire Line
+ 4300 2650 4300 2900
+Wire Wire Line
+ 4300 3000 4300 3250
+$Comp
+L d_and U6
+U 1 1 5CEE5432
+P 4750 3000
+F 0 "U6" H 4750 3000 60 0000 C CNN
+F 1 "d_and" H 4800 3100 60 0000 C CNN
+F 2 "" H 4750 3000 60 0000 C CNN
+F 3 "" H 4750 3000 60 0000 C CNN
+ 1 4750 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5CEE540C
+P 3800 3300
+F 0 "U3" H 3800 3300 60 0000 C CNN
+F 1 "d_and" H 3850 3400 60 0000 C CNN
+F 2 "" H 3800 3300 60 0000 C CNN
+F 3 "" H 3800 3300 60 0000 C CNN
+ 1 3800 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5CEE53DC
+P 3800 2700
+F 0 "U2" H 3800 2700 60 0000 C CNN
+F 1 "d_and" H 3850 2800 60 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 1 3800 2700
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub new file mode 100644 index 00000000..a92e83f3 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012
+.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4012
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib new file mode 100644 index 00000000..b58b86b5 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4012
+#
+DEF 4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir new file mode 100644 index 00000000..89708044 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim-Workspace\4012_test\4012_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 15:21:40
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U7-Pad1_ Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ ? ? ? Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ Net-_U7-Pad2_ ? 4012
+U5 a1 b1 c1 d1 Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ adc_bridge_4
+v1 a1 GND DC
+v2 b1 GND DC
+v3 c1 GND DC
+v4 d1 GND DC
+U9 a2 b2 d2 c2 Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ adc_bridge_4
+v8 a2 GND DC
+v7 b2 GND DC
+v6 d2 GND DC
+v5 c2 GND DC
+U1 a1 plot_v1
+U3 b1 plot_v1
+U4 c1 plot_v1
+U2 d1 plot_v1
+U11 d2 plot_v1
+U10 c2 plot_v1
+U13 a2 plot_v1
+U12 b2 plot_v1
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ q1 q2 dac_bridge_2
+U8 q2 plot_v1
+U6 q1 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out new file mode 100644 index 00000000..1b8ab981 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out @@ -0,0 +1,53 @@ +* c:\users\malli\esim-workspace\4012_test\4012_test.cir + +.include 4012.sub +x1 net-_u7-pad1_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ? ? ? net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u7-pad2_ ? 4012 +* u5 a1 b1 c1 d1 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ adc_bridge_4 +v1 a1 gnd dc 0 +v2 b1 gnd dc 0 +v3 c1 gnd dc 0 +v4 d1 gnd dc 0 +* u9 a2 b2 d2 c2 net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ adc_bridge_4 +v8 a2 gnd dc 0 +v7 b2 gnd dc 0 +v6 d2 gnd dc 0 +v5 c2 gnd dc 0 +* u1 a1 plot_v1 +* u3 b1 plot_v1 +* u4 c1 plot_v1 +* u2 d1 plot_v1 +* u11 d2 plot_v1 +* u10 c2 plot_v1 +* u13 a2 plot_v1 +* u12 b2 plot_v1 +* u7 net-_u7-pad1_ net-_u7-pad2_ q1 q2 dac_bridge_2 +* u8 q2 plot_v1 +* u6 q1 plot_v1 +a1 [a1 b1 c1 d1 ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] u5 +a2 [a2 b2 d2 c2 ] [net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] u9 +a3 [net-_u7-pad1_ net-_u7-pad2_ ] [q1 q2 ] u7 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(a1) +plot v(b1) +plot v(c1) +plot v(d1) +plot v(d2) +plot v(c2) +plot v(a2) +plot v(b2) +plot v(q2) +plot v(q1) +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro new file mode 100644 index 00000000..ee32c69b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro @@ -0,0 +1,45 @@ +update=06/01/19 15:09:21
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_User
+LibName12=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj new file mode 100644 index 00000000..6d5be088 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj @@ -0,0 +1 @@ +schematicFile 4012_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch new file mode 100644 index 00000000..1380bb1d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch @@ -0,0 +1,501 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4012 X1
+U 1 1 5CF22C85
+P 5050 4050
+F 0 "X1" H 5050 4050 60 0000 C CNN
+F 1 "4012" H 5050 4250 60 0000 C CNN
+F 2 "" H 5050 4050 60 0000 C CNN
+F 3 "" H 5050 4050 60 0000 C CNN
+ 1 5050 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_4 U5
+U 1 1 5CF24801
+P 3600 4050
+F 0 "U5" H 3600 4050 60 0000 C CNN
+F 1 "adc_bridge_4" H 3600 4350 60 0000 C CNN
+F 2 "" H 3600 4050 60 0000 C CNN
+F 3 "" H 3600 4050 60 0000 C CNN
+ 1 3600 4050
+ 1 0 0 -1
+$EndComp
+NoConn ~ 4550 4350
+NoConn ~ 5600 3750
+$Comp
+L DC v1
+U 1 1 5CF2488C
+P 1900 3450
+F 0 "v1" H 1700 3550 60 0000 C CNN
+F 1 "DC" H 1700 3400 60 0000 C CNN
+F 2 "R1" H 1600 3450 60 0000 C CNN
+F 3 "" H 1900 3450 60 0000 C CNN
+ 1 1900 3450
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v2
+U 1 1 5CF248E2
+P 1900 4000
+F 0 "v2" H 1700 4100 60 0000 C CNN
+F 1 "DC" H 1700 3950 60 0000 C CNN
+F 2 "R1" H 1600 4000 60 0000 C CNN
+F 3 "" H 1900 4000 60 0000 C CNN
+ 1 1900 4000
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 5CF24906
+P 1900 4550
+F 0 "v3" H 1700 4650 60 0000 C CNN
+F 1 "DC" H 1700 4500 60 0000 C CNN
+F 2 "R1" H 1600 4550 60 0000 C CNN
+F 3 "" H 1900 4550 60 0000 C CNN
+ 1 1900 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 5CF24935
+P 1900 5100
+F 0 "v4" H 1700 5200 60 0000 C CNN
+F 1 "DC" H 1700 5050 60 0000 C CNN
+F 2 "R1" H 1600 5100 60 0000 C CNN
+F 3 "" H 1900 5100 60 0000 C CNN
+ 1 1900 5100
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 2350 3450 2800 3450
+Wire Wire Line
+ 2800 3450 2800 3850
+Wire Wire Line
+ 2800 3850 3050 3850
+Wire Wire Line
+ 3050 3950 2350 3950
+Wire Wire Line
+ 2350 3950 2350 4000
+Wire Wire Line
+ 2350 4550 2700 4550
+Wire Wire Line
+ 2700 4550 2700 4050
+Wire Wire Line
+ 2700 4050 3050 4050
+Wire Wire Line
+ 3050 4150 3050 5100
+Wire Wire Line
+ 3050 5100 2350 5100
+Wire Wire Line
+ 1450 3450 1200 3450
+Wire Wire Line
+ 1200 3450 1200 5100
+Wire Wire Line
+ 1200 4000 1450 4000
+Wire Wire Line
+ 1200 4550 1450 4550
+Connection ~ 1200 4000
+Wire Wire Line
+ 1200 5100 1450 5100
+Connection ~ 1200 4550
+$Comp
+L adc_bridge_4 U9
+U 1 1 5CF24B4A
+P 6450 4050
+F 0 "U9" H 6450 4050 60 0000 C CNN
+F 1 "adc_bridge_4" H 6450 4350 60 0000 C CNN
+F 2 "" H 6450 4050 60 0000 C CNN
+F 3 "" H 6450 4050 60 0000 C CNN
+ 1 6450 4050
+ -1 0 0 1
+$EndComp
+$Comp
+L DC v8
+U 1 1 5CF24B50
+P 8150 4650
+F 0 "v8" H 7950 4750 60 0000 C CNN
+F 1 "DC" H 7950 4600 60 0000 C CNN
+F 2 "R1" H 7850 4650 60 0000 C CNN
+F 3 "" H 8150 4650 60 0000 C CNN
+ 1 8150 4650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v7
+U 1 1 5CF24B56
+P 8150 4100
+F 0 "v7" H 7950 4200 60 0000 C CNN
+F 1 "DC" H 7950 4050 60 0000 C CNN
+F 2 "R1" H 7850 4100 60 0000 C CNN
+F 3 "" H 8150 4100 60 0000 C CNN
+ 1 8150 4100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v6
+U 1 1 5CF24B5C
+P 8150 3550
+F 0 "v6" H 7950 3650 60 0000 C CNN
+F 1 "DC" H 7950 3500 60 0000 C CNN
+F 2 "R1" H 7850 3550 60 0000 C CNN
+F 3 "" H 8150 3550 60 0000 C CNN
+ 1 8150 3550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v5
+U 1 1 5CF24B62
+P 8150 3000
+F 0 "v5" H 7950 3100 60 0000 C CNN
+F 1 "DC" H 7950 2950 60 0000 C CNN
+F 2 "R1" H 7850 3000 60 0000 C CNN
+F 3 "" H 8150 3000 60 0000 C CNN
+ 1 8150 3000
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 7700 4650 7250 4650
+Wire Wire Line
+ 7250 4650 7250 4250
+Wire Wire Line
+ 7250 4250 7000 4250
+Wire Wire Line
+ 7000 4150 7700 4150
+Wire Wire Line
+ 7700 4150 7700 4100
+Wire Wire Line
+ 7700 3550 7350 3550
+Wire Wire Line
+ 7350 3400 7350 4050
+Wire Wire Line
+ 7350 4050 7000 4050
+Wire Wire Line
+ 7000 3950 7000 3000
+Wire Wire Line
+ 7000 3000 7700 3000
+Wire Wire Line
+ 8600 4650 8850 4650
+Wire Wire Line
+ 8850 4650 8850 3000
+Wire Wire Line
+ 8850 4100 8600 4100
+Wire Wire Line
+ 8850 3550 8600 3550
+Connection ~ 8850 4100
+Wire Wire Line
+ 8850 3000 8600 3000
+Connection ~ 8850 3550
+Wire Wire Line
+ 5900 3950 5600 3950
+Wire Wire Line
+ 5600 4050 5900 4050
+Wire Wire Line
+ 5600 4150 5900 4150
+Wire Wire Line
+ 5600 4250 5900 4250
+Wire Wire Line
+ 4550 3850 4150 3850
+Wire Wire Line
+ 4150 3950 4550 3950
+Wire Wire Line
+ 4150 4050 4550 4050
+Wire Wire Line
+ 4550 4150 4150 4150
+$Comp
+L plot_v1 U1
+U 1 1 5CF2512D
+P 2400 3300
+F 0 "U1" H 2400 3800 60 0000 C CNN
+F 1 "plot_v1" H 2600 3650 60 0000 C CNN
+F 2 "" H 2400 3300 60 0000 C CNN
+F 3 "" H 2400 3300 60 0000 C CNN
+ 1 2400 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 5CF25268
+P 3000 3450
+F 0 "U3" H 3000 3950 60 0000 C CNN
+F 1 "plot_v1" H 3200 3800 60 0000 C CNN
+F 2 "" H 3000 3450 60 0000 C CNN
+F 3 "" H 3000 3450 60 0000 C CNN
+ 1 3000 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 5CF252A7
+P 3050 4600
+F 0 "U4" H 3050 5100 60 0000 C CNN
+F 1 "plot_v1" H 3250 4950 60 0000 C CNN
+F 2 "" H 3050 4600 60 0000 C CNN
+F 3 "" H 3050 4600 60 0000 C CNN
+ 1 3050 4600
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 5CF25311
+P 2900 5100
+F 0 "U2" H 2900 5600 60 0000 C CNN
+F 1 "plot_v1" H 3100 5450 60 0000 C CNN
+F 2 "" H 2900 5100 60 0000 C CNN
+F 3 "" H 2900 5100 60 0000 C CNN
+ 1 2900 5100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 2400 3100 2400 3450
+Connection ~ 2400 3450
+Wire Wire Line
+ 3000 3250 3000 3550
+Wire Wire Line
+ 3000 3550 2700 3550
+Wire Wire Line
+ 2700 3550 2700 3950
+Connection ~ 2700 3950
+Wire Wire Line
+ 2700 4450 3250 4450
+Wire Wire Line
+ 3250 4450 3250 4600
+Connection ~ 2700 4450
+Wire Wire Line
+ 2900 5100 2900 5300
+Connection ~ 2900 5100
+Wire Wire Line
+ 1200 4250 850 4250
+Wire Wire Line
+ 850 4150 850 4500
+Connection ~ 1200 4250
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5CF254BC
+P 850 4150
+F 0 "#FLG01" H 850 4245 50 0001 C CNN
+F 1 "PWR_FLAG" H 850 4330 50 0000 C CNN
+F 2 "" H 850 4150 50 0000 C CNN
+F 3 "" H 850 4150 50 0000 C CNN
+ 1 850 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 5CF254EE
+P 850 4500
+F 0 "#PWR02" H 850 4250 50 0001 C CNN
+F 1 "eSim_GND" H 850 4350 50 0000 C CNN
+F 2 "" H 850 4500 50 0001 C CNN
+F 3 "" H 850 4500 50 0001 C CNN
+ 1 850 4500
+ 1 0 0 -1
+$EndComp
+Connection ~ 850 4250
+Text GLabel 2300 3250 0 60 Input ~ 0
+a1
+Text GLabel 2900 3350 0 60 Input ~ 0
+b1
+Text GLabel 2900 4550 3 60 Input ~ 0
+c1
+Text GLabel 2800 5200 0 60 Input ~ 0
+d1
+Wire Wire Line
+ 2800 5200 2900 5200
+Connection ~ 2900 5200
+Wire Wire Line
+ 2900 4450 2900 4550
+Connection ~ 2900 4450
+Wire Wire Line
+ 2900 3350 3000 3350
+Connection ~ 3000 3350
+Wire Wire Line
+ 2300 3250 2400 3250
+Connection ~ 2400 3250
+$Comp
+L plot_v1 U11
+U 1 1 5CF2581B
+P 7200 3000
+F 0 "U11" H 7200 3500 60 0000 C CNN
+F 1 "plot_v1" H 7400 3350 60 0000 C CNN
+F 2 "" H 7200 3000 60 0000 C CNN
+F 3 "" H 7200 3000 60 0000 C CNN
+ 1 7200 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U10
+U 1 1 5CF25889
+P 6500 3450
+F 0 "U10" H 6500 3950 60 0000 C CNN
+F 1 "plot_v1" H 6700 3800 60 0000 C CNN
+F 2 "" H 6500 3450 60 0000 C CNN
+F 3 "" H 6500 3450 60 0000 C CNN
+ 1 6500 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U13
+U 1 1 5CF258F2
+P 7550 4750
+F 0 "U13" H 7550 5250 60 0000 C CNN
+F 1 "plot_v1" H 7750 5100 60 0000 C CNN
+F 2 "" H 7550 4750 60 0000 C CNN
+F 3 "" H 7550 4750 60 0000 C CNN
+ 1 7550 4750
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U12
+U 1 1 5CF2597E
+P 7200 4800
+F 0 "U12" H 7200 5300 60 0000 C CNN
+F 1 "plot_v1" H 7400 5150 60 0000 C CNN
+F 2 "" H 7200 4800 60 0000 C CNN
+F 3 "" H 7200 4800 60 0000 C CNN
+ 1 7200 4800
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 7550 4950 7550 4650
+Connection ~ 7550 4650
+Wire Wire Line
+ 7000 4800 7150 4800
+Wire Wire Line
+ 7150 4800 7150 4150
+Connection ~ 7150 4150
+Wire Wire Line
+ 7200 2800 7200 3400
+Wire Wire Line
+ 7200 3400 7350 3400
+Connection ~ 7350 3550
+Wire Wire Line
+ 6500 3250 6500 3450
+Wire Wire Line
+ 6500 3450 7000 3450
+Connection ~ 7000 3450
+Wire Wire Line
+ 8850 3800 9450 3800
+Wire Wire Line
+ 9450 3800 9450 4150
+Connection ~ 8850 3800
+$Comp
+L eSim_GND #PWR03
+U 1 1 5CF25F3B
+P 9450 4150
+F 0 "#PWR03" H 9450 3900 50 0001 C CNN
+F 1 "eSim_GND" H 9450 4000 50 0000 C CNN
+F 2 "" H 9450 4150 50 0001 C CNN
+F 3 "" H 9450 4150 50 0001 C CNN
+ 1 9450 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U7
+U 1 1 5CF26149
+P 5050 2800
+F 0 "U7" H 5050 2800 60 0000 C CNN
+F 1 "dac_bridge_2" H 5100 2950 60 0000 C CNN
+F 2 "" H 5050 2800 60 0000 C CNN
+F 3 "" H 5050 2800 60 0000 C CNN
+ 1 5050 2800
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 4550 3250 4550 3750
+Wire Wire Line
+ 4550 3250 5000 3250
+Wire Wire Line
+ 5100 3250 5800 3250
+Wire Wire Line
+ 5800 3250 5800 3850
+Wire Wire Line
+ 5800 3850 5600 3850
+$Comp
+L plot_v1 U8
+U 1 1 5CF263AC
+P 5400 2000
+F 0 "U8" H 5400 2500 60 0000 C CNN
+F 1 "plot_v1" H 5600 2350 60 0000 C CNN
+F 2 "" H 5400 2000 60 0000 C CNN
+F 3 "" H 5400 2000 60 0000 C CNN
+ 1 5400 2000
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 5CF26445
+P 4800 2050
+F 0 "U6" H 4800 2550 60 0000 C CNN
+F 1 "plot_v1" H 5000 2400 60 0000 C CNN
+F 2 "" H 4800 2050 60 0000 C CNN
+F 3 "" H 4800 2050 60 0000 C CNN
+ 1 4800 2050
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 5000 2250 5000 2050
+Wire Wire Line
+ 5000 2050 4600 2050
+Wire Wire Line
+ 5100 2250 5100 2000
+Wire Wire Line
+ 5100 2000 5600 2000
+Text GLabel 4800 1850 1 60 Output ~ 0
+q1
+Text GLabel 5400 1850 1 60 Output ~ 0
+q2
+Text GLabel 7350 2900 2 60 Input ~ 0
+d2
+Text GLabel 6800 3350 1 60 Input ~ 0
+c2
+Text GLabel 7100 4500 0 60 Input ~ 0
+b2
+Text GLabel 7450 4800 0 60 Input ~ 0
+a2
+Wire Wire Line
+ 7450 4800 7550 4800
+Connection ~ 7550 4800
+Wire Wire Line
+ 7100 4500 7150 4500
+Connection ~ 7150 4500
+Wire Wire Line
+ 6800 3350 6800 3450
+Connection ~ 6800 3450
+Wire Wire Line
+ 7350 2900 7200 2900
+Connection ~ 7200 2900
+Wire Wire Line
+ 5400 1850 5400 2000
+Connection ~ 5400 2000
+Wire Wire Line
+ 4800 1850 4800 2050
+Connection ~ 4800 2050
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test_Previous_Values.xml new file mode 100644 index 00000000..87c47261 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v5 name="Source type">dc<field1 name="Value">0</field1></v5></source><model><u5 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u5><u9 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u9><u7 name="type">dac_bridge<field9 name="Enter value for input load (default=1.0e-12)" /><field10 name="Enter value for out_low (default=0.0)" /><field11 name="Enter value for out_high (default=5.0)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /><field14 name="Enter value for out_undef (default=0.5)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4012</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis b/Examples/Analysis_Of_Digital_IC/4012_test/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file |