diff options
| author | rahulp13 | 2020-02-14 15:16:35 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-14 15:16:35 +0530 |
| commit | cb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch) | |
| tree | de1b292a10e8196689bf1a208fe6fe32f4618846 /Examples/Analysis_Of_Digital_IC/4012_test | |
| parent | 08d4a0336550a0e610709970a0c5d366e109fe82 (diff) | |
| download | eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2 eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip | |
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC/4012_test')
15 files changed, 1319 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib new file mode 100644 index 00000000..6e0697ee --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir new file mode 100644 index 00000000..c81542fc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter
+U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and
+U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out new file mode 100644 index 00000000..b34bbe45 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro new file mode 100644 index 00000000..6ce7d980 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_User
+LibName11=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch new file mode 100644 index 00000000..6b950a1d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 5850 2900 60 0000 C CNN
+F 3 "" H 5850 2900 60 0000 C CNN
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+ 1 0 0 -1
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 5900 4250 60 0000 C CNN
+F 3 "" H 5900 4250 60 0000 C CNN
+ 1 5850 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 4300 6550 4300
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+L PORT U1
+U 2 1 5CEE57D6
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+F 1 "PORT" H 2300 2600 30 0000 C CNN
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+F 3 "" H 2300 2600 60 0000 C CNN
+ 2 2300 2600
+ 1 0 0 -1
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+F 1 "PORT" H 2300 2850 30 0000 C CNN
+F 2 "" H 2300 2850 60 0000 C CNN
+F 3 "" H 2300 2850 60 0000 C CNN
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+ 1 0 0 -1
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+U 4 1 5CEE58AF
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+F 1 "PORT" H 2300 3100 30 0000 C CNN
+F 2 "" H 2300 3100 60 0000 C CNN
+F 3 "" H 2300 3100 60 0000 C CNN
+ 4 2300 3100
+ 1 0 0 -1
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+$Comp
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+U 13 1 5CEE58E6
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+F 2 "" H 6800 4300 60 0000 C CNN
+F 3 "" H 6800 4300 60 0000 C CNN
+ 13 6800 4300
+ -1 0 0 1
+$EndComp
+$Comp
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+P 2300 3300
+AR Path="/5CEE58E6" Ref="U1" Part="1"
+AR Path="/5CEE5922" Ref="U1" Part="5"
+F 0 "U1" H 2350 3400 30 0000 C CNN
+F 1 "PORT" H 2300 3300 30 0000 C CNN
+F 2 "" H 2300 3300 60 0000 C CNN
+F 3 "" H 2300 3300 60 0000 C CNN
+ 5 2300 3300
+ 1 0 0 -1
+$EndComp
+$Comp
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+U 9 1 5CEE596F
+P 2350 3950
+AR Path="/5CEE5922" Ref="U1" Part="5"
+AR Path="/5CEE596F" Ref="U1" Part="9"
+F 0 "U1" H 2400 4050 30 0000 C CNN
+F 1 "PORT" H 2350 3950 30 0000 C CNN
+F 2 "" H 2350 3950 60 0000 C CNN
+F 3 "" H 2350 3950 60 0000 C CNN
+ 9 2350 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE59AF
+P 2350 4200
+AR Path="/5CEE596F" Ref="U1" Part="6"
+AR Path="/5CEE59AF" Ref="U1" Part="10"
+F 0 "U1" H 2400 4300 30 0000 C CNN
+F 1 "PORT" H 2350 4200 30 0000 C CNN
+F 2 "" H 2350 4200 60 0000 C CNN
+F 3 "" H 2350 4200 60 0000 C CNN
+ 10 2350 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE59F6
+P 2350 4450
+AR Path="/5CEE59AF" Ref="U1" Part="7"
+AR Path="/5CEE59F6" Ref="U1" Part="11"
+F 0 "U1" H 2400 4550 30 0000 C CNN
+F 1 "PORT" H 2350 4450 30 0000 C CNN
+F 2 "" H 2350 4450 60 0000 C CNN
+F 3 "" H 2350 4450 60 0000 C CNN
+ 11 2350 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE5A6A
+P 2350 4650
+AR Path="/5CEE59F6" Ref="U1" Part="8"
+AR Path="/5CEE5A6A" Ref="U1" Part="12"
+F 0 "U1" H 2400 4750 30 0000 C CNN
+F 1 "PORT" H 2350 4650 30 0000 C CNN
+F 2 "" H 2350 4650 60 0000 C CNN
+F 3 "" H 2350 4650 60 0000 C CNN
+ 12 2350 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE5BF8
+P 6750 2950
+AR Path="/5CEE5A6A" Ref="U1" Part="9"
+AR Path="/5CEE5BF8" Ref="U1" Part="1"
+F 0 "U1" H 6800 3050 30 0000 C CNN
+F 1 "PORT" H 6750 2950 30 0000 C CNN
+F 2 "" H 6750 2950 60 0000 C CNN
+F 3 "" H 6750 2950 60 0000 C CNN
+ 1 6750 2950
+ -1 0 0 1
+$EndComp
+$Comp
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+F 0 "U1" H 7900 1550 30 0000 C CNN
+F 1 "PORT" H 7850 1450 30 0000 C CNN
+F 2 "" H 7850 1450 60 0000 C CNN
+F 3 "" H 7850 1450 60 0000 C CNN
+ 6 7850 1450
+ -1 0 0 1
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+$Comp
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+F 0 "U1" H 7900 1800 30 0000 C CNN
+F 1 "PORT" H 7850 1700 30 0000 C CNN
+F 2 "" H 7850 1700 60 0000 C CNN
+F 3 "" H 7850 1700 60 0000 C CNN
+ 7 7850 1700
+ -1 0 0 1
+$EndComp
+$Comp
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+U 14 1 5CEE5D75
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+F 3 "" H 7850 1950 60 0000 C CNN
+ 14 7850 1950
+ -1 0 0 1
+$EndComp
+$Comp
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+F 2 "" H 7850 2250 60 0000 C CNN
+F 3 "" H 7850 2250 60 0000 C CNN
+ 8 7850 2250
+ -1 0 0 1
+$EndComp
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+NoConn ~ 7600 2250
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+ 1 0 0 -1
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+ 1 0 0 -1
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+$Comp
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+ 1 0 0 -1
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+$Comp
+L d_and U2
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diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub new file mode 100644 index 00000000..a92e83f3 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012
+.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4012
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib new file mode 100644 index 00000000..b58b86b5 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4012
+#
+DEF 4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir new file mode 100644 index 00000000..89708044 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim-Workspace\4012_test\4012_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 15:21:40
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U7-Pad1_ Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ ? ? ? Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ Net-_U7-Pad2_ ? 4012
+U5 a1 b1 c1 d1 Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ adc_bridge_4
+v1 a1 GND DC
+v2 b1 GND DC
+v3 c1 GND DC
+v4 d1 GND DC
+U9 a2 b2 d2 c2 Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ adc_bridge_4
+v8 a2 GND DC
+v7 b2 GND DC
+v6 d2 GND DC
+v5 c2 GND DC
+U1 a1 plot_v1
+U3 b1 plot_v1
+U4 c1 plot_v1
+U2 d1 plot_v1
+U11 d2 plot_v1
+U10 c2 plot_v1
+U13 a2 plot_v1
+U12 b2 plot_v1
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ q1 q2 dac_bridge_2
+U8 q2 plot_v1
+U6 q1 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out new file mode 100644 index 00000000..1b8ab981 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out @@ -0,0 +1,53 @@ +* c:\users\malli\esim-workspace\4012_test\4012_test.cir + +.include 4012.sub +x1 net-_u7-pad1_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ? ? ? net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u7-pad2_ ? 4012 +* u5 a1 b1 c1 d1 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ adc_bridge_4 +v1 a1 gnd dc 0 +v2 b1 gnd dc 0 +v3 c1 gnd dc 0 +v4 d1 gnd dc 0 +* u9 a2 b2 d2 c2 net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ adc_bridge_4 +v8 a2 gnd dc 0 +v7 b2 gnd dc 0 +v6 d2 gnd dc 0 +v5 c2 gnd dc 0 +* u1 a1 plot_v1 +* u3 b1 plot_v1 +* u4 c1 plot_v1 +* u2 d1 plot_v1 +* u11 d2 plot_v1 +* u10 c2 plot_v1 +* u13 a2 plot_v1 +* u12 b2 plot_v1 +* u7 net-_u7-pad1_ net-_u7-pad2_ q1 q2 dac_bridge_2 +* u8 q2 plot_v1 +* u6 q1 plot_v1 +a1 [a1 b1 c1 d1 ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] u5 +a2 [a2 b2 d2 c2 ] [net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] u9 +a3 [net-_u7-pad1_ net-_u7-pad2_ ] [q1 q2 ] u7 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(a1) +plot v(b1) +plot v(c1) +plot v(d1) +plot v(d2) +plot v(c2) +plot v(a2) +plot v(b2) +plot v(q2) +plot v(q1) +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro new file mode 100644 index 00000000..ee32c69b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro @@ -0,0 +1,45 @@ +update=06/01/19 15:09:21
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_User
+LibName12=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj new file mode 100644 index 00000000..6d5be088 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj @@ -0,0 +1 @@ +schematicFile 4012_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch new file mode 100644 index 00000000..1380bb1d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch @@ -0,0 +1,501 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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