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path: root/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out
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* c:\users\malli\esim-workspace\4012_test\4012_test.cir

.include 4012.sub
x1 net-_u7-pad1_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ? ? ? net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u7-pad2_ ? 4012
* u5  a1 b1 c1 d1 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ adc_bridge_4
v1 a1 gnd  dc 0
v2 b1 gnd  dc 0
v3 c1 gnd  dc 0
v4 d1 gnd  dc 0
* u9  a2 b2 d2 c2 net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ adc_bridge_4
v8 a2 gnd  dc 0
v7 b2 gnd  dc 0
v6 d2 gnd  dc 0
v5 c2 gnd  dc 0
* u1  a1 plot_v1
* u3  b1 plot_v1
* u4  c1 plot_v1
* u2  d1 plot_v1
* u11  d2 plot_v1
* u10  c2 plot_v1
* u13  a2 plot_v1
* u12  b2 plot_v1
* u7  net-_u7-pad1_ net-_u7-pad2_ q1 q2 dac_bridge_2
* u8  q2 plot_v1
* u6  q1 plot_v1
a1 [a1 b1 c1 d1 ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] u5
a2 [a2 b2 d2 c2 ] [net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] u9
a3 [net-_u7-pad1_ net-_u7-pad2_ ] [q1 q2 ] u7
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
.tran 10e-03 100e-03 0e-03

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot v(a1)
plot v(b1)
plot v(c1)
plot v(d1)
plot v(d2)
plot v(c2)
plot v(a2)
plot v(b2)
plot v(q2)
plot v(q1)
.endc
.end