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authorSumanto Kar2024-11-21 20:51:48 +0530
committerGitHub2024-11-21 20:51:48 +0530
commit70dbdd89d848221c612f6111b9d84e52211c3287 (patch)
tree9d9e029da9e5c82587eb527ab70a734282016276
parentbad2ecec9f975e23c24242c1798a734d11285241 (diff)
parent4783a9db2daecb6256a4cb89c01e9b369ae2e927 (diff)
downloadeSim-70dbdd89d848221c612f6111b9d84e52211c3287.tar.gz
eSim-70dbdd89d848221c612f6111b9d84e52211c3287.tar.bz2
eSim-70dbdd89d848221c612f6111b9d84e52211c3287.zip
Merge pull request #287 from Eyantra698Sumanto/master
Subcircuit Files of ICs(Contributor: Sudheshna Prabakaran)
Diffstat
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib170
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir48
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out160
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro73
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch896
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub154
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/CA3140_sub-cache.lib190
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir55
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir.out72
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/CA3140_sub.pro73
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sch914
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sub66
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/CA3140_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/D.lib2
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/PMOS-0.5um.lib6
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/CA3140_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/LM111_sub/LM111_sub-cache.lib139
-rw-r--r--library/SubcircuitLibrary/LM111_sub/LM111_sub.cir56
-rw-r--r--library/SubcircuitLibrary/LM111_sub/LM111_sub.cir.out66
-rw-r--r--library/SubcircuitLibrary/LM111_sub/LM111_sub.pro73
-rw-r--r--library/SubcircuitLibrary/LM111_sub/LM111_sub.sch898
-rw-r--r--library/SubcircuitLibrary/LM111_sub/LM111_sub.sub60
-rw-r--r--library/SubcircuitLibrary/LM111_sub/LM111_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/LM111_sub/NJF.lib4
-rw-r--r--library/SubcircuitLibrary/LM111_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/LM111_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/LM111_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/LM323A_sub-cache.lib158
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir66
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir.out79
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/LM323A_sub.pro73
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sch986
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sub73
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/LM323A_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/NJF.lib4
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/LM323A_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/LM341_sub/LM341_sub-cache.lib138
-rw-r--r--library/SubcircuitLibrary/LM341_sub/LM341_sub.cir56
-rw-r--r--library/SubcircuitLibrary/LM341_sub/LM341_sub.cir.out68
-rw-r--r--library/SubcircuitLibrary/LM341_sub/LM341_sub.pro73
-rw-r--r--library/SubcircuitLibrary/LM341_sub/LM341_sub.sch825
-rw-r--r--library/SubcircuitLibrary/LM341_sub/LM341_sub.sub62
-rw-r--r--library/SubcircuitLibrary/LM341_sub/LM341_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/LM341_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/LM341_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/LM341_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/LM380_sub/D.lib2
-rw-r--r--library/SubcircuitLibrary/LM380_sub/LM380_sub-cache.lib145
-rw-r--r--library/SubcircuitLibrary/LM380_sub/LM380_sub.cir34
-rw-r--r--library/SubcircuitLibrary/LM380_sub/LM380_sub.cir.out38
-rw-r--r--library/SubcircuitLibrary/LM380_sub/LM380_sub.pro73
-rw-r--r--library/SubcircuitLibrary/LM380_sub/LM380_sub.sch622
-rw-r--r--library/SubcircuitLibrary/LM380_sub/LM380_sub.sub32
-rw-r--r--library/SubcircuitLibrary/LM380_sub/LM380_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/LM380_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/LM380_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/LM380_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/3_and-cache.lib61
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/3_and.cir13
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out20
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/3_and.pro43
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/3_and.sch130
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/3_and.sub14
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/3_and_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_OR-cache.lib63
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_OR.cir14
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out24
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_OR.pro44
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_OR.sch150
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_OR.sub18
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_OR_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and-cache.lib79
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and-rescue.lib22
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and.cir13
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and.cir.out18
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and.pro57
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and.sch151
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and.sub12
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/4_and_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and-cache.lib79
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and-rescue.lib22
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and.cir14
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and.cir.out22
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and.pro49
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and.sch171
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and.sub16
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/5_and_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub-cache.lib306
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir60
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir.out188
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.pro73
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch1136
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sub182
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN7483A_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/lm102_sub/D.lib2
-rw-r--r--library/SubcircuitLibrary/lm102_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/lm102_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/lm102_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib162
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.cir51
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out61
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.pro73
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.sch801
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.sub55
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/lm110_sub/D.lib2
-rw-r--r--library/SubcircuitLibrary/lm110_sub/NJF.lib4
-rw-r--r--library/SubcircuitLibrary/lm110_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/lm110_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/lm110_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/lm110_sub/lm110_sub-cache.lib165
-rw-r--r--library/SubcircuitLibrary/lm110_sub/lm110_sub.cir45
-rw-r--r--library/SubcircuitLibrary/lm110_sub/lm110_sub.cir.out50
-rw-r--r--library/SubcircuitLibrary/lm110_sub/lm110_sub.pro73
-rw-r--r--library/SubcircuitLibrary/lm110_sub/lm110_sub.sch707
-rw-r--r--library/SubcircuitLibrary/lm110_sub/lm110_sub.sub44
-rw-r--r--library/SubcircuitLibrary/lm110_sub/lm110_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/lm123_sub/NJF.lib4
-rw-r--r--library/SubcircuitLibrary/lm123_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/lm123_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/lm123_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/lm123_sub/lm123_sub-cache.lib158
-rw-r--r--library/SubcircuitLibrary/lm123_sub/lm123_sub.cir64
-rw-r--r--library/SubcircuitLibrary/lm123_sub/lm123_sub.cir.out77
-rw-r--r--library/SubcircuitLibrary/lm123_sub/lm123_sub.pro73
-rw-r--r--library/SubcircuitLibrary/lm123_sub/lm123_sub.sch976
-rw-r--r--library/SubcircuitLibrary/lm123_sub/lm123_sub.sub71
-rw-r--r--library/SubcircuitLibrary/lm123_sub/lm123_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/lm384_sub/D.lib2
-rw-r--r--library/SubcircuitLibrary/lm384_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/lm384_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/lm384_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/lm384_sub/lm384_sub-cache.lib145
-rw-r--r--library/SubcircuitLibrary/lm384_sub/lm384_sub.cir34
-rw-r--r--library/SubcircuitLibrary/lm384_sub/lm384_sub.cir.out38
-rw-r--r--library/SubcircuitLibrary/lm384_sub/lm384_sub.pro73
-rw-r--r--library/SubcircuitLibrary/lm384_sub/lm384_sub.sch622
-rw-r--r--library/SubcircuitLibrary/lm384_sub/lm384_sub.sub32
-rw-r--r--library/SubcircuitLibrary/lm384_sub/lm384_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/sn7445/analysis1
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445-cache.lib106
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.cir53
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.cir.out180
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.pro73
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.sch968
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.sub174
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml1
154 files changed, 17364 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib
new file mode 100644
index 00000000..4c0d3858
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib
@@ -0,0 +1,170 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_3
+#
+DEF adc_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_7
+#
+DEF adc_bridge_7 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_7" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -600 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X OUT1 8 550 50 200 L 50 50 1 1 O
+X OUT2 9 550 -50 200 L 50 50 1 1 O
+X OUT3 10 550 -150 200 L 50 50 1 1 O
+X OUT4 11 550 -250 200 L 50 50 1 1 O
+X OUT5 12 550 -350 200 L 50 50 1 1 O
+X OUT6 13 550 -450 200 L 50 50 1 1 O
+X OUT7 14 550 -550 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir
new file mode 100644
index 00000000..32fe40e6
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir
@@ -0,0 +1,48 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC688_sub\74HC688_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/06/2024 12:19:51 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5 Net-_U2-Pad8_ Net-_U22-Pad1_ d_inverter
+U6 Net-_U2-Pad9_ Net-_U22-Pad2_ d_inverter
+U7 Net-_U2-Pad10_ Net-_U23-Pad1_ d_inverter
+U8 Net-_U2-Pad11_ Net-_U23-Pad2_ d_inverter
+U9 Net-_U2-Pad12_ Net-_U24-Pad1_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter
+U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter
+U21 Net-_U21-Pad1_ Net-_U21-Pad2_ d_inverter
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_xnor
+U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_xnor
+U24 Net-_U24-Pad1_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_xnor
+U25 Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U25-Pad3_ d_xnor
+U26 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U26-Pad3_ d_xnor
+U27 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U27-Pad3_ d_xnor
+U28 Net-_U17-Pad2_ Net-_U18-Pad2_ Net-_U28-Pad3_ d_xnor
+U29 Net-_U19-Pad2_ Net-_U20-Pad2_ Net-_U29-Pad3_ d_xnor
+U30 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U30-Pad3_ d_and
+U31 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U31-Pad3_ d_and
+U32 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U32-Pad3_ d_and
+U33 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U33-Pad3_ d_and
+U34 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U34-Pad3_ d_and
+U35 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U35-Pad3_ d_and
+U37 Net-_U36-Pad3_ Net-_U21-Pad2_ Net-_U37-Pad3_ d_nand
+U36 Net-_U34-Pad3_ Net-_U35-Pad3_ Net-_U36-Pad3_ d_and
+U38 Net-_U37-Pad3_ Net-_U1-Pad18_ dac_bridge_1
+U2 Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U10-Pad1_ Net-_U11-Pad1_ adc_bridge_7
+U3 Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U14-Pad1_ Net-_U15-Pad1_ Net-_U16-Pad1_ Net-_U17-Pad1_ Net-_U18-Pad1_ adc_bridge_7
+U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U19-Pad1_ Net-_U20-Pad1_ Net-_U21-Pad1_ adc_bridge_3
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out
new file mode 100644
index 00000000..b0a3d406
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out
@@ -0,0 +1,160 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc688_sub\74hc688_sub.cir
+
+* u5 net-_u2-pad8_ net-_u22-pad1_ d_inverter
+* u6 net-_u2-pad9_ net-_u22-pad2_ d_inverter
+* u7 net-_u2-pad10_ net-_u23-pad1_ d_inverter
+* u8 net-_u2-pad11_ net-_u23-pad2_ d_inverter
+* u9 net-_u2-pad12_ net-_u24-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_xnor
+* u24 net-_u24-pad1_ net-_u10-pad2_ net-_u24-pad3_ d_xnor
+* u25 net-_u11-pad2_ net-_u12-pad2_ net-_u25-pad3_ d_xnor
+* u26 net-_u13-pad2_ net-_u14-pad2_ net-_u26-pad3_ d_xnor
+* u27 net-_u15-pad2_ net-_u16-pad2_ net-_u27-pad3_ d_xnor
+* u28 net-_u17-pad2_ net-_u18-pad2_ net-_u28-pad3_ d_xnor
+* u29 net-_u19-pad2_ net-_u20-pad2_ net-_u29-pad3_ d_xnor
+* u30 net-_u22-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_and
+* u31 net-_u24-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_and
+* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_and
+* u33 net-_u28-pad3_ net-_u29-pad3_ net-_u33-pad3_ d_and
+* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_and
+* u35 net-_u32-pad3_ net-_u33-pad3_ net-_u35-pad3_ d_and
+* u37 net-_u36-pad3_ net-_u21-pad2_ net-_u37-pad3_ d_nand
+* u36 net-_u34-pad3_ net-_u35-pad3_ net-_u36-pad3_ d_and
+* u38 net-_u37-pad3_ net-_u1-pad18_ dac_bridge_1
+* u2 net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ adc_bridge_7
+* u3 net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ adc_bridge_7
+* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ adc_bridge_3
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port
+a1 net-_u2-pad8_ net-_u22-pad1_ u5
+a2 net-_u2-pad9_ net-_u22-pad2_ u6
+a3 net-_u2-pad10_ net-_u23-pad1_ u7
+a4 net-_u2-pad11_ net-_u23-pad2_ u8
+a5 net-_u2-pad12_ net-_u24-pad1_ u9
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u11-pad1_ net-_u11-pad2_ u11
+a8 net-_u12-pad1_ net-_u12-pad2_ u12
+a9 net-_u13-pad1_ net-_u13-pad2_ u13
+a10 net-_u14-pad1_ net-_u14-pad2_ u14
+a11 net-_u15-pad1_ net-_u15-pad2_ u15
+a12 net-_u16-pad1_ net-_u16-pad2_ u16
+a13 net-_u17-pad1_ net-_u17-pad2_ u17
+a14 net-_u18-pad1_ net-_u18-pad2_ u18
+a15 net-_u19-pad1_ net-_u19-pad2_ u19
+a16 net-_u20-pad1_ net-_u20-pad2_ u20
+a17 net-_u21-pad1_ net-_u21-pad2_ u21
+a18 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a20 [net-_u24-pad1_ net-_u10-pad2_ ] net-_u24-pad3_ u24
+a21 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u25-pad3_ u25
+a22 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u26-pad3_ u26
+a23 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u27-pad3_ u27
+a24 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u28-pad3_ u28
+a25 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u29-pad3_ u29
+a26 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30
+a27 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a28 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32
+a29 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u33-pad3_ u33
+a30 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34
+a31 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u35-pad3_ u35
+a32 [net-_u36-pad3_ net-_u21-pad2_ ] net-_u37-pad3_ u37
+a33 [net-_u34-pad3_ net-_u35-pad3_ ] net-_u36-pad3_ u36
+a34 [net-_u37-pad3_ ] [net-_u1-pad18_ ] u38
+a35 [net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ ] [net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ ] u2
+a36 [net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ ] u3
+a37 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u28 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch
new file mode 100644
index 00000000..c2d69973
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch
@@ -0,0 +1,896 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74HC688-cache
+EELAYER 25 0
+EELAYER END
+$Descr User 23622 19685
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U5
+U 1 1 66694310
+P 9200 5800
+F 0 "U5" H 9200 5700 60 0000 C CNN
+F 1 "d_inverter" H 9200 5950 60 0000 C CNN
+F 2 "" H 9250 5750 60 0000 C CNN
+F 3 "" H 9250 5750 60 0000 C CNN
+ 1 9200 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 66694311
+P 9200 6150
+F 0 "U6" H 9200 6050 60 0000 C CNN
+F 1 "d_inverter" H 9200 6300 60 0000 C CNN
+F 2 "" H 9250 6100 60 0000 C CNN
+F 3 "" H 9250 6100 60 0000 C CNN
+ 1 9200 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 66694312
+P 9200 6550
+F 0 "U7" H 9200 6450 60 0000 C CNN
+F 1 "d_inverter" H 9200 6700 60 0000 C CNN
+F 2 "" H 9250 6500 60 0000 C CNN
+F 3 "" H 9250 6500 60 0000 C CNN
+ 1 9200 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 66694313
+P 9200 6950
+F 0 "U8" H 9200 6850 60 0000 C CNN
+F 1 "d_inverter" H 9200 7100 60 0000 C CNN
+F 2 "" H 9250 6900 60 0000 C CNN
+F 3 "" H 9250 6900 60 0000 C CNN
+ 1 9200 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 66694314
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diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub
new file mode 100644
index 00000000..68303a9d
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub
@@ -0,0 +1,154 @@
+* Subcircuit 74HC688_sub
+.subckt 74HC688_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_
+* c:\fossee\esim\library\subcircuitlibrary\74hc688_sub\74hc688_sub.cir
+* u5 net-_u2-pad8_ net-_u22-pad1_ d_inverter
+* u6 net-_u2-pad9_ net-_u22-pad2_ d_inverter
+* u7 net-_u2-pad10_ net-_u23-pad1_ d_inverter
+* u8 net-_u2-pad11_ net-_u23-pad2_ d_inverter
+* u9 net-_u2-pad12_ net-_u24-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_xnor
+* u24 net-_u24-pad1_ net-_u10-pad2_ net-_u24-pad3_ d_xnor
+* u25 net-_u11-pad2_ net-_u12-pad2_ net-_u25-pad3_ d_xnor
+* u26 net-_u13-pad2_ net-_u14-pad2_ net-_u26-pad3_ d_xnor
+* u27 net-_u15-pad2_ net-_u16-pad2_ net-_u27-pad3_ d_xnor
+* u28 net-_u17-pad2_ net-_u18-pad2_ net-_u28-pad3_ d_xnor
+* u29 net-_u19-pad2_ net-_u20-pad2_ net-_u29-pad3_ d_xnor
+* u30 net-_u22-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_and
+* u31 net-_u24-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_and
+* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_and
+* u33 net-_u28-pad3_ net-_u29-pad3_ net-_u33-pad3_ d_and
+* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_and
+* u35 net-_u32-pad3_ net-_u33-pad3_ net-_u35-pad3_ d_and
+* u37 net-_u36-pad3_ net-_u21-pad2_ net-_u37-pad3_ d_nand
+* u36 net-_u34-pad3_ net-_u35-pad3_ net-_u36-pad3_ d_and
+* u38 net-_u37-pad3_ net-_u1-pad18_ dac_bridge_1
+* u2 net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ adc_bridge_7
+* u3 net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ adc_bridge_7
+* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ adc_bridge_3
+a1 net-_u2-pad8_ net-_u22-pad1_ u5
+a2 net-_u2-pad9_ net-_u22-pad2_ u6
+a3 net-_u2-pad10_ net-_u23-pad1_ u7
+a4 net-_u2-pad11_ net-_u23-pad2_ u8
+a5 net-_u2-pad12_ net-_u24-pad1_ u9
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u11-pad1_ net-_u11-pad2_ u11
+a8 net-_u12-pad1_ net-_u12-pad2_ u12
+a9 net-_u13-pad1_ net-_u13-pad2_ u13
+a10 net-_u14-pad1_ net-_u14-pad2_ u14
+a11 net-_u15-pad1_ net-_u15-pad2_ u15
+a12 net-_u16-pad1_ net-_u16-pad2_ u16
+a13 net-_u17-pad1_ net-_u17-pad2_ u17
+a14 net-_u18-pad1_ net-_u18-pad2_ u18
+a15 net-_u19-pad1_ net-_u19-pad2_ u19
+a16 net-_u20-pad1_ net-_u20-pad2_ u20
+a17 net-_u21-pad1_ net-_u21-pad2_ u21
+a18 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a20 [net-_u24-pad1_ net-_u10-pad2_ ] net-_u24-pad3_ u24
+a21 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u25-pad3_ u25
+a22 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u26-pad3_ u26
+a23 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u27-pad3_ u27
+a24 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u28-pad3_ u28
+a25 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u29-pad3_ u29
+a26 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30
+a27 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a28 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32
+a29 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u33-pad3_ u33
+a30 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34
+a31 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u35-pad3_ u35
+a32 [net-_u36-pad3_ net-_u21-pad2_ ] net-_u37-pad3_ u37
+a33 [net-_u34-pad3_ net-_u35-pad3_ ] net-_u36-pad3_ u36
+a34 [net-_u37-pad3_ ] [net-_u1-pad18_ ] u38
+a35 [net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ ] [net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ ] u2
+a36 [net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ ] u3
+a37 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u28 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC688_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml
new file mode 100644
index 00000000..8781d549
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u5 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field1><field2 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field2><field3 name="Enter Input Load (default=1.0e-12)">1.0e-12</field3></u5><u6 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field4><field5 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field5><field6 name="Enter Input Load (default=1.0e-12)">1.0e-12</field6></u6><u7 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field7><field8 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field8><field9 name="Enter Input Load (default=1.0e-12)">1.0e-12</field9></u7><u8 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field10><field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field11><field12 name="Enter Input Load (default=1.0e-12)">1.0e-12</field12></u8><u9 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field13><field14 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field14><field15 name="Enter Input Load (default=1.0e-12)">1.0e-12</field15></u9><u10 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field16><field17 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field17><field18 name="Enter Input Load (default=1.0e-12)">1.0e-12</field18></u10><u11 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field19><field20 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field20><field21 name="Enter Input Load (default=1.0e-12)">1.0e-12</field21></u11><u12 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field22><field23 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field23><field24 name="Enter Input Load (default=1.0e-12)">1.0e-12</field24></u12><u13 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field25><field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field26><field27 name="Enter Input Load (default=1.0e-12)">1.0e-12</field27></u13><u14 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field28><field29 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field29><field30 name="Enter Input Load (default=1.0e-12)">1.0e-12</field30></u14><u15 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field31><field32 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field32><field33 name="Enter Input Load (default=1.0e-12)">1.0e-12</field33></u15><u16 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field34><field35 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field35><field36 name="Enter Input Load (default=1.0e-12)">1.0e-12</field36></u16><u17 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field37><field38 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field38><field39 name="Enter Input Load (default=1.0e-12)">1.0e-12</field39></u17><u18 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field40><field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field41><field42 name="Enter Input Load (default=1.0e-12)">1.0e-12</field42></u18><u19 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field43><field44 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field44><field45 name="Enter Input Load (default=1.0e-12)">1.0e-12</field45></u19><u20 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field46><field47 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field47><field48 name="Enter Input Load (default=1.0e-12)">1.0e-12</field48></u20><u21 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field49><field50 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field50><field51 name="Enter Input Load (default=1.0e-12)">1.0e-12</field51></u21><u22 name="type">d_xnor<field52 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field52><field53 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field53><field54 name="Enter Input Load (default=1.0e-12)">1.0e-12</field54></u22><u23 name="type">d_xnor<field55 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field55><field56 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field56><field57 name="Enter Input Load (default=1.0e-12)">1.0e-12</field57></u23><u24 name="type">d_xnor<field58 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field58><field59 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field59><field60 name="Enter Input Load (default=1.0e-12)">1.0e-12</field60></u24><u25 name="type">d_xnor<field61 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field61><field62 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field62><field63 name="Enter Input Load (default=1.0e-12)">1.0e-12</field63></u25><u26 name="type">d_xnor<field64 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field64><field65 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field65><field66 name="Enter Input Load (default=1.0e-12)">1.0e-12</field66></u26><u27 name="type">d_xnor<field67 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field67><field68 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field68><field69 name="Enter Input Load (default=1.0e-12)">1.0e-12</field69></u27><u28 name="type">d_xnor<field70 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field70><field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field71><field72 name="Enter Input Load (default=1.0e-12)">1.0e-12</field72></u28><u29 name="type">d_xnor<field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field73><field74 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field74><field75 name="Enter Input Load (default=1.0e-12)">1.0e-12</field75></u29><u30 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field76><field77 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field77><field78 name="Enter Input Load (default=1.0e-12)">1.0e-12</field78></u30><u31 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field79><field80 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field80><field81 name="Enter Input Load (default=1.0e-12)">1.0e-12</field81></u31><u32 name="type">d_and<field82 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field82><field83 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field83><field84 name="Enter Input Load (default=1.0e-12)">1.0e-12</field84></u32><u33 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field85><field86 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field86><field87 name="Enter Input Load (default=1.0e-12)">1.0e-12</field87></u33><u34 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field88><field89 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field89><field90 name="Enter Input Load (default=1.0e-12)">1.0e-12</field90></u34><u35 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field91><field92 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field92><field93 name="Enter Input Load (default=1.0e-12)">1.0e-12</field93></u35><u37 name="type">d_nand<field94 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field94><field95 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field95><field96 name="Enter Input Load (default=1.0e-12)">1.0e-12</field96></u37><u36 name="type">d_and<field97 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field97><field98 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field98><field99 name="Enter Input Load (default=1.0e-12)">1.0e-12</field99></u36><u38 name="type">dac_bridge<field100 name="Enter value for out_low (default=0.0)">0.0</field100><field101 name="Enter value for out_high (default=5.0)">5.0</field101><field102 name="Enter value for out_undef (default=0.5)">0.5</field102><field103 name="Enter value for input load (default=1.0e-12)">1.0e-12</field103><field104 name="Enter the Rise Time (default=1.0e-9)">1.0e-9</field104><field105 name="Enter the Fall Time (default=1.0e-9)">1.0e-9</field105></u38><u2 name="type">adc_bridge<field106 name="Enter value for in_low (default=1.0)">1.0</field106><field107 name="Enter value for in_high (default=2.0)">2.0</field107><field108 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field108><field109 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field109></u2><u3 name="type">adc_bridge<field110 name="Enter value for in_low (default=1.0)">1.0</field110><field111 name="Enter value for in_high (default=2.0)">2.0</field111><field112 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field112><field113 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field113></u3><u4 name="type">adc_bridge<field114 name="Enter value for in_low (default=1.0)">1.0</field114><field115 name="Enter value for in_high (default=2.0)">2.0</field115><field116 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field116><field117 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field117></u4></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC688_sub/analysis b/library/SubcircuitLibrary/74HC688_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/CA3140_sub/CA3140_sub-cache.lib b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub-cache.lib
new file mode 100644
index 00000000..40eaa2d7
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub-cache.lib
@@ -0,0 +1,190 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir
new file mode 100644
index 00000000..a1a0b11b
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir
@@ -0,0 +1,55 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CA3140_sub\CA3140_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 18/06/2024 3:54:31 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_PNP
+Q3 Net-_M1-Pad3_ Net-_Q1-Pad1_ Net-_D1-Pad2_ eSim_PNP
+Q2 Net-_Q1-Pad1_ Net-_M1-Pad3_ Net-_Q2-Pad3_ eSim_NPN
+M1 Net-_D2-Pad1_ Net-_D2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p
+R1 Net-_D2-Pad2_ Net-_Q2-Pad3_ 8K
+D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode
+U2 Net-_U2-PadIN_ Net-_M2-Pad2_ zener
+U4 Net-_U2-PadIN_ Net-_M3-Pad2_ zener
+U3 Net-_U2-PadIN_ Net-_M2-Pad3_ zener
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p
+M3 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p
+R2 Net-_Q4-Pad1_ Net-_M2-Pad1_ 500
+R4 Net-_C1-Pad1_ Net-_M3-Pad1_ 500
+R3 Net-_D2-Pad2_ Net-_Q4-Pad3_ 500
+R5 Net-_D2-Pad2_ Net-_Q7-Pad3_ 500
+Q4 Net-_Q4-Pad1_ Net-_M2-Pad1_ Net-_Q4-Pad3_ eSim_NPN
+Q7 Net-_C1-Pad1_ Net-_M2-Pad1_ Net-_Q7-Pad3_ eSim_NPN
+Q6 Net-_M2-Pad3_ Net-_Q1-Pad1_ Net-_Q5-Pad1_ eSim_PNP
+Q5 Net-_Q5-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_PNP
+Q8 Net-_Q13-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_PNP
+Q9 Net-_C1-Pad2_ Net-_Q1-Pad1_ Net-_Q13-Pad1_ eSim_PNP
+Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN
+Q11 Net-_D1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q12 Net-_Q11-Pad3_ Net-_D2-Pad1_ Net-_Q12-Pad3_ eSim_NPN
+Q14 Net-_M4-Pad2_ Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_NPN
+Q16 Net-_M4-Pad2_ Net-_D4-Pad1_ Net-_D2-Pad2_ eSim_NPN
+R6 Net-_D2-Pad2_ Net-_Q12-Pad3_ 50
+R12 Net-_D2-Pad2_ Net-_D4-Pad2_ 30
+R7 Net-_Q11-Pad3_ Net-_Q15-Pad2_ 1K
+R8 Net-_Q13-Pad2_ Net-_R10-Pad2_ 1K
+R10 Net-_Q13-Pad3_ Net-_R10-Pad2_ 20
+R9 Net-_D3-Pad2_ Net-_R10-Pad2_ 50
+D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode
+D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode
+Q17 Net-_D1-Pad1_ Net-_Q17-Pad2_ Net-_Q17-Pad3_ eSim_NPN
+R13 Net-_Q17-Pad2_ Net-_D1-Pad1_ 5K
+R14 Net-_D2-Pad2_ Net-_R14-Pad2_ 20K
+R11 Net-_M4-Pad3_ Net-_Q17-Pad3_ 12K
+M4 Net-_D4-Pad1_ Net-_M4-Pad2_ Net-_M4-Pad3_ Net-_M4-Pad3_ mosfet_p
+U5 Net-_R14-Pad2_ Net-_Q17-Pad2_ zener
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 12pF
+Q10 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_D2-Pad2_ eSim_NPN
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+Q15 Net-_Q13-Pad3_ Net-_Q15-Pad2_ Net-_M4-Pad2_ eSim_NPN
+U1 Net-_Q7-Pad3_ Net-_M2-Pad2_ Net-_M3-Pad2_ Net-_D2-Pad2_ Net-_Q4-Pad3_ Net-_M4-Pad2_ Net-_D1-Pad1_ Net-_C1-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir.out b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir.out
new file mode 100644
index 00000000..452bb744
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.cir.out
@@ -0,0 +1,72 @@
+* c:\fossee\esim\library\subcircuitlibrary\ca3140_sub\ca3140_sub.cir
+
+.include D.lib
+.include PNP.lib
+.include PMOS-0.5um.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A
+q3 net-_m1-pad3_ net-_q1-pad1_ net-_d1-pad2_ Q2N2907A
+q2 net-_q1-pad1_ net-_m1-pad3_ net-_q2-pad3_ Q2N2222
+m1 net-_d2-pad1_ net-_d2-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1
+r1 net-_d2-pad2_ net-_q2-pad3_ 8k
+d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
+* u2 net-_u2-padin_ net-_m2-pad2_ zener
+* u4 net-_u2-padin_ net-_m3-pad2_ zener
+* u3 net-_u2-padin_ net-_m2-pad3_ zener
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m3-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1
+r2 net-_q4-pad1_ net-_m2-pad1_ 500
+r4 net-_c1-pad1_ net-_m3-pad1_ 500
+r3 net-_d2-pad2_ net-_q4-pad3_ 500
+r5 net-_d2-pad2_ net-_q7-pad3_ 500
+q4 net-_q4-pad1_ net-_m2-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_c1-pad1_ net-_m2-pad1_ net-_q7-pad3_ Q2N2222
+q6 net-_m2-pad3_ net-_q1-pad1_ net-_q5-pad1_ Q2N2907A
+q5 net-_q5-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A
+q8 net-_q13-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A
+q9 net-_c1-pad2_ net-_q1-pad1_ net-_q13-pad1_ Q2N2907A
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222
+q11 net-_d1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
+q12 net-_q11-pad3_ net-_d2-pad1_ net-_q12-pad3_ Q2N2222
+q14 net-_m4-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2222
+q16 net-_m4-pad2_ net-_d4-pad1_ net-_d2-pad2_ Q2N2222
+r6 net-_d2-pad2_ net-_q12-pad3_ 50
+r12 net-_d2-pad2_ net-_d4-pad2_ 30
+r7 net-_q11-pad3_ net-_q15-pad2_ 1k
+r8 net-_q13-pad2_ net-_r10-pad2_ 1k
+r10 net-_q13-pad3_ net-_r10-pad2_ 20
+r9 net-_d3-pad2_ net-_r10-pad2_ 50
+d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148
+d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
+q17 net-_d1-pad1_ net-_q17-pad2_ net-_q17-pad3_ Q2N2222
+r13 net-_q17-pad2_ net-_d1-pad1_ 5k
+r14 net-_d2-pad2_ net-_r14-pad2_ 20k
+r11 net-_m4-pad3_ net-_q17-pad3_ 12k
+m4 net-_d4-pad1_ net-_m4-pad2_ net-_m4-pad3_ net-_m4-pad3_ mos_p W=100u L=100u M=1
+* u5 net-_r14-pad2_ net-_q17-pad2_ zener
+c1 net-_c1-pad1_ net-_c1-pad2_ 12pf
+q10 net-_c1-pad2_ net-_c1-pad1_ net-_d2-pad2_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q15 net-_q13-pad3_ net-_q15-pad2_ net-_m4-pad2_ Q2N2222
+* u1 net-_q7-pad3_ net-_m2-pad2_ net-_m3-pad2_ net-_d2-pad2_ net-_q4-pad3_ net-_m4-pad2_ net-_d1-pad1_ net-_c1-pad2_ port
+a1 net-_u2-padin_ net-_m2-pad2_ u2
+a2 net-_u2-padin_ net-_m3-pad2_ u4
+a3 net-_u2-padin_ net-_m2-pad3_ u3
+a4 net-_r14-pad2_ net-_q17-pad2_ u5
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.pro b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sch b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sch
new file mode 100644
index 00000000..dda0e308
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sch
@@ -0,0 +1,914 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CA3140-cache
+EELAYER 25 0
+EELAYER END
+$Descr User 17000 15748
+encoding utf-8
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+Wire Wire Line
+ 4850 7250 5100 7250
+Connection ~ 4550 6550
+Connection ~ 4950 7250
+Wire Wire Line
+ 5650 5400 5800 5400
+Wire Wire Line
+ 5800 5400 5800 6250
+Connection ~ 5800 6250
+Wire Wire Line
+ 4550 7850 4550 7900
+Wire Wire Line
+ 5400 7900 5400 7850
+Wire Wire Line
+ 4550 7500 4250 7500
+Wire Wire Line
+ 4250 7500 4250 8200
+Connection ~ 4550 7500
+Wire Wire Line
+ 5400 7500 5650 7500
+Wire Wire Line
+ 5650 7500 5650 8200
+Connection ~ 5400 7500
+Wire Wire Line
+ 3700 2400 3700 3150
+Connection ~ 3200 2700
+Wire Wire Line
+ 4750 2900 4750 3100
+Wire Wire Line
+ 4750 3500 4750 5950
+Connection ~ 4750 5950
+Wire Wire Line
+ 4750 2100 4750 2500
+Wire Wire Line
+ 2750 2100 11500 2100
+Wire Wire Line
+ 3200 2100 3200 2150
+Wire Wire Line
+ 2750 2100 2750 2500
+Connection ~ 3200 2100
+Wire Wire Line
+ 2750 3350 3400 3350
+Connection ~ 2750 3350
+Wire Wire Line
+ 5050 2700 6900 2700
+Wire Wire Line
+ 5050 3300 6900 3300
+Wire Wire Line
+ 3700 2400 5300 2400
+Wire Wire Line
+ 5300 2400 5300 2700
+Connection ~ 5300 2700
+Connection ~ 3700 2700
+Wire Wire Line
+ 3200 3350 3200 3050
+Wire Wire Line
+ 3200 3050 5300 3050
+Wire Wire Line
+ 5300 3050 5300 3300
+Connection ~ 5300 3300
+Connection ~ 3200 3350
+Wire Wire Line
+ 7200 2100 7200 2500
+Connection ~ 4750 2100
+Wire Wire Line
+ 7200 2900 7200 3100
+Wire Wire Line
+ 7200 3500 7200 6750
+Wire Wire Line
+ 7200 7900 7200 7150
+Connection ~ 5400 7900
+Wire Wire Line
+ 5400 6950 6900 6950
+Connection ~ 5400 6950
+Wire Wire Line
+ 6700 6700 6550 6700
+Wire Wire Line
+ 6550 6700 6550 6950
+Connection ~ 6550 6950
+Wire Wire Line
+ 7000 6700 7200 6700
+Connection ~ 7200 6700
+Wire Wire Line
+ 7200 6250 6400 6250
+Wire Wire Line
+ 6400 6250 6400 8250
+Connection ~ 7200 6250
+Wire Wire Line
+ 10150 7900 10150 7700
+Connection ~ 7200 7900
+Wire Wire Line
+ 10150 7400 10150 7350
+Wire Wire Line
+ 10150 4700 10150 7050
+Wire Wire Line
+ 10150 6950 10000 6950
+Wire Wire Line
+ 9700 7300 9700 7150
+Wire Wire Line
+ 8800 7300 9700 7300
+Wire Wire Line
+ 8800 7300 8800 7150
+Wire Wire Line
+ 8800 6750 8800 6600
+Wire Wire Line
+ 8800 6600 9700 6600
+Wire Wire Line
+ 9700 6600 9700 6750
+Connection ~ 9000 7300
+Wire Wire Line
+ 8050 6950 8500 6950
+Wire Wire Line
+ 7750 7150 7750 7350
+Wire Wire Line
+ 7750 7900 7750 7650
+Connection ~ 7750 7900
+Wire Wire Line
+ 3700 5000 8250 5000
+Wire Wire Line
+ 8250 5000 8250 6950
+Connection ~ 8250 6950
+Connection ~ 3700 5000
+Wire Wire Line
+ 7750 4500 7750 6750
+Wire Wire Line
+ 7750 2100 7750 4100
+Connection ~ 7200 2100
+Wire Wire Line
+ 8200 3100 8200 3000
+Wire Wire Line
+ 8200 3000 7200 3000
+Connection ~ 7200 3000
+Wire Wire Line
+ 9150 3750 9150 4550
+Wire Wire Line
+ 9150 3850 8200 3850
+Wire Wire Line
+ 8200 3850 8200 3500
+Wire Wire Line
+ 8500 3300 8650 3300
+Wire Wire Line
+ 8950 3300 9150 3300
+Wire Wire Line
+ 9150 2950 9150 3450
+Connection ~ 9150 3300
+Wire Wire Line
+ 9150 2600 9150 2650
+Wire Wire Line
+ 9150 2100 9150 2300
+Connection ~ 7750 2100
+Connection ~ 9150 3850
+Wire Wire Line
+ 8850 4750 8350 4750
+Wire Wire Line
+ 8050 4750 7750 4750
+Connection ~ 7750 4750
+Wire Wire Line
+ 9150 4950 9150 6600
+Connection ~ 9150 6600
+Wire Wire Line
+ 3150 6250 4250 6250
+Wire Wire Line
+ 7450 4300 7200 4300
+Connection ~ 7200 4300
+Wire Wire Line
+ 10900 3550 10900 3750
+Wire Wire Line
+ 10900 7900 10900 4050
+Connection ~ 10150 7900
+Connection ~ 10900 7900
+Connection ~ 10150 6950
+Wire Wire Line
+ 10500 5100 10500 4500
+Wire Wire Line
+ 10500 4500 10450 4500
+Connection ~ 9150 5100
+Connection ~ 10500 5100
+Wire Wire Line
+ 10150 3900 10150 4300
+Wire Wire Line
+ 10150 3600 10150 3150
+Wire Wire Line
+ 10050 4350 10050 4250
+Wire Wire Line
+ 10050 4250 10150 4250
+Connection ~ 10150 4250
+Wire Wire Line
+ 10450 2950 10900 2950
+Wire Wire Line
+ 10900 2600 10900 3050
+Connection ~ 10900 2950
+Wire Wire Line
+ 10900 2100 10900 2300
+Connection ~ 9150 2100
+Connection ~ 10900 2100
+Wire Wire Line
+ 3300 6500 3300 6550
+Wire Wire Line
+ 10150 2750 10150 2100
+Connection ~ 10150 2100
+Connection ~ 3700 5500
+Connection ~ 4550 7900
+Wire Wire Line
+ 3700 7900 11400 7900
+Wire Wire Line
+ 9000 7300 9000 7900
+Connection ~ 9000 7900
+Wire Wire Line
+ 9150 5100 12200 5100
+$Comp
+L PORT U1
+U 1 1 667186FE
+P 5400 8200
+F 0 "U1" H 5450 8300 30 0000 C CNN
+F 1 "PORT" H 5400 8200 30 0000 C CNN
+F 2 "" H 5400 8200 60 0000 C CNN
+F 3 "" H 5400 8200 60 0000 C CNN
+ 1 5400 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 66718826
+P 2900 6250
+F 0 "U1" H 2950 6350 30 0000 C CNN
+F 1 "PORT" H 2900 6250 30 0000 C CNN
+F 2 "" H 2900 6250 60 0000 C CNN
+F 3 "" H 2900 6250 60 0000 C CNN
+ 2 2900 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 667188F1
+P 3050 6550
+F 0 "U1" H 3100 6650 30 0000 C CNN
+F 1 "PORT" H 3050 6550 30 0000 C CNN
+F 2 "" H 3050 6550 60 0000 C CNN
+F 3 "" H 3050 6550 60 0000 C CNN
+ 3 3050 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 667189B4
+P 4000 8200
+F 0 "U1" H 4050 8300 30 0000 C CNN
+F 1 "PORT" H 4000 8200 30 0000 C CNN
+F 2 "" H 4000 8200 60 0000 C CNN
+F 3 "" H 4000 8200 60 0000 C CNN
+ 5 4000 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 66718A6F
+P 11650 7900
+F 0 "U1" H 11700 8000 30 0000 C CNN
+F 1 "PORT" H 11650 7900 30 0000 C CNN
+F 2 "" H 11650 7900 60 0000 C CNN
+F 3 "" H 11650 7900 60 0000 C CNN
+ 4 11650 7900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 66718B12
+P 12450 5100
+F 0 "U1" H 12500 5200 30 0000 C CNN
+F 1 "PORT" H 12450 5100 30 0000 C CNN
+F 2 "" H 12450 5100 60 0000 C CNN
+F 3 "" H 12450 5100 60 0000 C CNN
+ 6 12450 5100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 66718BC1
+P 11750 2100
+F 0 "U1" H 11800 2200 30 0000 C CNN
+F 1 "PORT" H 11750 2100 30 0000 C CNN
+F 2 "" H 11750 2100 60 0000 C CNN
+F 3 "" H 11750 2100 60 0000 C CNN
+ 7 11750 2100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 66718C6A
+P 6150 8250
+F 0 "U1" H 6200 8350 30 0000 C CNN
+F 1 "PORT" H 6150 8250 30 0000 C CNN
+F 2 "" H 6150 8250 60 0000 C CNN
+F 3 "" H 6150 8250 60 0000 C CNN
+ 8 6150 8250
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sub b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sub
new file mode 100644
index 00000000..c35cd85f
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub.sub
@@ -0,0 +1,66 @@
+* Subcircuit CA3140_sub
+.subckt CA3140_sub net-_q7-pad3_ net-_m2-pad2_ net-_m3-pad2_ net-_d2-pad2_ net-_q4-pad3_ net-_m4-pad2_ net-_d1-pad1_ net-_c1-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\ca3140_sub\ca3140_sub.cir
+.include D.lib
+.include PNP.lib
+.include PMOS-0.5um.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A
+q3 net-_m1-pad3_ net-_q1-pad1_ net-_d1-pad2_ Q2N2907A
+q2 net-_q1-pad1_ net-_m1-pad3_ net-_q2-pad3_ Q2N2222
+m1 net-_d2-pad1_ net-_d2-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1
+r1 net-_d2-pad2_ net-_q2-pad3_ 8k
+d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
+* u2 net-_u2-padin_ net-_m2-pad2_ zener
+* u4 net-_u2-padin_ net-_m3-pad2_ zener
+* u3 net-_u2-padin_ net-_m2-pad3_ zener
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m3-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1
+r2 net-_q4-pad1_ net-_m2-pad1_ 500
+r4 net-_c1-pad1_ net-_m3-pad1_ 500
+r3 net-_d2-pad2_ net-_q4-pad3_ 500
+r5 net-_d2-pad2_ net-_q7-pad3_ 500
+q4 net-_q4-pad1_ net-_m2-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_c1-pad1_ net-_m2-pad1_ net-_q7-pad3_ Q2N2222
+q6 net-_m2-pad3_ net-_q1-pad1_ net-_q5-pad1_ Q2N2907A
+q5 net-_q5-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A
+q8 net-_q13-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A
+q9 net-_c1-pad2_ net-_q1-pad1_ net-_q13-pad1_ Q2N2907A
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222
+q11 net-_d1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
+q12 net-_q11-pad3_ net-_d2-pad1_ net-_q12-pad3_ Q2N2222
+q14 net-_m4-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2222
+q16 net-_m4-pad2_ net-_d4-pad1_ net-_d2-pad2_ Q2N2222
+r6 net-_d2-pad2_ net-_q12-pad3_ 50
+r12 net-_d2-pad2_ net-_d4-pad2_ 30
+r7 net-_q11-pad3_ net-_q15-pad2_ 1k
+r8 net-_q13-pad2_ net-_r10-pad2_ 1k
+r10 net-_q13-pad3_ net-_r10-pad2_ 20
+r9 net-_d3-pad2_ net-_r10-pad2_ 50
+d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148
+d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
+q17 net-_d1-pad1_ net-_q17-pad2_ net-_q17-pad3_ Q2N2222
+r13 net-_q17-pad2_ net-_d1-pad1_ 5k
+r14 net-_d2-pad2_ net-_r14-pad2_ 20k
+r11 net-_m4-pad3_ net-_q17-pad3_ 12k
+m4 net-_d4-pad1_ net-_m4-pad2_ net-_m4-pad3_ net-_m4-pad3_ mos_p W=100u L=100u M=1
+* u5 net-_r14-pad2_ net-_q17-pad2_ zener
+c1 net-_c1-pad1_ net-_c1-pad2_ 12pf
+q10 net-_c1-pad2_ net-_c1-pad1_ net-_d2-pad2_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q15 net-_q13-pad3_ net-_q15-pad2_ net-_m4-pad2_ Q2N2222
+a1 net-_u2-padin_ net-_m2-pad2_ u2
+a2 net-_u2-padin_ net-_m3-pad2_ u4
+a3 net-_u2-padin_ net-_m2-pad3_ u3
+a4 net-_r14-pad2_ net-_q17-pad2_ u5
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends CA3140_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/CA3140_sub/CA3140_sub_Previous_Values.xml b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub_Previous_Values.xml
new file mode 100644
index 00000000..030989ed
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/CA3140_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)">5.6</field1><field2 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field2><field3 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field3><field4 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field4><field5 name="Enter Switch for Limiting (default=FALSE)">FALSE</field5></u2><u4 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)">5.6</field6><field7 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field7><field8 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field8><field9 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field9><field10 name="Enter Switch for Limiting (default=FALSE)">FALSE</field10></u4><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)">5.6</field11><field12 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field12><field13 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field13><field14 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field14><field15 name="Enter Switch for Limiting (default=FALSE)">FALSE</field15></u3><u5 name="type">zener<field16 name="Enter Breakdown Voltage (default=5.6)" /><field17 name="Enter Breakdown Current (default=2.0e-2)" /><field18 name="Enter Saturation Current (default=1.0e-12)" /><field19 name="Enter Forward Emission Coefficient (default=1.0)" /><field20 name="Enter Switch for Limiting (default=FALSE)" /></u5></model><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>100u</field><field>1</field></m1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>100u</field><field>1</field></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>100u</field><field>1</field></m3><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>100u</field><field>1</field></m4><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15></devicemodel><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/CA3140_sub/D.lib b/library/SubcircuitLibrary/CA3140_sub/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/CA3140_sub/NPN.lib b/library/SubcircuitLibrary/CA3140_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/CA3140_sub/PMOS-0.5um.lib b/library/SubcircuitLibrary/CA3140_sub/PMOS-0.5um.lib
new file mode 100644
index 00000000..848e8b05
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/PMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25
++ NSUB=1.0E17 ) \ No newline at end of file
diff --git a/library/SubcircuitLibrary/CA3140_sub/PNP.lib b/library/SubcircuitLibrary/CA3140_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/CA3140_sub/analysis b/library/SubcircuitLibrary/CA3140_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3140_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM111_sub/LM111_sub-cache.lib b/library/SubcircuitLibrary/LM111_sub/LM111_sub-cache.lib
new file mode 100644
index 00000000..64da9cd1
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/LM111_sub-cache.lib
@@ -0,0 +1,139 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_NJF
+#
+DEF eSim_NJF J 0 0 Y N 1 F N
+F0 "J" -100 50 50 H V R CNN
+F1 "eSim_NJF" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS jfet_n
+DRAW
+C 50 0 111 0 1 10 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 3 0 1 0 100 -100 100 -50 10 -50 N
+P 3 0 1 0 100 100 100 55 10 55 N
+P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 210 R 50 50 1 1 P
+X S 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM111_sub/LM111_sub.cir b/library/SubcircuitLibrary/LM111_sub/LM111_sub.cir
new file mode 100644
index 00000000..a53ffa11
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/LM111_sub.cir
@@ -0,0 +1,56 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM111_sub\LM111_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/06/2024 10:55:30 AM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q2 Net-_J1-Pad2_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_PNP
+Q1 Net-_J1-Pad2_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP
+U2 Net-_U2-PadIN_ Net-_Q1-Pad3_ zener
+U3 Net-_U2-PadIN_ Net-_Q2-Pad3_ zener
+Q6 Net-_Q11-Pad2_ Net-_Q2-Pad3_ Net-_Q5-Pad3_ eSim_NPN
+Q8 Net-_Q5-Pad3_ Net-_Q12-Pad2_ Net-_Q8-Pad3_ eSim_NPN
+R7 Net-_J1-Pad2_ Net-_Q8-Pad3_ 250
+Q4 Net-_Q1-Pad3_ Net-_Q3-Pad2_ Net-_Q4-Pad3_ eSim_PNP
+Q3 Net-_Q2-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_PNP
+R2 Net-_Q3-Pad3_ Net-_J1-Pad1_ 1.3k
+R4 Net-_Q4-Pad3_ Net-_J1-Pad1_ 1.3k
+R3 Net-_Q4-Pad3_ Net-_R3-Pad2_ 300
+R1 Net-_Q3-Pad3_ Net-_Q9-Pad3_ 300
+Q7 Net-_J1-Pad1_ Net-_J1-Pad1_ Net-_Q7-Pad3_ eSim_NPN
+R6 Net-_Q3-Pad2_ Net-_Q7-Pad3_ 70
+R5 Net-_Q10-Pad2_ Net-_Q3-Pad2_ 1.2k
+Q5 Net-_Q10-Pad2_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN
+Q9 Net-_Q11-Pad1_ Net-_Q3-Pad2_ Net-_Q9-Pad3_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q12 Net-_Q10-Pad3_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+R10 Net-_J1-Pad2_ Net-_Q12-Pad3_ 200
+R11 Net-_Q12-Pad2_ Net-_R11-Pad2_ 60
+Q14 Net-_Q12-Pad2_ Net-_Q14-Pad2_ Net-_J1-Pad2_ eSim_NPN
+R14 Net-_Q14-Pad2_ Net-_R11-Pad2_ 450
+R15 Net-_J1-Pad2_ Net-_Q14-Pad2_ 2k
+Q17 Net-_J1-Pad3_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN
+R13 Net-_R11-Pad2_ Net-_Q16-Pad3_ 400
+Q16 Net-_Q13-Pad3_ Net-_J1-Pad3_ Net-_Q16-Pad3_ eSim_NPN
+R8 Net-_Q11-Pad2_ Net-_Q3-Pad2_ 1.2k
+Q18 Net-_J1-Pad2_ Net-_J1-Pad2_ Net-_Q17-Pad3_ eSim_PNP
+Q15 Net-_Q11-Pad1_ Net-_Q13-Pad3_ Net-_Q15-Pad3_ eSim_PNP
+Q13 Net-_J1-Pad1_ Net-_Q10-Pad1_ Net-_Q13-Pad3_ eSim_NPN
+R9 Net-_Q10-Pad1_ Net-_J1-Pad1_ 750
+R12 Net-_Q11-Pad1_ Net-_J1-Pad1_ 600
+J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n
+R16 Net-_Q22-Pad3_ Net-_Q15-Pad3_ 4k
+Q20 Net-_Q15-Pad3_ Net-_Q15-Pad3_ Net-_Q20-Pad3_ eSim_NPN
+Q21 Net-_J1-Pad2_ Net-_Q21-Pad2_ Net-_Q20-Pad3_ eSim_PNP
+Q22 Net-_J1-Pad1_ Net-_Q15-Pad3_ Net-_Q22-Pad3_ eSim_NPN
+R17 Net-_Q23-Pad2_ Net-_Q22-Pad3_ 130
+R18 Net-_Q19-Pad2_ Net-_Q23-Pad2_ 600
+R19 Net-_Q19-Pad3_ Net-_Q19-Pad2_ 4
+Q19 Net-_Q15-Pad3_ Net-_Q19-Pad2_ Net-_Q19-Pad3_ eSim_NPN
+Q23 Net-_Q21-Pad2_ Net-_Q23-Pad2_ Net-_Q19-Pad2_ eSim_NPN
+U1 Net-_Q19-Pad3_ Net-_Q1-Pad2_ Net-_Q2-Pad2_ Net-_J1-Pad2_ Net-_R3-Pad2_ Net-_Q9-Pad3_ Net-_Q21-Pad2_ Net-_J1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/LM111_sub/LM111_sub.cir.out b/library/SubcircuitLibrary/LM111_sub/LM111_sub.cir.out
new file mode 100644
index 00000000..b83465e6
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/LM111_sub.cir.out
@@ -0,0 +1,66 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm111_sub\lm111_sub.cir
+
+.include NJF.lib
+.include PNP.lib
+.include NPN.lib
+q2 net-_j1-pad2_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A
+q1 net-_j1-pad2_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+* u2 net-_u2-padin_ net-_q1-pad3_ zener
+* u3 net-_u2-padin_ net-_q2-pad3_ zener
+q6 net-_q11-pad2_ net-_q2-pad3_ net-_q5-pad3_ Q2N2222
+q8 net-_q5-pad3_ net-_q12-pad2_ net-_q8-pad3_ Q2N2222
+r7 net-_j1-pad2_ net-_q8-pad3_ 250
+q4 net-_q1-pad3_ net-_q3-pad2_ net-_q4-pad3_ Q2N2907A
+q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2907A
+r2 net-_q3-pad3_ net-_j1-pad1_ 1.3k
+r4 net-_q4-pad3_ net-_j1-pad1_ 1.3k
+r3 net-_q4-pad3_ net-_r3-pad2_ 300
+r1 net-_q3-pad3_ net-_q9-pad3_ 300
+q7 net-_j1-pad1_ net-_j1-pad1_ net-_q7-pad3_ Q2N2222
+r6 net-_q3-pad2_ net-_q7-pad3_ 70
+r5 net-_q10-pad2_ net-_q3-pad2_ 1.2k
+q5 net-_q10-pad2_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+q9 net-_q11-pad1_ net-_q3-pad2_ net-_q9-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q10-pad3_ Q2N2222
+q12 net-_q10-pad3_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r10 net-_j1-pad2_ net-_q12-pad3_ 200
+r11 net-_q12-pad2_ net-_r11-pad2_ 60
+q14 net-_q12-pad2_ net-_q14-pad2_ net-_j1-pad2_ Q2N2222
+r14 net-_q14-pad2_ net-_r11-pad2_ 450
+r15 net-_j1-pad2_ net-_q14-pad2_ 2k
+q17 net-_j1-pad3_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
+r13 net-_r11-pad2_ net-_q16-pad3_ 400
+q16 net-_q13-pad3_ net-_j1-pad3_ net-_q16-pad3_ Q2N2222
+r8 net-_q11-pad2_ net-_q3-pad2_ 1.2k
+q18 net-_j1-pad2_ net-_j1-pad2_ net-_q17-pad3_ Q2N2907A
+q15 net-_q11-pad1_ net-_q13-pad3_ net-_q15-pad3_ Q2N2907A
+q13 net-_j1-pad1_ net-_q10-pad1_ net-_q13-pad3_ Q2N2222
+r9 net-_q10-pad1_ net-_j1-pad1_ 750
+r12 net-_q11-pad1_ net-_j1-pad1_ 600
+j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819
+r16 net-_q22-pad3_ net-_q15-pad3_ 4k
+q20 net-_q15-pad3_ net-_q15-pad3_ net-_q20-pad3_ Q2N2222
+q21 net-_j1-pad2_ net-_q21-pad2_ net-_q20-pad3_ Q2N2907A
+q22 net-_j1-pad1_ net-_q15-pad3_ net-_q22-pad3_ Q2N2222
+r17 net-_q23-pad2_ net-_q22-pad3_ 130
+r18 net-_q19-pad2_ net-_q23-pad2_ 600
+r19 net-_q19-pad3_ net-_q19-pad2_ 4
+q19 net-_q15-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222
+q23 net-_q21-pad2_ net-_q23-pad2_ net-_q19-pad2_ Q2N2222
+* u1 net-_q19-pad3_ net-_q1-pad2_ net-_q2-pad2_ net-_j1-pad2_ net-_r3-pad2_ net-_q9-pad3_ net-_q21-pad2_ net-_j1-pad1_ port
+a1 net-_u2-padin_ net-_q1-pad3_ u2
+a2 net-_u2-padin_ net-_q2-pad3_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM111_sub/LM111_sub.pro b/library/SubcircuitLibrary/LM111_sub/LM111_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/LM111_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM111_sub/LM111_sub.sch b/library/SubcircuitLibrary/LM111_sub/LM111_sub.sch
new file mode 100644
index 00000000..34bf08a8
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/LM111_sub.sch
@@ -0,0 +1,898 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:LM111_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_PNP Q2
+U 1 1 665D8677
+P 1600 4500
+F 0 "Q2" H 1500 4550 50 0000 R CNN
+F 1 "eSim_PNP" H 1550 4650 50 0000 R CNN
+F 2 "" H 1800 4600 29 0000 C CNN
+F 3 "" H 1600 4500 60 0000 C CNN
+ 1 1600 4500
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q1
+U 1 1 665D8678
+P 1600 3250
+F 0 "Q1" H 1500 3300 50 0000 R CNN
+F 1 "eSim_PNP" H 1550 3400 50 0000 R CNN
+F 2 "" H 1800 3350 29 0000 C CNN
+F 3 "" H 1600 3250 60 0000 C CNN
+ 1 1600 3250
+ 1 0 0 1
+$EndComp
+$Comp
+L zener U2
+U 1 1 665D8679
+P 2400 3350
+F 0 "U2" H 2350 3250 60 0000 C CNN
+F 1 "zener" H 2400 3450 60 0000 C CNN
+F 2 "" H 2450 3350 60 0000 C CNN
+F 3 "" H 2450 3350 60 0000 C CNN
+ 1 2400 3350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L zener U3
+U 1 1 665D867A
+P 2400 3900
+F 0 "U3" H 2350 3800 60 0000 C CNN
+F 1 "zener" H 2400 4000 60 0000 C CNN
+F 2 "" H 2450 3900 60 0000 C CNN
+F 3 "" H 2450 3900 60 0000 C CNN
+ 1 2400 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 665D867B
+P 3350 4250
+F 0 "Q6" H 3250 4300 50 0000 R CNN
+F 1 "eSim_NPN" H 3300 4400 50 0000 R CNN
+F 2 "" H 3550 4350 29 0000 C CNN
+F 3 "" H 3350 4250 60 0000 C CNN
+ 1 3350 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 665D867C
+P 3900 4750
+F 0 "Q8" H 3800 4800 50 0000 R CNN
+F 1 "eSim_NPN" H 3850 4900 50 0000 R CNN
+F 2 "" H 4100 4850 29 0000 C CNN
+F 3 "" H 3900 4750 60 0000 C CNN
+ 1 3900 4750
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R7
+U 1 1 665D867D
+P 3850 5750
+F 0 "R7" H 3900 5880 50 0000 C CNN
+F 1 "250" H 3900 5700 50 0000 C CNN
+F 2 "" H 3900 5730 30 0000 C CNN
+F 3 "" V 3900 5800 30 0000 C CNN
+ 1 3850 5750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_PNP Q4
+U 1 1 665D867E
+P 2850 2700
+F 0 "Q4" H 2750 2750 50 0000 R CNN
+F 1 "eSim_PNP" H 2800 2850 50 0000 R CNN
+F 2 "" H 3050 2800 29 0000 C CNN
+F 3 "" H 2850 2700 60 0000 C CNN
+ 1 2850 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q3
+U 1 1 665D867F
+P 2100 2700
+F 0 "Q3" H 2000 2750 50 0000 R CNN
+F 1 "eSim_PNP" H 2050 2850 50 0000 R CNN
+F 2 "" H 2300 2800 29 0000 C CNN
+F 3 "" H 2100 2700 60 0000 C CNN
+ 1 2100 2700
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 665D8680
+P 2050 2200
+F 0 "R2" H 2100 2330 50 0000 C CNN
+F 1 "1.3k" H 2100 2150 50 0000 C CNN
+F 2 "" H 2100 2180 30 0000 C CNN
+F 3 "" V 2100 2250 30 0000 C CNN
+ 1 2050 2200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 665D8681
+P 3000 2150
+F 0 "R4" H 3050 2280 50 0000 C CNN
+F 1 "1.3k" H 3050 2100 50 0000 C CNN
+F 2 "" H 3050 2130 30 0000 C CNN
+F 3 "" V 3050 2200 30 0000 C CNN
+ 1 3000 2150
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R3
+U 1 1 665D8682
+P 2500 1100
+F 0 "R3" H 2550 1230 50 0000 C CNN
+F 1 "300" H 2550 1050 50 0000 C CNN
+F 2 "" H 2550 1080 30 0000 C CNN
+F 3 "" V 2550 1150 30 0000 C CNN
+ 1 2500 1100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 665D8683
+P 1650 1100
+F 0 "R1" H 1700 1230 50 0000 C CNN
+F 1 "300" H 1700 1050 50 0000 C CNN
+F 2 "" H 1700 1080 30 0000 C CNN
+F 3 "" V 1700 1150 30 0000 C CNN
+ 1 1650 1100
+ 0 -1 -1 0
+$EndComp
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+U 3 1 665D8DE0
+P 1150 4500
+F 0 "U1" H 1200 4600 30 0000 C CNN
+F 1 "PORT" H 1150 4500 30 0000 C CNN
+F 2 "" H 1150 4500 60 0000 C CNN
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+ 3 1150 4500
+ 1 0 0 -1
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+ 5 2700 700
+ -1 0 0 -1
+$EndComp
+$Comp
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+ 6 1350 700
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+ 7 10500 3900
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+F 3 "" H 10600 6050 60 0000 C CNN
+ 1 10600 6050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
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+F 3 "" H 1150 3250 60 0000 C CNN
+ 2 1150 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+Connection ~ 5800 5050
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LM111_sub/LM111_sub.sub b/library/SubcircuitLibrary/LM111_sub/LM111_sub.sub
new file mode 100644
index 00000000..7adcf0e6
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/LM111_sub.sub
@@ -0,0 +1,60 @@
+* Subcircuit LM111_sub
+.subckt LM111_sub net-_q19-pad3_ net-_q1-pad2_ net-_q2-pad2_ net-_j1-pad2_ net-_r3-pad2_ net-_q9-pad3_ net-_q21-pad2_ net-_j1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm111_sub\lm111_sub.cir
+.include NJF.lib
+.include PNP.lib
+.include NPN.lib
+q2 net-_j1-pad2_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A
+q1 net-_j1-pad2_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+* u2 net-_u2-padin_ net-_q1-pad3_ zener
+* u3 net-_u2-padin_ net-_q2-pad3_ zener
+q6 net-_q11-pad2_ net-_q2-pad3_ net-_q5-pad3_ Q2N2222
+q8 net-_q5-pad3_ net-_q12-pad2_ net-_q8-pad3_ Q2N2222
+r7 net-_j1-pad2_ net-_q8-pad3_ 250
+q4 net-_q1-pad3_ net-_q3-pad2_ net-_q4-pad3_ Q2N2907A
+q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2907A
+r2 net-_q3-pad3_ net-_j1-pad1_ 1.3k
+r4 net-_q4-pad3_ net-_j1-pad1_ 1.3k
+r3 net-_q4-pad3_ net-_r3-pad2_ 300
+r1 net-_q3-pad3_ net-_q9-pad3_ 300
+q7 net-_j1-pad1_ net-_j1-pad1_ net-_q7-pad3_ Q2N2222
+r6 net-_q3-pad2_ net-_q7-pad3_ 70
+r5 net-_q10-pad2_ net-_q3-pad2_ 1.2k
+q5 net-_q10-pad2_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+q9 net-_q11-pad1_ net-_q3-pad2_ net-_q9-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q10-pad3_ Q2N2222
+q12 net-_q10-pad3_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r10 net-_j1-pad2_ net-_q12-pad3_ 200
+r11 net-_q12-pad2_ net-_r11-pad2_ 60
+q14 net-_q12-pad2_ net-_q14-pad2_ net-_j1-pad2_ Q2N2222
+r14 net-_q14-pad2_ net-_r11-pad2_ 450
+r15 net-_j1-pad2_ net-_q14-pad2_ 2k
+q17 net-_j1-pad3_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
+r13 net-_r11-pad2_ net-_q16-pad3_ 400
+q16 net-_q13-pad3_ net-_j1-pad3_ net-_q16-pad3_ Q2N2222
+r8 net-_q11-pad2_ net-_q3-pad2_ 1.2k
+q18 net-_j1-pad2_ net-_j1-pad2_ net-_q17-pad3_ Q2N2907A
+q15 net-_q11-pad1_ net-_q13-pad3_ net-_q15-pad3_ Q2N2907A
+q13 net-_j1-pad1_ net-_q10-pad1_ net-_q13-pad3_ Q2N2222
+r9 net-_q10-pad1_ net-_j1-pad1_ 750
+r12 net-_q11-pad1_ net-_j1-pad1_ 600
+j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819
+r16 net-_q22-pad3_ net-_q15-pad3_ 4k
+q20 net-_q15-pad3_ net-_q15-pad3_ net-_q20-pad3_ Q2N2222
+q21 net-_j1-pad2_ net-_q21-pad2_ net-_q20-pad3_ Q2N2907A
+q22 net-_j1-pad1_ net-_q15-pad3_ net-_q22-pad3_ Q2N2222
+r17 net-_q23-pad2_ net-_q22-pad3_ 130
+r18 net-_q19-pad2_ net-_q23-pad2_ 600
+r19 net-_q19-pad3_ net-_q19-pad2_ 4
+q19 net-_q15-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222
+q23 net-_q21-pad2_ net-_q23-pad2_ net-_q19-pad2_ Q2N2222
+a1 net-_u2-padin_ net-_q1-pad3_ u2
+a2 net-_u2-padin_ net-_q2-pad3_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends LM111_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM111_sub/LM111_sub_Previous_Values.xml b/library/SubcircuitLibrary/LM111_sub/LM111_sub_Previous_Values.xml
new file mode 100644
index 00000000..c04ba2c9
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/LM111_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)">5.6</field1><field2 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field2><field3 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field3><field4 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field4><field5 name="Enter Switch for Limiting (default=FALSE)">FALSE</field5></u2><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)">5.6</field6><field7 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field7><field8 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field8><field9 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field9><field10 name="Enter Switch for Limiting (default=FALSE)">FALSE</field10></u3></model><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><j1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM111_sub/NJF.lib b/library/SubcircuitLibrary/LM111_sub/NJF.lib
new file mode 100644
index 00000000..dbb2cbae
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/NJF.lib
@@ -0,0 +1,4 @@
+.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++ Af=1)
diff --git a/library/SubcircuitLibrary/LM111_sub/NPN.lib b/library/SubcircuitLibrary/LM111_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/LM111_sub/PNP.lib b/library/SubcircuitLibrary/LM111_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/LM111_sub/analysis b/library/SubcircuitLibrary/LM111_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/LM111_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM323A_sub/LM323A_sub-cache.lib b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub-cache.lib
new file mode 100644
index 00000000..c28cbe9d
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub-cache.lib
@@ -0,0 +1,158 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NJF
+#
+DEF eSim_NJF J 0 0 Y N 1 F N
+F0 "J" -100 50 50 H V R CNN
+F1 "eSim_NJF" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS jfet_n
+DRAW
+C 50 0 111 0 1 10 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 3 0 1 0 100 -100 100 -50 10 -50 N
+P 3 0 1 0 100 100 100 55 10 55 N
+P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 210 R 50 50 1 1 P
+X S 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir
new file mode 100644
index 00000000..4921f32b
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir
@@ -0,0 +1,66 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM323A_sub\LM323A_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 20/06/2024 4:29:20 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_C2-Pad2_ Net-_J1-Pad3_ zener
+U2 Net-_C2-Pad2_ Net-_Q1-Pad3_ zener
+J1 Net-_J1-Pad1_ Net-_C2-Pad2_ Net-_J1-Pad3_ jfet_n
+Q4 Net-_C2-Pad1_ Net-_Q4-Pad2_ Net-_C2-Pad2_ eSim_NPN
+R5 Net-_C2-Pad2_ Net-_Q4-Pad2_ 6k
+R4 Net-_Q4-Pad2_ Net-_Q5-Pad1_ 2k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_C2-Pad2_ eSim_NPN
+Q9 Net-_Q13-Pad2_ Net-_Q13-Pad2_ Net-_Q10-Pad1_ eSim_NPN
+R9 Net-_Q13-Pad2_ Net-_R10-Pad1_ 3.9k
+R8 Net-_R10-Pad1_ Net-_Q5-Pad2_ 2.6k
+Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP
+R7 Net-_Q5-Pad2_ Net-_Q5-Pad3_ 520
+Q8 Net-_Q11-Pad3_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN
+Q1 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN
+R10 Net-_R10-Pad1_ Net-_Q12-Pad2_ 6k
+R11 Net-_C2-Pad2_ Net-_Q13-Pad3_ 2.8k
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+Q14 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+Q13 Net-_Q12-Pad3_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 40pF
+Q15 Net-_C2-Pad2_ Net-_C1-Pad1_ Net-_Q15-Pad3_ eSim_PNP
+Q16 Net-_C2-Pad2_ Net-_Q15-Pad3_ Net-_Q16-Pad3_ eSim_PNP
+R13 Net-_C1-Pad1_ Net-_Q15-Pad3_ 5.6k
+R12 Net-_Q15-Pad3_ Net-_Q16-Pad3_ 3k
+R14 Net-_Q16-Pad3_ Net-_C2-Pad1_ 1k
+Q2 Net-_Q2-Pad1_ Net-_Q11-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+R3 Net-_Q1-Pad3_ Net-_Q2-Pad1_ 10k
+R2 Net-_Q2-Pad1_ Net-_Q11-Pad2_ 300
+Q7 Net-_Q1-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10pF
+Q6 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q6-Pad3_ eSim_PNP
+Q3 Net-_Q11-Pad2_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_PNP
+R1 Net-_Q3-Pad3_ Net-_J1-Pad1_ 1k
+R6 Net-_Q6-Pad3_ Net-_J1-Pad1_ 1k
+Q18 Net-_C2-Pad1_ Net-_Q18-Pad2_ Net-_Q18-Pad3_ eSim_NPN
+Q17 Net-_C2-Pad1_ Net-_Q11-Pad1_ Net-_J1-Pad1_ eSim_PNP
+R18 Net-_Q18-Pad2_ Net-_Q22-Pad3_ 300
+R15 Net-_C1-Pad2_ Net-_R15-Pad2_ 4k
+R16 Net-_R16-Pad1_ Net-_Q18-Pad3_ 50
+R22 Net-_R16-Pad1_ Net-_Q12-Pad1_ 2k
+U3 Net-_R17-Pad2_ Net-_J1-Pad1_ zener
+R17 Net-_Q18-Pad2_ Net-_R17-Pad2_ 16k
+R19 Net-_Q11-Pad1_ Net-_Q19-Pad2_ 210
+Q19 Net-_Q11-Pad1_ Net-_Q19-Pad2_ Net-_J1-Pad1_ eSim_PNP
+Q20 Net-_Q11-Pad1_ Net-_C2-Pad1_ Net-_Q20-Pad3_ eSim_NPN
+R20 Net-_C2-Pad1_ Net-_Q21-Pad2_ 100
+R21 Net-_Q20-Pad3_ Net-_Q12-Pad1_ 200
+Q21 Net-_J1-Pad1_ Net-_Q21-Pad2_ Net-_Q12-Pad1_ eSim_NPN
+R24 Net-_R16-Pad1_ Net-_Q23-Pad3_ 0.12
+Q23 Net-_J1-Pad1_ Net-_Q12-Pad1_ Net-_Q23-Pad3_ eSim_NPN
+R25 Net-_R15-Pad2_ Net-_R16-Pad1_ 900
+R26 Net-_C2-Pad2_ Net-_R15-Pad2_ 1.7k
+Q22 Net-_J1-Pad1_ Net-_Q12-Pad1_ Net-_Q22-Pad3_ eSim_NPN
+R23 Net-_R16-Pad1_ Net-_Q22-Pad3_ 13
+U4 Net-_J1-Pad1_ Net-_C2-Pad2_ Net-_R16-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir.out b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir.out
new file mode 100644
index 00000000..ca309436
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.cir.out
@@ -0,0 +1,79 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm323a_sub\lm323a_sub.cir
+
+.include NJF.lib
+.include NPN.lib
+.include PNP.lib
+* u1 net-_c2-pad2_ net-_j1-pad3_ zener
+* u2 net-_c2-pad2_ net-_q1-pad3_ zener
+j1 net-_j1-pad1_ net-_c2-pad2_ net-_j1-pad3_ J2N3819
+q4 net-_c2-pad1_ net-_q4-pad2_ net-_c2-pad2_ Q2N2222
+r5 net-_c2-pad2_ net-_q4-pad2_ 6k
+r4 net-_q4-pad2_ net-_q5-pad1_ 2k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_c2-pad2_ Q2N2222
+q9 net-_q13-pad2_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222
+r9 net-_q13-pad2_ net-_r10-pad1_ 3.9k
+r8 net-_r10-pad1_ net-_q5-pad2_ 2.6k
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
+r7 net-_q5-pad2_ net-_q5-pad3_ 520
+q8 net-_q11-pad3_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222
+r10 net-_r10-pad1_ net-_q12-pad2_ 6k
+r11 net-_c2-pad2_ net-_q13-pad3_ 2.8k
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+q14 net-_c1-pad1_ net-_c1-pad2_ net-_q12-pad3_ Q2N2222
+q13 net-_q12-pad3_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 40pf
+q15 net-_c2-pad2_ net-_c1-pad1_ net-_q15-pad3_ Q2N2907A
+q16 net-_c2-pad2_ net-_q15-pad3_ net-_q16-pad3_ Q2N2907A
+r13 net-_c1-pad1_ net-_q15-pad3_ 5.6k
+r12 net-_q15-pad3_ net-_q16-pad3_ 3k
+r14 net-_q16-pad3_ net-_c2-pad1_ 1k
+q2 net-_q2-pad1_ net-_q11-pad2_ net-_q1-pad3_ Q2N2222
+r3 net-_q1-pad3_ net-_q2-pad1_ 10k
+r2 net-_q2-pad1_ net-_q11-pad2_ 300
+q7 net-_q1-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+q6 net-_q1-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A
+q3 net-_q11-pad2_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A
+r1 net-_q3-pad3_ net-_j1-pad1_ 1k
+r6 net-_q6-pad3_ net-_j1-pad1_ 1k
+q18 net-_c2-pad1_ net-_q18-pad2_ net-_q18-pad3_ Q2N2222
+q17 net-_c2-pad1_ net-_q11-pad1_ net-_j1-pad1_ Q2N2907A
+r18 net-_q18-pad2_ net-_q22-pad3_ 300
+r15 net-_c1-pad2_ net-_r15-pad2_ 4k
+r16 net-_r16-pad1_ net-_q18-pad3_ 50
+r22 net-_r16-pad1_ net-_q12-pad1_ 2k
+* u3 net-_r17-pad2_ net-_j1-pad1_ zener
+r17 net-_q18-pad2_ net-_r17-pad2_ 16k
+r19 net-_q11-pad1_ net-_q19-pad2_ 210
+q19 net-_q11-pad1_ net-_q19-pad2_ net-_j1-pad1_ Q2N2907A
+q20 net-_q11-pad1_ net-_c2-pad1_ net-_q20-pad3_ Q2N2222
+r20 net-_c2-pad1_ net-_q21-pad2_ 100
+r21 net-_q20-pad3_ net-_q12-pad1_ 200
+q21 net-_j1-pad1_ net-_q21-pad2_ net-_q12-pad1_ Q2N2222
+r24 net-_r16-pad1_ net-_q23-pad3_ 0.12
+q23 net-_j1-pad1_ net-_q12-pad1_ net-_q23-pad3_ Q2N2222
+r25 net-_r15-pad2_ net-_r16-pad1_ 900
+r26 net-_c2-pad2_ net-_r15-pad2_ 1.7k
+q22 net-_j1-pad1_ net-_q12-pad1_ net-_q22-pad3_ Q2N2222
+r23 net-_r16-pad1_ net-_q22-pad3_ 13
+* u4 net-_j1-pad1_ net-_c2-pad2_ net-_r16-pad1_ port
+a1 net-_c2-pad2_ net-_j1-pad3_ u1
+a2 net-_c2-pad2_ net-_q1-pad3_ u2
+a3 net-_r17-pad2_ net-_j1-pad1_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.pro b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sch b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sch
new file mode 100644
index 00000000..481b83a2
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sch
@@ -0,0 +1,986 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:LM323A-cache
+EELAYER 25 0
+EELAYER END
+$Descr User 17000 15748
+encoding utf-8
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+F 0 "R20" H 11950 6980 50 0000 C CNN
+F 1 "100" H 11950 6800 50 0000 C CNN
+F 2 "" H 11950 6830 30 0000 C CNN
+F 3 "" V 11950 6900 30 0000 C CNN
+ 1 11900 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R21
+U 1 1 66740684
+P 11950 7350
+F 0 "R21" H 12000 7480 50 0000 C CNN
+F 1 "200" H 12000 7300 50 0000 C CNN
+F 2 "" H 12000 7330 30 0000 C CNN
+F 3 "" V 12000 7400 30 0000 C CNN
+ 1 11950 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q21
+U 1 1 66740685
+P 12700 6800
+F 0 "Q21" H 12600 6850 50 0000 R CNN
+F 1 "eSim_NPN" H 12650 6950 50 0000 R CNN
+F 2 "" H 12900 6900 29 0000 C CNN
+F 3 "" H 12700 6800 60 0000 C CNN
+ 1 12700 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R24
+U 1 1 66740686
+P 13650 8250
+F 0 "R24" H 13700 8380 50 0000 C CNN
+F 1 "0.12" H 13700 8200 50 0000 C CNN
+F 2 "" H 13700 8230 30 0000 C CNN
+F 3 "" V 13700 8300 30 0000 C CNN
+ 1 13650 8250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q23
+U 1 1 66740687
+P 13500 7300
+F 0 "Q23" H 13400 7350 50 0000 R CNN
+F 1 "eSim_NPN" H 13450 7450 50 0000 R CNN
+F 2 "" H 13700 7400 29 0000 C CNN
+F 3 "" H 13500 7300 60 0000 C CNN
+ 1 13500 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R25
+U 1 1 66740688
+P 13650 9550
+F 0 "R25" H 13700 9680 50 0000 C CNN
+F 1 "900" H 13700 9500 50 0000 C CNN
+F 2 "" H 13700 9530 30 0000 C CNN
+F 3 "" V 13700 9600 30 0000 C CNN
+ 1 13650 9550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R26
+U 1 1 66740689
+P 13650 10950
+F 0 "R26" H 13700 11080 50 0000 C CNN
+F 1 "1.7k" H 13700 10900 50 0000 C CNN
+F 2 "" H 13700 10930 30 0000 C CNN
+F 3 "" V 13700 11000 30 0000 C CNN
+ 1 13650 10950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q22
+U 1 1 6674068A
+P 13050 7300
+F 0 "Q22" H 12950 7350 50 0000 R CNN
+F 1 "eSim_NPN" H 13000 7450 50 0000 R CNN
+F 2 "" H 13250 7400 29 0000 C CNN
+F 3 "" H 13050 7300 60 0000 C CNN
+ 1 13050 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R23
+U 1 1 6674068B
+P 13200 8150
+F 0 "R23" H 13250 8280 50 0000 C CNN
+F 1 "13" H 13250 8100 50 0000 C CNN
+F 2 "" H 13250 8130 30 0000 C CNN
+F 3 "" V 13250 8200 30 0000 C CNN
+ 1 13200 8150
+ 0 -1 -1 0
+$EndComp
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+ 14150 11700 14150 10000
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+ 1500 11700 14150 11700
+$Comp
+L PORT U4
+U 2 1 66746A2C
+P 14400 10000
+F 0 "U4" H 14450 10100 30 0000 C CNN
+F 1 "PORT" H 14400 10000 30 0000 C CNN
+F 2 "" H 14400 10000 60 0000 C CNN
+F 3 "" H 14400 10000 60 0000 C CNN
+ 2 14400 10000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U4
+U 3 1 66746AFD
+P 15350 9300
+F 0 "U4" H 15400 9400 30 0000 C CNN
+F 1 "PORT" H 15350 9300 30 0000 C CNN
+F 2 "" H 15350 9300 60 0000 C CNN
+F 3 "" H 15350 9300 60 0000 C CNN
+ 3 15350 9300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U4
+U 1 1 66746BAE
+P 15050 5500
+F 0 "U4" H 15100 5600 30 0000 C CNN
+F 1 "PORT" H 15050 5500 30 0000 C CNN
+F 2 "" H 15050 5500 60 0000 C CNN
+F 3 "" H 15050 5500 60 0000 C CNN
+ 1 15050 5500
+ 0 -1 -1 0
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sub b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sub
new file mode 100644
index 00000000..13b022b9
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub.sub
@@ -0,0 +1,73 @@
+* Subcircuit LM323A_sub
+.subckt LM323A_sub net-_j1-pad1_ net-_c2-pad2_ net-_r16-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm323a_sub\lm323a_sub.cir
+.include NJF.lib
+.include NPN.lib
+.include PNP.lib
+* u1 net-_c2-pad2_ net-_j1-pad3_ zener
+* u2 net-_c2-pad2_ net-_q1-pad3_ zener
+j1 net-_j1-pad1_ net-_c2-pad2_ net-_j1-pad3_ J2N3819
+q4 net-_c2-pad1_ net-_q4-pad2_ net-_c2-pad2_ Q2N2222
+r5 net-_c2-pad2_ net-_q4-pad2_ 6k
+r4 net-_q4-pad2_ net-_q5-pad1_ 2k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_c2-pad2_ Q2N2222
+q9 net-_q13-pad2_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222
+r9 net-_q13-pad2_ net-_r10-pad1_ 3.9k
+r8 net-_r10-pad1_ net-_q5-pad2_ 2.6k
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
+r7 net-_q5-pad2_ net-_q5-pad3_ 520
+q8 net-_q11-pad3_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222
+r10 net-_r10-pad1_ net-_q12-pad2_ 6k
+r11 net-_c2-pad2_ net-_q13-pad3_ 2.8k
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+q14 net-_c1-pad1_ net-_c1-pad2_ net-_q12-pad3_ Q2N2222
+q13 net-_q12-pad3_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 40pf
+q15 net-_c2-pad2_ net-_c1-pad1_ net-_q15-pad3_ Q2N2907A
+q16 net-_c2-pad2_ net-_q15-pad3_ net-_q16-pad3_ Q2N2907A
+r13 net-_c1-pad1_ net-_q15-pad3_ 5.6k
+r12 net-_q15-pad3_ net-_q16-pad3_ 3k
+r14 net-_q16-pad3_ net-_c2-pad1_ 1k
+q2 net-_q2-pad1_ net-_q11-pad2_ net-_q1-pad3_ Q2N2222
+r3 net-_q1-pad3_ net-_q2-pad1_ 10k
+r2 net-_q2-pad1_ net-_q11-pad2_ 300
+q7 net-_q1-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+q6 net-_q1-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A
+q3 net-_q11-pad2_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A
+r1 net-_q3-pad3_ net-_j1-pad1_ 1k
+r6 net-_q6-pad3_ net-_j1-pad1_ 1k
+q18 net-_c2-pad1_ net-_q18-pad2_ net-_q18-pad3_ Q2N2222
+q17 net-_c2-pad1_ net-_q11-pad1_ net-_j1-pad1_ Q2N2907A
+r18 net-_q18-pad2_ net-_q22-pad3_ 300
+r15 net-_c1-pad2_ net-_r15-pad2_ 4k
+r16 net-_r16-pad1_ net-_q18-pad3_ 50
+r22 net-_r16-pad1_ net-_q12-pad1_ 2k
+* u3 net-_r17-pad2_ net-_j1-pad1_ zener
+r17 net-_q18-pad2_ net-_r17-pad2_ 16k
+r19 net-_q11-pad1_ net-_q19-pad2_ 210
+q19 net-_q11-pad1_ net-_q19-pad2_ net-_j1-pad1_ Q2N2907A
+q20 net-_q11-pad1_ net-_c2-pad1_ net-_q20-pad3_ Q2N2222
+r20 net-_c2-pad1_ net-_q21-pad2_ 100
+r21 net-_q20-pad3_ net-_q12-pad1_ 200
+q21 net-_j1-pad1_ net-_q21-pad2_ net-_q12-pad1_ Q2N2222
+r24 net-_r16-pad1_ net-_q23-pad3_ 0.12
+q23 net-_j1-pad1_ net-_q12-pad1_ net-_q23-pad3_ Q2N2222
+r25 net-_r15-pad2_ net-_r16-pad1_ 900
+r26 net-_c2-pad2_ net-_r15-pad2_ 1.7k
+q22 net-_j1-pad1_ net-_q12-pad1_ net-_q22-pad3_ Q2N2222
+r23 net-_r16-pad1_ net-_q22-pad3_ 13
+a1 net-_c2-pad2_ net-_j1-pad3_ u1
+a2 net-_c2-pad2_ net-_q1-pad3_ u2
+a3 net-_r17-pad2_ net-_j1-pad1_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends LM323A_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM323A_sub/LM323A_sub_Previous_Values.xml b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub_Previous_Values.xml
new file mode 100644
index 00000000..338a8c7a
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/LM323A_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)">5.6</field1><field2 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field2><field3 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field3><field4 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field4><field5 name="Enter Switch for Limiting (default=FALSE)">FALSE</field5></u1><u2 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)">5.6</field6><field7 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field7><field8 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field8><field9 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field9><field10 name="Enter Switch for Limiting (default=FALSE)">FALSE</field10></u2><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)">5.6</field11><field12 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field12><field13 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field13><field14 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field14><field15 name="Enter Switch for Limiting (default=FALSE)">FALSE</field15></u3></model><devicemodel><j1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q16><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM323A_sub/NJF.lib b/library/SubcircuitLibrary/LM323A_sub/NJF.lib
new file mode 100644
index 00000000..dbb2cbae
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/NJF.lib
@@ -0,0 +1,4 @@
+.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++ Af=1)
diff --git a/library/SubcircuitLibrary/LM323A_sub/NPN.lib b/library/SubcircuitLibrary/LM323A_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/LM323A_sub/PNP.lib b/library/SubcircuitLibrary/LM323A_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/LM323A_sub/analysis b/library/SubcircuitLibrary/LM323A_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/LM323A_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM341_sub/LM341_sub-cache.lib b/library/SubcircuitLibrary/LM341_sub/LM341_sub-cache.lib
new file mode 100644
index 00000000..27408fec
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/LM341_sub-cache.lib
@@ -0,0 +1,138 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM341_sub/LM341_sub.cir b/library/SubcircuitLibrary/LM341_sub/LM341_sub.cir
new file mode 100644
index 00000000..661848b1
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/LM341_sub.cir
@@ -0,0 +1,56 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM341_sub\LM341_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 13/06/2024 6:43:58 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_Q1-Pad2_ Net-_Q1-Pad1_ 80k
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+R2 Net-_Q3-Pad2_ Net-_Q1-Pad3_ 7k
+R3 Net-_Q2-Pad2_ Net-_Q3-Pad2_ 4.97k
+R4 Net-_Q16-Pad3_ Net-_Q2-Pad2_ 830
+R6 Net-_Q16-Pad3_ Net-_C1-Pad1_ 1.2k
+R9 Net-_Q16-Pad3_ Net-_Q10-Pad3_ 12.1k
+R12 Net-_Q16-Pad3_ Net-_Q11-Pad3_ 1k
+R15 Net-_Q16-Pad3_ Net-_Q15-Pad3_ 4k
+Q2 Net-_Q12-Pad1_ Net-_Q2-Pad2_ Net-_Q16-Pad3_ eSim_NPN
+Q9 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q16-Pad3_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q11 Net-_C2-Pad1_ Net-_Q10-Pad3_ Net-_Q11-Pad3_ eSim_NPN
+Q15 Net-_Q14-Pad3_ Net-_Q14-Pad3_ Net-_Q15-Pad3_ eSim_NPN
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 4pF
+Q7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ Net-_C1-Pad1_ eSim_NPN
+Q14 Net-_C2-Pad2_ Net-_C2-Pad1_ Net-_Q14-Pad3_ eSim_NPN
+Q16 Net-_C2-Pad2_ Net-_Q14-Pad3_ Net-_Q16-Pad3_ eSim_NPN
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 20pF
+R8 Net-_C1-Pad2_ Net-_Q7-Pad2_ 26
+R7 Net-_Q7-Pad2_ Net-_Q6-Pad3_ 1.9k
+R11 Net-_C2-Pad1_ Net-_Q10-Pad1_ 16.5k
+Q18 Net-_Q16-Pad3_ Net-_C2-Pad2_ Net-_Q18-Pad3_ eSim_PNP
+R17 Net-_C2-Pad2_ Net-_Q18-Pad3_ 4k
+R16 Net-_Q18-Pad3_ Net-_Q12-Pad1_ 850
+R21 Net-_Q16-Pad3_ Net-_Q13-Pad2_ 2.67k
+Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_Q10-Pad1_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+Q6 Net-_Q5-Pad3_ Net-_Q13-Pad2_ Net-_Q6-Pad3_ eSim_NPN
+R5 Net-_Q6-Pad3_ Net-_Q3-Pad3_ 500
+Q5 Net-_Q3-Pad1_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN
+R20 Net-_Q13-Pad2_ Net-_R10-Pad1_ 1.43k
+R19 Net-_R10-Pad1_ Net-_Q19-Pad3_ 0.25
+R10 Net-_R10-Pad1_ Net-_Q12-Pad3_ 100
+R18 Net-_Q12-Pad2_ Net-_Q13-Pad1_ 1.62k
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+R14 Net-_Q12-Pad2_ Net-_Q19-Pad3_ 380
+U3 Net-_Q12-Pad2_ Net-_R13-Pad1_ zener
+R13 Net-_R13-Pad1_ Net-_R13-Pad2_ 16k
+Q19 Net-_Q1-Pad1_ Net-_Q13-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+Q17 Net-_Q1-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad1_ eSim_NPN
+Q4 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_PNP
+Q8 Net-_Q12-Pad1_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_PNP
+U1 Net-_Q16-Pad3_ Net-_Q1-Pad2_ zener
+U2 Net-_R13-Pad2_ Net-_Q1-Pad1_ zener
+U4 Net-_Q1-Pad1_ Net-_Q16-Pad3_ Net-_R10-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/LM341_sub/LM341_sub.cir.out b/library/SubcircuitLibrary/LM341_sub/LM341_sub.cir.out
new file mode 100644
index 00000000..57dc4350
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/LM341_sub.cir.out
@@ -0,0 +1,68 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm341_sub\lm341_sub.cir
+
+.include NPN.lib
+.include PNP.lib
+r1 net-_q1-pad2_ net-_q1-pad1_ 80k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r2 net-_q3-pad2_ net-_q1-pad3_ 7k
+r3 net-_q2-pad2_ net-_q3-pad2_ 4.97k
+r4 net-_q16-pad3_ net-_q2-pad2_ 830
+r6 net-_q16-pad3_ net-_c1-pad1_ 1.2k
+r9 net-_q16-pad3_ net-_q10-pad3_ 12.1k
+r12 net-_q16-pad3_ net-_q11-pad3_ 1k
+r15 net-_q16-pad3_ net-_q15-pad3_ 4k
+q2 net-_q12-pad1_ net-_q2-pad2_ net-_q16-pad3_ Q2N2222
+q9 net-_c1-pad2_ net-_c1-pad1_ net-_q16-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_c2-pad1_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222
+q15 net-_q14-pad3_ net-_q14-pad3_ net-_q15-pad3_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 4pf
+q7 net-_q6-pad3_ net-_q7-pad2_ net-_c1-pad1_ Q2N2222
+q14 net-_c2-pad2_ net-_c2-pad1_ net-_q14-pad3_ Q2N2222
+q16 net-_c2-pad2_ net-_q14-pad3_ net-_q16-pad3_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 20pf
+r8 net-_c1-pad2_ net-_q7-pad2_ 26
+r7 net-_q7-pad2_ net-_q6-pad3_ 1.9k
+r11 net-_c2-pad1_ net-_q10-pad1_ 16.5k
+q18 net-_q16-pad3_ net-_c2-pad2_ net-_q18-pad3_ Q2N2907A
+r17 net-_c2-pad2_ net-_q18-pad3_ 4k
+r16 net-_q18-pad3_ net-_q12-pad1_ 850
+r21 net-_q16-pad3_ net-_q13-pad2_ 2.67k
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+q6 net-_q5-pad3_ net-_q13-pad2_ net-_q6-pad3_ Q2N2222
+r5 net-_q6-pad3_ net-_q3-pad3_ 500
+q5 net-_q3-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+r20 net-_q13-pad2_ net-_r10-pad1_ 1.43k
+r19 net-_r10-pad1_ net-_q19-pad3_ 0.25
+r10 net-_r10-pad1_ net-_q12-pad3_ 100
+r18 net-_q12-pad2_ net-_q13-pad1_ 1.62k
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r14 net-_q12-pad2_ net-_q19-pad3_ 380
+* u3 net-_q12-pad2_ net-_r13-pad1_ zener
+r13 net-_r13-pad1_ net-_r13-pad2_ 16k
+q19 net-_q1-pad1_ net-_q13-pad1_ net-_q19-pad3_ Q2N2222
+q17 net-_q1-pad1_ net-_q12-pad1_ net-_q13-pad1_ Q2N2222
+q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A
+q8 net-_q12-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A
+* u1 net-_q16-pad3_ net-_q1-pad2_ zener
+* u2 net-_r13-pad2_ net-_q1-pad1_ zener
+* u4 net-_q1-pad1_ net-_q16-pad3_ net-_r10-pad1_ port
+a1 net-_q12-pad2_ net-_r13-pad1_ u3
+a2 net-_q16-pad3_ net-_q1-pad2_ u1
+a3 net-_r13-pad2_ net-_q1-pad1_ u2
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM341_sub/LM341_sub.pro b/library/SubcircuitLibrary/LM341_sub/LM341_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/LM341_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM341_sub/LM341_sub.sch b/library/SubcircuitLibrary/LM341_sub/LM341_sub.sch
new file mode 100644
index 00000000..63b40307
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/LM341_sub.sch
@@ -0,0 +1,825 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:LM341-cache
+EELAYER 25 0
+EELAYER END
+$Descr User 17000 15748
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 666AF137
+P 2750 5650
+F 0 "R1" H 2800 5780 50 0000 C CNN
+F 1 "80k" H 2800 5600 50 0000 C CNN
+F 2 "" H 2800 5630 30 0000 C CNN
+F 3 "" V 2800 5700 30 0000 C CNN
+ 1 2750 5650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 666AF138
+P 3200 6500
+F 0 "Q1" H 3100 6550 50 0000 R CNN
+F 1 "eSim_NPN" H 3150 6650 50 0000 R CNN
+F 2 "" H 3400 6600 29 0000 C CNN
+F 3 "" H 3200 6500 60 0000 C CNN
+ 1 3200 6500
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 666AF139
+P 3350 8350
+F 0 "R2" H 3400 8480 50 0000 C CNN
+F 1 "7k" H 3400 8300 50 0000 C CNN
+F 2 "" H 3400 8330 30 0000 C CNN
+F 3 "" V 3400 8400 30 0000 C CNN
+ 1 3350 8350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R3
+U 1 1 666AF13A
+P 3350 10450
+F 0 "R3" H 3400 10580 50 0000 C CNN
+F 1 "4.97k" H 3400 10400 50 0000 C CNN
+F 2 "" H 3400 10430 30 0000 C CNN
+F 3 "" V 3400 10500 30 0000 C CNN
+ 1 3350 10450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 666AF13B
+P 3350 12200
+F 0 "R4" H 3400 12330 50 0000 C CNN
+F 1 "830" H 3400 12150 50 0000 C CNN
+F 2 "" H 3400 12180 30 0000 C CNN
+F 3 "" V 3400 12250 30 0000 C CNN
+ 1 3350 12200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R6
+U 1 1 666AF13C
+P 5950 12200
+F 0 "R6" H 6000 12330 50 0000 C CNN
+F 1 "1.2k" H 6000 12150 50 0000 C CNN
+F 2 "" H 6000 12180 30 0000 C CNN
+F 3 "" V 6000 12250 30 0000 C CNN
+ 1 5950 12200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R9
+U 1 1 666AF13D
+P 7950 12200
+F 0 "R9" H 8000 12330 50 0000 C CNN
+F 1 "12.1k" H 8000 12150 50 0000 C CNN
+F 2 "" H 8000 12180 30 0000 C CNN
+F 3 "" V 8000 12250 30 0000 C CNN
+ 1 7950 12200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R12
+U 1 1 666AF13E
+P 8850 12200
+F 0 "R12" H 8900 12330 50 0000 C CNN
+F 1 "1k" H 8900 12150 50 0000 C CNN
+F 2 "" H 8900 12180 30 0000 C CNN
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+ 0 1 -1 0
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+$Comp
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+ 0 1 -1 0
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+ -1 0 0 -1
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diff --git a/library/SubcircuitLibrary/LM341_sub/LM341_sub.sub b/library/SubcircuitLibrary/LM341_sub/LM341_sub.sub
new file mode 100644
index 00000000..cd8f2394
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/LM341_sub.sub
@@ -0,0 +1,62 @@
+* Subcircuit LM341_sub
+.subckt LM341_sub net-_q1-pad1_ net-_q16-pad3_ net-_r10-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm341_sub\lm341_sub.cir
+.include NPN.lib
+.include PNP.lib
+r1 net-_q1-pad2_ net-_q1-pad1_ 80k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r2 net-_q3-pad2_ net-_q1-pad3_ 7k
+r3 net-_q2-pad2_ net-_q3-pad2_ 4.97k
+r4 net-_q16-pad3_ net-_q2-pad2_ 830
+r6 net-_q16-pad3_ net-_c1-pad1_ 1.2k
+r9 net-_q16-pad3_ net-_q10-pad3_ 12.1k
+r12 net-_q16-pad3_ net-_q11-pad3_ 1k
+r15 net-_q16-pad3_ net-_q15-pad3_ 4k
+q2 net-_q12-pad1_ net-_q2-pad2_ net-_q16-pad3_ Q2N2222
+q9 net-_c1-pad2_ net-_c1-pad1_ net-_q16-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_c2-pad1_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222
+q15 net-_q14-pad3_ net-_q14-pad3_ net-_q15-pad3_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 4pf
+q7 net-_q6-pad3_ net-_q7-pad2_ net-_c1-pad1_ Q2N2222
+q14 net-_c2-pad2_ net-_c2-pad1_ net-_q14-pad3_ Q2N2222
+q16 net-_c2-pad2_ net-_q14-pad3_ net-_q16-pad3_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 20pf
+r8 net-_c1-pad2_ net-_q7-pad2_ 26
+r7 net-_q7-pad2_ net-_q6-pad3_ 1.9k
+r11 net-_c2-pad1_ net-_q10-pad1_ 16.5k
+q18 net-_q16-pad3_ net-_c2-pad2_ net-_q18-pad3_ Q2N2907A
+r17 net-_c2-pad2_ net-_q18-pad3_ 4k
+r16 net-_q18-pad3_ net-_q12-pad1_ 850
+r21 net-_q16-pad3_ net-_q13-pad2_ 2.67k
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+q6 net-_q5-pad3_ net-_q13-pad2_ net-_q6-pad3_ Q2N2222
+r5 net-_q6-pad3_ net-_q3-pad3_ 500
+q5 net-_q3-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222
+r20 net-_q13-pad2_ net-_r10-pad1_ 1.43k
+r19 net-_r10-pad1_ net-_q19-pad3_ 0.25
+r10 net-_r10-pad1_ net-_q12-pad3_ 100
+r18 net-_q12-pad2_ net-_q13-pad1_ 1.62k
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r14 net-_q12-pad2_ net-_q19-pad3_ 380
+* u3 net-_q12-pad2_ net-_r13-pad1_ zener
+r13 net-_r13-pad1_ net-_r13-pad2_ 16k
+q19 net-_q1-pad1_ net-_q13-pad1_ net-_q19-pad3_ Q2N2222
+q17 net-_q1-pad1_ net-_q12-pad1_ net-_q13-pad1_ Q2N2222
+q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A
+q8 net-_q12-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A
+* u1 net-_q16-pad3_ net-_q1-pad2_ zener
+* u2 net-_r13-pad2_ net-_q1-pad1_ zener
+a1 net-_q12-pad2_ net-_r13-pad1_ u3
+a2 net-_q16-pad3_ net-_q1-pad2_ u1
+a3 net-_r13-pad2_ net-_q1-pad1_ u2
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends LM341_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM341_sub/LM341_sub_Previous_Values.xml b/library/SubcircuitLibrary/LM341_sub/LM341_sub_Previous_Values.xml
new file mode 100644
index 00000000..97b4bd41
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/LM341_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)">5.6</field1><field2 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field2><field3 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field3><field4 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field4><field5 name="Enter Switch for Limiting (default=FALSE)">FALSE</field5></u3><u1 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)">5.6</field6><field7 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field7><field8 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field8><field9 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field9><field10 name="Enter Switch for Limiting (default=FALSE)">FALSE</field10></u1><u2 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)">5.6</field11><field12 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field12><field13 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field13><field14 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field14><field15 name="Enter Switch for Limiting (default=FALSE)">FALSE</field15></u2></model><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8></devicemodel><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM341_sub/NPN.lib b/library/SubcircuitLibrary/LM341_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/LM341_sub/PNP.lib b/library/SubcircuitLibrary/LM341_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/LM341_sub/analysis b/library/SubcircuitLibrary/LM341_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/LM341_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM380_sub/D.lib b/library/SubcircuitLibrary/LM380_sub/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/LM380_sub/LM380_sub-cache.lib b/library/SubcircuitLibrary/LM380_sub/LM380_sub-cache.lib
new file mode 100644
index 00000000..d80602ef
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/LM380_sub-cache.lib
@@ -0,0 +1,145 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM380_sub/LM380_sub.cir b/library/SubcircuitLibrary/LM380_sub/LM380_sub.cir
new file mode 100644
index 00000000..7010d935
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/LM380_sub.cir
@@ -0,0 +1,34 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM380_sub\LM380_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 17/06/2024 11:51:25 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP
+Q2 Net-_Q2-Pad1_ Net-_Q1-Pad3_ Net-_Q2-Pad3_ eSim_PNP
+Q5 Net-_C1-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP
+Q4 Net-_Q4-Pad1_ Net-_Q4-Pad1_ Net-_Q11-Pad1_ eSim_PNP
+Q7 Net-_Q1-Pad1_ Net-_Q7-Pad2_ Net-_Q5-Pad2_ eSim_PNP
+Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q6 Net-_C1-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_D1-Pad1_ Net-_Q11-Pad3_ eSim_NPN
+Q12 Net-_Q10-Pad3_ Net-_Q10-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q9 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q8 Net-_D1-Pad1_ Net-_Q4-Pad1_ Net-_Q11-Pad1_ eSim_PNP
+Q10 Net-_Q10-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+R1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 150k
+R4 Net-_Q2-Pad3_ Net-_Q5-Pad3_ 125K
+R3 Net-_Q2-Pad3_ Net-_R2-Pad1_ 17.5K
+R2 Net-_R2-Pad1_ Net-_Q4-Pad1_ 17.5k
+R5 Net-_Q5-Pad3_ Net-_R5-Pad2_ 22.5K
+R6 Net-_Q1-Pad1_ Net-_Q7-Pad2_ 150K
+R7 Net-_R5-Pad2_ Net-_Q11-Pad3_ 0.5
+R8 Net-_Q10-Pad3_ Net-_R5-Pad2_ 0.5
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10pF
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+D2 Net-_D1-Pad2_ Net-_C1-Pad2_ eSim_Diode
+U1 Net-_R2-Pad1_ Net-_Q7-Pad2_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad1_ Net-_R5-Pad2_ Net-_Q11-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/LM380_sub/LM380_sub.cir.out b/library/SubcircuitLibrary/LM380_sub/LM380_sub.cir.out
new file mode 100644
index 00000000..e37bfaa3
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/LM380_sub.cir.out
@@ -0,0 +1,38 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm380_sub\lm380_sub.cir
+
+.include NPN.lib
+.include D.lib
+.include PNP.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A
+q5 net-_c1-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
+q4 net-_q4-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q7 net-_q1-pad1_ net-_q7-pad2_ net-_q5-pad2_ Q2N2907A
+q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q6 net-_c1-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q11 net-_q11-pad1_ net-_d1-pad1_ net-_q11-pad3_ Q2N2222
+q12 net-_q10-pad3_ net-_q10-pad1_ net-_q1-pad1_ Q2N2222
+q9 net-_c1-pad2_ net-_c1-pad1_ net-_q1-pad1_ Q2N2222
+q8 net-_d1-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q10 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad3_ Q2N2907A
+r1 net-_q1-pad1_ net-_q1-pad2_ 150k
+r4 net-_q2-pad3_ net-_q5-pad3_ 125k
+r3 net-_q2-pad3_ net-_r2-pad1_ 17.5k
+r2 net-_r2-pad1_ net-_q4-pad1_ 17.5k
+r5 net-_q5-pad3_ net-_r5-pad2_ 22.5k
+r6 net-_q1-pad1_ net-_q7-pad2_ 150k
+r7 net-_r5-pad2_ net-_q11-pad3_ 0.5
+r8 net-_q10-pad3_ net-_r5-pad2_ 0.5
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c1-pad2_ 1N4148
+* u1 net-_r2-pad1_ net-_q7-pad2_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad1_ net-_r5-pad2_ net-_q11-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q11-pad1_ net-_q11-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM380_sub/LM380_sub.pro b/library/SubcircuitLibrary/LM380_sub/LM380_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/LM380_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM380_sub/LM380_sub.sch b/library/SubcircuitLibrary/LM380_sub/LM380_sub.sch
new file mode 100644
index 00000000..1bcd36e5
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/LM380_sub.sch
@@ -0,0 +1,622 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
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diff --git a/library/SubcircuitLibrary/LM380_sub/LM380_sub.sub b/library/SubcircuitLibrary/LM380_sub/LM380_sub.sub
new file mode 100644
index 00000000..fb7b3227
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/LM380_sub.sub
@@ -0,0 +1,32 @@
+* Subcircuit LM380_sub
+.subckt LM380_sub net-_r2-pad1_ net-_q7-pad2_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad1_ net-_r5-pad2_ net-_q11-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q11-pad1_ net-_q11-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm380_sub\lm380_sub.cir
+.include NPN.lib
+.include D.lib
+.include PNP.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A
+q5 net-_c1-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
+q4 net-_q4-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q7 net-_q1-pad1_ net-_q7-pad2_ net-_q5-pad2_ Q2N2907A
+q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q6 net-_c1-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q11 net-_q11-pad1_ net-_d1-pad1_ net-_q11-pad3_ Q2N2222
+q12 net-_q10-pad3_ net-_q10-pad1_ net-_q1-pad1_ Q2N2222
+q9 net-_c1-pad2_ net-_c1-pad1_ net-_q1-pad1_ Q2N2222
+q8 net-_d1-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q10 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad3_ Q2N2907A
+r1 net-_q1-pad1_ net-_q1-pad2_ 150k
+r4 net-_q2-pad3_ net-_q5-pad3_ 125k
+r3 net-_q2-pad3_ net-_r2-pad1_ 17.5k
+r2 net-_r2-pad1_ net-_q4-pad1_ 17.5k
+r5 net-_q5-pad3_ net-_r5-pad2_ 22.5k
+r6 net-_q1-pad1_ net-_q7-pad2_ 150k
+r7 net-_r5-pad2_ net-_q11-pad3_ 0.5
+r8 net-_q10-pad3_ net-_r5-pad2_ 0.5
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c1-pad2_ 1N4148
+* Control Statements
+
+.ends LM380_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM380_sub/LM380_sub_Previous_Values.xml b/library/SubcircuitLibrary/LM380_sub/LM380_sub_Previous_Values.xml
new file mode 100644
index 00000000..d1a61d87
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/LM380_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM380_sub/NPN.lib b/library/SubcircuitLibrary/LM380_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/LM380_sub/PNP.lib b/library/SubcircuitLibrary/LM380_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/LM380_sub/analysis b/library/SubcircuitLibrary/LM380_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/LM380_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/3_and-cache.lib
new file mode 100644
index 00000000..af058641
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.cir b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir
new file mode 100644
index 00000000..ba296cf0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out
new file mode 100644
index 00000000..d7cf79a0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.pro b/library/SubcircuitLibrary/SN7483A_sub/3_and.pro
new file mode 100644
index 00000000..00597a5a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.sch b/library/SubcircuitLibrary/SN7483A_sub/3_and.sch
new file mode 100644
index 00000000..d6ac89f9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.sub b/library/SubcircuitLibrary/SN7483A_sub/3_and.sub
new file mode 100644
index 00000000..3d9120bb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/3_and_Previous_Values.xml
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/4_OR-cache.lib
new file mode 100644
index 00000000..155f5e60
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir
new file mode 100644
index 00000000..b338b7b5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out
new file mode 100644
index 00000000..adb6b01b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.pro b/library/SubcircuitLibrary/SN7483A_sub/4_OR.pro
new file mode 100644
index 00000000..881563eb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.sch b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sch
new file mode 100644
index 00000000..11896865
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
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+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.sub b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sub
new file mode 100644
index 00000000..d1fd3a24
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/4_OR_Previous_Values.xml
new file mode 100644
index 00000000..0683d9eb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/4_and-cache.lib
new file mode 100644
index 00000000..60f1a83d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and-rescue.lib b/library/SubcircuitLibrary/SN7483A_sub/4_and-rescue.lib
new file mode 100644
index 00000000..e3833051
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.cir b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir
new file mode 100644
index 00000000..fdf2e107
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.cir.out b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir.out
new file mode 100644
index 00000000..f40e5bc6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.pro b/library/SubcircuitLibrary/SN7483A_sub/4_and.pro
new file mode 100644
index 00000000..b13a0a82
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.sch b/library/SubcircuitLibrary/SN7483A_sub/4_and.sch
new file mode 100644
index 00000000..f5e8febd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.sub b/library/SubcircuitLibrary/SN7483A_sub/4_and.sub
new file mode 100644
index 00000000..8663f37e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/4_and_Previous_Values.xml
new file mode 100644
index 00000000..f2ba0130
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/5_and-cache.lib
new file mode 100644
index 00000000..fc177c1f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN7483A_sub/5_and-rescue.lib
new file mode 100644
index 00000000..483b8efb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.cir b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir
new file mode 100644
index 00000000..6a05b9b5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
+U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
+U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.cir.out b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir.out
new file mode 100644
index 00000000..6a6b126a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.pro b/library/SubcircuitLibrary/SN7483A_sub/5_and.pro
new file mode 100644
index 00000000..c16a3f85
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.sch b/library/SubcircuitLibrary/SN7483A_sub/5_and.sch
new file mode 100644
index 00000000..aef3c043
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60 0000 C CNN
+F 1 "3_and" H 4750 3850 60 0000 C CNN
+F 2 "" H 3800 3350 60 0000 C CNN
+F 3 "" H 3800 3350 60 0000 C CNN
+ 1 3800 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60 0000 C CNN
+F 1 "d_and" H 4700 3500 60 0000 C CNN
+F 2 "" H 4650 3400 60 0000 C CNN
+F 3 "" H 4650 3400 60 0000 C CNN
+ 1 4650 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60 0000 C CNN
+F 1 "d_and" H 5600 3300 60 0000 C CNN
+F 2 "" H 5550 3200 60 0000 C CNN
+F 3 "" H 5550 3200 60 0000 C CNN
+ 1 5550 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5100 3100 5100 2950
+Wire Wire Line
+ 5100 3200 5100 3350
+Wire Wire Line
+ 4250 2850 4250 2700
+Wire Wire Line
+ 4250 2700 3600 2700
+Wire Wire Line
+ 4250 2950 4150 2950
+Wire Wire Line
+ 4150 2950 4150 2900
+Wire Wire Line
+ 4150 2900 3600 2900
+Wire Wire Line
+ 4200 3300 3600 3300
+Wire Wire Line
+ 4250 3050 4250 3100
+Wire Wire Line
+ 4250 3100 3600 3100
+Wire Wire Line
+ 4200 3400 4200 3500
+Wire Wire Line
+ 4200 3500 3600 3500
+Wire Wire Line
+ 6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30 0000 C CNN
+F 1 "PORT" H 3350 2700 30 0000 C CNN
+F 2 "" H 3350 2700 60 0000 C CNN
+F 3 "" H 3350 2700 60 0000 C CNN
+ 1 3350 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30 0000 C CNN
+F 1 "PORT" H 3350 2900 30 0000 C CNN
+F 2 "" H 3350 2900 60 0000 C CNN
+F 3 "" H 3350 2900 60 0000 C CNN
+ 2 3350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30 0000 C CNN
+F 1 "PORT" H 3350 3100 30 0000 C CNN
+F 2 "" H 3350 3100 60 0000 C CNN
+F 3 "" H 3350 3100 60 0000 C CNN
+ 3 3350 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30 0000 C CNN
+F 1 "PORT" H 3350 3300 30 0000 C CNN
+F 2 "" H 3350 3300 60 0000 C CNN
+F 3 "" H 3350 3300 60 0000 C CNN
+ 4 3350 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30 0000 C CNN
+F 1 "PORT" H 3350 3500 30 0000 C CNN
+F 2 "" H 3350 3500 60 0000 C CNN
+F 3 "" H 3350 3500 60 0000 C CNN
+ 5 3350 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30 0000 C CNN
+F 1 "PORT" H 6750 3150 30 0000 C CNN
+F 2 "" H 6750 3150 60 0000 C CNN
+F 3 "" H 6750 3150 60 0000 C CNN
+ 6 6750 3150
+ -1 0 0 1
+$EndComp
+Text Notes 3800 2700 0 60 ~ 12
+in1
+Text Notes 3800 2900 0 60 ~ 12
+in2
+Text Notes 3800 3100 0 60 ~ 12
+in3
+Text Notes 3800 3300 0 60 ~ 12
+in4
+Text Notes 3800 3500 0 60 ~ 12
+in5
+Text Notes 6150 3150 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.sub b/library/SubcircuitLibrary/SN7483A_sub/5_and.sub
new file mode 100644
index 00000000..35b10e17
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/5_and_Previous_Values.xml
new file mode 100644
index 00000000..ae2c08a7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub-cache.lib
new file mode 100644
index 00000000..45a4afe5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub-cache.lib
@@ -0,0 +1,306 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 50 -100 60 H V C CNN
+F1 "5_and" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -250 250 150 250 N
+P 3 0 1 0 -250 250 -250 -250 150 -250 N
+X in1 1 -450 200 200 R 50 50 1 1 I
+X in2 2 -450 100 200 R 50 50 1 1 I
+X in3 3 -450 0 200 R 50 50 1 1 I
+X in4 4 -450 -100 200 R 50 50 1 1 I
+X in5 5 -450 -200 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_5
+#
+DEF dac_bridge_5 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_5" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -400 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X OUT1 6 550 50 200 L 50 50 1 1 O
+X OUT2 7 550 -50 200 L 50 50 1 1 O
+X OUT3 8 550 -150 200 L 50 50 1 1 O
+X OUT4 9 550 -250 200 L 50 50 1 1 O
+X OUT5 10 550 -350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir
new file mode 100644
index 00000000..42089f0f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir
@@ -0,0 +1,60 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7483A_sub\SN7483A_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 13/06/2024 2:46:07 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U23 Net-_U12-Pad3_ Net-_U23-Pad2_ d_buffer
+U24 Net-_U15-Pad1_ Net-_U11-Pad3_ Net-_U24-Pad3_ d_and
+X1 Net-_U13-Pad1_ Net-_U11-Pad3_ Net-_U21-Pad1_ Net-_X1-Pad4_ 3_and
+X2 Net-_U14-Pad1_ Net-_U11-Pad3_ Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_X2-Pad5_ 4_and
+X4 Net-_U11-Pad3_ Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_U36-Pad2_ 5_and
+X8 Net-_U23-Pad2_ Net-_U24-Pad3_ Net-_X1-Pad4_ Net-_X2-Pad5_ Net-_U36-Pad1_ 4_OR
+U36 Net-_U36-Pad1_ Net-_U36-Pad2_ Net-_U36-Pad3_ d_or
+U40 Net-_U36-Pad3_ Net-_U40-Pad2_ d_inverter
+U26 Net-_U11-Pad3_ Net-_U16-Pad2_ Net-_U26-Pad3_ d_and
+U16 Net-_U12-Pad3_ Net-_U16-Pad2_ d_inverter
+U27 Net-_U15-Pad1_ Net-_U27-Pad2_ d_buffer
+U29 Net-_U13-Pad1_ Net-_U21-Pad1_ Net-_U29-Pad3_ d_and
+X5 Net-_U14-Pad1_ Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_X5-Pad4_ 3_and
+X6 Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_X6-Pad5_ 4_and
+X7 Net-_U27-Pad2_ Net-_U29-Pad3_ Net-_X5-Pad4_ Net-_X6-Pad5_ Net-_U35-Pad1_ 4_OR
+U35 Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter
+U39 Net-_U26-Pad3_ Net-_U35-Pad2_ Net-_U39-Pad3_ d_xor
+U21 Net-_U21-Pad1_ Net-_U15-Pad2_ Net-_U21-Pad3_ d_and
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U22 Net-_U13-Pad1_ Net-_U22-Pad2_ d_buffer
+U28 Net-_U14-Pad1_ Net-_U17-Pad1_ Net-_U28-Pad3_ d_and
+X3 Net-_U17-Pad1_ Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_U33-Pad2_ 3_and
+U30 Net-_U22-Pad2_ Net-_U28-Pad3_ Net-_U30-Pad3_ d_or
+U33 Net-_U30-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or
+U41 Net-_U21-Pad3_ Net-_U37-Pad2_ Net-_U41-Pad3_ d_xor
+U17 Net-_U17-Pad1_ Net-_U13-Pad2_ Net-_U17-Pad3_ d_and
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U18 Net-_U14-Pad1_ Net-_U18-Pad2_ d_buffer
+U25 Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_U25-Pad3_ d_and
+U19 Net-_U19-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U34 Net-_U31-Pad3_ Net-_U34-Pad2_ d_inverter
+U38 Net-_U17-Pad3_ Net-_U34-Pad2_ Net-_U38-Pad3_ d_xor
+U32 Net-_U19-Pad3_ Net-_U20-Pad2_ Net-_U32-Pad3_ d_xor
+U31 Net-_U18-Pad2_ Net-_U25-Pad3_ Net-_U31-Pad3_ d_or
+U20 Net-_U10-Pad2_ Net-_U20-Pad2_ d_inverter
+U37 Net-_U33-Pad3_ Net-_U37-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand
+U12 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad3_ d_nor
+U8 Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U21-Pad1_ d_nand
+U9 Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U15-Pad1_ d_nor
+U4 Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U17-Pad1_ d_nand
+U5 Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U13-Pad1_ d_nor
+U6 Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U19-Pad1_ d_nand
+U7 Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U14-Pad1_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad8_ Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8
+U3 Net-_U1-Pad7_ Net-_U10-Pad1_ adc_bridge_1
+U42 Net-_U40-Pad2_ Net-_U39-Pad3_ Net-_U41-Pad3_ Net-_U38-Pad3_ Net-_U32-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U1-Pad1_ Net-_U1-Pad4_ dac_bridge_5
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir.out b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir.out
new file mode 100644
index 00000000..4230bedc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir.out
@@ -0,0 +1,188 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7483a_sub\sn7483a_sub.cir
+
+.include 3_and.sub
+.include 4_OR.sub
+.include 4_and.sub
+.include 5_and.sub
+* u23 net-_u12-pad3_ net-_u23-pad2_ d_buffer
+* u24 net-_u15-pad1_ net-_u11-pad3_ net-_u24-pad3_ d_and
+x1 net-_u13-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_x1-pad4_ 3_and
+x2 net-_u14-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_x2-pad5_ 4_and
+x4 net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u36-pad2_ 5_and
+x8 net-_u23-pad2_ net-_u24-pad3_ net-_x1-pad4_ net-_x2-pad5_ net-_u36-pad1_ 4_OR
+* u36 net-_u36-pad1_ net-_u36-pad2_ net-_u36-pad3_ d_or
+* u40 net-_u36-pad3_ net-_u40-pad2_ d_inverter
+* u26 net-_u11-pad3_ net-_u16-pad2_ net-_u26-pad3_ d_and
+* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter
+* u27 net-_u15-pad1_ net-_u27-pad2_ d_buffer
+* u29 net-_u13-pad1_ net-_u21-pad1_ net-_u29-pad3_ d_and
+x5 net-_u14-pad1_ net-_u21-pad1_ net-_u17-pad1_ net-_x5-pad4_ 3_and
+x6 net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_x6-pad5_ 4_and
+x7 net-_u27-pad2_ net-_u29-pad3_ net-_x5-pad4_ net-_x6-pad5_ net-_u35-pad1_ 4_OR
+* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter
+* u39 net-_u26-pad3_ net-_u35-pad2_ net-_u39-pad3_ d_xor
+* u21 net-_u21-pad1_ net-_u15-pad2_ net-_u21-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u22 net-_u13-pad1_ net-_u22-pad2_ d_buffer
+* u28 net-_u14-pad1_ net-_u17-pad1_ net-_u28-pad3_ d_and
+x3 net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u33-pad2_ 3_and
+* u30 net-_u22-pad2_ net-_u28-pad3_ net-_u30-pad3_ d_or
+* u33 net-_u30-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
+* u41 net-_u21-pad3_ net-_u37-pad2_ net-_u41-pad3_ d_xor
+* u17 net-_u17-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_and
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u18 net-_u14-pad1_ net-_u18-pad2_ d_buffer
+* u25 net-_u19-pad1_ net-_u10-pad2_ net-_u25-pad3_ d_and
+* u19 net-_u19-pad1_ net-_u14-pad2_ net-_u19-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u34 net-_u31-pad3_ net-_u34-pad2_ d_inverter
+* u38 net-_u17-pad3_ net-_u34-pad2_ net-_u38-pad3_ d_xor
+* u32 net-_u19-pad3_ net-_u20-pad2_ net-_u32-pad3_ d_xor
+* u31 net-_u18-pad2_ net-_u25-pad3_ net-_u31-pad3_ d_or
+* u20 net-_u10-pad2_ net-_u20-pad2_ d_inverter
+* u37 net-_u33-pad3_ net-_u37-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u12 net-_u11-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_nor
+* u8 net-_u2-pad11_ net-_u2-pad12_ net-_u21-pad1_ d_nand
+* u9 net-_u2-pad11_ net-_u2-pad12_ net-_u15-pad1_ d_nor
+* u4 net-_u2-pad13_ net-_u2-pad14_ net-_u17-pad1_ d_nand
+* u5 net-_u2-pad13_ net-_u2-pad14_ net-_u13-pad1_ d_nor
+* u6 net-_u2-pad15_ net-_u2-pad16_ net-_u19-pad1_ d_nand
+* u7 net-_u2-pad15_ net-_u2-pad16_ net-_u14-pad1_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8
+* u3 net-_u1-pad7_ net-_u10-pad1_ adc_bridge_1
+* u42 net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ dac_bridge_5
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 net-_u12-pad3_ net-_u23-pad2_ u23
+a2 [net-_u15-pad1_ net-_u11-pad3_ ] net-_u24-pad3_ u24
+a3 [net-_u36-pad1_ net-_u36-pad2_ ] net-_u36-pad3_ u36
+a4 net-_u36-pad3_ net-_u40-pad2_ u40
+a5 [net-_u11-pad3_ net-_u16-pad2_ ] net-_u26-pad3_ u26
+a6 net-_u12-pad3_ net-_u16-pad2_ u16
+a7 net-_u15-pad1_ net-_u27-pad2_ u27
+a8 [net-_u13-pad1_ net-_u21-pad1_ ] net-_u29-pad3_ u29
+a9 net-_u35-pad1_ net-_u35-pad2_ u35
+a10 [net-_u26-pad3_ net-_u35-pad2_ ] net-_u39-pad3_ u39
+a11 [net-_u21-pad1_ net-_u15-pad2_ ] net-_u21-pad3_ u21
+a12 net-_u15-pad1_ net-_u15-pad2_ u15
+a13 net-_u13-pad1_ net-_u22-pad2_ u22
+a14 [net-_u14-pad1_ net-_u17-pad1_ ] net-_u28-pad3_ u28
+a15 [net-_u22-pad2_ net-_u28-pad3_ ] net-_u30-pad3_ u30
+a16 [net-_u30-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a17 [net-_u21-pad3_ net-_u37-pad2_ ] net-_u41-pad3_ u41
+a18 [net-_u17-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17
+a19 net-_u13-pad1_ net-_u13-pad2_ u13
+a20 net-_u14-pad1_ net-_u18-pad2_ u18
+a21 [net-_u19-pad1_ net-_u10-pad2_ ] net-_u25-pad3_ u25
+a22 [net-_u19-pad1_ net-_u14-pad2_ ] net-_u19-pad3_ u19
+a23 net-_u14-pad1_ net-_u14-pad2_ u14
+a24 net-_u31-pad3_ net-_u34-pad2_ u34
+a25 [net-_u17-pad3_ net-_u34-pad2_ ] net-_u38-pad3_ u38
+a26 [net-_u19-pad3_ net-_u20-pad2_ ] net-_u32-pad3_ u32
+a27 [net-_u18-pad2_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a28 net-_u10-pad2_ net-_u20-pad2_ u20
+a29 net-_u33-pad3_ net-_u37-pad2_ u37
+a30 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a31 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12
+a32 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u21-pad1_ u8
+a33 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u15-pad1_ u9
+a34 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u17-pad1_ u4
+a35 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u13-pad1_ u5
+a36 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u19-pad1_ u6
+a37 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u14-pad1_ u7
+a38 net-_u10-pad1_ net-_u10-pad2_ u10
+a39 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ ] [net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2
+a40 [net-_u1-pad7_ ] [net-_u10-pad1_ ] u3
+a41 [net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ ] u42
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u30 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u38 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge
+.model u42 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.pro b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch
new file mode 100644
index 00000000..4987c996
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch
@@ -0,0 +1,1136 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN7483A-cache
+EELAYER 25 0
+EELAYER END
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+$EndComp
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diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sub b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sub
new file mode 100644
index 00000000..206847bc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sub
@@ -0,0 +1,182 @@
+* Subcircuit SN7483A_sub
+.subckt SN7483A_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
+* c:\fossee\esim\library\subcircuitlibrary\sn7483a_sub\sn7483a_sub.cir
+.include 3_and.sub
+.include 4_OR.sub
+.include 4_and.sub
+.include 5_and.sub
+* u23 net-_u12-pad3_ net-_u23-pad2_ d_buffer
+* u24 net-_u15-pad1_ net-_u11-pad3_ net-_u24-pad3_ d_and
+x1 net-_u13-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_x1-pad4_ 3_and
+x2 net-_u14-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_x2-pad5_ 4_and
+x4 net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u36-pad2_ 5_and
+x8 net-_u23-pad2_ net-_u24-pad3_ net-_x1-pad4_ net-_x2-pad5_ net-_u36-pad1_ 4_OR
+* u36 net-_u36-pad1_ net-_u36-pad2_ net-_u36-pad3_ d_or
+* u40 net-_u36-pad3_ net-_u40-pad2_ d_inverter
+* u26 net-_u11-pad3_ net-_u16-pad2_ net-_u26-pad3_ d_and
+* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter
+* u27 net-_u15-pad1_ net-_u27-pad2_ d_buffer
+* u29 net-_u13-pad1_ net-_u21-pad1_ net-_u29-pad3_ d_and
+x5 net-_u14-pad1_ net-_u21-pad1_ net-_u17-pad1_ net-_x5-pad4_ 3_and
+x6 net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_x6-pad5_ 4_and
+x7 net-_u27-pad2_ net-_u29-pad3_ net-_x5-pad4_ net-_x6-pad5_ net-_u35-pad1_ 4_OR
+* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter
+* u39 net-_u26-pad3_ net-_u35-pad2_ net-_u39-pad3_ d_xor
+* u21 net-_u21-pad1_ net-_u15-pad2_ net-_u21-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u22 net-_u13-pad1_ net-_u22-pad2_ d_buffer
+* u28 net-_u14-pad1_ net-_u17-pad1_ net-_u28-pad3_ d_and
+x3 net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u33-pad2_ 3_and
+* u30 net-_u22-pad2_ net-_u28-pad3_ net-_u30-pad3_ d_or
+* u33 net-_u30-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
+* u41 net-_u21-pad3_ net-_u37-pad2_ net-_u41-pad3_ d_xor
+* u17 net-_u17-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_and
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u18 net-_u14-pad1_ net-_u18-pad2_ d_buffer
+* u25 net-_u19-pad1_ net-_u10-pad2_ net-_u25-pad3_ d_and
+* u19 net-_u19-pad1_ net-_u14-pad2_ net-_u19-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u34 net-_u31-pad3_ net-_u34-pad2_ d_inverter
+* u38 net-_u17-pad3_ net-_u34-pad2_ net-_u38-pad3_ d_xor
+* u32 net-_u19-pad3_ net-_u20-pad2_ net-_u32-pad3_ d_xor
+* u31 net-_u18-pad2_ net-_u25-pad3_ net-_u31-pad3_ d_or
+* u20 net-_u10-pad2_ net-_u20-pad2_ d_inverter
+* u37 net-_u33-pad3_ net-_u37-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u12 net-_u11-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_nor
+* u8 net-_u2-pad11_ net-_u2-pad12_ net-_u21-pad1_ d_nand
+* u9 net-_u2-pad11_ net-_u2-pad12_ net-_u15-pad1_ d_nor
+* u4 net-_u2-pad13_ net-_u2-pad14_ net-_u17-pad1_ d_nand
+* u5 net-_u2-pad13_ net-_u2-pad14_ net-_u13-pad1_ d_nor
+* u6 net-_u2-pad15_ net-_u2-pad16_ net-_u19-pad1_ d_nand
+* u7 net-_u2-pad15_ net-_u2-pad16_ net-_u14-pad1_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8
+* u3 net-_u1-pad7_ net-_u10-pad1_ adc_bridge_1
+* u42 net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ dac_bridge_5
+a1 net-_u12-pad3_ net-_u23-pad2_ u23
+a2 [net-_u15-pad1_ net-_u11-pad3_ ] net-_u24-pad3_ u24
+a3 [net-_u36-pad1_ net-_u36-pad2_ ] net-_u36-pad3_ u36
+a4 net-_u36-pad3_ net-_u40-pad2_ u40
+a5 [net-_u11-pad3_ net-_u16-pad2_ ] net-_u26-pad3_ u26
+a6 net-_u12-pad3_ net-_u16-pad2_ u16
+a7 net-_u15-pad1_ net-_u27-pad2_ u27
+a8 [net-_u13-pad1_ net-_u21-pad1_ ] net-_u29-pad3_ u29
+a9 net-_u35-pad1_ net-_u35-pad2_ u35
+a10 [net-_u26-pad3_ net-_u35-pad2_ ] net-_u39-pad3_ u39
+a11 [net-_u21-pad1_ net-_u15-pad2_ ] net-_u21-pad3_ u21
+a12 net-_u15-pad1_ net-_u15-pad2_ u15
+a13 net-_u13-pad1_ net-_u22-pad2_ u22
+a14 [net-_u14-pad1_ net-_u17-pad1_ ] net-_u28-pad3_ u28
+a15 [net-_u22-pad2_ net-_u28-pad3_ ] net-_u30-pad3_ u30
+a16 [net-_u30-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a17 [net-_u21-pad3_ net-_u37-pad2_ ] net-_u41-pad3_ u41
+a18 [net-_u17-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17
+a19 net-_u13-pad1_ net-_u13-pad2_ u13
+a20 net-_u14-pad1_ net-_u18-pad2_ u18
+a21 [net-_u19-pad1_ net-_u10-pad2_ ] net-_u25-pad3_ u25
+a22 [net-_u19-pad1_ net-_u14-pad2_ ] net-_u19-pad3_ u19
+a23 net-_u14-pad1_ net-_u14-pad2_ u14
+a24 net-_u31-pad3_ net-_u34-pad2_ u34
+a25 [net-_u17-pad3_ net-_u34-pad2_ ] net-_u38-pad3_ u38
+a26 [net-_u19-pad3_ net-_u20-pad2_ ] net-_u32-pad3_ u32
+a27 [net-_u18-pad2_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a28 net-_u10-pad2_ net-_u20-pad2_ u20
+a29 net-_u33-pad3_ net-_u37-pad2_ u37
+a30 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a31 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12
+a32 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u21-pad1_ u8
+a33 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u15-pad1_ u9
+a34 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u17-pad1_ u4
+a35 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u13-pad1_ u5
+a36 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u19-pad1_ u6
+a37 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u14-pad1_ u7
+a38 net-_u10-pad1_ net-_u10-pad2_ u10
+a39 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ ] [net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2
+a40 [net-_u1-pad7_ ] [net-_u10-pad1_ ] u3
+a41 [net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ ] u42
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u30 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u38 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge
+.model u42 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends SN7483A_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub_Previous_Values.xml
new file mode 100644
index 00000000..13a8b429
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u23 name="type">d_buffer<field1 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field1><field2 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field2><field3 name="Enter Input Load (default=1.0e-12)">1.0e-12</field3></u23><u24 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field4><field5 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field5><field6 name="Enter Input Load (default=1.0e-12)">1.0e-12</field6></u24><u36 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field7><field8 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field8><field9 name="Enter Input Load (default=1.0e-12)">1.0e-12</field9></u36><u40 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field10><field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field11><field12 name="Enter Input Load (default=1.0e-12)">1.0e-12</field12></u40><u26 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field13><field14 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field14><field15 name="Enter Input Load (default=1.0e-12)">1.0e-12</field15></u26><u16 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field16><field17 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field17><field18 name="Enter Input Load (default=1.0e-12)">1.0e-12</field18></u16><u27 name="type">d_buffer<field19 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field19><field20 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field20><field21 name="Enter Input Load (default=1.0e-12)">1.0e-12</field21></u27><u29 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field22><field23 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field23><field24 name="Enter Input Load (default=1.0e-12)">1.0e-12</field24></u29><u35 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field25><field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field26><field27 name="Enter Input Load (default=1.0e-12)">1.0e-12</field27></u35><u39 name="type">d_xor<field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field28><field29 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field29><field30 name="Enter Input Load (default=1.0e-12)">1.0e-12</field30></u39><u21 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field31><field32 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field32><field33 name="Enter Input Load (default=1.0e-12)">1.0e-12</field33></u21><u15 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field34><field35 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field35><field36 name="Enter Input Load (default=1.0e-12)">1.0e-12</field36></u15><u22 name="type">d_buffer<field37 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field37><field38 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field38><field39 name="Enter Input Load (default=1.0e-12)">1.0e-12</field39></u22><u28 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field40><field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field41><field42 name="Enter Input Load (default=1.0e-12)">1.0e-12</field42></u28><u30 name="type">d_or<field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field43><field44 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field44><field45 name="Enter Input Load (default=1.0e-12)">1.0e-12</field45></u30><u33 name="type">d_or<field46 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field46><field47 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field47><field48 name="Enter Input Load (default=1.0e-12)">1.0e-12</field48></u33><u41 name="type">d_xor<field49 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field49><field50 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field50><field51 name="Enter Input Load (default=1.0e-12)">1.0e-12</field51></u41><u17 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field52><field53 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field53><field54 name="Enter Input Load (default=1.0e-12)">1.0e-12</field54></u17><u13 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field55><field56 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field56><field57 name="Enter Input Load (default=1.0e-12)">1.0e-12</field57></u13><u18 name="type">d_buffer<field58 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field58><field59 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field59><field60 name="Enter Input Load (default=1.0e-12)">1.0e-12</field60></u18><u25 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field61><field62 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field62><field63 name="Enter Input Load (default=1.0e-12)">1.0e-12</field63></u25><u19 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field64><field65 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field65><field66 name="Enter Input Load (default=1.0e-12)">1.0e-12</field66></u19><u14 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field67><field68 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field68><field69 name="Enter Input Load (default=1.0e-12)">1.0e-12</field69></u14><u34 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field70><field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field71><field72 name="Enter Input Load (default=1.0e-12)">1.0e-12</field72></u34><u38 name="type">d_xor<field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field73><field74 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field74><field75 name="Enter Input Load (default=1.0e-12)">1.0e-12</field75></u38><u32 name="type">d_xor<field76 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field76><field77 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field77><field78 name="Enter Input Load (default=1.0e-12)">1.0e-12</field78></u32><u31 name="type">d_or<field79 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field79><field80 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field80><field81 name="Enter Input Load (default=1.0e-12)">1.0e-12</field81></u31><u20 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field82><field83 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field83><field84 name="Enter Input Load (default=1.0e-12)">1.0e-12</field84></u20><u37 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field85><field86 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field86><field87 name="Enter Input Load (default=1.0e-12)">1.0e-12</field87></u37><u11 name="type">d_nand<field88 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field88><field89 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field89><field90 name="Enter Input Load (default=1.0e-12)">1.0e-12</field90></u11><u12 name="type">d_nor<field91 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field91><field92 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field92><field93 name="Enter Input Load (default=1.0e-12)">1.0e-12</field93></u12><u8 name="type">d_nand<field94 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field94><field95 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field95><field96 name="Enter Input Load (default=1.0e-12)">1.0e-12</field96></u8><u9 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field97><field98 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field98><field99 name="Enter Input Load (default=1.0e-12)">1.0e-12</field99></u9><u4 name="type">d_nand<field100 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field100><field101 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field101><field102 name="Enter Input Load (default=1.0e-12)">1.0e-12</field102></u4><u5 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field103><field104 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field104><field105 name="Enter Input Load (default=1.0e-12)">1.0e-12</field105></u5><u6 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field106><field107 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field107><field108 name="Enter Input Load (default=1.0e-12)">1.0e-12</field108></u6><u7 name="type">d_nor<field109 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field109><field110 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field110><field111 name="Enter Input Load (default=1.0e-12)">1.0e-12</field111></u7><u10 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field112><field113 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field113><field114 name="Enter Input Load (default=1.0e-12)">1.0e-12</field114></u10><u2 name="type">adc_bridge<field115 name="Enter value for in_low (default=1.0)">1.0</field115><field116 name="Enter value for in_high (default=2.0)">2.0</field116><field117 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field117><field118 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field118></u2><u3 name="type">adc_bridge<field119 name="Enter value for in_low (default=1.0)">1.0</field119><field120 name="Enter value for in_high (default=2.0)">2.0</field120><field121 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field121><field122 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field122></u3><u42 name="type">dac_bridge<field123 name="Enter value for out_low (default=0.0)">0.0</field123><field124 name="Enter value for out_high (default=5.0)">5.0</field124><field125 name="Enter value for out_undef (default=0.5)">0.5</field125><field126 name="Enter value for input load (default=1.0e-12)">1.0e-12</field126><field127 name="Enter the Rise Time (default=1.0e-9)">1.0e-9</field127><field128 name="Enter the Fall Time (default=1.0e-9)">1.0e-9</field128></u42></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x8><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x7><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3></subcircuit></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7483A_sub/analysis b/library/SubcircuitLibrary/SN7483A_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm102_sub/D.lib b/library/SubcircuitLibrary/lm102_sub/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/lm102_sub/NPN.lib b/library/SubcircuitLibrary/lm102_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/lm102_sub/PNP.lib b/library/SubcircuitLibrary/lm102_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/lm102_sub/analysis b/library/SubcircuitLibrary/lm102_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib b/library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib
new file mode 100644
index 00000000..c751ab9b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib
@@ -0,0 +1,162 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir
new file mode 100644
index 00000000..1ab6c226
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir
@@ -0,0 +1,51 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\lm102_sub\lm102_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 30/05/2024 11:41:12 AM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_NPN
+Q5 Net-_C1-Pad1_ Net-_Q10-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+Q2 Net-_Q15-Pad2_ Net-_Q1-Pad1_ Net-_Q10-Pad2_ eSim_PNP
+R5 Net-_Q1-Pad3_ Net-_Q5-Pad3_ 6k
+R12 Net-_Q1-Pad3_ Net-_Q10-Pad3_ 3k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q15 Net-_Q12-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+R15 Net-_Q1-Pad3_ Net-_Q15-Pad3_ 270
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_D1-Pad1_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q10-Pad1_ eSim_NPN
+Q9 Net-_D1-Pad2_ Net-_Q8-Pad3_ Net-_Q11-Pad3_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q8 Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q8-Pad3_ eSim_NPN
+Q14 Net-_Q11-Pad1_ Net-_C2-Pad2_ Net-_Q11-Pad2_ eSim_NPN
+R10 Net-_Q13-Pad1_ Net-_Q8-Pad3_ 80k
+R13 Net-_Q13-Pad1_ Net-_Q11-Pad2_ 80k
+R14 Net-_C2-Pad2_ Net-_Q12-Pad1_ 3k
+R17 Net-_Q12-Pad1_ Net-_D1-Pad2_ 250
+R16 Net-_D1-Pad2_ Net-_Q16-Pad2_ 4k
+Q16 Net-_C2-Pad1_ Net-_Q16-Pad2_ Net-_Q11-Pad1_ eSim_NPN
+Q18 Net-_Q18-Pad1_ Net-_C2-Pad1_ Net-_Q16-Pad2_ eSim_NPN
+Q19 Net-_Q18-Pad1_ Net-_Q16-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q17 Net-_C2-Pad1_ Net-_D1-Pad2_ Net-_Q12-Pad1_ eSim_NPN
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 20pF
+Q6 Net-_C1-Pad1_ Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_PNP
+Q7 Net-_C2-Pad1_ Net-_Q6-Pad2_ Net-_Q7-Pad3_ eSim_PNP
+R3 Net-_R3-Pad1_ Net-_Q18-Pad1_ 500
+R8 Net-_R8-Pad1_ Net-_Q18-Pad1_ 500
+R9 Net-_Q7-Pad3_ Net-_R8-Pad1_ 1k
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+R4 Net-_Q6-Pad3_ Net-_R3-Pad1_ 1k
+R11 Net-_Q10-Pad1_ Net-_Q11-Pad3_ 200
+R1 Net-_Q10-Pad2_ Net-_Q3-Pad3_ 10K
+U2 Net-_U2-PadIN_ Net-_Q6-Pad2_ zener
+U3 Net-_C1-Pad2_ Net-_U2-PadIN_ zener
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10pF
+R6 Net-_Q3-Pad3_ Net-_C1-Pad2_ 2k
+Q4 Net-_Q18-Pad1_ Net-_C1-Pad1_ Net-_Q3-Pad2_ eSim_NPN
+Q3 Net-_Q18-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+R2 Net-_Q3-Pad3_ Net-_Q3-Pad2_ 4k
+U1 Net-_R3-Pad1_ Net-_R8-Pad1_ Net-_D1-Pad1_ Net-_Q1-Pad3_ Net-_Q15-Pad3_ Net-_Q12-Pad1_ Net-_Q18-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out
new file mode 100644
index 00000000..91abf6b9
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out
@@ -0,0 +1,61 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm102_sub\lm102_sub.cir
+
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222
+q5 net-_c1-pad1_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222
+q2 net-_q15-pad2_ net-_q1-pad1_ net-_q10-pad2_ Q2N2907A
+r5 net-_q1-pad3_ net-_q5-pad3_ 6k
+r12 net-_q1-pad3_ net-_q10-pad3_ 3k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q15 net-_q12-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222
+r15 net-_q1-pad3_ net-_q15-pad3_ 270
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_d1-pad1_ Q2N2222
+q13 net-_q13-pad1_ net-_q13-pad1_ net-_q10-pad1_ Q2N2222
+q9 net-_d1-pad2_ net-_q8-pad3_ net-_q11-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q8 net-_d1-pad2_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+q14 net-_q11-pad1_ net-_c2-pad2_ net-_q11-pad2_ Q2N2222
+r10 net-_q13-pad1_ net-_q8-pad3_ 200k
+r13 net-_q13-pad1_ net-_q11-pad2_ 200k
+r14 net-_c2-pad2_ net-_q12-pad1_ 3k
+r17 net-_q12-pad1_ net-_d1-pad2_ 246
+r16 net-_d1-pad2_ net-_q16-pad2_ 3k
+q16 net-_c2-pad1_ net-_q16-pad2_ net-_q11-pad1_ Q2N2222
+q18 net-_q18-pad1_ net-_c2-pad1_ net-_q16-pad2_ Q2N2222
+q19 net-_q18-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222
+q17 net-_c2-pad1_ net-_d1-pad2_ net-_q12-pad1_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 20pf
+q6 net-_c1-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2907A
+q7 net-_c2-pad1_ net-_q6-pad2_ net-_q7-pad3_ Q2N2907A
+r3 net-_r3-pad1_ net-_q18-pad1_ 500
+r8 net-_r8-pad1_ net-_q18-pad1_ 500
+r9 net-_q7-pad3_ net-_r8-pad1_ 1k
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r4 net-_q6-pad3_ net-_r3-pad1_ 1k
+r11 net-_q10-pad1_ net-_q11-pad3_ 200
+r1 net-_q10-pad2_ net-_q3-pad3_ 10k
+* u2 net-_u2-padin_ net-_q6-pad2_ zener
+* u3 net-_c1-pad2_ net-_u2-padin_ zener
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r6 net-_q3-pad3_ net-_c1-pad2_ 2k
+q4 net-_q18-pad1_ net-_c1-pad1_ net-_q3-pad2_ Q2N2222
+q3 net-_q18-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r2 net-_q3-pad3_ net-_q3-pad2_ 4k
+* u1 net-_r3-pad1_ net-_r8-pad1_ net-_d1-pad1_ net-_q1-pad3_ net-_q15-pad3_ net-_q12-pad1_ net-_q18-pad1_ port
+a1 net-_u2-padin_ net-_q6-pad2_ u2
+a2 net-_c1-pad2_ net-_u2-padin_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.pro b/library/SubcircuitLibrary/lm102_sub/lm102_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.sch b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sch
new file mode 100644
index 00000000..b9c59ddf
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sch
@@ -0,0 +1,801 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:lm102_sub-cache
+EELAYER 25 0
+EELAYER END
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+F 0 "U1" H 1400 3050 30 0000 C CNN
+F 1 "PORT" H 1350 2950 30 0000 C CNN
+F 2 "" H 1350 2950 60 0000 C CNN
+F 3 "" H 1350 2950 60 0000 C CNN
+ 3 1350 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4700 5100 4700 6650
+Wire Wire Line
+ 1650 6100 1650 6600
+Wire Wire Line
+ 2600 6000 2600 6650
+Wire Wire Line
+ 2300 5800 1950 5800
+Wire Wire Line
+ 1950 4050 1950 5900
+Wire Wire Line
+ 1350 6800 1350 6100
+Wire Wire Line
+ 1350 6100 1650 6100
+Connection ~ 1950 5800
+Wire Wire Line
+ 1650 7050 1650 7000
+Wire Wire Line
+ 2600 7050 2600 6950
+Connection ~ 1650 7050
+Wire Wire Line
+ 2600 1350 2600 1400
+Wire Wire Line
+ 3500 1400 3500 1350
+Wire Wire Line
+ 2900 1600 3200 1600
+Connection ~ 3050 1600
+Connection ~ 3500 1800
+Wire Wire Line
+ 4700 7050 4700 6950
+Connection ~ 2600 7050
+Wire Wire Line
+ 4400 4900 1950 4900
+Connection ~ 1950 4900
+Wire Wire Line
+ 1950 6300 6250 6300
+Wire Wire Line
+ 6550 6500 6550 6650
+Connection ~ 4700 7050
+Wire Wire Line
+ 7000 4600 5600 4600
+Wire Wire Line
+ 6550 4600 6550 6100
+Wire Wire Line
+ 5400 4900 5900 4900
+Wire Wire Line
+ 5900 4900 5900 4600
+Connection ~ 5900 4600
+Wire Wire Line
+ 4700 3850 4700 3550
+Wire Wire Line
+ 4250 3700 4250 3750
+Wire Wire Line
+ 4250 3750 5600 3750
+Wire Wire Line
+ 5600 3700 5600 3900
+Wire Wire Line
+ 5300 4100 5300 3750
+Connection ~ 5300 3750
+Connection ~ 5600 3750
+Wire Wire Line
+ 5150 3550 5150 3650
+Wire Wire Line
+ 5150 3650 4700 3650
+Connection ~ 4700 3650
+Wire Wire Line
+ 4250 3400 4250 3150
+Wire Wire Line
+ 4400 3350 4250 3350
+Connection ~ 4250 3350
+Wire Wire Line
+ 5600 3400 5600 3150
+Wire Wire Line
+ 5450 3350 5600 3350
+Connection ~ 5600 3350
+Wire Wire Line
+ 4700 4150 4700 4700
+Wire Wire Line
+ 5600 4300 4700 4300
+Connection ~ 4700 4300
+Wire Wire Line
+ 5200 4600 3500 4600
+Wire Wire Line
+ 3500 4600 3500 2550
+Wire Wire Line
+ 3500 2550 3750 2550
+Connection ~ 3500 2950
+Wire Wire Line
+ 3500 1800 7150 1800
+Wire Wire Line
+ 5900 1800 5900 1850
+Wire Wire Line
+ 6550 1800 6550 1850
+Connection ~ 5900 1800
+Wire Wire Line
+ 5150 2750 6550 2750
+Wire Wire Line
+ 6550 2750 6550 2250
+Connection ~ 6550 1800
+Wire Wire Line
+ 5900 2950 6300 2950
+Wire Wire Line
+ 5900 2150 5900 2900
+Wire Wire Line
+ 5900 2900 6000 2900
+Wire Wire Line
+ 6000 2900 6000 2950
+Connection ~ 6000 2950
+Wire Wire Line
+ 7450 2000 7450 2400
+Wire Wire Line
+ 7450 2700 7450 3000
+Wire Wire Line
+ 6600 2950 6750 2950
+Wire Wire Line
+ 6750 2950 6750 3400
+Wire Wire Line
+ 6750 3400 8100 3400
+Wire Wire Line
+ 7450 3300 7450 3400
+Connection ~ 7450 3400
+Wire Wire Line
+ 7000 3150 7000 4600
+Connection ~ 7000 3400
+Connection ~ 6550 4600
+Wire Wire Line
+ 7300 2950 7450 2950
+Connection ~ 7450 2950
+Wire Wire Line
+ 7000 2750 7000 1800
+Connection ~ 7000 1800
+Wire Wire Line
+ 6850 2050 7550 2050
+Connection ~ 7450 2050
+Wire Wire Line
+ 4050 2550 7200 2550
+Wire Wire Line
+ 7200 2550 7200 2750
+Wire Wire Line
+ 7200 2750 7850 2750
+Connection ~ 7450 2750
+Wire Wire Line
+ 7850 2750 7850 2250
+Wire Wire Line
+ 4250 2750 4250 2550
+Connection ~ 4250 2550
+Wire Wire Line
+ 4700 3150 4700 2550
+Connection ~ 4700 2550
+Wire Wire Line
+ 5150 3150 5150 2750
+Connection ~ 5600 2750
+Wire Wire Line
+ 7450 850 7450 1600
+Connection ~ 7450 850
+Wire Wire Line
+ 7850 850 7850 1850
+Connection ~ 7850 850
+Connection ~ 6550 7050
+Wire Wire Line
+ 6850 6550 6550 6550
+Connection ~ 6550 6550
+Wire Wire Line
+ 2600 1050 2600 950
+Wire Wire Line
+ 3500 1050 3500 950
+Wire Wire Line
+ 2600 1000 2900 1000
+Wire Wire Line
+ 2900 1000 2900 550
+Connection ~ 2600 1000
+Wire Wire Line
+ 3500 1000 3200 1000
+Wire Wire Line
+ 3200 1000 3200 550
+Connection ~ 3500 1000
+Wire Wire Line
+ 1950 650 3750 650
+Connection ~ 2600 650
+Wire Wire Line
+ 3750 650 3750 850
+Connection ~ 3500 650
+Wire Wire Line
+ 1650 7050 6550 7050
+Wire Wire Line
+ 3050 2700 3000 2700
+Wire Wire Line
+ 3050 1650 3050 1600
+Wire Wire Line
+ 3050 2200 3050 2150
+Wire Wire Line
+ 2600 1800 2600 5600
+Wire Wire Line
+ 3050 2700 3050 2850
+Wire Wire Line
+ 3050 2850 3000 2850
+Wire Wire Line
+ 2700 2850 1950 2850
+Connection ~ 1950 2850
+Wire Wire Line
+ 1950 2250 1950 3750
+Wire Wire Line
+ 2250 2000 2250 2250
+Connection ~ 2250 2050
+Wire Wire Line
+ 2250 2550 2250 2850
+Connection ~ 2250 2850
+Wire Wire Line
+ 1950 1850 1950 650
+Wire Wire Line
+ 2250 1600 1950 1600
+Connection ~ 1950 1600
+Wire Wire Line
+ 2700 2700 2600 2700
+Connection ~ 2600 2700
+Wire Wire Line
+ 2550 1800 2600 1800
+Wire Wire Line
+ 3750 850 8150 850
+Wire Wire Line
+ 6550 6950 6550 7150
+Wire Wire Line
+ 1600 2950 3950 2950
+Wire Wire Line
+ 3200 550 3550 550
+Wire Wire Line
+ 2900 550 2550 550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.sub b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sub
new file mode 100644
index 00000000..8a4eee3b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sub
@@ -0,0 +1,55 @@
+* Subcircuit lm102_sub
+.subckt lm102_sub net-_r3-pad1_ net-_r8-pad1_ net-_d1-pad1_ net-_q1-pad3_ net-_q15-pad3_ net-_q12-pad1_ net-_q18-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm102_sub\lm102_sub.cir
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222
+q5 net-_c1-pad1_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222
+q2 net-_q15-pad2_ net-_q1-pad1_ net-_q10-pad2_ Q2N2907A
+r5 net-_q1-pad3_ net-_q5-pad3_ 6k
+r12 net-_q1-pad3_ net-_q10-pad3_ 3k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q15 net-_q12-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222
+r15 net-_q1-pad3_ net-_q15-pad3_ 270
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_d1-pad1_ Q2N2222
+q13 net-_q13-pad1_ net-_q13-pad1_ net-_q10-pad1_ Q2N2222
+q9 net-_d1-pad2_ net-_q8-pad3_ net-_q11-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q8 net-_d1-pad2_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+q14 net-_q11-pad1_ net-_c2-pad2_ net-_q11-pad2_ Q2N2222
+r10 net-_q13-pad1_ net-_q8-pad3_ 200k
+r13 net-_q13-pad1_ net-_q11-pad2_ 200k
+r14 net-_c2-pad2_ net-_q12-pad1_ 3k
+r17 net-_q12-pad1_ net-_d1-pad2_ 246
+r16 net-_d1-pad2_ net-_q16-pad2_ 3k
+q16 net-_c2-pad1_ net-_q16-pad2_ net-_q11-pad1_ Q2N2222
+q18 net-_q18-pad1_ net-_c2-pad1_ net-_q16-pad2_ Q2N2222
+q19 net-_q18-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222
+q17 net-_c2-pad1_ net-_d1-pad2_ net-_q12-pad1_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 20pf
+q6 net-_c1-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2907A
+q7 net-_c2-pad1_ net-_q6-pad2_ net-_q7-pad3_ Q2N2907A
+r3 net-_r3-pad1_ net-_q18-pad1_ 500
+r8 net-_r8-pad1_ net-_q18-pad1_ 500
+r9 net-_q7-pad3_ net-_r8-pad1_ 1k
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r4 net-_q6-pad3_ net-_r3-pad1_ 1k
+r11 net-_q10-pad1_ net-_q11-pad3_ 200
+r1 net-_q10-pad2_ net-_q3-pad3_ 10k
+* u2 net-_u2-padin_ net-_q6-pad2_ zener
+* u3 net-_c1-pad2_ net-_u2-padin_ zener
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r6 net-_q3-pad3_ net-_c1-pad2_ 2k
+q4 net-_q18-pad1_ net-_c1-pad1_ net-_q3-pad2_ Q2N2222
+q3 net-_q18-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r2 net-_q3-pad3_ net-_q3-pad2_ 4k
+a1 net-_u2-padin_ net-_q6-pad2_ u2
+a2 net-_c1-pad2_ net-_u2-padin_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends lm102_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml b/library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml
new file mode 100644
index 00000000..04d007d7
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u3></model><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm110_sub/D.lib b/library/SubcircuitLibrary/lm110_sub/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/lm110_sub/NJF.lib b/library/SubcircuitLibrary/lm110_sub/NJF.lib
new file mode 100644
index 00000000..dbb2cbae
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/NJF.lib
@@ -0,0 +1,4 @@
+.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++ Af=1)
diff --git a/library/SubcircuitLibrary/lm110_sub/NPN.lib b/library/SubcircuitLibrary/lm110_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/lm110_sub/PNP.lib b/library/SubcircuitLibrary/lm110_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/lm110_sub/analysis b/library/SubcircuitLibrary/lm110_sub/analysis
new file mode 100644
index 00000000..9d6c62c3
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/analysis
@@ -0,0 +1 @@
+.tran 0.001e-00 0.1e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm110_sub/lm110_sub-cache.lib b/library/SubcircuitLibrary/lm110_sub/lm110_sub-cache.lib
new file mode 100644
index 00000000..5b1e78bd
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/lm110_sub-cache.lib
@@ -0,0 +1,165 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NJF
+#
+DEF eSim_NJF J 0 0 Y N 1 F N
+F0 "J" -100 50 50 H V R CNN
+F1 "eSim_NJF" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS jfet_n
+DRAW
+C 50 0 111 0 1 10 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 3 0 1 0 100 -100 100 -50 10 -50 N
+P 3 0 1 0 100 100 100 55 10 55 N
+P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 210 R 50 50 1 1 P
+X S 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/lm110_sub/lm110_sub.cir b/library/SubcircuitLibrary/lm110_sub/lm110_sub.cir
new file mode 100644
index 00000000..16563df8
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/lm110_sub.cir
@@ -0,0 +1,45 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\lm110_sub\lm110_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 30/05/2024 10:59:26 AM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad2_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_J1-Pad3_ Net-_Q3-Pad3_ eSim_NPN
+Q2 Net-_Q14-Pad2_ Net-_Q1-Pad1_ Net-_J1-Pad3_ eSim_PNP
+R2 Net-_J1-Pad2_ Net-_Q3-Pad3_ 3k
+R8 Net-_J1-Pad2_ Net-_Q9-Pad3_ 1.5k
+Q9 Net-_Q12-Pad3_ Net-_J1-Pad3_ Net-_Q9-Pad3_ eSim_NPN
+Q14 Net-_Q11-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN
+R11 Net-_J1-Pad2_ Net-_Q14-Pad3_ 200
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad1_ Net-_D1-Pad1_ eSim_NPN
+J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN
+Q8 Net-_D1-Pad2_ Net-_Q7-Pad3_ Net-_Q10-Pad3_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q7 Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q7-Pad3_ eSim_NPN
+Q13 Net-_Q10-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN
+R6 Net-_Q12-Pad1_ Net-_Q7-Pad3_ 200k
+R9 Net-_Q12-Pad1_ Net-_Q10-Pad2_ 200k
+R10 Net-_C1-Pad2_ Net-_Q11-Pad1_ 5k
+R13 Net-_Q11-Pad1_ Net-_D1-Pad2_ 25
+R12 Net-_D1-Pad2_ Net-_Q15-Pad2_ 3k
+Q15 Net-_C1-Pad1_ Net-_Q15-Pad2_ Net-_Q10-Pad1_ eSim_NPN
+Q17 Net-_J1-Pad1_ Net-_C1-Pad1_ Net-_Q15-Pad2_ eSim_NPN
+Q18 Net-_J1-Pad1_ Net-_Q15-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q16 Net-_C1-Pad1_ Net-_D1-Pad2_ Net-_Q11-Pad1_ eSim_NPN
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10pF
+Q4 Net-_Q3-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_PNP
+Q5 Net-_Q4-Pad2_ Net-_Q4-Pad2_ Net-_Q5-Pad3_ eSim_PNP
+Q6 Net-_C1-Pad1_ Net-_Q3-Pad1_ Net-_Q4-Pad2_ eSim_PNP
+R3 Net-_R1-Pad2_ Net-_J1-Pad1_ 500
+R4 Net-_J1-Pad1_ Net-_R4-Pad2_ 500
+R5 Net-_Q5-Pad3_ Net-_R4-Pad2_ 1k
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+R1 Net-_Q4-Pad3_ Net-_R1-Pad2_ 1k
+R7 Net-_Q12-Pad3_ Net-_Q10-Pad3_ 150
+U1 Net-_R1-Pad2_ Net-_R4-Pad2_ Net-_D1-Pad1_ Net-_J1-Pad2_ Net-_Q14-Pad3_ Net-_Q11-Pad1_ Net-_J1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/lm110_sub/lm110_sub.cir.out b/library/SubcircuitLibrary/lm110_sub/lm110_sub.cir.out
new file mode 100644
index 00000000..a9ad359d
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/lm110_sub.cir.out
@@ -0,0 +1,50 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm110_sub\lm110_sub.cir
+
+.include NJF.lib
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad2_ Q2N2222
+q3 net-_q3-pad1_ net-_j1-pad3_ net-_q3-pad3_ Q2N2222
+q2 net-_q14-pad2_ net-_q1-pad1_ net-_j1-pad3_ Q2N2907A
+r2 net-_j1-pad2_ net-_q3-pad3_ 3k
+r8 net-_j1-pad2_ net-_q9-pad3_ 1.5k
+q9 net-_q12-pad3_ net-_j1-pad3_ net-_q9-pad3_ Q2N2222
+q14 net-_q11-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222
+r11 net-_j1-pad2_ net-_q14-pad3_ 200
+q11 net-_q11-pad1_ net-_q11-pad1_ net-_d1-pad1_ Q2N2222
+j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2222
+q8 net-_d1-pad2_ net-_q7-pad3_ net-_q10-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q7 net-_d1-pad2_ net-_d1-pad1_ net-_q7-pad3_ Q2N2222
+q13 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222
+r6 net-_q12-pad1_ net-_q7-pad3_ 200k
+r9 net-_q12-pad1_ net-_q10-pad2_ 200k
+r10 net-_c1-pad2_ net-_q11-pad1_ 5k
+r13 net-_q11-pad1_ net-_d1-pad2_ 25
+r12 net-_d1-pad2_ net-_q15-pad2_ 3k
+q15 net-_c1-pad1_ net-_q15-pad2_ net-_q10-pad1_ Q2N2222
+q17 net-_j1-pad1_ net-_c1-pad1_ net-_q15-pad2_ Q2N2222
+q18 net-_j1-pad1_ net-_q15-pad2_ net-_d1-pad2_ Q2N2222
+q16 net-_c1-pad1_ net-_d1-pad2_ net-_q11-pad1_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+q4 net-_q3-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A
+q5 net-_q4-pad2_ net-_q4-pad2_ net-_q5-pad3_ Q2N2907A
+q6 net-_c1-pad1_ net-_q3-pad1_ net-_q4-pad2_ Q2N2907A
+r3 net-_r1-pad2_ net-_j1-pad1_ 500
+r4 net-_j1-pad1_ net-_r4-pad2_ 500
+r5 net-_q5-pad3_ net-_r4-pad2_ 1k
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r1 net-_q4-pad3_ net-_r1-pad2_ 1k
+r7 net-_q12-pad3_ net-_q10-pad3_ 150
+* u1 net-_r1-pad2_ net-_r4-pad2_ net-_d1-pad1_ net-_j1-pad2_ net-_q14-pad3_ net-_q11-pad1_ net-_j1-pad1_ port
+.tran 0.001e-00 0.1e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/lm110_sub/lm110_sub.pro b/library/SubcircuitLibrary/lm110_sub/lm110_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/lm110_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/lm110_sub/lm110_sub.sch b/library/SubcircuitLibrary/lm110_sub/lm110_sub.sch
new file mode 100644
index 00000000..8046fe1f
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/lm110_sub.sch
@@ -0,0 +1,707 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:lm110_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
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+Date ""
+Rev ""
+Comp ""
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+Comment3 ""
+Comment4 ""
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+ 1 3900 2550
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+ 1 2650 1250
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+F 1 "150" H 4800 4000 50 0000 C CNN
+F 2 "" H 4800 4030 30 0000 C CNN
+F 3 "" V 4800 4100 30 0000 C CNN
+ 1 4750 4050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 4 1 66506B5A
+P 6550 7450
+F 0 "U1" H 6600 7550 30 0000 C CNN
+F 1 "PORT" H 6550 7450 30 0000 C CNN
+F 2 "" H 6550 7450 60 0000 C CNN
+F 3 "" H 6550 7450 60 0000 C CNN
+ 4 6550 7450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 5 1 66506BD3
+P 7100 6550
+F 0 "U1" H 7150 6650 30 0000 C CNN
+F 1 "PORT" H 7100 6550 30 0000 C CNN
+F 2 "" H 7100 6550 60 0000 C CNN
+F 3 "" H 7100 6550 60 0000 C CNN
+ 5 7100 6550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 66507118
+P 8350 3400
+F 0 "U1" H 8400 3500 30 0000 C CNN
+F 1 "PORT" H 8350 3400 30 0000 C CNN
+F 2 "" H 8350 3400 60 0000 C CNN
+F 3 "" H 8350 3400 60 0000 C CNN
+ 6 8350 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6650739F
+P 8400 850
+F 0 "U1" H 8450 950 30 0000 C CNN
+F 1 "PORT" H 8400 850 30 0000 C CNN
+F 2 "" H 8400 850 60 0000 C CNN
+F 3 "" H 8400 850 60 0000 C CNN
+ 7 8400 850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 66507622
+P 1250 2950
+F 0 "U1" H 1300 3050 30 0000 C CNN
+F 1 "PORT" H 1250 2950 30 0000 C CNN
+F 2 "" H 1250 2950 60 0000 C CNN
+F 3 "" H 1250 2950 60 0000 C CNN
+ 3 1250 2950
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 66507B04
+P 2350 700
+F 0 "U1" H 2400 800 30 0000 C CNN
+F 1 "PORT" H 2350 700 30 0000 C CNN
+F 2 "" H 2350 700 60 0000 C CNN
+F 3 "" H 2350 700 60 0000 C CNN
+ 1 2350 700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4700 5100 4700 6650
+Wire Wire Line
+ 1650 6100 1650 6600
+Wire Wire Line
+ 2600 6000 2600 6650
+Wire Wire Line
+ 2300 5800 1950 5800
+Wire Wire Line
+ 1950 4050 1950 5900
+Wire Wire Line
+ 1350 6800 1350 6100
+Wire Wire Line
+ 1350 6100 1650 6100
+Wire Wire Line
+ 2600 1800 2600 5600
+Connection ~ 1950 5800
+Wire Wire Line
+ 1650 3850 1200 3850
+Wire Wire Line
+ 1200 3850 1200 7050
+Wire Wire Line
+ 1200 7050 6550 7050
+Wire Wire Line
+ 1650 7050 1650 7000
+Wire Wire Line
+ 2600 7050 2600 6950
+Connection ~ 1650 7050
+Wire Wire Line
+ 2950 1050 3150 1050
+Wire Wire Line
+ 2600 1050 2650 1050
+Wire Wire Line
+ 2600 1350 2600 1400
+Wire Wire Line
+ 3500 1400 3500 1350
+Wire Wire Line
+ 3500 1050 3450 1050
+Wire Wire Line
+ 2900 1600 3200 1600
+Wire Wire Line
+ 3050 1800 3600 1800
+Wire Wire Line
+ 3050 1800 3050 1600
+Connection ~ 3050 1600
+Connection ~ 3500 1800
+Wire Wire Line
+ 3050 850 3050 1050
+Connection ~ 3050 1050
+Wire Wire Line
+ 1950 850 1950 3650
+Wire Wire Line
+ 3800 2100 2600 2100
+Connection ~ 2600 2100
+Wire Wire Line
+ 4700 7050 4700 6950
+Connection ~ 2600 7050
+Wire Wire Line
+ 4400 4900 1950 4900
+Connection ~ 1950 4900
+Wire Wire Line
+ 1950 6300 6250 6300
+Wire Wire Line
+ 6550 6500 6550 6650
+Connection ~ 4700 7050
+Wire Wire Line
+ 7000 4600 5600 4600
+Wire Wire Line
+ 6550 4600 6550 6100
+Wire Wire Line
+ 5400 4900 5900 4900
+Wire Wire Line
+ 5900 4900 5900 4600
+Connection ~ 5900 4600
+Wire Wire Line
+ 4700 3850 4700 3550
+Wire Wire Line
+ 4250 3700 4250 3750
+Wire Wire Line
+ 4250 3750 5600 3750
+Wire Wire Line
+ 5600 3700 5600 3900
+Wire Wire Line
+ 5300 4100 5300 3750
+Connection ~ 5300 3750
+Connection ~ 5600 3750
+Wire Wire Line
+ 5150 3550 5150 3650
+Wire Wire Line
+ 5150 3650 4700 3650
+Connection ~ 4700 3650
+Wire Wire Line
+ 4250 3400 4250 3150
+Wire Wire Line
+ 4400 3350 4250 3350
+Connection ~ 4250 3350
+Wire Wire Line
+ 5600 3400 5600 3150
+Wire Wire Line
+ 5450 3350 5600 3350
+Connection ~ 5600 3350
+Wire Wire Line
+ 4700 4150 4700 4700
+Wire Wire Line
+ 5600 4300 4700 4300
+Connection ~ 4700 4300
+Wire Wire Line
+ 5200 4600 3500 4600
+Wire Wire Line
+ 3500 4600 3500 2550
+Wire Wire Line
+ 3500 2550 3750 2550
+Connection ~ 3500 2950
+Wire Wire Line
+ 4000 1800 7150 1800
+Wire Wire Line
+ 5900 1800 5900 1850
+Wire Wire Line
+ 6550 1800 6550 1850
+Connection ~ 5900 1800
+Wire Wire Line
+ 5150 2750 6550 2750
+Wire Wire Line
+ 6550 2750 6550 2250
+Connection ~ 6550 1800
+Wire Wire Line
+ 5900 2950 6300 2950
+Wire Wire Line
+ 5900 2150 5900 2900
+Wire Wire Line
+ 5900 2900 6000 2900
+Wire Wire Line
+ 6000 2900 6000 2950
+Connection ~ 6000 2950
+Wire Wire Line
+ 7450 2000 7450 2400
+Wire Wire Line
+ 7450 2700 7450 3000
+Wire Wire Line
+ 6600 2950 6750 2950
+Wire Wire Line
+ 6750 2950 6750 3400
+Wire Wire Line
+ 6750 3400 8100 3400
+Wire Wire Line
+ 7450 3300 7450 3400
+Connection ~ 7450 3400
+Wire Wire Line
+ 7000 3150 7000 4600
+Connection ~ 7000 3400
+Connection ~ 6550 4600
+Wire Wire Line
+ 7300 2950 7450 2950
+Connection ~ 7450 2950
+Wire Wire Line
+ 7000 2750 7000 1800
+Connection ~ 7000 1800
+Wire Wire Line
+ 6850 2050 7550 2050
+Connection ~ 7450 2050
+Wire Wire Line
+ 4050 2550 7200 2550
+Wire Wire Line
+ 7200 2550 7200 2750
+Wire Wire Line
+ 7200 2750 7850 2750
+Connection ~ 7450 2750
+Wire Wire Line
+ 7850 2750 7850 2250
+Wire Wire Line
+ 4250 2750 4250 2550
+Connection ~ 4250 2550
+Wire Wire Line
+ 4700 3150 4700 2550
+Connection ~ 4700 2550
+Wire Wire Line
+ 5150 3150 5150 2750
+Connection ~ 5600 2750
+Connection ~ 3050 850
+Wire Wire Line
+ 7450 850 7450 1600
+Connection ~ 7450 850
+Wire Wire Line
+ 7850 850 7850 1850
+Connection ~ 7850 850
+Connection ~ 6550 7050
+Wire Wire Line
+ 6850 6550 6550 6550
+Connection ~ 6550 6550
+Wire Wire Line
+ 2600 1050 2600 700
+Wire Wire Line
+ 3500 700 3500 1050
+Wire Wire Line
+ 6550 6950 6550 7200
+$Comp
+L PORT U1
+U 2 1 6657A824
+P 3750 700
+F 0 "U1" H 3800 800 30 0000 C CNN
+F 1 "PORT" H 3750 700 30 0000 C CNN
+F 2 "" H 3750 700 60 0000 C CNN
+F 3 "" H 3750 700 60 0000 C CNN
+ 2 3750 700
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1950 850 8150 850
+Wire Wire Line
+ 1500 2950 3950 2950
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/lm110_sub/lm110_sub.sub b/library/SubcircuitLibrary/lm110_sub/lm110_sub.sub
new file mode 100644
index 00000000..4e48accb
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/lm110_sub.sub
@@ -0,0 +1,44 @@
+* Subcircuit lm110_sub
+.subckt lm110_sub net-_r1-pad2_ net-_r4-pad2_ net-_d1-pad1_ net-_j1-pad2_ net-_q14-pad3_ net-_q11-pad1_ net-_j1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm110_sub\lm110_sub.cir
+.include NJF.lib
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad2_ Q2N2222
+q3 net-_q3-pad1_ net-_j1-pad3_ net-_q3-pad3_ Q2N2222
+q2 net-_q14-pad2_ net-_q1-pad1_ net-_j1-pad3_ Q2N2907A
+r2 net-_j1-pad2_ net-_q3-pad3_ 3k
+r8 net-_j1-pad2_ net-_q9-pad3_ 1.5k
+q9 net-_q12-pad3_ net-_j1-pad3_ net-_q9-pad3_ Q2N2222
+q14 net-_q11-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222
+r11 net-_j1-pad2_ net-_q14-pad3_ 200
+q11 net-_q11-pad1_ net-_q11-pad1_ net-_d1-pad1_ Q2N2222
+j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2222
+q8 net-_d1-pad2_ net-_q7-pad3_ net-_q10-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q7 net-_d1-pad2_ net-_d1-pad1_ net-_q7-pad3_ Q2N2222
+q13 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222
+r6 net-_q12-pad1_ net-_q7-pad3_ 200k
+r9 net-_q12-pad1_ net-_q10-pad2_ 200k
+r10 net-_c1-pad2_ net-_q11-pad1_ 5k
+r13 net-_q11-pad1_ net-_d1-pad2_ 25
+r12 net-_d1-pad2_ net-_q15-pad2_ 3k
+q15 net-_c1-pad1_ net-_q15-pad2_ net-_q10-pad1_ Q2N2222
+q17 net-_j1-pad1_ net-_c1-pad1_ net-_q15-pad2_ Q2N2222
+q18 net-_j1-pad1_ net-_q15-pad2_ net-_d1-pad2_ Q2N2222
+q16 net-_c1-pad1_ net-_d1-pad2_ net-_q11-pad1_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+q4 net-_q3-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A
+q5 net-_q4-pad2_ net-_q4-pad2_ net-_q5-pad3_ Q2N2907A
+q6 net-_c1-pad1_ net-_q3-pad1_ net-_q4-pad2_ Q2N2907A
+r3 net-_r1-pad2_ net-_j1-pad1_ 500
+r4 net-_j1-pad1_ net-_r4-pad2_ 500
+r5 net-_q5-pad3_ net-_r4-pad2_ 1k
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r1 net-_q4-pad3_ net-_r1-pad2_ 1k
+r7 net-_q12-pad3_ net-_q10-pad3_ 150
+* Control Statements
+
+.ends lm110_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm110_sub/lm110_sub_Previous_Values.xml b/library/SubcircuitLibrary/lm110_sub/lm110_sub_Previous_Values.xml
new file mode 100644
index 00000000..4f10264b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm110_sub/lm110_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><j1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.001</field2><field3 name="Stop Time">0.1</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm123_sub/NJF.lib b/library/SubcircuitLibrary/lm123_sub/NJF.lib
new file mode 100644
index 00000000..dbb2cbae
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/NJF.lib
@@ -0,0 +1,4 @@
+.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++ Af=1)
diff --git a/library/SubcircuitLibrary/lm123_sub/NPN.lib b/library/SubcircuitLibrary/lm123_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/lm123_sub/PNP.lib b/library/SubcircuitLibrary/lm123_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/lm123_sub/analysis b/library/SubcircuitLibrary/lm123_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm123_sub/lm123_sub-cache.lib b/library/SubcircuitLibrary/lm123_sub/lm123_sub-cache.lib
new file mode 100644
index 00000000..c28cbe9d
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/lm123_sub-cache.lib
@@ -0,0 +1,158 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NJF
+#
+DEF eSim_NJF J 0 0 Y N 1 F N
+F0 "J" -100 50 50 H V R CNN
+F1 "eSim_NJF" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS jfet_n
+DRAW
+C 50 0 111 0 1 10 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 3 0 1 0 100 -100 100 -50 10 -50 N
+P 3 0 1 0 100 100 100 55 10 55 N
+P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 210 R 50 50 1 1 P
+X S 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/lm123_sub/lm123_sub.cir b/library/SubcircuitLibrary/lm123_sub/lm123_sub.cir
new file mode 100644
index 00000000..c1a66832
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/lm123_sub.cir
@@ -0,0 +1,64 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\lm123_sub\lm123_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/06/2024 11:06:50 AM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q2 Net-_J1-Pad1_ Net-_J1-Pad1_ Net-_Q2-Pad3_ eSim_PNP
+Q3 Net-_Q1-Pad2_ Net-_J1-Pad1_ Net-_Q2-Pad3_ eSim_PNP
+Q5 Net-_Q10-Pad1_ Net-_J1-Pad1_ Net-_Q2-Pad3_ eSim_PNP
+J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n
+R1 Net-_Q4-Pad2_ Net-_J1-Pad3_ 4k
+R2 Net-_J1-Pad2_ Net-_Q4-Pad2_ 250
+U2 Net-_J1-Pad2_ Net-_Q1-Pad2_ zener
+Q1 Net-_J1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad3_ eSim_NPN
+Q4 Net-_Q10-Pad1_ Net-_Q4-Pad2_ Net-_J1-Pad2_ eSim_NPN
+R3 Net-_J1-Pad2_ Net-_Q6-Pad3_ 1k
+Q6 Net-_Q6-Pad1_ Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_NPN
+R4 Net-_Q6-Pad1_ Net-_Q9-Pad3_ 2k
+R5 Net-_Q6-Pad2_ Net-_Q9-Pad3_ 1.32k
+R6 Net-_Q10-Pad2_ Net-_Q6-Pad2_ 100
+Q7 Net-_Q10-Pad2_ Net-_Q6-Pad3_ Net-_Q7-Pad3_ eSim_NPN
+R7 Net-_J1-Pad2_ Net-_Q7-Pad3_ 100
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R8 Net-_J1-Pad2_ Net-_Q10-Pad3_ 12k
+R10 Net-_J1-Pad2_ Net-_Q11-Pad3_ 1k
+Q11 Net-_C1-Pad1_ Net-_Q10-Pad3_ Net-_Q11-Pad3_ eSim_NPN
+Q14 Net-_Q13-Pad3_ Net-_Q13-Pad3_ Net-_Q14-Pad3_ eSim_NPN
+R11 Net-_J1-Pad2_ Net-_Q14-Pad3_ 4k
+Q13 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q13-Pad3_ eSim_NPN
+Q16 Net-_C1-Pad2_ Net-_Q13-Pad3_ Net-_J1-Pad2_ eSim_NPN
+R9 Net-_C1-Pad1_ Net-_Q12-Pad3_ 20k
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30pF
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+Q9 Net-_Q6-Pad1_ Net-_Q6-Pad1_ Net-_Q9-Pad3_ eSim_NPN
+Q8 Net-_J1-Pad1_ Net-_Q12-Pad1_ Net-_Q6-Pad1_ eSim_NPN
+R14 Net-_Q12-Pad2_ Net-_Q12-Pad1_ 50k
+R15 Net-_Q20-Pad3_ Net-_Q12-Pad2_ 500
+Q20 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q20-Pad3_ eSim_NPN
+R16 Net-_J1-Pad2_ Net-_Q20-Pad3_ 20k
+R19 Net-_J1-Pad2_ Net-_Q12-Pad1_ 4k
+U4 Net-_J1-Pad2_ Net-_Q12-Pad1_ zener
+Q19 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q12-Pad1_ eSim_NPN
+Q17 Net-_J1-Pad2_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_PNP
+R12 Net-_C1-Pad2_ Net-_Q15-Pad3_ 1k
+Q15 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q15-Pad3_ eSim_NPN
+Q18 Net-_J1-Pad2_ Net-_C2-Pad1_ Net-_Q10-Pad1_ eSim_PNP
+R13 Net-_C2-Pad1_ Net-_Q10-Pad1_ 2k
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10pF
+R17 Net-_C2-Pad2_ Net-_Q21-Pad1_ 2k
+R18 Net-_Q21-Pad1_ Net-_Q21-Pad2_ 200
+Q21 Net-_Q21-Pad1_ Net-_Q21-Pad2_ Net-_Q21-Pad3_ eSim_NPN
+R20 Net-_Q21-Pad2_ Net-_Q10-Pad1_ 6k
+R22 Net-_Q21-Pad3_ Net-_Q23-Pad3_ 50
+R21 Net-_Q21-Pad3_ Net-_R21-Pad2_ 50k
+R24 Net-_Q12-Pad1_ Net-_Q23-Pad3_ 0.03
+R23 Net-_Q23-Pad3_ Net-_Q22-Pad3_ 1k
+Q22 Net-_Q2-Pad3_ Net-_Q10-Pad1_ Net-_Q22-Pad3_ eSim_NPN
+Q23 Net-_Q2-Pad3_ Net-_Q22-Pad3_ Net-_Q23-Pad3_ eSim_NPN
+U3 Net-_R21-Pad2_ Net-_Q2-Pad3_ zener
+U1 Net-_Q2-Pad3_ Net-_Q12-Pad1_ Net-_J1-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/lm123_sub/lm123_sub.cir.out b/library/SubcircuitLibrary/lm123_sub/lm123_sub.cir.out
new file mode 100644
index 00000000..b71432eb
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/lm123_sub.cir.out
@@ -0,0 +1,77 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm123_sub\lm123_sub.cir
+
+.include PNP.lib
+.include NJF.lib
+.include NPN.lib
+q2 net-_j1-pad1_ net-_j1-pad1_ net-_q2-pad3_ Q2N2907A
+q3 net-_q1-pad2_ net-_j1-pad1_ net-_q2-pad3_ Q2N2907A
+q5 net-_q10-pad1_ net-_j1-pad1_ net-_q2-pad3_ Q2N2907A
+j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819
+r1 net-_q4-pad2_ net-_j1-pad3_ 4k
+r2 net-_j1-pad2_ net-_q4-pad2_ 250
+* u2 net-_j1-pad2_ net-_q1-pad2_ zener
+q1 net-_j1-pad1_ net-_q1-pad2_ net-_j1-pad3_ Q2N2222
+q4 net-_q10-pad1_ net-_q4-pad2_ net-_j1-pad2_ Q2N2222
+r3 net-_j1-pad2_ net-_q6-pad3_ 1k
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222
+r4 net-_q6-pad1_ net-_q9-pad3_ 2k
+r5 net-_q6-pad2_ net-_q9-pad3_ 1.32k
+r6 net-_q10-pad2_ net-_q6-pad2_ 100
+q7 net-_q10-pad2_ net-_q6-pad3_ net-_q7-pad3_ Q2N2222
+r7 net-_j1-pad2_ net-_q7-pad3_ 100
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r8 net-_j1-pad2_ net-_q10-pad3_ 12k
+r10 net-_j1-pad2_ net-_q11-pad3_ 1k
+q11 net-_c1-pad1_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222
+q14 net-_q13-pad3_ net-_q13-pad3_ net-_q14-pad3_ Q2N2222
+r11 net-_j1-pad2_ net-_q14-pad3_ 4k
+q13 net-_c1-pad2_ net-_c1-pad1_ net-_q13-pad3_ Q2N2222
+q16 net-_c1-pad2_ net-_q13-pad3_ net-_j1-pad2_ Q2N2222
+r9 net-_c1-pad1_ net-_q12-pad3_ 20k
+c1 net-_c1-pad1_ net-_c1-pad2_ 30pf
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+q9 net-_q6-pad1_ net-_q6-pad1_ net-_q9-pad3_ Q2N2222
+q8 net-_j1-pad1_ net-_q12-pad1_ net-_q6-pad1_ Q2N2222
+r14 net-_q12-pad2_ net-_q12-pad1_ 50k
+r15 net-_q20-pad3_ net-_q12-pad2_ 500
+q20 net-_q12-pad1_ net-_q12-pad1_ net-_q20-pad3_ Q2N2222
+r16 net-_j1-pad2_ net-_q20-pad3_ 20k
+r19 net-_j1-pad2_ net-_q12-pad1_ 4k
+* u4 net-_j1-pad2_ net-_q12-pad1_ zener
+q19 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad1_ Q2N2222
+q17 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A
+r12 net-_c1-pad2_ net-_q15-pad3_ 1k
+q15 net-_q10-pad1_ net-_q10-pad1_ net-_q15-pad3_ Q2N2222
+q18 net-_j1-pad2_ net-_c2-pad1_ net-_q10-pad1_ Q2N2907A
+r13 net-_c2-pad1_ net-_q10-pad1_ 2k
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r17 net-_c2-pad2_ net-_q21-pad1_ 2k
+r18 net-_q21-pad1_ net-_q21-pad2_ 200
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_q21-pad3_ Q2N2222
+r20 net-_q21-pad2_ net-_q10-pad1_ 6k
+r22 net-_q21-pad3_ net-_q23-pad3_ 50
+r21 net-_q21-pad3_ net-_r21-pad2_ 50k
+r24 net-_q12-pad1_ net-_q23-pad3_ 0.03
+r23 net-_q23-pad3_ net-_q22-pad3_ 1k
+q22 net-_q2-pad3_ net-_q10-pad1_ net-_q22-pad3_ Q2N2222
+q23 net-_q2-pad3_ net-_q22-pad3_ net-_q23-pad3_ Q2N2222
+* u3 net-_r21-pad2_ net-_q2-pad3_ zener
+* u1 net-_q2-pad3_ net-_q12-pad1_ net-_j1-pad2_ port
+a1 net-_j1-pad2_ net-_q1-pad2_ u2
+a2 net-_j1-pad2_ net-_q12-pad1_ u4
+a3 net-_r21-pad2_ net-_q2-pad3_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/lm123_sub/lm123_sub.pro b/library/SubcircuitLibrary/lm123_sub/lm123_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/lm123_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/lm123_sub/lm123_sub.sch b/library/SubcircuitLibrary/lm123_sub/lm123_sub.sch
new file mode 100644
index 00000000..45edcf59
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/lm123_sub.sch
@@ -0,0 +1,976 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:lm123_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
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+ 1 1850 1000
+ 1 0 0 1
+$EndComp
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+ 1 0 0 1
+$EndComp
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+F 2 "" H 3100 1100 29 0000 C CNN
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+ 1 2600 5800
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+F 2 "" H 5200 4330 30 0000 C CNN
+F 3 "" V 5200 4400 30 0000 C CNN
+ 1 5150 4350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L capacitor C1
+U 1 1 665CB183
+P 5600 4200
+F 0 "C1" H 5625 4300 50 0000 L CNN
+F 1 "30pF" H 5625 4100 50 0000 L CNN
+F 2 "" H 5638 4050 30 0000 C CNN
+F 3 "" H 5600 4200 60 0000 C CNN
+ 1 5600 4200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 665CB184
+P 5200 3700
+F 0 "Q12" H 5100 3750 50 0000 R CNN
+F 1 "eSim_NPN" H 5150 3850 50 0000 R CNN
+F 2 "" H 5400 3800 29 0000 C CNN
+F 3 "" H 5200 3700 60 0000 C CNN
+ 1 5200 3700
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 665CB185
+P 3700 3700
+F 0 "Q9" H 3600 3750 50 0000 R CNN
+F 1 "eSim_NPN" H 3650 3850 50 0000 R CNN
+F 2 "" H 3900 3800 29 0000 C CNN
+F 3 "" H 3700 3700 60 0000 C CNN
+ 1 3700 3700
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 665CB186
+P 3700 3150
+F 0 "Q8" H 3600 3200 50 0000 R CNN
+F 1 "eSim_NPN" H 3650 3300 50 0000 R CNN
+F 2 "" H 3900 3250 29 0000 C CNN
+F 3 "" H 3700 3150 60 0000 C CNN
+ 1 3700 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R14
+U 1 1 665CB187
+P 7450 3400
+F 0 "R14" H 7500 3530 50 0000 C CNN
+F 1 "50k" H 7500 3350 50 0000 C CNN
+F 2 "" H 7500 3380 30 0000 C CNN
+F 3 "" V 7500 3450 30 0000 C CNN
+ 1 7450 3400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R15
+U 1 1 665CB188
+P 7450 4050
+F 0 "R15" H 7500 4180 50 0000 C CNN
+F 1 "500" H 7500 4000 50 0000 C CNN
+F 2 "" H 7500 4030 30 0000 C CNN
+F 3 "" V 7500 4100 30 0000 C CNN
+ 1 7450 4050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q20
+U 1 1 665CB189
+P 7850 3700
+F 0 "Q20" H 7750 3750 50 0000 R CNN
+F 1 "eSim_NPN" H 7800 3850 50 0000 R CNN
+F 2 "" H 8050 3800 29 0000 C CNN
+F 3 "" H 7850 3700 60 0000 C CNN
+ 1 7850 3700
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R16
+U 1 1 665CB18A
+P 7800 6050
+F 0 "R16" H 7850 6180 50 0000 C CNN
+F 1 "20k" H 7850 6000 50 0000 C CNN
+F 2 "" H 7850 6030 30 0000 C CNN
+F 3 "" V 7850 6100 30 0000 C CNN
+ 1 7800 6050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 665CB18B
+P 8850 6050
+F 0 "R19" H 8900 6180 50 0000 C CNN
+F 1 "4k" H 8900 6000 50 0000 C CNN
+F 2 "" H 8900 6030 30 0000 C CNN
+F 3 "" V 8900 6100 30 0000 C CNN
+ 1 8850 6050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L zener U4
+U 1 1 665CB18C
+P 9650 4900
+F 0 "U4" H 9600 4800 60 0000 C CNN
+F 1 "zener" H 9650 5000 60 0000 C CNN
+F 2 "" H 9700 4900 60 0000 C CNN
+F 3 "" H 9700 4900 60 0000 C CNN
+ 1 9650 4900
+ 0 1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q19
+U 1 1 665CB18D
+P 7500 2450
+F 0 "Q19" H 7400 2500 50 0000 R CNN
+F 1 "eSim_NPN" H 7450 2600 50 0000 R CNN
+F 2 "" H 7700 2550 29 0000 C CNN
+F 3 "" H 7500 2450 60 0000 C CNN
+ 1 7500 2450
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q17
+U 1 1 665CB18E
+P 6750 2600
+F 0 "Q17" H 6650 2650 50 0000 R CNN
+F 1 "eSim_PNP" H 6700 2750 50 0000 R CNN
+F 2 "" H 6950 2700 29 0000 C CNN
+F 3 "" H 6750 2600 60 0000 C CNN
+ 1 6750 2600
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R12
+U 1 1 665CB18F
+P 6450 2300
+F 0 "R12" H 6500 2430 50 0000 C CNN
+F 1 "1k" H 6500 2250 50 0000 C CNN
+F 2 "" H 6500 2280 30 0000 C CNN
+F 3 "" V 6500 2350 30 0000 C CNN
+ 1 6450 2300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 665CB190
+P 6300 1700
+F 0 "Q15" H 6200 1750 50 0000 R CNN
+F 1 "eSim_NPN" H 6250 1850 50 0000 R CNN
+F 2 "" H 6500 1800 29 0000 C CNN
+F 3 "" H 6300 1700 60 0000 C CNN
+ 1 6300 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q18
+U 1 1 665CB191
+P 7100 1650
+F 0 "Q18" H 7000 1700 50 0000 R CNN
+F 1 "eSim_PNP" H 7050 1800 50 0000 R CNN
+F 2 "" H 7300 1750 29 0000 C CNN
+F 3 "" H 7100 1650 60 0000 C CNN
+ 1 7100 1650
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 665CB192
+P 7450 1450
+F 0 "R13" H 7500 1580 50 0000 C CNN
+F 1 "2k" H 7500 1400 50 0000 C CNN
+F 2 "" H 7500 1430 30 0000 C CNN
+F 3 "" V 7500 1500 30 0000 C CNN
+ 1 7450 1450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L capacitor C2
+U 1 1 665CB193
+P 7900 1900
+F 0 "C2" H 7925 2000 50 0000 L CNN
+F 1 "10pF" H 7925 1800 50 0000 L CNN
+F 2 "" H 7938 1750 30 0000 C CNN
+F 3 "" H 7900 1900 60 0000 C CNN
+ 1 7900 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R17
+U 1 1 665CB194
+P 8250 2500
+F 0 "R17" H 8300 2630 50 0000 C CNN
+F 1 "2k" H 8300 2450 50 0000 C CNN
+F 2 "" H 8300 2480 30 0000 C CNN
+F 3 "" V 8300 2550 30 0000 C CNN
+ 1 8250 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R18
+U 1 1 665CB195
+P 8600 2050
+F 0 "R18" H 8650 2180 50 0000 C CNN
+F 1 "200" H 8650 2000 50 0000 C CNN
+F 2 "" H 8650 2030 30 0000 C CNN
+F 3 "" V 8650 2100 30 0000 C CNN
+ 1 8600 2050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q21
+U 1 1 665CB196
+P 8900 2350
+F 0 "Q21" H 8800 2400 50 0000 R CNN
+F 1 "eSim_NPN" H 8850 2500 50 0000 R CNN
+F 2 "" H 9100 2450 29 0000 C CNN
+F 3 "" H 8900 2350 60 0000 C CNN
+ 1 8900 2350
+ 0 -1 1 0
+$EndComp
+$Comp
+L resistor R20
+U 1 1 665CB197
+P 8950 1500
+F 0 "R20" H 9000 1630 50 0000 C CNN
+F 1 "6k" H 9000 1450 50 0000 C CNN
+F 2 "" H 9000 1480 30 0000 C CNN
+F 3 "" V 9000 1550 30 0000 C CNN
+ 1 8950 1500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R22
+U 1 1 665CB198
+P 9550 2500
+F 0 "R22" H 9600 2630 50 0000 C CNN
+F 1 "50" H 9600 2450 50 0000 C CNN
+F 2 "" H 9600 2480 30 0000 C CNN
+F 3 "" V 9600 2550 30 0000 C CNN
+ 1 9550 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R21
+U 1 1 665CB199
+P 9400 1500
+F 0 "R21" H 9450 1630 50 0000 C CNN
+F 1 "50k" H 9450 1450 50 0000 C CNN
+F 2 "" H 9450 1480 30 0000 C CNN
+F 3 "" V 9450 1550 30 0000 C CNN
+ 1 9400 1500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R24
+U 1 1 665CB19A
+P 10450 3000
+F 0 "R24" H 10500 3130 50 0000 C CNN
+F 1 "0.03" H 10500 2950 50 0000 C CNN
+F 2 "" H 10500 2980 30 0000 C CNN
+F 3 "" V 10500 3050 30 0000 C CNN
+ 1 10450 3000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R23
+U 1 1 665CB19B
+P 10050 2000
+F 0 "R23" H 10100 2130 50 0000 C CNN
+F 1 "1k" H 10100 1950 50 0000 C CNN
+F 2 "" H 10100 1980 30 0000 C CNN
+F 3 "" V 10100 2050 30 0000 C CNN
+ 1 10050 2000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q22
+U 1 1 665CB19C
+P 9650 1200
+F 0 "Q22" H 9550 1250 50 0000 R CNN
+F 1 "eSim_NPN" H 9600 1350 50 0000 R CNN
+F 2 "" H 9850 1300 29 0000 C CNN
+F 3 "" H 9650 1200 60 0000 C CNN
+ 1 9650 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q23
+U 1 1 665CB19D
+P 10300 1500
+F 0 "Q23" H 10200 1550 50 0000 R CNN
+F 1 "eSim_NPN" H 10250 1650 50 0000 R CNN
+F 2 "" H 10500 1600 29 0000 C CNN
+F 3 "" H 10300 1500 60 0000 C CNN
+ 1 10300 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L zener U3
+U 1 1 665CB19E
+P 9350 950
+F 0 "U3" H 9300 850 60 0000 C CNN
+F 1 "zener" H 9350 1050 60 0000 C CNN
+F 2 "" H 9400 950 60 0000 C CNN
+F 3 "" H 9400 950 60 0000 C CNN
+ 1 9350 950
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 1650 1000 1650 4900
+Wire Wire Line
+ 2200 1200 2200 5200
+Wire Wire Line
+ 2200 1200 2450 1200
+Wire Wire Line
+ 1950 800 3000 800
+Wire Wire Line
+ 2450 550 2450 800
+Connection ~ 2450 800
+Wire Wire Line
+ 9350 650 9350 550
+Wire Wire Line
+ 1500 550 10400 550
+Wire Wire Line
+ 10400 550 10400 1300
+Connection ~ 9350 550
+Wire Wire Line
+ 1300 4900 1300 4650
+Wire Wire Line
+ 1300 4650 1650 4650
+Connection ~ 1650 4650
+Wire Wire Line
+ 1650 5300 1650 5400
+Wire Wire Line
+ 1300 5300 1300 5350
+Wire Wire Line
+ 1300 5350 1650 5350
+Connection ~ 1650 5350
+Wire Wire Line
+ 1650 5700 1650 5850
+Wire Wire Line
+ 2400 5800 1650 5800
+Connection ~ 1650 5800
+Wire Wire Line
+ 1000 5100 1000 6300
+Wire Wire Line
+ 1000 6300 10500 6300
+Wire Wire Line
+ 8800 6150 8800 6300
+Connection ~ 8800 6300
+Wire Wire Line
+ 9650 6300 9650 5100
+Connection ~ 9650 6300
+Wire Wire Line
+ 1650 6150 1650 6300
+Connection ~ 1650 6300
+Wire Wire Line
+ 2200 5700 2200 6300
+Connection ~ 2200 6300
+Wire Wire Line
+ 2700 6000 2700 6300
+Connection ~ 2700 6300
+Wire Wire Line
+ 3050 6150 3050 6300
+Connection ~ 3050 6300
+Wire Wire Line
+ 3600 6150 3600 6300
+Connection ~ 3600 6300
+Wire Wire Line
+ 1950 5100 2200 5100
+Connection ~ 2200 5100
+Wire Wire Line
+ 2700 5600 2700 1550
+Wire Wire Line
+ 2700 1550 3600 1550
+Wire Wire Line
+ 3600 1550 3600 1200
+Wire Wire Line
+ 3000 1200 9450 1200
+Connection ~ 3600 1200
+Wire Wire Line
+ 1950 1200 1950 1400
+Wire Wire Line
+ 1950 1400 1650 1400
+Connection ~ 1650 1400
+Wire Wire Line
+ 1650 1000 2700 1000
+Connection ~ 2150 1000
+Connection ~ 2450 550
+Wire Wire Line
+ 3050 4800 3050 5850
+Wire Wire Line
+ 3300 5450 3050 5450
+Connection ~ 3050 5450
+Wire Wire Line
+ 3600 5850 3600 5650
+Wire Wire Line
+ 3600 5050 3600 5250
+Wire Wire Line
+ 3600 4400 3600 4750
+Wire Wire Line
+ 3350 4600 3600 4600
+Connection ~ 3600 4600
+Wire Wire Line
+ 3050 3450 3050 4400
+Wire Wire Line
+ 3050 4000 3150 4000
+Wire Wire Line
+ 3450 4000 3600 4000
+Wire Wire Line
+ 3600 3900 3600 4100
+Connection ~ 3600 4000
+Wire Wire Line
+ 3600 3350 3600 3500
+Wire Wire Line
+ 3900 3450 3900 3700
+Wire Wire Line
+ 3050 3450 3900 3450
+Connection ~ 3600 3450
+Connection ~ 3050 4000
+Wire Wire Line
+ 3600 2950 1650 2950
+Connection ~ 1650 2950
+Wire Wire Line
+ 4000 5150 3600 5150
+Connection ~ 3600 5150
+Wire Wire Line
+ 4300 5350 4300 5500
+Wire Wire Line
+ 4300 5500 4800 5500
+Wire Wire Line
+ 4650 5850 4650 5500
+Connection ~ 4650 5500
+Wire Wire Line
+ 4650 6150 4650 6300
+Connection ~ 4650 6300
+Wire Wire Line
+ 5100 6150 5100 6300
+Connection ~ 5100 6300
+Wire Wire Line
+ 5100 5850 5100 5700
+Wire Wire Line
+ 5600 5700 5600 5850
+Wire Wire Line
+ 5600 6150 5600 6300
+Connection ~ 5600 6300
+Wire Wire Line
+ 4300 4950 4300 1200
+Connection ~ 4300 1200
+Wire Wire Line
+ 6000 5500 5900 5500
+Wire Wire Line
+ 6000 5100 6000 5500
+Wire Wire Line
+ 5800 5100 6100 5100
+Wire Wire Line
+ 5600 5300 5600 5200
+Wire Wire Line
+ 5600 5200 6000 5200
+Connection ~ 6000 5200
+Wire Wire Line
+ 5800 5000 5800 5100
+Connection ~ 6000 5100
+Wire Wire Line
+ 6400 5300 6400 6300
+Connection ~ 6400 6300
+Wire Wire Line
+ 5100 4450 5100 5300
+Wire Wire Line
+ 5100 4800 5500 4800
+Connection ~ 5100 4800
+Wire Wire Line
+ 5450 4200 5300 4200
+Wire Wire Line
+ 5300 4200 5300 4800
+Connection ~ 5300 4800
+Wire Wire Line
+ 6400 4200 5750 4200
+Wire Wire Line
+ 5100 4150 5100 3900
+Wire Wire Line
+ 3900 3150 10650 3150
+Wire Wire Line
+ 5100 3500 5100 3150
+Connection ~ 5100 3150
+Wire Wire Line
+ 7400 3500 7400 3850
+Wire Wire Line
+ 7400 2650 7400 3200
+Connection ~ 7400 3150
+Wire Wire Line
+ 5400 3700 7400 3700
+Connection ~ 7400 3700
+Wire Wire Line
+ 7750 3900 7750 5850
+Wire Wire Line
+ 7750 6150 7750 6300
+Connection ~ 7750 6300
+Wire Wire Line
+ 8800 5850 8800 3150
+Connection ~ 8800 3150
+Wire Wire Line
+ 8050 3700 8300 3700
+Wire Wire Line
+ 8300 3700 8300 3150
+Connection ~ 8300 3150
+Wire Wire Line
+ 7750 3500 7750 3150
+Connection ~ 7750 3150
+Wire Wire Line
+ 7400 4150 7400 4300
+Wire Wire Line
+ 7400 4300 7750 4300
+Connection ~ 7750 4300
+Wire Wire Line
+ 6400 2400 6400 4900
+Wire Wire Line
+ 5800 4600 6400 4600
+Connection ~ 6400 4600
+Connection ~ 6400 4200
+Wire Wire Line
+ 6850 2800 6850 6300
+Connection ~ 6850 6300
+Wire Wire Line
+ 6400 2100 6400 1900
+Wire Wire Line
+ 6400 1500 6400 1200
+Connection ~ 6400 1200
+Wire Wire Line
+ 6100 1700 5900 1700
+Wire Wire Line
+ 5900 1700 5900 1200
+Connection ~ 5900 1200
+Wire Wire Line
+ 7000 1450 7000 1200
+Connection ~ 7000 1200
+Wire Wire Line
+ 6550 2600 6400 2600
+Connection ~ 6400 2600
+Wire Wire Line
+ 6850 2400 6850 1200
+Connection ~ 6850 1200
+Wire Wire Line
+ 7000 1850 7000 2900
+Wire Wire Line
+ 7000 2900 6850 2900
+Connection ~ 6850 2900
+Wire Wire Line
+ 7400 1550 7400 2250
+Wire Wire Line
+ 7300 1650 7900 1650
+Connection ~ 7400 1650
+Wire Wire Line
+ 7900 1650 7900 1750
+Wire Wire Line
+ 7900 2050 7900 2450
+Wire Wire Line
+ 7700 2450 8150 2450
+Connection ~ 7900 2450
+Wire Wire Line
+ 8450 2450 8700 2450
+Wire Wire Line
+ 8550 2150 8550 2450
+Connection ~ 8550 2450
+Wire Wire Line
+ 9100 2450 9450 2450
+Wire Wire Line
+ 8900 1600 8900 2150
+Wire Wire Line
+ 8550 1850 8550 1750
+Wire Wire Line
+ 8550 1750 8900 1750
+Connection ~ 8900 1750
+Wire Wire Line
+ 8900 1300 8900 1200
+Connection ~ 8900 1200
+Wire Wire Line
+ 9350 1150 9350 1300
+Wire Wire Line
+ 9350 1600 9350 2450
+Connection ~ 9350 2450
+Wire Wire Line
+ 9750 1000 9750 850
+Wire Wire Line
+ 9750 850 10400 850
+Connection ~ 10400 850
+Wire Wire Line
+ 9750 1400 9750 1500
+Wire Wire Line
+ 9750 1500 10100 1500
+Wire Wire Line
+ 10000 1800 10000 1500
+Connection ~ 10000 1500
+Wire Wire Line
+ 10000 2100 10000 2450
+Wire Wire Line
+ 9750 2450 10400 2450
+Wire Wire Line
+ 10400 1700 10400 2800
+Connection ~ 10000 2450
+Connection ~ 10400 2450
+Wire Wire Line
+ 10400 3150 10400 3100
+Connection ~ 10400 3150
+Wire Wire Line
+ 9650 4600 9650 3150
+Connection ~ 9650 3150
+Connection ~ 1000 6300
+Wire Wire Line
+ 7400 1250 7400 1200
+Connection ~ 7400 1200
+$Comp
+L PORT U1
+U 1 1 665D1194
+P 1250 550
+F 0 "U1" H 1300 650 30 0000 C CNN
+F 1 "PORT" H 1250 550 30 0000 C CNN
+F 2 "" H 1250 550 60 0000 C CNN
+F 3 "" H 1250 550 60 0000 C CNN
+ 1 1250 550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 665D1335
+P 10750 6300
+F 0 "U1" H 10800 6400 30 0000 C CNN
+F 1 "PORT" H 10750 6300 30 0000 C CNN
+F 2 "" H 10750 6300 60 0000 C CNN
+F 3 "" H 10750 6300 60 0000 C CNN
+ 3 10750 6300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 665D1462
+P 10900 3150
+F 0 "U1" H 10950 3250 30 0000 C CNN
+F 1 "PORT" H 10900 3150 30 0000 C CNN
+F 2 "" H 10900 3150 60 0000 C CNN
+F 3 "" H 10900 3150 60 0000 C CNN
+ 2 10900 3150
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/lm123_sub/lm123_sub.sub b/library/SubcircuitLibrary/lm123_sub/lm123_sub.sub
new file mode 100644
index 00000000..3c5d491e
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/lm123_sub.sub
@@ -0,0 +1,71 @@
+* Subcircuit lm123_sub
+.subckt lm123_sub net-_q2-pad3_ net-_q12-pad1_ net-_j1-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\lm123_sub\lm123_sub.cir
+.include PNP.lib
+.include NJF.lib
+.include NPN.lib
+q2 net-_j1-pad1_ net-_j1-pad1_ net-_q2-pad3_ Q2N2907A
+q3 net-_q1-pad2_ net-_j1-pad1_ net-_q2-pad3_ Q2N2907A
+q5 net-_q10-pad1_ net-_j1-pad1_ net-_q2-pad3_ Q2N2907A
+j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819
+r1 net-_q4-pad2_ net-_j1-pad3_ 4k
+r2 net-_j1-pad2_ net-_q4-pad2_ 250
+* u2 net-_j1-pad2_ net-_q1-pad2_ zener
+q1 net-_j1-pad1_ net-_q1-pad2_ net-_j1-pad3_ Q2N2222
+q4 net-_q10-pad1_ net-_q4-pad2_ net-_j1-pad2_ Q2N2222
+r3 net-_j1-pad2_ net-_q6-pad3_ 1k
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222
+r4 net-_q6-pad1_ net-_q9-pad3_ 2k
+r5 net-_q6-pad2_ net-_q9-pad3_ 1.32k
+r6 net-_q10-pad2_ net-_q6-pad2_ 100
+q7 net-_q10-pad2_ net-_q6-pad3_ net-_q7-pad3_ Q2N2222
+r7 net-_j1-pad2_ net-_q7-pad3_ 100
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r8 net-_j1-pad2_ net-_q10-pad3_ 12k
+r10 net-_j1-pad2_ net-_q11-pad3_ 1k
+q11 net-_c1-pad1_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222
+q14 net-_q13-pad3_ net-_q13-pad3_ net-_q14-pad3_ Q2N2222
+r11 net-_j1-pad2_ net-_q14-pad3_ 4k
+q13 net-_c1-pad2_ net-_c1-pad1_ net-_q13-pad3_ Q2N2222
+q16 net-_c1-pad2_ net-_q13-pad3_ net-_j1-pad2_ Q2N2222
+r9 net-_c1-pad1_ net-_q12-pad3_ 20k
+c1 net-_c1-pad1_ net-_c1-pad2_ 30pf
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+q9 net-_q6-pad1_ net-_q6-pad1_ net-_q9-pad3_ Q2N2222
+q8 net-_j1-pad1_ net-_q12-pad1_ net-_q6-pad1_ Q2N2222
+r14 net-_q12-pad2_ net-_q12-pad1_ 50k
+r15 net-_q20-pad3_ net-_q12-pad2_ 500
+q20 net-_q12-pad1_ net-_q12-pad1_ net-_q20-pad3_ Q2N2222
+r16 net-_j1-pad2_ net-_q20-pad3_ 20k
+r19 net-_j1-pad2_ net-_q12-pad1_ 4k
+* u4 net-_j1-pad2_ net-_q12-pad1_ zener
+q19 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad1_ Q2N2222
+q17 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A
+r12 net-_c1-pad2_ net-_q15-pad3_ 1k
+q15 net-_q10-pad1_ net-_q10-pad1_ net-_q15-pad3_ Q2N2222
+q18 net-_j1-pad2_ net-_c2-pad1_ net-_q10-pad1_ Q2N2907A
+r13 net-_c2-pad1_ net-_q10-pad1_ 2k
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r17 net-_c2-pad2_ net-_q21-pad1_ 2k
+r18 net-_q21-pad1_ net-_q21-pad2_ 200
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_q21-pad3_ Q2N2222
+r20 net-_q21-pad2_ net-_q10-pad1_ 6k
+r22 net-_q21-pad3_ net-_q23-pad3_ 50
+r21 net-_q21-pad3_ net-_r21-pad2_ 50k
+r24 net-_q12-pad1_ net-_q23-pad3_ 0.03
+r23 net-_q23-pad3_ net-_q22-pad3_ 1k
+q22 net-_q2-pad3_ net-_q10-pad1_ net-_q22-pad3_ Q2N2222
+q23 net-_q2-pad3_ net-_q22-pad3_ net-_q23-pad3_ Q2N2222
+* u3 net-_r21-pad2_ net-_q2-pad3_ zener
+a1 net-_j1-pad2_ net-_q1-pad2_ u2
+a2 net-_j1-pad2_ net-_q12-pad1_ u4
+a3 net-_r21-pad2_ net-_q2-pad3_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends lm123_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm123_sub/lm123_sub_Previous_Values.xml b/library/SubcircuitLibrary/lm123_sub/lm123_sub_Previous_Values.xml
new file mode 100644
index 00000000..176e25f3
--- /dev/null
+++ b/library/SubcircuitLibrary/lm123_sub/lm123_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)">5.6</field1><field2 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field2><field3 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field3><field4 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field4><field5 name="Enter Switch for Limiting (default=FALSE)">FALSE</field5></u2><u4 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)">5.6</field6><field7 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field7><field8 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field8><field9 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field9><field10 name="Enter Switch for Limiting (default=FALSE)">FALSE</field10></u4><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)">5.6</field11><field12 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field12><field13 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field13><field14 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field14><field15 name="Enter Switch for Limiting (default=FALSE)">FALSE</field15></u3></model><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><j1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm384_sub/D.lib b/library/SubcircuitLibrary/lm384_sub/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/lm384_sub/NPN.lib b/library/SubcircuitLibrary/lm384_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/lm384_sub/PNP.lib b/library/SubcircuitLibrary/lm384_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/lm384_sub/analysis b/library/SubcircuitLibrary/lm384_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm384_sub/lm384_sub-cache.lib b/library/SubcircuitLibrary/lm384_sub/lm384_sub-cache.lib
new file mode 100644
index 00000000..d80602ef
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/lm384_sub-cache.lib
@@ -0,0 +1,145 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/lm384_sub/lm384_sub.cir b/library/SubcircuitLibrary/lm384_sub/lm384_sub.cir
new file mode 100644
index 00000000..f7463971
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/lm384_sub.cir
@@ -0,0 +1,34 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\lm384_sub\lm384_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/06/2024 12:26:50 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP
+Q2 Net-_Q2-Pad1_ Net-_Q1-Pad3_ Net-_Q2-Pad3_ eSim_PNP
+Q5 Net-_C1-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP
+Q4 Net-_Q4-Pad1_ Net-_Q4-Pad1_ Net-_Q11-Pad1_ eSim_PNP
+Q7 Net-_Q1-Pad1_ Net-_Q7-Pad2_ Net-_Q5-Pad2_ eSim_PNP
+Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q6 Net-_C1-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_D1-Pad1_ Net-_Q11-Pad3_ eSim_NPN
+Q12 Net-_Q10-Pad3_ Net-_Q10-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q9 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q8 Net-_D1-Pad1_ Net-_Q4-Pad1_ Net-_Q11-Pad1_ eSim_PNP
+Q10 Net-_Q10-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+R1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 150k
+R4 Net-_Q2-Pad3_ Net-_Q5-Pad3_ 125K
+R3 Net-_Q2-Pad3_ Net-_R2-Pad1_ 17.5K
+R2 Net-_R2-Pad1_ Net-_Q4-Pad1_ 17.5k
+R5 Net-_Q5-Pad3_ Net-_R5-Pad2_ 22.5K
+R6 Net-_Q1-Pad1_ Net-_Q7-Pad2_ 150K
+R7 Net-_R5-Pad2_ Net-_Q11-Pad3_ 0.5
+R8 Net-_Q10-Pad3_ Net-_R5-Pad2_ 0.5
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10pF
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+D2 Net-_D1-Pad2_ Net-_C1-Pad2_ eSim_Diode
+U1 Net-_R2-Pad1_ Net-_Q7-Pad2_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad1_ Net-_R5-Pad2_ Net-_Q11-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/lm384_sub/lm384_sub.cir.out b/library/SubcircuitLibrary/lm384_sub/lm384_sub.cir.out
new file mode 100644
index 00000000..997eafc0
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/lm384_sub.cir.out
@@ -0,0 +1,38 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm384_sub\lm384_sub.cir
+
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A
+q5 net-_c1-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
+q4 net-_q4-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q7 net-_q1-pad1_ net-_q7-pad2_ net-_q5-pad2_ Q2N2907A
+q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q6 net-_c1-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q11 net-_q11-pad1_ net-_d1-pad1_ net-_q11-pad3_ Q2N2222
+q12 net-_q10-pad3_ net-_q10-pad1_ net-_q1-pad1_ Q2N2222
+q9 net-_c1-pad2_ net-_c1-pad1_ net-_q1-pad1_ Q2N2222
+q8 net-_d1-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q10 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad3_ Q2N2907A
+r1 net-_q1-pad1_ net-_q1-pad2_ 150k
+r4 net-_q2-pad3_ net-_q5-pad3_ 125k
+r3 net-_q2-pad3_ net-_r2-pad1_ 17.5k
+r2 net-_r2-pad1_ net-_q4-pad1_ 17.5k
+r5 net-_q5-pad3_ net-_r5-pad2_ 22.5k
+r6 net-_q1-pad1_ net-_q7-pad2_ 150k
+r7 net-_r5-pad2_ net-_q11-pad3_ 0.5
+r8 net-_q10-pad3_ net-_r5-pad2_ 0.5
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c1-pad2_ 1N4148
+* u1 net-_r2-pad1_ net-_q7-pad2_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad1_ net-_r5-pad2_ ? net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ ? net-_q11-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/lm384_sub/lm384_sub.pro b/library/SubcircuitLibrary/lm384_sub/lm384_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/lm384_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/lm384_sub/lm384_sub.sch b/library/SubcircuitLibrary/lm384_sub/lm384_sub.sch
new file mode 100644
index 00000000..1a5c48a2
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/lm384_sub.sch
@@ -0,0 +1,622 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:lm384_sub-cache
+LIBS:LM384-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
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diff --git a/library/SubcircuitLibrary/lm384_sub/lm384_sub.sub b/library/SubcircuitLibrary/lm384_sub/lm384_sub.sub
new file mode 100644
index 00000000..f7ee88f6
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/lm384_sub.sub
@@ -0,0 +1,32 @@
+* Subcircuit lm384_sub
+.subckt lm384_sub net-_r2-pad1_ net-_q7-pad2_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad1_ net-_r5-pad2_ ? net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad1_ ? net-_q11-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm384_sub\lm384_sub.cir
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A
+q5 net-_c1-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
+q4 net-_q4-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q7 net-_q1-pad1_ net-_q7-pad2_ net-_q5-pad2_ Q2N2907A
+q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q6 net-_c1-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222
+q11 net-_q11-pad1_ net-_d1-pad1_ net-_q11-pad3_ Q2N2222
+q12 net-_q10-pad3_ net-_q10-pad1_ net-_q1-pad1_ Q2N2222
+q9 net-_c1-pad2_ net-_c1-pad1_ net-_q1-pad1_ Q2N2222
+q8 net-_d1-pad1_ net-_q4-pad1_ net-_q11-pad1_ Q2N2907A
+q10 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad3_ Q2N2907A
+r1 net-_q1-pad1_ net-_q1-pad2_ 150k
+r4 net-_q2-pad3_ net-_q5-pad3_ 125k
+r3 net-_q2-pad3_ net-_r2-pad1_ 17.5k
+r2 net-_r2-pad1_ net-_q4-pad1_ 17.5k
+r5 net-_q5-pad3_ net-_r5-pad2_ 22.5k
+r6 net-_q1-pad1_ net-_q7-pad2_ 150k
+r7 net-_r5-pad2_ net-_q11-pad3_ 0.5
+r8 net-_q10-pad3_ net-_r5-pad2_ 0.5
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c1-pad2_ 1N4148
+* Control Statements
+
+.ends lm384_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm384_sub/lm384_sub_Previous_Values.xml b/library/SubcircuitLibrary/lm384_sub/lm384_sub_Previous_Values.xml
new file mode 100644
index 00000000..d1a61d87
--- /dev/null
+++ b/library/SubcircuitLibrary/lm384_sub/lm384_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/sn7445/analysis b/library/SubcircuitLibrary/sn7445/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/sn7445/sn7445-cache.lib b/library/SubcircuitLibrary/sn7445/sn7445-cache.lib
new file mode 100644
index 00000000..227513a4
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445-cache.lib
@@ -0,0 +1,106 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.cir b/library/SubcircuitLibrary/sn7445/sn7445.cir
new file mode 100644
index 00000000..853355c0
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.cir
@@ -0,0 +1,53 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\sn7445\sn7445.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 11/06/2024 7:04:06 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U34 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad1_ d_nand
+U35 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ d_nand
+U36 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U1-Pad3_ d_nand
+U43 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U1-Pad10_ d_nand
+U37 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U1-Pad4_ d_nand
+U38 Net-_U20-Pad3_ Net-_U25-Pad3_ Net-_U1-Pad5_ d_nand
+U39 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U1-Pad6_ d_nand
+U40 Net-_U26-Pad3_ Net-_U30-Pad3_ Net-_U1-Pad7_ d_nand
+U41 Net-_U31-Pad3_ Net-_U27-Pad3_ Net-_U1-Pad8_ d_nand
+U42 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad9_ d_nand
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and
+U16 Net-_U10-Pad2_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and
+U17 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U17-Pad3_ d_and
+U18 Net-_U14-Pad1_ Net-_U11-Pad2_ Net-_U18-Pad3_ d_and
+U19 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U19-Pad3_ d_and
+U23 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_and
+U24 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad3_ d_and
+U20 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U20-Pad3_ d_and
+U25 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U25-Pad3_ d_and
+U21 Net-_U10-Pad2_ Net-_U14-Pad2_ Net-_U21-Pad3_ d_and
+U22 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U22-Pad3_ d_and
+U26 Net-_U14-Pad1_ Net-_U11-Pad2_ Net-_U26-Pad3_ d_and
+U30 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U30-Pad3_ d_and
+U31 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U31-Pad3_ d_and
+U27 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U27-Pad3_ d_and
+U28 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U28-Pad3_ d_and
+U29 Net-_U15-Pad1_ Net-_U12-Pad2_ Net-_U29-Pad3_ d_and
+U32 Net-_U10-Pad2_ Net-_U14-Pad2_ Net-_U32-Pad3_ d_and
+U33 Net-_U15-Pad1_ Net-_U12-Pad2_ Net-_U33-Pad3_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_buffer
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_buffer
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_buffer
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_buffer
+U8 Net-_U15-Pad2_ Net-_U12-Pad1_ d_inverter
+U5 Net-_U1-Pad11_ Net-_U15-Pad2_ d_inverter
+U9 Net-_U15-Pad1_ Net-_U13-Pad1_ d_inverter
+U4 Net-_U1-Pad12_ Net-_U15-Pad1_ d_inverter
+U7 Net-_U14-Pad2_ Net-_U11-Pad1_ d_inverter
+U3 Net-_U1-Pad13_ Net-_U14-Pad2_ d_inverter
+U6 Net-_U14-Pad1_ Net-_U10-Pad1_ d_inverter
+U2 Net-_U1-Pad14_ Net-_U14-Pad1_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.cir.out b/library/SubcircuitLibrary/sn7445/sn7445.cir.out
new file mode 100644
index 00000000..e53a66ee
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.cir.out
@@ -0,0 +1,180 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7445\sn7445.cir
+
+* u34 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad1_ d_nand
+* u35 net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ d_nand
+* u36 net-_u18-pad3_ net-_u19-pad3_ net-_u1-pad3_ d_nand
+* u43 net-_u32-pad3_ net-_u33-pad3_ net-_u1-pad10_ d_nand
+* u37 net-_u23-pad3_ net-_u24-pad3_ net-_u1-pad4_ d_nand
+* u38 net-_u20-pad3_ net-_u25-pad3_ net-_u1-pad5_ d_nand
+* u39 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad6_ d_nand
+* u40 net-_u26-pad3_ net-_u30-pad3_ net-_u1-pad7_ d_nand
+* u41 net-_u31-pad3_ net-_u27-pad3_ net-_u1-pad8_ d_nand
+* u42 net-_u28-pad3_ net-_u29-pad3_ net-_u1-pad9_ d_nand
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u16 net-_u10-pad2_ net-_u14-pad2_ net-_u16-pad3_ d_and
+* u17 net-_u15-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_and
+* u18 net-_u14-pad1_ net-_u11-pad2_ net-_u18-pad3_ d_and
+* u19 net-_u15-pad1_ net-_u15-pad2_ net-_u19-pad3_ d_and
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_and
+* u24 net-_u15-pad1_ net-_u15-pad2_ net-_u24-pad3_ d_and
+* u20 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad3_ d_and
+* u25 net-_u13-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_and
+* u21 net-_u10-pad2_ net-_u14-pad2_ net-_u21-pad3_ d_and
+* u22 net-_u13-pad2_ net-_u15-pad2_ net-_u22-pad3_ d_and
+* u26 net-_u14-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_and
+* u30 net-_u13-pad2_ net-_u15-pad2_ net-_u30-pad3_ d_and
+* u31 net-_u10-pad2_ net-_u11-pad2_ net-_u31-pad3_ d_and
+* u27 net-_u13-pad2_ net-_u15-pad2_ net-_u27-pad3_ d_and
+* u28 net-_u14-pad1_ net-_u14-pad2_ net-_u28-pad3_ d_and
+* u29 net-_u15-pad1_ net-_u12-pad2_ net-_u29-pad3_ d_and
+* u32 net-_u10-pad2_ net-_u14-pad2_ net-_u32-pad3_ d_and
+* u33 net-_u15-pad1_ net-_u12-pad2_ net-_u33-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_buffer
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_buffer
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer
+* u8 net-_u15-pad2_ net-_u12-pad1_ d_inverter
+* u5 net-_u1-pad11_ net-_u15-pad2_ d_inverter
+* u9 net-_u15-pad1_ net-_u13-pad1_ d_inverter
+* u4 net-_u1-pad12_ net-_u15-pad1_ d_inverter
+* u7 net-_u14-pad2_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u14-pad2_ d_inverter
+* u6 net-_u14-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad14_ net-_u14-pad1_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u1-pad1_ u34
+a2 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u1-pad2_ u35
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u1-pad3_ u36
+a4 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u1-pad10_ u43
+a5 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u1-pad4_ u37
+a6 [net-_u20-pad3_ net-_u25-pad3_ ] net-_u1-pad5_ u38
+a7 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad6_ u39
+a8 [net-_u26-pad3_ net-_u30-pad3_ ] net-_u1-pad7_ u40
+a9 [net-_u31-pad3_ net-_u27-pad3_ ] net-_u1-pad8_ u41
+a10 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u1-pad9_ u42
+a11 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a13 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u16-pad3_ u16
+a14 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17
+a15 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u18-pad3_ u18
+a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u19-pad3_ u19
+a17 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a18 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad3_ u20
+a20 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
+a21 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u21-pad3_ u21
+a22 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u22-pad3_ u22
+a23 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u26-pad3_ u26
+a24 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u30-pad3_ u30
+a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u31-pad3_ u31
+a26 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u27-pad3_ u27
+a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u28-pad3_ u28
+a28 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u29-pad3_ u29
+a29 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u32-pad3_ u32
+a30 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u33-pad3_ u33
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 net-_u11-pad1_ net-_u11-pad2_ u11
+a33 net-_u13-pad1_ net-_u13-pad2_ u13
+a34 net-_u12-pad1_ net-_u12-pad2_ u12
+a35 net-_u15-pad2_ net-_u12-pad1_ u8
+a36 net-_u1-pad11_ net-_u15-pad2_ u5
+a37 net-_u15-pad1_ net-_u13-pad1_ u9
+a38 net-_u1-pad12_ net-_u15-pad1_ u4
+a39 net-_u14-pad2_ net-_u11-pad1_ u7
+a40 net-_u1-pad13_ net-_u14-pad2_ u3
+a41 net-_u14-pad1_ net-_u10-pad1_ u6
+a42 net-_u1-pad14_ net-_u14-pad1_ u2
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.pro b/library/SubcircuitLibrary/sn7445/sn7445.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.sch b/library/SubcircuitLibrary/sn7445/sn7445.sch
new file mode 100644
index 00000000..1c4acf18
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.sch
@@ -0,0 +1,968 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:7445-cache
+EELAYER 25 0
+EELAYER END
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+ 9000 6300 7800 6300
+Connection ~ 7800 6300
+Wire Wire Line
+ 9050 7600 7800 7600
+Connection ~ 7800 7600
+Wire Wire Line
+ 8950 4250 7400 4250
+Wire Wire Line
+ 7400 4250 7400 9550
+Wire Wire Line
+ 7400 9550 9100 9550
+Wire Wire Line
+ 9050 5650 7400 5650
+Connection ~ 7400 5650
+Wire Wire Line
+ 9000 6950 7400 6950
+Connection ~ 7400 6950
+Wire Wire Line
+ 9100 8250 7400 8250
+Connection ~ 7400 8250
+Wire Wire Line
+ 9000 5050 7950 5050
+Wire Wire Line
+ 7950 5050 7950 8350
+Wire Wire Line
+ 7950 8350 9100 8350
+Wire Wire Line
+ 9050 5750 7950 5750
+Connection ~ 7950 5750
+Wire Wire Line
+ 9050 7700 7950 7700
+Connection ~ 7950 7700
+Wire Wire Line
+ 9050 6600 8250 6600
+Wire Wire Line
+ 8250 6600 8250 8550
+Wire Wire Line
+ 8250 8550 9050 8550
+Wire Wire Line
+ 9000 7250 8250 7250
+Connection ~ 8250 7250
+Wire Wire Line
+ 6900 7950 9100 7950
+Connection ~ 8250 7950
+Connection ~ 8700 8650
+Wire Wire Line
+ 9050 9300 6850 9300
+Wire Wire Line
+ 9100 9950 8900 9950
+Wire Wire Line
+ 8900 9950 8900 9300
+Connection ~ 8900 9300
+Wire Wire Line
+ 4550 7350 8400 7350
+Connection ~ 8400 7350
+Wire Wire Line
+ 4500 3900 7800 3900
+Connection ~ 7800 3900
+Wire Wire Line
+ 7400 4800 6650 4800
+Connection ~ 7400 4800
+Wire Wire Line
+ 4500 5950 8100 5950
+Connection ~ 8100 5950
+Wire Wire Line
+ 7950 6600 6650 6600
+Connection ~ 7950 6600
+Wire Wire Line
+ 5350 4800 5500 4800
+Wire Wire Line
+ 4750 4800 4550 4800
+Wire Wire Line
+ 4550 4800 4550 3900
+Connection ~ 4550 3900
+Wire Wire Line
+ 5400 6600 5500 6600
+Wire Wire Line
+ 4800 6600 4600 6600
+Wire Wire Line
+ 4600 6600 4600 5950
+Connection ~ 4600 5950
+Wire Wire Line
+ 4950 7950 4650 7950
+Wire Wire Line
+ 4650 7950 4650 7350
+Connection ~ 4650 7350
+Wire Wire Line
+ 5550 7950 5750 7950
+Wire Wire Line
+ 5500 9300 5700 9300
+Wire Wire Line
+ 4900 9300 4700 9300
+Wire Wire Line
+ 4700 9300 4700 8650
+Connection ~ 4700 8650
+Wire Wire Line
+ 3700 3900 3900 3900
+Wire Wire Line
+ 3700 8650 4050 8650
+Wire Wire Line
+ 10900 9750 11900 9750
+Wire Wire Line
+ 11900 9750 11900 8200
+Wire Wire Line
+ 10900 9100 11700 9100
+Wire Wire Line
+ 11700 9100 11700 8100
+Wire Wire Line
+ 11700 8100 11900 8100
+Wire Wire Line
+ 10900 8450 11300 8450
+Wire Wire Line
+ 11300 8450 11300 8000
+Wire Wire Line
+ 11300 8000 11900 8000
+Wire Wire Line
+ 11900 7900 11300 7900
+Wire Wire Line
+ 11300 7900 11300 7800
+Wire Wire Line
+ 11300 7800 10900 7800
+Wire Wire Line
+ 11900 7800 11600 7800
+Wire Wire Line
+ 11600 7800 11600 7150
+Wire Wire Line
+ 11600 7150 10900 7150
+Wire Wire Line
+ 10900 6500 11800 6500
+Wire Wire Line
+ 11800 6500 11800 5200
+Wire Wire Line
+ 10900 5850 11650 5850
+Wire Wire Line
+ 11650 5850 11650 5100
+Wire Wire Line
+ 11650 5100 11800 5100
+Wire Wire Line
+ 10900 5150 11350 5150
+Wire Wire Line
+ 11350 5150 11350 5000
+Wire Wire Line
+ 11350 5000 11800 5000
+Wire Wire Line
+ 11300 4900 11800 4900
+Wire Wire Line
+ 11300 4450 11300 4900
+Wire Wire Line
+ 11300 4450 10900 4450
+Wire Wire Line
+ 11800 4800 11800 3800
+Wire Wire Line
+ 11800 3800 10850 3800
+$Comp
+L PORT U1
+U 5 1 66689C57
+P 12050 5200
+F 0 "U1" H 12100 5300 30 0000 C CNN
+F 1 "PORT" H 12050 5200 30 0000 C CNN
+F 2 "" H 12050 5200 60 0000 C CNN
+F 3 "" H 12050 5200 60 0000 C CNN
+ 5 12050 5200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 66689F05
+P 12150 7800
+F 0 "U1" H 12200 7900 30 0000 C CNN
+F 1 "PORT" H 12150 7800 30 0000 C CNN
+F 2 "" H 12150 7800 60 0000 C CNN
+F 3 "" H 12150 7800 60 0000 C CNN
+ 6 12150 7800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6668A02A
+P 12150 7900
+F 0 "U1" H 12200 8000 30 0000 C CNN
+F 1 "PORT" H 12150 7900 30 0000 C CNN
+F 2 "" H 12150 7900 60 0000 C CNN
+F 3 "" H 12150 7900 60 0000 C CNN
+ 7 12150 7900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6668A141
+P 12150 8000
+F 0 "U1" H 12200 8100 30 0000 C CNN
+F 1 "PORT" H 12150 8000 30 0000 C CNN
+F 2 "" H 12150 8000 60 0000 C CNN
+F 3 "" H 12150 8000 60 0000 C CNN
+ 8 12150 8000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6668A238
+P 12150 8100
+F 0 "U1" H 12200 8200 30 0000 C CNN
+F 1 "PORT" H 12150 8100 30 0000 C CNN
+F 2 "" H 12150 8100 60 0000 C CNN
+F 3 "" H 12150 8100 60 0000 C CNN
+ 9 12150 8100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6668B175
+P 12150 8200
+F 0 "U1" H 12200 8300 30 0000 C CNN
+F 1 "PORT" H 12150 8200 30 0000 C CNN
+F 2 "" H 12150 8200 60 0000 C CNN
+F 3 "" H 12150 8200 60 0000 C CNN
+ 10 12150 8200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6668B274
+P 3450 8650
+F 0 "U1" H 3500 8750 30 0000 C CNN
+F 1 "PORT" H 3450 8650 30 0000 C CNN
+F 2 "" H 3450 8650 60 0000 C CNN
+F 3 "" H 3450 8650 60 0000 C CNN
+ 11 3450 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6668BCDE
+P 3650 5950
+F 0 "U1" H 3700 6050 30 0000 C CNN
+F 1 "PORT" H 3650 5950 30 0000 C CNN
+F 2 "" H 3650 5950 60 0000 C CNN
+F 3 "" H 3650 5950 60 0000 C CNN
+ 13 3650 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6668BDDD
+P 3450 3900
+F 0 "U1" H 3500 4000 30 0000 C CNN
+F 1 "PORT" H 3450 3900 30 0000 C CNN
+F 2 "" H 3450 3900 60 0000 C CNN
+F 3 "" H 3450 3900 60 0000 C CNN
+ 14 3450 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6668BEE6
+P 12050 4900
+F 0 "U1" H 12100 5000 30 0000 C CNN
+F 1 "PORT" H 12050 4900 30 0000 C CNN
+F 2 "" H 12050 4900 60 0000 C CNN
+F 3 "" H 12050 4900 60 0000 C CNN
+ 2 12050 4900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6668E223
+P 12050 5100
+F 0 "U1" H 12100 5200 30 0000 C CNN
+F 1 "PORT" H 12050 5100 30 0000 C CNN
+F 2 "" H 12050 5100 60 0000 C CNN
+F 3 "" H 12050 5100 60 0000 C CNN
+ 4 12050 5100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6668E423
+P 12050 5000
+F 0 "U1" H 12100 5100 30 0000 C CNN
+F 1 "PORT" H 12050 5000 30 0000 C CNN
+F 2 "" H 12050 5000 60 0000 C CNN
+F 3 "" H 12050 5000 60 0000 C CNN
+ 3 12050 5000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6668E4E0
+P 12050 4800
+F 0 "U1" H 12100 4900 30 0000 C CNN
+F 1 "PORT" H 12050 4800 30 0000 C CNN
+F 2 "" H 12050 4800 60 0000 C CNN
+F 3 "" H 12050 4800 60 0000 C CNN
+ 1 12050 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 66694CAC
+P 3700 7350
+F 0 "U1" H 3750 7450 30 0000 C CNN
+F 1 "PORT" H 3700 7350 30 0000 C CNN
+F 2 "" H 3700 7350 60 0000 C CNN
+F 3 "" H 3700 7350 60 0000 C CNN
+ 12 3700 7350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.sub b/library/SubcircuitLibrary/sn7445/sn7445.sub
new file mode 100644
index 00000000..d413e1fa
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.sub
@@ -0,0 +1,174 @@
+* Subcircuit sn7445
+.subckt sn7445 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
+* c:\fossee\esim\library\subcircuitlibrary\sn7445\sn7445.cir
+* u34 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad1_ d_nand
+* u35 net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ d_nand
+* u36 net-_u18-pad3_ net-_u19-pad3_ net-_u1-pad3_ d_nand
+* u43 net-_u32-pad3_ net-_u33-pad3_ net-_u1-pad10_ d_nand
+* u37 net-_u23-pad3_ net-_u24-pad3_ net-_u1-pad4_ d_nand
+* u38 net-_u20-pad3_ net-_u25-pad3_ net-_u1-pad5_ d_nand
+* u39 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad6_ d_nand
+* u40 net-_u26-pad3_ net-_u30-pad3_ net-_u1-pad7_ d_nand
+* u41 net-_u31-pad3_ net-_u27-pad3_ net-_u1-pad8_ d_nand
+* u42 net-_u28-pad3_ net-_u29-pad3_ net-_u1-pad9_ d_nand
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u16 net-_u10-pad2_ net-_u14-pad2_ net-_u16-pad3_ d_and
+* u17 net-_u15-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_and
+* u18 net-_u14-pad1_ net-_u11-pad2_ net-_u18-pad3_ d_and
+* u19 net-_u15-pad1_ net-_u15-pad2_ net-_u19-pad3_ d_and
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_and
+* u24 net-_u15-pad1_ net-_u15-pad2_ net-_u24-pad3_ d_and
+* u20 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad3_ d_and
+* u25 net-_u13-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_and
+* u21 net-_u10-pad2_ net-_u14-pad2_ net-_u21-pad3_ d_and
+* u22 net-_u13-pad2_ net-_u15-pad2_ net-_u22-pad3_ d_and
+* u26 net-_u14-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_and
+* u30 net-_u13-pad2_ net-_u15-pad2_ net-_u30-pad3_ d_and
+* u31 net-_u10-pad2_ net-_u11-pad2_ net-_u31-pad3_ d_and
+* u27 net-_u13-pad2_ net-_u15-pad2_ net-_u27-pad3_ d_and
+* u28 net-_u14-pad1_ net-_u14-pad2_ net-_u28-pad3_ d_and
+* u29 net-_u15-pad1_ net-_u12-pad2_ net-_u29-pad3_ d_and
+* u32 net-_u10-pad2_ net-_u14-pad2_ net-_u32-pad3_ d_and
+* u33 net-_u15-pad1_ net-_u12-pad2_ net-_u33-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_buffer
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_buffer
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer
+* u8 net-_u15-pad2_ net-_u12-pad1_ d_inverter
+* u5 net-_u1-pad11_ net-_u15-pad2_ d_inverter
+* u9 net-_u15-pad1_ net-_u13-pad1_ d_inverter
+* u4 net-_u1-pad12_ net-_u15-pad1_ d_inverter
+* u7 net-_u14-pad2_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u14-pad2_ d_inverter
+* u6 net-_u14-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad14_ net-_u14-pad1_ d_inverter
+a1 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u1-pad1_ u34
+a2 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u1-pad2_ u35
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u1-pad3_ u36
+a4 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u1-pad10_ u43
+a5 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u1-pad4_ u37
+a6 [net-_u20-pad3_ net-_u25-pad3_ ] net-_u1-pad5_ u38
+a7 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad6_ u39
+a8 [net-_u26-pad3_ net-_u30-pad3_ ] net-_u1-pad7_ u40
+a9 [net-_u31-pad3_ net-_u27-pad3_ ] net-_u1-pad8_ u41
+a10 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u1-pad9_ u42
+a11 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a13 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u16-pad3_ u16
+a14 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17
+a15 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u18-pad3_ u18
+a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u19-pad3_ u19
+a17 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a18 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad3_ u20
+a20 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
+a21 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u21-pad3_ u21
+a22 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u22-pad3_ u22
+a23 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u26-pad3_ u26
+a24 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u30-pad3_ u30
+a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u31-pad3_ u31
+a26 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u27-pad3_ u27
+a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u28-pad3_ u28
+a28 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u29-pad3_ u29
+a29 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u32-pad3_ u32
+a30 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u33-pad3_ u33
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 net-_u11-pad1_ net-_u11-pad2_ u11
+a33 net-_u13-pad1_ net-_u13-pad2_ u13
+a34 net-_u12-pad1_ net-_u12-pad2_ u12
+a35 net-_u15-pad2_ net-_u12-pad1_ u8
+a36 net-_u1-pad11_ net-_u15-pad2_ u5
+a37 net-_u15-pad1_ net-_u13-pad1_ u9
+a38 net-_u1-pad12_ net-_u15-pad1_ u4
+a39 net-_u14-pad2_ net-_u11-pad1_ u7
+a40 net-_u1-pad13_ net-_u14-pad2_ u3
+a41 net-_u14-pad1_ net-_u10-pad1_ u6
+a42 net-_u1-pad14_ net-_u14-pad1_ u2
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends sn7445 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml b/library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml
new file mode 100644
index 00000000..e375ff77
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u34 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field1><field2 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field2><field3 name="Enter Input Load (default=1.0e-12)">1.0e-12</field3></u34><u35 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field4><field5 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field5><field6 name="Enter Input Load (default=1.0e-12)">1.0e-12</field6></u35><u36 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field7><field8 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field8><field9 name="Enter Input Load (default=1.0e-12)">1.0e-12</field9></u36><u43 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field10><field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field11><field12 name="Enter Input Load (default=1.0e-12)">1.0e-12</field12></u43><u37 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field13><field14 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field14><field15 name="Enter Input Load (default=1.0e-12)">1.0e-12</field15></u37><u38 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field16><field17 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field17><field18 name="Enter Input Load (default=1.0e-12)">1.0e-12</field18></u38><u39 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field19><field20 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field20><field21 name="Enter Input Load (default=1.0e-12)">1.0e-12</field21></u39><u40 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field22><field23 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field23><field24 name="Enter Input Load (default=1.0e-12)">1.0e-12</field24></u40><u41 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field25><field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field26><field27 name="Enter Input Load (default=1.0e-12)">1.0e-12</field27></u41><u42 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field28><field29 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field29><field30 name="Enter Input Load (default=1.0e-12)">1.0e-12</field30></u42><u14 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field31><field32 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field32><field33 name="Enter Input Load (default=1.0e-12)">1.0e-12</field33></u14><u15 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field34><field35 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field35><field36 name="Enter Input Load (default=1.0e-12)">1.0e-12</field36></u15><u16 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field37><field38 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field38><field39 name="Enter Input Load (default=1.0e-12)">1.0e-12</field39></u16><u17 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field40><field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field41><field42 name="Enter Input Load (default=1.0e-12)">1.0e-12</field42></u17><u18 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field43><field44 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field44><field45 name="Enter Input Load (default=1.0e-12)">1.0e-12</field45></u18><u19 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field46><field47 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field47><field48 name="Enter Input Load (default=1.0e-12)">1.0e-12</field48></u19><u23 name="type">d_and<field49 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field49><field50 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field50><field51 name="Enter Input Load (default=1.0e-12)">1.0e-12</field51></u23><u24 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field52><field53 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field53><field54 name="Enter Input Load (default=1.0e-12)">1.0e-12</field54></u24><u20 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field55><field56 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field56><field57 name="Enter Input Load (default=1.0e-12)">1.0e-12</field57></u20><u25 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field58><field59 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field59><field60 name="Enter Input Load (default=1.0e-12)">1.0e-12</field60></u25><u21 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field61><field62 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field62><field63 name="Enter Input Load (default=1.0e-12)">1.0e-12</field63></u21><u22 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field64><field65 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field65><field66 name="Enter Input Load (default=1.0e-12)">1.0e-12</field66></u22><u26 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field67><field68 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field68><field69 name="Enter Input Load (default=1.0e-12)">1.0e-12</field69></u26><u30 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field70><field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field71><field72 name="Enter Input Load (default=1.0e-12)">1.0e-12</field72></u30><u31 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field73><field74 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field74><field75 name="Enter Input Load (default=1.0e-12)">1.0e-12</field75></u31><u27 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field76><field77 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field77><field78 name="Enter Input Load (default=1.0e-12)">1.0e-12</field78></u27><u28 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field79><field80 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field80><field81 name="Enter Input Load (default=1.0e-12)">1.0e-12</field81></u28><u29 name="type">d_and<field82 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field82><field83 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field83><field84 name="Enter Input Load (default=1.0e-12)">1.0e-12</field84></u29><u32 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field85><field86 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field86><field87 name="Enter Input Load (default=1.0e-12)">1.0e-12</field87></u32><u33 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field88><field89 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field89><field90 name="Enter Input Load (default=1.0e-12)">1.0e-12</field90></u33><u10 name="type">d_buffer<field91 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field91><field92 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field92><field93 name="Enter Input Load (default=1.0e-12)">1.0e-12</field93></u10><u11 name="type">d_buffer<field94 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field94><field95 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field95><field96 name="Enter Input Load (default=1.0e-12)">1.0e-12</field96></u11><u13 name="type">d_buffer<field97 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field97><field98 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field98><field99 name="Enter Input Load (default=1.0e-12)">1.0e-12</field99></u13><u12 name="type">d_buffer<field100 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field100><field101 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field101><field102 name="Enter Input Load (default=1.0e-12)">1.0e-12</field102></u12><u8 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field103><field104 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field104><field105 name="Enter Input Load (default=1.0e-12)">1.0e-12</field105></u8><u5 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field106><field107 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field107><field108 name="Enter Input Load (default=1.0e-12)">1.0e-12</field108></u5><u9 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field109><field110 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field110><field111 name="Enter Input Load (default=1.0e-12)">1.0e-12</field111></u9><u4 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field112><field113 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field113><field114 name="Enter Input Load (default=1.0e-12)">1.0e-12</field114></u4><u7 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field115><field116 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field116><field117 name="Enter Input Load (default=1.0e-12)">1.0e-12</field117></u7><u3 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field118><field119 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field119><field120 name="Enter Input Load (default=1.0e-12)">1.0e-12</field120></u3><u6 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field121><field122 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field122><field123 name="Enter Input Load (default=1.0e-12)">1.0e-12</field123></u6><u2 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field124><field125 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field125><field126 name="Enter Input Load (default=1.0e-12)">1.0e-12</field126></u2></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-19 12:10:02 +0000