TL431 is an adjustable precision shunt regulator

11 files changed, 897 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/TL431_SUB/D.lib b/library/SubcircuitLibrary/TL431_SUB/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/TL431_SUB/NPN.lib b/library/SubcircuitLibrary/TL431_SUB/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/TL431_SUB/PNP.lib b/library/SubcircuitLibrary/TL431_SUB/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/TL431_SUB/TL431-PORT-cache.lib b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT-cache.lib
new file mode 100644
index 00000000..c1629264
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.cir b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.cir
new file mode 100644
index 00000000..99497646
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.cir
@@ -0,0 +1,36 @@
+* C:\FOSSEE2\eSim\library\SubcircuitLibrary\TL431-PORT\TL431-PORT.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 08/13/24 12:25:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q2  Net-_C2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
+Q4  Net-_C2-Pad2_ Net-_C2-Pad2_ Net-_Q2-Pad2_ eSim_NPN		
+R5  Net-_C2-Pad1_ Net-_Q7-Pad3_ 800		
+Q7  Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q7-Pad3_ eSim_PNP		
+Q8  Net-_C2-Pad2_ Net-_Q5-Pad1_ Net-_Q8-Pad3_ eSim_PNP		
+R8  Net-_C2-Pad1_ Net-_Q8-Pad3_ 800		
+C2  Net-_C2-Pad1_ Net-_C2-Pad2_ 20p		
+Q10  Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R9  Net-_Q10-Pad3_ Net-_Q11-Pad2_ 150		
+R10  Net-_Q11-Pad2_ Net-_D1-Pad1_ 10k		
+Q11  Net-_C2-Pad1_ Net-_Q11-Pad2_ Net-_D1-Pad1_ eSim_NPN		
+D2  Net-_D1-Pad1_ Net-_C2-Pad1_ eSim_Diode		
+R2  Net-_Q2-Pad3_ Net-_R1-Pad1_ 3.28k		
+Q5  Net-_Q5-Pad1_ Net-_Q2-Pad3_ Net-_Q5-Pad3_ eSim_NPN		
+R6  Net-_Q5-Pad3_ Net-_C1-Pad1_ 4k		
+R1  Net-_R1-Pad1_ Net-_Q1-Pad1_ 2.4k		
+R3  Net-_R1-Pad1_ Net-_C1-Pad2_ 7.2k		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN		
+Q3  Net-_C1-Pad2_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN		
+R4  Net-_Q3-Pad3_ Net-_D1-Pad1_ 800		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ capacitor_polarised		
+Q6  Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_D1-Pad1_ eSim_NPN		
+Q9  Net-_C2-Pad2_ Net-_Q9-Pad2_ Net-_D1-Pad1_ eSim_NPN		
+R7  Net-_Q1-Pad1_ Net-_Q9-Pad2_ 1k		
+D1  Net-_D1-Pad1_ Net-_C2-Pad2_ eSim_Diode		
+U1  Net-_C2-Pad1_ Net-_Q2-Pad2_ Net-_D1-Pad1_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.cir.out b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.cir.out
new file mode 100644
index 00000000..34404a7d
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.cir.out
@@ -0,0 +1,40 @@
+* c:\fossee2\esim\library\subcircuitlibrary\tl431-port\tl431-port.cir
+
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q2 net-_c2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 net-_c2-pad2_ net-_c2-pad2_ net-_q2-pad2_ Q2N2222
+r5  net-_c2-pad1_ net-_q7-pad3_ 800
+q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
+q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A
+r8  net-_c2-pad1_ net-_q8-pad3_ 800
+c2  net-_c2-pad1_ net-_c2-pad2_ 20p
+q10 net-_c2-pad1_ net-_c2-pad2_ net-_q10-pad3_ Q2N2222
+r9  net-_q10-pad3_ net-_q11-pad2_ 150
+r10  net-_q11-pad2_ net-_d1-pad1_ 10k
+q11 net-_c2-pad1_ net-_q11-pad2_ net-_d1-pad1_ Q2N2222
+d2 net-_d1-pad1_ net-_c2-pad1_ 1N4148
+r2  net-_q2-pad3_ net-_r1-pad1_ 3.28k
+q5 net-_q5-pad1_ net-_q2-pad3_ net-_q5-pad3_ Q2N2222
+r6  net-_q5-pad3_ net-_c1-pad1_ 4k
+r1  net-_r1-pad1_ net-_q1-pad1_ 2.4k
+r3  net-_r1-pad1_ net-_c1-pad2_ 7.2k
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222
+q3 net-_c1-pad2_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+r4  net-_q3-pad3_ net-_d1-pad1_ 800
+c1  net-_c1-pad1_ net-_c1-pad2_ capacitor_polarised
+q6 net-_c1-pad1_ net-_c1-pad2_ net-_d1-pad1_ Q2N2222
+q9 net-_c2-pad2_ net-_q9-pad2_ net-_d1-pad1_ Q2N2222
+r7  net-_q1-pad1_ net-_q9-pad2_ 1k
+d1 net-_d1-pad1_ net-_c2-pad2_ 1N4148
+* u1  net-_c2-pad1_ net-_q2-pad2_ net-_d1-pad1_ port
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.pro b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.sch b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.sch
new file mode 100644
index 00000000..4fa3fe5d
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.sch
@@ -0,0 +1,555 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TL432-PORT-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q2
+U 1 1 66BB02B4
+P 2950 2350
+F 0 "Q2" H 2850 2400 50  0000 R CNN
+F 1 "eSim_NPN" H 2900 2500 50  0000 R CNN
+F 2 "" H 3150 2450 29  0000 C CNN
+F 3 "" H 2950 2350 60  0000 C CNN
+	1    2950 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 66BB02B5
+P 3800 2550
+F 0 "Q4" H 3700 2600 50  0000 R CNN
+F 1 "eSim_NPN" H 3750 2700 50  0000 R CNN
+F 2 "" H 4000 2650 29  0000 C CNN
+F 3 "" H 3800 2550 60  0000 C CNN
+	1    3800 2550
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R5
+U 1 1 66BB02B6
+P 4550 2050
+F 0 "R5" H 4600 2180 50  0000 C CNN
+F 1 "800" H 4600 2000 50  0000 C CNN
+F 2 "" H 4600 2030 30  0000 C CNN
+F 3 "" V 4600 2100 30  0000 C CNN
+	1    4550 2050
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_PNP Q7
+U 1 1 66BB02B7
+P 4900 2600
+F 0 "Q7" H 4800 2650 50  0000 R CNN
+F 1 "eSim_PNP" H 4850 2750 50  0000 R CNN
+F 2 "" H 5100 2700 29  0000 C CNN
+F 3 "" H 4900 2600 60  0000 C CNN
+	1    4900 2600
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_PNP Q8
+U 1 1 66BB02B8
+P 5600 2600
+F 0 "Q8" H 5500 2650 50  0000 R CNN
+F 1 "eSim_PNP" H 5550 2750 50  0000 R CNN
+F 2 "" H 5800 2700 29  0000 C CNN
+F 3 "" H 5600 2600 60  0000 C CNN
+	1    5600 2600
+	1    0    0    1   
+$EndComp
+$Comp
+L resistor R8
+U 1 1 66BB02B9
+P 5900 2100
+F 0 "R8" H 5950 2230 50  0000 C CNN
+F 1 "800" H 5950 2050 50  0000 C CNN
+F 2 "" H 5950 2080 30  0000 C CNN
+F 3 "" V 5950 2150 30  0000 C CNN
+	1    5900 2100
+	0    1    1    0   
+$EndComp
+$Comp
+L capacitor_polarised C2
+U 1 1 66BB02BA
+P 6650 2350
+F 0 "C2" H 6675 2450 50  0000 L CNN
+F 1 "20p" H 6675 2250 50  0000 L CNN
+F 2 "" H 6650 2350 50  0001 C CNN
+F 3 "" H 6650 2350 50  0001 C CNN
+	1    6650 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 66BB02BB
+P 7250 2800
+F 0 "Q10" H 7150 2850 50  0000 R CNN
+F 1 "eSim_NPN" H 7200 2950 50  0000 R CNN
+F 2 "" H 7450 2900 29  0000 C CNN
+F 3 "" H 7250 2800 60  0000 C CNN
+	1    7250 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R9
+U 1 1 66BB02BC
+P 7900 3150
+F 0 "R9" H 7950 3280 50  0000 C CNN
+F 1 "150" H 7950 3100 50  0000 C CNN
+F 2 "" H 7950 3130 30  0000 C CNN
+F 3 "" V 7950 3200 30  0000 C CNN
+	1    7900 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R10
+U 1 1 66BB02BD
+P 8350 3500
+F 0 "R10" H 8400 3630 50  0000 C CNN
+F 1 "10k" H 8400 3450 50  0000 C CNN
+F 2 "" H 8400 3480 30  0000 C CNN
+F 3 "" V 8400 3550 30  0000 C CNN
+	1    8350 3500
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q11
+U 1 1 66BB02BE
+P 8750 3100
+F 0 "Q11" H 8650 3150 50  0000 R CNN
+F 1 "eSim_NPN" H 8700 3250 50  0000 R CNN
+F 2 "" H 8950 3200 29  0000 C CNN
+F 3 "" H 8750 3100 60  0000 C CNN
+	1    8750 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 66BB02BF
+P 9400 3050
+F 0 "D2" H 9400 3150 50  0000 C CNN
+F 1 "eSim_Diode" H 9400 2950 50  0000 C CNN
+F 2 "" H 9400 3050 60  0000 C CNN
+F 3 "" H 9400 3050 60  0000 C CNN
+	1    9400 3050
+	0    -1   -1   0   
+$EndComp
+$Comp
+L resistor R2
+U 1 1 66BB02C0
+P 3300 3250
+F 0 "R2" H 3350 3380 50  0000 C CNN
+F 1 "3.28k" H 3350 3200 50  0000 C CNN
+F 2 "" H 3350 3230 30  0000 C CNN
+F 3 "" V 3350 3300 30  0000 C CNN
+	1    3300 3250
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 66BB02C1
+P 4700 3300
+F 0 "Q5" H 4600 3350 50  0000 R CNN
+F 1 "eSim_NPN" H 4650 3450 50  0000 R CNN
+F 2 "" H 4900 3400 29  0000 C CNN
+F 3 "" H 4700 3300 60  0000 C CNN
+	1    4700 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R6
+U 1 1 66BB02C2
+P 4750 3850
+F 0 "R6" H 4800 3980 50  0000 C CNN
+F 1 "4k" H 4800 3800 50  0000 C CNN
+F 2 "" H 4800 3830 30  0000 C CNN
+F 3 "" V 4800 3900 30  0000 C CNN
+	1    4750 3850
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R1
+U 1 1 66BB02C3
+P 2700 4300
+F 0 "R1" H 2750 4430 50  0000 C CNN
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+F 2 "" H 2750 4280 30  0000 C CNN
+F 3 "" V 2750 4350 30  0000 C CNN
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+	0    1    1    0   
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+L resistor R3
+U 1 1 66BB02C4
+P 3800 4350
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+F 2 "" H 3850 4330 30  0000 C CNN
+F 3 "" V 3850 4400 30  0000 C CNN
+	1    3800 4350
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+$EndComp
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+U 1 1 66BB02C5
+P 2900 5150
+F 0 "Q1" H 2800 5200 50  0000 R CNN
+F 1 "eSim_NPN" H 2850 5300 50  0000 R CNN
+F 2 "" H 3100 5250 29  0000 C CNN
+F 3 "" H 2900 5150 60  0000 C CNN
+	1    2900 5150
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 66BB02C6
+P 3750 5150
+F 0 "Q3" H 3650 5200 50  0000 R CNN
+F 1 "eSim_NPN" H 3700 5300 50  0000 R CNN
+F 2 "" H 3950 5250 29  0000 C CNN
+F 3 "" H 3750 5150 60  0000 C CNN
+	1    3750 5150
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R4
+U 1 1 66BB02C7
+P 3850 5800
+F 0 "R4" H 3900 5930 50  0000 C CNN
+F 1 "800" H 3900 5750 50  0000 C CNN
+F 2 "" H 3900 5780 30  0000 C CNN
+F 3 "" V 3900 5850 30  0000 C CNN
+	1    3850 5800
+	0    1    1    0   
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+$Comp
+L capacitor_polarised C1
+U 1 1 66BB02C8
+P 4400 4600
+F 0 "C1" H 4425 4700 50  0000 L CNN
+F 1 "capacitor_polarised" H 4425 4500 50  0000 L CNN
+F 2 "" H 4400 4600 50  0001 C CNN
+F 3 "" H 4400 4600 50  0001 C CNN
+	1    4400 4600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 66BB02C9
+P 4750 5250
+F 0 "Q6" H 4650 5300 50  0000 R CNN
+F 1 "eSim_NPN" H 4700 5400 50  0000 R CNN
+F 2 "" H 4950 5350 29  0000 C CNN
+F 3 "" H 4750 5250 60  0000 C CNN
+	1    4750 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 66BB02CA
+P 5700 5750
+F 0 "Q9" H 5600 5800 50  0000 R CNN
+F 1 "eSim_NPN" H 5650 5900 50  0000 R CNN
+F 2 "" H 5900 5850 29  0000 C CNN
+F 3 "" H 5700 5750 60  0000 C CNN
+	1    5700 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R7
+U 1 1 66BB02CB
+P 5100 5800
+F 0 "R7" H 5150 5930 50  0000 C CNN
+F 1 "1k" H 5150 5750 50  0000 C CNN
+F 2 "" H 5150 5780 30  0000 C CNN
+F 3 "" V 5150 5850 30  0000 C CNN
+	1    5100 5800
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+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 66BB02CC
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+F 2 "" H 6300 4850 60  0000 C CNN
+F 3 "" H 6300 4850 60  0000 C CNN
+	1    6300 4850
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+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	2750 3850 3850 3850
+Wire Wire Line
+	3350 3850 3350 3450
+Wire Wire Line
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+Connection ~ 3350 3850
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	3850 4950 3850 4550
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2800 4800
+Connection ~ 3150 5150
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4600 1600
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4800 2900
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+Wire Wire Line
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+Connection ~ 5950 1600
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3850 4850
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4400 4850
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+Wire Wire Line
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+Connection ~ 3750 6000
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3450 5150
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+Wire Wire Line
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+Connection ~ 5700 2950
+Wire Wire Line
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+Wire Wire Line
+	5800 3150 7050 3150
+Connection ~ 5800 3150
+Wire Wire Line
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+Connection ~ 6300 3150
+Wire Wire Line
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+Connection ~ 4850 6150
+Wire Wire Line
+	6300 6150 6300 5000
+Connection ~ 5800 6150
+Wire Wire Line
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+Connection ~ 6650 3150
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+Connection ~ 6650 1600
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8400 3100
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8850 1600
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8850 6150
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8850 3900
+$Comp
+L PORT U1
+U 1 1 66BB02CD
+P 1800 1600
+F 0 "U1" H 1850 1700 30  0000 C CNN
+F 1 "PORT" H 1800 1600 30  0000 C CNN
+F 2 "" H 1800 1600 60  0000 C CNN
+F 3 "" H 1800 1600 60  0000 C CNN
+	1    1800 1600
+	1    0    0    -1  
+$EndComp
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+Wire Wire Line
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+Connection ~ 2500 2350
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2800 6000
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+F 1 "PORT" H 1600 2300 30  0000 C CNN
+F 2 "" H 1600 2300 60  0000 C CNN
+F 3 "" H 1600 2300 60  0000 C CNN
+	2    1600 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
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+P 1350 5650
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+F 1 "PORT" H 1350 5650 30  0000 C CNN
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+F 3 "" H 1350 5650 60  0000 C CNN
+	3    1350 5650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.sub b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.sub
new file mode 100644
index 00000000..eb174961
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT.sub
@@ -0,0 +1,34 @@
+* Subcircuit TL431-PORT
+.subckt TL431-PORT net-_c2-pad1_ net-_q2-pad2_ net-_d1-pad1_ 
+* c:\fossee2\esim\library\subcircuitlibrary\tl431-port\tl431-port.cir
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q2 net-_c2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 net-_c2-pad2_ net-_c2-pad2_ net-_q2-pad2_ Q2N2222
+r5  net-_c2-pad1_ net-_q7-pad3_ 800
+q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
+q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A
+r8  net-_c2-pad1_ net-_q8-pad3_ 800
+c2  net-_c2-pad1_ net-_c2-pad2_ 20p
+q10 net-_c2-pad1_ net-_c2-pad2_ net-_q10-pad3_ Q2N2222
+r9  net-_q10-pad3_ net-_q11-pad2_ 150
+r10  net-_q11-pad2_ net-_d1-pad1_ 10k
+q11 net-_c2-pad1_ net-_q11-pad2_ net-_d1-pad1_ Q2N2222
+d2 net-_d1-pad1_ net-_c2-pad1_ 1N4148
+r2  net-_q2-pad3_ net-_r1-pad1_ 3.28k
+q5 net-_q5-pad1_ net-_q2-pad3_ net-_q5-pad3_ Q2N2222
+r6  net-_q5-pad3_ net-_c1-pad1_ 4k
+r1  net-_r1-pad1_ net-_q1-pad1_ 2.4k
+r3  net-_r1-pad1_ net-_c1-pad2_ 7.2k
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222
+q3 net-_c1-pad2_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+r4  net-_q3-pad3_ net-_d1-pad1_ 800
+c1  net-_c1-pad1_ net-_c1-pad2_ capacitor_polarised
+q6 net-_c1-pad1_ net-_c1-pad2_ net-_d1-pad1_ Q2N2222
+q9 net-_c2-pad2_ net-_q9-pad2_ net-_d1-pad1_ Q2N2222
+r7  net-_q1-pad1_ net-_q9-pad2_ 1k
+d1 net-_d1-pad1_ net-_c2-pad2_ 1N4148
+* Control Statements
+
+.ends TL431-PORT
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TL431_SUB/TL431-PORT_Previous_Values.xml b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT_Previous_Values.xml
new file mode 100644
index 00000000..10cc4a70
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/TL431-PORT_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q8><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q10><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><d2><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q5><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q1><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q3><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q9><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><d1><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TL431_SUB/analysis b/library/SubcircuitLibrary/TL431_SUB/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03
\ No newline at end of file