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* c:\fossee\esim\library\subcircuitlibrary\sn7483a_sub\sn7483a_sub.cir
.include 3_and.sub
.include 4_OR.sub
.include 4_and.sub
.include 5_and.sub
* u23 net-_u12-pad3_ net-_u23-pad2_ d_buffer
* u24 net-_u15-pad1_ net-_u11-pad3_ net-_u24-pad3_ d_and
x1 net-_u13-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_x1-pad4_ 3_and
x2 net-_u14-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_x2-pad5_ 4_and
x4 net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u36-pad2_ 5_and
x8 net-_u23-pad2_ net-_u24-pad3_ net-_x1-pad4_ net-_x2-pad5_ net-_u36-pad1_ 4_OR
* u36 net-_u36-pad1_ net-_u36-pad2_ net-_u36-pad3_ d_or
* u40 net-_u36-pad3_ net-_u40-pad2_ d_inverter
* u26 net-_u11-pad3_ net-_u16-pad2_ net-_u26-pad3_ d_and
* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter
* u27 net-_u15-pad1_ net-_u27-pad2_ d_buffer
* u29 net-_u13-pad1_ net-_u21-pad1_ net-_u29-pad3_ d_and
x5 net-_u14-pad1_ net-_u21-pad1_ net-_u17-pad1_ net-_x5-pad4_ 3_and
x6 net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_x6-pad5_ 4_and
x7 net-_u27-pad2_ net-_u29-pad3_ net-_x5-pad4_ net-_x6-pad5_ net-_u35-pad1_ 4_OR
* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter
* u39 net-_u26-pad3_ net-_u35-pad2_ net-_u39-pad3_ d_xor
* u21 net-_u21-pad1_ net-_u15-pad2_ net-_u21-pad3_ d_and
* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
* u22 net-_u13-pad1_ net-_u22-pad2_ d_buffer
* u28 net-_u14-pad1_ net-_u17-pad1_ net-_u28-pad3_ d_and
x3 net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u33-pad2_ 3_and
* u30 net-_u22-pad2_ net-_u28-pad3_ net-_u30-pad3_ d_or
* u33 net-_u30-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
* u41 net-_u21-pad3_ net-_u37-pad2_ net-_u41-pad3_ d_xor
* u17 net-_u17-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_and
* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
* u18 net-_u14-pad1_ net-_u18-pad2_ d_buffer
* u25 net-_u19-pad1_ net-_u10-pad2_ net-_u25-pad3_ d_and
* u19 net-_u19-pad1_ net-_u14-pad2_ net-_u19-pad3_ d_and
* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
* u34 net-_u31-pad3_ net-_u34-pad2_ d_inverter
* u38 net-_u17-pad3_ net-_u34-pad2_ net-_u38-pad3_ d_xor
* u32 net-_u19-pad3_ net-_u20-pad2_ net-_u32-pad3_ d_xor
* u31 net-_u18-pad2_ net-_u25-pad3_ net-_u31-pad3_ d_or
* u20 net-_u10-pad2_ net-_u20-pad2_ d_inverter
* u37 net-_u33-pad3_ net-_u37-pad2_ d_inverter
* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
* u12 net-_u11-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_nor
* u8 net-_u2-pad11_ net-_u2-pad12_ net-_u21-pad1_ d_nand
* u9 net-_u2-pad11_ net-_u2-pad12_ net-_u15-pad1_ d_nor
* u4 net-_u2-pad13_ net-_u2-pad14_ net-_u17-pad1_ d_nand
* u5 net-_u2-pad13_ net-_u2-pad14_ net-_u13-pad1_ d_nor
* u6 net-_u2-pad15_ net-_u2-pad16_ net-_u19-pad1_ d_nand
* u7 net-_u2-pad15_ net-_u2-pad16_ net-_u14-pad1_ d_nor
* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8
* u3 net-_u1-pad7_ net-_u10-pad1_ adc_bridge_1
* u42 net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ dac_bridge_5
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
a1 net-_u12-pad3_ net-_u23-pad2_ u23
a2 [net-_u15-pad1_ net-_u11-pad3_ ] net-_u24-pad3_ u24
a3 [net-_u36-pad1_ net-_u36-pad2_ ] net-_u36-pad3_ u36
a4 net-_u36-pad3_ net-_u40-pad2_ u40
a5 [net-_u11-pad3_ net-_u16-pad2_ ] net-_u26-pad3_ u26
a6 net-_u12-pad3_ net-_u16-pad2_ u16
a7 net-_u15-pad1_ net-_u27-pad2_ u27
a8 [net-_u13-pad1_ net-_u21-pad1_ ] net-_u29-pad3_ u29
a9 net-_u35-pad1_ net-_u35-pad2_ u35
a10 [net-_u26-pad3_ net-_u35-pad2_ ] net-_u39-pad3_ u39
a11 [net-_u21-pad1_ net-_u15-pad2_ ] net-_u21-pad3_ u21
a12 net-_u15-pad1_ net-_u15-pad2_ u15
a13 net-_u13-pad1_ net-_u22-pad2_ u22
a14 [net-_u14-pad1_ net-_u17-pad1_ ] net-_u28-pad3_ u28
a15 [net-_u22-pad2_ net-_u28-pad3_ ] net-_u30-pad3_ u30
a16 [net-_u30-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
a17 [net-_u21-pad3_ net-_u37-pad2_ ] net-_u41-pad3_ u41
a18 [net-_u17-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17
a19 net-_u13-pad1_ net-_u13-pad2_ u13
a20 net-_u14-pad1_ net-_u18-pad2_ u18
a21 [net-_u19-pad1_ net-_u10-pad2_ ] net-_u25-pad3_ u25
a22 [net-_u19-pad1_ net-_u14-pad2_ ] net-_u19-pad3_ u19
a23 net-_u14-pad1_ net-_u14-pad2_ u14
a24 net-_u31-pad3_ net-_u34-pad2_ u34
a25 [net-_u17-pad3_ net-_u34-pad2_ ] net-_u38-pad3_ u38
a26 [net-_u19-pad3_ net-_u20-pad2_ ] net-_u32-pad3_ u32
a27 [net-_u18-pad2_ net-_u25-pad3_ ] net-_u31-pad3_ u31
a28 net-_u10-pad2_ net-_u20-pad2_ u20
a29 net-_u33-pad3_ net-_u37-pad2_ u37
a30 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
a31 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12
a32 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u21-pad1_ u8
a33 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u15-pad1_ u9
a34 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u17-pad1_ u4
a35 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u13-pad1_ u5
a36 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u19-pad1_ u6
a37 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u14-pad1_ u7
a38 net-_u10-pad1_ net-_u10-pad2_ u10
a39 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ ] [net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2
a40 [net-_u1-pad7_ ] [net-_u10-pad1_ ] u3
a41 [net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ ] u42
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u30 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u38 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nor, NgSpice Name: d_nor
.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nor, NgSpice Name: d_nor
.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nor, NgSpice Name: d_nor
.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nor, NgSpice Name: d_nor
.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge
.model u42 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
.tran 0e-00 0e-00 0e-00
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
|
