adding kicad analog and digital circuits

15 files changed, 592 insertions, 0 deletions

diff --git a/digital ciruits/or_sub/Logic_Gates.bck b/digital ciruits/or_sub/Logic_Gates.bck
new file mode 100644
index 0000000..5dd71cb
--- /dev/null
+++ b/digital ciruits/or_sub/Logic_Gates.bck
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0

+#

+#End Doc Library

diff --git a/digital ciruits/or_sub/Logic_Gates.dcm b/digital ciruits/or_sub/Logic_Gates.dcm
new file mode 100644
index 0000000..5dd71cb
--- /dev/null
+++ b/digital ciruits/or_sub/Logic_Gates.dcm
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0

+#

+#End Doc Library

diff --git a/digital ciruits/or_sub/Logic_Gates.lib b/digital ciruits/or_sub/Logic_Gates.lib
new file mode 100644
index 0000000..37a3300
--- /dev/null
+++ b/digital ciruits/or_sub/Logic_Gates.lib
@@ -0,0 +1,20 @@
+EESchema-LIBRARY Version 2.4

+#encoding utf-8

+#

+# OR

+#

+DEF OR X 0 40 Y Y 1 F N

+F0 "X" 0 50 50 H V C CNN

+F1 "OR" 0 -50 50 H V C CNN

+F2 "" 0 0 50 H I C CNN

+F3 "" 0 0 50 H I C CNN

+DRAW

+S -200 150 200 -200 0 1 0 N

+X A 1 -400 100 200 R 50 39 1 1 I

+X B 2 -400 -100 200 R 50 39 1 1 I

+X OUT 3 400 -150 200 L 50 39 1 1 O

+X VDD 4 400 100 200 L 50 39 1 1 I

+ENDDRAW

+ENDDEF

+#

+#End Library

diff --git a/digital ciruits/or_sub/b3v33check.log b/digital ciruits/or_sub/b3v33check.log
new file mode 100644
index 0000000..27ec4ed
--- /dev/null
+++ b/digital ciruits/or_sub/b3v33check.log
@@ -0,0 +1,4 @@
+BSIM3v3.3.0 Parameter Checking.

+Model = mpmos

+Warning: Pd = 0 is less than W.

+Warning: Ps = 0 is less than W.

diff --git a/digital ciruits/or_sub/basic_logicgates.bck b/digital ciruits/or_sub/basic_logicgates.bck
new file mode 100644
index 0000000..5dd71cb
--- /dev/null
+++ b/digital ciruits/or_sub/basic_logicgates.bck
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0

+#

+#End Doc Library

diff --git a/digital ciruits/or_sub/basic_logicgates.dcm b/digital ciruits/or_sub/basic_logicgates.dcm
new file mode 100644
index 0000000..5dd71cb
--- /dev/null
+++ b/digital ciruits/or_sub/basic_logicgates.dcm
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0

+#

+#End Doc Library

diff --git a/digital ciruits/or_sub/or_sub-cache.lib b/digital ciruits/or_sub/or_sub-cache.lib
new file mode 100644
index 0000000..3c0f171
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub-cache.lib
@@ -0,0 +1,81 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Device:R
+#
+DEF Device:R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "Device:R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# or_sub-rescue:OR-Logic_Gates
+#
+DEF or_sub-rescue:OR-Logic_Gates X 0 40 Y Y 1 F N
+F0 "X" 0 50 50 H V C CNN
+F1 "or_sub-rescue:OR-Logic_Gates" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -200 150 200 -200 0 1 0 N
+X A 1 -400 100 200 R 50 39 1 1 I
+X B 2 -400 -100 200 R 50 39 1 1 I
+X OUT 3 400 -150 200 L 50 39 1 1 O
+X VDD 4 400 100 200 L 50 39 1 1 I
+ENDDRAW
+ENDDEF
+#
+# power:GND
+#
+DEF power:GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power:GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power:VDD
+#
+DEF power:VDD #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power:VDD" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VDD 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pspice:VSOURCE
+#
+DEF pspice:VSOURCE V 0 40 Y Y 1 F N
+F0 "V" -250 300 50 H V C CNN
+F1 "pspice:VSOURCE" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 0 200 0 1 0 N
+T 0 -320 -10 50 0 0 1 V Normal 0 C C
+P 2 0 1 0 -250 -250 -250 150 F
+P 3 0 1 0 -300 150 -250 250 -200 150 F
+X E1 1 0 300 100 D 50 50 1 1 I
+X E2 2 0 -300 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/or_sub/or_sub-rescue.dcm b/digital ciruits/or_sub/or_sub-rescue.dcm
new file mode 100644
index 0000000..5f3ed79
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub-rescue.dcm
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/or_sub/or_sub-rescue.lib b/digital ciruits/or_sub/or_sub-rescue.lib
new file mode 100644
index 0000000..a170803
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub-rescue.lib
@@ -0,0 +1,20 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# OR-Logic_Gates
+#
+DEF OR-Logic_Gates X 0 40 Y Y 1 F N
+F0 "X" 0 50 50 H V C CNN
+F1 "OR-Logic_Gates" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -200 150 200 -200 0 1 0 N
+X A 1 -400 100 200 R 50 39 1 1 I
+X B 2 -400 -100 200 R 50 39 1 1 I
+X OUT 3 400 -150 200 L 50 39 1 1 O
+X VDD 4 400 100 200 L 50 39 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/or_sub/or_sub.bak b/digital ciruits/or_sub/or_sub.bak
new file mode 100644
index 0000000..3d55da0
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub.bak
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+EESchema Schematic File Version 4
+LIBS:or_sub-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+F 7 "/home/akshay/Desktop/digital ciruits/libs/fossee_spice_models.lib" H 5200 2800 50  0001 C CNN "Spice_Lib_File"
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diff --git a/digital ciruits/or_sub/or_sub.cir b/digital ciruits/or_sub/or_sub.cir
new file mode 100644
index 0000000..4724833
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub.cir
@@ -0,0 +1,9 @@
+.title KiCad schematic
+.include "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib"
+X1 a b out VDD OR
+V1 a GND dc 0 pulse(0 3.3 0 0 0 50m 100m)
+V2 b GND dc 0 pulse(0 3.3 50m 0 0 50m 100m)
+V3 VDD GND dc 3.3
+R1 out GND 10meg
+.tran .25m 30m
+.end
diff --git a/digital ciruits/or_sub/or_sub.kicad_pcb b/digital ciruits/or_sub/or_sub.kicad_pcb
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub.kicad_pcb
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+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/digital ciruits/or_sub/or_sub.pro b/digital ciruits/or_sub/or_sub.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/digital ciruits/or_sub/or_sub.sch b/digital ciruits/or_sub/or_sub.sch
new file mode 100644
index 0000000..cc5bcaf
--- /dev/null
+++ b/digital ciruits/or_sub/or_sub.sch
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+LIBS:or_sub-cache
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+EELAYER END
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+encoding utf-8
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+Text GLabel 3150 2250 0    50   Input ~ 0
+a
+Text GLabel 3850 2750 0    50   Input ~ 0
+b
+Wire Wire Line
+	3150 2250 3150 2450
+Connection ~ 3150 2450
+Wire Wire Line
+	3150 2450 2950 2450
+Wire Wire Line
+	3850 2750 3850 2850
+Connection ~ 3850 2850
+Wire Wire Line
+	3850 2850 4800 2850
+Text Notes 6500 5000 0    50   ~ 0
+.tran .25m 30m
+$EndSCHEMATC
diff --git a/digital ciruits/or_sub/sym-lib-table b/digital ciruits/or_sub/sym-lib-table
new file mode 100644
index 0000000..905d1e2
--- /dev/null
+++ b/digital ciruits/or_sub/sym-lib-table
@@ -0,0 +1,5 @@
+(sym_lib_table
+  (lib (name basic_logicgates)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/or_sub/basic_logicgates.lib)(options "")(descr ""))
+  (lib (name Logic_Gates)(type Legacy)(uri C:/Users/Mind/Downloads/Kicad/Project/or_sub/Logic_Gates.lib)(options "")(descr ""))
+  (lib (name or_sub-rescue)(type Legacy)(uri ${KIPRJMOD}/or_sub-rescue.lib)(options "")(descr ""))
+)