adding kicad analog and digital circuits

7 files changed, 654 insertions, 0 deletions

diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB-cache.lib b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB-cache.lib
new file mode 100644
index 0000000..49fc6b3
--- /dev/null
+++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB-cache.lib
@@ -0,0 +1,69 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Device:R
+#
+DEF Device:R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "Device:R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# basic_gates:jkff
+#
+DEF basic_gates:jkff X 0 40 Y Y 1 F N
+F0 "X" 0 -350 50 H V C CNN
+F1 "basic_gates:jkff" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -350 250 350 -300 0 1 0 N
+X J 1 -450 200 100 R 50 50 1 1 I
+X clk 2 -450 0 100 R 50 50 1 1 I
+X k 3 -450 -200 100 R 50 50 1 1 I
+X vdd 4 0 350 100 D 50 50 1 1 O
+X q 5 450 150 100 L 50 50 1 1 O
+X nq 6 450 -200 100 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# power:GND
+#
+DEF power:GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power:GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pspice:VSOURCE
+#
+DEF pspice:VSOURCE V 0 40 Y Y 1 F N
+F0 "V" -250 300 50 H V C CNN
+F1 "pspice:VSOURCE" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 0 200 0 1 0 N
+T 0 -320 -10 50 0 0 1 V Normal 0 C C
+P 2 0 1 0 -250 -250 -250 150 F
+P 3 0 1 0 -300 150 -250 250 -200 150 F
+X E1 1 0 300 100 D 50 50 1 1 I
+X E2 2 0 -300 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.bak b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.bak
new file mode 100644
index 0000000..0db1d6a
--- /dev/null
+++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.bak
@@ -0,0 +1,268 @@
+EESchema Schematic File Version 4
+LIBS:JK_FLL_SUB-cache
+EELAYER 26 0
+EELAYER END
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+encoding utf-8
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+F 6 "Y" H 5500 3950 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "/home/akshay/kicad_examples/masterslave_jkff/masterslave_jkff.sub" H 5500 3950 50  0001 C CNN "Spice_Lib_File"
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diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.cir b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.cir
new file mode 100644
index 0000000..031d2b3
--- /dev/null
+++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.cir
@@ -0,0 +1,11 @@
+.title KiCad schematic
+.include "/home/akshay/kicad_examples/masterslave_jkff/masterslave_jkff.sub"
+X1 j clk k vdd q0 q1 JKFLIPFLOP
+V1 j GND dc 3.3
+V2 clk GND dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3)
+V3 k GND dc 3.3
+V4 vdd GND dc 3.3
+R1 GND q0 10meg
+R2 GND q1 10meg
+.tran .25m 30m
+.end
diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.kicad_pcb b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.kicad_pcb
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.kicad_pcb
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.pro b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.sch b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.sch
new file mode 100644
index 0000000..9a87a0b
--- /dev/null
+++ b/digital ciruits/JK_FLL_SUB/JK_FLL_SUB.sch
@@ -0,0 +1,268 @@
+EESchema Schematic File Version 4
+LIBS:JK_FLL_SUB-cache
+EELAYER 26 0
+EELAYER END
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+encoding utf-8
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+Wire Wire Line
+	3900 3400 3900 3100
+Wire Wire Line
+	4700 3100 4700 3650
+Wire Wire Line
+	4700 3650 3900 3650
+Wire Wire Line
+	3900 3650 3900 3950
+Wire Wire Line
+	3900 3950 5050 3950
+Wire Wire Line
+	3900 3100 4700 3100
+$Comp
+L Device:R R2
+U 1 1 5B2B6E7D
+P 7250 4200
+F 0 "R2" V 7043 4200 50  0000 C CNN
+F 1 "10meg" V 7134 4200 50  0000 C CNN
+F 2 "" V 7180 4200 50  0001 C CNN
+F 3 "~" H 7250 4200 50  0001 C CNN
+	1    7250 4200
+	0    1    1    0   
+$EndComp
+$Comp
+L power:GND #PWR0101
+U 1 1 5B2B6EB2
+P 7550 4200
+F 0 "#PWR0101" H 7550 3950 50  0001 C CNN
+F 1 "GND" H 7555 4027 50  0000 C CNN
+F 2 "" H 7550 4200 50  0001 C CNN
+F 3 "" H 7550 4200 50  0001 C CNN
+	1    7550 4200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7550 4200 7400 4200
+Wire Wire Line
+	7100 4200 6950 4200
+Wire Wire Line
+	5950 4200 5950 4150
+Text GLabel 6800 4050 0    50   Output ~ 0
+q1
+Wire Wire Line
+	6800 4050 6950 4050
+Wire Wire Line
+	6950 4050 6950 4200
+Connection ~ 6950 4200
+Wire Wire Line
+	6950 4200 5950 4200
+$EndSCHEMATC
diff --git a/digital ciruits/JK_FLL_SUB/sym-lib-table b/digital ciruits/JK_FLL_SUB/sym-lib-table
new file mode 100644
index 0000000..c79a55b
--- /dev/null
+++ b/digital ciruits/JK_FLL_SUB/sym-lib-table
@@ -0,0 +1,4 @@
+(sym_lib_table
+  (lib (name basic_gates)(type Legacy)(uri /home/akshay/kicad_examples/and_sub/basic_gates.lib)(options "")(descr ""))
+  (lib (name sim_logic)(type Legacy)(uri /home/akshay/Downloads/kicad-simulation-examples-master/libs/sim_logic.lib)(options "")(descr ""))
+)