diff options
author | Akshay NH | 2018-06-28 19:22:03 +0530 |
---|---|---|
committer | Akshay NH | 2018-06-28 19:22:03 +0530 |
commit | d1edc2c0c9b8d823892b94482e01451e82c3eec1 (patch) | |
tree | 9fb54dfd93a975be8b2a8cb29b21eb5639ac29ef /analog circuits/ac to dc converter | |
download | eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.gz eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.bz2 eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.zip |
adding kicad analog and digital circuits
Diffstat (limited to 'analog circuits/ac to dc converter')
8 files changed, 725 insertions, 0 deletions
diff --git a/analog circuits/ac to dc converter/ZenerD1N750.lib b/analog circuits/ac to dc converter/ZenerD1N750.lib new file mode 100755 index 0000000..890c37f --- /dev/null +++ b/analog circuits/ac to dc converter/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/analog circuits/ac to dc converter/ac to dc converter-cache.lib b/analog circuits/ac to dc converter/ac to dc converter-cache.lib new file mode 100644 index 0000000..44a8ec5 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:D_Zener +# +DEF Device:D_Zener D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device:D_Zener" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 0 50 0 -50 0 N +P 3 0 1 8 -50 -50 -50 50 -30 50 N +P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# rectifier_schlib:D +# +DEF rectifier_schlib:D D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "rectifier_schlib:D" 0 -100 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + Diode_* + D-Pak_TO252AA + *SingleDiode + *_Diode_* + *SingleDiode* +$ENDFPLIST +DRAW +P 2 0 1 6 -50 50 -50 -50 N +P 3 0 1 0 50 50 -50 0 50 -50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/ac to dc converter/ac to dc converter.bak b/analog circuits/ac to dc converter/ac to dc converter.bak new file mode 100644 index 0000000..99fa2e0 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.bak @@ -0,0 +1,267 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0CF0CE +P 2750 4550 +F 0 "V1" H 2978 4596 50 0000 L CNN +F 1 "VSOURCE" H 2978 4505 50 0000 L CNN +F 2 "" H 2750 4550 50 0001 C CNN +F 3 "" H 2750 4550 50 0001 C CNN +F 4 "V" H 2750 4550 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 200)" H 2750 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2750 4550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2750 4550 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0CF1A2 +P 3950 3600 +F 0 "R1" V 3743 3600 50 0000 C CNN +F 1 "470k" V 3834 3600 50 0000 C CNN +F 2 "" V 3880 3600 50 0001 C CNN +F 3 "~" H 3950 3600 50 0001 C CNN + 1 3950 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0CF208 +P 3950 3950 +F 0 "C1" V 3698 3950 50 0000 C CNN +F 1 "22u" V 3789 3950 50 0000 C CNN +F 2 "" H 3988 3800 50 0001 C CNN +F 3 "~" H 3950 3950 50 0001 C CNN + 1 3950 3950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0CF246 +P 4350 5250 +F 0 "R2" V 4143 5250 50 0000 C CNN +F 1 "100" V 4234 5250 50 0000 C CNN +F 2 "" V 4280 5250 50 0001 C CNN +F 3 "~" H 4350 5250 50 0001 C CNN + 1 4350 5250 + 0 1 1 0 +$EndComp +$Comp +L Device:D_ALT D1 +U 1 1 5B0CF2C8 +P 5500 4300 +F 0 "D1" H 5500 4516 50 0000 C CNN +F 1 "D_ALT" H 5500 4425 50 0000 C CNN +F 2 "" H 5500 4300 50 0001 C CNN +F 3 "~" H 5500 4300 50 0001 C CNN + 1 5500 4300 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D3 +U 1 1 5B0CF325 +P 6300 4300 +F 0 "D3" H 6300 4516 50 0000 C CNN +F 1 "D_ALT" H 6300 4425 50 0000 C CNN +F 2 "" H 6300 4300 50 0001 C CNN +F 3 "~" H 6300 4300 50 0001 C CNN + 1 6300 4300 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D4 +U 1 1 5B0CF37B +P 6300 4700 +F 0 "D4" H 6300 4916 50 0000 C CNN +F 1 "D_ALT" H 6300 4825 50 0000 C CNN +F 2 "" H 6300 4700 50 0001 C CNN +F 3 "~" H 6300 4700 50 0001 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L Device:D_ALT D2 +U 1 1 5B0CF3C2 +P 5500 4700 +F 0 "D2" H 5500 4916 50 0000 C CNN +F 1 "D_ALT" H 5500 4825 50 0000 C CNN +F 2 "" H 5500 4700 50 0001 C CNN +F 3 "~" H 5500 4700 50 0001 C CNN + 1 5500 4700 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0CF442 +P 7150 4650 +F 0 "C2" H 7035 4604 50 0000 R CNN +F 1 "470u" H 7035 4695 50 0000 R CNN +F 2 "" H 7188 4500 50 0001 C CNN +F 3 "~" H 7150 4650 50 0001 C CNN + 1 7150 4650 + -1 0 0 1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0CF524 +P 8050 4400 +F 0 "R3" V 7843 4400 50 0000 C CNN +F 1 "100" V 7934 4400 50 0000 C CNN +F 2 "" V 7980 4400 50 0001 C CNN +F 3 "~" H 8050 4400 50 0001 C CNN + 1 8050 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 6150 4300 5900 4300 +Wire Wire Line + 5350 4300 5300 4300 +Wire Wire Line + 5300 4300 5300 4500 +Wire Wire Line + 5300 4700 5350 4700 +Wire Wire Line + 5650 4700 5900 4700 +Wire Wire Line + 6450 4700 6450 4550 +Wire Wire Line + 6450 4550 6750 4550 +Wire Wire Line + 6750 4550 6750 4400 +Wire Wire Line + 6750 4400 7150 4400 +Connection ~ 6450 4550 +Wire Wire Line + 6450 4550 6450 4300 +Wire Wire Line + 8200 4400 8400 4400 +Wire Wire Line + 8400 4400 8400 5000 +Wire Wire Line + 8400 5300 7450 5300 +Wire Wire Line + 4950 5300 4950 4500 +Wire Wire Line + 4950 4500 5300 4500 +Connection ~ 5300 4500 +Wire Wire Line + 5300 4500 5300 4700 +Wire Wire Line + 7150 4500 7150 4400 +Connection ~ 7150 4400 +Wire Wire Line + 7150 4400 7900 4400 +Wire Wire Line + 7150 4800 7150 5300 +Connection ~ 7150 5300 +Wire Wire Line + 7150 5300 4950 5300 +Wire Wire Line + 2750 4250 2750 3600 +Wire Wire Line + 2750 3600 3500 3600 +Wire Wire Line + 4100 3600 4250 3600 +Wire Wire Line + 5900 3600 5900 4300 +Connection ~ 5900 4300 +Wire Wire Line + 5900 4300 5650 4300 +Wire Wire Line + 3500 3600 3500 3950 +Wire Wire Line + 3500 3950 3800 3950 +Connection ~ 3500 3600 +Wire Wire Line + 3500 3600 3800 3600 +Wire Wire Line + 4100 3950 4250 3950 +Wire Wire Line + 4250 3950 4250 3600 +Connection ~ 4250 3600 +Wire Wire Line + 4250 3600 5900 3600 +Wire Wire Line + 2750 4850 2750 5250 +Wire Wire Line + 2750 5250 4200 5250 +Wire Wire Line + 4500 5250 4500 5650 +Wire Wire Line + 4500 5650 5900 5650 +Wire Wire Line + 5900 5650 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5900 4700 6150 4700 +Text GLabel 9050 4300 0 50 Output ~ 0 +out +Wire Wire Line + 9050 4300 9800 4300 +Wire Wire Line + 9800 4300 9800 4150 +Wire Wire Line + 9800 4150 8400 4150 +Wire Wire Line + 8400 4150 8400 4400 +Connection ~ 8400 4400 +Text GLabel 2500 3350 0 50 Input ~ 0 +ip +Wire Wire Line + 2500 3350 2750 3350 +Wire Wire Line + 2750 3350 2750 3600 +Connection ~ 2750 3600 +$Comp +L power:GND #PWR0101 +U 1 1 5B0D3840 +P 7450 5550 +F 0 "#PWR0101" H 7450 5300 50 0001 C CNN +F 1 "GND" H 7455 5377 50 0000 C CNN +F 2 "" H 7450 5550 50 0001 C CNN +F 3 "" H 7450 5550 50 0001 C CNN + 1 7450 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 5550 7450 5300 +Connection ~ 7450 5300 +Wire Wire Line + 7450 5300 7150 5300 +$Comp +L Device:D_Zener D5 +U 1 1 5B0D4B1F +P 8400 5150 +F 0 "D5" V 8354 5229 50 0000 L CNN +F 1 "D_Zener" V 8445 5229 50 0000 L CNN +F 2 "" H 8400 5150 50 0001 C CNN +F 3 "~" H 8400 5150 50 0001 C CNN + 1 8400 5150 + 0 1 1 0 +$EndComp +Text GLabel 7050 4050 0 50 Output ~ 0 +vd +Wire Wire Line + 7050 4050 7550 4050 +Wire Wire Line + 7550 4050 7550 3850 +Wire Wire Line + 7550 3850 6750 3850 +Wire Wire Line + 6750 3850 6750 4400 +Connection ~ 6750 4400 +$EndSCHEMATC diff --git a/analog circuits/ac to dc converter/ac to dc converter.cir b/analog circuits/ac to dc converter/ac to dc converter.cir new file mode 100644 index 0000000..0c7dca8 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.cir @@ -0,0 +1,15 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" +V1 ip Net-_R2-Pad2_ sin(0 250) +R1 Net-_C1-Pad1_ ip 470k +C1 Net-_C1-Pad1_ ip 22u +R2 Net-_D2-Pad2_ Net-_R2-Pad2_ 100 +C2 GND vd 470u +R3 out vd 100 +D5 out GND D1N750 +D1 Net-_C1-Pad1_ GND D +D3 vd Net-_C1-Pad1_ D +D4 vd Net-_D2-Pad2_ D +D2 Net-_D2-Pad2_ GND D +.tran .25m 30m +.end diff --git a/analog circuits/ac to dc converter/ac to dc converter.kicad_pcb b/analog circuits/ac to dc converter/ac to dc converter.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/ac to dc converter/ac to dc converter.pro b/analog circuits/ac to dc converter/ac to dc converter.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/ac to dc converter/ac to dc converter.sch b/analog circuits/ac to dc converter/ac to dc converter.sch new file mode 100644 index 0000000..85840c3 --- /dev/null +++ b/analog circuits/ac to dc converter/ac to dc converter.sch @@ -0,0 +1,290 @@ +EESchema Schematic File Version 4 +LIBS:ac to dc converter-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B0CF0CE +P 2750 4550 +F 0 "V1" H 2978 4596 50 0000 L CNN +F 1 "VSOURCE" H 2978 4505 50 0000 L CNN +F 2 "" H 2750 4550 50 0001 C CNN +F 3 "" H 2750 4550 50 0001 C CNN +F 4 "V" H 2750 4550 50 0001 C CNN "Spice_Primitive" +F 5 "sin(0 250)" H 2750 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2750 4550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2750 4550 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B0CF1A2 +P 3950 3600 +F 0 "R1" V 3743 3600 50 0000 C CNN +F 1 "470k" V 3834 3600 50 0000 C CNN +F 2 "" V 3880 3600 50 0001 C CNN +F 3 "~" H 3950 3600 50 0001 C CNN + 1 3950 3600 + 0 1 1 0 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B0CF208 +P 3950 3950 +F 0 "C1" V 3698 3950 50 0000 C CNN +F 1 "22u" V 3789 3950 50 0000 C CNN +F 2 "" H 3988 3800 50 0001 C CNN +F 3 "~" H 3950 3950 50 0001 C CNN + 1 3950 3950 + 0 1 1 0 +$EndComp +$Comp +L Device:R R2 +U 1 1 5B0CF246 +P 4350 5250 +F 0 "R2" V 4143 5250 50 0000 C CNN +F 1 "100" V 4234 5250 50 0000 C CNN +F 2 "" V 4280 5250 50 0001 C CNN +F 3 "~" H 4350 5250 50 0001 C CNN + 1 4350 5250 + 0 1 1 0 +$EndComp +$Comp +L Device:C C2 +U 1 1 5B0CF442 +P 7150 4650 +F 0 "C2" H 7035 4604 50 0000 R CNN +F 1 "470u" H 7035 4695 50 0000 R CNN +F 2 "" H 7188 4500 50 0001 C CNN +F 3 "~" H 7150 4650 50 0001 C CNN + 1 7150 4650 + -1 0 0 1 +$EndComp +$Comp +L Device:R R3 +U 1 1 5B0CF524 +P 8050 4400 +F 0 "R3" V 7843 4400 50 0000 C CNN +F 1 "100" V 7934 4400 50 0000 C CNN +F 2 "" V 7980 4400 50 0001 C CNN +F 3 "~" H 8050 4400 50 0001 C CNN + 1 8050 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 6150 4300 5900 4300 +Wire Wire Line + 5350 4300 5300 4300 +Wire Wire Line + 5300 4300 5300 4500 +Wire Wire Line + 5300 4700 5350 4700 +Wire Wire Line + 5650 4700 5900 4700 +Wire Wire Line + 6450 4550 6750 4550 +Wire Wire Line + 6750 4550 6750 4400 +Wire Wire Line + 6750 4400 7150 4400 +Connection ~ 6450 4550 +Wire Wire Line + 6450 4550 6450 4300 +Wire Wire Line + 8200 4400 8400 4400 +Wire Wire Line + 8400 4400 8400 5000 +Wire Wire Line + 8400 5300 7450 5300 +Wire Wire Line + 4950 5300 4950 4500 +Wire Wire Line + 4950 4500 5300 4500 +Connection ~ 5300 4500 +Wire Wire Line + 5300 4500 5300 4700 +Wire Wire Line + 7150 4500 7150 4400 +Connection ~ 7150 4400 +Wire Wire Line + 7150 4400 7900 4400 +Wire Wire Line + 7150 4800 7150 5300 +Connection ~ 7150 5300 +Wire Wire Line + 7150 5300 4950 5300 +Wire Wire Line + 2750 4250 2750 3600 +Wire Wire Line + 2750 3600 3500 3600 +Wire Wire Line + 4100 3600 4250 3600 +Wire Wire Line + 5900 3600 5900 4300 +Connection ~ 5900 4300 +Wire Wire Line + 5900 4300 5650 4300 +Wire Wire Line + 3500 3600 3500 3950 +Wire Wire Line + 3500 3950 3800 3950 +Connection ~ 3500 3600 +Wire Wire Line + 3500 3600 3800 3600 +Wire Wire Line + 4100 3950 4250 3950 +Wire Wire Line + 4250 3950 4250 3600 +Connection ~ 4250 3600 +Wire Wire Line + 4250 3600 5900 3600 +Wire Wire Line + 2750 4850 2750 5250 +Wire Wire Line + 2750 5250 4200 5250 +Wire Wire Line + 4500 5250 4500 5650 +Wire Wire Line + 4500 5650 5900 5650 +Wire Wire Line + 5900 5650 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5900 4700 6150 4700 +Text GLabel 9050 4300 0 50 Output ~ 0 +out +Wire Wire Line + 9050 4300 9800 4300 +Wire Wire Line + 9800 4300 9800 4150 +Wire Wire Line + 9800 4150 8400 4150 +Wire Wire Line + 8400 4150 8400 4400 +Connection ~ 8400 4400 +Text GLabel 2500 3350 0 50 Input ~ 0 +ip +Wire Wire Line + 2500 3350 2750 3350 +Wire Wire Line + 2750 3350 2750 3600 +Connection ~ 2750 3600 +$Comp +L power:GND #PWR0101 +U 1 1 5B0D3840 +P 7450 5550 +F 0 "#PWR0101" H 7450 5300 50 0001 C CNN +F 1 "GND" H 7455 5377 50 0000 C CNN +F 2 "" H 7450 5550 50 0001 C CNN +F 3 "" H 7450 5550 50 0001 C CNN + 1 7450 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 5550 7450 5300 +Connection ~ 7450 5300 +Wire Wire Line + 7450 5300 7150 5300 +$Comp +L Device:D_Zener D5 +U 1 1 5B0D4B1F +P 8400 5150 +F 0 "D5" V 8354 5229 50 0000 L CNN +F 1 "D_Zener" V 8445 5229 50 0000 L CNN +F 2 "" H 8400 5150 50 0001 C CNN +F 3 "~" H 8400 5150 50 0001 C CNN +F 4 "D" H 8400 5150 50 0001 C CNN "Spice_Primitive" +F 5 "D1N750" H 8400 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8400 5150 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/Design_Of_Binary_Phase_Shift_Keying_(bpsk)_Modulator_&_Demodulator_Using_Esim_By_Prof_Raghu_K/Design_Of_BPSK_by_Raghu/BPSK/ZenerD1N750.lib" H 8400 5150 50 0001 C CNN "Spice_Lib_File" + 1 8400 5150 + 0 1 1 0 +$EndComp +Text GLabel 7050 4050 0 50 Output ~ 0 +vd +Wire Wire Line + 7050 4050 7550 4050 +Wire Wire Line + 7550 4050 7550 3850 +Wire Wire Line + 7550 3850 6750 3850 +Wire Wire Line + 6750 3850 6750 4400 +Connection ~ 6750 4400 +Wire Wire Line + 6450 4550 6450 4700 +$Comp +L rectifier_schlib:D D1 +U 1 1 5B30D294 +P 5500 4300 +F 0 "D1" H 5500 4515 50 0000 C CNN +F 1 "D" H 5500 4424 50 0000 C CNN +F 2 "" H 5500 4300 50 0000 C CNN +F 3 "" H 5500 4300 50 0000 C CNN +F 4 "D" H 5500 4300 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 5500 4300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 4300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5500 4300 50 0001 C CNN "Spice_Node_Sequence" + 1 5500 4300 + 1 0 0 -1 +$EndComp +$Comp +L rectifier_schlib:D D3 +U 1 1 5B30D899 +P 6300 4300 +F 0 "D3" H 6300 4515 50 0000 C CNN +F 1 "D" H 6300 4424 50 0000 C CNN +F 2 "" H 6300 4300 50 0000 C CNN +F 3 "" H 6300 4300 50 0000 C CNN +F 4 "D" H 6300 4300 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 6300 4300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6300 4300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 6300 4300 50 0001 C CNN "Spice_Node_Sequence" + 1 6300 4300 + 1 0 0 -1 +$EndComp +$Comp +L rectifier_schlib:D D4 +U 1 1 5B30D908 +P 6300 4700 +F 0 "D4" H 6300 4915 50 0000 C CNN +F 1 "D" H 6300 4824 50 0000 C CNN +F 2 "" H 6300 4700 50 0000 C CNN +F 3 "" H 6300 4700 50 0000 C CNN +F 4 "D" H 6300 4700 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 6300 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 6300 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 6300 4700 50 0001 C CNN "Spice_Node_Sequence" + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L rectifier_schlib:D D2 +U 1 1 5B30D95C +P 5500 4700 +F 0 "D2" H 5500 4915 50 0000 C CNN +F 1 "D" H 5500 4824 50 0000 C CNN +F 2 "" H 5500 4700 50 0000 C CNN +F 3 "" H 5500 4700 50 0000 C CNN +F 4 "D" H 5500 4700 50 0001 C CNN "Spice_Primitive" +F 5 "D" H 5500 4700 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 4700 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "2 1" H 5500 4700 50 0001 C CNN "Spice_Node_Sequence" + 1 5500 4700 + 1 0 0 -1 +$EndComp +Text Notes 8450 5800 0 50 ~ 0 +.tran .25m 30m +$EndSCHEMATC diff --git a/analog circuits/ac to dc converter/sym-lib-table b/analog circuits/ac to dc converter/sym-lib-table new file mode 100644 index 0000000..efed22d --- /dev/null +++ b/analog circuits/ac to dc converter/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name rectifier_schlib)(type Legacy)(uri /home/akshay/kicad-source-mirror-master/demos/simulation/rectifier/rectifier_schlib.lib)(options "")(descr "")) +) |