diff options
| author | fahimkhan | 2016-08-24 15:33:26 +0530 |
|---|---|---|
| committer | fahimkhan | 2016-08-24 15:33:26 +0530 |
| commit | c634e048b6192d18eb3badda9c4c0c219dcc4ffb (patch) | |
| tree | d63f1a1a242531449c4e071b944ce9c94ace356a | |
| parent | ff95c8d76ed5a492fd3911fd86484cd82849ee26 (diff) | |
| download | Online-NgSpice-Simulator-c634e048b6192d18eb3badda9c4c0c219dcc4ffb.tar.gz Online-NgSpice-Simulator-c634e048b6192d18eb3badda9c4c0c219dcc4ffb.tar.bz2 Online-NgSpice-Simulator-c634e048b6192d18eb3badda9c4c0c219dcc4ffb.zip | |
Added Ngspice Netlist Example
32 files changed, 1096 insertions, 0 deletions
diff --git a/ngSpice-netlist-example/BJTAmplifier.cir.out b/ngSpice-netlist-example/BJTAmplifier.cir.out new file mode 100644 index 0000000..66dde49 --- /dev/null +++ b/ngSpice-netlist-example/BJTAmplifier.cir.out @@ -0,0 +1,30 @@ + +* Author: FOSSEE +* Date: + +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) +v1 net-_r2-pad1_ gnd dc 10 +r1 net-_c1-pad1_ in 50 +r2 net-_r2-pad1_ net-_c1-pad2_ 200k +c1 net-_c1-pad1_ net-_c1-pad2_ 40u +r3 net-_c1-pad2_ gnd 50k +r6 out gnd 1k +c2 gnd net-_c2-pad2_ 100u +c3 out net-_c3-pad2_ 40u +r5 net-_r2-pad1_ net-_c3-pad2_ 2k +r4 net-_c2-pad2_ gnd 1.5k +q1 net-_c3-pad2_ net-_c1-pad2_ net-_c2-pad2_ Q2N2222 +* u1 in plot_v1 +* u2 out plot_v1 +v2 in gnd sine(0 10m 1k 0 0) +.tran 10e-06 10e-03 0e-03 + +* Control Statements +.control +run +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/BJTCBConfig.cir.out b/ngSpice-netlist-example/BJTCBConfig.cir.out new file mode 100644 index 0000000..f184ee2 --- /dev/null +++ b/ngSpice-netlist-example/BJTCBConfig.cir.out @@ -0,0 +1,26 @@ + +* Author: FOSSEE +* Date: + +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) +q1 net-_q1-pad1_ gnd net-_q1-pad3_ Q2N2222 +v1 vcb gnd dc 12 +r1 net-_r1-pad1_ net-_q1-pad1_ 1k +r2 net-_q1-pad3_ ie 1k +* u_ic1 vcb net-_r1-pad1_ plot_i2 +i1 ie gnd dc 20m +v_u_ic1 vcb net-_r1-pad1_ 0 +.dc v1 -1e-00 5e-00 0.02e-00 i1 -1e-03 5e-03 1e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot i(v_u_ic1) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/BJTCEConfig.cir.out b/ngSpice-netlist-example/BJTCEConfig.cir.out new file mode 100644 index 0000000..289dff4 --- /dev/null +++ b/ngSpice-netlist-example/BJTCEConfig.cir.out @@ -0,0 +1,26 @@ + +* Author: FOSSEE +* Date: + +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) +q1 net-_q1-pad1_ net-_q1-pad2_ gnd Q2N2222 +v1 vce gnd dc 0 +r1 net-_r1-pad1_ net-_q1-pad1_ 1k +r2 net-_q1-pad2_ ib 1k +* u_ic1 vce net-_r1-pad1_ plot_i2 +i1 ib gnd dc 20m +v_u_ic1 vce net-_r1-pad1_ 0 +.dc v1 0e-00 5e-00 0.05e-00 i1 0e-03 5e-03 1e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot i(v_u_ic1) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/BJTFreqResponse.cir.out b/ngSpice-netlist-example/BJTFreqResponse.cir.out new file mode 100644 index 0000000..30f2282 --- /dev/null +++ b/ngSpice-netlist-example/BJTFreqResponse.cir.out @@ -0,0 +1,36 @@ + +* Author: FOSSEE +* Date: + +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) +v1 net-_r2-pad1_ gnd dc 10 +v2 in gnd ac 0.5 0 +c1 net-_c1-pad1_ net-_c1-pad2_ 40u +c2 gnd net-_c2-pad2_ 100u +c3 out net-_c3-pad2_ 40u +q1 net-_c3-pad2_ net-_c1-pad2_ net-_c2-pad2_ Q2N2222 +r3 net-_c1-pad2_ gnd 50k +r4 net-_c2-pad2_ gnd 1.5k +r6 out gnd 1k +r5 net-_r2-pad1_ net-_c3-pad2_ 2k +r2 net-_r2-pad1_ net-_c1-pad2_ 200k +r1 net-_c1-pad1_ in 50 +* u3 out plot_log +* u2 out plot_phase +* u1 in plot_v1 +.ac dec 100 10Hz 100Meg + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot log(out) +plot phase(out) +plot v(in) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/BridgeRectifier.cir.out b/ngSpice-netlist-example/BridgeRectifier.cir.out new file mode 100644 index 0000000..b08356a --- /dev/null +++ b/ngSpice-netlist-example/BridgeRectifier.cir.out @@ -0,0 +1,24 @@ + +* Author: FOSSEE +* Date: + +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) +v1 in1 in2 sine(0 5 50 0 0) +d1 in1 out 1N4148 +d3 in2 out 1N4148 +d2 gnd in1 1N4148 +d4 gnd in2 1N4148 +r1 out gnd 1k +* u2 out plot_v1 +* u1 in1 in2 plot_v2 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out) +plot v(in1,in2) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/CMOSInverter.cir.out b/ngSpice-netlist-example/CMOSInverter.cir.out new file mode 100644 index 0000000..6e67be7 --- /dev/null +++ b/ngSpice-netlist-example/CMOSInverter.cir.out @@ -0,0 +1,47 @@ + +* Author: FOSSEE +* Date: + +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 ++ MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) +v2 vcc gnd 5 +m1 out in gnd gnd CMOSN W=100u L=100u M=1 +m2 out in vcc vcc CMOSP W=100u L=100u M=1 +* u1 in plot_v1 +* u2 out plot_v1 +c1 out gnd 1u +v1 in gnd pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/Clamper.cir.out b/ngSpice-netlist-example/Clamper.cir.out new file mode 100644 index 0000000..1b6cc29 --- /dev/null +++ b/ngSpice-netlist-example/Clamper.cir.out @@ -0,0 +1,29 @@ + +* Author: FOSSEE +* Date: + +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) +v1 in_neg gnd sine(0 5 50 0 0) +c1 out_neg in_neg 1n +d1 out_neg gnd 1N4148 +v2 in_pos gnd sine(0 5 50 0 0) +c2 out_pos in_pos 1n +d2 gnd out_pos 1N4148 +* u1 in_neg plot_v1 +* u2 out_neg plot_v1 +* u3 in_pos plot_v1 +* u4 out_pos plot_v1 +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in_neg) +plot v(out_neg) +plot v(in_pos) +plot v(out_pos) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/Clipper.cir.out b/ngSpice-netlist-example/Clipper.cir.out new file mode 100644 index 0000000..3188642 --- /dev/null +++ b/ngSpice-netlist-example/Clipper.cir.out @@ -0,0 +1,23 @@ + +* Author: FOSSEE +* Date: + +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) +v1 in gnd sine(0 5 50 0 0) +d1 gnd out 1N4148 +d2 out gnd 1N4148 +r1 in out 1k +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/DiacTriac.cir.out b/ngSpice-netlist-example/DiacTriac.cir.out new file mode 100644 index 0000000..f964ea9 --- /dev/null +++ b/ngSpice-netlist-example/DiacTriac.cir.out @@ -0,0 +1,85 @@ + +* Author: FOSSEE +* Date: + +.subckt triac 8 11 10 +* /opt/esim/src/subcircuitlibrary/triac/triac.cir +.model PowerDiode D( ++ Vj=.75 ++ Cjo=175p ++ Rs=.25 ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3) +* f3 +v3 7 2 dc 0 +* f2 +v2 6 3 dc 0 +c1 8 9 10u +* f1 +v1 10 4 dc 0 +* u1 9 11 6 aswitch +* u2 9 2 11 aswitch +r1 8 9 1 +d1 5 8 PowerDiode +d2 1 7 PowerDiode +Vf3 1 8 0 +f3 8 9 Vf3 10 +Vf2 3 5 0 +f2 8 9 Vf2 10 +Vf1 4 8 0 +f1 8 9 Vf1 100 +a1 9 (11 6) u1 +a2 9 (2 11) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) + +* Control Statements + +.ends triac +.subckt diac 1 2 +* /opt/esim/src/subcircuitlibrary/diac/diac.cir +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 (1 2) u1 +a2 1 (1 2) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) + +* Control Statements + +.ends diac +c2 net-_c2-pad1_ gnd 0.1u +c1 net-_c1-pad1_ gnd 0.1u +r3 net-_c1-pad1_ net-_c2-pad1_ 250 +r2 in net-_c1-pad1_ 10k +r1 in out 100 +v1 in gnd sine(0 100 100 0 0) +x2 gnd out net-_x1-pad2_ triac +x1 net-_c2-pad1_ net-_x1-pad2_ diac +* u1 in plot_v1 +* u2 out plot_v1 +* u3 in out plot_v2 +.tran 20e-06 20e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +plot v(in,out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/Differentiator.cir.out b/ngSpice-netlist-example/Differentiator.cir.out new file mode 100644 index 0000000..e6b364d --- /dev/null +++ b/ngSpice-netlist-example/Differentiator.cir.out @@ -0,0 +1,35 @@ + +* Author: FOSSEE +* Date: + +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741 +x1 net-_r2-pad1_ net-_c1-pad2_ out ua741 +r3 net-_c1-pad2_ out 10k +r1 in net-_c1-pad1_ 100k +r2 net-_r2-pad1_ gnd 1k +r4 out gnd 1k +c1 net-_c1-pad1_ net-_c1-pad2_ 20n +v1 in gnd pwl(0m 0 0.5m 5 25m 5 25.5m -5 50m -5 50.5m 5 75m 5 75.5m -5 100m -5) +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/DiodeChar.cir.out b/ngSpice-netlist-example/DiodeChar.cir.out new file mode 100644 index 0000000..4f37a3c --- /dev/null +++ b/ngSpice-netlist-example/DiodeChar.cir.out @@ -0,0 +1,22 @@ + +* Author: FOSSEE +* Date: + +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) +v1 in gnd dc 1 +d1 in out 1N4148 +r1 net-_r1-pad1_ gnd 1k +* u1 out net-_r1-pad1_ plot_i2 +v_u1 out net-_r1-pad1_ 0 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.dc v1 0e-00 1e-00 0.01e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot i(v_u1) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/FETAmplifier.cir.out b/ngSpice-netlist-example/FETAmplifier.cir.out new file mode 100644 index 0000000..a349847 --- /dev/null +++ b/ngSpice-netlist-example/FETAmplifier.cir.out @@ -0,0 +1,29 @@ + +* Author: FOSSEE +* Date: + +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) +c1 net-_c1-pad1_ in 1u +c6 net-_c6-pad1_ gnd 0.1u +v2 net-_r3-pad1_ gnd dc 10 +j1 out net-_c1-pad1_ net-_c6-pad1_ J2N3819 +r3 net-_r3-pad1_ out 3k +r2 gnd net-_c1-pad1_ 1meg +r4 gnd net-_c6-pad1_ 470 +v1 in gnd sine(0 10m 1k 0 0) +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-06 10e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/FETChar.cir.out b/ngSpice-netlist-example/FETChar.cir.out new file mode 100644 index 0000000..7f494d0 --- /dev/null +++ b/ngSpice-netlist-example/FETChar.cir.out @@ -0,0 +1,23 @@ + +* Author: FOSSEE +* Date: + +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) +j1 id net-_j1-pad2_ gnd J2N3819 +vds1 net-_u_id1-pad1_ gnd dc 10 +vgs1 net-_j1-pad2_ gnd dc 0 +* u_id1 net-_u_id1-pad1_ id plot_i2 +v_u_id1 net-_u_id1-pad1_ id 0 +.dc vds1 0e-00 50e-00 10e-00 vgs1 0e-03 5e-03 1e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot i(v_u_id1) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/FETFreqResponse.cir.out b/ngSpice-netlist-example/FETFreqResponse.cir.out new file mode 100644 index 0000000..b630a17 --- /dev/null +++ b/ngSpice-netlist-example/FETFreqResponse.cir.out @@ -0,0 +1,33 @@ + +* Author: FOSSEE +* Date: + +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) +c1 net-_c1-pad1_ in 1u +c6 net-_c6-pad1_ gnd 0.1u +v2 net-_r3-pad1_ gnd dc 20 +j1 out net-_c1-pad1_ net-_c6-pad1_ J2N3819 +r3 net-_r3-pad1_ out 3k +r2 gnd net-_c1-pad1_ 1meg +r4 gnd net-_c6-pad1_ 470 +* u1 in plot_v1 +v1 in gnd ac 0.1m 0 +* u3 out plot_log +* u2 out plot_phase +* u4 out plot_db +.ac dec 100 10KHz 100Meg + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot log(out) +plot phase(out) +plot db(out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/FWRUsingSCR.cir.out b/ngSpice-netlist-example/FWRUsingSCR.cir.out new file mode 100644 index 0000000..63ca268 --- /dev/null +++ b/ngSpice-netlist-example/FWRUsingSCR.cir.out @@ -0,0 +1,76 @@ + +* Author: FOSSEE +* Date: + +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.model PowerDiode D( ++ Vj=.75 ++ Cjo=175p ++ Rs=.25 ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3) +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr +.model PowerDiode D( ++ Vj=.75 ++ Cjo=175p ++ Rs=.25 ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3) +x1 gnd pulse out2 scr +v1 in1 in2 sine(0 200 100 0 0) +v2 pulse gnd pulse(0 5 2m 0 0 1m 5m) +d1 in1 out1 PowerDiode +d3 in2 out1 PowerDiode +d2 gnd in1 PowerDiode +d4 gnd in2 PowerDiode +r1 out1 out2 100 +* u1 in1 in2 plot_v2 +* u3 pulse plot_v1 +* u2 out1 out2 plot_v2 +.tran 20e-06 20e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in1,in2) +plot v(pulse) +plot v(out1,out2) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/FullAdder.cir.out b/ngSpice-netlist-example/FullAdder.cir.out new file mode 100644 index 0000000..e1dfb92 --- /dev/null +++ b/ngSpice-netlist-example/FullAdder.cir.out @@ -0,0 +1,61 @@ + +* Author: FOSSEE +* Date: + +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder +x1 net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ net-_u7-pad1_ net-_u7-pad2_ full_adder +v1 in1 gnd dc 5 +v2 in2 gnd dc 0 +v3 cin gnd dc 5 +r1 sum gnd 1k +r2 cout gnd 1k +* u2 in1 plot_v1 +* u1 in2 plot_v1 +* u3 cin plot_v1 +* u4 sum plot_v1 +* u5 cout plot_v1 +* u6 in1 in2 cin net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ adc_bridge_3 +* u7 net-_u7-pad1_ net-_u7-pad2_ sum cout dac_bridge_2 +a1 [in1 in2 cin ] [net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ ] u6 +a2 [net-_u7-pad1_ net-_u7-pad2_ ] [sum cout ] u7 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u6 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-00 100e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in1) +plot v(in2) +plot v(cin) +plot v(sum) +plot v(cout) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/HWRusingSCR.cir.out b/ngSpice-netlist-example/HWRusingSCR.cir.out new file mode 100644 index 0000000..b151daa --- /dev/null +++ b/ngSpice-netlist-example/HWRusingSCR.cir.out @@ -0,0 +1,59 @@ + +* Author: FOSSEE +* Date: + +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.model PowerDiode D( ++ Vj=.75 ++ Cjo=175p ++ Rs=.25 ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3) +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr +v1 in gnd sine(0 100 50 0 0) +v2 pulse gnd pulse(0 5 4m 0 0 1m 20m) +r1 in a 100 +* u2 in a plot_v2 +* u1 in plot_v1 +* u3 pulse plot_v1 +x1 gnd pulse a scr +.tran 40e-06 40e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in,a) +plot v(in) +plot v(pulse) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/HalfAdder.cir.out b/ngSpice-netlist-example/HalfAdder.cir.out new file mode 100644 index 0000000..95d831c --- /dev/null +++ b/ngSpice-netlist-example/HalfAdder.cir.out @@ -0,0 +1,47 @@ + +* Author: FOSSEE +* Date: + +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder +x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder +* u1 in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2 +* u2 net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2 +v1 in1 gnd dc 5 +v2 in2 gnd dc 0 +r1 sum gnd 1k +r2 cout gnd 1k +* u3 in1 plot_v1 +* u4 in2 plot_v1 +* u5 sum plot_v1 +* u6 cout plot_v1 +a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2 +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in1) +plot v(in2) +plot v(sum) +plot v(cout) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/HalfwaveRectifier.cir.out b/ngSpice-netlist-example/HalfwaveRectifier.cir.out new file mode 100644 index 0000000..9a3ffde --- /dev/null +++ b/ngSpice-netlist-example/HalfwaveRectifier.cir.out @@ -0,0 +1,22 @@ + +* Author: FOSSEE +* Date: + +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) +d1 in out 1N4148 +r1 out gnd 1k +v1 in gnd sine(0 20 50 0 0) +* u2 in plot_v1 +* u3 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/HighPassFilter.cir.out b/ngSpice-netlist-example/HighPassFilter.cir.out new file mode 100644 index 0000000..5e82486 --- /dev/null +++ b/ngSpice-netlist-example/HighPassFilter.cir.out @@ -0,0 +1,22 @@ + +* Author: FOSSEE +* Date: + +r1 out gnd 1k +c1 out in 10u +v1 in gnd ac 10 0 +* u1 in plot_v1 +* u3 out plot_v1 +* u2 out plot_log +.ac dec 20 1Hz 1Meg + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +plot log(out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/Integrator.cir.out b/ngSpice-netlist-example/Integrator.cir.out new file mode 100644 index 0000000..1316e8c --- /dev/null +++ b/ngSpice-netlist-example/Integrator.cir.out @@ -0,0 +1,35 @@ + +* Author: FOSSEE +* Date: + +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741 +x1 net-_r2-pad1_ net-_c1-pad2_ out ua741 +r1 in net-_c1-pad2_ 10k +r2 net-_r2-pad1_ gnd 1k +r3 out gnd 1k +c1 out net-_c1-pad2_ 100n +r4 net-_c1-pad2_ out 100k +v1 in gnd pwl(0m 0 0.5m 5 25m 5 25.5m -5 50m -5 50.5m 5 75m 5 75.5m -5 100m -5) +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/InvertingAmplifier.cir.out b/ngSpice-netlist-example/InvertingAmplifier.cir.out new file mode 100644 index 0000000..a825b4b --- /dev/null +++ b/ngSpice-netlist-example/InvertingAmplifier.cir.out @@ -0,0 +1,34 @@ + +* Author: FOSSEE +* Date: + +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741 +x1 net-_r4-pad1_ net-_r1-pad2_ out ua741 +r1 in net-_r1-pad2_ 1k +r2 net-_r1-pad2_ out 5k +v1 in gnd sine(0 2 50 0 0) +r3 out gnd 1k +r4 net-_r4-pad1_ gnd 1k +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end
\ No newline at end of file diff --git a/ngSpice-netlist-example/JKFlipflop.cir.out b/ngSpice-netlist-example/JKFlipflop.cir.out new file mode 100644 index 0000000..3cc969c --- /dev/null +++ b/ngSpice-netlist-example/JKFlipflop.cir.out @@ -0,0 +1,51 @@ + +* Author: FOSSEE +* Date: + +v1 j gnd dc 5 +v3 k gnd dc 0 +r1 out gnd 1k +r2 nout gnd 1k +* u2 j plot_v1 +* u1 clk plot_v1 +* u3 k plot_v1 +* u4 out plot_v1 +* u5 nout plot_v1 +* u6 j clk k net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ adc_bridge_3 +* u7 net-_u7-pad1_ net-_u7-pad2_ out nout dac_bridge_2 +* u9 net-_u6-pad4_ net-_u6-pad6_ net-_u6-pad5_ net-_u8-pad2_ net-_u10-pad2_ net-_u7-pad1_ net-_u7-pad2_ d_jkff +* u8 net-_u8-pad1_ net-_u8-pad2_ adc_bridge_1 +* u10 net-_u10-pad1_ net-_u10-pad2_ adc_bridge_1 +v4 net-_u8-pad1_ gnd 0 +v5 net-_u10-pad1_ gnd 0 +v2 clk gnd pulse(0 5 1m 1m 1m 20 40) +a1 [j clk k ] [net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ ] u6 +a2 [net-_u7-pad1_ net-_u7-pad2_ ] [out nout ] u7 +a3 net-_u6-pad4_ net-_u6-pad6_ net-_u6-pad5_ net-_u8-pad2_ net-_u10-pad2_ net-_u7-pad1_ net-_u7-pad2_ u9 +a4 [net-_u8-pad1_ ] [net-_u8-pad2_ ] u8 +a5 [net-_u10-pad1_ ] [net-_u10-pad2_ ] u10 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u6 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u9 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u8 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u10 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +.tran 10e-00 100e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(j) +plot v(clk) +plot v(k) +plot v(out) +plot v(nout) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/LowPassFilter.cir.out b/ngSpice-netlist-example/LowPassFilter.cir.out new file mode 100644 index 0000000..38808ee --- /dev/null +++ b/ngSpice-netlist-example/LowPassFilter.cir.out @@ -0,0 +1,23 @@ + +* Author: FOSSEE +* Date: + +r1 in out 1k +c1 out gnd 10u +v1 in gnd ac 10 0 +* u1 in plot_v1 +* u2 out plot_v1 +* u3 out plot_log +.ac dec 20 1Hz 100KHz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +plot log(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/ParallelResonace.cir.out b/ngSpice-netlist-example/ParallelResonace.cir.out new file mode 100644 index 0000000..c28d282 --- /dev/null +++ b/ngSpice-netlist-example/ParallelResonace.cir.out @@ -0,0 +1,23 @@ + +* Author: FOSSEE +* Date: + +r1 out gnd 100 +l1 out gnd 100m +c1 gnd out 10u +v1 in gnd ac 1 0 +r2 out in 1000 +* u1 in plot_v1 +* u3 out plot_v1 +.ac lin 20 1Hz 700Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/RC.cir.out b/ngSpice-netlist-example/RC.cir.out new file mode 100644 index 0000000..d085b66 --- /dev/null +++ b/ngSpice-netlist-example/RC.cir.out @@ -0,0 +1,21 @@ + +* Author: FOSSEE +* Date: + +r1 in out 1k +c1 out gnd 10u +v1 in gnd pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0) +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/RL.cir.out b/ngSpice-netlist-example/RL.cir.out new file mode 100644 index 0000000..f74f09d --- /dev/null +++ b/ngSpice-netlist-example/RL.cir.out @@ -0,0 +1,21 @@ + +* Author: FOSSEE +* Date: + +r1 in out 10 +l1 out gnd 100m +v1 in gnd pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0) +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/RLC.cir.out b/ngSpice-netlist-example/RLC.cir.out new file mode 100644 index 0000000..ba20476 --- /dev/null +++ b/ngSpice-netlist-example/RLC.cir.out @@ -0,0 +1,22 @@ + +* Author: FOSSEE +* Date: + +r1 in net-_l1-pad1_ 1k +l1 net-_l1-pad1_ out 2 +c1 out gnd 0.5u +v1 in gnd pwl(0m 0 0.5m 5) +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/SeriesResonance.cir.out b/ngSpice-netlist-example/SeriesResonance.cir.out new file mode 100644 index 0000000..37c0f3b --- /dev/null +++ b/ngSpice-netlist-example/SeriesResonance.cir.out @@ -0,0 +1,22 @@ + +* Author: FOSSEE +* Date: + +r1 in net-_c1-pad2_ 1 +l1 out gnd 100m +c1 out net-_c1-pad2_ 10u +v1 in gnd ac 1 0 +* u1 in plot_v1 +* u2 out plot_v1 +.ac lin 20 1Hz 250Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/Transformer.cir.out b/ngSpice-netlist-example/Transformer.cir.out new file mode 100644 index 0000000..b373e58 --- /dev/null +++ b/ngSpice-netlist-example/Transformer.cir.out @@ -0,0 +1,31 @@ + +* Author: FOSSEE +* Date: + +v1 net-_r2-pad2_ gnd sine(0 10 50 0 0) +r1 out gnd 1k +r2 in net-_r2-pad2_ 1k +* u1 in gnd gnd out transfo +* u2 in plot_v1 +* u3 out plot_v1 +a1 (in gnd) (interNode_1 gnd) u1_primary +a2 (out gnd) (interNode_2 gnd) u1_secondary +a3 (interNode_1 interNode_2) u1_iron_core +*primary lcouple +.model u1_primary lcouple (num_turns= 310) +*iron core +.model u1_iron_core core (H_array = [-1000 -500 -375 -250 -188 -125 -63 0 63 125 188 250 375 500 1000] B_array = [-3.13e-3 -2.63e-3 -2.33e-3 -1.93e-3 -1.5e-3 -6.25e-4 -2.5e-4 0 2.5e-4 6.25e-4 1.5e-3 1.93e-3 2.33e-3 2.63e-3 3.13e-3] area = 1 length =0.01) +*secondary lcouple +.model u1_secondary lcouple (num_turns =620) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/ZenerChar.cir.out b/ngSpice-netlist-example/ZenerChar.cir.out new file mode 100644 index 0000000..2809ccf --- /dev/null +++ b/ngSpice-netlist-example/ZenerChar.cir.out @@ -0,0 +1,25 @@ + +* Author: FOSSEE +* Date: + +v1 in gnd dc 10 +r1 in net-_r1-pad2_ 1k +* u2 net-_r1-pad2_ out plot_i2 +* u3 out plot_v1 +* u1 gnd out zener +v_u2 net-_r1-pad2_ out 0 +a1 gnd out u1 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.dc v1 0e-00 8e-00 0.05e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot i(v_u2) +plot v(out) +.endc +.end +
\ No newline at end of file diff --git a/ngSpice-netlist-example/oscillator.cir.out b/ngSpice-netlist-example/oscillator.cir.out new file mode 100644 index 0000000..a807fd3 --- /dev/null +++ b/ngSpice-netlist-example/oscillator.cir.out @@ -0,0 +1,33 @@ + +* Author: FOSSEE +* Date: + +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) +q1 out net-_q1-pad2_ net-_c3-pad1_ Q2N2222 +r5 net-_r2-pad1_ out 8.6k +r2 net-_r2-pad1_ net-_q1-pad2_ 56k +r6 net-_c3-pad1_ gnd 1.5k +r3 net-_q1-pad2_ gnd 8.2k +r1 net-_c1-pad2_ net-_q1-pad2_ 3k +c3 net-_c3-pad1_ gnd 20u +c1 net-_c1-pad1_ net-_c1-pad2_ 1500p +c2 net-_c2-pad1_ net-_c1-pad1_ 1500p +c4 out net-_c2-pad1_ 1500p +r4 net-_c1-pad1_ gnd 3k +r7 net-_c2-pad1_ gnd 3k +v1 net-_r2-pad1_ gnd dc 22 +* u1 out plot_v1 +.tran 100e-06 5e-03 1e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out) +.endc +.end +
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