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* Author: FOSSEE
* Date:
.subckt half_adder 1 4 3 2
* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
* u2 1 4 3 d_xor
* u3 1 4 2 d_and
a1 [1 4 ] 3 u2
a2 [1 4 ] 2 u3
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
* Control Statements
.ends half_adder
x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
* u1 in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
* u2 net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2
v1 in1 gnd dc 5
v2 in2 gnd dc 0
r1 sum gnd 1k
r2 cout gnd 1k
* u3 in1 plot_v1
* u4 in2 plot_v1
* u5 sum plot_v1
* u6 cout plot_v1
a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2
* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
.tran 10e-03 100e-03 0e-03
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot v(in1)
plot v(in2)
plot v(sum)
plot v(cout)
.endc
.end
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