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+
+* Author: FOSSEE
+* Date:
+
+.subckt full_adder 8 7 5 4 1
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015
+.subckt half_adder 1 4 3 2
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+* u2 1 4 3 d_xor
+* u3 1 4 2 d_and
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_adder
+x1 8 7 6 2 half_adder
+x2 5 6 4 3 half_adder
+* u2 3 2 1 d_or
+a1 [3 2 ] 1 u2
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends full_adder
+x1 net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ net-_u7-pad1_ net-_u7-pad2_ full_adder
+v1 in1 gnd dc 5
+v2 in2 gnd dc 0
+v3 cin gnd dc 5
+r1 sum gnd 1k
+r2 cout gnd 1k
+* u2 in1 plot_v1
+* u1 in2 plot_v1
+* u3 cin plot_v1
+* u4 sum plot_v1
+* u5 cout plot_v1
+* u6 in1 in2 cin net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ adc_bridge_3
+* u7 net-_u7-pad1_ net-_u7-pad2_ sum cout dac_bridge_2
+a1 [in1 in2 cin ] [net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ ] u6
+a2 [net-_u7-pad1_ net-_u7-pad2_ ] [sum cout ] u7
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u6 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-00 100e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(in1)
+plot v(in2)
+plot v(cin)
+plot v(sum)
+plot v(cout)
+.endc
+.end \ No newline at end of file