Samples of VHDL code added for testing

1 files changed, 19 insertions, 0 deletions

diff --git a/VHDL/d_ff.vhdl b/VHDL/d_ff.vhdl
new file mode 100644
index 0000000..efc4177
--- /dev/null
+++ b/VHDL/d_ff.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee. std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity d_ff is
+PORT( D: in std_logic_vector(0 downto 0);
+CLOCK: in std_logic_vector(0 downto 0);
+Q: out std_logic_vector(0 downto 0));
+end d_ff;
+ 
+architecture behavioral of d_ff is
+begin
+process(CLOCK)
+begin
+if(CLOCK='1' and CLOCK'EVENT) then
+Q<=D;
+end if;
+end process;
+end behavioral;