From b503d66fcc1e26be28b58cccf888e43f99d35ae2 Mon Sep 17 00:00:00 2001
From: Ambikeshwar
Date: Wed, 25 May 2016 14:20:23 +0530
Subject: Samples of VHDL code added for testing

---
 VHDL/d_ff.vhdl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 VHDL/d_ff.vhdl

(limited to 'VHDL/d_ff.vhdl')

diff --git a/VHDL/d_ff.vhdl b/VHDL/d_ff.vhdl
new file mode 100644
index 0000000..efc4177
--- /dev/null
+++ b/VHDL/d_ff.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee. std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity d_ff is
+PORT( D: in std_logic_vector(0 downto 0);
+CLOCK: in std_logic_vector(0 downto 0);
+Q: out std_logic_vector(0 downto 0));
+end d_ff;
+ 
+architecture behavioral of d_ff is
+begin
+process(CLOCK)
+begin
+if(CLOCK='1' and CLOCK'EVENT) then
+Q<=D;
+end if;
+end process;
+end behavioral;
-- 
cgit